# Patent

## Title
Resource allocation in PON networks via wave-front multiplexing and de-multiplexing

## Abstract

A data communication system comprises a wave-front multiplexer configured to wave-front multiplex first electronic signals into second electronic signals. The data communication system further comprises an electronic-to-optical converter configured to convert a third electronic signal carrying information associated with the second electronic signals into a first optical signal; and an optical transferring module configured to split the first optical signal into second optical signals, wherein each of the second optical signals carries the same data as the first optical signal carries. The data communication system further comprises optical-to-electronic converters configured to convert the second optical signals into fourth electronic signals; and wave-front demultiplexers each configured to wave-front demultiplex one of the fourth electronic signals into fifth electronic signals equivalent to the first electronic signals respectively.

## Background
RELATED APPLICATION
This application is a continuation of application Ser. No. 13/778,168, filed on Feb. 27, 2013, now pending, which claims priority to U.S. provisional application No. 61/604,326, filed on Feb. 28, 2012, which is incorporated herein by reference in its entirety.


BACKGROUND OF THE DISCLOSURE
Field of the Disclosure
The invention relates to resource allocation via wave-front multiplexing and demultiplexing, and particularly to resource allocation in passive optical networks (PON) via wave-front multiplexing and demultiplexing.
Brief Description of the Related Art
Most of the Fiber-to-the-Home deployments in recent years have been based on industry standard technologies such as Gigabit Ethernet Passive Optical Networks (GEPON) and Gigabit PON (GPON). Passive Optical Network (PON) is a point-to multipoint network. A PON consists of optical line terminal at the service provider's central office and many number of optical network units near end users. The goal of PON is to reduce the amount of fiber. There are two standards of the Passive Optical Network available, the GPON and the GEPON.
GPON (Gigabit PON) is the evolution of broadband PON (BPON) standard. The protocols used by GPON are ATM, GEM, and Ethernet. It supports higher rates and has more security.
GEPON or EPON (Ethernet PON) is an IEEE standard that uses Ethernet for sending data packets. In current there are 15 million EPON ports installed. GEPON uses 1 gigabit per second upstream and downstream rates. EPON/GEPON is a fast Ethernet over passive optical networks which are point to multipoint to the premises (FTTP) or fiber to the home (FTTH) architecture in which single optical fiber is used to serve multiple premises or users.
The success of these deployments has led to significant innovation in both system architecture and the components that are used to build these systems, and the next generation of passive optical networks will inevitably be far more advanced than what is typically deployed today.
Traditional PON architectures feature one optical feed shared among 32 or more users. In a GPON or GEPON system all subscribers use a common optical wavelength. They share the fiber infrastructure, which is done through time division multiplexing (TDM). Each of those 32 homes transmits over the same fiber, but the time in which they are allowed to “occupy” the fiber is allocated by the optical line terminal (OLT) at the central office. While the equipment in each home is capable of transmitting at over 1,250 Mbps, it can only do so during its allotted time on the fiber, and therefore it is not uncommon for each subscriber in a legacy PON system to only achieve sustained data rates of around 30 Mbps. This concept of many users sharing a common fiber helps minimizing the fiber infrastructure required in an FTTH deployment.
SUMMARY OF THE DISCLOSURE
This invention relates to methods and architectures for dynamic allocations of time slots or equivalent bandwidths of passive optical networks (PON) via wave-front (WF) multiplexing/demultiplexing techniques to generate multi-dimensional wavefront-multiplexed signals concurrently propagating through the passive optical networks (PON), and thereby bandwidth limits set for subscribers can be broken through. The architectures of the invention support dynamic bandwidth allocations as well as configurable bandwidth allocations. They also support dynamic allocations for power resources as well as configurable allocations for power resources of optical lasers with regards to different signals transmitted to/from various subscribers.
In an embodiment, a data communication system comprises: a first processor configured to receive a first electronic signal and a second electronic signal and output a third electronic signal carrying information associated with said first and second electronic signals and a fourth electronic signal carrying information associated with said first and second electronic signals; a first signal mapping unit at a downstream side of said first processor, wherein said first signal mapping unit is configured to combine said third and fourth electronic signals into a fifth electronic signal; an electronic-to-optical converter at a downstream side of said first signal mapping unit, wherein said electronic-to-optical converter is configured to convert said fifth electronic signal into a first optical signal; an optical transferring module at a downstream side of said electronic-to-optical converter, wherein said optical transferring module is configured to split said first optical signal into a second optical signal and a third optical signal, wherein said first optical signal carries the same data as said second optical signal carries and said third optical signal carries; a first optical-to-electronic converter at a downstream side of said optical transferring module, wherein said first optical-to-electronic converter is configured to convert said second optical signal into a sixth electronic signal; a second optical-to-electronic converter at a downstream side of said optical transferring module, wherein said second optical-to-electronic converter is configured to convert said third optical signal into a seventh electronic signal; a second signal mapping unit at a downstream side of said first optical-to-electronic converter, wherein said second signal mapping unit is configured to allocate said sixth electronic signal into an eighth electronic signal and a ninth electronic signal; a third signal mapping unit at a downstream side of said second optical-to-electronic converter, wherein said third signal mapping unit configured to allocate said seventh electronic signal into a tenth electronic signal and an eleventh electronic signal; a second processor at a downstream side of said second signal mapping unit, wherein said second processor is configured to receive said eighth electronic signal and said ninth electronic signal and output a twelfth electronic signal carrying information associated with said eighth and ninth electronic signals and a thirteenth electronic signal carrying information associated with said eighth and ninth electronic signals, wherein said twelfth electronic signal is substantially equivalent to said first electronic signal, and said thirteenth electronic signal is substantially equivalent to said second electronic signal; and a third processor at a downstream side of said third signal mapping unit, wherein said third processor is configured to receive said tenth electronic signal and said eleventh electronic signal and output a fourteenth electronic signal carrying information associated with said tenth and eleventh electronic signals and a fifteenth electronic signal carrying information associated with said tenth and eleventh electronic signals, wherein said fourteenth electronic signal is substantially equivalent to said first electronic signal, and said fifteenth electronic signal is substantially equivalent to said second electronic signal.
In an embodiment, a data communication system comprises: a first signal mapping unit configured to allocate a first signal into a second signal and a third signal; a controller configured to alter the number of signals, into which said first signal is allocated; a first processor at a downstream side of said first signal mapping unit, wherein said first processor is configured to receive a fourth signal carrying information associated with said second signal and a fifth signal carrying information associated said third signal and output a sixth signal carrying information associated with said fourth and fifth signals and a seventh signal carrying information associated with said fourth and fifth signals; a second processor at a downstream side of said first processor, wherein said second processor is configured to receive an eighth signal carrying information associated with said sixth signal and a ninth signal carrying information associated said seventh signal and output a tenth signal carrying information associated with said eighth and ninth signals and an eleventh signal carrying information associated with said eighth and ninth signals, wherein said tenth signal is substantially equivalent to said fourth signal, and said eleventh signal is substantially equivalent to said fifth signal; and a second signal mapping unit at a downstream side of said second processor, wherein said second signal mapping unit is configured to combine said tenth and eleventh signals into a twelfth signal, wherein said controller is configured to alter the number of signals that are combined into said twelfth signal.
These, as well as other components, steps, features, benefits, and advantages of the present disclosure, will now become clear from a review of the following detailed description of illustrative embodiments, the accompanying drawings, and the claims.



BRIEF DESCRIPTION OF THE DRAWINGS
The drawings disclose illustrative embodiments of the present disclosure. They do not set forth all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Conversely, some embodiments may be practiced without all of the details that are disclosed. When the same reference number or reference indicator appears in different drawings, it may refer to the same or like components or steps.
Aspects of the disclosure may be more fully understood from the following description when read together with the accompanying drawings, which are to be regarded as illustrative in nature, and not as limiting. The drawings are not necessarily to scale, emphasis instead being placed on the principles of the disclosure. In the drawings:
FIG. 1A shows a data communication system including a wave-front multiplexer, a data relaying system and a wave-front demultiplexer according to an embodiment of the present disclosure;
FIG. 1B shows a data communication system including a wave-front multiplexer, a data relaying system, an equalization processor, a wave-front demultiplexer and an optimizer according to another embodiment of the present disclosure;
FIG. 1C shows architecture of a wave-front multiplexer according to an embodiment of the present disclosure;
FIG. 1D shows architecture of a wave-front demultiplexer according to an embodiment of the present disclosure;
FIG. 2A shows a schematic diagram of a passive optical network according to an embodiment of the present disclosure;
FIG. 2B shows a schematic diagram of a passive optical network according to another embodiment of the present disclosure;
FIGS. 3A-3C show schematic diagrams of downstream data flows via a passive optical network PON system according to an embodiment of the present disclosure;
FIGS. 4A-4D show schematic diagrams of upstream data flows via a passive optical network PON system according to an embodiment of the present disclosure.



While certain embodiments are depicted in the drawings, one skilled in the art will appreciate that the embodiments depicted are illustrative and that variations of those shown, as well as other embodiments described herein, may be envisioned and practiced within the scope of the present disclosure.
DETAILED DESCRIPTION OF THE INVENTION
Illustrative embodiments are now described. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for a more effective presentation. Conversely, some embodiments may be practiced without all of the details that are disclosed.
Before describing embodiments of the present invention, a definition has been included for these various terms. These definitions are provided to assist in teaching a general understanding of the present invention.
Wave-Front Multiplexer (WF Muxer):
The term “wave-front multiplexer” is used herein to denote a specialized signal processing transform from a spatial-domain representation of signals to a wavefront-domain representation of the signals. A wave-front multiplexer performs an orthogonal functional transformation to multiply an orthogonal matrix, such as Fourier matrix, Butler matrix or Hadamard matrix, by an input matrix representing multiple input signals so as to obtain an output matrix representing multiple output signals. The orthogonal functional transformation can be, but not limited to, Fourier transformation, discrete Fourier transformation (DFT), fast Fourier transformation (FFT), Hartley transformation, Hadamard transformation, or any other Fourier-related transformation. Each output signal output from the wave-front multiplexer is a linear combination, i.e. weighted sum, of all input signals input into the wave-front multiplexer. As a result, each input signal into the wave-front multiplexer appears in all output signals. The weightings of one input signal among all the output signals feature a unique distribution which is defined as a wavefront multiplexing vector (WFMV). When the wave-front multiplexer features H inputs receiving H input signals and H outputs outputting H output signals, there are H wavefront multiplexing vectors (WFMVs) associated with the H inputs of the H-to-H wave-front multiplexer, and each of the H wavefront multiplexing vectors is an H-dimensional vector, where H is an integer equal to or greater than two, four, eight, sixteen, thirty-two, sixty-four or two-hundred-and-fifty-six. The H wavefront multiplexing vectors are mutually orthogonal to one another. Each of the H output signals carries a linear combination of all the H input signals, and the H input signals appearing in each of the H output signals can be completely independent from one another. The above-mentioned transform performed by the wave-front multiplexer is called herein a wave-front multiplexing transform or transformation, which can be applied to the following embodiments.
The wave-front multiplexing transform may be, but not limited to, implemented at base band in a digital format or by analog devices, wherein the devices may be selected from a group consisting of a Butler Matrix, a Fourier transform, and a Hartley transform.
The wave-front multiplexer can be, but not limited to, embedded in a processor. The wave-front multiplexer can be implemented by hardware which performing the above wave-front multiplexing transformation, such as FFT chip, Butler matrix, or a device performing a specified transformation of an orthogonal matrix such as Fourier matrix or Hadamard matrix. Alternatively, the function of the wave-front multiplexer can be realized by software installed in and performed by the processor, wherein the software can perform the above wave-front multiplexing transform. Alternatively, the wave-front multiplexer can be or include, but not limited to, a field programmable gate array (FPGA) or a digital signal processor (DSP).
The wave-front multiplexer can be layout with circuits for cells of basic functions recorded in a cell library such that any company of interest can implement the circuit layout in an integrated-circuit chip, a system-on chip (SOC) or an integrated-circuit chip package.
The wave-front multiplexer (WF muxer) features multiple-input and multiple-output (MIMO) processing that receives multiple input signals passing in parallel through multiple parallel input ports of the WF muxer and outputs multiple output signals passing in parallel through multiple parallel output ports of the WF muxer. The total number of the parallel input ports of the WF muxer may be equal to the total number of the parallel output ports of the WF muxer, may be equal to the number of rows or columns of an orthogonal matrix characterizing the WF muxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six. The total number of the input signals into the WF muxer may be equal to or less than the total number of the parallel input ports of the WF muxer, may be equal to or less than the number of rows or columns of the orthogonal matrix characterizing the WF muxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six. The total number of the output signals output form the WF muxer may be equal to the total number of the parallel output ports of the WF muxer, may be equal to the number of rows or columns of the orthogonal matrix characterizing the WF muxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six.
Wave-Front Demultiplexer (WF Demuxer):
The term “Wave-front demultiplexer” is used herein to denote a specialized signal processing transform from a wavefront-domain representation of signals to a spatial-domain representation of the signals. A wave-front demultiplexer performs a complementary transformation to a wave-front multiplexer and extracts multiple signals each corresponding to one of the original signals input to the wave-front multiplexer.
The wave-front demultiplexer performs an inverse orthogonal functional transformation to multiply an inverse orthogonal matrix, such as inverse Fourier matrix, Butler matrix or Hadamard matrix, by an input matrix representing multiple input signals so as to obtain an output matrix representing multiple output signals. The inverse transformation performed by the wave-front demultiplexer is the inverse of the transformation performed by a corresponding or complementary wave-front multiplexer. Many orthogonal matrixes, such as Hadamard matrix, have inverses which equal to the orthogonal matrixes themselves. The inverse orthogonal functional transformation can be, but not limited to, inverse Fourier transformation, inverse discrete Fourier transformation, inverse fast Fourier transformation (IFFT), Hadamard transformation, inverse Hartley transformation, any other inverse Fourier-related transformation, or any transformation of an orthogonal matrix (such as inverse Fourier matrix, Butler matrix, or Hadamard matrix).
Hadamard transforms featuring the inverse transforms equal to themselves may be used for the wave-front multiplexing and demultiplexing transforms. In the present disclosure, the wave-front multiplexing and demultiplexing transforms can be, but not limited to, characterized by same matrixes.
Alternatively, the wave-front multiplexing transform may have an inverse not equal to itself. The wave-front multiplexing transform is not equal to the corresponding or complementary wave-front demultiplexing transform. For example, the wave-front multiplexing and demultiplexing transforms can be, but not limited to, a fast Fourier transform (FFT) and its corresponding or complementary inverse fast Fourier transforms (IFFT).
Each output signal output from the wave-front demultiplexer is a linear combination, i.e. weighted sum, of all input signals input into the wave-front demultiplexer. As a result, each input signal into the wave-front demultiplexer appears in all output signals. The weightings of one input signal among all the output signals feature a unique distribution which is defined as a wavefront demultiplexing vector (WFDV). When the wave-front demultiplexer features I inputs receiving I input signals and I outputs outputting I output signals, there are I wavefront demultiplexing vectors (WFDVs) associated with the I inputs of the I-to-I wave-front demultiplexer, and each of the I wavefront demultiplexing vectors is an I-dimensional vector, where I is an integer equal to or greater than two, four, eight, sixteen, thirty-two, sixty-four or two-hundred-and-fifty-six. The I wavefront demultiplexing vectors are mutually orthogonal to one another. Each of the I output signals carries a linear combination of all the I input signals, and the I input signals appearing in each of the I output signals can be completely independent from one another.
Therefore, the wave-front demultiplexer extracts coherently combined signals from input signals input to the wave-front demultiplexer and outputs the coherently combined signals, such that each of the coherently combined signals output from the wave-front demultiplexer can be correspondent to or associated with one of the input signals input into the wave-front multiplexer. The above-mentioned transform performed by the wave-front demultiplexer is called herein a wave-front demultiplexing transform or transformation, which can be applied to the following embodiments.
The wave-front demultiplexer can be, but not limited to, embedded in a processor. The wave-front demultiplexer can be implemented by hardware which performing the above wave-front demultiplexing transformation, such as IFFT chip, Butler matrix, or a device performing a specified transformation of an inverse orthogonal matrix. Alternatively, the function of the wave-front demultiplexer can be realized by software installed in and performed by the processor, wherein the software can perform the above wave-front demultiplexing transform. Alternatively, the wave-front demultiplexer can be or include, but not limited to, a field programmable gate array (FPGA) or a digital signal processor (DSP). When the wave-front multiplexing and demultiplexing transformations are implemented by hardware, the wave-front multiplexer and the wave-front demultiplexer can be, but not limited to, a pair of Butler Matrixes, a Fourier transform pair, or a Hartley transform pair.
The wave-front demultiplexer can be layout with circuits for cells of basic functions recorded in a cell library such that any company of interest can implement the circuit layout in an integrated-circuit chip, a system-on chip (SOC) or an integrated-circuit chip package.
The wave-front demultiplexer (WF demuxer) features multiple-input and multiple-output (MIMO) processing that receives multiple input signals passing in parallel through multiple parallel input ports of the WF demuxer and outputs multiple output signals passing in parallel through multiple parallel output ports of the WF demuxer. The total number of the parallel input ports of the WF demuxer may be equal to the total number of the parallel output ports of the WF demuxer, may be equal to the total number of parallel input ports of a corresponding or complementary WF muxer, may be equal to the total number of parallel output ports of the corresponding or complementary WF muxer, may be equal to the number of rows or columns of an orthogonal matrix characterizing the corresponding or complementary WF muxer, may be equal to the number of rows or columns of an inverse orthogonal matrix characterizing the WF demuxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six. The total number of the input signals input in parallel to the WF demuxer may be equal to the total number of output signals output in parallel from the corresponding or complementary WF muxer, may be equal to the total number of the parallel inputs of the WF demuxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six. The total number of the output signals output in parallel form the WF demuxer may be equal to the total number of input signals input in parallel to the corresponding or complementary WF muxer, may be equal to or less than the total number of the input signals input in parallel to the WF demuxer, may be equal to or less than the total number of the output signals output in parallel from the corresponding or complementary WF muxer, may be equal to or less than the total number of the parallel output ports of the WF demuxer, and may be any number equal to or more than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six.
Mathematically, the wave-front demultiplexing transformation can be expressed by a linear equation as Z=WFDM*S, where S denotes input vectors such as four components S1-S4 in the following matrix D as illustrated in FIG. 1A, Z denotes output vectors such as four components in the following matrix F as illustrated in FIG. 1A, and WFDM denotes an inverse orthogonal matrix, such as the following matrix E as illustrated in FIG. 1A, of the wave-front demultiplexer. The wave-front multiplexing transformation can be expressed by a linear equation as Y=WFM*X, where X denotes input vectors such as four components X1-X4 in the following matrix A as illustrated in FIG. 1A, Y denotes output vectors such as four components in the following matrix C as illustrated in FIG. 1A, and WFM denotes an orthogonal matrix, such as the following matrix B as illustrated in FIG. 1A, of the wave-front multiplexer. The wave-front demultiplexing transformation features the characteristic that WFM*WFDM=I, where I is a unit matrix. Basically, WFM and WFDM are square matrices, and the order of WFM has the same rows and columns as the order of WFDM. For example, in case the orders of WFM and WFDM each having N rows and N columns are N×N, each of the wave-front multiplexing and demultiplexing transformations is available to processing N input vectors, i.e. input signals, and transforming the N input vectors into N output vectors, i.e. output signals, where N is an integer equal to or greater than two, four, eight, sixteen, thirty-two or two-hundred-and-fifty-six.
The wave-front demultiplexer, for example, can be used at a receiving side of a passive optical network (PON) with a complementary wave-front multiplexer at a transmitting side of the passive optical network, and multiple signal paths, such as physical fiber channels, can be set between the transmitting side of the passive optical network and the receiving side of the passive optical network. One or more optical transferring devices can be arranged in the signal paths between the transmitting side of the passive optical network and the receiving side of the passive optical network.
The above-mentioned descriptions of the wave-front multiplexer and the wave-front demultiplexer can be applied to the following embodiments.
FIG. 1A shows an example illustrating how a four-input and four-output wave-front multiplexer along with a four-input and four-output wave-front demultiplexer works.
Referring to FIG. 1A, a data communication system 888 includes a wave-front multiplexer 213, a wave-front demultiplexer 232 and a data relaying system 998. Each of the wave-front multiplexer 213 and the wave-front multiplexer 232 can be, but not limited to, a four-input and four-output unit. That is, the wave-front multiplexer 213 may have four inputs 2a, 2b, 2c and 2d and four outputs 3a, 3b, 3c and 3d, and the wave-front demultiplexer 232 may have four inputs 6a, 6b, 6c and 6d and four outputs 7a, 7b, 7c and 7d. 
The data relaying system 998 may include an optical line terminal (OLT), at least one optical transferring device and multiple optical network units (ONU) so as to relay data from a central office (CO) processor to multiple user processors or relay data from the user processors to the CO processor.
There are four input signals X1, X2, X3 and X4 input in parallel to the four inputs 2a, 2b, 2c and 2d of the wave-front multiplexer 213. The signals X1, X2, X3 and X4 can be, but not limited to, digital signals, analog signals, mixed analog and digital signals, or digital signal streams. Next, the wave-front multiplexer 213 performs the wave-front multiplexing transform to multiply the four input signals X1, X2, X3 and X4, represented by a 4×1 input matrix A, by an orthogonal matrix B so as to obtain four output signals Y1, Y2, Y3 and Y4 represented by a 4×1 output matrix C and then outputs the four output signals Y1, Y2, Y3 and Y4 from its four outputs 3a, 3b, 3c and 3d. The matrix B is a square matrix, and the transpose of the matrix B is equal to the inverse of the matrix B. The below formula (1) illustrates the input matrix A multiplied by the orthogonal matrix B, performed on the wave-front multiplexer 213.




  
    
      
        
          
            matrix
            ⁢
            
              
            
            ⁢
            A
          
          =
          
            [
            
              
                
                  
                    X
                    1
                  
                
              
              
                
                  
                    X
                    2
                  
                
              
              
                
                  
                    X
                    3
                  
                
              
              
                
                  
                    X
                    4
                  
                
              
            
            ]
          
        
        ⁢
        
          

        
        ⁢
        
          
            matrix
            ⁢
            
              
            
            ⁢
            B
          
          =
          
            [
            
              
                
                  
                    C
                    11
                  
                
                
                  
                    C
                    12
                  
                
                
                  
                    C
                    13
                  
                
                
                  
                    C
                    14
                  
                
              
              
                
                  
                    C
                    21
                  
                
                
                  
                    C
                    22
                  
                
                
                  
                    C
                    23
                  
                
                
                  
                    C
                    24
                  
                
              
              
                
                  
                    C
                    31
                  
                
                
                  
                    C
                    32
                  
                
                
                  
                    C
                    33
                  
                
                
                  
                    C
                    34
                  
                
              
              
                
                  
                    C
                    41
                  
                
                
                  
                    C
                    42
                  
                
                
                  
                    C
                    43
                  
                
                
                  
                    C
                    44
                  
                
              
            
            ]
          
        
        ⁢
        
          

        
        ⁢
        
          
            matrix
            ⁢
            
              
            
            ⁢
            C
          
          =
          
            
              
                [
                
                  
                    
                      
                        
                          
                            C
                            11
                          
                          ⁢
                          
                            X
                            1
                          
                        
                        +
                        
                          
                            C
                            12
                          
                          ⁢
                          
                            X
                            2
                          
                        
                        +
                        
                          
                            C
                            13
                          
                          ⁢
                          
                            X
                            3
                          
                        
                        +
                        
                          
                            C
                            14
                          
                          ⁢
                          
                            X
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            C
                            21
                          
                          ⁢
                          
                            X
                            1
                          
                        
                        +
                        
                          
                            C
                            22
                          
                          ⁢
                          
                            X
                            2
                          
                        
                        +
                        
                          
                            C
                            23
                          
                          ⁢
                          
                            X
                            3
                          
                        
                        +
                        
                          
                            C
                            24
                          
                          ⁢
                          
                            X
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            C
                            31
                          
                          ⁢
                          
                            X
                            1
                          
                        
                        +
                        
                          
                            C
                            32
                          
                          ⁢
                          
                            X
                            2
                          
                        
                        +
                        
                          
                            C
                            33
                          
                          ⁢
                          
                            X
                            3
                          
                        
                        +
                        
                          
                            C
                            34
                          
                          ⁢
                          
                            X
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            C
                            41
                          
                          ⁢
                          
                            X
                            1
                          
                        
                        +
                        
                          
                            C
                            42
                          
                          ⁢
                          
                            X
                            2
                          
                        
                        +
                        
                          
                            C
                            43
                          
                          ⁢
                          
                            X
                            3
                          
                        
                        +
                        
                          
                            C
                            44
                          
                          ⁢
                          
                            X
                            4
                          
                        
                      
                    
                  
                
                ]
              
              ⁢
              
                

              
              [
              
                
                  
                    
                      C
                      11
                    
                  
                  
                    
                      C
                      12
                    
                  
                  
                    
                      C
                      13
                    
                  
                  
                    
                      C
                      14
                    
                  
                
                
                  
                    
                      C
                      21
                    
                  
                  
                    
                      C
                      22
                    
                  
                  
                    
                      C
                      23
                    
                  
                  
                    
                      C
                      24
                    
                  
                
                
                  
                    
                      C
                      31
                    
                  
                  
                    
                      C
                      32
                    
                  
                  
                    
                      C
                      33
                    
                  
                  
                    
                      C
                      34
                    
                  
                
                
                  
                    
                      C
                      41
                    
                  
                  
                    
                      C
                      42
                    
                  
                  
                    
                      C
                      43
                    
                  
                  
                    
                      C
                      44
                    
                  
                
              
              ]
            
            ⁢
            
               
              
                
                  [
                  
                    
                      
                        
                          X
                          1
                        
                      
                    
                    
                      
                        
                          X
                          2
                        
                      
                    
                    
                      
                        
                          X
                          3
                        
                      
                    
                    
                      
                        
                          X
                          4
                        
                      
                    
                  
                  ]
                
                =
                
                  
                    [
                    
                      
                        
                          
                            
                              
                                C
                                11
                              
                              ⁢
                              
                                X
                                1
                              
                            
                            +
                            
                              
                                C
                                12
                              
                              ⁢
                              
                                X
                                2
                              
                            
                            +
                            
                              
                                C
                                13
                              
                              ⁢
                              
                                X
                                3
                              
                            
                            +
                            
                              
                                C
                                14
                              
                              ⁢
                              
                                X
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                C
                                21
                              
                              ⁢
                              
                                X
                                1
                              
                            
                            +
                            
                              
                                C
                                22
                              
                              ⁢
                              
                                X
                                2
                              
                            
                            +
                            
                              
                                C
                                23
                              
                              ⁢
                              
                                X
                                3
                              
                            
                            +
                            
                              
                                C
                                24
                              
                              ⁢
                              
                                X
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                C
                                31
                              
                              ⁢
                              
                                X
                                1
                              
                            
                            +
                            
                              
                                C
                                32
                              
                              ⁢
                              
                                X
                                2
                              
                            
                            +
                            
                              
                                C
                                33
                              
                              ⁢
                              
                                X
                                3
                              
                            
                            +
                            
                              
                                C
                                34
                              
                              ⁢
                              
                                X
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                C
                                41
                              
                              ⁢
                              
                                X
                                1
                              
                            
                            +
                            
                              
                                C
                                42
                              
                              ⁢
                              
                                X
                                2
                              
                            
                            +
                            
                              
                                C
                                43
                              
                              ⁢
                              
                                X
                                3
                              
                            
                            +
                            
                              
                                C
                                44
                              
                              ⁢
                              
                                X
                                4
                              
                            
                          
                        
                      
                    
                    ]
                  
                  =
                  
                    [
                    
                      
                        
                          
                            Y
                            1
                          
                        
                      
                      
                        
                          
                            Y
                            2
                          
                        
                      
                      
                        
                          
                            Y
                            3
                          
                        
                      
                      
                        
                          
                            Y
                            4
                          
                        
                      
                    
                    ]
                  
                
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




The components associated with the input X1 in the four outputs are in the forms of C11X1, C21X1, C31X1 and C41X1. The weighting distribution of the components associated with the input X1 in the four outputs is characterized by a first column vector, i.e. first wave-front multiplexing vector (WFMV1), where




  
    WFMV
    ⁢
    
      
    
    ⁢
    1
  
  =
  
    [
    
      
        
          
            C
            11
          
        
      
      
        
          
            C
            21
          
        
      
      
        
          
            C
            31
          
        
      
      
        
          
            C
            41
          
        
      
    
    ]
  




Similarly, the components associated with the input X2 in the four outputs are in the forms of C12X2, C22X2, C32X2 and C42X2. The weighting distribution of the components associated with the input X2 in the four outputs is characterized by a second column vector, i.e. second wave-front multiplexing vector (WFMV2), where




  
    WFMV
    ⁢
    
      
    
    ⁢
    2
  
  =
  
    [
    
      
        
          
            C
            12
          
        
      
      
        
          
            C
            22
          
        
      
      
        
          
            C
            32
          
        
      
      
        
          
            C
            42
          
        
      
    
    ]
  




The components associated with the input X3 in the four outputs are in the forms of C13X3, C23X3, C33X3 and C43X3. The weighting distribution of the components associated with the input X3 in the four outputs is characterized by a third column vector, i.e. third wave-front multiplexing vector (WFMV3), where




  
    WFMV
    ⁢
    
      
    
    ⁢
    3
  
  =
  
    [
    
      
        
          
            C
            13
          
        
      
      
        
          
            C
            23
          
        
      
      
        
          
            C
            33
          
        
      
      
        
          
            C
            43
          
        
      
    
    ]
  




The components associated with the input X4 in the four outputs are in the forms of C14X4, C24X4, C34X4 and C44X4. The weighting distribution of the components associated with the input X4 in the four outputs is characterized by a fourth column vector, i.e. fourth wave-front multiplexing vector (WFMV4), where




  
    WFMV
    ⁢
    
      
    
    ⁢
    4
  
  =
  
    [
    
      
        
          
            C
            14
          
        
      
      
        
          
            C
            24
          
        
      
      
        
          
            C
            34
          
        
      
      
        
          
            C
            44
          
        
      
    
    ]
  




The first and second wave-front multiplexing vectors are mutually orthogonal to each other. The first and third wave-front multiplexing vectors are mutually orthogonal to each other. The first and fourth wave-front multiplexing vectors are mutually orthogonal to each other. The second and third wave-front multiplexing vectors are mutually orthogonal to each other. The second and fourth wave-front multiplexing vectors are mutually orthogonal to each other. The third and fourth multiplexing wave-front vectors are mutually orthogonal to each other.
The output signal Y1 is a linear combination, i.e. weighted sum, of all input signals X1, X2, X3 and X4 multiplied by the weightings C11, C12, C13, and C14, respectively. That is, the output signal Y1 can be represented by a linear combination of C11X1 plus C12X2 plus C13X3 plus C14X4. The four input signals X1, X2, X3 and X4 can be completely independent. The output signal Y2 is a linear combination, i.e. weighted sum, of all input signals X1, X2, X3 and X4 multiplied by the weightings C21, C22, C23, and C24, respectively. That is, the output signal Y2 can be represented by a linear combination of C21X1 plus C22X2 plus C23X3 plus C24X4. The output signal Y3 is a linear combination, i.e. weighted sum, of all input signals X1, X2, X3 and X4 multiplied by the weightings C31, C32, C33, and C34, respectively. That is, the output signal Y3 can be represented by a linear combination of C31X1 plus C32X2 plus C33X3 plus C34X4. The output signal Y4 is a linear combination, i.e. weighted sum, of all input signals X1, X2, X3 and X4 multiplied by the weightings C41, C42, C43, and C44, respectively. That is, the output signal Y4 can be represented by a linear combination of C41X1 plus C42X2 plus C43X3 plus C44X4.
Therefore, each of the output signals Y1, Y2, Y3 and Y4 output from the wave-front multiplexer 213 is a linear combination, i.e. weighted sum, of all input signals X1, X2, X3 and X4 multiplied by respective weightings, and distributions of the weightings of any two input components in the four output signals Y1, Y2, Y3 and Y4 are orthogonal.
In other words, each of the output signals Y1, Y2, Y3 and Y4 carries information associated with all of the input signals X1, X2, X3 and X4 multiplied by the corresponding weightings, respectively. The output signal Y1 carries information associated with all of the input signals X1, X2, X3 and X4 multiplied by the respective weightings C11, C12, C13 and C14. The output signal Y2 carries information associated with all of the input signals X1, X2, X3 and X4 multiplied by the respective weightings C21, C22, C23 and C24. The output signal Y3 carries information associated with all of the input signals X1, X2, X3 and X4 multiplied by the respective weightings C31, C32, C33 and C34. The output signal Y4 carries information associated with all of the input signals X1, X2, X3 and X4 multiplied by the respective weightings C41, C42, C43 and C44.
Referring to FIG. 1C showing architecture of a wave-front multiplexer in accordance with the present invention. For more elaboration, the wave-front multiplexer can be adapted to receive the number H of input signals X, process the number H of the input signals X to be multiplied by the above-mentioned WFM matrix, such as H-by-H square orthogonal matrix, and output the number H of output signals Y, wherein H could be any number greater than or equal to 2, 4, 8, 16, 32, 64, 128 or 256. The input signals X can be, but not limited to, analog or digital signals. The output signals Y can be, but not limited to, analog or digital signals. The wave-front multiplexer may include the number H*H of computing units (CUs) and the number H of summing processors (SPs). The computing units (CUs) form an H-by-H processor array with the number H of columns and the number H of rows. The computing units (CUs) in each column in the processor array receive a corresponding input signal X, and thus the number H of the input signals X can be received by the computing units (CUs) in the number H of the respective columns in the processor array. Upon receiving the input signals X, each of the computing units (CUs) independently weights its received signal, multiplied by a corresponding weighting value, to generate a weighted signal. Each of the summing processors (SPs) provides a means for summing weighted signals generated by the corresponding computing units (CUs) in the same row in the processor array to produce a corresponding output signal Y. Accordingly, the number H of the summing processors (SPs) can output the number H of the output signals Y each combining the weighted signals output from the computing units (CUs) in a corresponding one of the number H of the rows in the processor array. The above-mentioned description of the wave-front multiplexer can be applied to the following embodiments.
In the case illustrated in FIG. 1A, the number of H is equal to 4. The wave-front multiplexer 213 illustrated in FIG. 1A may include 4*4 computing units (CUs) and four summing processors (SPs). The computing units (CUs) form a processor array with four rows and four columns. The input signals X1-X4 illustrated in FIG. 1A can be received by the computing units (CUs) in the respective four columns in the processor array. Upon receiving the input signals X1-X4, each of the computing units (CUs) independently weights its received signal, multiplied by a corresponding weighting value, to generate a corresponding weighted signal. The four summing processors (SPs) can output the four signals Y1-Y4 each combining the weighted signals output from the computing units (CUs) in a corresponding one of the four rows in the processor array.
Referring to FIG. 1A, after the wave-front multiplexer 213 outputs the signals Y1, Y2, Y3 and Y4, the signals Y1, Y2, Y3 and Y4 are transmitted in parallel into four inputs 4a, 4b, 4c and 4d of the data relaying system 998. The data relaying system 998 can relay data from the wave-front multiplexer 213 in the central office (CO) processor to a plurality of the wave-front demultiplexer 232 in the user processors, wherein the data carried by the signals Y1, Y2, Y3 and Y4 at the outputs 3a, 3b, 3c and 3d of the wave-front multiplexer 213 and the inputs of 4a, 4b, 4c and 4d of the data relaying system 998 are equivalent or correspondent to those carried by the signals S1, S2, S3 and S4 at the outputs 5a, 5b, 5c and 5d of the data relaying system 998 and the inputs of 6a, 6b, 6c and 6d of the wave-front demultiplexer 232, respectively. Alternatively, the data relaying system 998 can relay data from the wave-front multiplexer 213 in one of the user processor to the wave-front demultiplexer 232 in the central office (CO) processor, wherein the data carried by one or more of the signals Y1, Y2, Y3 and Y4 at the outputs 3a, 3b, 3c and 3d of the wave-front multiplexer 213 and the inputs of 4a, 4b, 4c and 4d of the data relaying system 998 are equivalent or correspondent to those carried by the corresponding one or more of the signals S1, S2, S3 and S4 at the outputs 5a, 5b, 5c and 5d of the data relaying system 998 and the inputs of 6a, 6b, 6c and 6d of the wave-front demultiplexer 232.
After the four signals S1, S2, S3 and S4 input in parallel to the four inputs 6a, 6b, 6c and 6d of the wave-front demultiplexer 232, the wave-front demultiplexer 232 performs the wave-front demultiplexing transform to multiply the four input signals S1, S2, S3 and S4, represented by a 4×1 input matrix D, by an orthogonal 4×4 matrix E so as to obtain four output signals Z1, Z2, Z3 and Z4 represented by a 4×1 output matrix F and then outputs the four output signals Z1, Z2, Z3 and Z4 from its outputs 7a, 7b, 7c and 7d. The matrix E is a square matrix, and the transponse of the matrix E is equal to the inverse of the matrix E. The below formula (2) illustrates the input matrix D multiplied by the orthogonal matrix E, performed on the wave-front demultiplexer 232.




  
    
      
        
          
            matrix
            ⁢
            
              
            
            ⁢
            D
          
          =
          
            [
            
              
                
                  
                    S
                    1
                  
                
              
              
                
                  
                    S
                    2
                  
                
              
              
                
                  
                    S
                    3
                  
                
              
              
                
                  
                    S
                    4
                  
                
              
            
            ]
          
        
        ⁢
        
          

        
        ⁢
        
          
            matrix
            ⁢
            
              
            
            ⁢
            E
          
          =
          
            [
            
              
                
                  
                    D
                    11
                  
                
                
                  
                    D
                    12
                  
                
                
                  
                    D
                    13
                  
                
                
                  
                    D
                    14
                  
                
              
              
                
                  
                    D
                    21
                  
                
                
                  
                    D
                    22
                  
                
                
                  
                    D
                    23
                  
                
                
                  
                    D
                    24
                  
                
              
              
                
                  
                    D
                    31
                  
                
                
                  
                    D
                    32
                  
                
                
                  
                    D
                    33
                  
                
                
                  
                    D
                    34
                  
                
              
              
                
                  
                    D
                    41
                  
                
                
                  
                    D
                    42
                  
                
                
                  
                    D
                    43
                  
                
                
                  
                    D
                    44
                  
                
              
            
            ]
          
        
        ⁢
        
          

        
        ⁢
        
          
            matrix
            ⁢
            
              
            
            ⁢
            F
          
          =
          
            
              
                [
                
                  
                    
                      
                        
                          
                            D
                            11
                          
                          ⁢
                          
                            S
                            1
                          
                        
                        +
                        
                          
                            D
                            12
                          
                          ⁢
                          
                            S
                            2
                          
                        
                        +
                        
                          
                            D
                            13
                          
                          ⁢
                          
                            S
                            3
                          
                        
                        +
                        
                          
                            D
                            14
                          
                          ⁢
                          
                            S
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            D
                            21
                          
                          ⁢
                          
                            S
                            1
                          
                        
                        +
                        
                          
                            D
                            22
                          
                          ⁢
                          
                            S
                            2
                          
                        
                        +
                        
                          
                            D
                            23
                          
                          ⁢
                          
                            S
                            3
                          
                        
                        +
                        
                          
                            D
                            24
                          
                          ⁢
                          
                            S
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            D
                            31
                          
                          ⁢
                          
                            S
                            1
                          
                        
                        +
                        
                          
                            D
                            32
                          
                          ⁢
                          
                            S
                            2
                          
                        
                        +
                        
                          
                            D
                            33
                          
                          ⁢
                          
                            S
                            3
                          
                        
                        +
                        
                          
                            D
                            34
                          
                          ⁢
                          
                            S
                            4
                          
                        
                      
                    
                  
                  
                    
                      
                        
                          
                            D
                            41
                          
                          ⁢
                          
                            S
                            1
                          
                        
                        +
                        
                          
                            D
                            42
                          
                          ⁢
                          
                            S
                            2
                          
                        
                        +
                        
                          
                            D
                            43
                          
                          ⁢
                          
                            S
                            3
                          
                        
                        +
                        
                          
                            D
                            44
                          
                          ⁢
                          
                            S
                            4
                          
                        
                      
                    
                  
                
                ]
              
              ⁢
              
                

              
              [
              
                
                  
                    
                      D
                      11
                    
                  
                  
                    
                      D
                      12
                    
                  
                  
                    
                      D
                      13
                    
                  
                  
                    
                      D
                      14
                    
                  
                
                
                  
                    
                      D
                      21
                    
                  
                  
                    
                      D
                      22
                    
                  
                  
                    
                      D
                      23
                    
                  
                  
                    
                      D
                      24
                    
                  
                
                
                  
                    
                      D
                      31
                    
                  
                  
                    
                      D
                      32
                    
                  
                  
                    
                      D
                      33
                    
                  
                  
                    
                      D
                      34
                    
                  
                
                
                  
                    
                      D
                      41
                    
                  
                  
                    
                      D
                      42
                    
                  
                  
                    
                      D
                      43
                    
                  
                  
                    
                      D
                      44
                    
                  
                
              
              ]
            
            ⁢
            
               
              
                
                  [
                  
                    
                      
                        
                          S
                          1
                        
                      
                    
                    
                      
                        
                          S
                          2
                        
                      
                    
                    
                      
                        
                          S
                          3
                        
                      
                    
                    
                      
                        
                          S
                          4
                        
                      
                    
                  
                  ]
                
                =
                
                  
                    [
                    
                      
                        
                          
                            
                              
                                D
                                11
                              
                              ⁢
                              
                                S
                                1
                              
                            
                            +
                            
                              
                                D
                                12
                              
                              ⁢
                              
                                S
                                2
                              
                            
                            +
                            
                              
                                D
                                13
                              
                              ⁢
                              
                                S
                                3
                              
                            
                            +
                            
                              
                                D
                                14
                              
                              ⁢
                              
                                S
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                D
                                21
                              
                              ⁢
                              
                                S
                                1
                              
                            
                            +
                            
                              
                                D
                                22
                              
                              ⁢
                              
                                S
                                2
                              
                            
                            +
                            
                              
                                D
                                23
                              
                              ⁢
                              
                                S
                                3
                              
                            
                            +
                            
                              
                                D
                                24
                              
                              ⁢
                              
                                S
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                D
                                31
                              
                              ⁢
                              
                                S
                                1
                              
                            
                            +
                            
                              
                                D
                                32
                              
                              ⁢
                              
                                S
                                2
                              
                            
                            +
                            
                              
                                D
                                33
                              
                              ⁢
                              
                                S
                                3
                              
                            
                            +
                            
                              
                                D
                                34
                              
                              ⁢
                              
                                S
                                4
                              
                            
                          
                        
                      
                      
                        
                          
                            
                              
                                D
                                41
                              
                              ⁢
                              
                                S
                                1
                              
                            
                            +
                            
                              
                                D
                                42
                              
                              ⁢
                              
                                S
                                2
                              
                            
                            +
                            
                              
                                D
                                43
                              
                              ⁢
                              
                                S
                                3
                              
                            
                            +
                            
                              
                                D
                                44
                              
                              ⁢
                              
                                S
                                4
                              
                            
                          
                        
                      
                    
                    ]
                  
                  =
                  
                    [
                    
                      
                        
                          
                            Z
                            1
                          
                        
                      
                      
                        
                          
                            Z
                            2
                          
                        
                      
                      
                        
                          
                            Z
                            3
                          
                        
                      
                      
                        
                          
                            Z
                            4
                          
                        
                      
                    
                    ]
                  
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




The components associated with the input S1 in the four outputs are in the forms of D11S1, D21S1, D31S1 and D41S1. The weighting distribution of the components associated with the input S1 in the four outputs is characterized by a first column vector, i.e. first wave-front demultiplexing vector (WFDV1), where




  
    WFDV
    ⁢
    
      
    
    ⁢
    1
  
  =
  
    [
    
      
        
          
            D
            11
          
        
      
      
        
          
            D
            21
          
        
      
      
        
          
            D
            31
          
        
      
      
        
          
            D
            41
          
        
      
    
    ]
  




Similarly, the components associated with the input S2 in the four outputs are in the forms of D12S2, D22S2, D32S2 and D42S2. The weighting distribution of the components associated with the input S2 in the four outputs is characterized by a second column vector, i.e. second wave-front demultiplexing vector (WFDV2), where




  
    WFDV
    ⁢
    
      
    
    ⁢
    2
  
  =
  
    [
    
      
        
          
            D
            12
          
        
      
      
        
          
            D
            22
          
        
      
      
        
          
            D
            32
          
        
      
      
        
          
            D
            42
          
        
      
    
    ]
  




The components associated with the input S3 in the four outputs are in the forms of D13S3, D23S3, D33S3 and D43S3. The weighting distribution of the components associated with the input S3 in the four outputs is characterized by a third column vector, i.e. third wave-front demultiplexing vector (WFDV3), where




  
    WFDV
    ⁢
    
      
    
    ⁢
    3
  
  =
  
    [
    
      
        
          
            D
            13
          
        
      
      
        
          
            D
            23
          
        
      
      
        
          
            D
            33
          
        
      
      
        
          
            D
            43
          
        
      
    
    ]
  




The components associated with the input S4 in the four outputs are in the forms of D14S4, D24S4, D34S4 and D44S4. The weighting distribution of the components associated with the input S4 in the four outputs is characterized by a fourth column vector, i.e. fourth wave-front demultiplexing vector (WFDV4), where




  
    WFDV
    ⁢
    
      
    
    ⁢
    4
  
  =
  
    [
    
      
        
          
            D
            14
          
        
      
      
        
          
            D
            24
          
        
      
      
        
          
            D
            34
          
        
      
      
        
          
            D
            44
          
        
      
    
    ]
  




The first and second wave-front demultiplexing vectors are mutually orthogonal to each other. The first and third wave-front demultiplexing vectors are mutually orthogonal to each other. The first and fourth wave-front demultiplexing vectors are mutually orthogonal to each other. The second and third wave-front demultiplexing vectors are mutually orthogonal to each other. The second and fourth wave-front demultiplexing vectors are mutually orthogonal to each other. The third and fourth wave-front demultiplexing vectors are mutually orthogonal to each other.
The output signal Z1 is a linear combination, i.e. weighted sum, of all input signals S1, S2, S3 and S4 multiplied by the weightings D11, D12, D13, and D14, respectively. That is, the output signal Z1 can be represented by a linear combination of D11S1 plus D12S2 plus D13S3 plus D14S4. The output signal Z2 is a linear combination, i.e. weighted sum, of all input signals S1, S2, S3 and S4 multiplied by the weightings D21, D22, D23, and D24, respectively. That is, the output signal Z2 can be represented by a linear combination of D21S1 plus D22S2 plus D23S3 plus D24S4. The output signal Z3 is a linear combination, i.e. weighted sum, of all input signals S1, S2, S3 and S4 multiplied by the weightings D31, D32, D33, and D34, respectively. That is, the output signal Z3 can be represented by a linear combination of D31S1 plus D32S2 plus D33S3 plus D34S4. The output signal Z4 is a linear combination, i.e. weighted sum, of all input signals S1, S2, S3 and S4 multiplied by the weightings D41, D42, D43, and D44, respectively. That is, the output signal Z4 can be represented by a linear combination of D41S1 plus D42S2 plus D43S3 plus D44S4.
Therefore, each of the output signals Z1, Z2, Z3 and Z4 output from the wave-front demultiplexer 232 is a linear combination, i.e. weighted sum, of all input signals S1, S2, S3 and S4 multiplied by respective weightings, and distributions of the weightings of any two input components in the four output signals are orthogonal.
In other words, each of the output signals Z1, Z2, Z3 and Z4 carries information associated with all of the input signals S1, S2, S3 and S4 multiplied by the corresponding weightings, respectively. The output signal Z1 carries information associated with all of the input signals S1, S2, S3 and S4 multiplied by the respective weightings D11, D12, D13 and D14. The output signal Z2 carries information associated with all of the input signals S1, S2, S3 and S4 multiplied by the respective weightings D21, D22, D23 and D24. The output signal Z3 carries information associated with all of the input signals S1, S2, S3 and S4 multiplied by the respective weightings D31, D32, D33 and D34. The output signal Z4 carries information associated with all of the input signals S1, S2, S3 and S4 multiplied by the respective weightings D41, D42, D43 and D44.
Therefore, each of the signals Z1, Z2, Z3 and Z4 output from the wave-front demultiplexer 232 is correspondent or substantially equivalent to or carries information associated with a corresponding one of the signals X1, X2, X3 and X4 input to the wave-front multiplexer 213.
The matrix B and the matrix E, for example, can be equal. That is, the weightings at the same column and row in the matrix B and the matrix E have the same values, and the matrix B has the same number of rows and columns as the matrix E. In other words, the matrix B and the matrix E have the same dimensions and have the same values at the same positions. For instance, the weighting C11 of the matrix B may have a value equal to the value of the weighting D11 of the matrix E. The weighting C12 of the matrix B may have a value equal to the value of the weighting D12 of the matrix E. The weighting C13 of the matrix B may have a value equal to the value of the weighting D13 of the matrix E. The weighting C14 of the matrix B may have a value equal to the value of the weighting D14 of the matrix E. The weighting C21 of the matrix B may have a value equal to the value of the weighting D21 of the matrix E. The weighting C22 of the matrix B may have a value equal to the value of the weighting D22 of the matrix E. The weighting C23 of the matrix B may have a value equal to the value of the weighting D23 of the matrix E. The weighting C24 of the matrix B may have a value equal to the value of the weighting D24 of the matrix E. The weighting C31 of the matrix B may have a value equal to the value of the weighting D31 of the matrix E. The weighting C32 of the matrix B may have a value equal to the value of the weighting D32 of the matrix E. The weighting C33 of the matrix B may have a value equal to the value of the weighting D33 of the matrix E. The weighting C34 of the matrix B may have a value equal to the value of the weighting D34 of the matrix E. The weighting C41 of the matrix B may have a value equal to the value of the weighting D41 of the matrix E. The weighting C42 of the matrix B may have a value equal to the value of the weighting D42 of the matrix E. The weighting C43 of the matrix B may have a value equal to the value of the weighting D43 of the matrix E. The weighting C44 of the matrix B may have a value equal to the value of the weighting D44 of the matrix E.
Alternatively, the matrix E can be constructed to be equal to the matrix B multiplied by a scalar, and the matrix B and the matrix E have the same dimensions. That is, each of the weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E may have a value equal to the value of the corresponding one of the weightings C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43 and C44 in the matrix B, at the same column and row as the each of the weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E, multiplied by the same scalar, and the matrix B has the same numbers of rows and columns as the matrix E. The weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E may have values equal respectively to the values of the corresponding weightings C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43 and C44 in the matrix B multiplied by the same scalar.
Alternatively, each weighting in the matrix E may have a value taking the complex conjugate of the value of the corresponding weighting in the matrix B, at the same column and row as the each weighting in the matrix E. For instance, the weighting C11 of the matrix B has a value equal to the conjugate of the value of the weighting D11. The weighting C12 of the matrix B has a value equal to the conjugate of the value of the weighting D12. The weighting C13 of the matrix B has a value equal to the conjugate of the value of the weighting D13. The weighting C14 of the matrix B has a value equal to the conjugate of the value of the weighting D14. The weighting C21 of the matrix B has a value equal to the conjugate of the value of the weighting D21. The weighting C22 of the matrix B has a value equal to the conjugate of the value of the weighting D22. The weighting C23 of the matrix B has a value equal to the conjugate of the value of the weighting D23. The weighting C24 of the matrix B has a value equal to the conjugate of the value of the weighting D24. The weighting C31 of the matrix B has a value equal to the conjugate of the value of the weighting D31. The weighting C32 of the matrix B has a value equal to the conjugate of the value of the weighting D32. The weighting C33 of the matrix B has a value equal to the value of the conjugate of the weighting D33. The weighting C34 of the matrix B has a value equal to the conjugate of the value of the weighting D34. The weighting C41 of the matrix B has a value equal to the conjugate of the value of the weighting D41. The weighting C42 of the matrix B has a value equal to the conjugate of the value of the weighting D42. The weighting C43 of the matrix B has a value equal to the conjugate of the value of the weighting D43. The weighting C44 of the matrix B has a value equal to the conjugate of the value of the weighting D44.
Alternatively, each of the weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E may have a value taking the complex conjugate of the value of the corresponding one of the weightings C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43 and C44 in the matrix B, at the same column and row as the each of the weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E, multiplied by the same scalar, and the matrix B has the same numbers of rows and columns as the matrix E. The weightings D11, D12, D13, D14, D21, D22, D23, D24, D31, D32, D33, D34, D41, D42, D43 and D44 in the matrix E may have values equal respectively to the conjugates of the values of the weightings C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43 and C44 in the matrix B multiplied by the same scalar.
Referring to FIG. 1D showing architecture of a wave-front demultiplexer in accordance with the present invention. For more elaboration, the wave-front demultiplexer can be adapted to receive the number I of input signals S, process the number I of the input signals S to be multiplied by the above-mentioned WFDM matrix, such as I-by-I square orthogonal matrix, and output the number I of output signals Z, wherein I could be any number greater than or equal to 2, 4, 8, 16, 32, 64, 128 or 256. The input signals S can be, but not limited to, analog or digital signals. The output signals Z can be, but not limited to, analog or digital signals. The wave-front demultiplexer may include the number I*I of computing units (CUs) and the number I of summing processors (SPs). The computing units (CUs) form an I-by-I processor array with the number I of columns and the number I of rows. The computing units (CUs) in each column in the processor array receive a corresponding input signal S, and thus the number I of the input signals S can be received by the computing units (CUs) in the number I of the respective columns in the processor array. Upon receiving the input signals S, each of the computing units (CUs) independently weights its received signal, multiplied by a corresponding weighting value, to generate a weighted signal. Each of the summing processors (SPs) provides a means for summing weighted signals generated by the corresponding computing units (CUs) in the same row in the processor array to produce a corresponding output signal Z. Accordingly, the number I of the summing processors (SPs) can output the number I of the output signals Z each combining the weighted signals output from the computing units (CUs) in a corresponding one of the number I of the rows in the processor array. The above-mentioned description of the wave-front demultiplexer can be applied to the following embodiments.
In the case illustrated in FIG. 1A, the number of I is equal to 4. The wave-front demultiplexer 232 illustrated in FIG. 1A may include 4*4 computing units (CUs) and four summing processors (SPs). The computing units (CUs) form a processor array with four rows and four columns. The four input signals S1-S4 illustrated in FIG. 1A can be received by the computing units (CUs) in the respective four columns in the processor array. Upon receiving the four input signals S1-S4, each of the computing units (CUs) independently weights its received signal, multiplied by a corresponding weighting value, to generate a corresponding weighted signal. The four summing processors (SPs) can output the four signals Z1-Z4 each combining the weighted signals output from the computing units (CUs) in a corresponding one of the four rows in the processor array.
Referring to FIGS. 1A, 1C and 1D, when the above-mentioned wave-front demultiplexing transformation performed by the wave-front demultiplexer 232 having the architecture illustrated in FIG. 1D inverts or transforms signals previously transformed by the wave-front multiplexing transformation performed by its complementary wave-front multiplexer 213 having the architecture illustrated in FIG. 1C, the number of H is equal to the number of I. Each weighting for multiplying a corresponding one of the input signals X, performed by a corresponding one of the computing units of the wave-front multiplexer 213, may have the same value as the corresponding weighting for multiplying a corresponding one of the input signals S, performed by a corresponding one of the computing units of the wave-front demultiplexer 232 at the same row and column as the corresponding computing unit of the wave-front multiplexer 213. Alternatively, each weighting for multiplying a corresponding one of the input signals X, performed by a corresponding one of the computing units of the wave-front multiplexer 213, may have a value equal to that of the corresponding weighting for multiplying a corresponding one of the input signals S, performed by a corresponding one of the computing units of the wave-front demultiplexer 232 at the same row and column as the corresponding computing unit of the wave-front multiplexer 213, multiplied by the same scalar. Alternatively, each weighting for multiplying a corresponding one of the input signals X, performed by a corresponding one of the computing units of the wave-front multiplexer 213, may have a value equal to the conjugate of the value of the corresponding weighting for multiplying a corresponding one of the input signals S, performed by a corresponding one of the computing units of the wave-front demultiplexer 232 at the same row and column as the corresponding computing unit of the wave-front multiplexer 213. Alternatively, each weighting for multiplying a corresponding one of the input signals X, performed by a corresponding one of the computing units of the wave-front multiplexer 213, may have a value equal to the conjugate of the value of the corresponding weighting for multiplying a corresponding one of the input signals S, performed by a corresponding one of the computing units of the wave-front demultiplexer 232 at the same row and column as the corresponding computing unit of the wave-front multiplexer 213, multiplied by the same scalar.
Alternatively, referring to FIG. 1B, the data communication system 888 may further include an equalization processor 231 and an optimizer or optimization processor 235 for performing signal compensations. The equalization processor 231 may include multiple adaptive equalizers 231a, 231b, 231c and 231d for compensating the amplitudes, phases and/or time delays of signals passing through respective paths between the outputs 5a, 5b, 5c and 5d of the data relaying system 998 and the inputs 6a, 6b, 6c and 6d of the wave-front demultiplexer 232. The data communication system 888 shown in FIG. 1B is similar to the data communication system 888 illustrated in FIG. 1A except that the data communication system 888 illustrated in FIG. 1B further includes the equalization processor 231 and the optimizer 235 and that the signal X4 illustrated in FIG. 1B is a pilot or diagnostic signal. The pilot or diagnostic signal X4 may have a single frequency and fixed amplitude. Alternatively, the pilot or diagnostic signal X4 could change based on time or could be any signal known by the data communication system 888. In contrast, the extraneous signals X1, X2 and X3 are unknown by the data communication system 888 and input into the data communication system 888 from an extraneous system.
Besides, compared with the signals S1, S2, S3 and S4, in FIG. 1A, input into the wave-front demultiplexer 232, the signals S1, S2, S3 and S4, in FIG. 1B, are equalized by the equalizers 231a, 231b, 231c and 231d. In this embodiment, four signals W1, W2, W3 and W4 are defined as ones output from outputs 5a, 5b, 5c and 5d of the data relaying system 998 and have not been equalized by the equalization processor 231.
Referring to FIG. 1B, the data relaying system 998 can be arranged between the wave-front multiplexer 213 and the equalization processor 231. The data relaying system 998 can relay data from the wave-front multiplexer 213 in the CO processor to a plurality of the equalization processor 231 in the user processors, wherein the data carried by the signals Y1, Y2, Y3 and Y4 at the inputs of 4a, 4b, 4c and 4d of the data relaying system 998 are equivalent or correspondent to those carried by the signals W1, W2, W3 and W4 at the outputs 5a, 5b, 5c and 5d of the data relaying system 998, respectively. Alternatively, the data relaying system 998 can relay data from the wave-front multiplexer 213 in one of the user processor to the equalization processor 231 in the CO processor, wherein the data carried by one or more of the signals Y1, Y2, Y3 and Y4 at the inputs of 4a, 4b, 4c and 4d of the data relaying system 998 are equivalent or correspondent to those carried by the corresponding one or more of the signals W1, W2, W3 and W4 at the outputs 5a, 5b, 5c and 5d of the data relaying system 998.
The equalizers 231a, 231b, 231c and 231d are in four signal paths between the four outputs 5a, 5b, 5c and 5d of the data relaying system 998 and the input ports 6a, 6b, 6c and 6d of the wave-front demultiplexer 232. The optimizer 235 is in signal paths between the outputs 7a, 7b, 7c and 7d of the wave-front demultiplexer 232 and the equalizers 231a, 231b, 231c and 231d. In this embodiment, the input signal X4 input to the input 2d of the wave-front multiplexer 213 is a pilot or diagnostic signal. The output signal Z4 output from the output 7d of the wave-front demultiplexer 232 is supposed to be correspondent or substantially equivalent to the input signal X4, i.e. pilot or diagnostic signal. The equalization processor 231 can perform amplitude, phase, and time-delay compensation to adjust the amplitudes, phases, and/or time-delays of the signals W1, W2, W3 and W4. The wave-front multiplexing transform performed by the wave-front multiplexer 213 shown in FIG. 1B can refer to the wave-front multiplexing transform performed by the wave-front multiplexer 213 as illustrated in FIG. 1A. The wave-front demultiplexing transform performed by the wave-front demultiplexer 232 shown in FIG. 1B can refer to the wave-front demultiplexing transform performed by the wave-front demultiplexer 232 as illustrated in FIG. 1A.
To avoid propagation effects and/or the difference of unbalanced amplitudes, unbalanced phases and/or unbalanced time-delays among the signals W1, W2, W3 and W4 output from the data relaying system 998, the data communication system 888 performs an optimizing and equalizing process to the signals W1, W2, W3 and W4 by the equalization processor 231 and the optimization processor 235. The signals W1, W2, W3 and W4 input to the inputs 10a, 10b, 10c and 10d of the equalizers 231a, 231b, 231c and 231d can be equalized by the equalizers 231a, 231b, 231c and 231d weighting or multiplying the signals W1, W2, W3 and W4 by four respective equalizing weights for compensating unbalanced amplitudes, unbalanced phases and/or unbalanced time-delays among the signals W1, W2, W3 and W4 so as to generate the respective equalized signals S1, S2, S3 and S4. The equalizing weights can be updated by the optimizer 235 based on calculation of cost functions in accordance with a cost minimization algorithm, such as steepest descent method.
During the optimizing and equalizing process, one (F1) of the cost functions may observe the change between the known diagnostic data, which is carried by the diagnostic or pilot signal X4 at the input 2d of the wave-front multiplexer 213, and the signal Z4 at the output 7d of the wave-front demultiplexer 232. In the other words, the cost function (F1) may be based on observation of changes between the recovered diagnostic signal Z4 at the output 7d of the wave-front demultiplexer 232 and the injected diagnostic signal X4 at the input 2d of the wavefront multiplexer 432. When there is no observed change, the cost function (F1) shall be assigned to zero. On the other hand, the value of the cost function (F1) shall be assigned to a positive number when there are observed change. The larger the positive number shall be assigned to the larger the observed change is.
Alternatively, others (F2) of the cost functions may be based on observations among the signals Z1, Z2, Z3 and Z4 output from the wave-front demultiplexer 232. More specifically, the cost functions (F2) may be related to cross-correlation between each two of the signals Z1, Z2, Z3 and Z4 received by the optimizer 235. When the observed cross-correlations are less than a pre-assigned threshold, the corresponding cost functions (F2) shall be assigned to zero. On the other hand, when the observed cross-correlation is greater than the pre-assigned threshold, the value of the corresponding cost function (F2) shall be assigned to a positive number. The larger the observed cross-correlation is the larger value the corresponding cost function (F2) shall be assigned to.
In the equalizing and optimizing process, the optimizer 235 is configured to calculate a total cost based on the sum of all of the cost functions (F1) and (F2) and then compare the total cost with a predetermined cost threshold. When the total cost is verified to be greater than the predetermined cost threshold, the optimizer 235 is configured to calculate a variation in the total cost in response to perturbations on the equalizing weights buffered in the equalizers 231a, 231b, 231c and 231d or to measure each gradient of the total cost with respect to the equalizing weights buffered in the equalizers 231a, 231b, 231c and 231d. Based on the calculated variation or measured gradients, the optimizer 235 creates updated equalizing weights, based on a cost minimization algorithm, such as steepest descent method, to be sent to the adaptive equalizers 231a, 231b, 231c and 231d respectively and to replace respective current ones buffered in the adaptive equalizers 231a, 231b, 231c and 231d in the next scheduled clock cycle. Thereby, the equalizing weights buffered in the equalizers 231a, 231b, 231c and 231d can be updated. The optimizer 235 is configured to stop the equalizing and optimizing process when the total cost is verified to be less than the predetermined cost threshold.
Each of the equalizing weights buffered in the equalizers 231a, 231b, 231c and 231c can be, but not limited to, a complex value such that the equalized signals, such as the equalized signals S1, S2, S3 and S4, e.g., illustrated in FIG. 1B, can be rotated precisely to become in phase. In the case that the equalizer is performed by a narrow band equalizer, such as amplitude-and-phase filter, the narrow band equalizer can alter each of the received signals, such as the signals W1, W2, W3 and W4, e.g., illustrated in FIG. 1B, by fixed amplitude and phase across a narrow frequency band. The narrow band equalizer can provide phase and amplitude modifications to each of the received signals, such as the signals W1, W2, W3 and W4, e.g., illustrated in FIG. 1B, with a constant phase shift and constant amplitude attenuation across the narrow frequency band. Alternatively, in the case that the equalizer is performed by a broadband equalizer, such as finite impulse filter (FIR), the broadband equalizer can alter each of the received signals, such as the signals W1, W2, W3 and W4, e.g., illustrated in FIG. 1B, by amplitude and phase depending on an amplitude and phase profile, changing with frequencies, across a broad frequency band. The broad band equalizer can provide phase and amplitude modifications to each of the received signals, such as the signals W1, W2, W3 and W4, e.g., illustrated in FIG. 1B, with a constant phase shift and a constant amplitude attenuation in each sub-band across the broad frequency band, but the phase shift and amplitude attenuation in one sub-band across the broad frequency band is different from those in the other sub-bands across the broad frequency band.
The equalized signals, such as the equalized signals S1, S2, S3 and S4, e.g., illustrated in FIG. 1B, are transformed by the wave-front demultiplexer 232, which can refer to the wave-front demultiplexing transform performed by the wave-front demultiplexer 232 as illustrated in FIG. 1A.
In all of the embodiments of the present disclosure, the equalization processor 231, the wave-front demultiplexer 232 and the optimizer 235 can be, but not limited to, embedded in a single integrated circuit chip, single system-on chip or single chip package. The equalization processor 231 can be hardware or can be realized by software installed in and performed by a computer. The optimizer 235 can be hardware or can be realized by software installed in and performed by the computer.
The above-mentioned descriptions of the wave-front multiplexer 213, the wave-front demultiplexer 232, the equalization processor 231, and the optimizer 235 can be applied to the following embodiments of the invention.
Time-Domain Multiplexer (TDM):
A time-domain multiplexer (TDM) can perform time-domain multiplexing to combine or integrate the number N of pieces of input digital data in the number N of respective input data flows each having a low bandwidth J/N sampled at a low sampling rate K/N into a piece of output digital data in an output data flow having a high bandwidth J sampled at a high sampling rate K based on the number N of respective non-overlapped time slots. For example, the time-domain multiplexer is a 4-to-1 time-domain multiplexer that can combine or integrate four pieces of input digital data, i.e. first, second, third and fourth pieces of input data flow, in four respective input data flows, i.e. first, second, third and fourth input data flows, each having a bandwidth J/4 sampled at a sampling rate K/4 into a piece of output digital data in an output data flow having a bandwidth J sampled at a sampling rate K based on four respective non-overlapped time slots, i.e. first, second, third and fourth time slots. For more elaboration, the piece of output digital data output from the 4-to-1 time-domain multiplexer at the first time slot may be the first piece of input digital data in the first input data flow. The piece of output digital data output from the 4-to-1 time-domain multiplexer at the second time slot may be the second piece of input digital data in the second input data flow. The piece of output digital data output from the 4-to-1 time-domain multiplexer at the third time slot may be the third piece of input digital data in the third input data flow. The piece of output digital data output from the 4-to-1 time-domain multiplexer at the fourth time slot may be the fourth piece of input digital data in the fourth input data flow.
The time-domain multiplexer can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA).
Time-Domain Demultiplexer (TDDM):
A time-domain demultiplexer (TDDM) can perform time-domain demultiplexing to allocate input digital data in an input data flow having a high bandwidth P sampled at a high sampling rate Q into the number M of pieces of output digital data in the number M of respective data flows having a low bandwidth P/M sampled at a low sampling rate Q/M based on the number M of respective non-overlapped time slots. For example, the time-domain demultiplexer is a 1-to-4 time-domain demultiplexer that can allocate input digital data in an input data flow having a high bandwidth P sampled at a high sampling rate Q into four pieces of output digital data, i.e. first, second, third and fourth pieces of output digital data, in four respective non-overlapped data flows, i.e. first, second, third and fourth data flows, having a bandwidth P/4 sampled at a sampling rate Q/4 based on four respective time slots, i.e. first, second, third and fourth time slots. For more elaboration, the first piece of output digital data in the first output data flow may be the input digital data, in the input data flow, arriving at the 1-to-4 time-domain demultiplexer at the first time slot. The second piece of output digital data in the second output data flow may be the input digital data, in the input data flow, arriving at the 1-to-4 time-domain demultiplexer at the second time slot. The third piece of output digital data in the third output data flow may be the input digital data, in the input data flow, arriving at the 1-to-4 time-domain demultiplexer at the third time slot. The fourth piece of output digital data in the fourth output data flow may be the input digital data, in the input data flow, arriving at the 1-to-4 time-domain demultiplexer at the fourth time slot.
The time-domain demultiplexer can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA).
Structure of Passive Optical Network (PON):
FIG. 2A is a schematic diagram showing a passive optical network (PON) in combination with wave-front multiplexing and demultiplexing techniques for dynamically allocating the resource of the passive optical network system for multiple user processors according to an embodiment of the present invention. The passive optical network 200 includes an optical line terminal 202 (OLT) 202, an optical transferring device 204, the number n of optical network units 206 (ONUs), and multiple optical fibers 207 and 208, wherein the number n may be a positive integer greater than 2, such as 4, 8 or 12. The optical fiber 207 connects the optical line terminal 202 (OLT) and the optical transferring device 204 and each of the optical fibers 208 connects the optical transferring device 204 and a corresponding one of the optical network units 206 (ONUs).
Referring to FIG. 2A, the optical transferring device 204 may serve as an optical coupler and an optical splitter. For example, in a downstream direction, the optical transferring device 204 can serve as an optical splitter for splitting an input optical signal, passing from the optical line terminal 202 and through the optical fiber 207, into multiple output optical signals, passing to the respective optical network units 206 and through the respective optical fibers 208, wherein data carried by each of the output optical signals are substantially equivalent to those carried by the input optical signal. In an upstream direction, the optical transferring device 204 can serve as an optical coupler for combining optical signals, passing from the respective optical network units 206 and through the respective optical fibers 208, into an optical signal, passing to the optical line terminal 202 and through the optical fiber 207.
Referring to FIG. 2A, the optical line terminal 202 (OLT) is arranged between the central office (CO) processor 210 and the optical transferring device 204. In the downstream direction, the optical line terminal 202 can transform electronic data, output from the central office processor 210, into optical data sent to the optical transferring device 204 through the optical fiber 207. In the upstream direction, the optical line terminal 202 can transform optical data, output from the optical transferring device 204, into electronic data sent to the central office processor 210.
Referring to FIG. 2A, each of the optical network units 206 (ONUs) is arranged between and the optical transferring device 204 and a corresponding one of thirty-two user processors 222. In the downstream direction, each of the optical network units 206 can transform optical data, output from the optical transferring device 204, into electronic data sent to a corresponding one of the user processors 222. In the upstream direction, each of the optical network units 206 can transform electronic data, output from a corresponding one of the user processors 222, into optical data sent to the optical transferring device 204 through a correspond one of the optical fibers 208.
Alternatively, FIG. 2B is a schematic diagram showing a passive optical network (PON) in combination with wave-front multiplexing and demultiplexing techniques for dynamically allocating the resource of the passive optical network system for multiple user processors according to another embodiment of the present invention. Referring to FIG. 2B, the optical transferring devices 204 can be multiple layered for some of the user processors 222, i.e. the top two and bottom two of the user processors 222, wherein an optical fiber 208 connects optical transferring devices 204 at different layers for communicating data therebetween. The optical transferring device 204 can be single layered for some of the user processors 222, i.e. the middle ones of the user processors 222.
Downstream Dataflow Via Passive Optical Network (PON):
FIGS. 3A, 3B and 3C are schematic diagrams showing downstream dataflow performed by a passive optical network (PON) in combination with wave-front multiplexing and demultiplexing techniques according to an embodiment of the present invention. Referring to FIG. 3A and FIG. 3B, the passive optical network includes a central office (CO) processor 210 and thirty-two user processors 2221-22232, for example. The central office processor 210 includes a first wave-front multiplexer 212, which can refer to the wave-front multiplexer 212 as illustrated in FIGS. 1A and 1B, a first input mapping unit 218 at the upstream side of the wave-front multiplexer 212, a first output mapping unit 224 at the downstream side of the wave-front multiplexer 212 and a controller 220 controlling the mapping of the first input mapping unit 218 and second output mapping unit 240 and/or the mapping of the first output mapping unit 224 and second input mapping unit 234. Digital electronic data in thirty-two data flows Da1-Da32 and pilot or diagnostic electronic data in data flow XZ are injected into the central office processor 210 and are to be transmitted to the thirty-two user processor 2221-22232, respectively.
Referring to FIGS. 3A and 3B, the first input mapping unit 218 is arranged for dynamically mapping digital data in the data flows Da1-Da32 and pilot or diagnostic data in the data flow XZ and can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA). The first input mapping unit 218 can perform time-domain demultiplexing (TDDM), frequency-division/domain demultiplexing (FDDM) or combinations of FDDM/TDDM techniques, to map digital data in the data flows Da1-Da32 and the pilot or diagnostic data in the data flow XZ. The pilot or diagnostic signal XZ may have a single frequency and fixed amplitude. Alternatively, the pilot or diagnostic signal XZ could change based on time or could be any signal known by the passive optical network (PON). In contrast, the extraneous signals Da1-Da32 are unknown by the passive optical network and input into the passive optical network from an extraneous system. In this embodiment, the first input mapping unit 218 may include thirty-three time-domain demultiplexers 2181-21833 each allocating digital data in a corresponding received one of the data flows Da1-Da32 and XZ into the corresponding number of pieces of digital electronic data in corresponding ones of 128 data flows Df1-Df128 based on the corresponding number of respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”. For example, the time-domain demultiplexer 2181 may allocate the received digital data in the data flow Da1 into thirty-two pieces of digital data in the thirty-two respective data flows Df1-Df32 based on thirty-two respective non-overlapped time slots ta11-ta132. For more elaboration, the digital data in the data flow Df1 output from the time-domain demultiplexer 2181 may be the digital data, in the data flow Da1, arriving at the time-domain demultiplexer 2181 at the time slot ta11. The digital data in the data flow Df2 output from the time-domain demultiplexer 2181 may be the digital data, in the data flow Da1, arriving at the time-domain demultiplexer 2181 at the time slot ta12. Other situations can be considered in a similar way.
Alternatively, the thirty-three time-domain demultiplexers 2181-21833 may be replaced with thirty-three respective frequency-domain demultiplexers each allocating digital data in a corresponding received one of the data flows Da1-Da32 and XZ into the corresponding number of pieces of digital electronic data in corresponding ones of 128 data flows Df1-Df128 based on the corresponding number of respective non-overlapped frequency spectrums. For example, the frequency-domain demultiplexer 2181 may allocate the received digital data in the data flow Da1 into thirty-two pieces of digital data in the thirty-two respective data flows Df1-Df32 based on thirty-two respective non-overlapped frequency spectrums fa11-fa132. For more elaboration, the digital data in the data flow Df1 output from the frequency-domain demultiplexer 2181 may be the digital data in the data flow Da1 at the frequency spectrum fa11. The digital data in the data flow Df2 output from the frequency-domain demultiplexer 2181 may be the digital data in the data flow Da1 at the frequency spectrum fa12. Other situations can be considered in a similar way.
The digital data in each of the data flows Da1-Da32 and XZ can be allocated into the various number of pieces of data in accordance with data volume of the digital data to be transferred. The larger the data volume of the digital data to be transferred in one of the data flows Da1-Da32 and XZ, the larger number of pieces of data the digital data to be transferred in one of the data flows Da1-Da32 and XZ can be allocated into. In this embodiment, currently, the data volume of the digital data to be transferred in the data flow Da1 is larger than that in the data flow Da2, so the digital data in the data flow Da1 are allocated into the larger number of pieces of data than the digital data in the data flow Da2 are allocated, wherein the digital data in the data flow Da1 are allocated into thirty-two pieces of data in the data flows Df1-Df32, and the digital data in the data flow Da2 are allocated into sixteen pieces of data in the data flows Df33-Df48. At the next time point, if the data volume of the digital data to be transferred in the data flow Da1 is less than that in the data flow Da2, the digital data in the data flow Da1 can be allocated into the smaller number of pieces of data than the digital data in the data flow Da2 are allocated.
Alternatively, the digital data in each of the data flows Da1-Da32 and XZ can be allocated into the various number of pieces of data in accordance with user's subscription for a specific data flow rate.
Referring to FIGS. 3A and 3B, the number of pieces of data, into which the digital data in each of the data flows Da1-Da32 and XZ are allocated, can be altered or controlled by the controller 220. The controller 220 also synchronously alters or controls mapping of each second output mapping unit 240 in the thirty-two user processor 2221-22232, that is the controller 220 can dynamically and synchronously alter or control the input mapping of the central office processor 210 and the output mapping of the user processors 2221-22232, such that the mapping of the first input mapping unit 218 is correspondent to that of the second output mapping unit 240 in each of the thirty-two user processor 2221-22232. Thereby, the digital data in the data flows Da1-Da32 and XZ can efficiently share the resource or bandwidth of the passive optical network 200. The resource or bandwidth of the passive optical network 200 for the digital data in the data flows Da1-Da32 and XZ can be dynamically controlled or altered.
Referring to FIG. 3B, the first wave-front multiplexer 212 performs the above wave-front multiplexing transform to process 128 input signals, carrying 128 respective pieces of digital data in the respective data flows Df1-Df128, into 128 linear combinations in the respective data flows Dg1-Dg128, each combining all of the input signals multiplied by respective weightings, which can refer to the description illustrated in FIGS. 1A, 1B and 1C. In this case, the number of H is equal to 128. The first wave-front multiplexer 212 may include 128*128 computing units (CU) and 128 summing processors (SP). The computing units (CU) form a processor array with 128 rows and 128 columns. The 128 input digital signals Df1-Df128 can be received by the computing units (CU) in the respective 128 columns in the processor array. Upon receiving the input digital signals Df1-Df128, each of the computing units (CU) independently weights or multiplies its received signal by a weighting value, to generate a weighted signal. The 128 summing processors (SP) can output 128 digital signals Dg1-Dg128 each combining the weighted signals output from the computing units (CU) in a corresponding one of the 128 rows in the processor array.
The first output mapping unit 224 can receive digital electronic data in the data flows Dg1-Dg128 output from the first wave-front multiplexer 212, wherein the first output mapping unit 224 comprises thirty-two 4-to-1 time-domain multiplexer (TDM) 2241-22432, each combining four received corresponding pieces of digital data in respective four of the data flows Dg1-Dg128 into digital data in corresponding one of the thirty-two data flows Dv1-Dv32 based on four respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For example, the time-domain multiplexer 2241 may combine or integrate the four received pieces of digital electronic data in the respective four data flows Dg1-Dg4 into a piece of digital data in the data flow Dv1 based on four respective non-overlapped time slots tb11-tb14. For more elaboration, the digital data in the data flow Dv1 output from the time-domain multiplexer 2241 at the time slot tb11 may be the digital data in the data flow Dg1, the digital data in the data flow Dv1 output from the time-domain multiplexer 2241 at the time slot tb12 may be the digital data in the data flow Dg2, the digital data in the data flow Dv1 output from the time-domain multiplexer 2241 at the time slot tb13 may be the digital data in the data flow Dg3 and the digital data in the data flow Dv1 output from the time-domain multiplexer 2241 at the time slot tb14 may be the digital data in the data flow Dg4. Other situations can be considered in a similar way.
Alternatively, the thirty-two time-domain multiplexers 2241-22432 may be replaced with thirty-two respective 4-to-1 frequency-domain multiplexers each combining four received corresponding pieces of digital electronic data in respective four of the data flows Dg1-Dg128 into digital data in corresponding one of the thirty-two data flows Dv1-Dv32 based on four respective non-overlapped frequency spectrums. For example, the 4-to-1 frequency-domain multiplexer 2241 may combine or integrate the four received pieces of digital data in the respective four data flows Dg1-Dg4 into a piece of digital data in the data flow Dv1 based on four respective non-overlapped frequency slots fb11-fb14. For more elaboration, the digital data in the data flow Dv1 output from the frequency-domain multiplexer 2241 at the frequency spectrum fb11 may be the digital data in the data flow Dg1, the digital data in the data flow Dv1 output from the frequency-domain multiplexer 2241 at the frequency spectrum fb12 may be the digital data in the data flow Dg2, the digital data in the data flow Dv1 output from the frequency-domain multiplexer 2241 at the frequency spectrum fb13 may be the digital data in the data flow Dg3 and the digital data in the data flow Dv1 output from the frequency-domain multiplexer 2241 at the frequency spectrum fb14 may be the digital data in the data flow Dg4. Other situations can be considered in a similar way.
Referring to FIGS. 3A and 3B, the number of pieces of data, which are combined into a corresponding one of the data flows Dv1-Dv32, can also be altered or controlled by the controller 220. The controller 220 also synchronously alters or controls mapping of each second input mapping unit 234 in the thirty-two user processor 2221-22232, that is the controller 220 can dynamically and synchronously alter or control the output mapping of the central office processor 210 and the input mapping of the user processors 2221-22232, such that the mapping of the first output mapping unit 224 is correspondent to that of the second input mapping unit 234 in each of the thirty-two user processor 2221-22232.
Referring to FIG. 3B, the optical line terminal (OLT) 202 comprises a time-domain multiplexer (TDM) 226 and an optical laser device 228 connected to the time-domain multiplexer (TDM) 226, wherein the optical laser device 228 is at the downstream side of the time-domain multiplexer (TDM) 226. The time-domain multiplexer (TDM) 226 can receive digital electronic data in the data flows Dv1-Dv32 output from the first output mapping unit 224 of the central office processor 210. The time-domain multiplexer 226 may combine or integrate the thirty-two received pieces of digital electronic data in the respective thirty-two data flows Dv1-Dv32 into a piece of digital electronic data in the data flow Dp based on thirty-two respective non-overlapped time slots tc1-tc32, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For more elaboration, the digital electronic data in the data flow Dp output from the time-domain multiplexer 226 at the time slot tc1 may be the digital electronic data in the data flow Dv1. The digital electronic data in the data flow Dp output from the time-domain multiplexer 226 at the time slot tc2 may be the digital electronic data in the data flow Dv2. Other situations can be considered in a similar way.
Alternatively, the time-domain multiplexer (TDM) 226 may be replaced with a frequency-domain multiplexer combining or integrating the thirty-two received pieces of digital electronic data in the respective thirty-two data flows Dv1-Dv32 into a piece of digital electronic data in the data flow Dp based on thirty-two respective non-overlapped frequency spectrums fc1-fc32. For more elaboration, the digital electronic data in the data flow Dp output from the frequency-domain multiplexer 226 at the frequency spectrum fc1 may be the digital electronic data in the data flow Dv1. The digital electronic data in the data flow Dp output from the frequency-domain multiplexer 226 at the frequency spectrum fc2 may be the digital electronic data in the data flow Dv2. Other situations can be considered in a similar way.
Referring to FIGS. 3A and 3B, the optical laser device 228 can transform the electronic digital electronic data in the data flow Dp into an optical signal Do, wherein the optical signal Do can be output from the optical laser device 228 to the optical transferring device 204 via the optical fiber 207. In this embodiment, the optical transferring device 204 serves as an optical splitter (OS). The optical signal Do can be split to thirty-two optical signals Do1-Do32 by the optical transferring device 204, wherein each of the optical signals Do1-Do32 is substantially equivalent to the optical signal Do. The thirty-two split optical signals Do1-Do32 can be transmitted to thirty-two optical network units (ONU) 2061-20632 via the optical fibers 208, respectively.
Referring to FIGS. 3A and 3C, the optical network units (ONU) 2061-20632 have the same architecture as one another and each include an optical signal receiver 230 and a time-domain demultiplexer (TDDM) 238. One of the thirty-two optical network units (ONU) 2061-20632 is shown in detail in FIGS. 3A and 3C. With regards to each of the optical network units (ONU) 2061-20632, the optical signal receivers 230 can transform a corresponding received one of the optical signals Do1-Do32 into electronic digital electronic data Dm to be transmitted to the time-domain demultiplexer (TDDM) 238. Each of the time-domain demultiplexer (TDDM) 238 can allocate the received electronic digital electronic data Dm into thirty-two pieces of digital electronic data in thirty-two respective data flows Dj1-Dj32 based on thirty-two respective non-overlapped time slots td1-td32, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”. For more elaboration, the digital electronic data in the data flow Dj1 output from the time-domain demultiplexer 238 may be the digital electronic data Dm arriving at the time-domain demultiplexer 238 at the time slot td1. The digital electronic data in the data flow Dj2 output from the time-domain demultiplexer 238 may be the digital electronic data Dm arriving at the time-domain demultiplexer 238 at the time slot td2. Other situations can be considered in a similar way.
Alternatively, the time-domain demultiplexer 238 may be replaced with a frequency-domain demultiplexer allocating the received electronic digital electronic data Dm into thirty-two pieces of digital electronic data in thirty-two respective data flows Dj1-Dj32 based on thirty-two respective non-overlapped frequency spectrums fd1-fd32. For more elaboration, the digital electronic data in the data flow Dj1 output from the frequency-domain demultiplexer 238 may be the digital electronic data Dm at the frequency spectrum fd1. The digital electronic data in the data flow Dj2 output from the frequency-domain demultiplexer 238 may be the digital electronic data Dm at the frequency spectrum fd2. Other situations can be considered in a similar way.
When the device 226 of the optical line terminal (OLT) 202 is the above-mentioned time-domain multiplexer, the device 238 in each of the optical network units (ONU) 2061-20632 can be the above-mentioned time-domain demultiplexer. When the device 226 of the optical line terminal (OLT) 202 is the above-mentioned frequency-domain multiplexer, the device 238 in each of the optical network units (ONU) 2061-20632 can be the above-mentioned frequency-domain demultiplexer. The thirty-two pieces of digital electronic data in the data flows Dj1-Dj32 are substantially equivalent to the thirty-two pieces of digital electronic data in the data flows Dv1-Dv32, respectively, that is, the data flows Dj1-Dj32 carry substantially the same information as the respective data flows Dv1-Dv32 carry.
Referring to FIGS. 3A and 3C, the user processors 2221-22232 have the same architecture as one another and each include a second input mapping unit 234 at a downstream side of a corresponding one of the optical network units (ONU) 2061-20632, a first equalization processor 231 at a downstream side of the second input mapping unit 234, a first wave-front demultiplexer 232 at a downstream side of the first equalization processor 231, a second output mapping unit 240 at a downstream side of the first wave-front demultiplexer 232, a filter 244 at a downstream side of the second output mapping unit 240, a first optimizer 235 arranged between outputs of the second output mapping unit 240 and the first equalization processor 231 and a sub-controller 250 configured to control or alter the mapping of the second output mapping unit 240 and/or the mapping of the second input mapping unit 234. One of the thirty-two user processors 2221-22232 is shown in detail in FIGS. 3A and 3C.
Referring to FIG. 3C, the second input mapping unit 234 can receive digital electronic data in the data flows Dj1 ̃Dj32 output from a corresponding one of the optical network units (ONU) 2061-20632, wherein the second input mapping unit 234 comprises thirty-two 1-to-4 time-domain demultiplexer (TDDM) 2341-23432, each allocating digital electronic data in a corresponding received one of the data flows Dj1-Dj32 into four pieces of digital electronic data in corresponding four of 128 data flows Dr1-Dr128 based on four respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”. For example, the time-domain demultiplexer 2341 may allocate the received digital electronic data in the data flow Dj1 into four pieces of digital electronic data in the four respective data flows Dr1-Dr4 based on four respective non-overlapped time slots te11-te14. For more elaboration, the digital electronic data in the data flow Dr1 output from the time-domain demultiplexer 2341 may be the digital electronic data, in the data flow Dj1, arriving at the time-domain demultiplexer 2341 at the time slot te11, the digital electronic data in the data flow Dr2 output from the time-domain demultiplexer 2341 may be the digital electronic data, in the data flow arriving at the time-domain demultiplexer 2341 at the time slot te12, the digital electronic data in the data flow Dr3 output from the time-domain demultiplexer 2341 may be the digital electronic data, in the data flow Dj1, arriving at the time-domain demultiplexer 2341 at the time slot te13, and the digital electronic data in the data flow Dr4 output from the time-domain demultiplexer 2341 may be the digital electronic data, in the data flow Dj1, arriving at the time-domain demultiplexer 2341 at the time slot te14. Other situations can be considered in a similar way.
Alternatively, the thirty-two time-domain demultiplexers 2341-23432 may be replaced with thirty-two respective 1-to-4 frequency-domain demultiplexers each allocating digital electronic data in a corresponding received one of the data flows Dj1-Dj32 into four pieces of digital electronic data in corresponding four of 128 data flows Dr1-Dr128 based on four respective non-overlapped frequency spectrums. For example, the frequency-domain demultiplexer 2341 may allocate the received digital electronic data in the data flow Dj1 into four pieces of digital electronic data in the four respective data flows Dr1-Dr4 based on four respective non-overlapped frequency spectrums fe11-fe14. For more elaboration, the digital electronic data in the data flow Dr1 output from the frequency-domain demultiplexer 2341 may be the digital electronic data in the data flow Dj1 at the frequency spectrum fe11, the digital electronic data in the data flow Dr2 output from the frequency-domain demultiplexer 2341 may be the digital electronic data in the data flow Dj1 at the frequency spectrum fe12, the digital electronic data in the data flow Dr3 output from the frequency-domain demultiplexer 2341 may be the digital electronic data in the data flow Dj1 at the frequency spectrum fe13, and the digital electronic data in the data flow Dr4 output from the frequency-domain demultiplexer 2341 may be the digital electronic data in the data flow Dj1 at the frequency spectrum fe14. Other situations can be considered in a similar way.
When the devices 2241-22432 of the first output mapping unit 224 are the above-mentioned time-domain multiplexers, the devices 2341-23432 of the second input mapping unit 234 in each of the user processors 2221-22232 can be the above-mentioned time-domain demultiplexers. When the devices 2241-22432 of the first output mapping unit 224 are the above-mentioned frequency-domain multiplexers, the devices 2341-23432 of the second input mapping unit 234 in each of the user processors 2221-22232 can be the above-mentioned frequency-domain demultiplexers. The 128 pieces of digital electronic data in the data flows Dr1-Dr128 are substantially equivalent to the 128 pieces of digital electronic data in the data flows Dg1-Dg128, respectively, that is, the data flows Dr1-Dr128 carry substantially the same information as the respective data flows Dg1-Dg128 carry.
Referring to FIG. 3C, the sub-controllers 250 of the user processors 2221-22232 are controlled by the controller 220 of the central office processor 210 and can alter or control the mapping of the second input mapping units 234 of the user processors 2221-22232, respectively. The mapping of the second input mapping unit 234 in each of the thirty-two user processor 2221-22232 is correspondent to that of the first output mapping unit 224 in the central office processor 210, that is, the number of pieces of digital electronic data in the input data flows, e.g. Dg1-Dg4, that are mapped, by the first output mapping unit 224, to be combined into a specific piece of digital electronic data in the output data flow, e.g. Dv1, can be substantially the same as the number of pieces of digital electronic data in the output data flows, e.g. Dr1-Dr4, into which the digital electronic data in the input data flow, e.g. Dj1, substantially equivalent to the specific piece of digital electronic data in the output data flow, e.g. Dv1, from the first output mapping unit 224, are mapped, by the second input mapping unit 234 in each of the user processors 2221-22232, to be allocated.
For instance, when the time-domain or frequency-domain multiplexer 2241 of the first output mapping unit 224, as illustrated in FIG. 3B, is mapped to combine the four pieces of digital electronic data in the data flows Dg1-Dg4 into the digital electronic data in the data flow Dv1 based on the four respective non-overlapped time slots tb11-tb14 or frequency spectrums fb11-fb14, the time-domain or frequency-domain multiplexer 2341 in each of the user processors 2221-22232, complementary to the time-domain or frequency-domain demultiplexer 2241, as illustrated in FIG. 3C, can be mapped to allocate the input digital electronic data in the data flow Dj1 into the four pieces of digital electronic data in the data flows Dr1-Dr4, which are substantially equivalent to the four pieces of digital electronic data in the data flows Dg1-Dg4 respectively, based on the four respective non-overlapped time slots te11-te14 or frequency spectrums fe11-fe14. The time slots tb11-tb14 may have substantially the same time interval or period as the time slots te11-te14, respectively. For example, the time slot te11 may have substantially the same time interval or period as the time slot tb11. The time slot te14 may have substantially the same time interval or period as the time slot tb14. Alternatively, all of the time slots te11-te14 and tb11-tb14 may have substantially the same time interval or period. The frequency spectrums fb11-fb14 may have substantially the same frequency bandwidth as the frequency spectrums fe11-fe14, respectively. For example, the frequency spectrum fe11 may have substantially the same frequency bandwidth as the frequency spectrum fb11. The frequency spectrum fe14 may have substantially the same frequency bandwidth as the frequency spectrum fb14. Alternatively, all of the frequency spectrums fe11-fe14 and fb11-fb14 may have substantially the same frequency bandwidth.
Referring to FIG. 3C, the digital electronic data in the data flows Dr1-Dr128 can be transmitted in parallel to the first equalization processor 231 through, e.g., 128 parallel signal paths, 128 parallel wireless channels, or 128 parallel physical channels. The first equalization processor 231 can weight or multiply each of the 128 input signals, i.e. the digital electronic data in the data flows Dr1-Dr128, by a corresponding equalizing weight, which can refer to the illustration in FIG. 1B, so as to create 128 equalized signals, i.e. the digital electronic data in the data flows De1-De128, respectively. The first equalization processor 231 can compensate unbalanced amplitudes, unbalanced phases and/or unbalanced time-delays among the digital electronic data in the data flows Dr1-Dr128. The equalizing weights can be updated by the first optimizer 235 based on calculation of cost functions in accordance with a cost minimization algorithm, such as steepest descent method, as mentioned above. The first equalization processor 231 and first optimizer 235 can perform the above-mentioned equalizing and optimizing process, which can refer to the illustration in FIG. 1B.
Referring to FIG. 3C, upon receiving the digital electronic data in the data flows De1-De128, the first wave-front demultiplexer 232 performs the above wave-front demultiplexing transformation, which can refer to the illustration in FIGS. 1A-1D, to process the equalized signals, i.e. the digital electronic data in the data flows De1-De128, into multiple linear combinations, each combining all of the 128 equalized signals, i.e. the digital electronic data in the data flows De1-De128, multiplied by 128 respective weightings, represented by the digital electronic data in the respective data flows Di1-Di128 output in parallel from the first wave-front demultiplexer 232 to the second output mapping unit 240. The 128 pieces of digital electronic data in the data flows Di1-Di128 are substantially equivalent to the 128 pieces of digital electronic data in the data flows Df1-Df128, respectively, that is, the data flows Di1-Di128 carry substantially the same information as the respective data flows Df1-Df128 carry.
Referring to FIG. 3C, the second output mapping unit 240 is arranged for dynamically mapping the digital electronic data in the data flows Di1-Di128 and can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA). The second output mapping unit 240 can perform time-domain multiplexing (TDM), frequency-division/domain multiplexing (FDM) or combinations of FDM/TDM techniques, to map the digital electronic data in the data flows Di1-Di128. In this embodiment, the second output mapping unit 240 may include thirty-three time-domain multiplexers (TDM) 2401-24033 each combining the corresponding number of the received pieces of digital electronic data in the corresponding ones of the data flows Di1-Di128 into a piece of digital electronic data in corresponding one of the thirty-three data flows Dn1-Dn33 based on the corresponding number of respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For example, the time-domain multiplexer 2401 may combine the thirty-two received pieces of digital electronic data in the thirty-two data flows Di1-Di32 into a piece of digital electronic data in the data flow Dn1 based on thirty-two respective non-overlapped time slots tf11-tf132. For more elaboration, the digital electronic data in the data flow Dn1 output from the time-domain multiplexer 2401 at the time slot tf11 may be the digital electronic data in the data flow Di1. The digital electronic data in the data flow Dra output from the time-domain multiplexer 2401 at the time slot tf12 may be the digital electronic data in the data flow Di2. The digital electronic data in the data flow Dn1 output from the time-domain multiplexer 2401 at the time slot tf132 may be the digital electronic data in the data flow Di32. Other situations can be considered in a similar way.
Alternatively, the thirty-three time-domain multiplexers 2401-24033 may be replaced with thirty-three respective frequency-domain multiplexers each combining the corresponding number of the received pieces of digital electronic data in the corresponding ones of the data flows Di1-Di128 into a piece of digital electronic data in corresponding one of the thirty-three data flows Dn1-Dn33 based on the corresponding number of respective non-overlapped frequency spectrums. For example, the frequency-domain multiplexer 2401 may combine the thirty-two received pieces of digital electronic data in the thirty-two data flows Di1-Di32 into a piece of digital electronic data in the data flow Dn1 based on thirty-two respective non-overlapped frequency spectrum ff11-ff132. For more elaboration, the digital electronic data in the data flow Dn1 output from the frequency-domain multiplexer 2401 at the frequency spectrum ff11 may be the digital electronic data in the data flow Di1. The digital electronic data in the data flow Dn1 output from the frequency-domain multiplexer 2401 at the frequency spectrum ff12 may be the digital electronic data in the data flow Di2. The digital electronic data in the data flow Dn1 output from the frequency-domain multiplexer 2401 at the frequency spectrum ff132 may be the digital electronic data in the data flow Di32. Other situations can be considered in a similar way.
When the devices 2181-21833 of the first input mapping unit 218 are the above-mentioned time-domain demultiplexers, the devices 2401-24033 of the second output mapping unit 240 in each of the user processors 2221-22232 can be the above-mentioned time-domain multiplexers. When the devices 2181-21833 of the first input mapping unit 218 are the above-mentioned frequency-domain demultiplexers, the devices 2401-24033 of the second output mapping unit 240 in each of the user processors 2221-22232 can be the above-mentioned frequency-domain multiplexers.
Thereby, the digital electronic data in the data flows Dn1-Dn33 output from the second output mapping unit 240 can be substantially equivalent to the digital electronic data in the data flows Da1-Da32 and XZ injected to the first input mapping unit 218, respectively, that is, the data flows Dn1-Dn33 carry substantially the same information as the respective data flows Da1-Da32 and XZ carry.
Referring to FIG. 3C, in the equalizing and optimizing process, one (F1) of the cost functions may observe the change between the known diagnostic data, which is carried by the diagnostic or pilot signal XZ, and the digital electronic data in the data flow Dn33 received by the first optimizer 235. Others (F2) of the cost functions may be based on observations among the signals Dn1-Dn33. More specifically, the cost functions (F2) may be related to cross-correlation between each two of the signals Dn1-Dn33 received by the first optimizer 235. In the equalizing and optimizing process, the first optimizer 235 is configured to calculate a total cost based on the sum of all of the cost functions (F1) and (F2) and then compare the total cost with a predetermined cost threshold. When the total cost is verified to be greater than the predetermined cost threshold, the first optimizer 235 is configured to calculate a variation in the total cost in response to perturbations on the equalizing weights buffered in the first equalization processor 231 or to measure each gradient of the total cost with respect to the equalizing weights buffered in the first equalization processor 231. Based on the calculated variation or measured gradients, the first optimizer 235 creates updated equalizing weights, based on a cost minimization algorithm, such as steepest descent method, to be sent to the first equalization processor 231 and to replace current ones buffered in the first equalization processor 231 in the next scheduled clock cycle. Thereby, the equalizing weights buffered in the first equalization processor 231 can be updated. The first optimizer 235 is configured to stop the equalizing and optimizing process when the total cost is verified to be less than the predetermined cost threshold.
Referring to FIG. 3C, the filter 244 can filter one of the thirty-two pieces of digital electronic data in the respective data flows Dn1-Dn32. For example, the filter 244 of the user processor 2221 can filter the digital electronic data in the data flow Dn1. The filter 244 of the user processor 2222 can filter the digital electronic data in the data flow Dn2. The filter 244 of the user processor 22231 can filter the digital electronic data in the data flow Dn31. The filter 244 of the user processor 22232 can filter the digital electronic data in the data flow Dn32.
Referring to FIG. 3C, the sub-controllers 250 of the user processors 2221-22232 are controlled by the controller 220 of the central office processor 210 and can alter or control the mapping of the second output mapping units 240 of the user processors 2221-22232, respectively. The mapping of the second output mapping unit 240 in each of the thirty-two user processor 2221-22232 is correspondent to that of the first input mapping unit 218 in the central office processor 210, that is, the number of specific pieces of digital electronic data in the output data flows, e.g. Df1-Df32, into which the digital electronic data in the input data flow, e.g. Da1 are mapped, by the first input mapping unit 218, to be allocated, can be the same as the number of pieces of digital electronic data in the input data flows, e.g. Di1-Di32, substantially equivalent to the specific pieces of digital electronic data in the respective output data flows, e.g. Df1-Df32 from the first input mapping unit 218, that are mapped, by the second output mapping unit 240 in each of the user processors 2221-22232, to be combined into a piece of digital electronic data in the output data flow, e.g. Dn1.
For instance, when the time-domain or frequency-domain demultiplexer 2181 of the first input mapping unit 218, as illustrated in FIG. 3B, is mapped to allocate the input digital electronic data in the data flow Da1 into the thirty-two pieces of digital electronic data in the data flows Df1-Df32 based on the thirty-two respective non-overlapped time slots ta11-ta132 or frequency spectrums fa11-fa132, the time-domain or frequency-domain multiplexer 2401 in each of the user processors 2221-22232, complementary to the time-domain or frequency-domain demultiplexer 2181, as illustrated in FIG. 3C, can be mapped to combine the thirty-two pieces of digital electronic data in the data flows Di1-Di32, which are substantially equivalent to the thirty-two pieces of digital electronic data in the data flows Df1-Df32 respectively, into the digital electronic data in the data flow Dn1 based on the thirty-two respective non-overlapped time slots tf11-tf132 or frequency spectrums ff11-ff132. The time slots ta11-ta132 may have substantially the same time interval or period as the time slots tf11-tf132, respectively. For example, the time slot tf11 may have substantially the same time interval or period as the time slot ta11. The time slot tf132 may have substantially the same time interval or period as the time slot ta132. Alternatively, all of the time slots tf11-tf132 and ta11-ta132 may have substantially the same time interval or period. The frequency spectrums fa11-fa132 may have substantially the same frequency bandwidth as the frequency spectrums ff11-ff132, respectively. For example, the frequency spectrum ff11 may have substantially the same frequency bandwidth as the frequency spectrum fa11. The frequency spectrum ff132 may have substantially the same frequency bandwidth as the frequency spectrum fa132. Alternatively, all of the frequency spectrums ff11-ff132 and fa11-fa132 may have substantially the same frequency bandwidth.
For instance, when the time-domain or frequency-domain demultiplexer 2182 of the first input mapping unit 218, as illustrated in FIG. 3B, is mapped to allocate the input digital electronic data in the data flow Da2 into the sixteen pieces of digital electronic data in the data flows Df33-Df48 based on the sixteen respective non-overlapped time slots ta21-ta216 or frequency spectrums fa21-fa216, the time-domain or frequency-domain multiplexer 2402 in each of the user processors 2221-22232, complementary to the time-domain or frequency-domain demultiplexer 2182, as illustrated in FIG. 3C, can be mapped to combine the sixteen pieces of digital electronic data in the data flows Di33-Di48, which are substantially equivalent to the sixteen pieces of digital electronic data in the data flows Df33-Df48 respectively, into the digital electronic data in the data flow Dn2 based on the sixteen respective non-overlapped time slots tf21-tf216 or frequency spectrums ff21-ff216. The time slots ta21-ta216 may have substantially the same time interval or period as the time slots tf21-tf216, respectively. For example, the time slot tf21 may have substantially the same time interval or period as the time slot ta21. The time slot tf216 may have substantially the same time interval or period as the time slot ta216. Alternatively, all of the time slots tf21-tf216 and ta21-ta216 may have substantially the same time interval or period. The frequency spectrums fa21-fa216 may have substantially the same frequency bandwidth as the frequency spectrums ff21-ff216, respectively. For example, the frequency spectrum ff21 may have substantially the same frequency bandwidth as the frequency spectrum fa21. The frequency spectrum ff216 may have substantially the same frequency bandwidth as the frequency spectrum fa216. Alternatively, all of the frequency spectrums ff21-ff216 and fa21-fa216 may have substantially the same frequency bandwidth.
For instance, when the time-domain or frequency-domain demultiplexer 21833 of the first input mapping unit 218, as illustrated in FIG. 3B, is mapped to allocate the input digital electronic data in the data flow XZ into the two pieces of digital electronic data in the data flows Df127 and Df128 based on the two respective non-overlapped time slots ta331 and ta332 or frequency spectrums fa331 and fa332, the time-domain or frequency-domain multiplexer 24033 in each of the user processors 2221-22232, complementary to the time-domain demultiplexer 21833, as illustrated in FIG. 3C, can be mapped to combine the two pieces of digital electronic data in the data flows Di127 and Di128, which are substantially equivalent to the two pieces of digital electronic data in the data flows Df127 and Df128 respectively, into the digital electronic data in the data flow Dn33 based on the two respective non-overlapped time slots tf331 and tf332 or frequency spectrums ff331 and ff332. The time slots ta331 and ta332 may have substantially the same time interval or period as the time slots tf321 and tf322, respectively. For example, the time slot tf331 may have substantially the same time interval or period as the time slot ta331 and the time slot tf332 may have substantially the same time interval or period as the time slot ta332. Alternatively, all of the time slots tf331, tf332, ta331 and ta332 may have substantially the same time interval or period. The frequency spectrums fa331 and fa332 may have substantially the same frequency bandwidth as the frequency spectrums ff331 and ff332, respectively. For example, the frequency spectrum ff331 may have substantially the same frequency bandwidth as the frequency spectrum fa331. The frequency spectrum ff332 may have substantially the same frequency bandwidth as the frequency spectrum ff332. Alternatively, all of the frequency spectrums ff331, ff332, fa331 and fa332 may have substantially the same frequency bandwidth. Other situations can be considered in a similar way.
The controller 220 can dynamically and synchronously alter or control the input mapping of the central office processor 210 and the output mapping of the user processors 2221-22232 such that the mapping of the first input mapping unit 218 can be correspondent to that of the second output mapping unit 240 in each of the thirty-two user processor 2221-22232. Thereby, the digital electronic data in the data flows Da1-Da32 and XZ can efficiently share the resource or bandwidth of the passive optical network 200. The resource or bandwidth of the passive optical network 200 for the digital electronic data in the data flows Da1-Da32 and XZ can be dynamically controlled or altered.
In this embodiment, the first output mapping unit 224 of the central office processor 210, the time-domain or frequency-domain multiplexer 226 of the optical line terminal (OLT) 202, the optical laser device 228 of the optical line terminal (OLT) 202, the optical transferring device 204, the optical signal receiver 230 in one of the optical network units (ONU) 2061-20632, the time-domain demultiplexer 238 in one of the optical network units (ONU) 2061-20632 and the second input mapping unit 234 in one of the user processors 2221-22232 compose the data relaying system 998 as illustrated in FIGS. 1A and 1B and are arranged in sequence between the wave-front multiplexer 213 and the wave-front demultiplexer 232.
Upstream Dataflow Via Passive Optical Network (PON):
FIGS. 4A-4D are schematic diagrams showing upstream dataflow performed by a passive optical network (PON) system in combination with wave-front multiplexing and demultiplexing techniques according to an embodiment of the present invention.
Referring to FIGS. 4A-4C, the user processors 2221-22232 have the same architecture as one another and each further include a second wave-front multiplexer 212, which can refer to the wave-front multiplexer 212 as illustrated in FIGS. 1A and 1B, a third input mapping unit 260 at the upstream side of the wave-front multiplexer 212, a third output mapping unit 266 at the downstream side of the wave-front multiplexer 212 and a sub-controller 262 controlling the mapping of the third input mapping unit 260 and/or third output mapping unit 266. The user processors 2221-22232 may receive digital electronic data in thirty-two data flows Ua1-Ua32, respectively. Further, each of the user processor 2221-22232 may generate a pilot or diagnostic signal XY to be transmitted to the corresponding third input mapping unit 260 in each of the user processor 2221-22232. The pilot or diagnostic signal XY may have a single frequency and fixed amplitude. Alternatively, the pilot or diagnostic signal XY could change based on time or could be any signal known by the passive optical network (PON). In contrast, the extraneous signals Ua1-Ua32 are unknown by the passive optical network and input into the passive optical network from an extraneous system. Two of the thirty-two user processors 2221-22232 are shown in detail in FIGS. 4A-4C.
Referring to FIG. 4A, the third input mapping unit 260 in each of the user processors 2221-22232 is arranged for dynamically mapping digital electronic data in a corresponding one of the data flows Ua1-Ua32 and pilot or diagnostic data in the data flow XY. The third input mapping unit 260 can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA). The third input mapping unit 260 in each of the user processors 2221-22232 can perform time-domain demultiplexing (TDDM), frequency-division/domain demultiplexing (FDDM) or combinations of FDDM/TDDM techniques, to map digital electronic data in a corresponding one of the data flows Ua1-Ua32 and the pilot or diagnostic data in the data flow XY.
The third input mapping units 260 of the user processors 2221-22232 may have the same infrastructures as one another. In this embodiment, the third input mapping unit 260 may include thirty-three time-domain demultiplexers 2601-26033 arranged in parallel. Each of the third input mapping units 260 of the user processors 2221-22232 employs one of the thirty-three time-domain demultiplexers 2601-26033 to perform time-domain demultiplexing to the received one piece of digital electronic data in the data flows Ua1-Ua32, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”, but either two of the third input mapping units 260 of the user processors 2221-22232 employs different ones of the thirty-three time-domain demultiplexers 2601-26033 to perform time-domain demultiplexing to the different pieces of digital electronic data in data flows Ua1-Ua32.
For example, referring to FIG. 4B, with regards to the user processor 2221, the digital electronic data in the data stream Ua1 injected to the user processor 2221 can be allocated by the time-domain demultiplexer 2601 into thirty-two pieces of digital electronic data in the data flows Uf1-Uf32 based on thirty-two respective non-overlapped time slots tg11-tg132, the time-domain demultiplexers 2602-26032 can be coupled to the ground, and the pilot and diagnostic data can be allocated by the time-domain demultiplexer 26033 into two pieces of digital electronic data in the data flows Uf127 and Uf128 based on two respective non-overlapped time slots tg331 and tg332. For more elaboration, the digital electronic data in the data flow Uf1 output from the time-domain demultiplexer 2601 may be the digital electronic data, in the data flow Ua1, arriving at the time-domain demultiplexer 2601 at the time slot tg11. The digital electronic data in the data flow Uf2 output from the time-domain demultiplexer 2601 may be the digital electronic data, in the data flow Ua1, arriving at the time-domain demultiplexer 2601 at the time slot tg12. Other situations can be considered in a similar way. However, the time-domain demultiplexers 2601 in the other user processors 2222-22232, correspondent to the time-domain demultiplexer 2601 of the user processor 2221, are coupled to the ground.
For example, referring to FIG. 4C, with regards to the user processor 2222, the digital electronic data in the data stream Ua2 injected to the user processor 2222 can be allocated by the time-domain demultiplexer 2602 into sixteen pieces of digital electronic data in the data flows Uf33-Uf48 based on sixteen respective non-overlapped time slots tg21-tg216, the time-domain demultiplexers 2601 and 2603-26032 can be coupled to the ground, and the pilot and diagnostic data can be allocated by the time-domain demultiplexer 26033 into two pieces of digital electronic data in the data flows Uf127 and Uf128 based on two respective non-overlapped time slots tg331 and tg332. For more elaboration, the digital electronic data in the data flow Uf33 output from the time-domain demultiplexer 2602 may be the digital electronic data, in the data flow Ua2, arriving at the time-domain demultiplexer 2602 at the time slot tg21. The digital electronic data in the data flow Uf34 output from the time-domain demultiplexer 2602 may be the digital electronic data, in the data flow Ua2, arriving at the time-domain demultiplexer 2602 at the time slot tg22. Other situations can be considered in a similar way. However, the time-domain demultiplexers 2602 in the other user processors 2221 and 2223-22232, correspondent to the time-domain demultiplexer 2602 of the user processor 2222, are coupled to the ground.
Alternatively, the thirty-three time-domain demultiplexers 2601-26033 in each of the user processors 2221-22232 can be replaced with thirty-three frequency-domain demultiplexers performing frequency-domain demultiplexing to the received one piece of digital electronic data in the data flows Ua1-Ua32, but either two of the third input mapping units 260 of the user processors 2221-22232 employs different ones of the thirty-three frequency-domain demultiplexers 2601-26033 to perform frequency-domain demultiplexing to the different pieces of digital electronic data in data flows Ua1-Ua32.
For example, referring to FIG. 4B, with regards to the user processor 2221, the digital electronic data in the data stream Ua1 injected to the user processor 2221 can be allocated by the frequency-domain demultiplexer 2601 into thirty-two pieces of digital electronic data in the data flows Uf1-Uf32 based on thirty-two respective non-overlapped frequency spectrums fg11-fg132, the frequency-domain demultiplexers 2602-26032 can be coupled to the ground, and the pilot and diagnostic data can be allocated by the frequency-domain demultiplexer 26033 into two pieces of digital electronic data in the data flows Uf127 and Uf128 based on two respective non-overlapped time slots tg331 and tg332. For more elaboration, the digital electronic data in the data flow Uf1 output from the frequency-domain demultiplexer 2601 may be the digital electronic data in the data flow Ua1 at the frequency spectrum fg11. The digital electronic data in the data flow Uf2 output from the frequency-domain demultiplexer 2601 may be the digital electronic data in the data flow Ua1 at the frequency spectrum fg12. Other situations can be considered in a similar way. However, the frequency-domain demultiplexers 2601 in the other user processors 2222-22232, correspondent to the frequency-domain demultiplexer 2601 of the user processor 2221, are coupled to the ground.
For example, referring to FIG. 4C, with regards to the user processor 2222, the digital electronic data in the data stream Ua2 injected to the user processor 2222 can be allocated by the frequency-domain demultiplexer 2602 into sixteen pieces of digital electronic data in the data flows Uf33-Uf48 based on sixteen respective non-overlapped frequency spectrums fg21-fg216, the frequency-domain demultiplexers 2601 and 2603-26032 can be coupled to the ground, and the pilot and diagnostic data can be allocated by the frequency-domain demultiplexer 26033 into two pieces of digital electronic data in the data flows Uf127 and Uf128 based on two respective non-overlapped frequency spectrums fg331 and fg332. For more elaboration, the digital electronic data in the data flow Uf33 output from the frequency-domain demultiplexer 2602 may be the digital electronic data in the data flow Ua2 at the frequency spectrum fg21. The digital electronic data in the data flow Uf34 output from the frequency-domain demultiplexer 2602 may be the digital electronic data in the data flow Ua2 at the frequency spectrum fg22. Other situations can be considered in a similar way. However, the frequency-domain demultiplexers 2602 in the other user processors 2221 and 2223-22232, correspondent to the frequency-domain demultiplexer 2602 of the user processor 2222, are coupled to the ground.
Referring to FIGS. 4A-4C, with regards to each of the user processors 2221-22232, the second wave-front multiplexer 212 performs the above wave-front multiplexing transform to process 128 input signals, carrying 128 respective pieces of digital electronic data in the respective data flows Uf1-Uf128, into 128 linear combinations in the respective data flows Ug1-Ug128, each combining all of the input signals multiplied by respective weightings, which can refer to the description illustrated in FIGS. 1A, 1B and 1C. In this case, the number of H is equal to 128. The first wave-front multiplexer 212 may include 128*128 computing units (CU) and 128 summing processors (SP). The computing units (CU) form a processor array with 128 rows and 128 columns. The 128 input digital signals Uf1-Uf128 can be received by the computing units (CU) in the respective 128 columns in the processor array. Upon receiving the input digital signals Uf1-Uf128, each of the computing units (CU) independently weights or multiplies its received signal by a weighting value, to generate a weighted signal. The 128 summing processors (SP) can output 128 digital signals Ug1-Ug128 each combining the weighted signals output from the computing units (CU) in a corresponding one of the 128 rows in the processor array.
With regards to each of the user processors 2221-22232, the third output mapping unit 266 can receive digital electronic data in the data flows Ug1-Ug128 output from the first wave-front multiplexer 212, wherein the third output mapping unit 266 comprises thirty-two 4-to-1 time-domain multiplexers (TDM) 2661-26632, each combining four received corresponding pieces of digital electronic data in respective four of the data flows Ug1-Ug128 into a piece of digital electronic data in corresponding one of the thirty-two data flows Uv1-Uv32 based on four respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For example, with regards to the user processor 2221, referring to FIG. 4B, the time-domain multiplexer 2661 may combine or integrate the four received pieces of digital electronic data in the respective four data flows Ug1-Ug4 into a piece of digital electronic data in the data flow Uv1 based on four respective non-overlapped time slots th11-th14. For more elaboration, the digital electronic data in the data flow Uv1 output from the time-domain multiplexer 2661 at the time slot th11 may be the digital electronic data in the data flow Ug1, the digital electronic data in the data flow Uv1 output from the time-domain multiplexer 2661 at the time slot th12 may be the digital electronic data in the data flow Ug2, the digital electronic data in the data flow Uv1 output from the time-domain multiplexer 2661 at the time slot th13 may be the digital electronic data in the data flow Ug3 and the digital electronic data in the data flow Uv1 output from the time-domain multiplexer 2661 at the time slot th14 may be the digital electronic data in the data flow Ug4. Other situations can be considered in a similar way.
For example, with regards to the user processor 2222, referring to FIG. 4C, the time-domain multiplexer 2662 may combine or integrate the four received pieces of digital electronic data in the respective four data flows Ug5-Ug8 into a piece of digital electronic data in the data flow Uv2 based on four respective non-overlapped time slots th21-th24. For more elaboration, the digital electronic data in the data flow Uv2 output from the time-domain multiplexer 2662 at the time slot th21 may be the digital electronic data in the data flow Ug5, the digital electronic data in the data flow Uv2 output from the time-domain multiplexer 2662 at the time slot th22 may be the digital electronic data in the data flow Ug6, the digital electronic data in the data flow Uv2 output from the time-domain multiplexer 2662 at the time slot th23 may be the digital electronic data in the data flow Ug7 and the digital electronic data in the data flow Uv2 output from the time-domain multiplexer 2662 at the time slot th24 may be the digital electronic data in the data flow Ug8. Other situations can be considered in a similar way.
Alternatively, the thirty-two 4-to-1 time-domain multiplexers 2661-26632 can be replaced with thirty-two 4-to-1 frequency-domain multiplexers each combining four received corresponding pieces of digital electronic data in respective four of the data flows Ug1-Ug128 into a piece of digital electronic data in corresponding one of the thirty-two data flows Uv1-Uv32 based on four respective non-overlapped frequency spectrums. For example, with regards to the user processor 2221, referring to FIG. 4B, the frequency-domain multiplexer 2661 may combine or integrate the four received pieces of digital electronic data in the respective four data flows Ug1-Ug4 into a piece of digital electronic data in the data flow Uv1 based on four respective non-overlapped frequency spectrums fh11-fh14. For more elaboration, the digital electronic data in the data flow Uv1 output from the frequency-domain multiplexer 2661 at the frequency spectrum fh11 may be the digital electronic data in the data flow Ug1, the digital electronic data in the data flow Uv1 output from the frequency-domain multiplexer 2661 at the frequency spectrum fh12 may be the digital electronic data in the data flow Ug2, the digital electronic data in the data flow Uv1 output from the frequency-domain multiplexer 2661 at the frequency spectrum fh13 may be the digital electronic data in the data flow Ug3, and the digital electronic data in the data flow Uv1 output from the frequency-domain multiplexer 2661 at the frequency spectrum fh14 may be the digital electronic data in the data flow Ug4. Other situations can be considered in a similar way.
For example, with regards to the user processor 2222, referring to FIG. 4C, the frequency-domain multiplexer 2662 may combine or integrate the four received pieces of digital electronic data in the respective four data flows Ug5-Ug8 into a piece of digital electronic data in the data flow Uv2 based on four respective non-overlapped frequency spectrums fh21-fh24. For more elaboration, the digital electronic data in the data flow Uv2 output from the frequency-domain multiplexer 2662 at the frequency spectrum fh21 may be the digital electronic data in the data flow Ug5, the digital electronic data in the data flow Uv2 output from the frequency-domain multiplexer 2662 at the frequency spectrum fh22 may be the digital electronic data in the data flow Ug6, the digital electronic data in the data flow Uv2 output from the frequency-domain multiplexer 2662 at the frequency spectrum fh23 may be the digital electronic data in the data flow Ug7 and the digital electronic data in the data flow Uv2 output from the frequency-domain multiplexer 2662 at the frequency spectrum fh24 may be the digital electronic data in the data flow Ug8. Other situations can be considered in a similar way.
Referring to FIGS. 4A-4C, the optical network units (ONU) 2061-20632 have the same architecture as one another and each include a time-domain multiplexer (TDM) 278 receiving digital electronic data in the data flows Uv1-Uv32 output from the third output mapping unit 206 of the corresponding one of the user processors 2121-21232 and an optical laser device 280 at the downstream side of the time-domain multiplexer 278. Two of the thirty-two optical network units (ONU) 2061-20632 are shown in detail in FIGS. 4A-4C. With regards to each of the optical network units (ONU) 2061-20632, the time-domain multiplexer 278 may combine or integrate the thirty-two received pieces of digital electronic data in the respective thirty-two data flows Uv1-Uv32 into a piece of digital electronic data in the data flow Up based on thirty-two respective non-overlapped time slots ti1-ti32, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For more elaboration, the digital electronic data in the data flow Up output from the time-domain multiplexer 278 at the time slot ti1 may be the digital electronic data in the data flow Uv1. The digital electronic data in the data flow Up output from the time-domain multiplexer 278 at the time slot ti2 may be the digital electronic data in the data flow Uv2. Other situations can be considered in a similar way.
Alternatively, the time-domain multiplexer 278 may be replaced with a time-domain multiplexer combining or integrating the thirty-two received pieces of digital electronic data in the respective thirty-two data flows Uv1-Uv32 into a piece of digital electronic data in the data flow Up based on thirty-two respective non-overlapped frequency spectrums fi1-fi32. For more elaboration, the digital electronic data in the data flow Up output from the frequency-domain multiplexer 278 at the frequency spectrum fi1 may be the digital electronic data in the data flow Uv1. The digital electronic data in the data flow Up output from the frequency-domain multiplexer 278 at the frequency spectrum fi2 may be the digital electronic data in the data flow Uv2. Other situations can be considered in a similar way.
Referring to FIGS. 4A-4C, with regards to each of the thirty-two optical network units (ONU) 2061-20632, the optical laser device 280 can transform the electronic digital electronic data in the data flow Up into corresponding one of thirty-two optical signals Uo1-Uo32, wherein the thirty-two optical signals Do1-Uo32 can be output from the optical laser devices 228 of the respective optical network units (ONU) 2061-20632 to the optical transferring device 204 via the thirty-two respective optical fibers 208. In this embodiment, the optical transferring device 204 serves as an optical coupler. The optical signals Uo1-Uo32 can be combined into an optical signal Uo by the optical transferring device 204o. The combined optical signals Uo can be transmitted to the optical line terminal (OLT) 202 via the optical fiber 207.
The optical line terminal (OLT) 202 may further includes an optical signal receiver 286 receiving the optical signal Uo and a time-domain demultiplexer (TDDM) 288 at downstream side of the optical signal receiver 286. The optical signal receiver 286 can transform the optical signals Uo into electronic digital electronic data Um to be transmitted to the time-domain demultiplexer (TDDM) 288. The digital electronic data in the data flow Um is substantially equivalent to the combination of the digital electronic data in the data flows Up input to the optical laser devices 280 of all of the optical network units (ONU) 2061-20632, that is the data flow Um carries substantially the same information as the combination of the digital electronic data in the data flows Up input to the optical laser devices 280 of all of the optical network units (ONU) 2061-20632. The time-domain demultiplexer (TDDM) 288 can allocate the received electronic digital electronic data Um into thirty-two pieces of digital electronic data in thirty-two respective data flows Uj1-Uj32 based on thirty-two respective non-overlapped time slots tj1-tj32, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”. For more elaboration, the digital electronic data in the data flow Uj1 output from the time-domain demultiplexer 288 may be the digital electronic data Um arriving at the time-domain demultiplexer 288 at the time slot tj1, the digital electronic data in the data flow Uj2 output from the time-domain demultiplexer 288 may be the digital electronic data Um arriving at the time-domain demultiplexer 288 at the time slot tj2. Other situations can be considered in a similar way.
Alternatively, the time-domain demultiplexer 288 may be replaced with a frequency-domain demultiplexer allocating the received electronic digital electronic data Um into thirty-two pieces of digital electronic data in thirty-two respective data flows Uj1-Uj32 based on thirty-two respective non-overlapped frequency spectrums fj1-fj32. For more elaboration, the digital electronic data in the data flow Uj1 output from the time-domain demultiplexer 288 may be the digital electronic data Um at the frequency spectrum tj1. The digital electronic data in the data flow Uj2 output from the time-domain demultiplexer 288 may be the digital electronic data Um at the frequency spectrum fj2. Other situations can be considered in a similar way.
When the device 288 of the optical line terminal (OLT) 202 is the above-mentioned time-domain demultiplexer, the device 278 in each of the optical network units (ONU) 2061-20632 can be the above-mentioned time-domain multiplexer. When the device 288 of the optical line terminal (OLT) 202 is the above-mentioned frequency-domain demultiplexer, the device 278 in each of the optical network units (ONU) 2061-20632 can be the above-mentioned frequency-domain multiplexer. The thirty-two pieces of digital electronic data in the data flows Uj1-Uj32 are substantially equivalent to the combination of the digital electronic data in the respective data flows Uv1-Uv32 output from all of the user processors 2221-22232, that is, the data flows Uj1-Uj32 carry substantially the same information as the combination of the digital electronic data in the respective data flows Uv1-Uv32 output from all of the user processors 2221-22232. For example, the digital electronic data in the data flows Uj1 is substantially equivalent to the combination of the digital electronic data in the data flows Uv1 output from all of the user processors 2221-22232, that is, the data flows Uj1 carry substantially the same information as the combination of the digital electronic data in the data flows Uv1 output from all of the user processors 2221-22232. Referring to FIGS. 4A and 4D, the central office processor 210 includes a fourth input mapping unit 290 at a downstream side of the optical line terminal (OLT) 202, a second equalization processor 231 at a downstream side of the fourth input mapping unit 231, a second wave-front demultiplexer 232 at a downstream side of the second equalization processor 231, a fourth output mapping unit 296 at a downstream side of the second wave-front demultiplexer 232, a second optimizer 235 arranged between outputs of the fourth output mapping unit 296 and the second equalization processor 231 and a controller 272 configured to control or alter the mapping of the fourth output mapping unit 296 and third input mapping unit 260 and/or the mapping of the third output mapping unit 266 and fourth input mapping unit 290.
Referring to FIG. 4D, the fourth input mapping unit 290 can receive digital electronic data in the data flows Uj1-Uj32 output from the optical line terminal (OLT) 202, wherein the fourth input mapping unit 290 comprises thirty-two 1-to-4 time-domain demultiplexers (TDDM) 2901-29032, each allocating digital electronic data in a corresponding received one of the data flows Uj1-Uj32 into four pieces of digital electronic data in corresponding four of 128 data flows Ur1-Ur128 based on four respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain demultiplexer (TDDM)”. For example, the time-domain demultiplexer 2901 may allocate the received digital electronic data in the data flow Uj1 into four pieces of digital electronic data in the four respective data flows Ur1-Ur4 based on four respective non-overlapped time slots tk11-tk14. For more elaboration, the digital electronic data in the data flow Ur1 output from the time-domain demultiplexer 2901 may be the digital electronic data, in the data flow Uj1, arriving at the time-domain demultiplexer 2901 at the time slot tk11, the digital electronic data in the data flow Ur2 output from the time-domain demultiplexer 2901 may be the digital electronic data, in the data flow Uj1, arriving at the time-domain demultiplexer 2901 at the time slot tk12, the digital electronic data in the data flow Ur3 output from the time-domain demultiplexer 2901 may be the digital electronic data, in the data flow Uj1, arriving at the time-domain demultiplexer 2901 at the time slot tk13, and the digital electronic data in the data flow Ur4 output from the time-domain demultiplexer 2901 may be the digital electronic data, in the data flow Uj1, arriving at the time-domain demultiplexer 2901 at the time slot tk14. Other situations can be considered in a similar way.
Alternatively, the thirty-two 1-to-4 time-domain demultiplexer (TDDM) 2901-29032 may be replaced with thirty-two respective 1-to-4 frequency-domain demultiplexer each allocating digital electronic data in a corresponding received one of the data flows Uj1-Uj32 into four pieces of digital electronic data in corresponding four of 128 data flows Ur1-Ur128 based on four respective non-overlapped frequency spectrums. For example, the frequency-domain demultiplexer 2901 may allocate the received digital electronic data in the data flow Uj1 into four pieces of digital electronic data in the four respective data flows Ur1-Ur4 based on four respective non-overlapped frequency spectrums fk11-fk14. For more elaboration, the digital electronic data in the data flow Ur1 output from the frequency-domain demultiplexer 2901 may be the digital electronic data in the data flow Uj1 at the frequency spectrum fk11, the digital electronic data in the data flow Ur2 output from the frequency-domain demultiplexer 2901 may be the digital electronic data in the data flow Uj1 at the frequency spectrum fk12, the digital electronic data in the data flow Ur3 output from the frequency-domain demultiplexer 2901 may be the digital electronic data in the data flow Uj1 at the frequency spectrum fk13, and the digital electronic data in the data flow Ur4 output from the frequency-domain demultiplexer 2901 may be the digital electronic data in the data flow Uj1 at the frequency spectrum fk14. Other situations can be considered in a similar way.
When the devices 2901-29032 of the fourth input mapping unit 290 are the above-mentioned time-domain demultiplexers, the devices 2661-26632 of the third output mapping unit 266 in each of the user processors 2221-22232 can be the above-mentioned time-domain multiplexers. When the devices 2901-29032 of the fourth input mapping unit 290 are the above-mentioned frequency-domain demultiplexers, the devices 2661-26632 of the third output mapping unit 266 in each of the user processors 2221-22232 can be the above-mentioned frequency-domain multiplexers. The 128 pieces of digital electronic data in the data flows Ur1-Ur128 are substantially equivalent to the combination of the digital electronic data in the respective data flows Ug1-Ug128 input to the third input mapping units 266 in all of the user processors 2221-22232, that is, the data flows Ur1-Ur128 carry substantially the same information as the combination of the digital electronic data in the respective data flows Ug1-Ug128 input to the third input mapping units 266 in all of the user processors 2221-22232. For example, the digital electronic data in the data flows Ur1 is substantially equivalent to the combination of the digital electronic data in the data flows Ug1 input to the third input mapping units 266 in all of the user processors 2221-22232, that is, the data flows Ur1 carry substantially the same information as the combination of the digital electronic data in the data flows Ug1 input to the third input mapping units 266 in all of the user processors 2221-22232.
Referring to FIG. 4C, the controller 272 of the central office processor 210 can control the sub-controllers 262 in all of the user processors 2221-22232 and can alter or control the mapping of the fourth input mapping unit 290 of the central office processor 210. The mapping of the fourth input mapping unit 290 in the central office processor 210 is correspondent to that of the third output mapping unit 266 in each of the user processors 2221-22232, that is, the number of pieces of digital electronic data in the input data flows, e.g. Ug1-Ug4, that are mapped, by the third output mapping unit 266 in each of the user processors 2221-22232, to be combined into a specific piece of digital electronic data in the output data flow, e.g. Uv1, can be substantially the same as the number of pieces of digital electronic data in the output data flows, e.g. Ur1-Ur4, into which the digital electronic data in the input data flow, e.g. Uj1, substantially equivalent to the combination of the specific pieces of digital electronic data in the output data flow, e.g. Uv1, from the third output mapping unit 266, are mapped, by the fourth input mapping unit 290, to be allocated.
For instance, when the time-domain or frequency-domain multiplexer 2661 of the third output mapping unit 266 in each of the user processors 2221-22232, as illustrated in FIGS. 4B and 4C, is mapped to combine the four pieces of digital electronic data in the data flows Ug1-Ug4 into the digital electronic data in the data flow Uv1 based on the four respective non-overlapped time slots th11-th14 or frequency spectrums fh11-fh14, the time-domain or frequency-domain multiplexer 2901 in the central office processor 210, complementary to the time-domain or frequency-domain demultiplexer 2661 in each of the user processors 2221-22232, as illustrated in FIG. 4D, can be mapped to allocate the input digital electronic data in the data flow Uj1 into the four pieces of digital electronic data in the data flows Ur1-Ur4, which are substantially equivalent to the combination of the four respective pieces of digital electronic data in the respective data flows Ug1-Ug4 input to the third output mapping units 266 in the user processors 2221-22232, based on the four respective non-overlapped time slots tk11-tk14 or frequency spectrums fk11-fk14. The time slots th11-th14 may have substantially the same time interval or period as the time slots tk11-tk14, respectively. For example, the time slot tk11 may have substantially the same time interval or period as the time slot th11. The time slot tk14 may have substantially the same time interval or period as the time slot th14. Alternatively, all of the time slots tk11-tk14 and th11-th14 may have substantially the same time interval or period. The frequency spectrums fh11-fh14 may have substantially the same frequency bandwidth as the frequency spectrums fk11-fk14, respectively. For example, the frequency spectrum fk11 may have substantially the same frequency bandwidth as the frequency spectrum fh11. The frequency spectrum fk14 may have substantially the same frequency bandwidth as the frequency spectrum fh14. Alternatively, all of the frequency spectrums fk11-fk14 and fh11-fh14 may have substantially the same frequency bandwidth.
Referring to FIG. 4D, the digital electronic data in the data flows Ur1-Ur128 can be transmitted in parallel to the second equalization processor 231 through, e.g., 128 parallel signal paths, 128 parallel wireless channels, or 128 parallel physical channels. The second equalization processor 231 can weight or multiply each of the 128 input signals, i.e. the digital electronic data in the data flows Ur1-Ur128, by a corresponding equalizing weight, which can refer to the illustration in FIG. 1B, so as to create 128 equalized signals, i.e. the digital electronic data in the data flows Ue1-Ue128, respectively. The second equalization processor 231 can compensate unbalanced amplitudes, unbalanced phases and/or unbalanced time-delays among the digital electronic data in the data flows Ur1-Ur128. The equalizing weights can be updated by the second optimizer 235 based on calculation of cost functions in accordance with a cost minimization algorithm, such as steepest descent method, as mentioned above. The second equalization processor 231 and second optimizer 235 can perform the above-mentioned equalizing and optimizing process, which can refer to the illustration in FIG. 1B.
Referring to FIG. 4D, upon receiving the digital electronic data in the data flows Ue1-Ue128, the second wave-front demultiplexer 232 performs the above wave-front demultiplexing transformation, which can refer to the illustration in FIGS. 1A-1D, to process the equalized signals, i.e. the digital electronic data in the data flows Ue1-Ue128, into multiple linear combinations, each combining all of the 128 equalized signals, i.e. the digital electronic data in the data flows Ue1-Ue128, multiplied by 128 respective weightings, represented by the digital electronic data in the respective data flows Ui1-Ui128 output in parallel from the second wave-front demultiplexer 232 to the fourth output mapping unit 296. The 128 pieces of digital electronic data in the data flows Ui1-Ui128 are substantially equivalent to the 128 pieces of digital electronic data in the respective data flows Uf1-Uf128 associated with the thirty-two pieces of digital electronic data in the data flows Ua1-Ua32 received by the thirty-two respective user processors 2321-23232. For example, the thirty-two pieces of digital electronic data in the data flows Ui1-Ui32 are substantially equivalent to the thirty-two pieces of digital electronic data in the respective data flows Uf1-Uf32 associated with the digital electronic data in the data flow Ua1 received by the user processor 2321. The thirty-two pieces of digital electronic data in the data flows Ui1-Ui32 are substantially equivalent to the thirty-two pieces of digital electronic data in the respective data flows Uf1-Uf32 associated with the digital electronic data in the data flow Ua1 received by the user processor 2321 as seen in FIG. 4B. The sixteen pieces of digital electronic data in the data flows Ui33-Ui48 are substantially equivalent to the sixteen pieces of digital electronic data in the respective data flows Uf33-Uf48 associated with the digital electronic data in the data flow Ua2 received by the user processor 2322 as seen in FIG. 4C. Other situations can be considered in a similar way. The 128 pieces of digital electronic data in the data flows Ui1-Ui128 are substantially equivalent to the combination of the digital electronic data in the respective data flows Uf1-Uf128 input to the second wave-front multiplexers 212 in all of the user processors 2221-22232, that is, the data flows Ui1-Ui128 carry substantially the same information as the combination of the digital electronic data in the respective data flows Uf1-Uf128 input to the second wave-front multiplexers 212 in all of the user processors 2221-22232. For example, the digital electronic data in the data flows Ui1 is substantially equivalent to the combination of the digital electronic data in the data flows Uf1 input to the second wave-front multiplexers 212 in all of the user processors 2221-22232, that is, the data flows Ui1 carry substantially the same information as the combination of the digital electronic data in the data flows Uf1 input to the second wave-front multiplexers 212 in all of the user processors 2221-22232.
Referring to FIG. 4D, the fourth output mapping unit 296 is arranged for dynamically mapping the digital electronic data in the data flows Ui1-Ui128 and can be implemented digitally in software programming in a microprocessor, programmable application-specific integrated circuit (ASIC), and/or field-programmable gate array (FPGA). The fourth output mapping unit 296 can perform time-domain multiplexing (TDM), frequency-division/domain multiplexing (FDM) or combinations of FDM/TDM techniques, to map the digital electronic data in the data flows Ui1-Ui128. In this embodiment, the fourth output mapping unit 296 may include thirty-three time-domain multiplexers (TDM) 2961-29633 each combining the corresponding number of the received pieces of digital electronic data in the corresponding ones of the data flows Ui1-Ui128 into a piece of digital electronic data in corresponding one of the thirty-three data flows Un1-Un33 based on the corresponding number of respective non-overlapped time slots, which can refer to the above paragraphs in the section “Time-domain multiplexer (TDM)”. For example, the time-domain multiplexer 2961 may combine the thirty-two received pieces of digital electronic data in the thirty-two data flows Di1-Di32 into a piece of digital electronic data in the data flow Dn1 based on thirty-two respective non-overlapped time slots tm11-tm132. For more elaboration, the digital electronic data in the data flow Un1 output from the time-domain multiplexer 2961 at the time slot tm11 may be the digital electronic data in the data flow Ui1. The digital electronic data in the data flow Un1 output from the time-domain multiplexer 2961 at the time slot tm12 may be the digital electronic data in the data flow Ui2. The digital electronic data in the data flow Un1 output from the time-domain multiplexer 2961 at the time slot tm132 may be the digital electronic data in the data flow Ui32. Other situations can be considered in a similar way.
Alternatively, the thirty-three time-domain multiplexers 2961-29633 can be replaced with thirty-three respective frequency-domain multiplexers each combining the corresponding number of the received pieces of digital electronic data in the corresponding ones of the data flows Ui1-Ui128 into a piece of digital electronic data in corresponding one of the thirty-three data flows Un1-Un33 based on the corresponding number of respective non-overlapped frequency spectrums. For example, the frequency-domain multiplexer 2961 may combine the thirty-two received pieces of digital electronic data in the thirty-two data flows Di1-Di32 into a piece of digital electronic data in the data flow Dn1 based on thirty-two respective non-overlapped frequency spectrums fm11-fm132. For more elaboration, the digital electronic data in the data flow Un1 output from the frequency-domain multiplexer 2961 at the frequency spectrum fm11 may be the digital electronic data in the data flow Ui1. The digital electronic data in the data flow Un1 output from the frequency-domain multiplexer 2961 at the frequency spectrum fm12 may be the digital electronic data in the data flow Ui2. The digital electronic data in the data flow Un1 output from the frequency-domain multiplexer 2961 at the frequency spectrum fm132 may be the digital electronic data in the data flow Ui32. Other situations can be considered in a similar way.
When the devices 2961-29633 of the fourth output mapping unit 296 are the above-mentioned time-domain multiplexers, the devices 2601-26033 of the third input mapping unit 260 in each of the user processors 2221-22232 can be the above-mentioned time-domain demultiplexers. When the devices 2961-29633 of the fourth output mapping unit 296 are the above-mentioned frequency-domain multiplexers, the devices 2601-26033 of the third input mapping unit 260 in each of the user processors 2221-22232 can be the above-mentioned frequency-domain demultiplexers.
Thereby, the digital electronic data in the data flows Un1-Un32 output from the fourth output mapping unit 296 can be substantially equivalent to the digital electronic data in the data flows Ua1-Ua32 injected to the user processors 2221-22232, respectively, that is, the digital electronic data in the data flows Un1-Un32 output from the fourth output mapping unit 296 can carry substantially the same information as the digital electronic data in the respective data flows Ua1-Ua32 injected to the user processors 2221-22232. For example, the digital electronic data in the data flow Un1 output from the fourth output mapping unit 296 can be substantially equivalent to the digital electronic data in the data flow Ua1 injected to the user processor 2221, that is, the digital electronic data in the data flow Un1 output from the fourth output mapping unit 296 can carry substantially the same information as the digital electronic data in the data flow Ua1 injected to the user processor 2221. The digital electronic data in the data flow Un33 output from the fourth output mapping unit 296 can be substantially equivalent to the digital electronic data in the data flows XY input to the time-domain demultiplexers 26033 in all of the user processors 2221-22232, that is, the digital electronic data in the data flow Un33 output from the fourth output mapping unit 296 carry substantially the same information as the digital electronic data in the data flows XY input to the time-domain demultiplexers 26033 in all of the user processors 2221-22232 carry.
Referring to FIG. 4D, in the equalizing and optimizing process, one (F1) of the cost functions may observe the change between the known diagnostic data, which is carried by the diagnostic or pilot signal XY, and the digital electronic data in the data flow Un33 received by the second optimizer 235. Others (F2) of the cost functions may be based on observations among the signals Un1-Un33. More specifically, the cost functions (F2) may be related to cross-correlation between each two of the signals Un1-Un33 received by the second optimizer 235. In the equalizing and optimizing process, the second optimizer 235 is configured to calculate a total cost based on the sum of all of the cost functions (F1) and (F2) and then compare the total cost with a predetermined cost threshold. When the total cost is verified to be greater than the predetermined cost threshold, the second optimizer 235 is configured to calculate a variation in the total cost in response to perturbations on the equalizing weights buffered in the second equalization processor 231 or to measure each gradient of the total cost with respect to the equalizing weights buffered in the second equalization processor 231. Based on the calculated variation or measured gradients, the second optimizer 235 creates updated equalizing weights, based on a cost minimization algorithm, such as steepest descent method, to be sent to the second equalization processor 231 and to replace current ones buffered in the second equalization processor 231 in the next scheduled clock cycle. Thereby, the equalizing weights buffered in the second equalization processor 231 can be updated. The second optimizer 235 is configured to stop the equalizing and optimizing process when the total cost is verified to be less than the predetermined cost threshold.
Referring to FIGS. 4A-4D, the sub-controllers 262 of the user processors 2221-22232 are controlled by the controller 272 of the central office processor 210 and can alter or control the mapping of the third input mapping units 260 of the user processors 2221-22232, respectively. The controller 272 of the central office processor 210 can also alter or control the mapping of the fourth output mapping unit 296 such that the mapping of the third input mapping unit 260 in each of the thirty-two user processor 2221-22232 is correspondent to that of the fourth output mapping unit 296 in the central office processor 210, that is, the number of specific pieces of digital electronic data in the output data flows, e.g. Uf1-Uf32, into which the digital electronic data in the input data flow, e.g. Ua1 are mapped, by the third input mapping unit 260 in each of the user processors 2221-22232, to be allocated, can be the same as the number of pieces of digital electronic data in the input data flows, e.g. Ui1-Ui32, substantially equivalent to the specific pieces of digital electronic data in the respective output data flows, e.g. Uf1-Uf32 from the third input mapping unit 260 in each of the user processors 2221-22232, that are mapped, by the fourth output mapping unit 296, to be combined into a piece of digital electronic data in the output data flow, e.g. Un1.
For instance, when the time-domain or frequency-domain demultiplexer 2601 of the third input mapping unit 260, as illustrated in FIG. 4B, in the user processor 2221 is mapped to allocate the input digital electronic data in the data flow Ua1 into the thirty-two pieces of digital electronic data in the data flows Uf1-Uf32 based on the thirty-two respective non-overlapped time slots tg11-tg132 or frequency spectrums fg11-fg132 and the time-domain or frequency-domain demultiplexer 2601 of the third input mapping unit 260, as illustrated in FIG. 4C, in each of the user processors 2222-22232 is mapped to allocate the received ground data into the thirty-two pieces of ground data in the data flows Uf1-Uf32 based on the thirty-two respective non-overlapped time slots tg11-tg132 or frequency spectrums fg11-fg132, the time-domain or frequency-domain multiplexer 2961 of the fourth output mapping unit 296 as illustrated in FIG. 4D, complementary to the time-domain or frequency-domain demultiplexers 2601 of the user processors 2221-22232 as illustrated in FIGS. 4B and 4C, can be mapped to combine the thirty-two pieces of digital electronic data in the data flows Ui1-Ui32, which are substantially equivalent to the thirty-two pieces of digital electronic data in the data flows Uf1-Uf32, associated with the digital electronic data in the data flow Ua1 input to the user processor 2221, respectively, into the digital electronic data in the data flow Un1 based on the thirty-two respective non-overlapped time slots tm11-tm132 or frequency spectrums fm11-fm132. The time slots tg11-tg132 may have substantially the same time interval or period as the time slots tm11-tm132, respectively. For example, the time slot tg11 may have substantially the same time interval or period as the time slot tm11. The time slot tg132 may have substantially the same time interval or period as the time slot tm132. Alternatively, all of the time slots tg11-tg132 and tm11-tm132 may have substantially the same time interval or period. The frequency spectrums fg11-fg132 may have substantially the same frequency bandwidth as the frequency spectrums fm11-fm132, respectively. For example, the frequency spectrum fg11 may have substantially the same frequency bandwidth as the frequency spectrum fm11. The frequency spectrum fg132 may have substantially the same frequency bandwidth as the frequency spectrum fm132. Alternatively, all of the frequency spectrums fg11-fg132 and fm11-fm132 may have substantially the same frequency bandwidth.
For instance, when the time-domain or frequency-domain demultiplexer 2602 of the third input mapping unit 260, as illustrated in FIG. 4C, in the user processor 2222 is mapped to allocate the input digital electronic data in the data flow Ua2 into the sixteen pieces of digital electronic data in the data flows Uf33-Uf48 based on the sixteen respective non-overlapped time slots tg21-tg216 or frequency spectrums fg21-fg216 and the time-domain or frequency-domain demultiplexer 2602 of the third input mapping unit 260, as illustrated in FIG. 4B, in each of the user processors 2221 and 2223-22232 is mapped to allocate the received ground data into the sixteen pieces of ground data in the data flows Uf33-Uf48 based on the sixteen respective non-overlapped time slots tg21-tg216 or frequency spectrums fg21-fg216, the time-domain or frequency-domain multiplexer 2962 of the fourth output mapping unit 296 as illustrated in FIG. 4D, complementary to the time-domain or frequency-domain demultiplexers 2602 of the user processors 2221-22232 as illustrated in FIGS. 4B and 4C, can be mapped to combine the sixteen pieces of digital electronic data in the data flows Ui33-Ui48, which are substantially equivalent to the sixteen pieces of digital electronic data in the data flows Uf33-Uf48, associated with the digital electronic data in the data flow Ua2 input to the user processor 2222, respectively, into the digital electronic data in the data flow Un2 based on the sixteen respective non-overlapped time slots tm21-tm216 or frequency spectrums fm21-fm216. The time slots tg21-tg216 may have substantially the same time interval or period as the time slots tm21-tm216, respectively. For example, the time slot tg21 may have substantially the same time interval or period as the time slot tm21. The time slot tg216 may have substantially the same time interval or period as the time slot tm216. Alternatively, all of the time slots tg21-tg216 and tm21-tm216 may have substantially the same time interval or period. The frequency spectrums fg21-fg216 may have substantially the same frequency bandwidth as the frequency spectrums fm21-fm216, respectively. For example, the frequency spectrum fg21 may have substantially the same frequency bandwidth as the frequency spectrum fm21. The frequency spectrum fg216 may have substantially the same frequency bandwidth as the frequency spectrum fm216. Alternatively, all of the frequency spectrums fg21-fg216 and fm21-fm216 may have substantially the same frequency bandwidth.
For instance, when the time-domain or frequency-domain demultiplexer 26033 of the third input mapping unit 260, as illustrated in FIGS. 4B and 4C, in each of the user processors 2221-22232 is mapped to allocate the input diagnostic or pilot data in the data flow XY into the two pieces of digital electronic data in the data flows Uf127-Uf128 based on the two respective non-overlapped time slots tg331 and tg332 or frequency spectrums fg331 and fg332, the time-domain or frequency-domain multiplexer 29633 of the fourth output mapping unit 296 as illustrated in FIG. 4D, complementary to the time-domain or frequency-domain demultiplexers 26033 of the user processors 2221-22232 as illustrated in FIGS. 4B and 4C, can be mapped to combine the two pieces of digital electronic data in the data flows Ui127 and Ui128, which are substantially equivalent to the two pieces of digital electronic data in the data flows Uf127 and Uf128, associated with the diagnostic or pilot data in the data flows XY input to the time-domain demultiplexers 26033 of the user processors 2221-22232, respectively, into the digital electronic data in the data flow Un33 based on the two respective non-overlapped time slots tm331 and tm332 or frequency spectrums fm331 and fm332. The time slots tg331 and tg332 may have substantially the same time interval or period as the time slots tm331 and tm332, respectively. For example, the time slot tg331 may have substantially the same time interval or period as the time slot tm331. The time slot tg332 may have substantially the same time interval or period as the time slot tm332. Alternatively, all of the time slots tg331, tg332, tm331 and tm332 may have substantially the same time interval or period. The frequency spectrums fg331 and fg332 may have substantially the same frequency bandwidth as the frequency spectrums fm331 and fm332, respectively. For example, the frequency spectrum fg331 may have substantially the same frequency bandwidth as the frequency spectrum fm331. The frequency spectrum fg332 may have substantially the same frequency bandwidth as the frequency spectrum fm332. Alternatively, all of the frequency spectrums fg331, fg332, fm331 and fm332 may have substantially the same frequency bandwidth. Other situations can be considered in a similar way.
The controller 272 can dynamically and synchronously alter or control the input mapping of the user processors 2221-22232 and the output mapping of the central office processor 210 such that the mapping of the third input mapping unit 260 in each of the thirty-two user processor 2221-22232 can be correspondent to that of the fourth output mapping unit 296. Thereby, the digital electronic data in the data flows Ua1-Ua32 and XY can efficiently share the resource or bandwidth of the passive optical network 200. The resource or bandwidth of the passive optical network 200 for the digital electronic data in the data flows Ua1-Ua32 and XY can be dynamically controlled or altered. The digital electronic data in each of the data flows Ua1-Ua32 can be allocated into the various number of pieces of data in accordance with user's subscription for a specific data flow rate.
In this embodiment, the third output mapping unit 266 in one of the user processors 2221-22232, the time-domain or frequency-domain multiplexer 278 in one of the optical network units (ONU) 2061-20632, the optical laser device 280 in one of the optical network units (ONU) 2061-20632, the optical transferring device 204, the optical signal receiver 286 of the optical line terminal (OLT) 202, the time-domain demultiplexer 288 of the optical line terminal (OLT) 202 and the fourth input mapping unit 290 in the central office processor 210 composes the data relaying system 998 as illustrated in FIGS. 1A and 1B and are arranged in sequence between the wave-front multiplexer 213 and the wave-front demultiplexer 232.
Accordingly, dynamic allocations of time slots or equivalent bandwidths of passive optical networks (PON) in combination with wave-front (WF) multiplexing/demultiplexing techniques to generate multi-dimensional wavefront-multiplexed signals concurrently propagating through the passive optical networks (PON) can break through bandwidth limits set for subscribers. The architectures of the invention support dynamic bandwidth allocations as well as configurable bandwidth allocations. The architectures of the invention support dynamic bandwidth allocations as well as configurable bandwidth allocations. They also support dynamic allocations for power resources as well as configurable allocations for power resources of optical lasers with regards to different signals transmitted to/from various subscribers.
Wave-front multiplexing techniques allow a fiber infrastructure to be used more effectively, while enabling a subscriber to dynamically access the passive optical network with high re-configurable data rate, up to the full 1,250 Mbps.
The upgraded passive optical networks in accordance with the invention can support:
a. subscribers/users ask for different but fixed needs in data rates;
b. subscribers/users ask for different and dynamic needs in data rates; and
c. subscribers/users ask for different needs in optical powers in a passive optical network.
The invention can enhance coverage quality of the passive optical network because subscribers/users (user processors) in shorter distances from the central office processor can obtain relatively small shares of laser power to boost their signals for compensating subscribers/users (user processors) in long distances from the central office processor to obtain relatively large shares of laser power to boost their signals.
Other Applications:
Alternatively, the above techniques may be applicable to wireless communication. For example, referring to FIGS. 3A-3C and 4A-4D, the optical transferring device 204 can be replaced with a satellite. The optical laser device 228 and the optical signal receiver 286 in the optical line terminal (OLT) 202 can be replaced with a first signal radiating/receiving system and a first antenna array. The optical laser device 280 and the optical signal receiver 230 in each of the optical network units (ONU) 2061-20632 can be replaced with a second signal radiating/receiving system and a second antenna array. Referring to FIGS. 3A-3C, in a downstream dataflow, the first signal radiating/receiving system can convert the digital electronic data in the data flow Dp output from the time-domain multiplexer 226 into a relatively high frequency band, such as Ka or Ku band, and into an analog mode. The first antenna array can radiate analog data, converted by the first signal radiating/receiving system, to the second antenna arrays, coupled to the respective user processors 2221-22232, through the satellite. For each of the user processors 2221-22232, the second signal radiating/receiving system can convert the analog data, received by the corresponding second antenna array, into a relatively low frequency band, such as intermediate frequency band or baseband, and into a digital mode. Digital electronic data, converted by the second signal radiating/receiving system, can be output in the data flow Dm to the corresponding time-domain demultiplexer 238.
Referring to FIGS. 4A-4D, in an upstream dataflow, for each of the user processors 2221-22232, the second signal radiating/receiving system can convert the digital electronic data in the data flow Dp output from the corresponding time-domain multiplexer 226 into a relatively high frequency band, such as Ka or Ku band, and into an analog mode. The second antenna arrays can radiate analog data, converted by the second signal radiating/receiving systems, to the satellite. The radiated analog data from the second antenna arrays can be combined at the satellite. The first antenna array can receive the combined analog data from the satellite. The first signal radiating/receiving system can convert the received analog data into a relatively low frequency band, such as intermediate frequency band or baseband, and into a digital mode. Digital electronic data, converted by the first signal radiating/receiving system, can be output in the data flow Um to the time-domain demultiplexer 288.
Alternatively, the above techniques may be applicable to cable networks replacing the optical transferring device 204, the optical laser device 228 and optical signal receiver 286 in the optical line terminal (OLT) 202 and the optical laser device 280 and optical signal receiver 230 in each of the optical network units (ONU) 2061-20632.
The components, steps, features, benefits and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
In reading the present disclosure, one skilled in the art will appreciate that embodiments of the present disclosure can be implemented in hardware, software, firmware, or any combinations of such, and over one or more networks. Suitable software can include computer-readable or machine-readable instructions for performing methods and techniques (and portions thereof) of designing and/or controlling the implementation of the wave-front multiplexing and demultiplexing processes.
Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain. Furthermore, unless stated otherwise, the numerical ranges provided are intended to be inclusive of the stated lower and upper values. Moreover, unless stated otherwise, all material selections and numerical values are representative of preferred embodiments and other ranges and/or materials may be used.
The scope of protection is limited solely by the claims, and such scope is intended and should be interpreted to be as broad as is consistent with the ordinary meaning of the language that is used in the claims when interpreted in light of this specification and the prosecution history that follows, and to encompass all structural and functional equivalents thereof.

## Claims

1. A data communication system comprising:
an optical-to-electronic converter configured to convert an optical signal into a first electronic signal;
a first signal mapping unit downstream of said first optical-to-electronic converter, wherein said first signal mapping unit is configured to allocate said first electronic signal into multiple electronic signals comprising a second electronic signal and a third electronic signal based on multiple time slots; and
a processor downstream of said first signal mapping unit, wherein said processor is configured to have a first input associated with said second electronic signal and a second input associated with said third electronic signal and generate a fourth electronic signal carrying information associated with said first and second inputs and a fifth electronic signal carrying information associated with said first and second inputs.

2. The data communication system of claim 1, wherein said optical-to-electronic converter is configured to couple with an optical fiber.

3. The data communication system of claim 1 further comprising a second signal mapping unit downstream of said processor, wherein said second signal mapping unit is configured to combine multiple electronic signals comprising said fourth and fifth electronic signals into a sixth signal.

4. The data communication system of claim 3 further comprising a controller configured to alter the number of electronic signals that are combined into said sixth signal.

5. The data communication system of claim 1, wherein said fourth electronic signal is a linear combination of said first and second inputs.

6. The data communication system of claim 1 further comprising a second signal mapping unit downstream of said first signal mapping unit, wherein said second signal mapping unit is configured to allocate said second electronic signal into multiple electronic signals comprising a sixth electronic signal and a seventh electronic signal, and a third signal mapping unit downstream of said first signal mapping unit, wherein said third signal mapping unit is configured to allocate said third electronic signal into multiple electronic signals comprising an eighth electronic signal and a ninth electronic signal, wherein said first input is associated with said sixth electronic signal and said second input is associated with said eighth electronic signal, wherein said processor is configured to have a third input associated with said seventh electronic signal and a fourth input associated with said ninth electronic signal, wherein said fourth electronic signal carries information associated with said first, second, third and fourth inputs and said fifth electronic signal carries information associated with said first, second, third and fourth inputs.

7. The data communication system of claim 1 further comprising an equalizing unit downstream of said first signal mapping unit and upstream of said processor, wherein said equalizing unit is configured to have a third input associated with said second electronic signal and a fourth input associated with said third electronic signal and weigh said third input into a first equalized signal coupled to said first input of said processor and said fourth input into a second equalized signal coupled to said second input of said processor.

8. A data communication system comprising:
an optical-to-electronic converter configured to convert an optical signal into a first electronic signal;
a first signal mapping unit downstream of said first optical-to-electronic converter, wherein said first signal mapping unit is configured to allocate said first electronic signal into multiple electronic signals comprising a second electronic signal and a third electronic signal based on multiple frequency spectrums; and
a processor downstream of said first signal mapping unit, wherein said processor is configured to have a first input associated with said second electronic signal and a second input associated with said third electronic signal and generate a fourth electronic signal carrying information associated with said first and second inputs and a fifth electronic signal carrying information associated with said first and second inputs.

9. The data communication system of claim 8, wherein said optical-to-electronic converter is configured to couple with an optical fiber.

10. The data communication system of claim 8 further comprising a second signal mapping unit downstream of said processor, wherein said second signal mapping unit is configured to combine multiple electronic signals comprising said fourth and fifth electronic signals into a sixth signal.

11. The data communication system of claim 10 further comprising a controller configured to alter the number of electronic signals that are combined into said sixth signal.

12. The data communication system of claim 8, wherein said fourth electronic signal is a linear combination of said first and second inputs.

13. The data communication system of claim 8 further comprising a second signal mapping unit downstream of said first signal mapping unit, wherein said second signal mapping unit is configured to allocate said second electronic signal into multiple electronic signals comprising a sixth electronic signal and a seventh electronic signal, and a third signal mapping unit downstream of said first signal mapping unit, wherein said third signal mapping unit is configured to allocate said third electronic signal into multiple electronic signals comprising an eighth electronic signal and a ninth electronic signal, wherein said first input is associated with said sixth electronic signal and said second input is associated with said eighth electronic signal, wherein said processor is configured to have a third input associated with said seventh electronic signal and a fourth input associated with said ninth electronic signal, wherein said fourth electronic signal carries information associated with said first, second, third and fourth inputs and said fifth electronic signal carries information associated with said first, second, third and fourth inputs.

14. The data communication system of claim 8 further comprising an equalizing unit downstream of said first signal mapping unit and upstream of said processor, wherein said equalizing unit is configured to have a third input associated with said second electronic signal and a fourth input associated with said third electronic signal and weigh said third input into a first equalized signal coupled to said first input of said processor and said fourth input into a second equalized signal coupled to said second input of said processor.

15. A data communication system comprising:
a processor configured to receive a first signal and a second signal and generate a third signal carrying information associated with said first and second signals and a fourth signal carrying information associated with said first and second signals;
a first signal mapping unit downstream of said processor, wherein said first signal mapping unit is configured to combine multiple signals comprising said third and fourth signals into a fifth signal; and
a controller configured to alter the number of signals that are combined into said fifth signal.

16. The data communication system of claim 15, wherein said third signal carries information associated with a linear combination of said first and second signals, and said fourth signal carries information associated with a linear combination of said first and second signals.

17. The data communication system of claim 15 further comprising a second signal mapping unit upstream of said processor, wherein said second signal mapping unit is configured to allocate a first input into multiple outputs comprising a first output and a second output, wherein said first signal is associated with said first output and said second signal is associated with said second output.

18. The data communication system of claim 15 further comprising an optical-to-electronic converter upstream of said processor, wherein said optical-to-electronic converter is configured to convert an optical signal into an electronic signal, wherein said first and second signals are associated with said electronic signal.

19. The data communication system of claim 15, wherein said first and second signals come from an optical signal.

20. The data communication system of claim 15 further comprising an equalizing unit upstream of said processor, wherein said equalizing unit is configured to have a first input and a second input and weigh said first input into said first signal and said second input into said second signal.