# Patent

## Title
Semiconductor device

## Abstract

To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film.

## Background
This application is a continuation of copending U.S. application Ser. No. 14/885,545, filed on Oct. 16, 2015 which is a continuation of U.S. application Ser. No. 14/294,638, filed on Jun. 3, 2014 (now U.S. Pat. No. 9,166,060 issued Oct. 20, 2015, which are all incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device.
In this specification, a “semiconductor device” refers to a device that can function by utilizing semiconductor characteristics; an electro-optical device, a semiconductor circuit, and an electrical device are all included in the category of the semiconductor device.
2. Description of the Related Art
Attention has been focused on a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface (also referred to as thin film transistor (TFT)). The transistor is used for a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film which can be used for a transistor. As another material, an oxide semiconductor has been attracting attention.
For example, a transistor including an amorphous oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is disclosed in Patent Document 1.
Techniques for improving carrier mobility by stacking oxide semiconductor films are disclosed in Patent Documents 2 and 3.
A transistor including an oxide semiconductor film is known to have extremely low leakage current in an off state. For example, a CPU with low-power consumption utilizing the low leakage current of the transistor including an oxide semiconductor film is disclosed (see Patent Document 4).
REFERENCE
Patent Document


    [Patent Document 1] Japanese Published Patent Application No. 2006-165528
    [Patent Document 2] Japanese Published Patent Application No. 2011-124360
    [Patent Document 3] Japanese Published Patent Application No. 2011-138934
    [Patent Document 4] Japanese Published Patent Application No. 2012-257187


SUMMARY OF THE INVENTION
Miniaturization of transistors has been progressing with an increase in the degree of integration of circuits. In some cases, miniaturization of transistors causes deterioration of the electrical characteristics of the transistors, such as on-state current, off-state current, threshold voltage, and a subthreshold swing value (an S value). In general, a decrease in channel length leads to an increase in off-state current, an increase in variations of threshold voltage, and an increase in S value, whereas a decrease in channel width leads to a decrease in on-state current.
Thus, an object of one embodiment of the present invention is to provide a semiconductor device having a structure which can prevent the deterioration of electrical characteristics, which becomes more significant with miniaturization of transistors. Another object is to provide a semiconductor device having a high degree of integration. Another object is to provide a semiconductor device in which decrease of on-state current characteristics is reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device which can retain data even when power supply is stopped.
Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
A transistor including an oxide semiconductor film is an accumulation-type transistor in which electrons are majority carriers. Therefore, drain-induced barrier lowering (DIBL) as a short-channel effect is less likely to occur than in an inversion-type transistor having a pn junction. In other words, the transistor including an oxide semiconductor film is resistant to a short-channel effect.
When a channel width of a transistor is shortened, on-state current becomes low. For the purpose of increasing the on-state current, there is a method in which the thickness of a semiconductor film is increased so that a channel is formed on a top surface of the semiconductor film and side surfaces of the semiconductor film. However, an increase in a surface area where a channel is formed increases scattering of carriers at the interface between a channel formation region and a gate insulating layer; therefore, it is not easy to increase the on-state current sufficiently.
To achieve any of the above objects, the following structures of a semiconductor device are provided in one embodiment of the present invention.
One embodiment of the present invention is a semiconductor device including a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with a top surface of the gate insulating film, the gate electrode facing the top surface of the second oxide semiconductor film and the side surface of the second oxide semiconductor film. In the semiconductor device, the thickness of the first oxide semiconductor film is larger than the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film.
Note that in this specification and the like, ordinal numbers such as “first” and “second” are used in order to avoid confusion among components and do not limit the components numerically.
In the above structure, the difference of the thickness of the first oxide semiconductor film from the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is preferably greater than 0 nm and less than 300% of a channel width, more preferably greater than 0 nm and less than the channel width.
Another embodiment of the present invention is a semiconductor device including a first oxide semiconductor film provided over a projected portion of an insulating surface including a depressed portion and the projected portion; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a bottom surface of the depressed portion of the insulating surface, a side surface of the projected portion of the insulating surface, a side surface of the first oxide semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with a top surface of the gate insulating film, the gate electrode facing the top surface of the second oxide semiconductor film and the side surface of the second oxide semiconductor film. In the semiconductor device, the sum of the height of the projected portion of the insulating surface from the bottom surface of the depressed portion of the insulating surface and the thickness of the first oxide semiconductor film is larger than the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film.
In the above structure, the difference of the sum of the height of the projected portion of the insulating surface from the bottom surface of the depressed portion of the insulating surface and the thickness of the first oxide semiconductor film from the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is preferably greater than 0 nm and less than 300% of a channel width, more preferably greater than 0 nm and less than the channel width, still more preferably greater than 0 nm and less than the thickness of the first oxide semiconductor film.
In any of the above structures, an end portion of the top surface of the second oxide semiconductor film may have a curved surface.
In any of the above structures, the top surface of the second oxide semiconductor film may have a flat portion.
In any of the above structures, a curvature radius r of an end portion (in the case of two end portions, each of curvature radiuses r1 and r2) in a channel width direction of the second oxide semiconductor film is greater than 0 and less than or equal to a channel width W (0<r (or r1 or r2)≦W), preferably greater than 0 and less than or equal to a half of the channel width W (0<r (or r1 or r2)≦W/2).
In any of the above structures, the third oxide semiconductor film may include a first layer including a crystalline region, and a second layer including a crystalline region over the first layer; a crystal included in the first layer is not aligned in a specific direction, whereas a c-axis of a crystal included in the second layer is aligned in a direction parallel to a normal vector of a top surface of the second layer.
In any of the above structures, energy of conduction band minimum of each of the first oxide semiconductor film and the third oxide semiconductor film is preferably closer to a vacuum level than energy of conduction band minimum of the second oxide semiconductor film by 0.05 eV or more and 2 eV or less.
In one embodiment of the present invention, a semiconductor device can be provided in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed. A highly integrated semiconductor device can be provided. A semiconductor device in which deterioration of on-state current characteristics is reduced can be provided. A semiconductor device with low power consumption can be provided. A highly reliable semiconductor device can be provided. A semiconductor device which can retain data even when power supply is stopped can be provided.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 1C are a top view and cross-sectional views of a transistor.
FIGS. 2A and 2B each show a band structure of a multilayer film.
FIG. 3 is a cross-sectional view of a transistor taken along a channel length direction.
FIGS. 4A to 4C are a top view and cross-sectional views of a transistor.
FIGS. 5A to 5C are a top view and cross-sectional views of a transistor.
FIGS. 6A to 6C are a top view and cross-sectional views of a transistor.
FIGS. 7A to 7C illustrate a method for manufacturing a transistor.
FIGS. 8A to 8C illustrate a method for manufacturing a transistor.
FIGS. 9A to 9C are a top view and cross-sectional views of a transistor.
FIGS. 10A to 10C are a top view and cross-sectional views of a transistor.
FIGS. 11A to 11C are a top view and cross-sectional views of a transistor.
FIGS. 12A to 12C illustrate a method for manufacturing a transistor.
FIGS. 13A to 13C illustrate a method for manufacturing a transistor.
FIGS. 14A to 14D each illustrate an inverter including a semiconductor device of one embodiment of the present invention.
FIG. 15 is a circuit diagram of a semiconductor device according to an embodiment.
FIG. 16 is a block diagram of a semiconductor device according to an embodiment.
FIG. 17 is a circuit diagram of a memory device according to an embodiment.
FIGS. 18A to 18C illustrate electronic devices according to an embodiment.
FIG. 19 is an equivalent circuit diagram illustrating an example of a semiconductor device.
FIGS. 20A to 20C are a top view and cross-sectional views of a transistor.
FIGS. 21A to 21C illustrate a method for manufacturing a transistor.
FIGS. 22A to 22C illustrate a method for manufacturing a transistor.
FIGS. 23A to 23C are a top view and cross-sectional views of a transistor.
FIGS. 24A to 24D illustrate a method for manufacturing a transistor.
FIGS. 25A to 25C are a schematic diagram illustrating a deposition model of a CAAC-OS and a pellet, and cross-sectional views of a CAAC-OS.
FIG. 26 illustrates a deposition model of an nc-OS schematically and a pellet.
FIG. 27 illustrates a pellet.
FIG. 28 illustrates force applied to a pellet on a film formation surface.
FIGS. 29A and 29B illustrate transfer of pellets on film formation surfaces.
FIGS. 30A and 30B illustrate a crystal of InGaZnO4.
FIGS. 31A and 31B illustrate a structure of InGaZnO4 and the like before an atom collides.
FIGS. 32A and 32B illustrate a structure of InGaZnO4 and the like after an atom collides.
FIGS. 33A and 33B illustrate a trajectory of an atom after collision.
FIGS. 34A and 34B are cross-sectional HAADF-STEM images of a CAAC-OS and a target.



DETAILED DESCRIPTION OF THE INVENTION
Embodiments will be described in detail with reference to drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of Embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases.
Note that functions of a “source” and a “drain” of a transistor are sometimes replaced with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be replaced with each other in this specification.
[Embodiment 1]
In this embodiment, a semiconductor device of one embodiment of the present invention is described with reference to drawings.
FIGS. 1A to 1C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention. FIG. 1A is the top view. FIG. 1B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 1A. FIG. 1C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 1A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 1A. In some cases, the direction of the dashed-dotted line A-B is referred to as a channel length direction, and the direction of the dashed-dotted line C-D is referred to as a channel width direction.
A transistor 450 illustrated in FIGS. 1A to 1C includes a base insulating film 402 having a depressed portion and a projected portion over a substrate 400; a first oxide semiconductor film 404a and a second oxide semiconductor film 404b over the projected portion of the base insulating layer 402; a source electrode 406a and a drain electrode 406b over the first oxide semiconductor film 404a and the second oxide semiconductor film 404b; a third oxide semiconductor film 404c in contact with a bottom surface of the depressed portion of the base insulating film 402, a side surface of the projected portion of the base insulating film 402, a side surface of the first oxide semiconductor film 404a, a side surface of the second oxide semiconductor film 404b, a top surface of the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b; a gate insulating film 408 over the third oxide semiconductor film 404c; a gate electrode 410 which is in contact with a top surface of the gate insulating film 408 and faces the top surface of the second oxide semiconductor film 404b and the side surface of the second oxide semiconductor film 404b; and an oxide insulating film 412 over the source electrode 406a, the drain electrode 406b, and the gate electrode 410. The first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c are collectively referred to as a multilayer film 404.
Note that a channel length refers to a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor film and a gate electrode overlap with each other in a top view. Accordingly, in FIG. 1A, a channel length (L) is a distance between the source electrode 406a and the drain electrode 406b in a region where the second oxide semiconductor film 404b and the gate electrode 410 overlap with each other. A channel width refers to a length of a portion where a source and a drain face each other and where a semiconductor film and a gate electrode overlap with each other. Accordingly, in FIG. 1A, a channel width (W) is a length of a portion where the source electrode 406a and the drain electrode 406b face each other and where the second oxide semiconductor film 404b and the gate electrode 410 overlap with each other.
In the transistor 450, a perpendicular distance H is the difference of the sum of a height h1 of the projected portion of the base insulating film 402 from the bottom surface of the depressed portion of the base insulating film 402 and a thickness t1 of the first oxide semiconductor film 404a (h1+t1) from the sum of a thickness t3 of the third oxide semiconductor film 404c and a thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W, more preferably greater than 0 nm and less than the thickness t1 of the first oxide semiconductor film 404a. 
The gate electrode 410 electrically covers the second oxide semiconductor film 404b when seen in the channel width direction in such a structure, whereby on-state current is increased. Such a structure of a transistor is referred to as a surrounded channel (s-channel) structure. Note that in the s-channel structure, current flows in the whole (bulk) of the second oxide semiconductor film 404b. Because current flows in an inner part of the multilayer film 404 (the whole of the second oxide semiconductor film 404b), the current is hardly affected by interface scattering, leading to high on-state current. Note that when the second oxide semiconductor film 404b is thick, high on-state current can be obtained. Since the gate electrode 410 extending lower than the interface between the first oxide semiconductor film 404a and the second oxide semiconductor film 404b and reaching a position on the base insulating film 402 side does not affect the channel width W, the channel width W can be made small, achieving high density (high integration).
In fabricating a transistor with a small channel length and a small channel width, when an electrode, a semiconductor film, or the like is processed while a resist mask is reduced in size, the electrode, the semiconductor film, or the like has a round end portion (curved surface) in some cases. With this structure, the coverage with the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412, which are to be formed over the second oxide semiconductor film 404b, the source electrode 406a, and the source electrode 406b, can be improved. In addition, electric field concentration which might occur at end portions of the source electrode 406a and the drain electrode 406b can be reduced, which can suppress deterioration of the transistor.
Miniaturization of a transistor leads to high integration and high density. In the miniaturization, for example, the channel length of the transistor is set to be less than or equal to 100 nm, preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm, and the channel width of the transistor is set to be less than or equal to 100 nm, preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm. The transistor of one embodiment of the present invention has an s-channel structure. Therefore, even when the channel width is shortened to the above range, high on-state current can be obtained.
The second oxide semiconductor film 404b has a curvature of an osculating circle whose radius of curvature is r. Note that the radius of curvature is equal to the radius of an osculating circle of a curve. The second oxide semiconductor film 404b may have two or more portions with curvatures of different osculating circles.
Specifically, a top surface of the second oxide semiconductor film 404b illustrated in FIGS. 1A to 1C has a flat portion. A curvature radius r1 of an end portion in the channel width direction of the top surface of the second oxide semiconductor film 404b is greater than 0 and less than or equal to the channel width W (0<r1≦W), preferably greater than 0 and less than or equal to a half of the channel width W (0<r1≦W/2); similarly, a curvature radius r2 of another end portion in the channel width direction of the top surface is greater than 0 and less than or equal to the channel width W (0<r2≦W), preferably greater than 0 and less than or equal to a half of the channel width W (0<r2≦W/2).
The third oxide semiconductor film 404c includes a first layer and a second layer over the first layer. The first layer and the second layer each include a crystalline region. A crystal included in the first layer is not aligned in a specific crystal direction. The second layer is formed so that a c-axis of a crystal in the second layer is aligned in a direction parallel to a normal vector of a top surface of the second layer.
When the second oxide semiconductor film 404b is formed to have a curved surface, a channel region in the second oxide semiconductor film 404b can be densely covered by the crystal whose c-axis is aligned. In the second layer, oxygen and an impurity do not easily pass in the direction of the c-axis of the crystal. That is, the second layer has a function of blocking the release of oxygen to the outside and the entrance of an impurity from the outside. Therefore, with the second layer, an oxygen vacancy is not generated easily in the second oxide semiconductor film 404b and an impurity does not enter the second oxide semiconductor film 404b easily. Thus, the density of defect states and the carrier density of the second oxide semiconductor film 404b can be reduced.
The substrate 400 is not limited to a simple supporting substrate, and may be a substrate where a device such as a transistor is formed. In that case, at least one of the gate electrode 410, the source electrode 406a, and the drain electrode 406b of the transistor 450 may be electrically connected to the above device.
The base insulating film 402 can have a function of supplying oxygen to the multilayer film 404 as well as a function of preventing diffusion of impurities from the substrate 400. For this reason, the base insulating film 402 is preferably an insulating film containing oxygen and more preferably, the base insulating film 402 is an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. In the case where the substrate 400 is provided with another device as described above, the base insulating film 402 also has a function as an interlayer insulating film. In that case, since the base insulating film 402 has an uneven surface, the base insulating film 402 is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) treatment so as to have a flat surface before forming the transistor 450.
An aluminum oxide film that can supply oxygen is preferably used for the base insulating film 402. The aluminum oxide film has not only a function of supplying oxygen but also a function of blocking hydrogen, water, and oxygen. An aluminum oxide film containing silicon oxide, which is formed using a target in which an aluminum oxide and silicon oxide are mixed, can be used. In that case, the content of silicon oxide is preferably greater than or equal to 0.1 weight % and less than or equal to 30 weight %.
In a region of the transistor 450 where a channel is formed, the multilayer film 404 has a structure in which the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c are stacked in this order from the substrate 400 side. The second oxide semiconductor film 404b is surrounded by the first oxide semiconductor film 404a and the third oxide semiconductor film 404c. As in FIG. 1C, the gate electrode 410 electrically covers the second oxide semiconductor film 404b when seen in the channel width direction.
Here, for the second oxide semiconductor film 404b, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the first semiconductor oxide film 404a and the third oxide semiconductor film 404c is used. The electron affinity can be obtained by subtracting an energy difference between the conduction band minimum and the valence band maximum (the difference is called an energy gap) from an energy difference between the vacuum level and the valence band maximum (the difference is called an ionization potential).
The first oxide semiconductor film 404a and the third oxide semiconductor film 404c each contain one or more kinds of metal elements forming the second oxide semiconductor film 404b. For example, the first oxide semiconductor film 404a and the third oxide semiconductor film 404c are preferably formed using an oxide semiconductor whose conduction band minimum is closer to a vacuum level than that of the second oxide semiconductor film 404b. Further, the energy difference of the conduction band minimum between the second oxide semiconductor film 404b and the first oxide semiconductor film 404a and the energy difference of the conduction band minimum between the second oxide semiconductor film 404b and the third oxide semiconductor film 404c are each preferably greater than or equal to 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV and less than or equal to 2 eV, 1 eV, 0.5 eV, or 0.4 eV.
In such a structure, when an electric field is applied to the gate electrode 410, a channel is formed in the second oxide semiconductor film 404b whose conduction band minimum is the lowest in the multilayer film 404. In other words, when the third oxide semiconductor film 404c is formed between the second oxide semiconductor film 404b and the gate insulating film 408, the channel of the transistor is formed in a region which is not in contact with the gate insulating film 408.
Further, since the first oxide semiconductor film 404a contains one or more kinds of metal elements forming the second oxide semiconductor film 404b, an interface state is less likely to be formed at the interface of the second oxide semiconductor film 404b with the first oxide semiconductor film 404a than at the interface with the base insulating film 402 on the assumption that the second oxide semiconductor film 404b is in contact with the base insulating film 402. The interface state sometimes forms a channel, leading to a change in the threshold voltage of the transistor. Thus, with the first oxide semiconductor film 404a, variation in the electrical characteristics of the transistor, such as a threshold voltage, can be reduced. Further, the reliability of the transistor can be improved.
Furthermore, since the third oxide semiconductor film 404c contains one or more metal elements contained in the second oxide semiconductor film 404b, scattering of carriers is less likely to occur at the interface of the second oxide semiconductor film 404b with the third oxide semiconductor film 404c than at the interface with the gate insulating film 408 on the assumption that the second oxide semiconductor film 404b is in contact with the gate insulating film 408. Thus, with the third oxide semiconductor film 404c, the field-effect mobility of the transistor can be increased.
For the first oxide semiconductor film 404a and the third oxide semiconductor film 404c, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf with a higher atomic ratio than that used for the second oxide semiconductor film 404b can be used. Specifically, an atomic ratio of any of the above metal elements in the first oxide semiconductor film 404a and the third oxide semiconductor film 404c is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as much as that in the second oxide semiconductor film 404b. Any of the above metal elements is strongly bonded to oxygen and thus has a function of suppressing generation of an oxygen vacancy in the oxide semiconductor films. That is, an oxygen vacancy is less likely to be generated in the first oxide semiconductor film 404a and the third oxide semiconductor film 404c than in the second oxide semiconductor film 404b. 
Note that when each of the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c is an In—M—Zn oxide containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), and the first oxide semiconductor film 404a has an atomic ratio of In to M and Zn which is x1:y1:z1,the second oxide semiconductor film 404b has an atomic ratio of In to M and Zn which is x2:y2:z2, and the third oxide semiconductor film 404c has an atomic ratio of In to M and Zn which is x3:y3:z3, each of y1/x1 and y3/x3 is preferably larger than y2/x2. Each of y1/x1 and y3/x3 is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as large as y2/x2. At this time, when y2 is greater than or equal to x2 in the second oxide semiconductor film 404b, the transistor can have stable electrical characteristics. However, when y2 is 3 times or more as large as x2, the field-effect mobility of the transistor is reduced; accordingly, y2 is preferably less than 3 times x2.
The atomic ratio of In to M in each of the first oxide semiconductor film 404a and the third oxide semiconductor film 404c in the case where Zn and O are not taken into consideration is preferably as follows: the proportion of In is lower than 50 atomic % and the proportion of M is higher than or equal to 50 atomic %; and it is further preferably as follows: the proportion of In be lower than 25 atomic % and the proportion of M is higher than or equal to 75 atomic %. The atomic ratio of In to M in the second oxide semiconductor film 404b in the case where Zn and O are not taken into consideration is preferably as follows: the proportion of In is higher than or equal to 25 atomic % and the proportion of M is lower than 75 atomic %; and it is further preferably as follows: the proportion of In is higher than or equal to 34 atomic % and the proportion of M is lower than 66 atomic %.
The thicknesses of the first oxide semiconductor film 404a and the third oxide semiconductor film 404c are each greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm. The thickness of the second oxide semiconductor film 404b is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm. The second oxide semiconductor film 404b is preferably thicker than the first oxide semiconductor film 404a and the third oxide semiconductor film 404c. 
For the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c, an oxide semiconductor containing indium, zinc, and gallium can be used, for example. Note that the second oxide semiconductor film 404b preferably contains indium because carrier mobility can be increased.
Note that stable electrical characteristics can be effectively imparted to a transistor including an oxide semiconductor film by reducing the concentration of impurities in the oxide semiconductor film to make the oxide semiconductor film intrinsic or substantially intrinsic. The term “substantially intrinsic” refers to the state where an oxide semiconductor film has a carrier density lower than 1×1017/cm3, preferably lower than 1×1015/cm3, further preferably lower than 1×1013/cm3.
In the oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and a metal element other than main components of the oxide semiconductor film are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density. In addition, silicon in the oxide semiconductor film forms an impurity level. The impurity level might become a trap, which deteriorates the electrical characteristics of the transistor. Accordingly, in the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c and at interfaces between these films, the impurity concentration is preferably reduced.
In order to make the oxide semiconductor film intrinsic or substantially intrinsic, in SIMS (secondary ion mass spectrometry), for example, the concentration of silicon at a certain depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably lower than 1×1019 atoms/cm3, more preferably lower than 5×1018 atoms/cm3, still more preferably lower than 1×1018 atoms/cm3. Further, the concentration of hydrogen at a certain depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably lower than or equal to 2×1020 atoms/cm3, more preferably lower than or equal to 5×1019 atoms/cm3, still more preferably lower than or equal to 1×1019 atoms/cm3, yet still more preferably lower than or equal to 5×1018 atoms/cm3. Further, the concentration of nitrogen at a certain depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably lower than 5×1019 atoms/cm3, more preferably lower than or equal to 5×1018 atoms/cm3, still more preferably lower than or equal to 1×1018 atoms/cm3, yet still more preferably lower than or equal to 5×1017 atom s/cm3.
In the case where the oxide semiconductor film includes crystals, high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor film. In order not to lower the crystallinity of the oxide semiconductor film, for example, the concentration of silicon at a certain depth of the oxide semiconductor film or in a region of the oxide semiconductor film may be lower than 1×1019 atoms/cm3, preferably lower than 5×1018 atoms/cm3, more preferably lower than 1×1018 atoms/cm3. Further, the concentration of carbon at a certain depth of the oxide semiconductor film or in a region of the oxide semiconductor film may be lower than 1×1019 atoms/cm3, preferably lower than 5×1018 atoms/cm3, more preferably lower than 1×1018 atoms/cm3, for example.
A transistor in which the above-described highly purified oxide semiconductor film is used for a channel formation region has an extremely low off-state current. In the case where the voltage between a source and a drain is set to about 0.1 V, 5 V, or 10 V, for example, the off-state current standardized on the channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.
Note that as the gate insulating film of the transistor, an insulating film containing silicon is used in many cases; thus, it is preferable that, as in the transistor of one embodiment of the present invention, a region of the multilayer film, which serves as a channel, be not in contact with the gate insulating film for the above-described reason. In the case where a channel is formed at the interface between the gate insulating film and the multilayer film, scattering of carriers occurs at the interface, whereby the field-effect mobility of the transistor is reduced in some cases. Also from the view of the above, it is preferable that the region of the multilayer film, which serves as a channel, be separated from the gate insulating film.
Accordingly, with the multilayer film 404 having a stacked structure including the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c in this order, a channel can be formed in the second oxide semiconductor film 404b; thus, the transistor can have a high field-effect mobility and stable electrical characteristics.
Next, the band structure of the multilayer film 404 is described. For analyzing the band structure shown in FIG. 2A, a stacked film corresponding to the multilayer film 404 is formed. In the stacked film, In—Ga—Zn oxide with an energy gap of 3.5 eV is used for layers corresponding to the first oxide semiconductor film 404a and the third oxide semiconductor film 404c, and In—Ga—Zn oxide with an energy gap of 3.15 eV is used for a layer corresponding to the second oxide semiconductor film 404b. 
The thickness of each of the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c was 10 nm. The energy gap is measured with the use of a spectroscopic ellipsometer (UT-300 manufactured by HORIBA Jobin Yvon). Further, the energy difference between the vacuum level and the valence band maximum is measured using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe, ULVAC-PHI, Inc.).
FIG. 2A is part of a schematic band structure showing an energy difference (electron affinity) between the vacuum level and the conduction band minimum of each layer, which is calculated by subtracting the energy gap from the energy difference between the vacuum level and the valence band maximum. FIG. 2A is a band diagram showing the case where silicon oxide films are provided in contact with the first oxide semiconductor film 404a and the third oxide semiconductor film 404c. Here, Evac represents energy of the vacuum level, EcI1 and EcI2 each represent the conduction band minimum of the silicon oxide film, EcS1 represents the conduction band minimum of the first oxide semiconductor film 404a, EcS2 represents the conduction band minimum of the second oxide semiconductor film 404b, and EcS3 represents the conduction band minimum of the third oxide semiconductor film 404c. 
As shown in FIG. 2A, the energies of the conduction band minimums of the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c successively vary. This can be understood also from the fact that a common element is included in the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c and oxygen is easily diffused among the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c. Thus, the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c have a continuous physical property although they have different compositions and form a stack.
The multilayer film 404 in which layers containing the same main components are stacked is formed to have not only a simple stacked-layer structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which the conduction band minimums successively vary between layers). In other words, the stacked-layer structure is formed such that there exists no impurity which forms a defect level such as a trap center or a recombination center at each interface. If impurities exist between the stacked layers in the multilayer film, the continuity of the energy band is lost and carriers disappear by a trap or recombination.
Note that FIG. 2A shows the case where EcS1 and EcS3 are similar to each other; however, EcS1 and EcS3 may be different from each other. For example, part of the band structure in the case where EcS1 is higher than EcS3 is shown as in FIG. 2B.
For example, when EcS1 is equal to EcS3, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, 1:6:4, or 1:9:6 can be used for the first oxide semiconductor film 404a and the third oxide semiconductor film 404c and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 or 3:1:2 can be used for the second oxide semiconductor film 404b. Further, when EcS1 is higher than EcS3, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:6:4 or 1:9:6 can be used for the first oxide semiconductor film 404a, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 or 3:1:2 can be used for the second oxide semiconductor film 404b, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, or 1:3:4 can be used for the third oxide semiconductor film 404c, for example.
According to FIGS. 2A and 2B, the second oxide semiconductor film 404b of the multilayer film 404 serves as a well, so that a channel is formed in the second oxide semiconductor film 404b in a transistor including the multilayer film 404. Since the energies of the conduction band minimums are continuously changed, the multilayer film 404 can also be referred to as a U-shaped well. Further, a channel formed to have such a structure can also be referred to as a buried channel.
Note that trap levels due to impurities or defects might be formed in the vicinity of the interface between an insulating film such as a silicon oxide film and each of the first oxide semiconductor film 404a and the third oxide semiconductor film 404c. The second oxide semiconductor film 404b can be distanced away from the trap levels owing to existence of the first oxide semiconductor film 404a and the third oxide semiconductor film 404c. However, when the energy difference between EcS2 and EcS1 or EcS3 is small, an electron in the second oxide semiconductor film 404b might reach the trap level by passing over the energy difference. When the electron is trapped in the trap level, a negative fixed charge is generated at the interface with the insulating film, whereby the threshold voltage of the transistor is shifted in the positive direction.
Thus, to reduce fluctuations in the threshold voltage of the transistor, energy differences of at least certain values between EcS2 and EcS1 and between EcS2 and EcS3 are necessary. Each of the energy differences is preferably greater than or equal to 0.1 eV, further preferably greater than or equal to 0.15 eV.
The first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c preferably include crystal parts. In particular, when c-axis aligned crystals are used, the transistor can have stable electrical characteristics.
In the case where an In—Ga—Zn oxide is used for the multilayer film 404, it is preferable that the third oxide semiconductor film 404c contain less In than the second oxide semiconductor film 404b so that diffusion of In to the gate insulating film is prevented.
For the source electrode 406a and the drain electrode 406b, a conductive material which can be bonded to oxygen is preferably used. For example, Al, Cr, Cu, Ta, Ti, Mo, or W can be used. Among the materials, in particular, it is preferable to use Ti which is easily bonded to oxygen or to use W with a high melting point, which allows subsequent process temperatures to be relatively high. Note that the conductive material which can be bonded to oxygen includes, in its category, a material to which oxygen can be diffused.
When the conductive material which can be bonded to oxygen is in contact with a multilayer film, a phenomenon occurs in which oxygen in the multilayer film is diffused to the conductive material which can be bonded to oxygen. The phenomenon noticeably occurs when the temperature is high. Since the fabricating process of the transistor involves some heat treatment steps, the above phenomenon causes generation of oxygen vacancies in a region of the multilayer film near and in contact with the source electrode or the drain electrode. The oxygen vacancies bond to hydrogen slightly contained in the film, whereby the region is changed to an n-type region. Thus, the n-type region can serve as a source region or a drain region of the transistor. Alternatively, an oxide semiconductor film may be provided directly under a conductive film which is to be the source electrode 406a and the drain electrode 406b and may be changed to an n-type oxide semiconductor film having a low-resistance region to reduce a contact resistance.
The n-type region is illustrated in the enlarged cross-sectional view (a cross section taken along the channel length direction) of the transistor in FIG. 3. A boundary 435 indicated by a dotted line in the second oxide semiconductor film 404b is a boundary between an intrinsic semiconductor region and an n-type semiconductor region. In the second oxide semiconductor film 404b, a region near and in contact with the source electrode 406a or the drain electrode 406b becomes an n-type region. Note that the boundary 435 is schematically illustrated here, but actually, the boundary is not clearly seen in some cases. Although FIG. 3 shows that the boundary 435 extends in the lateral direction in the second oxide semiconductor film 404b, a region in the second oxide semiconductor film 404b that is sandwiched between the source electrode 406a or the drain electrode 406b and the first oxide semiconductor film 404a becomes an n-type region entirely in the thickness direction, in some cases. Furthermore, although not shown, an n-type region is formed in the first oxide semiconductor film 404a or the third oxide semiconductor film 404c in some cases.
In the case of forming a transistor with an extremely short channel length, an n-type region which is formed by the generation of oxygen vacancies might extend in the channel length direction of the transistor, causing a short-circuit. In that case, the electrical characteristics of the transistor are changed by a threshold voltage shift; for example, on and off of the transistor cannot be controlled with a gate voltage at a practical level (in which case the transistor is on). Accordingly, when a transistor with an extremely short channel length is formed, it is not always preferable that a conductive material which is easily bonded to oxygen be used for a source electrode and a drain electrode.
In such a case, a conductive material which is not easily bonded to oxygen than the above material is preferably used for the source electrode 406a and the drain electrode 406b. As the conductive material which is not easily bonded to oxygen, for example, a material containing tantalum nitride, titanium nitride, or ruthenium, or the like can be used. As a structure in which the conductive material is in contact with the second oxide semiconductor film 404b, a stack including the conductive material and the aforementioned conductive material which is easily bonded to oxygen may be used.
The gate insulating film 408 can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The gate insulating film 408 may be a stack including any of the above materials.
For the gate electrode 410, a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or the like can be used. The gate electrode may be a stack of any of the above materials. Alternatively, a conductive film containing nitrogen may be used for the gate electrode 410.
The oxide insulating film 412 may be formed over the gate insulating film 408 and the gate electrode 410. The oxide insulating film can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The oxide insulating film may be a stack of any of the above materials.
Here, the oxide insulating film 412 preferably contains excess oxygen. An oxide insulating film containing excess oxygen refers to an oxide insulating film from which oxygen can be released by heat treatment or the like. The oxide insulating film containing excess oxygen is preferably a film of which the amount of released oxygen when converted into oxygen atoms is 1.0×1019 atoms/cm3 or more in thermal desorption spectroscopy analysis performed such that the surface temperature is higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. Oxygen released from the oxide insulating film can be diffused to the channel formation region in the multilayer film 404 through the gate insulating film 408, so that oxygen vacancies formed in the channel formation region can be filled with the oxygen. In this manner, stable electrical characteristics of the transistor can be achieved.
An aluminum oxide film is preferably used for the oxide insulating film 412. The aluminum oxide film has not only a function of supplying oxygen but also a function of blocking hydrogen, water, and oxygen. Alternatively, an aluminum oxide film containing silicon oxide, which is formed using a target in which aluminum oxide and silicon oxide are mixed, can be used. In that case, the content of silicon oxide is preferably greater than or equal to 0.1 weight % and less than or equal to 30 weight %.
High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of the electrical characteristics of the transistor. In particular, a reduction in the on-state current, which is directly caused by a decrease in channel width, is significant.
However, in the transistor of one embodiment of the present invention, as described above, the third oxide semiconductor film 404c is formed so as to cover a region where the channel is formed in the second oxide semiconductor film 404b, and a channel formation layer and the gate insulating film are not in contact with each other. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating film can be reduced and the field-effect mobility of the transistor can be increased.
In the case where an oxide semiconductor film is an intrinsic or substantially intrinsic oxide semiconductor film, it is concerned that the field-effect mobility is decreased because of a reduction in the number of carriers in the oxide semiconductor film. However, in the transistor of one embodiment of the present invention, a gate electric field is applied to the oxide semiconductor film not only in the vertical direction but also from the side surfaces. That is, the gate electric field is applied to the whole of the oxide semiconductor film, whereby current flows in the bulk of the oxide semiconductor film. Consequently, it is possible to improve the field-effect mobility of a transistor and suppress variations in electrical characteristics of the transistor due to a highly purified intrinsic oxide semiconductor film.
In the transistor of one embodiment of the present invention, the second oxide semiconductor film 404b is formed over the first oxide semiconductor film 404a, so that an interface state is less likely to be formed. In addition, impurities do not enter the second oxide semiconductor film 404b from above and below because the second oxide semiconductor film 404b is an intermediate layer in a three-layer structure. With the structure in which the second oxide semiconductor film 404b is surrounded by the first oxide semiconductor film 404a and the third oxide semiconductor film 404c (or the second oxide semiconductor film 404b is electrically covered by the gate electrode 410), on-state current of the transistor is increased as described above, and in addition, threshold voltage can be stabilized and an S value can be reduced. Thus, Icut (drain current when gate voltage VG is 0 V) can be reduced and power consumption can be reduced. Further, the threshold voltage of the transistor becomes stable; thus, long-term reliability of the semiconductor device can be improved.
A transistor 460 illustrated in FIGS. 4A to 4C can be used. FIGS. 4A to 4C are a top view and cross-sectional views which illustrate the transistor 460. FIG. 4A is the top view. FIG. 4B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 4A. FIG. 4C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 4A. Note that for simplification of the drawing, some components in the top view in FIG. 4A are not illustrated.
In the transistor 460 shown in FIGS. 4A to 4C, a conductive film 401 is provided between the base insulating film 402 and the substrate 400. When the conductive film 401 is used as a second gate electrode, the on-state current can be further increased or the threshold voltage can be controlled. In order to increase the on-state current, for example, as shown in FIGS. 4A to 4C, the gate electrode 410 and the conductive film 401 are electrically connected to each other to have the same potential, and the transistor is driven as a dual-gate transistor. Alternatively, to control the threshold voltage, the gate electrode 410 and the conductive film 401 are not electrically connected to each other, so that a fixed potential, which is different from a potential of the gate electrode 410, is supplied to the conductive film 401.
A transistor 470 illustrated in FIGS. 5A to 5C can be used. FIGS. 5A to 5C are a top view and cross-sectional views which illustrate the transistor 470. FIG. 5A is the top view. FIG. 5B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 5A. FIG. 5C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 5A. Note that for simplification of the drawing, some components are not illustrated in the top view of FIG. 5A.
The transistor 470 has a structure in which a top surface of the second oxide semiconductor film 404b does not have a flat portion in the channel width direction as shown in FIG. 5C. In this case, a curvature radius r3 of an end portion of the top surface is greater than 0 and less than or equal to the channel width W (0<r3≦W), preferably greater than 0 and less than or equal to a half of the channel width W (0<r3≦W/2).
A transistor 480 illustrated in FIGS. 6A to 6C can be used. FIGS. 6A to 6C are a top view and cross-sectional views which illustrate the transistor 480. FIG. 6A is the top view. FIG. 6B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 6A. FIG. 6C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 6A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 6A.
The transistor 480 has a structure in which the base insulating film 402 is not overetched when the source electrode 406a and the drain electrode 406b are formed.
In order to prevent the base insulating film 402 from being overetched, the etching selectivity ratio of the conductive film to be the source electrode 406a and the drain electrode 406b with respect to the base insulating film 402 is increased.
In the transistor 480, a perpendicular distance H is the difference of the thickness t1 of the first oxide semiconductor film 404a from the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W.
In each of the structures described in this embodiment, the second oxide semiconductor film is provided between the first oxide semiconductor film and the third oxide semiconductor film. However, one embodiment of the present invention is not limited to the structures. A structure in which the first oxide semiconductor film and the third oxide semiconductor film are not included and only the second oxide semiconductor film is electrically covered by the gate electrode may be used.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 2]
In this embodiment, a method for manufacturing the transistor 450, which is described in Embodiment 1 with reference to FIGS. 1A to 1C, is described with reference to FIGS. 7A to 7C and FIGS. 8A to 8C.
First, the base insulating film 402 is formed over the substrate 400 (see FIG. 7A).
For the substrate 400, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, a silicon-on-insulator (SOI) substrate, or the like can be used. Further alternatively, any of these substrates further provided with a semiconductor element can be used.
The base insulating film 402 can be formed by a plasma CVD method, a sputtering method, or the like using an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a film in which any of the above materials are mixed. Alternatively, a stack including any of the above materials may be used, and at least an upper layer of the base insulating film 402 which is in contact with the multilayer film 404 is preferably formed using a material containing excess oxygen that might serve as a supply source of oxygen to the multilayer film 404.
Oxygen may be added to the base insulating film 402 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen enables the base insulating film 402 to supply oxygen much easily to the multilayer film 404.
In the case where a surface of the substrate 400 is made of an insulator and there is no influence of impurity diffusion to the multilayer film 404 to be formed later, the base insulating film 402 is not necessarily provided.
Next, the first oxide semiconductor film 404a and the second oxide semiconductor film 404b are formed over the base insulating film 402 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method (see FIG. 7B). At this time, as shown in FIG. 7B, the base insulating film 402 can be slightly over-etched. By over-etching of the base insulating film 402, the gate electrode 410 to be formed later can cover the third oxide semiconductor film 404c easily.
For processing the first oxide semiconductor film 404a and the second oxide semiconductor film 404b into island shapes, first, a film to be a hard mask (e.g., a tungsten film) and a resist mask are provided over the second oxide semiconductor film 404b, and the film to be a hard mask is etched to form a hard mask. Then, the resist mask is removed, and etching of the first oxide semiconductor film 404a and the second oxide semiconductor film 404b is performed using the hard mask, which is followed by removal of the hard mask. At the time of the etching, an end portion of the hard mask is gradually reduced as the etching progresses; as a result, the end portion of the hard mask is rounded to have a curved surface. Accordingly, the end portion of the second oxide semiconductor film 404b is rounded to have a curved surface. With this structure, the coverage with the third oxide semiconductor film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412, which are to be formed over the second oxide semiconductor film 404b, can be improved; thus, occurrence of a shape defect such as disconnection can be inhibited. In addition, electric field concentration which might occur at the end portions of the source electrode 406a and the drain electrode 406b can be reduced, which can suppress deterioration of the transistor.
In order to form a continuous energy band in a stack including the first oxide semiconductor film 404a and the second oxide semiconductor film 404b, or a stack including the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c to be formed in a later step, the layers need to be formed successively without exposure to the air with the use of a multi-chamber deposition apparatus (e.g., a sputtering apparatus) including a load lock chamber. It is preferable that each chamber of the sputtering apparatus be able to be evacuated to a high vacuum (to approximately higher than or equal to 5×10−7 Pa and lower than or equal to 1×10−4 Pa) by an adsorption vacuum evacuation pump such as a cryopump and that the chamber be able to heat a substrate over which a film is to be deposited to 100° C. or higher, preferably 500° C. or higher, so that water and the like acting as impurities of an oxide semiconductor are removed as much as possible. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas containing a carbon component, moisture, or the like from an evacuation system into the chamber.
Not only high vacuum evacuation of the chamber but also high purity of a sputtering gas is necessary to obtain a highly purified intrinsic oxide semiconductor. An oxygen gas or an argon gas used as the sputtering gas is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, further preferably −100° C. or lower, so that entry of moisture and the like into the oxide semiconductor film can be prevented as much as possible.
The materials described in Embodiment 1 can be used for the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c that is to be formed in a later step. For example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:4 or 1:3:2 can be used for the first oxide semiconductor film 404a, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 can be used for the second oxide semiconductor film 404b, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:4 or 1:3:2 can be used for the third oxide semiconductor film 404c. 
An oxide semiconductor that can be used for each of the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c preferably contains at least indium (In) or zinc (Zn). Alternatively, the oxide semiconductor preferably contains both In and Zn. In order to reduce variations in the electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to In and/or Zn.
Examples of a stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other examples of a stabilizer are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).
As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn oxide, a Sn—Zn oxide, an Al—Zn oxide, a Zn—Mg oxide, a Sn—Mg oxide, an In—Mg oxide, an In—Ga oxide, an In—Ga—Zn oxide, an In—Al—Zn oxide, an In—Sn—Zn oxide, a Sn—Ga—Zn oxide, an Al—Ga—Zn oxide, a Sn—Al—Zn oxide, an In—Hf—Zn oxide, an In—La—Zn oxide, an In—Ce—Zn oxide, an In—Pr—Zn oxide, an In—Nd—Zn oxide, an In—Sm—Zn oxide, an In—Eu—Zn oxide, an In—Gd—Zn oxide, an In—Tb—Zn oxide, an In—Dy—Zn oxide, an In—Ho—Zn oxide, an In—Er—Zn oxide, an In—Tm—Zn oxide, an In—Yb—Zn oxide, an In—Lu—Zn oxide, an In—Sn—Ga—Zn oxide, an In—Hf—Ga—Zn oxide, an In—Al—Ga—Zn oxide, an In—Sn—Al—Zn oxide, an In—Sn—Hf—Zn oxide, and an In—Hf—Al—Zn oxide.
Note that here, for example, an “In—Ga—Zn oxide” means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain a metal element other than In, Ga, and Zn. Further, in this specification, a film formed using an In—Ga—Zn oxide is also referred to as an IGZO film
Alternatively, a material represented by InMO3(ZnO)m (m>0, where m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Further alternatively, a material represented by In2SnO5(ZnO)n (n>0, where n is an integer) may be used.
Note that as described in Embodiment 1 in detail, materials are selected so that the first oxide semiconductor film 404a and the third oxide semiconductor film 404c each have an electron affinity lower than that of the second oxide semiconductor film 404b. 
The oxide semiconductor films are each preferably formed by a sputtering method. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In particular, a DC sputtering method is preferably used because dust generated in the deposition can be reduced and the film thickness can be uniform.
In the case of using an In—Ga—Zn oxide, a material whose atomic ratio of In to Ga and Zn is any of 1:1:1, 2:2:1, 3:1:2, 1:3:2, 1:3:4, 1:4:3, 1:5:4, 1:6:6, 2:1:3 1:6:4, 1:9:6, 1:1:4, and 1:1:2 is used for the first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and/or the third oxide semiconductor film 404c so that the first oxide semiconductor film 404a and the third oxide semiconductor film 404c each have an electron affinity lower than that of the second oxide semiconductor film 404b. 
Note that for example, in the case where the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1), is in the neighborhood of the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1), a, b, and c satisfy the following relation: (a−A)2+(b−B)2+(c−C)2≦r2, and r may be 0.05, for example. The same applies to other oxides.
The indium content of the second oxide semiconductor film 404b is preferably higher than the indium content of the first oxide semiconductor film 404a and the indium content of the third oxide semiconductor film 404c. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Thus, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga. For this reason, with the use of an oxide having a high indium content for the second oxide semiconductor film 404b, a transistor having high mobility can be achieved.
A structure of an oxide semiconductor film is described below.
Note that in this specification, a term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.
In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.
An oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.
First, a CAAC-OS film is described.
The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm.
In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.
According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a film formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the film formation surface or the top surface of the CAAC-OS film.
On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan-view TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.
From the results of the cross-sectional TEM image and the plan-view TEM image, alignment is found in the crystal parts in the CAAC-OS film.
A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO4 crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO4 crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the film formation surface or the top surface of the CAAC-OS film.
On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO4 crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO4, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56°.
According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a film formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.
Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a film formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a film formation surface or a normal vector of a top surface of the CAAC-OS film.
Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the film formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.
Note that when the CAAC-OS film with an InGaZnO4 crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appears at around 31° and a peak of 2θ do not appear at around 36°.
The CAAC-OS film is an oxide semiconductor film having low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element that has higher bonding strength to oxygen than a metal element included in the oxide semiconductor film, such as silicon, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and causes a decrease in crystallinity. Further, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.
The CAAC-OS film is an oxide semiconductor film having a low density of defect states. In some cases, oxygen vacancies in the oxide semiconductor film serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.
The state in which impurity concentration is low and density of defect states is low (the amount of oxygen vacancies is small) is referred to as a “highly purified intrinsic” or “substantially highly purified intrinsic” state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has little variation in electrical characteristics and high reliability. Electric charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released, and might behave like fixed electric charge. Thus, the transistor which includes the oxide semiconductor film having high impurity concentration and a high density of defect states has unstable electrical characteristics in some cases.
With the use of the CAAC-OS film in a transistor, variation in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small.
Next, a microcrystalline oxide semiconductor film is described.
In an image obtained with the TEM, crystal parts cannot be found clearly in the microcrystalline oxide semiconductor in some cases. In most cases, a crystal part in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor film including nanocrystal (nc), which is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm, is specifically referred to as a nanocrystalline oxide semiconductor (nc-OS) film. In an image obtained with TEM, a crystal grain cannot be found clearly in the nc-OS film in some cases.
In the nc-OS film, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic order. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than that of a crystal part, a peak which shows a crystal plane does not appear. Further, a halo pattern is shown in a selected-area electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter larger than the diameter of a crystal part (e.g., larger than or equal to 50 nm). Meanwhile, spots are shown in a nanobeam electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter (e.g., larger than or equal to 1 nm and smaller than or equal to 30 nm) close to, or smaller than or equal to the diameter of a crystal part. Further, in a nanobeam electron diffraction pattern of the nc-OS film, regions with high luminance in a circular (ring) pattern are observed in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are shown in a ring-like region in some cases.
The nc-OS film is an oxide semiconductor film that has high regularity as compared to an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film; hence, the nc-OS film has a higher density of defect states than the CAAC-OS film.
Note that an oxide semiconductor film may be a stacked film including two or more kinds of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.
For example, a CAAC-OS film can be deposited by sputtering with a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along the a-b plane, and a sputtered particle having a plane parallel to the a-b plane (flat-plate-like sputtered particle or a pellet-like sputtered particle) might be separated from the sputtering target. In this case, the flat-plate-like sputtered particle or the pellet-like sputtered particle is electrically charged and thus reaches a substrate while maintaining its crystal state without being aggregated in plasma, whereby a CAAC-OS film can be formed.
First heat treatment may be performed after the second oxide semiconductor film 404b is formed. The first heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced pressure state. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, in order to compensate desorbed oxygen. By the first heat treatment, the crystallinity of the second oxide semiconductor film 404b can be improved, and in addition, impurities such as hydrogen and water can be removed from the base insulating film 402 and the first oxide semiconductor film 404a. Note that the first heat treatment may be performed before etching for formation of the second oxide semiconductor film 404b. 
A first conductive film to be the source electrode 406a and the drain electrode 406b is formed over the first oxide semiconductor film 404a and the second oxide semiconductor film 404b. For the first conductive film, Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material containing any of these as its main component can be used. For example, a 100-nm-thick titanium film is formed by a sputtering method or the like. Alternatively, a tungsten film may be formed by a CVD method.
Then, the first conductive film is etched so as to be divided over the second oxide semiconductor film 404b to form the source electrode 406a and the drain electrode 406b (see FIG. 7C).
Next, a third oxide semiconductor film 403c is formed over the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b. 
Note that second heat treatment may be performed after the third oxide semiconductor film 403c is formed. The second heat treatment can be performed in a condition similar to that of the first heat treatment. The second heat treatment can remove impurities such as hydrogen and water from the third oxide semiconductor film 403c. In addition, impurities such as hydrogen and water can be further removed from the first oxide semiconductor film 404a and the second oxide semiconductor film 404b. 
Next, an insulating film 407 to be the gate insulating film 408 is formed over the third oxide semiconductor film 403c (see FIG. 8A). The insulating film 407 can be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like. The insulating film 407 may be a stack including any of the above materials. The insulating film 407 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like.
Then, a second conductive film 409 to be the gate electrode 410 is formed over the insulating film 407 (see FIG. 8B). For the second conductive film 409, a conductive film including Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or an alloy material containing any of these as its main component can be used. The second conductive film 409 can be formed by a sputtering method, a CVD method, or the like. The second conductive film 409 may be formed using a conductive film containing nitrogen or a stack including the conductive film and a conductive film containing nitrogen.
After that, the second conductive film 409 is selectively etched using a resist mask to form the gate electrode 410 (see FIG. 8C). Note that as shown in FIG. 1C, the sum of the height h1 of the projected portion of the base insulating film 402 and the thickness t1 of the first oxide semiconductor film 404a (h1+t1) is set larger than the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). Thus, the gate electrode 410 is formed so as to electrically cover the second oxide semiconductor film 404b in the channel width direction.
In the transistor 450, the perpendicular distance H is the difference of the sum of the height h1 of the projected portion of the base insulating film 402 and the thickness t1 of the first oxide semiconductor film 404a (h1+t1) from the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W, more preferably greater than 0 nm and less than the thickness t1 of the first oxide semiconductor film 404a. Since the gate electrode 410 extending lower than the interface between the first oxide semiconductor film 404a and the second oxide semiconductor film 404b and reaching a position on the base insulating film 402 side does not affect the channel width W, the channel width W can be made small, achieving high density (high integration).
Then, the insulating film 407 is selectively etched using the resist mask or the gate electrode 410 as a mask to form the gate insulating film 408.
Next, the third oxide semiconductor film 403c is etched using the resist mask or the gate electrode 410 as a mask to form the third oxide semiconductor film 404c. 
A top end portion of the third oxide semiconductor film 404c is aligned with a bottom end portion of the gate insulating film 408. A top end portion of the gate insulating film 408 is aligned with a bottom end portion of the gate electrode 410. Although the gate insulating film 408 and the third oxide semiconductor film 404c are formed using the gate electrode 410 as a mask, the gate insulating film 408 and the third oxide semiconductor film 404c may be formed before the second conductive film 409 is formed, for example.
Next, the oxide insulating film 412 is formed over the source electrode 406a, the drain electrode 406b, and the gate electrode 410 (see FIGS. 1B and 1C). A material and a formation method of the oxide insulating film 412 can be similar to those of the base insulating film 402. The oxide insulating film 412 may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or an oxide insulating film containing nitrogen. The oxide insulating film 412 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method, and is preferably formed to contain excess oxygen so as to be able to supply oxygen to the multilayer film 404.
Oxygen may be added to the oxide insulating film 412 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen enables the oxide insulating film 412 to supply oxygen much easily to the multilayer film 404.
Next, third heat treatment may be performed. The third heat treatment can be performed under a condition similar to that of the first heat treatment. By the third heat treatment, excess oxygen is easily released from the base insulating film 402, the gate insulating film 408, and the oxide insulating film 412, so that oxygen vacancies in the multilayer film 404 can be reduced.
Through the above process, the transistor 450 illustrated in FIGS. 1A to 1C can be manufactured.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 3]
In this embodiment, a transistor having a structure different from that of the transistor described in Embodiment 1 is described.
FIGS. 9A to 9C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention. FIG. 9A is the top view. FIG. 9B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 9A. FIG. 9C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 9A. Note that for simplification of the drawing, some components in the top view in FIG. 9A are not illustrated. In some cases, the direction of the dashed-dotted line A-B is referred to as a channel length direction, and the direction of the dashed-dotted line C-D is referred to as a channel width direction.
A transistor 550 illustrated in FIGS. 9A to 9C includes the base insulating film 402 having the depressed portion and the projected portion over the substrate 400; the first oxide semiconductor film 404a and the second oxide semiconductor film 404b over the projected portion of the base insulating layer 402; the source electrode 406a and the drain electrode 406b over the first oxide semiconductor film 404a and the second oxide semiconductor film 404b; the third oxide semiconductor film 404c in contact with the bottom surface of the depressed portion of the base insulating film 402, the side surface of the projected portion of the base insulating film 402, the side surface of the first oxide semiconductor film 404a, the side surface of the second oxide semiconductor film 404b, the top surface of the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b; the gate insulating film 408 over the third oxide semiconductor film 404c; the gate electrode 410 which is in contact with a top surface of the gate insulating film 408 and faces the top surface of the second oxide semiconductor film 404b and the side surface of the second oxide semiconductor film 404b; and the oxide insulating film 412 over the source electrode 406a, the drain electrode 406b, and the gate electrode 410. The first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c are collectively referred to as a multilayer film 404.
Note that a channel length refers to a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor film and a gate electrode overlap with each other in a top view. Accordingly, in FIG. 9A, a channel length (L) is a distance between the source electrode 406a and the drain electrode 406b in a region where the second oxide semiconductor film 404b and the gate electrode 410 overlap with each other. A channel width refers to a length of a portion where a source and a drain face each other and where a semiconductor film and a gate electrode overlap with each other. Accordingly, in FIG. 9A, a channel width (W) is a length of a portion where the source electrode 406a and the drain electrode 406b face each other and where the second oxide semiconductor film 404b and the gate electrode 410 overlap with each other.
In the transistor 550, a perpendicular distance H is the difference of the sum of the height h1 of the projected portion of the base insulating film 402 from the bottom surface of the depressed portion of the base insulating film 402 and the thickness t1 of the first oxide semiconductor film 404a (h1+t1) from the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W, more preferably greater than 0 nm and less than the thickness t1 of the first oxide semiconductor film 404a. 
With such a structure, the gate electrode 410 can electrically surround the second oxide semiconductor film 404b when seen in the channel width direction, so that on-state current can be increased.
Miniaturization of a transistor leads to high integration and high density. In the miniaturization, for example, the channel length of the transistor is set to be less than or equal to 100 nm, preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm, and the channel width of the transistor is set to be less than or equal to 100 nm, preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm. The transistor of one embodiment of the present invention has an s-channel structure. Therefore, even when the channel width is shortened to the above range, high on-state current can be obtained.
Furthermore, in this embodiment, the oxide semiconductor film has angular end portions. The angular end portions can be obtained such that, when a film is processed using a resist mask or a hard mask, an etching selectivity ratio of the film to be processed to the resist mask or the hard mask is set high.
A transistor 560 illustrated in FIGS. 10A to 10C can be used. FIGS. 10A to 10C are a top view and cross-sectional views which illustrate the transistor 560. FIG. 10A is the top view. FIG. 10B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 10A. FIG. 10C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 10A. Note that for simplification of the drawing, some components in the top view in FIG. 10A are not illustrated.
In the transistor 560 illustrated in FIGS. 10A to 10C, the conductive film 401 is provided between the base insulating film 402 and the substrate 400. When the conductive film 401 is used as a second gate electrode, the on-state current can be further increased and the threshold voltage can be controlled. In order to increase the on-state current, for example, as shown in FIGS. 10A to 10C, the gate electrode 410 and the conductive film 401 are electrically connected to each other to have the same potential, and the transistor is driven as a dual-gate transistor. Alternatively, to control the threshold voltage, the gate electrode 410 and the conductive film 401 are not electrically connected to each other, so that a fixed potential, which is different from a potential of the gate electrode 410, is supplied to the conductive film 401.
A transistor 570 illustrated in FIGS. 11A to 11C can be used. FIGS. 11A to 11C are a top view and cross-sectional views which illustrate the transistor 570. FIG. 11A is the top view. FIG. 11B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 11A. FIG. 11C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 11A. Note that for simplification of the drawing, some components in the top view in FIG. 11A are not illustrated.
The transistor 570 has a structure in which the base insulating film 402 is not overetched when the source electrode 406a and the drain electrode 406b are formed.
In order to prevent the base insulating film 402 from being overetched, the etching selectivity ratio of the conductive film to be the source electrode 406a and the drain electrode 406b with respect to the base insulating film 402 is increased.
In the transistor 570, a perpendicular distance H is the difference of the thickness t1 of the first oxide semiconductor film 404a from the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W.
In each of the structures described in this embodiment, the second oxide semiconductor film is provided between the first oxide semiconductor film and the third oxide semiconductor film. However, one embodiment of the present invention is not limited to the structures. A structure in which the first oxide semiconductor film and the third oxide semiconductor film are not included and only the second oxide semiconductor film is electrically covered by the gate electrode may be used.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 4]
In this embodiment, a method for manufacturing the transistor 550 described in Embodiment 3 with reference to FIGS. 9A to 9C is described with reference to FIGS. 12A to 12C and FIGS. 13A to 13C.
First, the base insulating film 402 is formed over the substrate 400 (see FIG. 12A). The above embodiments can be referred to for materials and formation methods of the substrate 400 and the base insulating film 402.
Next, the first oxide semiconductor film 404a and the second oxide semiconductor film 404b are formed over the base insulating film 402 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method (see FIG. 12B). At this time, as shown in FIG. 12B, the base insulating film 402 can be slightly over-etched. By over-etching of the base insulating film 402, the gate electrode 410 to be formed later can cover the third oxide semiconductor film 404c easily. The above embodiments can be referred to for materials and formation methods of the first oxide semiconductor film 404a and the second oxide semiconductor film 404b. 
For processing the first oxide semiconductor film 404a and the second oxide semiconductor film 404b into island shapes, first, a film to be a hard mask and a resist mask are provided over the second oxide semiconductor film 404b, and the film to be a hard mask is etched to form a hard mask. Then, the resist mask is removed, and the first oxide semiconductor film 404a and the second oxide semiconductor film 404b are etched using the hard mask, which is followed by removal of the hard mask. At this time, the etching is performed with a high selectivity ratio so that end portions of the hard mask can be prevented from being reduced in size. Thus, the second oxide semiconductor film 404b has angular end portions.
Then, the first conductive film is etched so as to be divided over the second oxide semiconductor film 404b to form the source electrode 406a and the drain electrode 406b (see FIG. 12C). The above embodiments can be referred to for materials and formation methods of the source electrode 406a and the drain electrode 406b. 
Next, the third oxide semiconductor film 403c is formed over the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b, and the insulating film 407 which is to be the gate insulating film 408 is formed over the third oxide semiconductor film 403c (see FIG. 13A). The above embodiments can be referred to for materials and formation methods of the third oxide semiconductor film 403c and the insulating film 407.
Then, the second conductive film 409 to be the gate electrode 410 is formed over the insulating film 407 (see FIG. 13B). The above embodiments can be referred to for materials and formation methods of the second conductive film 409.
After that, the second conductive film 409 is selectively etched using a resist mask to form the gate electrode 410 (see FIG. 13C). Note that as shown in FIG. 9C, the sum of the height h1 of the projected portion of the base insulating film 402 from the bottom surface of the depressed portion of the base insulating film 402 and the thickness t1 of the first oxide semiconductor film 404a (h1+t1) is set larger than the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). Thus, the gate electrode 410 is formed so as to electrically cover the second oxide semiconductor film 404b. 
In the transistor 550, a perpendicular distance H is the difference of the sum of the height h1 of the projected portion of the base insulating film 402 from the bottom surface of the depressed portion of the base insulating film 402 and the thickness t1 of the first oxide semiconductor film 404a (h1+t1) from the sum of the thickness t3 of the third oxide semiconductor film 404c and the thickness tGI of the gate insulating film 408 (t3+tGI). The perpendicular distance H is greater than 0 nm, preferably greater than or equal to 5% of the channel width W and less than 300% of the channel width W, more preferably greater than or equal to 10% of the channel width W and less than 300% of the channel width W. When the perpendicular distance H is too large and the sum of the thickness of the first oxide semiconductor film 404a and the thickness of the second oxide semiconductor film 404b is fixed, the second oxide semiconductor film 404b has a small thickness, leading to low productivity and low coverage with a film. Thus, the perpendicular distance H is preferably greater than 0 nm and less than the channel width W, more preferably greater than 0 nm and less than the thickness t1 of the first oxide semiconductor film 404a. Since the gate electrode 410 extending lower than the interface between the first oxide semiconductor film 404a and the second oxide semiconductor film 404b and reaching a position on the base insulating film 402 side does not affect the channel width W, the channel width W can be made small, achieving high density (high integration).
Then, the insulating film 407 is selectively etched using the resist mask or the gate electrode 410 as a mask to form the gate insulating film 408.
Next, the third oxide semiconductor film 403c is etched using the resist mask or the gate electrode 410 as a mask to form the third oxide semiconductor film 404c. 
The top end portion of the third oxide semiconductor film 404c is aligned with the bottom end portion of the gate insulating film 408. The top end portion of the gate insulating film 408 is aligned with the bottom end portion of the gate electrode 410. Although the gate insulating film 408 and the third oxide semiconductor film 404c are formed using the gate electrode 410 as a mask, the gate insulating film 408 and the third oxide semiconductor film 404c may be formed before the second conductive film 409 is formed, for example.
Next, the oxide insulating film 412 is formed over the source electrode 406a, the drain electrode 406b, and the gate electrode 410 (see FIGS. 9B and 9C). The above embodiments can be referred to for a material and a formation method of the oxide insulating film 412.
Through the above process, the transistor 550 illustrated in FIGS. 9A to 9C can be manufactured.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 5]
In this embodiment, a transistor having a structure different from those of the transistors described in Embodiments 1 and 3 is described.
FIGS. 20A to 20C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention. FIG. 20A is the top view. FIG. 20B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 20A. FIG. 20C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 20A. Note that for simplification of the drawing, some components in the top view in FIG. 20A are not illustrated. In some cases, the direction of the dashed-dotted line A-B is referred to as a channel length direction, and the direction of the dashed-dotted line C-D is referred to as a channel width direction.
In a transistor 490 illustrated in FIGS. 20A to 20C, n-type fourth oxide semiconductor films 404d are provided directly under the source electrode 406a and the drain electrode 406b unlike in the transistor 450 of Embodiment 1. The fourth oxide semiconductor films 404d have a function of reducing a contact resistance with the multilayer film 404. The second oxide semiconductor film 404b is partly etched at the time of etching of the source electrode 406a and the drain electrode 406b. The third oxide semiconductor film 404c covers the source electrode 406a and the drain electrode 406b. The oxide insulating film 412 may be formed using a film capable of releasing oxygen by heat treatment or the like, and a barrier film 414 having a function of suppressing the release of oxygen to the outside may be provided over the oxide insulating film 412. The barrier film 414 is preferably formed using an aluminum oxide film. The aluminum oxide film has a blocking effect against hydrogen, water, and oxygen. An aluminum oxide film containing silicon oxide, which is formed using a target in which aluminum oxide and silicon oxide are mixed, can be used. In that case, the content of silicon oxide is preferably greater than or equal to 0.1 weight % and less than or equal to 30 weight %.
Furthermore, In—Ga—Zn oxide can be used for the fourth oxide semiconductor films 404d; for example, a material whose atomic ratio of In to Ga and Zn is 3:1:2 can be used. The thickness of the fourth oxide semiconductor film 404d is preferably less than or equal to 10 nm, more preferably less than or equal to 5 nm.
Next, a method for manufacturing the transistor 490 is described with reference to FIGS. 7A and 7B and FIGS. 21A to 21C.
First, the base insulating film 402, the first oxide semiconductor film 404a, and the second oxide semiconductor film 404b are formed over the substrate 400 (see FIGS. 7A and 7B). Embodiment 1 can be referred to for materials and formation methods of the substrate 400, the base insulating film 402, the first oxide semiconductor film 404a, and the second oxide semiconductor film 404b. 
Next, a fourth oxide semiconductor film 403d is formed over the base insulating film 402, the first oxide semiconductor film 404a, and the second oxide semiconductor film 404b, and the source electrode 406a and the drain electrode 406b are formed over the fourth oxide semiconductor film 403d (see FIG. 21A).
Next, the fourth oxide semiconductor film 403d is etched using the source electrode 406a and the drain electrode 406b as masks to form the fourth oxide semiconductor films 404d (see FIG. 21B). At this time, the second oxide semiconductor film 404b is partly etched in some cases.
Oxygen is extracted from the fourth oxide semiconductor films 404d to the source electrode 406a and the drain electrode 406b, so that an oxygen vacancy is generated in a region of the fourth oxide semiconductor film 404d that is near and in contact with the source electrode 406a and the drain electrode 406b. The region becomes an n-type region by bonding between the oxygen vacancy and hydrogen slightly contained in the film. The n-type region can serve as a source region or a drain region of the transistor, and a contact resistance with the oxide semiconductor film can be reduced.
Then, the third oxide semiconductor film 403c is formed over the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b (see FIG. 21C).
Next, the insulating film 407 to be the gate insulating film 408 is formed over the third oxide semiconductor film 403c (see FIG. 22A).
Then, the conductive film 409 to be the gate electrode 410 is formed over the insulating film 407 (see FIG. 22B).
Next, the conductive film 409 is selectively etched to form the gate electrode 410 (see FIG. 22C).
Next, the oxide insulating film 412 is formed over the source electrode 406a, the drain electrode 406b, and the gate electrode 410 (see FIGS. 20B and 20C).
Through the above process, the transistor 490 illustrated in FIGS. 20A to 20C can be manufactured.
Note that the oxide semiconductor film may have angular end portions as in Embodiment 3.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 6]
In this embodiment, a transistor having a structure different from those of the transistors described in Embodiments 1, 3, and 5 is described.
FIGS. 23A to 23C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention. FIG. 23A is the top view. FIG. 23B illustrates a cross section taken along the dashed-dotted line A-B in FIG. 23A. FIG. 23C illustrates a cross section taken along the dashed-dotted line C-D in FIG. 23A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 23A. In some cases, the direction of the dashed-dotted line A-B is referred to as a channel length direction, and the direction of the dashed-dotted line C-D is referred to as a channel width direction.
A transistor 850 illustrated in FIGS. 23A to 23C includes a first gate electrode 801 over the substrate 400; the base insulating film 402 having a groove portion; an insulating film 416 provided in contact with the first gate electrode 801 so as to cover at least a part of a top surface of the base insulating film 402 and the groove portion; an insulating film 418 with which the groove portion of the base insulating film 402 is filled and which overlaps the first gate electrode 801 with the insulating film 416 provided therebetween; the first oxide semiconductor film 404a and the second oxide semiconductor film 404b over the insulating film 416 and the insulating film 418; the source electrode 406a and the drain electrode 406b over the first oxide semiconductor film 404a and the second oxide semiconductor film 404b; the third oxide semiconductor film 404c in contact with a top surface of the insulating film 418, the side surface of the first oxide semiconductor film 404a, the side surface of the second oxide semiconductor film 404b, the top surface of the second oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b; the gate insulating film 408 over the third oxide semiconductor film 404c; the gate electrode 410 which is in contact with a top surface of the gate insulating film 408 and faces the top surface of the second oxide semiconductor film 404b and the side surface of the second oxide semiconductor film 404b; and the oxide insulating film 412 over the source electrode 406a, the drain electrode 406b, and the gate electrode 410. The first oxide semiconductor film 404a, the second oxide semiconductor film 404b, and the third oxide semiconductor film 404c are collectively referred to as the multilayer film 404.
In the transistor 850, the insulating film 416 provided between the first gate electrode 801 and the insulating film 418 serves as a gate insulating film. The insulating film 416 can be formed using an aluminum oxide film that can serve as a barrier film and supply oxygen. The insulating film 418 is preferably formed using an oxide insulating film that can supply oxygen. The insulating film 418 can be formed using the material of the oxide insulating film 412 in the above embodiments.
Excess oxygen contained in the aluminum oxide film is released by heat treatment in a manufacturing process of the transistor 850 to be supplied to the second oxide semiconductor film 404b. This heat treatment is not necessarily performed when heat treatment for forming an insulating film and the like over the second oxide semiconductor film 404b is performed. Since the aluminum oxide film is a barrier film against oxygen and hydrogen, the amount of oxygen vacancies is reduced in the second oxide semiconductor film 404b because removal of oxygen is minimized and a sufficient amount of oxygen is supplied thereto, and furthermore, entry of impurities such as hydrogen into the second oxide semiconductor film 404b is reduced. That is, the second oxide semiconductor film 404b is a highly purified intrinsic oxide semiconductor film. The transistor 850 including the highly purified intrinsic (i-type) second oxide semiconductor film 404b has smaller variation in the electrical characteristics and is electrically stable.
The above embodiments can be referred to for a component over the insulating film 416 and the insulating film 418.
Next, a method for manufacturing the transistor 850 is described with reference to FIGS. 24A to 24D.
First, the first gate electrode 801 is formed over the substrate 400, and a base insulating film 402a is formed over the first gate electrode 801 (see FIG. 24A).
Then, the base insulating film 402a is subjected to etch-back treatment or chemical mechanical polishing (CMP) treatment so that part of the first gate electrode 801 is exposed. Note that the CMP treatment and the etch-back treatment may be performed in combination. By the etch-back treatment or the CMP treatment here, part of the base insulating film 402a that is provided over the first gate electrode 801 is removed, so that a base insulating film 402b is formed (see FIG. 24B).
Next, a base insulating film 402c processed into an island-like shape is formed over the base insulating film 402b and the first gate electrode 801, and the insulating film 416 and an insulating film 417 are formed over the first gate electrode 801 and the base insulating film 402c (see FIG. 24C). Note that the base insulating film 402b and the base insulating film 402c are collectively referred to as the base insulating film 402.
After that, the insulating film 417 is subjected to etch-back treatment or CMP treatment so that part of the insulating film 416 is exposed. Note that the CMP treatment and the etch-back treatment may be performed in combination. By the etch-back treatment or the CMP treatment here, part of the insulating film 417 over the insulating film 416 is removed, so that the insulating film 418 is formed (see FIG. 24D).
Next, the first oxide semiconductor film 404a and the second oxide semiconductor film 404b are formed over the insulating film 416 and the insulating film 418. FIG. 7C and FIGS. 8A to 8C of Embodiment 1 can be referred to for methods for forming the source electrode 406a, the drain electrode 406b, the third oxide semiconductor film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412 after the second oxide semiconductor film 404b is formed.
Through the above process, the transistor 850 illustrated in FIGS. 23A to 23C can be manufactured.
Note that the oxide semiconductor film may have angular end portions as in Embodiment 3.
Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.
[Embodiment 7]
In this embodiment, deposition models of a CAAC-OS and an nc-OS are described.
FIG. 25A is a schematic view of the inside of a deposition chamber where a CAAC-OS is deposited by a sputtering method.
A target 230 is attached to a backing plate. Under the target 230 and the backing plate, a plurality of magnets are provided. The plurality of magnets cause a magnetic field over the target 230. A sputtering method in which the deposition rate is increased by utilizing the magnetic field caused by the magnets is called a magnetron sputtering method.
The target 230 has a polycrystalline structure in which a cleavage plane exists in at least one crystal grain. Note that the details of the cleavage plane are described later.
A substrate 220 is placed to face the target 230, and the distance d (also referred to as a target-substrate distance (T-S distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m. The deposition chamber is mostly filled with a deposition gas (e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at 50 vol % or higher) and controlled to be higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa. Here, discharge starts by application of a voltage at a constant value or higher to the target 230, and plasma is observed. Note that the magnetic field over the target 230 forms a high-density plasma region. In the high-density plasma region, the deposition gas is ionized, so that an ion 201 is generated. Examples of the ion 201 include an oxygen cation (O+) and an argon cation (Ar+).
The ion 201 is accelerated toward the target 230 side by an electric field, and collides with the target 230 eventually. At this time, a pellet 200a and a pellet 200b which are flat-plate-like (pellet-like) sputtered particles are separated and sputtered from the cleavage plane. Note that structures of the pellet 200a and the pellet 200b may be distorted by an impact of collision of the ion 201.
The pellet 200a is a flat-plate-like (pellet-like) sputtered particle having a triangle plane, e.g., regular triangle plane. The pellet 200b is a flat-plate-like (pellet-like) sputtered particle having a hexagon plane, e.g., regular hexagon plane. Note that a flat-plate-like (pellet-like) sputtered particle such as the pellet 200a and the pellet 200b is collectively called a pellet 200. The shape of a flat plane of the pellet 200 is not limited to a triangle or a hexagon. For example, the flat plane may have a shape formed by combining greater than or equal to 2 and less than or equal to 6 triangles. For example, a square (rhombus) is formed by combining two triangles (regular triangles) in some cases.
The thickness of the pellet 200 is determined depending on the kind of deposition gas and the like. The thicknesses of the pellets 200 are preferably uniform; the reasons thereof are described later. In addition, it is preferable for the sputtered particle to have a pellet shape with a small thickness than a dice shape with a large thickness.
The pellet 200 receives a charge when passing through the plasma, so that side surfaces thereof are negatively or positively charged in some cases. The pellet 200 includes an oxygen atom on its side surface, and the oxygen atom may be negatively charged. For example, a case in which the pellet 200a includes, on its side surfaces, oxygen atoms that are negatively charged is illustrated in FIG. 27. As in this view, when the side surfaces are charged in the same polarity, charges repel each other, and accordingly, the pellet 200a can maintain a flat-plate shape. In the case where a CAAC-OS is an In—Ga—Zn oxide, there is a possibility that an oxygen atom bonded to an indium atom is negatively charged. There is another possibility that an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged.
As illustrated in FIG. 25A, the pellet 200 flies like a kite in plasma and flutters up to the substrate 220. Since the pellets 200 are charged, when the pellet 200 gets close to a region where another pellet 200 has already been deposited, repulsion is generated. Here, above the substrate 220, a magnetic field is generated in a direction parallel to a top surface of the substrate 220. A potential difference is given between the substrate 220 and the target 230, and accordingly, current flows from the substrate 220 toward the target 230. Thus, the pellet 200 is given a force (Lorentz force) on a surface of the substrate 220 by an effect of the magnetic field and the current (see FIG. 28). This is explainable with Fleming's left-hand rule. In order to increase a force applied to the pellet 200, it is preferable to provide, on the top surface, a region where the magnetic field in a direction parallel to the top surface of the substrate 220 is 10 G or higher, preferably 20 G or higher, further preferably 30 G or higher, still further preferably 50 G or higher. Alternatively, it is preferable to provide, on the top surface, a region where the magnetic field in a direction parallel to the top surface of the substrate 220 is 1.5 times or higher, preferably twice or higher, further preferably 3 times or higher, still further preferably 5 times or higher as high as the magnetic field in a direction perpendicular to the top surface of the substrate 220.
Further, the substrate 220 is heated, and the resistance such as friction between the pellet 200 and the substrate 220 is low. As a result, as illustrated in FIG. 29A, the pellet 200 glides above the surface of the substrate 220. The glide of the pellet 200 is caused in a state where the flat plane faces the substrate 220. Then, as illustrated in FIG. 29B, when the pellet 200 reaches the side surface of another pellet 200 that has been already deposited, the side surfaces of the pellets 200 are bonded. At this time, the oxygen atom on the side surface of the pellet 200 is released. With the released oxygen atom, oxygen vacancies in a CAAC-OS is filled in some cases; thus, the CAAC-OS has a low density of defect states.
Further, the pellet 200 is heated on the substrate 220, whereby atoms are rearranged, and the structure distortion caused by the collision of the ion 201 can be reduced. The pellet 200 whose structure distortion is reduced is substantially single crystal. Even when the pellets 200 are heated after being bonded, expansion and contraction of the pellet 200 itself hardly occurs, which is caused by turning the pellet 200 to be substantially single crystal. Thus, formation of defects such as a grain boundary due to expansion of a space between the pellets 200 can be prevented, and accordingly, generation of crevasses can be prevented. Further, the space is filled with elastic metal atoms and the like, whereby the elastic metal atoms have a function, like a highway, of jointing side surfaces of the pellets 200 which are not aligned with each other.
It is considered that as shown in such a model, the pellets 200 are deposited on the substrate 220. Thus, a CAAC-OS film can be deposited even when a surface over which a film is formed (film formation surface) does not have a crystal structure, which is different from film deposition by epitaxial growth. For example, even when a surface (film formation surface) of the substrate 220 has an amorphous structure, a CAAC-OS film can be formed.
Further, it is found that in formation of the CAAC-OS, the pellets 200 are arranged in accordance with a surface shape of the substrate 220 that is the film formation surface even when the film formation surface has unevenness besides a flat surface. For example, in the case where the surface of the substrate 220 is flat at the atomic level, the pellets 200 are arranged so that flat planes parallel to the a-b plane face downwards; thus, a layer with a uniform thickness, flatness, and high crystallinity is formed. By stacking n layers (n is a natural number), the CAAC-OS film can be obtained (see FIG. 25B).
In the case where the surface of the substrate 220 has unevenness, a CAAC-OS film in which n layers (n is a natural number) in each of which the pellets 200 are arranged along the convex surface are stacked is formed. Since the substrate 220 has unevenness, a gap is easily generated between in the pellets 200 in the CAAC-OS in some cases. Note that owing to intermolecular force, the pellets 200 are arranged so that a gap between the pellets is as small as possible even on the unevenness surface. Therefore, even when the film formation surface has unevenness, a CAAC-OS film with high crystallinity can be formed (see FIG. 25C).
As a result, laser crystallization is not needed for formation of a CAAC-OS, and a uniform film can be formed even over a large-sized glass substrate.
Since the CAAC-OS film is deposited in accordance with such a model, the sputtered particle preferably has a pellet shape with a small thickness. Note that when the sputtered particles has a dice shape with a large thickness, planes facing the substrate 220 vary, which may lead to formation of a film whose thickness or crystal alignment is not uniformed.
According to the deposition model described above, a CAAC-OS with high crystallinity can be formed even on a film formation surface with an amorphous structure.
Further, formation of a CAAC-OS can be described with a deposition model including a zinc oxide particle besides the pellet 200.
The zinc oxide particle reaches the substrate 220 before the pellet 200 does because the zinc oxide particle is smaller than the pellet 200 in mass. On the surface of the substrate 220, crystal growth of the zinc oxide particle preferentially occurs in the horizontal direction, so that a thin zinc oxide layer is formed. The zinc oxide layer has c-axis alignment. Note that c-axes of crystals in the zinc oxide layer are aligned in the direction parallel to a normal vector of the substrate 220. The zinc oxide layer serves as a seed layer that makes a CAAC-OS grow and thus has a function of increasing crystallinity of the CAAC-OS. The thickness of the zinc oxide layer is greater than or equal to 0.1 nm and less than or equal to 5 nm, mostly greater than or equal to 1 nm and less than or equal to 3 nm. Since the zinc oxide layer is sufficiently thin, a grain boundary is hardly observed.
Thus, in order to deposit a CAAC-OS with high crystallinity, a target containing zinc at a proportion higher than that of the stoichiometric composition is preferably used.
An nc-OS can be understood with a deposition model illustrated in FIG. 26. Note that a difference between FIG. 26 and FIG. 25A lies only in the fact that whether the substrate 220 is heated or not.
Thus, the substrate 220 is not heated, and a resistance such as friction between the pellet 200 and the substrate 220 is high. As a result, the pellets 200 cannot glide on the surface of the substrate 220 and are stacked randomly, thereby forming a nc-OS.
A cleavage plane that has been mentioned in the deposition model of the CAAC-OS is described below.
First, a cleavage plane of a target is described with reference to FIGS. 30A and 30B. FIGS. 30A and 30B show a structure of an InGaZnO4 crystal. Note that FIG. 30A shows a structure of the case where the InGaZnO4 crystal is observed from a direction parallel to the b-axis when the c-axis is in an upward direction. Further, FIG. 30B shows a structure of the case where the InGaZnO4 crystal is observed from a direction parallel to the c-axis.
Energy needed for cleavage at each of crystal planes of the InGaZnO4 crystal is calculated by the first principles calculation. Note that a “pseudopotential” and density functional theory program (CASTEP) using the plane wave basis are used for the calculation. Note that an ultrasoft type pseudopotential is used as the pseudopotential. Further, GGA/PBE is used as the functional. Cut-off energy is 400 eV.
Energy of a structure in an initial state is obtained after structural optimization including a cell size is performed. Further, energy of a structure after the cleavage at each plane is obtained after structural optimization of atomic arrangement is performed in a state where the cell size is fixed.
On the basis of the structure of the InGaZnO4 crystal shown in FIGS. 30A and 30B, a structure cleaved at any one of a first plane, a second plane, a third plane, and a fourth plane is formed and subjected to structural optimization calculation in which the cell size is fixed. Here, the first plane is a crystal plane between a Ga—Zn—O layer and an In—O layer and is parallel to the (001) plane (or the a-b plane) (see FIG. 30A). The second plane is a crystal plane between a Ga—Zn—O layer and a Ga—Zn—O layer and is parallel to the (001) plane (or the a-b plane) (see FIG. 30A). The third plane is a crystal plane parallel to the (110) plane (see FIG. 30B). The fourth plane is a crystal plane parallel to the (100) plane (or the b-c plane) (see FIG. 30B).
Under the above conditions, the energy of the structure at each plane after the cleavage is calculated. Next, a difference between the energy of the structure after the cleavage and the energy of the structure in the initial state is divided by the area of the cleavage plane; thus, cleavage energy which serves as a measure of easiness of cleavage at each plane is calculated. Note that the energy of a structure indicates energy obtained in such a manner that electronic kinetic energy of electrons included in the structure and interactions between atoms included in the structure, between the atom and the electron, and between the electrons are considered.
As calculation results, the cleavage energy of the first plane is 2.60 J/m2, that of the second plane is 0.68 J/m2, that of the third plane is 2.18 J/m2, and that of the fourth plane is 2.12 J/m2 (see Table 1).










TABLE 1








Cleavage energy [J/m2]









First plane
2.60



Second plane
0.68



Third plane
2.18



Fourth plane
2.12










From the calculations, in the structure of the InGaZnO4 crystal shown in FIGS. 30A and 30B, the cleavage energy at the second plane is the lowest. In other words, a plane between a Ga—Zn—O layer and a Ga—Zn—O layer is cleaved most easily (cleavage plane). Therefore, in this specification, the cleavage plane indicates the second plane, which is a plane where cleavage is performed most easily.
Since the cleavage plane is the second plane between a Ga—Zn—O layer and a Ga—Zn—O layer, the InGaZnO4 crystals shown in FIG. 30A can be separated at two planes equivalent to the second plane. Thus, it is considered that when an ion or the like collides with the target, a wafer unit cleaved at the plane with the lowest cleavage energy (we called this unit “pellet”) is separated off as the minimum unit. In that cases, a pellet of InGaZnO4 is composed of three layers of a Ga—Zn—O layer, an In—O layer, and a Ga—Zn—O layer.
The cleavage energies of the third plane (crystal plane parallel to the (110) plane) and the fourth plane (crystal plane parallel to the (100) plane (or the b-c plane)) are lower than that of the first plane (crystal plane between the Ga—Zn—O layer and the In—O layer and plane that is parallel to the (001) plane (or the a-b plane)), which suggests that most of the flat planes of the pellets have triangle shapes or hexagonal shapes.
Next, through classical molecular dynamics calculation, on the assumption of an InGaZnO4 crystal having a homologous structure as a target, a cleavage plane in the case where the target is sputtered using argon (Ar) or oxygen (O) is examined. FIG. 31A shows a cross-sectional structure of an InGaZnO4 crystal (2688 atoms) used for the calculation, and FIG. 31B shows a top structure thereof. Note that a fixed layer in FIG. 31A is a layer which prevents the positions of the atoms from moving. A temperature control layer in FIG. 31A is a layer whose temperature is constantly set to a fixed temperature (300 K).
For the classical molecular dynamics calculation, Materials Explorer 5.0 manufactured by Fujitsu Limited. is used. Note that the initial temperature, the cell size, the time step size, and the number of steps are set to be 300 K, a certain size, 0.01 fs, and ten million, respectively. In calculation, an atom to which an energy of 300 eV is applied is made to enter a cell from a direction perpendicular to the a-b plane of the InGaZnO4 crystal under the conditions.
FIG. 32A shows an atomic arrangement when 99.9 picoseconds have passed after argon enters the cell including the InGaZnO4 crystal shown in FIGS. 31A and 31B. FIG. 32B shows an atomic arrangement when 99.9 picoseconds have passed after oxygen enters the cell. Note that in FIGS. 32A and 32B, part of the fixed layer in FIG. 31A is omitted.
According to FIG. 32A, in a period from entry of argon into the cell to when 99.9 picoseconds have passed, a crack is formed from the cleavage plane corresponding to the second plane shown in FIG. 30A. Thus, in the case where argon collides with the InGaZnO4 crystal and the uppermost surface is the second plane (the zero-th), a large crack is found to be formed in the second plane (the second).
On the other hand, according to FIG. 32B, in a period from entry of oxygen into the cell to when 99.9 picoseconds have passed, a crack is found to be formed from the cleavage plane corresponding to the second plane shown in FIG. 30A. Note that in the case where oxygen collides with the cell, a large crack is found to be formed in the second plane (the first) of the InGaZnO4 crystal.
Accordingly, it is found that an atom (ion) collides with a target including an InGaZnO4 crystal having a homologous structure from the upper surface of the target, the InGaZnO4 crystal is cleaved along the second plane, and a flat-plate-like sputtered particle (pellet) is separated. It is also found that the pellet formed in the case where oxygen collides with the cell is smaller than that formed in the case where argon collides with the cell.
The above calculation suggests that the separated pellet includes a damaged region. In some cases, the damaged region included in the pellet can be repaired in such a way that a defect caused by the damage reacts with oxygen.
Here, difference in size of the pellet depending on atoms which are made to collide is studied.
FIG. 33A shows trajectories of the atoms from 0 picosecond to 0.3 picoseconds after argon enters the cell including the InGaZnO4 crystal shown in FIGS. 31A and 31B. Accordingly, FIG. 33A corresponds to a period from FIGS. 31A and 31B to FIG. 32A.
On the other hand, according to FIG. 33B, when oxygen collides with gallium (Ga) of the first layer (Ga—Zn—O layer) counted from the top, the gallium collides with zinc (Zn) of the third layer (Ga—Zn—O layer) counted from the top and then, the zinc does not reach the fifth layer (In—O layer) counted from the top. Note that the oxygen which collides with the gallium is sputtered to the outside. Accordingly, in the case where oxygen collides with the target including the InGaZnO4 crystal, a crack is thought to be formed in the second plane (the first) in FIG. 31A.
This calculation also shows that the InGaZnO4 crystal with which an atom (ion) collides is separated from the cleavage plane.
In addition, a difference in depth of a crack is examined in view of conservation laws. The energy conservation law and the law of conservation of momentum can be represented by the following formula (1) and the following formula (2). Here, E represents energy of argon or oxygen before collision (300 eV), mA represents mass of argon or oxygen, vA represents the speed of argon or oxygen before collision, v′A represents the speed of argon or oxygen after collision, mGa represents mass of gallium, vGa represents the speed of gallium before collision, and v′Ga represents the speed of gallium after collision.




  
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          1
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        E
        =
        
          
            
              1
              2
            
            ⁢
            
              m
              A
            
            ⁢
            
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              A
              2
            
          
          +
          
            
              1
              2
            
            ⁢
            
              m
              A
            
            ⁢
            
              v
              Ga
              2
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




[Formula 2]

mAvA+mGavGa=mAv′A+mGav′Ga  (2)

On the assumption that collision of argon or oxygen is elastic collision, the relationship among vA, v′A, vGa, and v′Ga can be represented by the following formula (3).
[Formula 3]

v′A−v′Ga=−(vA−vGa)  (3)

From the formulae (1), (2), and (3), on the assumption that vGa is 0, the speed of gallium v′Ga after collision of argon or oxygen can be represented by the following formula (4).



  
    [
    
      Formula
      ⁢
      
        
      
      ⁢
      4
    
    ]
  




  
    
      
        
          
            v
            Ga
            ′
          
          =
          
            
              
                
                  
                    m
                    A
                  
                
                
                  
                    m
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                    m
                    Ga
                  
                
              
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              2
            
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                2
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          (
          4
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In the formula (4), mass of argon or oxygen is substituted into mA, whereby the speeds of gallium after collision of the atoms are compared. In the case where the argon and the oxygen have the same energy before collision, the speed of gallium in the case where argon collides with the gallium was found to be 1.24 times as high as that in the case where oxygen collides with the gallium. Thus, the energy of the gallium in the case where argon collides with the gallium is higher than that in the case where oxygen collides with the gallium by the square of the speed.
The speed (energy) of gallium after collision in the case where argon collides with the gallium is found to be higher than that in the case where oxygen collides with the gallium. Accordingly, it is considered that a crack is formed at a deeper position in the case where argon collides with the gallium than in the case where oxygen collides with the gallium.
The above calculation shows that when a target including the InGaZnO4 crystal having a homologous structure is sputtered, separation occurs from the cleavage plane to form a pellet. In contrast, when a region of a target having no cleavage plane is sputtered, a pellet is not formed. In that case, a sputtered particle at an atomic level that is finer than the pellet is formed. Since the sputtered particle is smaller than the pellet, it is considered that the sputtered particle is removed through a vacuum pump connected to the sputtering apparatus. Thus, it is quite unlikely to form a model by stacking particles which have various sizes and shapes and reach the substrate when a target including an InGaZnO4 crystal having a homologous structure is sputtered. The model illustrated in FIG. 25A where sputtered pellets are deposited to form a CAAC-OS is a reasonable model.
The CAAC-OS deposited in such a manner has a density substantially equal to that of a single crystal OS. For example, the density of the single crystal OS film having a homologous structure of InGaZnO4 is 6.36 g/cm3, and the density of the CAAC-OS film having substantially the same atomic ratio is approximately 6.3 g/cm3.
FIGS. 34A and 34B show atomic arrangements of cross sections of an In—Ga—Zn oxide (see FIG. 34A) that is a CAAC-OS deposited by a sputtering method and a target thereof (see FIG. 34B). For observation of atomic arrangement, a high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) is used. The contrast of the image of each of the atoms in a HAADF-STEM image is proportional to the square of its atomic number. Therefore, Zn (atomic number: 30) and Ga (atomic number: 31), which have close atomic numbers, are difficult to distinguish. A Hitachi scanning transmission electron microscope HD-2700 is used for the HAADF-STEM.
When FIG. 34A and FIG. 34B are compared, it is found that the CAAC-OS and the target each have a homologous structure and arrangements of atoms in the CAAC-OS correspond to those in the target. Thus, as illustrated in the deposition model in FIG. 25A, the crystal structure of the target is transferred, whereby a CAAC-OS is formed.
[Embodiment 8]
In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention is described with reference to the drawings.
FIGS. 14A and 14B are each a circuit diagram of a semiconductor device and FIGS. 14C and 14D are each a cross-sectional view of a semiconductor device. FIGS. 14C and 14D each illustrate a cross-sectional view of the transistor 450 taken along a channel length direction on the left and a cross-sectional view of the transistor 450 taken along a channel width direction on the right. In the circuit diagram, “OS” is written beside a transistor in order to clearly demonstrate that the transistor includes an oxide semiconductor.
The semiconductor devices illustrated in FIGS. 14C and 14D each include a transistor 2200 containing a first semiconductor material in a lower portion and a transistor containing a second semiconductor material in an upper portion. Here, an example is described in which the transistor 450 described in Embodiment 1 as an example is used as the transistor containing the second semiconductor material.
Here, the first semiconductor material and the second semiconductor material preferably have different energy gaps. For example, the first semiconductor material may be a semiconductor material (e.g., silicon, germanium, silicon germanium, silicon carbide, or gallium arsenic) other than an oxide semiconductor, and the second semiconductor material may be the oxide semiconductor described in Embodiment 1. A transistor including single crystal silicon or the like as a material other than an oxide semiconductor can operate at high speed easily. In contrast, a transistor including an oxide semiconductor has the low off-state current.
Although the transistor 2200 is a p-channel transistor here, it is needless to say that an n-channel transistor can be used to form a circuit having a different configuration. The specific structure of the semiconductor device, such as a material used for the semiconductor device and the structure of the semiconductor device, does not need to be limited to that described here except for the use of the transistor described in Embodiment 1, which is formed using an oxide semiconductor.
FIGS. 14A, 14C, and 14D each illustrate a configuration example of what is called a CMOS circuit, in which a p-channel transistor and an n-channel transistor are connected in series and gates of the transistors are connected.
The transistor using an oxide semiconductor of one embodiment of the present invention has high on-state current, which can achieve high-speed operation of a circuit.
In the structure illustrated in FIG. 14C, the transistor 450 is provided over the transistor 2200 with an insulating film 2201 positioned therebetween. Wirings 2202 are provided between the transistor 2200 and the transistor 450. Wirings and electrodes over and under insulating films are electrically connected via plugs 2203 embedded in the insulating films. An insulating film 2204 covering the transistor 450, a wiring 2205 over the insulating film 2204, and a wiring 2206 formed by processing the same conductive film as the pair of electrodes of the transistor are provided.
By stacking two transistors in the above manner, an area occupied by a circuit can be reduced; accordingly, a plurality of circuits can be arranged in high density.
In FIG. 14C, one of the source and the drain of the transistor 450 is electrically connected to one of a source and a drain of the transistor 2200 via the wiring 2202 and the plug 2203. The gate of the transistor 450 is electrically connected to a gate of the transistor 2200 via the wiring 2205, the wiring 2206, the plug 2203, the wiring 2202, and the like.
In the configuration illustrated in FIG. 14D, an opening portion in which the plug 2203 is embedded is provided in a gate insulating layer of the transistor 450, and the gate of the transistor 450 is in contact with the plug 2203. Such a configuration makes it possible to achieve the integration of the circuit easily and to make the lengths and the number of wirings and plugs to be smaller than those in the configuration illustrated in FIG. 14C; thus, the circuit can operate at higher speed.
Note that when a connection between the electrodes of the transistor 450 and the transistor 2200 is changed from that in the configuration illustrated in FIG. 14C or FIG. 14D, a variety of circuits can be formed. For example, a circuit having a configuration in which a source and a drain of a transistor are connected to those of another transistor as illustrated in FIG. 14B can operate as what is called an analog switch.
A semiconductor device having an image sensor function for reading data of an object can be fabricated with the use of the transistor described in any of the above embodiments.
FIG. 19 illustrates an example of an equivalent circuit of a semiconductor device having an image sensor function.
In a photodiode 602, one electrode is electrically connected to a photodiode reset signal line 658, and the other electrode is electrically connected to a gate of a transistor 640. One of a source and a drain of the transistor 640 is electrically connected to a photosensor reference signal line 672, and the other of the source and the drain thereof is electrically connected to one of a source and a drain of a transistor 656. A gate of the transistor 656 is electrically connected to a gate signal line 659, and the other of the source and the drain thereof is electrically connected to a photosensor output signal line 671.
As the photodiode 602, for example, a pin photodiode in which a semiconductor layer having p-type conductivity, a high-resistance semiconductor layer (semiconductor layer having i-type conductivity), and a semiconductor layer having n-type conductivity are stacked can be used.
With detection of light that enters the photodiode 602, data of an object can be read. Note that a light source such as a backlight can be used at the time of reading data of an object.
As each of the transistor 640 and the transistor 656, the transistor in which a channel is formed in an oxide semiconductor, which is described in any of the above embodiments, can be used. In FIG. 19, “OS” is written beside the transistor 640 and the transistor 656 so that the transistors 640 and 656 can be identified as transistors including an oxide semiconductor.
It is preferable that each of the transistor 640 and the transistor 656 be one of the transistors described in the above embodiments, in which the oxide semiconductor film is electrically covered with the gate electrode when seen in the channel width direction. When the oxide semiconductor film has round end portions and a curved surface in the transistor, coverage with a film formed over the oxide semiconductor film can be improved. In addition, electric field concentration which might occur at end portions of the source electrode and the drain electrode can be reduced, which can suppress deterioration of the transistor. Therefore, variation in the electric characteristics of the transistor 640 and the transistor 656 is suppressed, and the transistor 640 and the transistor 656 are electrically stable. The semiconductor device having an image sensor function illustrated in FIG. 19 can have high reliability by including the transistor.
This embodiment can be combined as appropriate with any of the other embodiments in this specification.
[Embodiment 9]
In this embodiment, an example of a semiconductor device (storage device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is described with reference to drawings.
FIG. 15 is a circuit diagram of the semiconductor device.
The semiconductor device illustrated in FIG. 15 includes a transistor 3200 including a first semiconductor material, a transistor 3300 including a second semiconductor material, and a capacitor 3400. Note that the transistor described in Embodiment 1 can be used as the transistor 3300.
The transistor 3300 is a top-gate transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period owing to such a transistor. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation in a semiconductor storage device can be extremely low, which leads to a sufficient reduction in power consumption.
In FIG. 15, a first wiring 3001 is electrically connected to a source electrode of the transistor 3200. A second wiring 3002 is electrically connected to a drain electrode of the transistor 3200. A third wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the transistor 3300. A fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. The gate electrode of the transistor 3200 and the other of the source electrode and the drain electrode of the transistor 3300 are electrically connected to the one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.
The semiconductor device in FIG. 15 utilizes a feature that the potential of the gate electrode of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.
Writing and retaining of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, a predetermined charge is supplied to the gate electrode of the transistor 3200 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off. Thus, the charge supplied to the gate electrode of the transistor 3200 is retained (retaining).
Since the off-state current of the transistor 3300 is extremely low, the charge of the gate electrode of the transistor 3200 is retained for a long time.
Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of charge retained in the gate electrode of the transistor 3200. This is because in general, in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage Vth_H at the time when the high-level charge is given to the gate electrode of the transistor 3200 is lower than an apparent threshold voltage Vth_L at the time when the low-level charge is given to the gate electrode of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to turn on the transistor 3200. Thus, the potential of the fifth wiring 3005 is set to a potential V0 which is between Vth_H and Vth_L, whereby charge supplied to the gate electrode of the transistor 3200 can be determined. For example, in the case where the high-level charge is supplied in writing and the potential of the fifth wiring 3005 is V0 (>Vth_H), the transistor 3200 is turned on. In the case where the low-level charge is supplied in writing, even when the potential of the fifth wiring 3005 is V0 (<Vth_L), the transistor 3200 remains off. Thus, the data retained in the gate electrode can be read by determining the potential of the second wiring 3002.
Note that in the case where memory cells are arrayed, it is necessary that only data of a desired memory cell be able to be read. The fifth wiring 3005 in the case where data is not read may be supplied with a potential at which the transistor 3200 is turned off regardless of the state of the gate electrode, that is, a potential lower than Vth_H. Alternatively, the fifth wiring 3005 may be supplied with a potential at which the transistor 3200 is turned on regardless of the state of the gate electrode, that is, a potential higher than Vth_L.
When including a transistor having a channel formation region formed using an oxide semiconductor and having an extremely low off-state current, the semiconductor device described in this embodiment can retain stored data for an extremely long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).
Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of a gate insulating layer does not occur. That is, the semiconductor device of the disclosed invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be easily achieved.
As described above, a miniaturized and highly integrated semiconductor device having high electrical characteristics can be provided.
[Embodiment 10]
In this embodiment, a CPU in which at least the transistor described in any of the above embodiments can be used and the storage device described in the above embodiment is included is described.
FIG. 16 is a block diagram illustrating a configuration example of a CPU at least partly including the transistor described in Embodiment 1.
The CPU illustrated in FIG. 16 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I/F), a rewritable ROM 1199, and an ROM interface 1189 (ROM I/F). A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 16 is just an example in which the configuration has been simplified, and an actual CPU may have various configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 16 or an arithmetic circuit is considered as one core; a plurality of the cores is included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.
An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.
The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal CLK2 based on a reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above circuits.
In the CPU illustrated in FIG. 16, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.
In the CPU illustrated in FIG. 16, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register 1196 can be stopped.
FIG. 17 is an example of a circuit diagram of a storage element that can be used as the register 1196. A memory element 700 includes a circuit 701 in which stored data is volatile when power supply is stopped, a circuit 702 in which stored data is nonvolatile when power supply is stopped, a switch 703, a switch 704, a logic element 706, a capacitor 707, and a circuit 720 having a selecting function. The circuit 702 includes a capacitor 708, a transistor 709, and a transistor 710. Note that the memory element 700 may further include another element such as a diode, a resistor, or an inductor, as needed.
Here, the storage device described in the above embodiment can be used as the circuit 702. When supply of the power supply voltage to the memory element 700 is stopped, a ground potential (0 V) or a potential at which the transistor 709 in the circuit 702 is turned off continues to be input to a gate of the transistor 709. For example, the gate of the transistor 709 is grounded through a load such as a resistor.
An example in which the switch 703 is a transistor 713 having one conductivity type (e.g., an n-channel transistor) and the switch 704 is a transistor 714 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor) is described. Here, a first terminal of the switch 703 corresponds to one of a source and a drain of the transistor 713, a second terminal of the switch 703 corresponds to the other of the source and the drain of the transistor 713, and conduction or non-conduction between the first terminal and the second terminal of the switch 703 (i.e., the on/off state of the transistor 713) is selected by a control signal RD input to a gate of the transistor 713. A first terminal of the switch 704 corresponds to one of a source and a drain of the transistor 714, a second terminal of the switch 704 corresponds to the other of the source and the drain of the transistor 714, and conduction or non-conduction between the first terminal and the second terminal of the switch 704 (i.e., the on/off state of the transistor 714) is selected by the control signal RD input to a gate of the transistor 714.
One of a source and a drain of the transistor 709 is electrically connected to one of a pair of electrodes of the capacitor 708 and a gate of the transistor 710. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 710 is electrically connected to a line which can supply a low potential power source (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 703 (the one of the source and the drain of the transistor 713). The second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is electrically connected to the first terminal of the switch 704 (the one of the source and the drain of the transistor 714). The second terminal of the switch 704 (the other of the source and the drain of the transistor 714) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch 703 (the other of the source and the drain of the transistor 713), the first terminal of the switch 704 (the one of the source and the drain of the transistor 714), an input terminal of the logic element 706, and one of a pair of electrodes of the capacitor 707 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 707 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 707 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 707 is electrically connected to the line which can supply a low potential power source (e.g., a GND line). The other of the pair of electrodes of the capacitor 708 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 708 can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 708 is electrically connected to the line which can supply a low potential power source (e.g., a GND line).
The capacitor 707 and the capacitor 708 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.
A control signal WE is input to the first gate (first gate electrode) of the transistor 709. As for each of the switch 703 and the switch 704, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.
A signal corresponding to data retained in the circuit 701 is input to the other of the source and the drain of the transistor 709. FIG. 17 illustrates an example in which a signal output from the circuit 701 is input to the other of the source and the drain of the transistor 709. The logic value of a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is inverted by the logic element 706, and the inverted signal is input to the circuit 701 through the circuit 720.
In the example of FIG. 17, a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is input to the circuit 701 through the logic element 706 and the circuit 720; however, this embodiment is not limited thereto. The signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) may be input to the circuit 701 without its logic value being inverted. For example, in the case where a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained is provided in the circuit 701, the signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) can be input to the node.
As the transistor 709 in FIG. 17, the transistor described in Embodiment 1 can be used. The transistor 709 preferably includes a second gate (second gate electrode). The control signal WE can be input to the first gate and the control signal WE2 can be input to the second gate. The control signal WE2 is a signal having a constant potential. As the constant potential, for example, a ground potential GND or a potential lower than a source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709, and Icut of the transistor 709 can be further reduced. Note that as the transistor 709, the transistor without the second gate can be used.
Further, in FIG. 17, the transistors included in the memory element 700 except for the transistor 709 can each be a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Alternatively, a transistor in which a channel is formed in an oxide semiconductor film can be used for all the transistors used for the memory element 700. Further alternatively, in the memory element 700, a transistor in which a channel is formed in an oxide semiconductor film can be included besides the transistor 709, and a transistor in which a channel is formed in a layer or the substrate 1190 including a semiconductor other than an oxide semiconductor can be used for the rest of the transistors.
As the circuit 701 in FIG. 17, for example, a flip-flop circuit can be used. As the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.
The semiconductor device of one embodiment of the present invention can, in a period during which the memory element 700 is not supplied with the power supply voltage, retain data stored in the circuit 701 by the capacitor 708 which is provided in the circuit 702.
The off-state current of a transistor in which a channel is formed in an oxide semiconductor film is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when such a transistor including an oxide semiconductor is used for the transistor 709, a signal held in the capacitor 708 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 700. The memory element 700 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.
Since the switch 703 and the switch 704 are provided, the memory element performs pre-charge operation; thus, the time required for the circuit 701 to retain original data again after the supply of the power supply voltage is restarted can be shortened.
In the circuit 702, a signal retained by the capacitor 708 is input to the gate of the transistor 710. Therefore, after supply of the power supply voltage to the memory element 700 is restarted, the signal retained by the capacitor 708 can be converted into the one corresponding to the state (the on state or the off state) of the transistor 710 to be read from the circuit 702. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 708 fluctuates to some degree.
By applying the above-described memory element 700 to a storage device such as a register or a cache memory included in a processor, data in the storage device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Further, shortly after the supply of the power supply voltage is restarted, the storage device can be returned to the same state as that before the power supply is stopped. Thus, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor. Accordingly, power consumption can be suppressed.
Although an example in which the storage element 700 is used in a CPU is described in this embodiment, the storage element 700 can also be used in a digital signal processor (DSP), a custom LSI, an LSI such as a programmable logic device (PLD), and a radio frequency identification (RF-ID).
This embodiment can be combined as appropriate with any of the other embodiments in this specification.
[Embodiment 11]
In this embodiment, examples of an electronic device which can include the transistor described in Embodiment 1, the storage device described in Embodiment 7 or 8, or the CPU and the like (including a DSP, a custom LSI, a PLD, and an RF-ID) described in Embodiment 9 is described.
The transistor described in Embodiment 1, the storage device described in Embodiment 7 or 8, and the CPU and the like described in Embodiment 9 can be applied to a variety of electronic devices (including game machines). Example's of the electronic devices include display devices of televisions, monitors, and the like, lighting devices, personal computers, word processors, image reproduction devices, portable audio players, radios, tape recorders, stereos, phones, cordless phones, mobile phones, car phones, transceivers, wireless devices, game machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, IC chips, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air-conditioning systems such as air conditioners, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, radiation counters, and medical equipment such as dialyzers and X-ray diagnostic equipment. In addition, the examples of the electronic devices include alarm devices such as smoke detectors, heat detectors, gas alarm devices, and security alarm devices. Further, the examples of the electronic devices also include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, moving objects and the like driven by fuel engines and electric motors using power from non-aqueous secondary batteries are also included in the category of electronic devices. Examples of the moving objects include electric vehicles (EV), hybrid electric vehicles (REV) which include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats or ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecraft. Some specific examples of these electronic devices are illustrated in FIGS. 18A to 18C.
In a television set 8000 illustrated in FIG. 18A, a display portion 8002 is incorporated in a housing 8001. The display portion 8002 can display an image and a speaker portion 8003 can output sound. Any of the transistors described in the above embodiments can be used in a pixel or a driver circuit for operating the display portion 8002 incorporated in the housing 8001.
A semiconductor display device such as a liquid crystal display device, a light-emitting device in which a light-emitting element such as an organic EL element is provided in each pixel, an electrophoretic display device, a digital micromirror device (DMD), or a plasma display panel (PDP) can be used for the display portion 8002.
The television set 8000 may be provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Furthermore, when the television set 8000 is connected to a communication network by wired or wireless connection via the modern, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver, between receivers, or the like) data communication can be performed.
In addition, the television set 8000 may include a CPU 8004 for performing information communication or a memory. Any of the transistors, the memory device, and the CPU described in the above embodiments is used for the CPU 8004 or the memory, whereby power consumption can be reduced.
An alarm device 8100 illustrated in FIG. 18A is a residential fire alarm including a sensor portion 8102 for smoke or heat and a microcomputer 8101. Note that the microcomputer 8101 is an example of an electrical device including the transistor, the storage device, or the CPU described in any of the above embodiments.
An air conditioner which includes an indoor unit 8200 and an outdoor unit 8204 illustrated in FIG. 18A is an example of an electrical device including the transistor, the storage device, the CPU, or the like described in any of the above embodiments.
Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. Although the CPU 8203 is provided in the indoor unit 8200 in FIG. 18A, the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using any of the transistors described in the above embodiments for the CPU in the air conditioner, a reduction in power consumption of the air conditioner can be achieved.
An electric refrigerator-freezer 8300 illustrated in FIG. 18A is an example of an electrical device including the transistor, the storage device, the CPU, or the like described in any of the above embodiments. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a door for a refrigerator 8302, a door for a freezer 8303, a CPU 8304, and the like. In FIG. 18A, the CPU 8304 is provided in the housing 8301. When any of the transistors described in the above embodiments is used as the CPU 8304 of the electric refrigerator-freezer 8300, a reduction in power consumption of the electric refrigerator-freezer 8300 can be achieved.
FIGS. 18B and 18C illustrate an example of an electric vehicle which is an example of an electrical device. An electric vehicle 9700 is equipped with a secondary battery 9701. The output of the electric power of the secondary battery 9701 is adjusted by a circuit 9702 and the electric power is supplied to a driving device 9703. The circuit 9702 is controlled by a processing unit 9704 including a ROM, a RAM, a CPU, or the like which is not illustrated. When any of the transistors described in the above embodiments is used as the CPU in the electric vehicle 9700, a reduction in power consumption of the electric vehicle 9700 can be achieved.
The driving device 9703 includes a DC motor or an AC motor either alone or in combination with an internal-combustion engine. The processing unit 9704 outputs a control signal to the circuit 9702 based on input data such as data of operation (e.g., acceleration, deceleration, or stop) by a driver or data during driving (e.g., data on an upgrade or a downgrade, or data on a load on a driving wheel) of the electric vehicle 9700. The circuit 9702 adjusts the electric energy supplied from the secondary battery 9701 in accordance with the control signal of the processing unit 9704 to control the output of the driving device 9703. In the case where the AC motor is mounted, although not illustrated, an inverter which converts a direct current into an alternate current is also incorporated.
This embodiment can be combined as appropriate with any of the other embodiments in this specification.
This application is based on Japanese Patent Application serial no. 2013-119169 filed with Japan Patent Office on Jun. 5, 2013, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
a first gate electrode;
a first gate insulating film over the first gate electrode;
a first oxide semiconductor film over the first gate insulating film;
a second oxide semiconductor film over and in contact with the first oxide semiconductor film;
a source electrode and a drain electrode over the second oxide semiconductor film;
a third oxide semiconductor film in contact with the source electrode, the drain electrode, a top surface and a side surface of the second oxide semiconductor film, and a side surface of the first oxide semiconductor film;
a second gate insulating film over the third oxide semiconductor film; and
a second gate electrode in contact with a top surface of the second gate insulating film, the second gate electrode facing the top surface and the side surface of the second oxide semiconductor film,

wherein a portion of a bottom surface of the second gate electrode is located lower than an interface between the first oxide semiconductor film and the second oxide semiconductor film, and
wherein a difference in height between the portion of the bottom surface of the second gate electrode and the interface between the first oxide semiconductor film and the second oxide semiconductor film is greater than 0 and less than 300% of a channel width.

2. The semiconductor device according to claim 1, wherein the first gate insulating film has a projected portion,
wherein the first oxide semiconductor film is on the projected portion, and
wherein the third oxide semiconductor film is in contact with a side surface of the projected portion.

3. The semiconductor device according to claim 1, wherein the difference is less than the channel width.

4. The semiconductor device according to claim 1, wherein end portions of the top surface of the second oxide semiconductor film each have a curved surface.

5. The semiconductor device according to claim 1, wherein the second oxide semiconductor film comprises randomly arranged crystals.

6. The semiconductor device according to claim 1, wherein the third oxide semiconductor film includes a first layer including a crystalline region and a second layer including a crystalline region over the first layer,
wherein crystals included in the first layer are randomly arranged, and
wherein crystals included in the second layer are c-axis-aligned in a direction parallel to a normal vector of a top surface of the second layer.

7. The semiconductor device according to claim 1, wherein energy of a conduction band minimum of each of the first oxide semiconductor film and the third oxide semiconductor film is closer to a vacuum level than energy of a conduction band minimum of the second oxide semiconductor film by 0.05 eV or more and 2 eV or less.

8. The semiconductor device according to claim 1, wherein the first gate electrode is electrically isolated from the second gate electrode.

9. The semiconductor device according to claim 1, wherein the first gate electrode is electrically connected to the second gate electrode.

10. A semiconductor device comprising:
a first gate electrode;
a first gate insulating film over the first gate electrode;
a first oxide semiconductor film over the first gate insulating film;
a second oxide semiconductor film over and in contact with the first oxide semiconductor film;
a source electrode and a drain electrode over the second oxide semiconductor film;
a third oxide semiconductor film in contact with the source electrode, the drain electrode, a top surface and a side surface of the second oxide semiconductor film, and a side surface of the first oxide semiconductor film;
a second gate insulating film over the third oxide semiconductor film; and
a second gate electrode over and in contact with the second gate insulating film, the second gate electrode facing the top surface of the second oxide semiconductor film,
wherein the second gate electrode extends lower than an interface between the first oxide semiconductor film and the second oxide semiconductor film, and
wherein a thickness of a region in which the second gate electrode faces the side surface of the first oxide semiconductor film is greater than 0 and less than 300% of a channel width.

11. The semiconductor device according to claim 10, wherein the thickness of the region is less than the channel width.

12. The semiconductor device according to claim 10, wherein end portions of the top surface of the second oxide semiconductor film each have a curved surface.

13. The semiconductor device according to claim 10, wherein the second oxide semiconductor film comprises randomly arranged crystals.

14. The semiconductor device according to claim 10, wherein the third oxide semiconductor film includes a first layer including a crystalline region and a second layer including a crystalline region over the first layer,
wherein crystals included in the first layer are randomly arranged, and
wherein crystals included in the second layer are c-axis-aligned in a direction parallel to a normal vector of a top surface of the second layer.

15. The semiconductor device according to claim 10, wherein energy of a conduction band minimum of each of the first oxide semiconductor film and the third oxide semiconductor film is closer to a vacuum level than energy of a conduction band minimum of the second oxide semiconductor film by 0.05 eV or more and 2 eV or less.

16. The semiconductor device according to claim 10, wherein the first gate electrode is electrically isolated from the second gate electrode.

17. The semiconductor device according to claim 10, wherein the first gate electrode is electrically connected to the second gate electrode.

18. A semiconductor device comprising:
a first gate electrode;
a first gate insulating film over the first gate electrode;
the first gate insulating film having a projected portion and a depressed portion;
a first oxide semiconductor film over the projected portion;
a second oxide semiconductor film over and in contact with the first oxide semiconductor film;
a source electrode and a drain electrode over the second oxide semiconductor film;
a third oxide semiconductor film in contact with the source electrode, the drain electrode, a side surface and a top surface of the second oxide semiconductor film, a side surface of the first oxide semiconductor film, a side surface of the projected portion, and a bottom surface of the depressed portion;
a second gate insulating film over the third oxide semiconductor film; and
a second gate electrode over and in contact with the second gate insulating film, the second gate electrode facing the top surface of the second oxide semiconductor film,
wherein the second gate electrode extends lower than an interface between the first oxide semiconductor film and the second oxide semiconductor film, and
wherein a thickness of a region in which the second gate electrode faces the side surface of the first oxide semiconductor film and the side surface of the projected portion is greater than 0 and less than 300% of a channel width.

19. The semiconductor device according to claim 18, wherein the thickness of the region is less than the channel width.

20. The semiconductor device according to claim 18, wherein end portions of the top surface of the second oxide semiconductor film each have a curved surface.

21. The semiconductor device according to claim 18, wherein the second oxide semiconductor film comprises randomly arranged crystals.

22. The semiconductor device according to claim 18, wherein the third oxide semiconductor film includes a first layer including a crystalline region and a second layer including a crystalline region over the first layer,
wherein crystals included in the first layer are randomly arranged, and
wherein crystals included in the second layer are c-axis-aligned in a direction parallel to a normal vector of a top surface of the second layer.

23. The semiconductor device according to claim 18, wherein energy of a conduction band minimum of each of the first oxide semiconductor film and the third oxide semiconductor film is closer to a vacuum level than energy of a conduction band minimum of the second oxide semiconductor film by 0.05 eV or more and 2 eV or less.

24. The semiconductor device according to claim 18, wherein the first gate electrode is electrically isolated from the second gate electrode.

25. The semiconductor device according to claim 18, wherein the first gate electrode is electrically connected to the second gate electrode.