# Patent

## Title
Memory semiconductor device having aligned side surfaces

## Abstract

An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

## Background
TECHNICAL FIELD
An embodiment of the invention disclosed herein relates to a semiconductor device including a semiconductor element and a manufacturing method of the semiconductor device.
BACKGROUND ART
Memory devices including semiconductor elements are broadly classified into two categories: volatile memory devices that lose stored data when not powered, and nonvolatile memory devices that hold stored data even when not powered.
A typical example of volatile memory devices is a dynamic random access memory (DRAM). A DRAM stores data in such a manner that a transistor included in a memory element is selected and electric charge is stored in a capacitor.
When data is read from a DRAM, electric charge in a capacitor is lost according to the above-described principle; thus, another writing operation is necessary every time data is read out. Moreover, a transistor included in a memory element has leakage current (off-state current) between a source and a drain in an off state or the like and electric charge flows into or out of the transistor even if the transistor is not selected, which makes a data holding period short. For that reason, writing operation (refresh operation) is necessary at predetermined intervals, and it is difficult to sufficiently reduce power consumption. Furthermore, since stored data is lost when power supply stops, another memory device utilizing a magnetic material or an optical material is needed in order to hold the data for a long time.
Another example of volatile memory devices is a static random access memory (SRAM). An SRAM holds stored data by using a circuit such as a flip-flop and thus does not need refresh operation, which is an advantage over a DRAM. However, cost per storage capacity is high because a circuit such as a flip-flop is used. Moreover, as in a DRAM, stored data in an SRAM is lost when power supply stops.
A typical example of nonvolatile memory devices is a flash memory. A flash memory includes a floating gate between a gate electrode and a channel formation region in a transistor and stores data by holding charge in the floating gate. Therefore, a flash memory has advantages in that the data holding period is extremely long (semi-permanent) and refresh operation which is necessary to volatile memory devices is not needed (e.g., see Patent Document 1).
However, in a flash memory, there is a problem in that a memory element becomes unable to function after a predetermined number of writing operations because a gate insulating layer included in the memory element deteriorates due to tunneling current generated in writing operations. In order to reduce effects of this problem, a method in which the number of writing operations is equalized among memory elements can be employed, for example, but a complex peripheral circuit is needed to realize this method. Moreover, even when such a method is employed, the fundamental problem of lifetime cannot be resolved. In other words, a flash memory is not suitable for applications in which data is frequently rewritten.
In addition, high voltage is necessary in order to inject charge into the floating gate or removing the charge, and a circuit for that purpose is required. Further, it takes a relatively long time to inject or remove electric charge, and it is not easy to increase the speed of writing or erasing data.
REFERENCE


    [Patent Document 1] Japanese Published Patent Application No. S57-105889


DISCLOSURE OF INVENTION
For memory devices (also simply referred to as semiconductor devices) including semiconductor elements as described above, a sufficient reduction in size is required in terms of an increase in storage capacity, a reduction in product unit price, or the like. In addition, memory devices including semiconductor elements as described above do not have satisfactory functions that meet a variety of requirements, and therefore need to have further improved functions.
In view of the above problems, it is an object of one embodiment of the disclosed invention to provide a semiconductor device having a novel structure with a high degree of integration.
It is another object to achieve a high degree of integration of a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles.
In an embodiment of the disclosed invention, side surfaces (or portions thereof) of components of a transistor included in a semiconductor device are aligned with each other. Transistors are integrated three-dimensionally. Specifically, an example of a structure of a semiconductor device is as follows.
In one embodiment of the disclosed invention, a semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.
Here, the channel formation region may include an oxide semiconductor. In addition, a material of the gate insulating layer and a material of the source electrode or the drain electrode may be processable by the same process (such as a dry etching process using the same etching gas). Furthermore, the side surface of the gate insulating layer may be perpendicular to a channel length direction.
The above semiconductor device may include an electrode over the gate insulating layer, which overlaps with the source electrode or the drain electrode. A portion of a side surface of the electrode, the portion of the side surface of the gate insulating layer, and the portion of the side surface of the source electrode or the drain electrode may be substantially aligned with each other when seen from a planar direction. In addition, a portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode may be substantially aligned with each other when seen from a planar direction.
In another embodiment of the disclosed invention, a semiconductor device includes a first transistor including a first channel formation region, a first gate insulating layer over the first channel formation region, a first gate electrode over the first gate insulating layer, which overlaps with the first channel formation region, and a first source region and a first drain region between which the first channel formation region is sandwiched, and a second transistor including a semiconductor layer having a second channel formation region, a second source electrode and a second drain electrode electrically connected to the second channel formation region, a second gate electrode overlapping with the second channel formation region, and a second gate insulating layer between the second channel formation region and the second gate electrode. The first channel formation region and the second channel formation region include different semiconductor materials as their respective main components. A portion of a side surface of the second gate insulating layer and a portion of a side surface of the second source electrode or the second drain electrode are substantially aligned with each other when seen from a planar direction.
Here, the second channel formation region may include an oxide semiconductor. A material of the second gate insulating layer and a material of the second source electrode and the second drain electrode may be processable by the same process. The side surface of the second gate insulating layer may be perpendicular to a channel length direction. The semiconductor device may include an electrode over the second gate insulating layer, which overlaps with the second source electrode or the second drain electrode. A portion of a side surface of the electrode, the portion of the side surface of the second gate insulating layer, and the portion of the side surface of the second source electrode or the second drain electrode may be substantially aligned with each other when seen from a planar direction.
In the above semiconductor device, a portion of a side surface of the first channel formation region, a portion of a side surface of the first gate insulating layer, and a portion of a side surface of the first gate electrode may be substantially aligned with each other when seen from a planar direction, and a portion of a side surface of the semiconductor layer having the second channel formation region and a portion of a side surface of the second source electrode or the second drain electrode may be substantially aligned with each other when seen from a planar direction. The side surface of the first channel formation region may be parallel with a channel length direction of the first transistor. The side surface of the semiconductor layer having the second channel formation region may be parallel with a channel length direction of the second transistor.
In the above embodiment, the first gate electrode may be electrically connected to the second source electrode or the second drain electrode. The semiconductor device may include a plurality of first transistors and a plurality of second transistors. A first source region or a first drain region of one of the plurality of first transistors may be electrically connected to a first drain region or a first source region of a first transistor adjacent to the one of the plurality of first transistors.
Note that although, in the above embodiments, the transistor may be formed using an oxide semiconductor, the disclosed invention is not limited thereto. A material capable of realizing off-state current characteristics comparable to those of an oxide semiconductor, for example, a widegap material (specifically, a semiconductor material having an energy gap Eg of more than 3 eV, for example), such as silicon carbide, or the like may be employed.
In this specification and the like, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface (either a front surface or a rear surface) of a substrate. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers with the same mask. Furthermore, the term “channel length direction” refers to a direction from a source region (or a source electrode) toward a drain region (or a drain electrode), or the opposite direction, along the shortest path between the source region and the drain region.
In addition, the term “main component” used in this specification and the like refers to a component whose content is the highest (at. %). According to this statement, for example, it can be said that the main component of a so-called “silicon wafer” is silicon.
Note that the term such as “over” or “below” in this specification and the like does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where a component is placed between the gate insulating layer and the gate electrode.
In addition, the term such as “electrode” or “wiring” in this specification and the like does not limit a function of a component. For example, an “electrode” can be used as part of a “wiring”, and the “wiring” can be used as part of the “electrode”. Furthermore, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner.
Functions of a “source” and a “drain” are sometimes interchanged with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification and the like.
Note that the term “electrically connected” in this specification and the like includes the case where components are connected through an “object having any electric function”. There is no particular limitation on an object having any electric function as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring.
In a semiconductor device according to an embodiment of the disclosed invention, side surfaces (or portions thereof) of components of a transistor are aligned with each other. Accordingly, an increase in the degree of integration of the semiconductor device can be achieved. In particular, in a structure including three-dimensionally integrated transistors, a more significant effect can be obtained in combination with an increase in the degree of integration owing to this three-dimensional structure.



BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A and 1B are a plan view and a cross-sectional view of a semiconductor device.
FIGS. 2A to 2C are perspective views illustrating a manufacturing process of a semiconductor device.
FIGS. 3A to 3C are perspective views illustrating a manufacturing process of a semiconductor device.
FIGS. 4A to 4C are perspective views illustrating a manufacturing process of a semiconductor device.
FIGS. 5A to 5C are perspective views illustrating a manufacturing process of a semiconductor device.
FIGS. 6A to 6C are perspective views illustrating a manufacturing process of a semiconductor device.
FIG. 7 is a perspective view illustrating a manufacturing process of a semiconductor device.
FIGS. 8A-1, 8A-2, and 8B are circuit diagrams of a semiconductor device.
FIG. 9 is a circuit diagram of a semiconductor device.
FIG. 10 illustrates a timing chart.
FIG. 11 is a circuit diagram of a semiconductor device.
FIG. 12 illustrates a timing chart.
FIGS. 13A to 13F are diagrams each illustrating an electronic device including a semiconductor device.



BEST MODE FOR CARRYING OUT THE INVENTION
Examples of embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention should not be interpreted as being limited to the description in the following embodiments.
Note that the position, size, range, or the like of each component illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like.
Note that ordinal numbers such as “first”, “second”, and “third” in this specification and the like are used in order to avoid confusion among components, and the terms do not limit the components numerically.
Embodiment 1
In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. 1A and 1B, FIGS. 2A to 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, FIGS. 6A to 6C, and FIG. 7. Note that FIGS. 1A and 1B, FIGS. 2A to 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, FIGS. 6A to 6C, and FIG. 7 illustrate part of the semiconductor device for explanation of the semiconductor device and the manufacturing method thereof and do not illustrate the entire structure of the semiconductor device.
<Cross-Sectional Structure and Planar Structure of Semiconductor Device>
FIGS. 1A and 1B illustrate an example of a structure of the semiconductor device. FIG. 1A is a plan view illustrating part of the semiconductor device, and FIG. 1B is a cross-sectional view taken along line A1-A2 of FIG. 1A. The semiconductor device illustrated in FIGS. 1A and 1B includes a transistor 160 including a first semiconductor material in a lower portion, and a transistor 162 including a second semiconductor material and a capacitor 164 in an upper portion.
Here, the first semiconductor material and the second semiconductor material preferably include different semiconductor materials as their respective main components. For example, the first semiconductor material can be a semiconductor material (such as silicon) other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor, such as single crystal silicon, can operate at high speed easily. On the other hand, a transistor including an oxide semiconductor can hold electric charge for a long time owing to its characteristics. Note that the term “main component” used in this specification and the like refers to a component whose content is the highest (at. %). According to this statement, for example, it can be said that the main component of a so-called “silicon wafer” is silicon.
Note that these transistors may be either n-channel transistors or p-channel transistors.
The transistor 160 in FIGS. 1A and 1B includes a channel formation region 132 provided in a substrate 101 including a semiconductor material (such as silicon), an impurity region 128 and an impurity region 130 provided such that the channel formation region 132 is sandwiched therebetween, a gate insulating layer 111 provided over the channel formation region 132, and a gate electrode 125 provided over the gate insulating layer 111. Here, the impurity region 128 and the impurity region 130 each function as a source region or a drain region of the transistor. In addition, the impurity region 128 is a region to which an impurity is added at high concentration, and also functions as a wiring. Note that a transistor whose source electrode and drain electrode are not illustrated in a drawing may also be referred to as a transistor for the sake of convenience. Further, in such a case, in description of a connection of a transistor, a source region and a source electrode may be collectively referred to as a source electrode, and a drain region and a drain electrode may be collectively referred to as a drain electrode. That is, in this specification, the term “source electrode” may include a source region and the term “drain electrode” may include a drain region.
When the transistor 160 is seen from a planar direction, portions of side surfaces of the channel formation region 132 provided in the substrate 101, the gate insulating layer 111, and the gate electrode 125 are substantially aligned with each other (see FIG. 1A). In particular, side surfaces of the channel formation region 132 provided in the substrate 101, the gate insulating layer 111, and the gate electrode 125 which are parallel with a channel length direction (for example, side surfaces located in a region 155 in FIG. 1A) are substantially aligned with each other. By formation of the transistor 160 in such a planar layout, an increase in the degree of integration of the semiconductor device including the transistor 160 can be achieved. Here, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface (either a front surface or a rear surface) of the substrate 101. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers with the same mask. Furthermore, the term “channel length direction” refers to a direction from a source region toward a drain region, or the opposite direction, along the shortest path between the source region and the drain region.
In addition, an element isolation insulating layer 121 for isolating the adjacent transistors 160 from each other is embedded in the substrate 101 as illustrated in FIG. 3B, and an insulating layer 131 is provided over the transistors 160 such that the top surface of the gate electrode 125 is exposed as illustrated in FIG. 4C. Note that in order to realize higher integration, the transistor 160 preferably has a structure without a sidewall insulating layer as illustrated in FIGS. 1A and 1B. On the other hand, in the case where characteristics of the transistor 160 have priority, a sidewall insulating layer may be provided on a side surface of the gate electrode 125, and the impurity region 130 and the like may include a region having a different impurity concentration.
Here, the insulating layer 131 preferably has a surface with favorable planarity; for example, the surface of the insulating layer 131 preferably has a root-mean-square (RMS) roughness of 1 nm or less. This is because the transistor 162 can have better characteristics when provided over the insulating layer 131 having a highly planar surface.
The transistor 162 in FIGS. 1A and 1B includes an oxide semiconductor layer 141 formed over the insulating layer 131 and having a channel formation region, a source electrode 143 and a drain electrode 145 connected to part of the oxide semiconductor layer 141, a gate insulating layer 147 covering the oxide semiconductor layer 141, and a gate electrode 149 provided over the gate insulating layer 147 so as to overlap with the oxide semiconductor layer 141. Here, the source electrode 143 (which may be the drain electrode 145) of the transistor 162 is electrically connected to the gate electrode 125 of the transistor 160. It is needless to say that the connection between transistors according to the disclosed invention is not limited to this example.
Here, the oxide semiconductor layer 141 is preferably an oxide semiconductor layer which is purified by sufficiently removing an impurity such as hydrogen therefrom or by sufficiently supplying oxygen thereto. Specifically, the hydrogen concentration of the oxide semiconductor layer 141 is 5×1019 atoms/cm3 or less, preferably 5×1018 atoms/cm3 or less, more preferably 5×1017 atoms/cm3 or less, for example. Note that the above hydrogen concentration of the oxide semiconductor layer 141 is measured by secondary ion mass spectrometry (SIMS). The density of carriers generated due to a donor such as hydrogen in the oxide semiconductor layer 141, in which hydrogen is reduced to a sufficiently low concentration so that the oxide semiconductor layer is purified and in which defect states in an energy gap due to oxygen deficiency are reduced by sufficiently supplying oxygen as described above, is less than 1×1012/cm3, preferably less than 1×1011/cm3, more preferably less than 1.45×1010/cm3. In addition, for example, the off-state current (per unit channel width (1 μm), here) at room temperature (25° C.) is 100 zA (1 zA (zeptoampere) is 1×10−21 A) or less, preferably 10 zA or less. In this manner, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, the transistor 162 which has extremely favorable off-state current characteristics can be obtained.
In addition, a region which is part of a surface of the insulating layer 131 and is in contact with the oxide semiconductor layer 141 preferably has a root-mean-square (RMS) roughness of 1 nm or less. In this manner, the channel formation region of the transistor 162 is provided in an extremely flat region having a root-mean-square (RMS) roughness of 1 nm or less, whereby the transistor 162 which can prevent a malfunction such as a short-channel effect and has favorable characteristics can be provided even when the transistor 162 is miniaturized.
Here, when the transistor 162 is seen from a planar direction, portions of side surfaces of the oxide semiconductor layer 141 having the channel formation region and the source electrode 143 (or the drain electrode 145) are substantially aligned with each other. In particular, as illustrated in FIG. 5C, side surfaces of the oxide semiconductor layer 141 having the channel formation region and the source electrode 142 (corresponding to the source electrode 143) (or the drain electrode 145) which are parallel with a channel length direction (for example, side surfaces located in a region 157 in FIG. 1A) are substantially aligned with each other.
Similarly, when the transistor 162 is seen from a planar direction, a portion of a side surface of the gate insulating layer 147 and a portion of a side surface of the source electrode 143 (or the drain electrode 145) are substantially aligned with each other. In particular, as illustrated in FIG. 7, side surfaces of the gate insulating layer 147 and the source electrode 143 (or the drain electrode 145) which are perpendicular to the channel length direction (for example, side surfaces located in a region 159 in FIG. 1A) are substantially aligned with each other.
Here, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface (either a front surface or a rear surface) of the substrate 101. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers with the same mask. Furthermore, the term “channel length direction” refers to a direction from a source region toward a drain region, or the opposite direction, along the shortest path between the source region and the drain region. By formation of the transistor 162 in such a planar layout, an increase in the degree of integration of the semiconductor device including the transistor 162 can be achieved.
The capacitor 164 in FIGS. 1A and 1B includes the source electrode 143, the gate insulating layer 147, and an electrode 151 over the gate insulating layer 147. In other words, the source electrode 143 functions as one electrode of the capacitor 164, and the electrode 151 functions as the other electrode of the capacitor 164. Meanwhile, the capacitor 164 is not an essential component in an embodiment of the disclosed invention; thus, the electrode 151 or the like can be omitted as appropriate. Moreover, when the transistor 162 is seen from the planar direction, a portion of a side surface of the electrode 151 is preferably substantially aligned with the portion of the side surface of the gate insulating layer 147 and the portion of the side surface of the source electrode 143 (or the drain electrode 145). As illustrated in FIG. 7, side surfaces of the electrode 151, the gate insulating layer 147, and the source electrode 143 (or the drain electrode 145) which are perpendicular to the channel length direction (for example, side surfaces located in the region 159 in FIG. 1A) are preferably substantially aligned with each other.
In an embodiment in which side surfaces (or portions thereof) of components of a transistor are aligned with each other as described above, a highly integrated semiconductor device can be realized. In particular, in a structure including three-dimensionally integrated transistors, a more significant effect can be obtained in combination with an increase in the degree of integration owing to this three-dimensional structure. Note that although the side surfaces (or portions thereof) of components of the transistors in the semiconductor device illustrated in FIGS. 1A and 1B are aligned in a plurality of regions (the region 155, the region 157, and the region 159), the effect can be sufficiently obtained even when side surfaces of components are aligned in only one of the regions.
Note that the structure of a semiconductor device according to an embodiment of the disclosed invention is not limited to that illustrated in FIGS. 1A and 1B. Since the technical idea of an embodiment of the disclosed invention is to achieve an increase in the degree of integration of a semiconductor device by aligning side surfaces (or portions thereof) of components of a transistor with each other, details such as an electrode connection can be changed as appropriate.
<Method for Manufacturing Semiconductor Device>
Next, an example of a method for manufacturing the above-described semiconductor device will be described.
First, the substrate 101 including a semiconductor material is prepared (see FIG. 2A). Note that a cross section taken along line A1-A2 of FIG. 2A corresponds to the cross section shown in FIG. 1B. The same applies to FIGS. 2B and 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, FIGS. 6A to 6C and FIG. 7. A single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like, a compound semiconductor substrate of silicon germanium or the like, an SOI substrate, or the like can be used as the substrate 101 including a semiconductor material. Here, an example of the case where a single crystal silicon substrate is used as the substrate 101 including a semiconductor material is described. Note that the term “SOI substrate” generally means a substrate where a silicon semiconductor layer is provided over an insulating surface. In this specification and the like, the term “SOI substrate” also means a substrate where a semiconductor layer including a material other than silicon is provided over an insulating surface. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer. Moreover, the SOI substrate can be a substrate having a structure where a semiconductor layer is provided over an insulating substrate such as a glass substrate with an insulating layer interposed therebetween.
It is particularly preferable that a single crystal semiconductor substrate of silicon or the like be used as the substrate 101 including a semiconductor material because the speed of reading operation of the semiconductor device can be increased.
Note that an impurity element may be added to a region which later functions as the channel formation region 132 of the transistor 160, in order to control the threshold voltage of the transistor. Here, an impurity element imparting conductivity is added so that the threshold voltage of the transistor 160 becomes positive. When the semiconductor material is silicon, the impurity imparting conductivity may be boron, aluminum, gallium, or the like.
Next, an insulating layer 103 is formed over the substrate 101 (see FIG. 2A). The insulating layer 103 is later processed into the gate insulating layer 111 and can be formed by, for example, heat treatment (thermal oxidation treatment, thermal nitridation treatment, or the like) of the surface of the substrate 101 including a semiconductor material. Instead of heat treatment, high-density plasma treatment may be employed. The high-density plasma treatment can be performed using, for example, a mixed gas of any of a rare gas such as He, Ar, Kr, or Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, and the like. It is needless to say that the insulating layer may be formed by a CVD method, a sputtering method, or the like. The insulating layer 103 preferably has a single-layer structure or a stacked-layer structure with a film including silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate (HfSixOy (x>0, y>0)) to which nitrogen is added, hafnium aluminate (HfAlxOy (x>0, y>0)) to which nitrogen is added, or the like. The insulating layer 103 can have a thickness of 1 nm to 100 nm, preferably 10 nm to 50 nm, for example.
Next, a layer 105 including a conductive material is formed over the insulating layer 103 (see FIG. 2A). The layer 105 including a conductive material is later processed into the gate electrode 125. The layer 105 including a conductive material can be formed using a semiconductor material such as polycrystalline silicon, to which an impurity element imparting one conductivity type such as phosphorus or boron is added. The layer 105 including a conductive material may be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. There is no particular limitation on the method for forming the layer 105 including a conductive material, and a variety of film formation methods such as an evaporation method, a CVD method, a sputtering method, or a spin coating method can be employed.
Then, an insulating layer 107 is formed over the layer 105 including a conductive material (see FIG. 2A). The insulating layer 107 is later processed into an insulating layer 115 which protects a portion of the layer 105 including a conductive material to be the gate electrode 125 during a later step of etching the layer 105 including a conductive material. The insulating layer 107 is preferably formed using a material having an etching rate different from that of the element isolation insulating layer 121 to be formed in a later step; for example, when silicon oxide is used for the element isolation insulating layer 121, silicon nitride or the like is preferably used for the insulating layer 107.
After that, a resist mask 109 is formed over the insulating layer 107 (see FIG. 2A).
Next, a region not covered with the resist mask 109 is removed by selectively etching part of the insulating layer 107, the layer 105 including a conductive material, the insulating layer 103, and the substrate 101 with the use of the resist mask 109. Accordingly, the gate insulating layer 111, a layer 113 including a conductive material, and the insulating layer 115 are formed (see FIG. 2B). In addition, a portion of a side surface of a region later serving as the channel formation region 132 (a projecting region of the substrate 101, which is formed by the above etching step), a portion of a side surface of the gate insulating layer 111, and a portion of a side surface of the layer 113 including a conductive material, which is later processed into the gate electrode, are substantially aligned with each other when seen from a planar direction. Furthermore, the side surfaces substantially aligned with each other as described above (for example, the side surface of the region later serving as the channel formation region 132) are parallel with the channel length direction. Here, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface of the substrate 101. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers with the same mask. Furthermore, the term “channel length direction” refers to a direction from a source region toward a drain region, or the opposite direction, along the shortest path between the source region and the drain region.
By etching part of the insulating layer 107, the layer 105 including a conductive material, the insulating layer 103, and the substrate 101 at a time with the use of the resist mask 109 as described above, it becomes possible to eliminate variation in shape which may be caused by mask misalignment when the components are formed separately by etching. In that case, there is no need to leave a margin for mask alignment and it is therefore possible to sufficiently increase the degree of integration.
Note that the resist mask 109 is removed after the above etching step. As the etching, dry etching is preferably performed, but wet etching may be performed. An etching gas or an etchant can be selected as appropriate depending on a material to be etched. In addition, the layer 105 including a conductive material, the insulating layer 103, and the substrate 101 preferably include materials which are successively processable by changing conditions during the etching process, and preferably include, for example, materials which are successively processable by changing conditions, e.g., by changing gases, during a dry etching process. In particular, the layer 105 including a conductive material, the insulating layer 103, and the substrate 101 preferably include materials which are processable by the same process (for example, by a dry etching process using the same etching gas).
Next, an insulating layer 117 is formed so as to cover the substrate 101, the gate insulating layer 111, the layer 113 including a conductive material, and the insulating layer 115 (see FIG. 2C). There is no particular limitation on methods for forming the insulating layer 117; for example, the insulating layer 117 may be a thermal oxide film formed by thermal oxidation of the substrate 101, the gate insulating layer 111, the layer 113 including a conductive material, and the insulating layer 115. In the case of forming the insulating layer 117 by thermal oxidation as mentioned above, a high-temperature oxide film can be formed using CVD, for example. When the layer 113 including a conductive material is formed using a semiconductor material such as polycrystalline silicon to which an impurity element is added, a thermal oxide film is preferably formed by thermal oxidation. In that case, heat treatment may also be performed before or after forming the thermal oxide film. By performing thermal oxidation and heat treatment as described above, portions of the substrate 101, the gate insulating layer 111, the layer 113 including a conductive material, and the insulating layer 115 which are damaged during the above etching step can be repaired.
Next, an insulating layer 119 is formed so as to cover the substrate 101, the gate insulating layer 111, the layer 113 including a conductive material, the insulating layer 115, and the insulating layer 117 (see FIG. 3A). The insulating layer 119 is later processed into the element isolation insulating layer 121 and is formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.
Then, the element isolation insulating layer 121 is formed by processing the insulating layer 119 so as to expose at least part of the insulating layer 115. After that, the layer 113 including a conductive material is exposed by removing the insulating layer 115 (see FIG. 3B). Methods for processing the insulating layer 119 include etching treatment, polishing treatment such as chemical mechanical polishing (CMP), and the like; any of these methods may be employed. Note that an example is described here in which part of the insulating layer 119 is removed such that the upper surface of the element isolation insulating layer 121 is at a level lower than that of the upper surface of the layer 113 including a conductive material. At the same time, a portion of the insulating layer 117 above the element isolation insulating layer 121 may also be removed in some cases.
Next, an insulating layer and a resist mask 123 are formed over the element isolation insulating layer 121 and the layer 113 including a conductive material, and a mask 124 is formed by selectively etching the insulating layer. In addition, the gate electrode 125 is formed by selectively etching the layer 113 including a conductive material (see FIG. 3C). The insulating layer can be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide, and is preferably formed using silicon nitride oxide or silicon nitride. Note that in some cases, part of the insulating layer 117 may also be removed at the time of the above etching step.
Then, by irradiating regions 127 with an impurity element such as phosphorus (P) or arsenic (As) by using, as a mask, the gate electrode 125, the resist mask 123, the mask 124, and the like formed by the above etching step, the channel formation region 132 and the impurity regions 130 to which the impurity element is added are formed in the substrate 101 (see FIGS. 1A and 1B and FIG. 3C). The resist mask 123 is removed after this step. Note that phosphorus or arsenic is added here in order to form an n-type transistor; an impurity element such as boron (B) or aluminum (Al) may be added in the case of forming a p-type transistor. The concentration of the impurity added can be set as appropriate; the concentration is preferably set high when a semiconductor element is highly miniaturized. Note that it is preferable to perform heat treatment after adding the impurity element, in order to activate the impurity element or reduce defects which may be generated during addition of the impurity element.
Note that a sidewall insulating layer may be formed on a side surface of the gate electrode 125 in the channel length direction, and impurity regions to which the impurity element is added at a different concentration may be formed.
In addition, metal compound regions may be formed by forming a metal layer so as to cover the gate electrode 125, the impurity regions 130, and the like and performing heat treatment to cause a reaction between the metal layer and the semiconductor material. The metal layer can be formed by a variety of film formation methods such as a vacuum evaporation method, a sputtering method, and a spin coating method. The metal layer is preferably formed using a metal material which forms a low-resistance metal compound by reacting with the semiconductor material included in the substrate 101. Examples of such metal materials are titanium, tantalum, tungsten, nickel, cobalt, platinum, and the like. Note that in the case of forming such metal compound regions, part of the gate insulating layer 111 needs to be removed in advance.
As the heat treatment, irradiation with a flash lamp can be employed, for example. Although it is needless to say that another heat treatment method may be used, a method by which heat treatment can be achieved in an extremely short time is preferably used in order to improve the controllability of chemical reaction for formation of the metal compound. Note that the metal compound regions are formed by reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can properly reduce the electric resistance and improve element characteristics. Note that the metal layer is removed after the metal compound regions are formed.
Through the above steps, the transistor 160 is formed with the use of the substrate 101 including a semiconductor material (see FIG. 3C).
Next, a resist mask 126 whose edge portion overlaps with the mask 124 is formed so as to cover the components formed in the above steps. Then, part of the gate insulating layer 111, the insulating layer 117, and the element isolation insulating layer 121 is selectively removed by etching with the use of the resist mask 126 and the mask 124 (see FIG. 4A). At that time, depending on a material used for the mask 124, part of the mask 124 may be selectively removed (see FIG. 4A).
Then, the impurity region 128 is formed by adding an impurity element, which is similar to that added to the impurity regions 130, at high concentration to an exposed region of the substrate 101 with the use of the mask 124, the resist mask 126, and the like as a mask (see FIGS. 1A and 1B and FIG. 4A). The impurity region 128 is a region to which an impurity element is added at high concentration, and thus can also be used as a wiring. Note that the mask 124 and the resist mask 126 are removed after this step.
Next, an insulating layer 129 is formed so as to cover the components formed in the above steps (see FIG. 4B). The insulating layer 129 can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide. It is particularly preferable to use a low dielectric constant (low-k) material for the insulating layer 129 because capacitance due to overlap of electrodes or wirings can be sufficiently reduced. Note that a porous insulating layer with such a material may be employed as the insulating layer 129. The porous insulating layer has a lower dielectric constant than an insulating layer with high density and thus makes it possible to further reduce capacitance due to electrodes or wirings. Alternatively, the insulating layer 129 can be formed using an organic insulating material such as polyimide or acrylic. The insulating layer 129 may have a single-layer structure or a stacked-layer structure including two or more layers and can have, for example, a three-layer structure of a silicon oxynitride layer, a silicon nitride oxide layer, and a silicon oxide layer stacked in this order from the bottom.
After that, by performing CMP treatment of the insulating layer 129 before the formation of the transistor 162 and the capacitor 164, the insulating layer 131 is formed such that the upper surface of the gate electrode 125 is exposed (see FIG. 4C). As treatment for exposing the upper surface of the gate electrode 125, etching treatment or the like can be employed instead of the CMP treatment. Note that in order to improve characteristics of the transistor 162, the surface of the insulating layer 131 is preferably made as flat as possible; in this regard, the CMP treatment is preferable. In the case of using the CMP treatment, the surface of the insulating layer 131 can have a root-mean-square (RMS) roughness of 1 nm or less, for example.
Note that before or after each of the above steps, a step of forming an electrode, a wiring, a semiconductor layer, an insulating layer, or the like may be further performed. For example, when the wiring has a multilayer wiring structure of a stacked-layer structure including insulating layers and conductive layers, a highly integrated semiconductor device can also be realized.
Next, an oxide semiconductor layer 133 is formed over the insulating layer 131, the gate electrode 125, and the like (see FIG. 5A). The oxide semiconductor layer 133 is later processed into the oxide semiconductor layer 141 which is a component of the transistor 162. Note that an insulating layer functioning as a base may be provided over the insulating layer 131. The insulating layer can be formed by a PVD method, a CVD method, or the like. In that case, an opening is preferably formed in the insulating layer functioning as a base so as to expose the upper surface of the gate electrode 125.
As a material of the oxide semiconductor layer 133, for example, an oxide semiconductor material containing indium, an oxide semiconductor material containing indium and gallium, or the like may be used. As a material of the oxide semiconductor layer 133, a four-component metal oxide such as In—Sn—Ga—Zn—O-based material, a three-component metal oxide such as an In—Ga—Zn—O-based material, an In—Sn—Zn—O-based material, an In—Al—Zn—O-based material, a Sn—Ga—Zn—O-based material, an Al—Ga—Zn—O-based material, or a Sn—Al—Zn—O-based material, a two-component metal oxide such as an In—Zn—O-based material, a Sn—Zn—O-based material, an Al—Zn—O-based material, a Zn—Mg—O-based material, a Sn—Mg—O-based material, an In—Mg—O-based material, or an In—Ga—O-based material, a single-component metal oxide such as an In—O-based material, a Sn—O-based material, or a Zn—O-based material, or the like may be used. In addition, any of the above materials may contain SiO2. For example, an In—Ga—Zn—O-based material means an oxide material containing indium (In), gallium (Ga), and zinc (Zn), and there is no limitation on the stoichiometric proportion thereof. In addition, the material may contain an element other than In, Ga, and Zn.
In particular, an In—Ga—Zn—O-based oxide semiconductor material has sufficiently high resistance when there is no electric field and thus off-state current can be sufficiently reduced. In addition, also having high field-effect mobility, the In—Ga—Zn—O-based oxide semiconductor material is suitable for a semiconductor material used in a semiconductor device.
As a typical example of the In—Ga—Zn—O-based oxide semiconductor material, an oxide semiconductor material represented by InGaO3(ZnO)m (m>0) is given. Using M instead of Ga, there is an oxide semiconductor material represented by InMO3(ZnO)m (m>0). Here, M denotes one or more metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), or the like. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, or the like. Note that the above-described compositions are derived from the crystal structures that the oxide semiconductor material can have and are mere examples.
As a target used for forming the oxide semiconductor layer 133 by a sputtering method, a target having a composition ratio of In:Ga:Zn=1:x:y (x is greater than or equal to 0 and y is greater than or equal to 0.5 and less than or equal to 5) is preferably used. For example, a target having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] (x=1, y=1) (i.e., In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) or the like can be used. In addition, a target having a composition ratio of In:Ga:Zn=1:1:0.5 [atomic ratio] (x=1, y=0.5) (i.e., In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]), a target having a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio] (x=1, y=2) (i.e., In2O3:Ga2O3:ZnO=1:1:4 [molar ratio]), or a target having a composition ratio of In:Ga:Zn=1:0:1 [atomic ratio] (x=0, y=1) (i.e., In2O3:Ga2O3:ZnO=1:0:2 [molar ratio]) can also be used.
In the case where an In—Zn—O-based material is used as an oxide semiconductor, a target therefore has a composition ratio of In:Zn=50:1 to 1:2 in an atomic ratio (In2O3:ZnO=25:1 to 1:4 in a molar ratio), preferably, In:Zn=20:1 to 1:1 in an atomic ratio (In2O3:ZnO=10:1 to 1:2 in a molar ratio), further preferably, In:Zn=15:1 to 1.5:1 in an atomic ratio (In2O3:ZnO=15:2 to 3:4 in a molar ratio). For example, in a target used for formation of an In—Zn—O-based oxide semiconductor which has an atomic ratio of In:Zn:O=X:Y:Z, the relation of Z>1.5X+Y is satisfied.
In this embodiment, an oxide semiconductor layer having an amorphous structure is formed as the oxide semiconductor layer 133 by a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target. The thickness ranges from 1 nm to 50 nm, preferably from 2 nm to 20 nm, more preferably from 3 nm to 15 nm.
The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, and more preferably 99.9% or more. The use of the metal oxide target with high relative density makes it possible to form an oxide semiconductor layer having a dense structure.
The atmosphere in which the oxide semiconductor layer 133 is formed is preferably a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. Specifically, it is preferable to use a high-purity gas atmosphere, for example, from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of 1 ppm or less (preferably, 10 ppb or less).
In forming the oxide semiconductor layer 133, for example, an object to be processed is held in a treatment chamber that is maintained under reduced pressure, and the object to be processed is heated to a temperature higher than or equal to 100° C. and lower than 550° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C. Alternatively, the temperature of an object to be processed in forming the oxide semiconductor layer 133 may be room temperature (25° C.±10° C.). Then, moisture in the treatment chamber is removed, a sputtering gas from which hydrogen, water, or the like is removed is introduced, and the above-described target is used; thus, the oxide semiconductor layer 133 is formed. By forming the oxide semiconductor layer 133 while heating the object to be processed, an impurity in the oxide semiconductor layer 133 can be reduced. Moreover, damage due to sputtering can be reduced. In order to remove the moisture in the treatment chamber, it is preferable to use an entrapment vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, or the like can be used. A turbomolecular pump provided with a cold trap may be used. Since hydrogen, water, or the like can be removed from the treatment chamber evacuated with a cryopump or the like, the concentration of an impurity in the oxide semiconductor layer can be reduced.
For example, conditions for forming the oxide semiconductor layer 133 can be set as follows: the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen (100% oxygen) atmosphere, an argon (100% argon) atmosphere, or a mixed atmosphere of oxygen and argon. Note that a pulsed direct current (DC) power source is preferably used because dust (such as powder substances generated in film formation) can be reduced and the film thickness can be made uniform. The appropriate thickness of the oxide semiconductor layer 133 differs depending on the oxide semiconductor material to be used, the intended use of the semiconductor device, or the like; therefore, the thickness can be determined as appropriate in accordance with the material, the intended use, or the like. Note that when the insulating layer 131 is formed in the above manner, a surface over which a portion corresponding to the channel formation region in the oxide semiconductor layer 133 is to be formed can be sufficiently planarized; thus, the oxide semiconductor layer can be suitably formed even when having a small thickness. In addition, because the portion corresponding to the channel formation region in the oxide semiconductor layer 133 can be planarized, the leakage current can be made smaller than that in the case where the portion is not planarized.
Note that before the oxide semiconductor layer 133 is formed by a sputtering method, reverse sputtering in which plasma is generated with an argon gas introduced may be performed so that a material attached to a formation surface (e.g., a surface of the insulating layer 131) is removed. Here, the reverse sputtering is a method in which ions collide with a surface to be processed so that the surface is modified, in contrast to normal sputtering in which ions collide with a sputtering target. An example of a method for making ions collide with a surface to be processed is a method in which high-frequency voltage is applied to the surface side in an argon atmosphere so that plasma is generated near the object to be processed. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of an argon atmosphere.
After formation of the oxide semiconductor layer 133, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 133. Through the first heat treatment, excess hydrogen (including water or a hydroxyl group) in the oxide semiconductor layer 133 can be removed, the structure of the oxide semiconductor layer 133 can be ordered, and defect states in an energy gap can be reduced. For example, the temperature of the first heat treatment can be set higher than or equal to 300° C. and lower than 550° C., preferably higher than or equal to 400° C. and lower than or equal to 500° C.
For example, after an object to be processed is introduced into an electric furnace including a resistance heater or the like, the heat treatment can be performed at 450° C. for one hour in a nitrogen atmosphere. The oxide semiconductor layer is not exposed to the air during the heat treatment so that entry of water or hydrogen can be prevented.
The heat treatment apparatus is not limited to the electric furnace and may be an apparatus for heating an object to be processed by thermal radiation or thermal conduction from a medium such as a heated gas. For example, a lamp rapid thermal annealing (LRTA) apparatus or a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object to be processed by heat treatment, for example, nitrogen or a rare gas such as argon is used.
For example, as the first heat treatment, GRTA treatment may be performed as follows. The object to be processed is put in a heated inert gas atmosphere, heated for several minutes, and taken out of the inert gas atmosphere. The GRTA treatment enables high-temperature heat treatment in a short time. Moreover, the GRTA treatment can be employed even when the temperature exceeds the upper temperature limit of the object to be processed. Note that the inert gas may be switched to a gas including oxygen during the treatment. This is because defect states in an energy gap caused by oxygen vacancies can be reduced by performing the first heat treatment in an atmosphere including oxygen.
Note that as the inert gas atmosphere, an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).
The above heat treatment (the first heat treatment) can also be referred to as dehydration treatment, dehydrogenation treatment, or the like because it has the effect of removing hydrogen, water, or the like. The dehydration treatment or the dehydrogenation treatment can be performed after an oxide semiconductor layer 135 is formed later, after the oxide semiconductor layer 141 is formed, after the gate insulating layer 147 is formed, or after the gate electrode 149 is formed. Such dehydration treatment or dehydrogenation treatment may be performed once or plural times.
Next, the oxide semiconductor layer 135 is formed by selectively etching the oxide semiconductor layer 133 (see FIG. 5B). The length of the oxide semiconductor layer 141 in the channel length direction is determined by this etching step. The oxide semiconductor layer 133 is preferably etched by dry etching in terms of element miniaturization, but may be etched by wet etching. An etching gas or an etchant can be selected as appropriate depending on a material to be etched.
Then, a conductive layer is formed so as to cover the gate electrode 125, the insulating layer 131, and the oxide semiconductor layer 135 and is then selectively etched; thus, a conductive layer 137 and a conductive layer 139 are formed (see FIG. 5B). The conductive layer 137 and the conductive layer 139 are later processed into the source electrode 143 and the drain electrode 145. Note that before the conductive layer is formed, a protective insulating layer may be formed over the oxide semiconductor layer 135 in order to prevent the oxide semiconductor layer 135 from being damaged in the step of etching the conductive layer.
The conductive layer can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. As a material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy including any of these elements as a component, or the like can be used. A material including one of manganese, magnesium, zirconium, beryllium, neodymium, and scandium or a combination of a plurality of these elements may be used.
The conductive layer may have a single-layer structure or a stacked-layer structure including two or more layers. For example, the conductive layer may have a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, or the like. Note that the conductive layer having a single-layer structure of a titanium film or a titanium nitride film has an advantage in that it can be easily processed into the source electrode 143 and the drain electrode 145 having a tapered shape.
The conductive layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an indium oxide-tin oxide alloy (In2O3—SnO2, which is abbreviated to ITO in some cases), an indium oxide-zinc oxide alloy (In2O3—ZnO), any of these metal oxide materials including silicon or silicon oxide, or the like can be used.
Although either dry etching or wet etching may be performed as the etching of the conductive layer, dry etching with high controllability is preferably used for miniaturization. The etching may be performed so that the source electrode 143 and the drain electrode 145 to be formed have a tapered shape. The taper angle can be, for example, greater than or equal to 30° and less than or equal to 60°.
The channel length (L) of the transistor 162 is determined by a distance between lower edge portions of the conductive layer 137 and the conductive layer 139 (the source electrode 143 and the drain electrode 145). Note that for light exposure for forming a mask in the case of manufacturing a transistor with a channel length (L) of less than 25 nm, light exposure is preferably performed with extreme ultraviolet light whose wavelength is several nanometers to several tens of nanometers, which is extremely short. The resolution of light exposure with extreme ultraviolet rays is high and the depth of focus is large. For these reasons, the channel length (L) of the transistor to be formed later can be made sufficiently small, and accordingly, the circuit can operate at higher speed.
Next, the oxide semiconductor layer 141, the source electrode 142 (which is processed into the source electrode 143 in a later step), and the drain electrode 145 are formed by selectively etching the oxide semiconductor layer 135, the conductive layer 137, and the conductive layer 139 (see FIG. 5C). By this etching step, a portion of a side surface of the oxide semiconductor layer 141 and a portion of a side surface of the source electrode 142 (or a portion of a side surface of the drain electrode 145) are substantially aligned with each other when seen from a planar direction. Furthermore, the side surfaces substantially aligned with each other as described above (for example, the side surface of the oxide semiconductor layer 141) are parallel with the channel length direction. Here, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface of the substrate 101. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers with the same mask. Furthermore, the term “channel length direction” refers to a direction from the source electrode 142 toward the drain electrode 145, or the opposite direction, along the shortest path between the source electrode 142 and the drain electrode 145.
By etching the oxide semiconductor layer 135, the conductive layer 137, and the conductive layer 139 at a time as described above, it becomes possible to eliminate variation in shape which may be caused by mask misalignment when the components are formed separately by etching. In that case, there is no need to leave a margin for mask alignment and it is therefore possible to sufficiently increase the degree of integration.
Note that the oxide semiconductor layer 135, the conductive layer 137, and the conductive layer 139 are preferably etched by dry etching in terms of element miniaturization, but may be etched by wet etching. An etching gas or an etchant can be selected as appropriate depending on a material to be etched. The oxide semiconductor layer 135, the conductive layer 137, and the conductive layer 139 preferably include materials which are processable by the same process (for example, by a dry etching process using the same etching gas).
Next, a gate insulating layer 146 (which is later processed into the gate insulating layer 147) is formed so as to cover the oxide semiconductor layer 141 (see FIG. 6A). The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 is preferably formed so as to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, gallium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium aluminate (HfAlxOy (x>0, y>0)), hafnium silicate to which nitrogen is added, hafnium aluminate to which nitrogen is added, or the like. The gate insulating layer 146 may have a single-layer structure or a stacked-layer structure. There is no particular limitation on the thickness of the gate insulating layer 146; the thickness is preferably small in order to ensure the operation of the transistor when the semiconductor device is miniaturized. Note that the gate insulating layer 146 functions as not only the gate insulating layer of the transistor 162 but also a dielectric of the capacitor 164.
Note that when the gate insulating layer is thin, gate leakage due to a tunneling effect or the like becomes a problem. In order to solve the problem of gate leakage, the gate insulating layer 146 may be formed using a high dielectric constant (high-k) material such as hafnium oxide, tantalum oxide, yttrium oxide, hafnium silicate, hafnium silicate to which nitrogen is added, or hafnium aluminate to which nitrogen is added. The use of a high-k material for the gate insulating layer 146 makes it possible to increase the thickness in order to suppress gate leakage as well as ensuring electrical properties. For example, the relative permittivity of hafnium oxide is approximately 15, which is much higher than that of silicon oxide which is 3 to 4. Therefore, it is possible to increase the thickness of the gate insulating layer as well as ensuring electrical properties. Note that a stacked-layer structure of a film including a high-k material and a film including any of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and the like may also be employed.
After the gate insulating layer 146 is formed, second heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is set in the range of 200° C. to 450° C., preferably 250° C. to 350° C. For example, the heat treatment may be performed at 250° C. for one hour in a nitrogen atmosphere. By the second heat treatment, variation in electrical characteristics of the transistor can be reduced. In the case where the gate insulating layer 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 141 and oxygen vacancies in the oxide semiconductor layer 141 are filled.
Note that the second heat treatment is performed in this embodiment after the gate insulating layer 146 is formed; there is no limitation on the timing of the second heat treatment. For example, the second heat treatment may be performed after the gate electrode is formed.
By reducing impurities and filling oxygen vacancies in the oxide semiconductor layer 141 by performing the first heat treatment and the second heat treatment as described above, the oxide semiconductor layer 141 can be purified so as to contain impurities other than main components as little as possible.
Note that oxygen plasma treatment may be performed instead of the second heat treatment or at the same time as the second heat treatment. Also by the oxygen plasma treatment, oxygen can be supplied to the oxide semiconductor layer 141 and oxygen vacancies in the oxide semiconductor layer 141 can be filled.
Next, the gate electrode 149 and the electrode 151 are formed over the gate insulating layer 146 (see FIG. 6B). Note that a sidewall insulating layer may be formed on a side surface of the gate electrode 149 or the electrode 151 in the channel length direction. With such a sidewall insulating layer, the side surface of the electrode 151 serving as an upper electrode of the capacitor 164 can be protected, and leakage current can be reduced between the upper electrode and a lower electrode of the capacitor 164, for example.
The gate electrode 149 and the electrode 151 can be formed by forming a conductive layer over the gate insulating layer 146 and then by selectively etching the conductive layer. The conductive layer to be the gate electrode 149 and the electrode 151 can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The details are similar to those of the source electrode 143, the drain electrode 145, or the like; thus, the description thereof can be referred to.
Next, a resist mask 152 whose edge portion overlaps with the electrode 151 is formed so as to cover the components formed in the above steps. Then, part of the gate insulating layer 146 and the source electrode 142 (which may be the drain electrode 145 in some cases) is selectively removed by etching with the use of the resist mask 152 and the electrode 151; thus, the gate insulating layer 147 and the source electrode 143 are formed (see FIG. 6C). By this etching step, a portion of a side surface of the gate insulating layer 147 and a portion of a side surface of the source electrode 143 (or a portion of a side surface of the drain electrode 145) are substantially aligned with each other when seen from a planar direction. Furthermore, the portion of the side surface of the gate insulating layer 147, the portion of the side surface of the source electrode 143 (or the portion of the side surface of the drain electrode 145), and a portion of a side surface of the electrode 151 are preferably aligned with each other when seen from the planar direction. The side surfaces substantially aligned with each other as described above (for example, the side surface of the gate insulating layer 147) are perpendicular to the channel length direction. Here, the expression “portions of side surfaces are aligned with each other when seen from a planar direction” means that side surfaces of objects overlap each other at least partly when seen from a direction perpendicular to a surface of the substrate 101. In addition, the expression “substantially aligned” does not require exact alignment. For example, the expression “substantially aligned” includes a degree of alignment in a shape obtained by etching a plurality of layers using the same mask. Furthermore, the term “channel length direction” refers to a direction from the source electrode 143 toward the drain electrode 145, or the opposite direction, along the shortest path between the source electrode 143 and the drain electrode 145.
Because the source electrode 143 (or the drain electrode 145) of the transistor 162 can be formed in the above etching step with the minimum feature size, the degree of integration of the semiconductor device can be sufficiently increased.
Note that the gate insulating layer 147 and the source electrode 143 (or the drain electrode 145) are preferably etched by dry etching in terms of element miniaturization, but may be etched by wet etching. An etching gas or an etchant can be selected as appropriate depending on a material to be etched. In addition, the gate insulating layer 147 and the source electrode 143 (or the drain electrode 145) preferably include materials which are successively processable by changing etching conditions during the etching step, and preferably include, for example, materials which are successively processable by changing conditions, e.g., by changing gases, during a dry etching step. In particular, the gate insulating layer 147 and the source electrode 143 (or the drain electrode 145) preferably include materials which are processable by the same process (for example, by a dry etching process using the same etching gas).
Through the above steps, the transistor 162 including the oxide semiconductor layer 141 and the capacitor 164 including the source electrode 143, the electrode 151, and the gate insulating layer 147 are completed (see FIGS. 1A and 1B and FIG. 7). Note that the transistor 162 includes the oxide semiconductor layer 141 which is i-type (intrinsic) or substantially intrinsic, and therefore exhibits highly excellent characteristics.
Note that the transistor 162 manufactured through the above steps has the feature of sufficiently small off-state current.
After the above steps, an insulating layer may be formed so as to cover the gate insulating layer 147, the gate electrode 149, and the electrode 151. The insulating layer can be formed by a PVD method, a CVD method, or the like. The insulating layer can be formed so as to have a single-layer structure or a stacked-layer structure using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, or aluminum oxide.
The insulating layer is preferably formed using a low dielectric constant material or a low dielectric constant structure (such as a porous structure). This is because when the insulating layer has a low dielectric constant, capacitance generated between wirings, electrodes, or the like can be reduced and operation at higher speed can be achieved.
In addition, the insulating layer is desirably formed so as to have a flat surface. This is because when the insulating layer has a flat surface, an electrode, a wiring, or the like can be favorably formed over the insulating layer even in the case where the semiconductor device or the like is miniaturized. Note that the insulating layer can be planarized using a method such as chemical mechanical polishing (CMP).
In addition, a variety of wirings, electrodes, or the like may be formed after the above steps. The wirings or the electrodes can be formed by a method such as a so-called damascene method or dual damascene method.
Through the above steps, the semiconductor device having the structure illustrated in FIGS. 1A and 1B can be manufactured.
In an embodiment in which side surfaces (or portions thereof) of components of a transistor are aligned with each other as described above in this embodiment, a highly integrated semiconductor device can be realized. In particular, in a structure including three-dimensionally integrated transistors, a more significant effect can be obtained in combination with an increase in the degree of integration owing to this three-dimensional structure.
The configurations, methods, and the like described in this embodiment can be combined as appropriate with any of the configurations, methods, and the like described in the other embodiments.
Embodiment 2
In this embodiment, an example of application of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. 8A-1, 8A-2, and 8B and FIGS. 9 to 12. Here, an example of a memory device is described. Note that in some circuit diagrams, “OS” is written beside a transistor in order to indicate that the transistor includes an oxide semiconductor.
<Basic Circuit>
First, a basic circuit configuration and an operation thereof will be described with reference to FIGS. 8A-1, 8A-2, and 8B. In a semiconductor device illustrated in FIG. 8A-1, a first wiring (1st Line) is electrically connected to a source electrode (or a drain electrode) of a transistor 160. A second wiring (2nd Line) is electrically connected to a drain electrode (or a source electrode) of the transistor 160. A third wiring (3rd Line) is electrically connected to a source electrode (or a drain electrode) of a transistor 162. A fourth wiring (4th Line) is electrically connected to a gate electrode of the transistor 162. A gate electrode of the transistor 160 and a drain electrode (or a source electrode) of the transistor 162 are electrically connected to one electrode of a capacitor 164. A fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 164.
Here, as the transistor 162, the transistor 162 including an oxide semiconductor as described in the above embodiment can be used. A transistor including an oxide semiconductor has a characteristic of a significantly small off-state current. For that reason, a potential of the gate electrode of the transistor 160 can be held for an extremely long period by turning off the transistor 162. By providing the capacitor 164, holding of charge applied to the gate electrode of the transistor 160 and reading of data held can be performed more easily.
Although there is no particular limitation on the transistor 160, the transistor 160 described in the above embodiment is preferably used. In terms of increasing the speed of reading data, it is preferable to use a transistor with high switching speed such as a transistor formed using single crystal silicon, for example.
Alternatively, a structure in which the capacitor 164 is not provided is also possible as illustrated in FIG. 8B.
The semiconductor device in FIG. 8A-1 utilizes a characteristic in which the potential of the gate electrode of the transistor 160 can be held, and can thus write, hold, and read data as follows.
First of all, writing and holding of data will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 160 and to the capacitor 164. That is, predetermined charge is supplied to the gate electrode of the transistor 160 (writing). Here, one of two kinds of charges providing different potentials (hereinafter, a charge providing a low potential is referred to as charge QL and a charge providing a high potential is referred to as charge QH) is applied. Note that three or more kinds of charges providing different potentials may be applied to improve storage capacity. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, so that the transistor 162 is turned off. Thus, the charge supplied to the gate electrode of the transistor 160 is held (holding).
Since the off-state current of the transistor 162 is significantly small, the charge of the gate electrode of the transistor 160 is held for a long time.
Next, reading of data will be described. By supplying an appropriate potential (a reading potential) to the fifth wiring while supplying a predetermined potential (a constant potential) to the first wiring, the potential of the second wiring varies depending on the amount of charge held at the gate electrode of the transistor 160. This is because in general, when the transistor 160 is an n-channel transistor, an apparent threshold voltage Vth—H in the case where QH is given to the gate electrode of the transistor 160 is lower than an apparent threshold voltage Vth—L in the case where QL is given to the gate electrode of the transistor 160. Here, an apparent threshold voltage refers to the potential of the fifth wiring, which is needed to turn on the transistor 160. Thus, the potential of the fifth wiring is set to a potential V0 intermediate between Vth—H and Vth—L, whereby charge supplied to the gate electrode of the transistor 160 can be determined. For example, in the case where QH is supplied in writing, when the potential of the fifth wiring is V0 (>Vth—H), the transistor 160 is turned on. In the case where QL is supplied in writing, even when the potential of the fifth wiring is V0 (<Vth—L), the transistor 160 remains off. Therefore, the data held can be read by measuring the potential of the second wiring.
Note that in the case where memory cells are arrayed to be used, it is necessary that data of only a desired memory cell can be read. In the case where data of a predetermined memory cell are read and data of the other memory cells are not read, fifth wirings in memory cells that are not a target for reading are supplied with a potential at which the transistors 160 are turned off regardless of the state of the gate electrodes, that is, a potential lower than Vth—H. Alternatively, fifth wirings are supplied with a potential at which the transistors 160 are turned on regardless of the state of the gate electrodes, that is, a potential higher than Vth—L.
Next, rewriting of data will be described. Rewriting of data is performed in a manner similar to that of the writing and holding of data. That is, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring (a potential for new data) is supplied to the gate electrode of the transistor 160 and to the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, so that the transistor 162 is turned off. Accordingly, the gate electrode of the transistor 160 is supplied with charge for new data.
In the semiconductor device according to an embodiment of the disclosed invention, data can be directly rewritten by another data writing operation as described above. Therefore, extraction of charge from a floating gate with the use of a high voltage which is necessary for a flash memory or the like is not needed, and thus a decrease in operation speed due to erasing operation can be suppressed. In other words, high-speed operation of the semiconductor device can be realized.
Note that the drain electrode (or the source electrode) of the transistor 162 is electrically connected to the gate electrode of the transistor 160 and therefore has a function similar to that of a floating gate of a floating gate transistor used for a nonvolatile memory element. A portion where the drain electrode (or the source electrode) of the transistor 162 and the gate electrode of the transistor 160 are electrically connected to each other is called a node FG in some cases. When the transistor 162 is turned off, the node FG can be regarded as being embedded in an insulator and thus charge is held at the node FG. The off-state current of the transistor 162 including an oxide semiconductor is smaller than or equal to 1/100000 of the off-state current of a transistor including a silicon semiconductor; thus, loss of the charge accumulated in the node FG due to leakage in the transistor 162 is negligible. That is, with the transistor 162 including an oxide semiconductor, a nonvolatile memory device which can hold data without being supplied with power can be realized.
For example, when the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA (zeptoampere) is 1×10−21 A) or less and the capacitance of the capacitor 164 is approximately 10 fF, data can be held for 104 seconds or longer. It is needless to say that the holding time depends on transistor characteristics and capacitance.
Further, the semiconductor device according to an embodiment of the disclosed invention does not have the problem of deterioration of a gate insulating film (a tunnel insulating film), which is a problem of a conventional floating gate transistor. That is, the problem of deterioration of a gate insulating film due to injection of electrons into a floating gate, which is a conventional problem, can be solved. This means that there is no limit on the number of write cycles in principle. Furthermore, a high voltage needed for writing or erasing in a conventional floating gate transistor is not necessary.
Components such as transistors in the semiconductor device in FIG. 8A-1 can be regarded as including resistors and capacitors as illustrated in FIG. 8A-2. That is, in FIG. 8A-2, the transistor 160 and the capacitor 164 are each regarded as including a resistor and a capacitor. R1 and C1 denote the resistance and the capacitance of the capacitor 164, respectively. The resistance R1 corresponds to the resistance of the insulating layer included in the capacitor 164. R2 and C2 denote the resistance and the capacitance of the transistor 160, respectively. The resistance R2 corresponds to the resistance of the gate insulating layer at the time when the transistor 160 is turned on. The capacitance C2 corresponds to a so-called gate capacitance (capacitance formed between the gate electrode and the source or drain electrode, and capacitance formed between the gate electrode and the channel formation region).
A charge holding period (also referred to as a data holding period) is determined mainly by the off-state current of the transistor 162 under the conditions where the gate leakage current of the transistor 162 is sufficiently small and R1 and R2 satisfy R1≧ROS and R2≧ROS, where ROS is the resistance (also referred to as effective resistance) between the source electrode and the drain electrode in a state where the transistor 162 is turned off.
On the other hand, in the case where the above conditions are not satisfied, it is difficult to secure a sufficient holding period even if the off-state current of the transistor 162 is sufficiently small. This is because a leakage current other than the off-state current of the transistor 162 (e.g., a leakage current generated between the source electrode and the gate electrode of the transistor 160) is large. Accordingly, it can be said that it is preferable that the semiconductor device disclosed in this embodiment satisfies the above relationships of R1≧ROS and R2≧ROS.
Meanwhile, it is desirable that C1 and C2 satisfy C1≧C2. This is because if C1 is large, when the potential of the node FG is controlled by the fifth wiring, the potential of the fifth wiring can be efficiently supplied to the node FG and the difference between potentials supplied to the fifth wiring (e.g., a reading potential and a non-reading potential) can be kept small.
When the above relationships are satisfied, a more favorable semiconductor device can be realized. Note that R1 and R2 depend on the gate insulating layer of the transistor 160 and the insulating layer of the capacitor 164. The same applies to C1 and C2. Therefore, the material, the thickness, and the like of the gate insulating layer are preferably set as appropriate to satisfy the above relationships.
In the semiconductor device described in this embodiment, the node FG has a function similar to a floating gate of a floating gate transistor of a flash memory or the like, but the node FG of this embodiment has a feature which is essentially different from that of the floating gate of the flash memory or the like.
In the case of a flash memory, since a high potential is applied to a control gate, it is necessary to keep a proper distance between cells in order to prevent the potential of the control gate from affecting a floating gate of an adjacent cell. This is one factor inhibiting higher integration of the semiconductor device. The factor is attributed to a basic principle of a flash memory, in which a tunneling current is generated by applying a high electric field.
On the other hand, the semiconductor device according to this embodiment is operated by switching of a transistor including an oxide semiconductor and does not use the above-described principle of charge injection by a tunneling current. That is, a high electric field for charge injection is not necessary, unlike a flash memory. Accordingly, it is not necessary to consider an influence of a high electric field from a control gate on an adjacent cell, and this facilitates an increase in the degree of integration.
In addition, the semiconductor device according to this embodiment is advantageous over a flash memory also in that a high electric field is not necessary and a large peripheral circuit (such as a step-up circuit) is not necessary. For example, the highest voltage applied to the memory cell according to this embodiment (the difference between the highest potential and the lowest potential applied to respective terminals of the memory cell at the same time) can be 5 V or less, preferably 3 V or less, in each memory cell in the case where data of two stages (one bit) is written.
In the case where the relative permittivity ∈r1 of the insulating layer included in the capacitor 164 is different from the relative permittivity ∈r2 of the insulating layer included in the transistor 160, it is easy to satisfy C1≧C2 while satisfying 2·S2≧S1 (preferably S2≧S1), where S1 is the area of the insulating layer included in the capacitor 164 and S2 is the area of the insulating layer forming a gate capacitor of the transistor 160. In other words, C1 can easily be made greater than or equal to C2 while the area of the insulating layer included in the capacitor 164 is made small. Specifically, for example, a film including a high-k material such as hafnium oxide or a stack of a film including a high-k material such as hafnium oxide and a film including an oxide semiconductor is used for the insulating layer included in the capacitor 164 so that ∈r1 can be set to 10 or more, preferably 15 or more, and silicon oxide is used for the insulating layer forming the gate capacitor so that ∈r2 can be set to approximately 3 to 4.
A combination of such structures enables the semiconductor device according to one embodiment of the disclosed invention to have further higher integration.
Note that in addition to the increase in the degree of integration, a multilevel technique can be employed to increase the storage capacity of the semiconductor device. For example, three or more levels of data are written to one memory cell, whereby the storage capacity can be increased as compared to the case where two-level (one-bit) data is written. The multilevel technique can be achieved by, for example, supplying charge Q providing a potential to the gate electrode of the transistor 160, in addition to charge QL providing a low potential and charge QH providing a high potential as described above.
APPLICATION EXAMPLE
Next, a more specific circuit configuration to which the circuit illustrated in FIGS. 8A-1, 8A-2, and 8B is applied and an operation thereof will be described with reference to FIGS. 9 to 12.
FIG. 9 illustrates an example of a circuit diagram of a semiconductor device having a storage capacity of (m×n) bits.
The semiconductor device according to one embodiment of the present invention includes m (m is an integer of 2 or more) signal lines S, m word lines WL, n (n is an integer of 2 or more) bit lines BL, k (k is a natural number smaller than n) source lines SL, a memory cell array having memory cells 1100 arranged in a matrix of m rows (in the vertical direction)×n columns (in the horizontal direction), and peripheral circuits such as a first driver circuit 1111, a second driver circuit 1112, a third driver circuit 1113, and a fourth driver circuit 1114. Here, the structure illustrated in FIG. 8A-1 is applied to the memory cells 1100. The memory cells 1100 are connected in parallel with respect to the wirings.
Each of the memory cells 1100 includes a first transistor, a second transistor, and a capacitor. In each of the memory cells 1100, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other, and the source line SL and a source electrode (a source region) of the first transistor are electrically connected to each other. In addition, the bit line BL, the other of the source electrode and the drain electrode of the second transistor, and a drain electrode of the first transistor are electrically connected to each other. The word line WL and the other of the electrodes of the capacitor are electrically connected to each other. The signal line S and a gate electrode of the second transistor are electrically connected to each other. In other words, the source line SL corresponds to the first wiring (1st Line) in the structure illustrated in FIG. 8A-1, the bit line BL corresponds to the second wiring (2nd Line) and the third wiring (3rd Line), the signal line S corresponds to the fourth wiring (4th Line), and the word line WL corresponds to the fifth wiring (5th Line).
In the memory cell array illustrated in FIG. 9, the bit lines BL, the source lines SL, the word lines WL, and the signal lines S form a matrix. To one bit line BL, m memory cells 1100 arranged in one column are connected. In addition, n memory cells 1100 arranged in one row are connected to one word line WL and one signal line S. Further, the number of source lines SL is smaller than that of the bit lines BL; therefore, one source line SL needs to be connected to a plurality of memory cells 1100 including at least memory cells 1100 which are connected to different bit lines BL. In other words, j (j is an integer greater than or equal to (m+1) and smaller than or equal to (m×n)) memory cells 1100 are connected to one source line SL. Note that the first transistors included in the plurality of memory cells 1100 connected to one source line SL have a common source region. Note that it is preferable that the source line SL be arranged in the proportion of one to plural bit lines BL (i.e., (n/k) is an integer). In that case, if an equal number of the memory cells 1100 is connected to each source line SL, (m×n/k) memory cells 1100 are connected to each source line SL.
As in the memory cell array illustrated in FIG. 9, when the source line SL, which connects one memory cell 1100 to another memory cell 1100, is connected to a plurality of memory cells 1100 including at least memory cells 1100 which are connected to different bit lines BL to make the number of source lines SL smaller than that of bit lines BL, the number of source lines can be made sufficiently small; thus, the degree of integration of the semiconductor device can be increased.
The bit line BL is electrically connected to the first driver circuit 1111. The source line SL is electrically connected to the second driver circuit 1112. The signal line S is electrically connected to the third driver circuit 1113. The word line WL is electrically connected to the fourth driver circuit 1114. Note that here, the first driver circuit 1111, the second driver circuit 1112, the third driver circuit 1113, and the fourth driver circuit 1114 are separately provided; however, the disclosed invention is not limited to this. A driver circuit having any one or some of the functions may alternatively be used.
Next, write operation and read operation will be described. FIG. 10 is an example of a timing chart of write operation and read operation of the semiconductor device illustrated in FIG. 9.
Although operation of a semiconductor device including a memory cell array of two rows and two columns will be described for simplification here, the disclosed invention is not limited to this.
Writing data to the memory cell 1100 (1,1) and the memory cell 1100 (1,2), which are in the first row, and reading data from the memory cell 1100 (1,1) and the memory cell 1100 (1,2), which are in the first row, will be described. Note that in the following description, the data to be written to the memory cell (1,1) is “1” and data to be written to the memory cell (1,2) is “0”.
First of all, the write operation will be described. A potential V1 is applied to the signal line S(1) in the first row, whereby the second transistors in the first row are turned on. Further, a potential of 0 V is applied to the signal line S(2) in the second row, whereby the second transistors in the second row are turned off.
Further, a potential V2 is applied to the bit line BL(1) in the first column and the potential of 0 V is applied to the bit line BL(2) in the second column.
Thus, the potential V2 is applied to the node FG of the memory cell (1,1), and the potential of 0 V is applied to the node FG of the memory cell (1,2). Here, the potential V2 is higher than the threshold value of the first transistor. Then, the potential of the signal line S(1) in the first row is set to 0 V, whereby the second transistors in the first row are turned off to finish writing. It is preferable that the potential V2 be substantially equal to the potential V1 or lower than or equal to the potential V1.
Note that the word line WL(1) in the first row and the word line WL(2) in the second row are at the potential of 0 V during the write operation. At the end of the write operation, before the potential of the bit line BL(1) in the first column is changed, the potential of the signal line S(1) in the first row is set to 0 V. After the write operation, the threshold value of a memory cell is Vw0 in the case where data “0” has been written and Vw1 in the case where data “1” has been written. Here, the threshold value of the memory cell means the voltage of the terminal connected to the word line WL, which changes resistance between the source electrode and the drain electrode of the first transistor. Note that, here, Vw0>0>Vw1 is satisfied.
Second, the read operation will be described. Here, the bit lines BL are electrically connected to a reading circuit illustrated in FIG. 11.
The potential of 0 V and the potential VL are applied to the word line WL(1) in the first row and the word line WL(2) in the second row, respectively. The potential VL is lower than the threshold value Vw1. When the word line WL(1) is at the potential of 0 V, in the first row, the first transistor of the memory cell in which data “0” is held is turned off, and the first transistor of the memory cell in which data “1” is held is turned on. When the word line WL(2) is at the potential VL, in the second row, the first transistors of the memory cells in which either data “0” or data “1” is held are turned off.
As a result, the resistance between the bit line BL(1) and the source line SL is low because the first transistor in the memory cell (1,1) is on, and the resistance between the bit line BL(2) and the source line SL is high because the first transistor in the memory cell (1,2) is off. The reading circuit connected to the bit line BL(1) and the bit line BL(2) can read data utilizing a difference in resistance of the bit line.
Note that, during the read operation, the potential of 0 V and the potential VL are applied to the signal line S(1) and the signal line S(2), respectively, whereby all the second transistors are off. The potential of the nodes FG in the first row is 0 V or V2; thus, all the second transistors can be turned off by setting the potential of the signal line S(1) at 0 V. On the other hand, if the potential VL is applied to the word line WL(2), the potential of the nodes FG in the second row would become lower than the potential right after writing. Therefore, in order to prevent the second transistors from being turned on, the signal line S(2) is set at a low potential (the potential VL) which is the same as the potential of the word line WL(2). That is, the potentials of the signal line S and the word line WL in the row where data is not read are set to the same low potential (the potential VL). Thus, all the second transistors can be turned off.
Next, an output potential in the case where the circuit in FIG. 11 is used as a reading circuit will be described. In the reading circuit illustrated in FIG. 11, the bit line BL is connected to a clocked inverter and a transistor which is diode-connected to a wiring to which the potential V1 is applied, through a switch controlled by a read enable signal (a RE signal). Further, a fixed potential (e.g., 0 V) is applied to the source line SL. Since the resistance between the bit line BL(1) and the source line SL is low, a low potential is applied to the clocked inverter and an output D(1) is High. Since the resistance between the bit line BL(2) and the source line SL is high, a high potential is applied to the clocked inverter and the output D(2) is Low.
The operation potentials can be set as follows, for example; V1=2 V, V2=1.5 V, VH=2 V, and VL=−2 V.
Next, write operation which is different from the above write operation will be described. The data to be written is the same as that in the above write operation. FIG. 12 is an example of a timing chart of the write operation and read operation.
In the write operation based on the timing chart of FIG. 10 (i.e., writing to the first row), the potential of the word line WL(2) at the time of writing is set to a potential of 0 V; thus, for example, in the case where data which has been written to the memory cell (2,1) or the memory cell (2,2) is data “1”, steady-state current flows between the bit line BL(1) and the bit line BL(2). This is because at the time of the writing to the first row, the first transistors in the memory cells in the second row are turned on, whereby the bit line BL(1) and the bit line BL(2) are connected at low resistance through the source line. In the write operation illustrated in FIG. 12, such steady-state current is less likely to be generated.
A potential V1 is applied to the signal line S(1) in the first row, whereby the second transistors in the first row are turned on. Further, a potential of 0 V is applied to the signal line S(2) in the second row, whereby the second transistors in the second row are turned off.
Further, a potential V2 is applied to the bit line BL(1) in the first column and the potential of 0 V is applied to the bit line BL(2) in the second column.
Thus, the potential V2 is applied to the node FG of the memory cell (1,1), and the potential of 0 V is applied to the node FG of the memory cell (1,2). Here, the potential V2 is higher than the threshold value of the first transistor. Then, the potential of the signal line S(1) in the first row is set to 0 V, whereby the second transistors in the first row are turned off to finish writing.
Note that the word line WL(1) in the first row and the word line WL(2) in the second row are at the potential of 0 V and the potential of VL, respectively, during the write operation. When the word line WL(2) in the second row is at the potential VL, the first transistors of the memory cells in which either data “0” or data “1” is held in the second row are turned off. The potential V2 is applied to the source line SL during the write operation. In the case where data “0” is written to all the memory cells, the potential of 0 V may be applied to the source line.
At the end of the write operation, before the potential of the bit line BL(1) in the first column is changed, the potential of the signal line S(1) in the first row is set to 0 V. After the write operation, the threshold value of a memory cell is Vw0 in the case where data “0” has been written and Vw1 in the case where data “1” has been written. Here, Vw0>0>Vw1 is satisfied.
In the write operation, the first transistors in the memory cells in the row to which data is not written (in this case, the second row) are off. Thus, only the row to which data is written has a problem of steady-state current between the bit line and the source line. In the case where data “0” is written to the memory cell of the row to which data is written, the first transistor in the memory cell is off; thus, a problem of steady-state current does not occur. On the other hand, in the case where data “1” is written to the memory cell of the row to which data is written, the first transistor in the memory cell is on; thus, steady-state current occurs if there is a potential difference between the source line SL and the bit line BL (in this case, the bit line BL(1)). Therefore, the potential of the source line SL is made to be equal to the potential V2 of the bit line BL(1), whereby steady-state current between the bit line and the source line can be prevented.
As described above, generation of steady-state current at the time of writing can be prevented in the write operation. In other words, power consumed at the time of the write operation can be sufficiently reduced in the write operation.
Note that the read operation is performed in a manner similar to that of the above read operation.
Since the off-state current of the transistors including an oxide semiconductor in the semiconductor device described in this embodiment is extremely small, stored data can be held for an extremely long time owing to such transistors. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely lowered, which leads to a sufficient reduction in power consumption. Moreover, stored data can be held for a long period even when power is not supplied (note that a potential is preferably fixed).
Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike a conventional nonvolatile memory, it is not necessary to inject and extract electrons into and from a floating gate, and thus a problem such as deterioration of a gate insulating layer does not arise at all. That is, the semiconductor device according to the disclosed invention does not have a limitation on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, since data is written by turning on or off the transistors, high-speed operation can be easily realized.
Since a transistor including a material other than an oxide semiconductor can operate at sufficiently high speed, when this is combined with a transistor including an oxide semiconductor, a semiconductor device can perform operation (e.g., data reading) at sufficiently high speed. Further, a transistor including a material other than an oxide semiconductor can favorably realize a variety of circuits (e.g., a logic circuit or a driver circuit) which needs to operate at high speed.
A semiconductor device having a novel feature can be realized by being provided with both the transistor including a material other than an oxide semiconductor (in a broader sense, a transistor capable of operating at sufficiently high speed) and the transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small).
In an embodiment in which side surfaces (or portions thereof) of components of a transistor are aligned with each other as in the semiconductor device described in this embodiment, a highly integrated semiconductor device can be realized. In particular, in a structure including three-dimensionally integrated transistors, a more significant effect can be obtained in combination with an increase in the degree of integration owing to this three-dimensional structure. Therefore, a highly integrated semiconductor device can be realized and the area occupied by the memory cells can be reduced. Accordingly, the storage capacity per unit area can be increased.
Note that the circuit configuration of a semiconductor device according to an embodiment of the disclosed invention is not limited to that illustrated in FIG. 9. For example, a circuit configuration may be employed in which the transistors 162 included in the memory cells 1100 are connected in series with respect to wirings instead of being connected in parallel, or in which the transistors 160 included in the memory cells 1100 are connected in series with respect to wirings instead of being connected in parallel.
The configurations, methods, and the like described in this embodiment can be combined as appropriate with any of the configurations, methods, and the like described in the other embodiments.
Embodiment 3
In this embodiment, the cases where the semiconductor device described in any of the above embodiments is applied to electronic devices will be described with reference to FIGS. 13A to 13F. The cases where the above-described semiconductor device is applied to electronic devices such as a computer, a mobile phone set (also referred to as a mobile phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproducing device, and the like), a digital camera, a digital video camera, electronic paper, a television set (also referred to as a television or a television receiver), and the like are described in this embodiment.
FIG. 13A illustrates a notebook personal computer, which includes a housing 701, a housing 702, a display portion 703, a keyboard 704, and the like. The semiconductor device described in any of the above embodiments is provided in at least one of the housings 701 and 702. Thus, a notebook personal computer with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
FIG. 13B illustrates a portable information terminal (PDA). A main body 711 is provided with a display portion 713, an external interface 715, operation buttons 714, and the like. Further, a stylus 712 for operation of the portable information terminal, or the like is provided. The semiconductor device described in any of the above embodiments is provided in the main body 711. Thus, a portable information terminal with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
FIG. 13C illustrates an electronic book 720 incorporating electronic paper, which includes two housings, a housing 721 and a housing 723. The housing 721 and the housing 723 include a display portion 725 and a display portion 727, respectively. The housing 721 is connected to the housing 723 by a hinge 737, so that the electronic book can be opened and closed using the hinge 737 as an axis. In addition, the housing 721 is provided with a power switch 731, operation keys 733, a speaker 735, and the like. At least one of the housings 721 and 723 is provided with the semiconductor device described in any of the above embodiments. Thus, an electronic book with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
FIG. 13D illustrates a mobile phone set, which includes two housings, a housing 740 and a housing 741. Moreover, the housings 740 and 741 in a state where they are developed as illustrated in FIG. 13D can be slid so that one is lapped over the other. Therefore, the size of the mobile phone set can be reduced, which makes the mobile phone set suitable for being carried around. The housing 741 includes a display panel 742, a speaker 743, a microphone 744, operation keys 745, a pointing device 746, a camera lens 747, an external connection terminal 748, and the like. The housing 740 includes a solar cell 749 for charging the cellular phone, an external memory slot 750, and the like. An antenna is incorporated in the housing 741. The semiconductor device described in any of the above embodiments is provided in at least one of the housings 740 and 741. Thus, a mobile phone set with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
FIG. 13E illustrates a digital camera, which includes a main body 761, a display portion 767, an eyepiece 763, an operation switch 764, a display portion 765, a battery 766, and the like. The semiconductor device described in any of the above embodiments is provided in the main body 761. Thus, a digital camera with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
FIG. 13F is a television set 770, which includes a housing 771, a display portion 773, a stand 775, and the like. The television set 770 can be operated with a switch included in the housing 771 or with a remote controller 780. The semiconductor device described in any of the above embodiments is mounted in the housing 771 and the remote controller 780. Thus, a television set with sufficiently low power consumption, in which the semiconductor device has a higher degree of integration, writing and reading of data can be performed at high speed, and data can be stored for a long time, can be realized.
As described above, the electronic devices described in this embodiment each include the semiconductor device according to any of the above embodiments. Therefore, electronic devices with low power consumption, in which the semiconductor device has a higher degree of integration, can be realized.
EXPLANATION OF REFERENCE


    101: substrate, 103: insulating layer, 105: layer including conductive material, 107: insulating layer, 109: resist mask, 111: gate insulating layer, 113: layer including conductive material, 115: insulating layer, 117: insulating layer, 119: insulating layer, 121: element isolation insulating layer, 123: resist mask, 124: mask, 125: gate electrode, 126: resist mask, 127: region, 128: impurity region, 129: insulating layer, 130: impurity region, 131: insulating layer, 132: channel formation region, 133: oxide semiconductor layer, 135: oxide semiconductor layer, 137: conductive layer, 139: conductive layer, 141: oxide semiconductor layer, 142: source electrode, 143: source electrode, 145: drain electrode, 147: gate insulating layer, 149: gate electrode, 151: electrode, 152: resist mask, 155: region, 157: region, 159: region, 160: transistor, 162: transistor, 164: capacitor, 701: housing, 702: housing, 703: display portion, 704: keyboard, 711: main body, 712: stylus, 713: display portion, 714: operation button, 715: external interface, 720: electronic book, 721: housing, 723: housing, 725: display portion, 727: display portion, 731: power switch, 733: operation key, 735: speaker, 737: hinge, 740: housing, 741: housing, 742: display panel, 743: speaker, 744: microphone, 745: operation key, 746: pointing device, 747: camera lens, 748: external connection terminal, 749: solar cell, 750: external memory slot, 761: main body, 763: eyepiece, 764: operation switch, 765: display portion, 766: battery, 767: display portion, 770: television set, 771: housing, 773: display portion, 775: stand, 780: remote controller, 1100: memory cell, 1111: driver circuit, 1112: driver circuit, 1113: driver circuit, and 1114: driver circuit.


This application is based on Japanese Patent Application serial no. 2010-129349 filed with Japan Patent Office on Jun. 4, 2010, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
a semiconductor layer comprising a channel formation region;
a source electrode and a drain electrode over the semiconductor layer and electrically connected to the channel formation region;
a gate electrode over the channel formation region;
a gate insulating layer between the semiconductor layer and the gate electrode; and
an electrode over the gate insulating layer, the electrode overlapping with the source electrode or the drain electrode with the gate insulating layer interposed therebetween,
wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the gate insulating layer,
wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride,
wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode, and
wherein a portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other.

2. The semiconductor device according to claim 1, wherein a portion of a side surface of the semiconductor layer and the portion of the side surface of the source electrode or the drain electrode are substantially aligned with each other.

3. The semiconductor device according to claim 1, wherein a width of the semiconductor layer and a width of the source electrode or the drain electrode are substantially aligned with each other.

4. The semiconductor device according to claim 1, wherein the channel formation region comprises an oxide semiconductor.

5. The semiconductor device according to claim 1, wherein a material of the gate insulating layer and a material of the source electrode or the drain electrode are processable by the same process.

6. The semiconductor device according to claim 1, wherein the portion of the side surface of the gate insulating layer is perpendicular to a channel length direction.

7. A semiconductor device comprising:
an impurity region provided in a semiconductor substrate; and
a first transistor and a second transistor, each of the first transistor and the second transistor comprising:
a channel formation region provided in the semiconductor substrate;
a gate insulating layer over the channel formation region;
a gate electrode over the gate insulating layer, the gate electrode overlapping with the channel formation region; and
a source region and a drain region provided in the semiconductor substrate and between which the channel formation region is sandwiched,

wherein one of the source region and the drain region is covered by the gate insulating layer while the gate insulating layer is not provided over the other of the source region and the drain region,
wherein each of the first transistor and the second transistor includes a portion of the impurity region as the other of the source region and the drain region, and
wherein a portion of a side surface of the channel formation region and a portion of a side surface of the gate insulating layer are substantially aligned with each other.

8. The semiconductor device according to claim 7, wherein the portion of the side surface of the gate insulating layer and a portion of a side surface of the gate electrode are substantially aligned with each other.

9. The semiconductor device according to claim 7, wherein a width of the channel formation region and a width of the gate insulating layer are substantially aligned with each other.

10. The semiconductor device according to claim 7, wherein a width of the channel formation region, a width of the gate insulating layer and a width of the gate electrode are substantially aligned with each other.

11. The semiconductor device according to claim 7, wherein a material of the channel formation region, a material of the gate insulating layer and a material of the gate electrode are processable by the same process.

12. A semiconductor device comprising:
a first transistor comprising:
a first channel formation region provided in a semiconductor substrate;
a first gate insulating layer over the first channel formation region;
a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region; and
a source region and a drain region provided in the semiconductor substrate and between which the first channel formation region is sandwiched; and

a second transistor comprising:
a semiconductor layer comprising a second channel formation region;
a source electrode and a drain electrode electrically connected to the second channel formation region;
a second gate electrode over the second channel formation region; and
a second gate insulating layer between the second channel formation region and the second gate electrode,

wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the second gate insulating layer,
wherein the first gate electrode is in direct contact with the source electrode or the drain electrode,
wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride,
wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode,
wherein the first channel formation region and the second channel formation region comprise different semiconductor materials as respective main components, and
wherein a portion of a side surface of the second gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other.

13. The semiconductor device according to claim 12, wherein a portion of a side surface of the semiconductor layer and the portion of the side surface of the source electrode or the drain electrode are substantially aligned with each other.

14. The semiconductor device according to claim 12, further comprising an electrode over the second gate insulating layer, the electrode overlapping with the source electrode or the drain electrode with the second gate insulating layer interposed therebetween,
wherein a portion of a side surface of the electrode and the portion of the side surface of the second gate insulating layer are substantially aligned with each other.

15. The semiconductor device according to claim 12, wherein a width of the semiconductor layer and a width of the source electrode or the drain electrode are substantially aligned with each other.

16. The semiconductor device according to claim 12, wherein the second channel formation region comprises an oxide semiconductor.

17. The semiconductor device according to claim 12, wherein a material of the first channel formation region, a material of the first gate insulating layer and a material of the first gate electrode are processable by the same process.

18. The semiconductor device according to claim 12, wherein a material of the second gate insulating layer and a material of the source electrode or the drain electrode are processable by the same process.

19. The semiconductor device according to claim 12, wherein the portion of the side surface of the second gate insulating layer is perpendicular to a channel length direction.

20. The semiconductor device according to claim 12, further comprising a plurality of first transistors and a plurality of second transistors,
wherein a source region or a drain region of one of the plurality of first transistors is electrically connected to a drain region or a source region of a first transistor adjacent to the one of the plurality of first transistors, and
wherein a source electrode or a drain electrode of one of the plurality of second transistors is electrically connected to a drain electrode or a source electrode of a second transistor adjacent to the one of the plurality of second transistors.