# Patent

## Title
Flyback switching regulator with primary side regulation

## Abstract

The disclosed switching regulator, including a controller for a switching regulator, is adaptable to supplying, or controlling the supply of, regulated current to a load that is isolated from a source of input power by a flyback transformer, and includes: (a) detecting, after transistor SWOFF, a zero crossing ZCD corresponding to a primary side switching node voltage VSW decreasing to the input voltage Vin, which occurs after a secondary current IS is substantially zero and before the next SWON; (c) establishing a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD; and (d) modulating at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window, such that a regulated load current is supplied to the load.

## Background
CROSS-REFERENCES TO RELATED APPLICATIONS
Priority is hereby claimed under U.S.C. §119(e) to U.S. Provisional Application 61/586,616, filed Jan. 13, 2012


BACKGROUND
1. Technical Field
This Specification relates generally to switching regulators (switched mode power supplies) for isolated-load applications, such as may be used as a switching regulator for an isolated LED (string) load.
2. Related Art
One application for switching regulators (switched mode power supplies/converters or SNAPS) is to provide a regulated load current for an LED string. Such LED switching regulators may be used in DC/DC converter applications, but are commonly used in off-line AC/DC applications (i.e., where the power input to the switching regulator is from an AC power line). In such off-line AC/DC applications, and some DC/DC applications, the load is required to be isolated from the AC line or other source of input power.
For off-line isolated applications, an LED switching regulator is commonly based on a flyback converter/transformer with primary side switching and control. The regulation loop includes a primary side controller that provides gate drive for the switching transistor, converting AC voltage/current from the AC power line into a regulated, substantially constant secondary side current supplied to the LED load.
Implementing a switching regulation loop requires that the primary side controller directly or indirectly receive some indication or representation of secondary side current. A direct approach is to use direct secondary side current sensing with secondary-to-primary side feedback across the isolation transformer to the primary side controller, such as by means of an opto-coupler.
To eliminate the need for an opto-coupler or other means of secondary side sensing/feedback, an alternative approach is to use information detected/sensed on the primary side as a representation of secondary side current. That is, the primary side controller receive input(s) from detecting/sensing primary side operational parameters, which are used to control transistor switching, establishing an primary side regulation loop to control primary side power conversion and provide regulated, substantially constant secondary side current through the LED load.
While this Background information is presented in the context of a switching regulator for LED applications, this Specification is not limited to such applications, but is more generally directed to switching regulators (SMPS converter/controller) applications in which an isolated load requires a regulated supply current.
BRIEF SUMMARY
This Specification discloses and claims apparatus and methods for supplying regulated current to an isolated load using a primary side regulation loop that obviates direct secondary-side current sensing and feedback. The Detailed Description and Figures set forth example embodiments that illustrate various aspects and technical features of the invention defined by the Claims.
Aspects and technical features of the claimed invention include supplying, or controlling the supply of, regulated current to a load that is isolated from a source of input power by a flyback transformer, including: (a) controlling a switching transistor to switch on at a time SWON and off at a time SWOFF, such that a primary side current IP increases from substantially zero at SWON to a primary peak current IPP at SWOFF, inducing a secondary side current IS that decreases from a peak current ISP at SWOFF to substantially zero before the next SWON, in accordance with discontinuous conduction mode operation; (b) detecting, after SWOFF, a zero crossing ZCD corresponding to the primary side switching node voltage V decreasing to the input voltage Vin, which occurs after the secondary current IS is substantially zero and before the next SWON; (c) establishing a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD; and (d) modulating at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window, such that a regulated load current is supplied to the load.
In other aspects of the claimed invention, (a) the flyback transformer is characterized by quasi-resonance such that, at a time after SWOFF, VSW decreases by quasi-resonant damping through a zero crossing ZCD to a valley voltage VSW(Valley), where ZCD occurs after a time delay DLY corresponding to a time for VSW to decrease by resonant damping from a voltage associated SWOFF to ZCD, and (b) DLY is used (i) to adjust the leading edge of the time-integral window T-I_W such that T-I_W corresponds to a duration TOFF1 between SWOFF and the time IS decreases to substantially zero, and/or (ii) to initiate SWON at a time corresponding to DLY after the occurrence of ZCD, corresponding to a duration TOFF2 between the time IS decreases to substantially zero and the time VSW decreases to VSW(Valley), thereby implementing valley switching.
Other aspects and technical features of the invention disclosed and claimed in this Specification will be apparent to those skilled in the art from the Description, Figures and Claims.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A illustrates an example embodiment of an off-line, flyback switching regulator for supplying regulated current to an isolated LED string, including primary side regulation according to aspects of the claimed invention disclosed in this Specification.
FIG. 1B illustrates an example embodiment of a primary side controller configured for primary side regulation according to aspects of the claimed invention disclosed in this Specification, such as may be used in the example embodiment of the flyback switching regulator in FIG. 1A.
FIGS. 2A and 2B illustrate, for an example embodiment of a flyback transformer operating in switched discontinuous conduction mode according to this Specification, example waveforms for (2A) switched primary and secondary side currents IP and IS, and (2B) a voltage VSW at a primary side switching node with quasi-resonant damping after the secondary current IS decreases to zero.
FIGS. 3A and 3B illustrate, for the example embodiment of a flyback transformer operating in discontinuous conduction mode according to this Specification, example waveforms for (3A) switched primary and secondary side currents IP and IS, with primary and secondary peak currents IPP and ISP, and (3B) the voltage VSW at a primary side switching node with quasi-resonant damping, including illustrating (a) transistor switching cycles TON and TOFF (TOFF1+TOFF2), and related primary and secondary side currents IP/IPP and IS/ISP, and (b) primary side switching node voltage VSW with quasi-resonant damping, resulting in (c) a zero crossing ZCD associated with VSW decreasing by quasi-resonant damping to VIN after a resonant time delay DLY in accordance with aspects of the claimed invention as disclosed in this Specification.
FIGS. 3C and 3D illustrate, in conjunction with the example waveforms in FIGS. 3A and 3B, example embodiments of the primary side regulation methodology disclosed in this Specification, as represented by example time-integral windows used in modulating primary side switching, where FIGS. 3C and 3D respectively illustrate example embodiments in which primary side regulation is based on a time-integral window respectively not adjusted and adjusted for the resonant time delay DLY associated with ZCD for the primary side VSW.
FIGS. 4A, 4B and 4C illustrate an example embodiment of the primary side regulation methodology in which primary side sensing of ZCD, and the relationship to DLY, is used for both adjusting the time-integral window based on the resonant time delay DLY associated with ZCD for the primary side VSW, and effecting valley switching by controlling the initiation of a switch on cycle SWON in relation to the resonant damping of VSW (as represented by ZCD and DLY), according to aspects of the claimed invention as disclosed in this Specification, where FIGS. 4A and 4C respectively illustrate example waveforms for primary and secondary side currents IP and IS, and primary side switching node voltage VSW with valley switching at VSW(Valley), and FIG. 4B illustrates an example waveform for a time-integral window adjusted for the resonant time delay DLY.



DETAILED DESCRIPTION
This Detailed Description, together with the Figures, discloses example embodiments, and example applications, that illustrate various aspects and technical features of the invention claimed in this Specification. However, these example embodiments and example applications, are illustrative only and should not be construed to limit the scope of the invention disclosed in this Specification which is defined by the Claims—other embodiments and applications will be apparent to those skilled in the art from the Description, Figures and Claims. Known circuits, functions and operations are not described in detail to avoid unnecessarily obscuring the principles and features of the claimed invention.
In brief overview, this Specification discloses and claims apparatus and methods for supplying, or controlling the supply of, regulated current to an isolated load using a primary side regulation loop that obviates direct secondary-side current sensing and feedback. An example application described in this Specification is an off-line AC/DC switching regulator configured to supply a regulated, substantially constant current to an isolated LED (string) load.
In an example embodiment, a circuit controls a switching regulator including a flyback transformer and a switching transistor coupled to a primary side winding at a switching node SW, which is configured to supply regulated current to a load that is isolated from a source of input power by the flyback transformer. The circuit includes: (a) controller circuitry, zero crossing detect circuitry and time-integral circuitry. The controller circuitry is configured to switch the transistor on at a time SWON and off at a time SWOFF, such that a primary current IP through the primary side winding increases from substantially zero at SWON to a primary peak current IPP at SWOFF, thereby inducing in the secondary side winding a secondary current IS that decreases from a peak current ISP at SWOFF to substantially zero before the transistor is switched on at a next SWON, in accordance with discontinuous conduction mode operation. The zero crossing detect circuitry is configured to detect, after SWOFF, a zero crossing ZCD corresponding to a voltage VSW at a primary side switching node SW decreasing in magnitude to an input voltage VIN, which occurs after the secondary current IS is substantially zero and before the transistor is switched on at the next SWON. The time-integral circuitry is configured to establish a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD. The controller circuitry operable to modulate at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window T-I_W, such that a regulated load current is supplied to the load.
In another example embodiment, the flyback transformer is characterized by quasi-resonance associated with the transformer inductance and node capacitance at the primary-side switching node SW, such that VSW decreases by quasi-resonant damping through a zero crossing ZCD to at least a first valley voltage VSW(Valley). The time-integral circuitry includes delay circuitry configured to determine, after the time SWOFF, a Lime delay DLY corresponding to a time for VSW to decrease by resonant damping from a voltage associated SWOFF to ZCD. The time delay DLY is used by at least one of: (a) the time-integral circuitry to adjust the leading edge of the time-integral window T-I_W by DLY such that T-I_W corresponds to a duration TOFF1 between SWOFF and the time IS decreases to substantially zero, and (b) the controller circuitry to initiate SWON at a time corresponding to DLY after the occurrence of ZCD, corresponding to a duration TOFF2 between the time IS decreases to substantially zero and the time VSW decreases to VSW(Valley).
FIG. 1A illustrates an example embodiment of an off-line, flyback switching regulator for supplying regulated current to an isolated LED (string) load, including primary side regulation according to aspects of the claimed invention disclosed in this Specification.
An LED light system 100 includes a switching regulator 101 that controls power conversion, supplying regulated current to an LED load 103. For off-line operation, a flyback transformer 111 isolates the LED load from the AC line. A full bridge rectifier 123 supplies rectified DC.
Switching regulator 101 includes a controller 105 providing gate drive to a switching transistor 107 (such as a power MOSFET). Flyback transformer 111 includes primary and secondary side windings 112 and 113, and an auxiliary winding 115. A diode snubber 117 is coupled across the primary winding. Switching transistor 107 is drain coupled to flyback transformer 111 at a primary side switching node SW.
Flyback transformer 111 operates in discontinuous conduction mode, where discontinuous conduction mode is used to mean that the secondary current IS in the secondary-side winding decreases to zero (IS=0) before the next switching cycle starts with SWON. The flyback transformer is quasi-resonant as a result of primary inductance and node capacitance at the switching node SW, such that during switching operation of the flyback transformer as described below, the voltage at the primary side switching node VSW rings down under quasi-resonant damping.
Switching regulator 101 and flyback transformer 111 provide power conversion by controlling switching transistor 107, and thereby the primary current IP through the flyback transformer (primary winding 112). Power from the AC line is converted through regulated operation of the flyback transformer into a regulated, substantially constant secondary-side current ILED supplied to LED string 103.
Controller 105 receives VCC from the auxiliary winding 115. Startup VCC is provided by an external startup resistor RSU, pulling up the VCC pin until the controller initiates gate drive to the switching transistor, transitioning from open (startup) to closed loop operation under the primary side regulation loop, with VCC supplied from the auxiliary winding.
Referring also to FIG. 1B, illustrating an example embodiment of the primary side controller 105, primary side regulation in accordance with the claimed invention as disclosed in this Specification is enabled by four inputs to the controller: COMP, ISNS, ZOO and DLY. Briefly:
COMP is a switching regulation input provided by an integration voltage VCOMP stored on a compensation capacitor CCOMP. The charge on CCOMP is regulated by controller 105 operating under the primary side regulation loop, and VCOMP is then used to modulate the switching cycles SWON/SWOFF of the transistor 107.
ISNS is a switching current sense input taken from a sense resistor RSENSE that senses current through the switching node SW and transistor 107. In particular, ISNS is used to capture and hold the primary peak current IPP at the time when the switching transistor switches off at SWOFF.
ZCD and DLY are inputs used by controller 105 to effect primary side regulation, including in one example embodiment, valley switching, in accordance with aspects of the claimed invention disclosed in this Specification.
ZCD is a zero crossing detect input taken from primary-side auxiliary winding 115 (through a voltage divider/clamp network 119), sensing the switching node voltage VSW (transistor drain voltage) at the primary side switching node SW to detect a primary side zero crossing ZCD associated with VSW resonating down to Vin after the secondary current IS in the secondary winding decreases to zero.
DLY is a time delay input associated with the quasi-resonant damping of the primary side switching node voltage VSW after the secondary current IS decreases to zero. For the exemplary embodiment, DLY is determined by a resistor RDLY which is selected/specified based on switch node resonance determined by primary side inductance and switching node capacitance.
FIG. 2A is an example waveform illustrating switched primary and secondary side currents IP and IS, and FIG. 2B is an example waveform for the voltage VSW at the primary side switching node SW. In these Figures (and FIGS. 3A/B/C/D and 4A/B/C):
IP Primary current through the primary-side winding
IS Secondary current through the secondary-side winding
ILED Average, regulated current through the LED load
LP Primary-side winding inductance
LS Secondary-side winding inductance
N Transformer turns ratio
VLED Output LED load voltage
VSW Voltage at the Primary-side switching node SW
In particular, FIGS. 2A and 2B illustrate the switching cycles of the switching transistor (FIG. 1A, 107) under primary side regulation according to this Specification, where
SWON Switching Transistor ON
SWOFF Switching Transistor OFF
TON Time between SWON and SWOFF 
TOFF Time between SWOFF and next SWON 
TOFF1 Time between SWOFF and IS=0
TOFF2 Time between IS=0 and next SWON 
A switching cycle is TON+TOFF, where TOFF=TOFF1+TOFF2. During TON, the primary current IP ramps up to the primary peak current IPP at SWOFF—by definition, during TOFF1 secondary current IS ramps down from secondary peak current ISP to IS=0, and in accordance with discontinuous conduction mode, TOFF2 is the time between IS=0 at the end of TOFF1 and the initiation of the next TON (i.e., the next switching cycle initiated by SWON).
The primary side regulation loop modulates the switching cycles TON/TOFF, and thereby the current through the primary side winding of the flyback transformer in order to regulate current through the secondary side winding and thereby current through the LED load. That is, regulation is in accordance with the proportionality between Ton (primary side current IP) and average LED load current ILED.




  ILED
  =
  
    
      
        N
        *
        VIN
      
      
        2
        *
        LP
        *
        
          (
          
            
              
                N
                *
                VLED
              
              VIN
            
            +
            
              
                TOFF
                ⁢
                
                  
                
                ⁢
                2
              
              
                TOFF
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            1
          
          )
        
      
    
    *
    TON
  




Typically, TOFF1>>TOFF2, so that





  ILED
  ≈
  
    
      
        N
        *
        VIN
      
      
        2
        *
        LP
        *
        
          (
          
            
              
                N
                *
                VLED
              
              VIN
            
            +
            1
          
          )
        
      
    
    *
    TON
  




Thus, ILED is directly proportional to TON, and ILED can be regulated by modulating TON.

However, closed loop modulation of TON requires information about secondary side current, because ILED is the time average of the secondary side current ramp from secondary side peak ISP to IS=0. Secondary peak current ISP is related to the primary peak current IPP by the transformer turns ratio N: ISP=IPP*N. However, under primary side regulation, IS=0 cannot be directly sensed—instead, in accordance with aspects of the claimed invention disclosed in this Specification, the primary side regulation loop uses the primary side detection of a zero crossing ZCD of VSW at the primary side switch node voltage SW to project for IS=0.
Referring to the example embodiment in FIG. 1A, in accordance with aspects of the claimed invention as disclosed in this Specification, switching regulator 101, including the controller 105, and the flyback transformer 111 establish a primary side regulation loop to control the switching cycles ION/TOFF of the transistor 107, including (a) modulating TON to regulate secondary side current IS, and thereby ILED through the LED load, and, in one example embodiment, (b) controlling TOFF and in particular TOFF2 to implement valley switching based on the resonant behavior of flyback transformer 111 at the primary side switch node SW.
FIGS. 2A and 2B illustrate the operation of flyback transformer in quasi-resonant, discontinuous conduction mode according to this Specification. At initiation of switching cycle TON, the switching transistor is switched on at SWON and primary current IP (transistor drain current) ramps up to the primary peak current IPP at the end of TON when the switching transistor is switched off at SWOFF. Under operation of the primary side regulation loop, SWOFF is controlled relative to SWON, modulating TON.
Referring also to FIG. 1A, when the switching transistor 107 is switched off, the current in primary winding 112 of the flyback transformer 111 collapses, and VSW at the switching node SW transitions rapidly (typically in microsecond range) to VIN plus reflected output voltage N*VLED (ignoring any inductive spike SWOFF). Secondary side current IS ramps down to zero in accordance with discontinuous conduction mode operation of the flyback transformer.
Because of the primary inductance and the node capacitance at the primary side switching node SW, flyback converter 111 is quasi resonant. That is, when the secondary current IS reaches zero, VSW at the primary side switching node SW does not instantaneously collapse to VIN, but rather, rings down with quasi-resonant damping. In particular, as illustrated in FIG. 2B, VSW resonates down from VIN+N*VLED through VIN, designated as a zero crossing voltage ZCD, toward a voltage valley VSW(Valley).
As noted, switch node resonance is determined by inductance of the primary winding and node capacitance, and is independent of primary side input voltage VIN and secondary side load current ILED. Thus, this switch node resonance is a design parameter of switching regulator 101 and flyback transformer 111 that can be configured and determined during design—as noted, for the example embodiment in FIGS. 1A and 1B, the switching regulator selects RDLY based on switch node resonance.
In accordance with aspects of the claimed invention as disclosed in this Specification, the zero crossing ZCD of the primary side switching node VSW is representative of the secondary side winding current IS, and in particular embodiments, ZCD is used in conjunction with the DLY adjustment to provide a time integral window corresponding in duration to TOFF1. On the primary side, ZCD is detected as a zero crossing that occurs when VSW resonates down from VIN+N*VLED (according to switch node resonance) to cross VIN after the secondary current IS ramps down to zero.
FIGS. 3A and 3B illustrate the relationship between ZCD detected on the primary side and the occurrence of IS=0 on the secondary side. FIG. 3A illustrates switched primary and secondary side currents IP and IS, with primary and secondary peak currents IPP and ISP. FIG. 3B illustrates the voltage VSW at the primary side switching node resonating down through the zero crossing ZCD, including illustrating transistor switching cycles TON and TOFF (=TOFF1+TOFF2), and in particular the relationship between TOFF2 and ZCD.
Specifically, during TOFF2 (i.e., after TOFF1 ends at IS=0), VSW resonates down through ZCD according to the primary side switch node resonance (which from above is determined by primary inductance and node capacitance at the switching node SW). TOFF2 (and therefore TOFF) ends, and the next switch cycle TON/TOFF begins with SWON at a quasi-resonant valley VSW(Valley) at the of primary side switch node, implementing valley switching. For the example embodiment, as a result of the quasi-resonant decrease of VSW, the occurrence on the primary side of ZCD is delayed after the occurrence IS=0 on the secondary side by a time delay DLY corresponding to TOFF2/2.
In accordance with aspects of the claimed invention as disclosed in this Specification, ZCD detected at the primary side switching node SW is used to define a time-integral window. This time-integral window is used to modulate the switch cycle TON, and thereby the secondary side current ILED supplied to the LED load (i.e., the average LED output current ILED). The duration of the time-integral window is determined by ZCD (adjusted in some example embodiments by DLY), and TON is modulated in accordance with the time-integral window and the relationship between primary and secondary side peak currents: ISP=IPP*N.
FIGS. 3C and 3D illustrate example embodiments of the primary side regulation methodology disclosed in this Specification, as represented by time-integral windows used in modulating primary side switching cycles TON/TOFF. FIG. 3C illustrates an embodiment in which primary side regulation modulates the switching cycle TON based on a time-integral window corresponding to SWOFF (leading edge) and ZCD (trading edge). FIG. 3C illustrates an embodiment in which primary side regulation modulates the switching cycle TON based on a time-integral window corresponding to a trailing edge ZCD but with a leading edge adjusted for the time delay DLY between the secondary side occurrence of IS=0, and the primary side detection of ZCD (basically, SWOFF+DLY).
FIGS. 4A, 4B and 4C illustrate an example embodiment of the primary side regulation methodology in which primary side sensing of ZCD and the determination of DLY associated switch node resonance is used both (a) for adjusting the leading edge of the time-integral window by DLY in relation to the primary side detection of ZCD, and (b) for effecting valley switching by controlling the initiation of the next switch on cycle TON at SWON to be the resonant time delay DLY after the primary side detection of ZCD, as VSW continues to resonate down to the valley at VSW(Valley). FIGS. 4A and 4C respectively illustrate primary and secondary side current ramps IP/IPP and ISP/IS, and primary side switching node voltage VSW with valley switching at VSW(Valley).
FIG. 4B illustrates the time-integral window in relation to FIGS. 4A and 4C. Specifically, for this example embodiment, the time-integral window is shown in relation to the period TOFF=TOFF1+TOFF2 between TON switching cycles, and in particular the time delay DLY due to resonant damping corresponding to TOFF2/2 before and after ZCD.
To improved modulation accuracy, the leading edge of the time integral window is adjusted for the time-delay DLY corresponding to the primary side switch node voltage V resonating down to VIN as detected at the primary side by ZCD. Thus, the time-integral window is set at TOFF1, corresponding to the secondary side current IS ramping down from ISP to zero (the integral of the secondary side current ramp corresponding the average load current ILED).
To effect valley switching, the next switching cycle TON is not initiated until the time delay DLY after the primary side detection of ZCD (i.e., TOFF2/2). Thus, the switching transistor does not switch on at SWON to initiate the next TON cycle until the primary side node voltage VSW decreases to a valley voltage VSW(Valley).
FIG. 1B illustrates an example embodiment of the primary side controller 105, such as may be used in the example embodiment of a switching regulator in FIG. 1A, including configuration for primary side regulation in accordance with the claimed invention as disclosed in this Specification.
The schematic in FIG. 1B for the example embodiment of controller 105 includes a number of circuits and blocks that provide functionality commonly implemented in a switching regulator controller for LED and other applications, but which functionalities are not relevant to the disclosure provided by this Specification, for example: UVLO (under voltage lock out), OVP (over voltage protection), OCP (over current protection), TSD (thermal shutdown). The following description of the circuitry and operation of controller 105 is limited to that circuitry and operation relevant to the claimed invention disclosed in this Specification.
Controller 105 includes control logic 131 that receives various control inputs and provides switching control signals to a gate driver 133 to control the switching of transistor 107.
Bias and VREF circuitry 135 receives VCC and provides voltage references VREF and VC1. After startup (as described in connection with FIG. 1A), VCC is provided by the auxiliary winding 115 of the flyback transformer (FIG. 1A, 111).
An On-Timer/Peak Current Controller 137 is responsive to VCOMP to generate modulation signals used by control logic 131 to control modulation of the TON switching cycles in accordance with the primary side regulation methodology disclosed in this Specification. TON modulation control, and the corresponding SWON/SWOFF switching control of switching transistor 107, may be provided by either modulating on-time TON, or modulating primary peak current (which indirectly controls the switch cycle TON).
Controller 105 operating under primary side regulation according to this Specification controls switching of transistor 107, and specifically the TON/TOFF switching cycles. In accordance with aspects of the claimed invention as disclosed in this Specification, primary side regulation of secondary side current is based on the primary side detection of a zero crossing ZCD corresponding to the primary side node voltage VSW resonating down to VIN after IS ramps from ISP to zero after SWOFF.
For this example embodiment, primary side regulation includes determination of a resonant time delay DLY between the secondary side occurrence of IS=0, and the primary side detection of ZCD. This resonant delay DLY is determined by the selection of RDLY based on measured primary inductance and node capacitance at the primary side switching node SW. This resonant time delay DLY is used both (a) to adjust for the leading edge of the time-integral window by DLY in relation to the primary side detection of ZCD (basically, SWOFF+DLY or TOFF/2), and (b) to effect valley switching by controlling the initiation of the next switch on cycle TON at SWON corresponding to DLY after the primary side detection of ZCD (basically, ZCD+DLY or TOFF/2).
Controller 105 includes two networks that control VCOMP and therefore modulation of the switch cycle TON: an integrator network 141 and a time-integral window network 151.
Integrator network 141 regulates the integration voltage VCOMP input at COMP and provided to the on-timer or peak current controller 137, and thereby controls modulation of the switching cycle TON. VCOMP is controlled according to the integration of IPP Hold and the time-integral window: [IPPHold*T-I_W].
Integrator network 141 includes two current sources: and IPP Hold current source 144 and IREF current source 147. IREF is an internal reference current generated from VREF provided by the bias and VREF circuitry 135. The IPP Hold current source 144 is controlled by an IPP Hold current control signal corresponding to the primary peak current IPP, captured and held each TON cycle by an IPP Peak Hold circuit 143 based on the ISNS input (the transistor current sensed by RSENSE).
Current sources 144 and 147 establish, respectively, discharge and charge paths for controlling the charge Q on CCOMP and therefore VCOMP. The integration [IPPHold*T-I_W] is accomplished a time-integral switch 149 controlled by the time-integral window T-I_W from the time integral network 151.
If discharge Q during the time-integral window (IPP Hold×T-I_W) is greater than charge Q from IREF, then VCOMP will decrease, as a result gate output SWON time will decrease at next cycle. Otherwise, if the charge Q from IREF is greater than the discharge Q during the time integral window (IPP×T-I_W), VCOMP will increase, and gate drive output ON time will increase at next cycle.
The time integral window T-I_W is generated by the time-integral window network 151 based on SWOFF and the zero crossing detect ZCD and, in this example embodiment, the time-delay DLY.
ZCD is provided by the primary-side auxiliary winding 115 (through a voltage divider/clamp network 119), sensing the VSW switching node voltage (transistor drain voltage) at the primary side switching node SW to detect a primary side zero crossing ZCD associated with VSW resonating down to VIN after the secondary current IS decreases to zero. The ZCD input is provided to a comparator 152 which generates an internal zero crossing signal ZC provided to control logic 131 and to the time integral network.
DLY is the time delay (time error) in ZCD relative to the secondary side winding current IS ramping down to zero. In the example embodiment in FIG. 1B, DLY is used to adjust the time integral window to correspond to TOFF1 (i.e., the time duration for the secondary side current ramp from IPS to zero after the switching transistor is switched off at SWOFF). As described above, for the exemplary embodiment, DLY is determined by the selection of resistor RDLY based on primary inductance and node capacitance at the primary side switching node SW. A reference voltage (such as a bandgap reference) from a V/I converter circuit 153 provides a DLY current IDLY corresponding to DLY according to V/RDLY.
IDLY is a control input to a delay circuit 155, setting the delay provided by the delay circuit, introducing the time delay adjustment to the time integral window. IDLY is also provided to control logic 131, controlling the initiation of switching cycles (SWON/TON) to effect valley switching.
To adjust the time integral window, the delay circuit receives the inverted ON signal from control logic 131, corresponding to the deassertion of the ON gate drive signal at SWOFF. This SWOFF signal, delayed by delay circuit 155 according to DLY/IDLY, is input to a logic gate 157 that also receives the inverted internal zero crossing signal ZC from comparator 152.
In response, logic gate 157 outputs a time integral widow with a leading edge corresponding to SWOFF adjusted by DLY and a trailing edge set by ZC (corresponding to TOFF1 in FIG. 4A).
For the example embodiment, control logic 131 uses the IDLY control input to effect valley switching by controlling initiation of a TON switching cycle with SWON in accordance with the quasi-resonant operation of the flyback transformer.
Thus, for this example embodiment, controller 105 establishes a primary side regulation loop for regulating power conversion by a switching regulator and flyback transformer, supplying a regulated load current (such as to a LED string/load) based on (a) the accurate determination of secondary side winding current based on primary side detection of ZCD and adjustment for quasi-resonant affects, and (b) quasi-resonant valley switching.
While this disclosure has described certain example embodiments and generally associated methods, and example applications, the principles and features of the invention may be implemented in or with any suitably arranged device or system, and various design choices are possible without departing from the scope of the invention as defined by the Claims. Accordingly, the above description of example embodiments and example applications does not define or constrain the scope of the invention, which shall be defined by the following Claims.

## Claims

1. A circuit for controlling a switching regulator including a flyback transformer with primary and secondary windings and a switching transistor coupled to the primary side winding at a switching node SW, and configured to supply regulated current to a load that is isolated from a source of input power by the flyback transformer, the circuit comprising:
controller circuitry configured to switch the transistor on at a time SWON and off at a time SWOFF, such that a primary current IP through the primary side winding increases from substantially zero at SWON to a primary peak current IPP at SWOFF, thereby inducing in the secondary side winding a secondary current IS that decreases from a peak current ISP at SWOFF to substantially zero before the transistor is switched on at a next SWON, in accordance with discontinuous conduction mode operation;
a zero crossing detect circuit configured to detect, after SWOFF, a zero crossing ZCD corresponding to a voltage VSW at the primary side switching node SW decreasing in magnitude to an input voltage VIN, which occurs after the secondary current IS is substantially zero and before the transistor is switched on at the next SWON; and
time-integral circuitry configured to establish a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD;
the controller circuitry operable to modulate at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window T-I_W, such that a regulated load current is supplied to the load.

2. The circuit of claim 1:
wherein the flyback transformer is characterized by quasi-resonance associated with the transformer inductance and node capacitance at the primary-side switching node SW, such that VSW decreases by quasi-resonant damping through the zero crossing ZCD to at least a first valley voltage VSW(Valley);
wherein the time-integral circuitry includes delay circuitry configured to determine, after the time SWOFF, a time delay DLY corresponding to the time for VSW to decrease by resonant damping from a voltage associated SWOFF to ZCD, and
wherein the time delay DLY is used by at least one of: (a) the time-integral circuitry to adjust the leading edge of the time-integral window T-I_W by DLY such that T-I_W corresponds to a duration TOFF1 between SWOFF and the time IS decreases to substantially zero, and (b) the controller circuitry to initiate SWON at a time corresponding to DLY after the occurrence of ZCD, corresponding to a duration TOFF2 between the time IS decreases to substantially zero and the time VSW decreases to VSW(Valley).

3. The circuit of claim 2, wherein the delay circuit comprises a predetermined voltage source and a predetermined resistance cooperatively configured to generated a current IDLY corresponding to DLY.

4. The circuit of claim 1, wherein the controller circuitry is operable to modulate at least one of: (a) the primary peak current by modulating the time SWOFF relative to SWON, and (b) Ton by modulating the time SWOFF relative to SWON.

5. The circuit of claim 1, wherein the load comprises at least one LED.

6. The circuit of claim 1, further comprising:
IPP hold circuitry configured to provide an IPP Hold signal corresponding to the primary peak current IPP at SWOFF;
integrator circuitry responsive to the IPP Hold signal and the time-integral window T-I_W to integrate onto a compensation capacitor a modulation voltage VCOMP according to [IPP Hold*T-I_W]
the controller circuitry being operable to modulate the time SWOFF relative to SWON based on Vcomp, such that a regulated load current is supplied to the load.

7. A method of supplying regulated current to a load that is isolated from a source of input power by a flyback transformer with primary and secondary side windings and a switching transistor coupled to the primary side winding at a primary side switching node SW, comprising:
controlling the transistor to switch on at a time SWON and off at a time SWOFF, such that a primary current IP through the primary side winding increases from substantially zero at SWON to a primary peak current IPP at SWOFF, thereby inducing in the secondary side winding a secondary current IS that decreases from a peak current ISP at SWOFF to substantially zero before the transistor is switched on at a next SWON, in accordance with discontinuous conduction mode operation;
detecting, after SWOFF, a zero crossing ZCD corresponding to a voltage VSW at the primary side switching node SW decreasing in magnitude to an input voltage VIN, which occurs after the secondary current IS is substantially zero and before the transistor is switched on at the next SWON;
establishing a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD; and
modulating at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window T-I_W, such that a regulated load current ILD is supplied to the load.

8. The method of claim 7, wherein the flyback transformer is characterized by quasi-resonance associated with the transformer inductance and node capacitance at the primary-side switching node SW, such that VSW decreases by quasi-resonant damping through a zero crossing ZCD to at least a first valley voltage VSW(Valley), further comprising
determining, after the time SWOFF, a time delay DLY corresponding to a time for VSW to decrease by resonant damping from a voltage associated SWOFF to ZCD, and
using the time delay DLY for at least one of: (a) adjusting the leading edge of the time-integral window T-I_W by DLY such that T-I_W corresponds to a duration TOFF1 between SWOFF and the time IS decreases to substantially zero, and (b) initiating SWON at a time corresponding to DLY after the occurrence of ZCD, corresponding to a duration TOFF2 between the time IS decreases to substantially zero and the time VSW decreases to VSW(Valley).

9. The method of claim 7, wherein modulating at least the time SWOFF relative to SWON is accomplished by at least one of: (a) the primary peak current by modulating the time SWOFF relative to SWON, and (b) Ton by modulating the time SWOFF relative to SWON.