# Patent

## Title
Thin-film transistor device manufacturing method, thin-film transistor device, and display device

## Abstract

A thin-film transistor device manufacturing method for forming a crystalline silicon film of stable crystallinity using a visible wavelength laser includes: a process of forming a plurality of gate electrodes above a substrate; a process of forming a silicon nitride layer on the plurality of gate electrodes; a process of forming a silicon oxide layer on the silicon nitride layer; a process of forming an amorphous silicon layer on the silicon oxide layer; a process of crystallizing the amorphous silicon layer using predetermined laser light to produce a crystalline silicon layer; and a process of forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

## Background
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation application of PCT Patent Application No. PCT/JP2011/002589 filed on May 10, 2011, designating the United States of America. The entire disclosure of the above-identified application, including the specification, drawings and claims is incorporated herein by reference in its entirety.


BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a thin-film transistor device manufacturing method, a thin-film transistor device, and a display device.
(2) Description of the Related Art
For example, a thin-film transistor (TFT) is included in a liquid crystal panel or an organic EL panel. A channel portion of the thin-film transistor is made of amorphous silicon a-Si, or polycrystalline silicon poly-Si which is a crystalline material. A crystalline silicon layer (poly-Si layer) of the channel portion of the thin-film transistor is typically produced by forming an amorphous silicon layer (a-Si layer) and then irradiating the amorphous silicon layer with laser light of an excimer laser or the like so that the amorphous silicon layer is instantly increased in temperature and crystallized.
There are two types of thin-film transistor structures, namely, a bottom-gate structure in which a gate metal is located on a substrate side as seen from x-Si (x is a or poly) of the channel portion, and a top-gate structure in which a gate metal and a source-drain metal are located on a side opposite to the substrate side as seen from x-Si of the channel portion. The bottom-gate structure is mainly used for a a-Si TFT whose channel portion is formed of an amorphous silicon layer, whereas the top-gate structure is mainly used for a poly-Si TFT whose channel portion is formed of a crystalline silicon layer. The bottom-gate structure is commonly used as a structure of thin-film transistors in a liquid crystal panel or an organic EL panel used for a large-area display device.
There is also an instance where the poly-Si TFT has the bottom-gate structure, which provides an advantage of a reduction in manufacturing cost. In the poly-Si TFT having the bottom-gate structure, the crystalline silicon layer is formed by irradiating an amorphous silicon layer with laser light to crystallize the amorphous silicon layer. In this method (laser annealing crystallization), the amorphous silicon layer is crystallized by heat generated by laser light irradiation.
Thin-film transistors in an organic EL panel are particularly required to have uniform characteristics. Applying the aforementioned laser annealing crystallization to manufacturing of the thin-film transistor of the bottom-gate structure, however, has the following drawback (problem). In the thin-film transistor of the bottom-gate structure, first a gate electrode is formed using a metal material of a higher heat conductivity than silicon or an insulation film, and then an insulation layer and an amorphous silicon layer are formed. Accordingly, when irradiating the amorphous silicon layer in the bottom-gate structure with laser light to crystallize the amorphous silicon layer by laser annealing crystallization, heat that is supposed to be used for crystallizing the amorphous silicon layer is absorbed and transmitted by the gate electrode, making it impossible to sufficiently crystallize the amorphous silicon layer. This causes decreased crystallinity or non-uniform crystallinity.
In view of such a problem, there is disclosed a method of disposing a dummy gate pattern in a nearby region of the gate electrode, i.e. a channel neighborhood, to reduce a difference in heat capacity between the amorphous silicon layer located above the gate electrode and the amorphous silicon layer located above the dummy gate pattern (for example, Patent Literature 1: Japanese Unexamined Patent Application Publication No. 10-242052). There is also disclosed a method of extending the gate electrode to a laser light scan upstream side so that, through the use of a pre-annealing effect of the extended portion of the gate electrode, the gate electrode is thermally saturated before laser light reaches the channel region of the thin-film transistor, thereby keeping the gate electrode from absorbing heat generated in the silicon thin film (for example, Patent Literature 2: Japanese Unexamined Patent Application Publication No. 2007-035964).
SUMMARY OF THE INVENTION
However, the aforementioned conventional methods have the following problems. In the methods disclosed in Patent Literatures 1 and 2, the electrode material is disposed near or in contact with the gate electrode, as a means of thermally saturating the gate electrode before laser light reaches the silicon thin film located above the gate electrode. Hence, there is a problem that it is difficult to densely arrange gate electrode patterns in the case of manufacturing a higher-resolution display device using thin-film transistors of the bottom-gate structure. Besides, the method disclosed in Patent Literature 2 has a constraint that thin-film transistors need to be arranged so that a channel direction of the thin-film transistors is constantly in parallel with a scan direction. This poses a serious problem in the case of manufacturing a higher-resolution display device, because design flexibility of circuit patterns in pixels of the display device is significantly reduced.
In the case where laser annealing crystallization is performed by scanning with a solid-state laser in a visible region, a problem different from the case where laser annealing crystallization is performed by scanning with an excimer laser arises. When performing laser annealing crystallization by scanning with the solid-state laser in the visible region, a heat diffusion length in the amorphous silicon layer becomes larger, which increases an influence of heat conduction by the gate electrode and results in insufficient crystallization. This is described below, with reference to FIG. 1. FIG. 1 is a diagram showing non-uniform crystallinity in the case where laser annealing crystallization is performed by scanning with the solid-state laser in the visible region.
As shown in the right part of FIG. 1, non-uniform crystallinity occurs on a scan upstream side (right in the drawing). The left part of FIG. 1 shows a crystallization rate of amorphous silicon above one of a plurality of gate metals shown in the right part of FIG. 1. In the left part of FIG. 1, for example, a crystallization rate of 80% indicates crystalline silicon of 30 nm to 40 nm in grain size, while a crystallization rate of 40% indicates crystalline silicon of 10 nm to 20 nm in grain size. Non-uniform crystallinity occurs in the case where crystallization is insufficient (not uniform), as shown in the left part of FIG. 1. Thus, crystallization is insufficient in the case where laser annealing crystallization is performed by scanning with the solid-state laser in the visible region. This causes problems such as degraded characteristics of manufactured thin-film transistors and non-uniform characteristics of individual transistors.
The present invention is made in view of the problems described above, and has an object of providing a thin-film transistor device manufacturing method, a thin-film transistor device, and a display device using the thin-film transistor device in which a crystalline silicon film of stable crystallinity can be formed using a laser of a wavelength in the visible region.
To achieve the stated object, a thin-film transistor device manufacturing method according to one aspect of the present invention includes: a first process of providing a substrate; a second process of forming a plurality of gate electrodes above the substrate; a third process of forming a silicon nitride layer on the plurality of gate electrodes; a fourth process of forming a silicon oxide layer on the silicon nitride layer; a fifth process of forming an amorphous silicon layer on the silicon oxide layer; a sixth process of crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, to produce a crystalline silicon layer; and a seventh process of forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, wherein a film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 1 to 6:

Y≧0.264+14.444×ΔA′  Expression 1

X≦0.729−67.777×ΔA′  Expression 2

Y≦−0.388X+0.584−21.124×ΔA′  Expression 3

Y≦0.427−28.519×ΔA′  Expression 4

X≧0.344+32.963×ΔA′  Expression 5

Y≧−0.388X+0.457+21.412×ΔA′,  Expression 6

where X is a value obtained by dividing an optical film thickness of the amorphous silicon layer by the wavelength of the laser light, the optical film thickness of the amorphous silicon layer being a result of multiplying the film thickness of the amorphous silicon layer by a refractive index of the amorphous silicon layer, Y is a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, the silicon oxide layer converted optical film thickness being a value obtained by dividing a sum of an optical film thickness of the silicon oxide layer and an optical film thickness of the silicon nitride layer by a refractive index of the silicon oxide layer, the optical film thickness of the silicon oxide layer being a result of multiplying the film thickness of the silicon oxide layer by the refractive index of the silicon oxide layer, and the optical film thickness of the silicon nitride layer being a result of multiplying the film thickness of the silicon nitride layer by a refractive index of the silicon nitride layer, and ΔA′ is a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG), where ρSi and cSi are respectively a density and a specific heat of the amorphous silicon layer, dG, ρG, and cG are respectively a film thickness, a density, and a specific heat of the gate electrode, and AG is a maximum absorptance of the gate electrode when the amorphous silicon layer located above the gate electrode and the amorphous silicon layer not located above the gate electrode have an equal light absorptance for the laser light.
According to the present invention, it is possible to realize a thin-film transistor device manufacturing method, a thin-film transistor, and a display device using the thin-film transistor in which a crystalline silicon film of stable crystallinity can be formed using a laser of a wavelength in the visible region. In detail, it is possible to realize a thin-film transistor device manufacturing method, a thin-film transistor device, and a display device using the thin-film transistor device in which a crystalline silicon layer of stable crystallinity can be formed using a laser of a wavelength in the visible region by forming a silicon thin film and a gate insulation layer with respective film thicknesses that satisfy a predetermined condition, without a need for a particular change in thin-film transistor device structure such as a gate electrode pattern shape.



BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the present invention. In the Drawings:
FIG. 1 is a diagram showing non-uniform crystallinity in the case where laser annealing crystallization is performed by scanning with a solid-state laser in the visible region;
FIG. 2 is a cross-section diagram showing a structure of a thin-film transistor included in a display device in an embodiment of the present invention;
FIG. 3 is a diagram showing an equivalent circuit of the display device in the embodiment of the present invention;
FIG. 4 is a flowchart showing a manufacturing process of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5A is a cross-section diagram for describing a manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5B is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5C is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5D is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5E is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5F is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5G is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5H is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5I is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 5J is a cross-section diagram for describing the manufacturing method of the thin-film transistor in the display device in the embodiment of the present invention;
FIG. 6 is a diagram schematically showing laser annealing in Step S14 in FIG. 4;
FIG. 7A is a diagram for describing a method of calculating an amplitude reflectance and an amplitude transmittance;
FIG. 7B is a diagram for describing the method of calculating an amplitude reflectance and an amplitude transmittance;
FIG. 8 is a diagram showing that there are appropriate film thickness ranges of a gate insulation layer and an amorphous silicon layer in the case of forming a crystalline silicon layer by laser annealing crystallization;
FIG. 9 is a diagram showing an example of a value obtained by converting a value in a horizontal axis in FIG. 8 to a film thickness of the amorphous silicon layer;
FIG. 10A is a diagram showing an example of a value obtained by converting a value in a vertical axis in FIG. 8 to film thicknesses of a silicon oxide layer and a silicon nitride layer that constitute the gate insulation layer;
FIG. 10B is a diagram showing an example of a value obtained by converting a value in the vertical axis in FIG. 8 to film thicknesses of the silicon oxide layer and the silicon nitride layer that constitute the gate insulation layer;
FIG. 10C is a diagram showing an example of a value obtained by converting a value in the vertical axis in FIG. 8 to film thicknesses of the silicon oxide layer and the silicon nitride layer that constitute the gate insulation layer;
FIG. 10D is a diagram showing an example of a value obtained by converting a value in the vertical axis in FIG. 8 to film thicknesses of the silicon oxide layer and the silicon nitride layer that constitute the gate insulation layer;
FIG. 11 is a diagram used for calculating the appropriate film thickness ranges of the gate insulation layer and the amorphous silicon layer in FIG. 8;
FIG. 12 is a diagram showing a model used for a simulation;
FIG. 13 is a diagram showing film thickness condition points in FIG. 8 which are subject to the simulation;
FIG. 14 is a diagram showing a simulation result of positional dependency of a maximum reached temperature of a surface of the amorphous silicon layer in a first region and a second region;
FIG. 15 is a diagram showing a simulation result of positional dependency of a maximum reached temperature of the surface of the amorphous silicon layer in the first region and the second region;
FIG. 16A is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer is 35 nm in film thickness;
FIG. 16B is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer is 37.5 nm in film thickness;
FIG. 16C is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer is 47.5 nm in film thickness;
FIG. 16D is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer is 50 nm in film thickness;
FIG. 17A is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the silicon oxide layer and the silicon nitride layer are respectively 110 nm and 18.0 nm in film thickness;
FIG. 17B is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the silicon oxide layer and the silicon nitride layer are respectively 105 nm and 27.1 nm in film thickness;
FIG. 17C is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the silicon oxide layer and the silicon nitride layer are respectively 100 nm and 36.1 nm in film thickness;
FIG. 17D is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the silicon oxide layer and the silicon nitride layer are respectively 95 nm and 45.1 nm in film thickness;
FIG. 17E is a diagram showing a calculation result of an absorptance of silicon in the first region and the second region in the case where the silicon oxide layer and the silicon nitride layer are respectively 90 nm and 54.1 nm in film thickness;
FIG. 18A is a diagram showing crystallinity of the crystalline silicon layer in the case where laser annealing crystallization is performed on the structure of the embodiment of the present invention using the solid-state laser in the visible region;
FIG. 18B is a diagram showing crystallinity of the crystalline silicon layer in the case where laser annealing crystallization is performed on a conventional structure using the solid-state laser in the visible region;
FIG. 19 is a diagram for describing advantageous effects of the embodiment of the present invention; and
FIG. 20 is a diagram showing an example of the display device that uses the thin-film transistor according to the present invention.



DESCRIPTION OF THE PREFERRED EMBODIMENT
A thin-film transistor device manufacturing method according to a first aspect of the present invention includes: a first process of providing a substrate; a second process of forming a plurality of gate electrodes above the substrate; a third process of forming a silicon nitride layer on the plurality of gate electrodes; a fourth process of forming a silicon oxide layer on the silicon nitride layer; a fifth process of forming an amorphous silicon layer on the silicon oxide layer; a sixth process of crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, to produce a crystalline silicon layer; and a seventh process of forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, wherein a film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 1 to 6:

Y≧0.264+14.444×ΔA′  Expression 1

X≦0.729−67.777×ΔA′  Expression 2

Y≦−0.388X+0.584−21.124×ΔA′  Expression 3

Y≦0.427−28.519×ΔA′  Expression 4

X≧0.344+32.963×ΔA′  Expression 5

Y≧−0.388X+0.457+21.412×ΔA′,  Expression 6

where X is a value obtained by dividing an optical film thickness of the amorphous silicon layer by the wavelength of the laser light, the optical film thickness of the amorphous silicon layer being a result of multiplying the film thickness of the amorphous silicon layer by a refractive index of the amorphous silicon layer, Y is a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, the silicon oxide layer converted optical film thickness being a value obtained by dividing a sum of an optical film thickness of the silicon oxide layer and an optical film thickness of the silicon nitride layer by a refractive index of the silicon oxide layer, the optical film thickness of the silicon oxide layer being a result of multiplying the film thickness of the silicon oxide layer by the refractive index of the silicon oxide layer, and the optical film thickness of the silicon nitride layer being a result of multiplying the film thickness of the silicon nitride layer by a refractive index of the silicon nitride layer, and ΔA′ is a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG), where ρSi and cSi are respectively a density and a specific heat of the amorphous silicon layer, dG, ρG, and cG are respectively a film thickness, a density, and a specific heat of the gate electrode, and AG is a maximum absorptance of the gate electrode when the amorphous silicon layer located above the gate electrode and the amorphous silicon layer not located above the gate electrode have an equal light absorptance for the laser light.
According to this aspect, the film thicknesses of the silicon nitride layer and the silicon oxide layer that serve as a gate insulation film and the film thickness of the amorphous silicon layer that serves as a channel layer satisfy the aforementioned condition, so that (1) the amorphous silicon layer not located above the gate electrode (hereafter referred to as the amorphous silicon layer in a second region) has a higher light absorptance than the amorphous silicon layer located above the gate electrode (hereafter referred to as the amorphous silicon layer in a first region), and also (2) the amorphous silicon layer located above the gate electrode has a higher heat generation temperature than a melting point of the amorphous silicon layer.
Owing to the advantageous effect (1), the amorphous silicon layer in the second region generates more heat than the amorphous silicon layer in the first region. Hence, heat generated in the amorphous silicon layer in the second region is transmitted to the gate electrode before the laser light emitted from the predetermined laser reaches a starting end of the gate electrode at which the irradiation with the laser light starts in the gate electrode, thereby thermally saturating the gate electrode.
As a result, from the starting end of the gate electrode at which the irradiation with the laser light starts to a terminating end of the gate electrode at which the irradiation with the laser light terminates in the gate electrode, a rate at which heat generated in the amorphous silicon layer in the first region is absorbed by the gate electrode can be reduced. This allows the amorphous silicon layer in the first region to have a substantially uniform heat generation temperature distribution. Thus, a substantially uniform crystal structure can be obtained in the crystalline silicon layer produced by crystallizing the amorphous silicon layer.
Moreover, owing to the advantageous effect (2), even in the case where the amorphous silicon layer in the second region has an excessively higher light absorptance than the amorphous silicon layer in the first region, that is, even in the case where the amorphous silicon layer in the second region generates excessively more heat than the amorphous silicon layer in the first region, the amorphous silicon in the first region and the second region melts to become molten silicon, as a result of which a heat conductivity of the amorphous silicon layer increases to a substantially same level as a heat conductivity of metal typically used as a gate electrode.
Accordingly, heat generated in the molten silicon layer in the second region is transmitted to the molten silicon layer in the first region, rather than being transmitted to the gate electrode via the silicon oxide layer and the silicon nitride layer. Since heat generated in the molten silicon layer in the second region is kept from being excessively transmitted to the gate electrode, there is no deterioration in heat generation temperature distribution of the gate electrode. Therefore, a decrease in uniformity of the heat generation temperature distribution of the amorphous silicon layer in the first region caused by the deterioration of the heat generation temperature distribution of the gate electrode can be prevented.
Thus, the combination of the advantageous effects (1) and (2) ensures a uniform crystal structure in the crystalline silicon layer produced by crystallizing the amorphous silicon layer. This makes it possible to realize a thin-film transistor device in which, from the crystalline silicon layer corresponding to the starting end of the gate electrode at which the irradiation with the laser light starts to the crystalline silicon layer corresponding to the terminating end of the gate electrode at which the irradiation with the laser light terminates in the gate electrode, a variation in crystallization rate in the crystalline silicon layer is suppressed.
A thin-film transistor device manufacturing method according to a second aspect of the present invention is the thin-film transistor device manufacturing method wherein in the sixth process, the predetermined laser emits the laser light in an oscillation mode that is a continuous wave mode or a quasi-continuous wave mode.
A thin-film transistor device manufacturing method according to a third aspect of the present invention is the thin-film transistor device manufacturing method wherein the predetermined laser includes a solid-state laser device.
A thin-film transistor device manufacturing method according to a fourth aspect of the present invention is the thin-film transistor device manufacturing method wherein the predetermined laser includes a laser device that uses a semiconductor laser element.
A thin-film transistor device manufacturing method according to a fifth aspect of the present invention is the thin-film transistor device manufacturing method wherein in the sixth process, a variation in irradiation energy density of the laser light on the amorphous silicon layer is less than approximately 5%.
A thin-film transistor device manufacturing method according to a sixth aspect of the present invention is the thin-film transistor device manufacturing method wherein in the third process and the fourth process, the silicon nitride layer and the silicon oxide layer are formed with the respective film thicknesses so that a capacitance of a series capacitor composed of the silicon nitride layer and the silicon oxide layer is equal to a capacitance of a silicon oxide single layer of 100 nm to 140 nm in film thickness.
A thin-film transistor device manufacturing method according to a seventh aspect of the present invention is the thin-film transistor device manufacturing method wherein the film thickness of the silicon oxide layer, the film thickness of the silicon nitride layer, and the film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 7 and 8:

0.442≦X≦0.559  Expression 7

0.310≦Y≦0.341.  Expression 8

According to this aspect, a gate breakdown voltage of the thin-film transistor device can be enhanced without excessively increasing a fixed charge in the silicon nitride layer included in the gate insulation film. This keeps a threshold voltage of the thin-film transistor device from being significantly shifted from 0 V. In addition, since the silicon nitride layer is limited to an adequate thickness, problems such as cracks, film peeling, and insufficient dehydrogenation caused by an increase in thickness of the silicon nitride layer can be suppressed. Hence, a productivity decline in thin-film transistor device manufacturing can be avoided. Moreover, according to this aspect, it is possible to realize a thin-film transistor device in which a variation in crystallization rate in the crystalline silicon layer is suppressed, even when the film thicknesses of the insulation layer (gate insulation layer) and the amorphous silicon layer in the thin-film transistor device change from their target film thicknesses by 10%.
A thin-film transistor device manufacturing method according to an eighth aspect of the present invention is the thin-film transistor device manufacturing method wherein the wavelength of the predetermined laser is 445 nm to 455 nm.
A thin-film transistor device manufacturing method according to a ninth aspect of the present invention is the thin-film transistor device manufacturing method wherein the film thickness of the amorphous silicon layer is in a range of 40 nm to 45 nm.
According to these aspects, it is possible to realize a thin-film transistor device in which a variation in crystallization rate in the crystalline silicon layer is suppressed, even when the film thicknesses of the silicon nitride layer, the silicon oxide layer, and the amorphous silicon layer in the thin-film transistor change from their target film thicknesses by 10%.
A thin-film transistor device manufacturing method according to a tenth aspect of the present invention is the thin-film transistor device manufacturing method wherein the second process includes: forming an undercoat layer made of silicon oxide, on the substrate; and forming the plurality of gate electrodes on the undercoat layer.
A thin-film transistor according to an eleventh aspect of the present invention includes: a substrate; a plurality of gate electrodes formed above the substrate; a silicon nitride layer formed on the plurality of gate electrodes; a silicon oxide layer formed on the silicon nitride layer; a crystalline silicon layer formed on the silicon oxide layer; and a source electrode and a drain electrode formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, wherein the crystalline silicon layer is produced by forming an amorphous silicon layer on the silicon oxide layer and then crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, and a film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 1 to 6:

Y≧0.264+14.444×ΔA′  Expression 1

X≦0.729−67.777×ΔA′  Expression 2

Y≦−0.388X+0.584−21.124×ΔA′  Expression 3

Y≦0.427−28.519×ΔA′  Expression 4

X≧0.344+32.963×ΔA′  Expression 5

Y≧−0.388X+0.457+21.412×ΔA′,  Expression 6

where X is a value obtained by dividing an optical film thickness of the amorphous silicon layer by the wavelength of the laser light, the optical film thickness of the amorphous silicon layer being a result of multiplying the film thickness of the amorphous silicon layer by a refractive index of the amorphous silicon layer, Y is a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, the silicon oxide layer converted optical film thickness being a value obtained by dividing a sum of an optical film thickness of the silicon oxide layer and an optical film thickness of the silicon nitride layer by a refractive index of the silicon oxide layer, the optical film thickness of the silicon oxide layer being a result of multiplying the film thickness of the silicon oxide layer by the refractive index of the silicon oxide layer, and the optical film thickness of the silicon nitride layer being a result of multiplying the film thickness of the silicon nitride layer by a refractive index of the silicon nitride layer, and ΔA′ is a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG), where ρSi and cSi are respectively a density and a specific heat of the amorphous silicon layer, dG, ρG, and cG are respectively a film thickness, a density, and a specific heat of the gate electrode, and AG is a maximum absorptance of the gate electrode when the amorphous silicon layer located above the gate electrode and the amorphous silicon layer not located above the gate electrode have an equal light absorptance for the laser light.
A display device according to a twelfth aspect of the present invention is a display device including a liquid crystal panel or an EL panel, the display device including the above-mentioned thin-film transistor, wherein the thin-film transistor drives the liquid crystal panel or the EL panel.
A display device according to a thirteenth aspect of the present invention is the display device wherein the EL panel is an organic EL panel.
A thin-film transistor device manufacturing method according to a fourteenth aspect of the present invention includes: a first process of providing a substrate; a second process of forming a plurality of gate electrodes above the substrate; a third process of forming a silicon nitride layer on the plurality of gate electrodes; a fourth process of forming a silicon oxide layer on the silicon nitride layer; a fifth process of forming an amorphous silicon layer on the silicon oxide layer; a sixth process of crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, to produce a crystalline silicon layer; and a seventh process of forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, wherein the second process, the third process, the fourth process, and the fifth process are performed so that, in the sixth process, when the amorphous silicon layer is irradiated with the laser light, a maximum reached temperature of the amorphous silicon layer in a region not located above the gate electrode is higher than a maximum reached temperature of the amorphous silicon layer in a region located above the gate electrode and also the amorphous silicon layer in the region located above the gate electrode has a substantially uniform maximum reached temperature, the region not located above the gate electrode being upstream in the direction of the relative movement of the predetermined laser.
A thin-film transistor device manufacturing method according to a fifteenth aspect of the present invention is the thin-film transistor device manufacturing method wherein in the second process, the third process, the fourth process, and the fifth process, the gate electrode, the silicon nitride layer, the silicon oxide layer, and the amorphous silicon layer are formed with respective film thicknesses so that, in the sixth process, when the amorphous silicon layer is irradiated with the laser light, the maximum reached temperature of the amorphous silicon layer in the region not located above the gate electrode is higher than the maximum reached temperature of the amorphous silicon layer in the region located above the gate electrode and also the amorphous silicon layer in the region located above the gate electrode has the substantially uniform maximum reached temperature, the region not located above the gate electrode being upstream in the direction of the relative movement of the predetermined laser.
A thin-film transistor device manufacturing method according to a sixteenth aspect of the present invention includes: a first process of providing a substrate; a second process of forming a gate electrode above the substrate; a third process of forming a silicon nitride layer on the gate electrode; a fourth process of forming a silicon oxide layer on the silicon nitride layer; a fifth process of forming a semiconductor material layer that includes a semiconductor material, on the silicon oxide layer; a sixth process of crystallizing the semiconductor material by irradiating the semiconductor material layer with predetermined laser light of 405 nm to 488 nm in wavelength, to produce a semiconductor layer; and a seventh process of forming a source electrode and a drain electrode on the semiconductor layer in a second region that does not correspond to the gate electrode, the second region being different from a first region that corresponds to the gate electrode, wherein the second process, the third process, the fourth process, and the fifth process are performed so that a heating value of the semiconductor material layer in the second region per unit volume is higher than a heating value of the semiconductor material layer in the first region per unit volume, and in the sixth process, heat generated in the semiconductor material layer in the first region by the irradiation with the predetermined laser light and transmitted to and absorbed by the gate electrode is accumulated in the gate electrode without being diffused into the semiconductor material layer in the second region, and a part having a uniform temperature distribution is formed in the semiconductor material layer in the first region generating the heat, to crystallize the semiconductor material.
A thin-film transistor device manufacturing method according to a seventeenth aspect of the present invention is the thin-film transistor device manufacturing method wherein in the second process, the third process, the fourth process, and the fifth process, the gate electrode, the silicon nitride layer, the silicon oxide layer, and the semiconductor material layer are formed with respective film thicknesses so that the heating value of the semiconductor material layer in the second region per unit volume is higher than the heating value of the semiconductor material layer in the first region per unit volume.
A thin-film transistor device manufacturing method according to an eighteenth aspect of the present invention is the thin-film transistor device manufacturing method wherein the second region of the semiconductor material layer is a region upstream and downstream of the first region of the semiconductor material layer, in a direction in which the predetermined laser light is moved relative to the substrate in the sixth process.
A thin-film transistor device manufacturing method according to a nineteenth aspect of the present invention is the thin-film transistor device manufacturing method wherein the second process, the third process, the fourth process, and the fifth process are performed so that, in the sixth process, a difference between the heating value of the semiconductor material layer in the second region per unit volume and the heating value of the semiconductor material layer in the first region per unit volume is equal to or more than a heating value of the gate electrode per unit volume.
A thin-film transistor device manufacturing method according to a twentieth aspect of the present invention is the thin-film transistor device manufacturing method wherein the second process, the third process, the fourth process, and the fifth process are performed so that, in the sixth process, the part having the uniform temperature distribution is formed in the semiconductor material layer in the first region at a ratio of 0.8 to 1.0 in size to the first region.
The following describes an embodiment of the present invention with reference to drawings.
FIG. 2 is a cross-section diagram showing a structure of a thin-film transistor included in an organic light-emitting display device in the embodiment of the present invention.
A thin-film transistor 100 shown in FIG. 2 is a thin-film transistor of the bottom-gate structure, and includes a substrate 10, an undercoat layer 11, a gate electrode 12, a gate insulation layer 13, a crystalline silicon layer 15, an amorphous silicon layer 16, a n+ silicon layer 17, and source and drain electrodes 18.
The substrate 10 is an insulation substrate made of, for example, transparent glass or quartz.
The undercoat layer 11 is formed on the substrate 10, and made of, for example, a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, or a stacked structure of a silicon nitride layer and a silicon oxide layer. It is preferable that the undercoat layer 11 is made of silicon oxide (SiOx) where 1.5<x<2.0, with a film thickness of 300 nm to 1500 nm. A more preferable film thickness range of the undercoat layer 11 is 500 nm to 1000 nm. When the undercoat layer 11 is thick, a heat load on the substrate 10 can be reduced. When the undercoat layer 11 is excessively thick, however, film peeling or cracks occur.
The gate electrode 12 is formed on the undercoat layer 11, and typically made of a metal material such as molybdenum (Mo) or a Mo alloy (e.g. MoW (molybdenum-tungsten alloy)). The gate electrode 12 is made of any metal capable of withstanding a melting point of silicon. Accordingly, the gate electrode 12 may be made of an alloy of W (tungsten), Ta (tantalum), Nb (niobium), Ni (nickel), Cr (chromium), Mo, and the like. The gate electrode 12 preferably has a film thickness of 30 nm to 300 nm, and more preferably has a film thickness of 50 nm to 100 nm. When the gate electrode 12 is thin, a transmittance of the gate electrode 12 increases, which tends to induce a decrease in reflection of laser light described later. When the gate electrode 12 is thick, on the other hand, the gate insulation layer 13 described later has a poor coverage, which tends to induce degradation in characteristics of the thin-film transistor 100. In particular, a break in the gate insulation film at a step portion at an end of the gate electrode 12 causes the gate electrode 12 and the n+ silicon layer 17 to be electrically continuous with each other.
The gate insulation layer 13 is formed so as to cover the gate electrode 12, and made of, for example, a stacked structure of a silicon oxide layer and a silicon nitride layer. The following description is based on an assumption that the gate insulation layer 13 is made of a stacked structure of a silicon oxide layer 13a and a silicon nitride layer 13b, where the silicon nitride layer 13b and the silicon oxide layer 13a are formed on the gate electrode 12 in this order.
For example, the gate insulation layer 13 is formed with a film thickness so as to have a substantially same capacitance as a capacitance of the silicon oxide layer 13a when the silicon oxide layer 13a is 100 nm to 140 nm in film thickness. That is, there is an appropriate range of the film thickness of the gate insulation layer 13 in the case of forming the crystalline silicon layer 15 by laser annealing crystallization. This appropriate range is defined by predetermined relational expressions. The predetermined relational expressions will be described in detail later.
The crystalline silicon layer 15 is formed on the gate insulation layer 13, and made of a polycrystalline silicon layer (poly-Si layer). The crystalline silicon layer 15 is produced by forming an amorphous silicon layer 14 (not shown) made of a-Si on the gate insulation layer 13 and then irradiating the amorphous silicon layer 14 with laser light to change the amorphous silicon layer 14 into polycrystalline form (including microcrystalline form).
Polycrystalline mentioned here has a broad meaning that includes not only a polycrystalline structure which is narrowly interpreted as being made up of crystals of 50 nm or more, but also a microcrystalline structure which is narrowly interpreted as being made up of crystals of 50 nm or less. The broad meaning of polycrystalline is hereafter adopted.
Note that the polycrystalline form in the present invention may include an amorphous component or a dangling bond in each grain boundary.
A laser light source used for laser irradiation is a laser of a wavelength in a visible region. The laser of the wavelength in the visible region is a laser of approximately 380 nm to 780 nm in wavelength, preferably a laser of 405 nm to 488 nm in wavelength, and more preferably a blue laser of 445 nm to 455 nm in wavelength.
This is because, in the visible wavelength region, amorphous silicon exhibits a high absorptance in a blue region. For instance, a substrate of a structure composed of glass and a-Si (45 nm) has an absorptance of 45.5% when λ=455 nm, and an absorptance of 24.1% when λ=532 nm. This means that, assuming power efficiency is equal between laser light sources used for laser irradiation, the use of the blue laser allows annealing to be performed with high energy efficiency, and thus achieves a reduction of power required for crystallization by about half. Moreover, with the blue laser especially in the wavelength region of 445 nm to 455 nm, the absorptance decreases only by approximately 10% even when the film property of amorphous silicon (a-Si) changes from non-crystalline to crystalline. That is, even when amorphous silicon (a-Si) varies in film property and so has a variation in optical constant, a high absorptance can be maintained, which contributes to stable crystallization. Note that, though currently a single blue light-emitting diode laser has a small output of the order of mW, by combining a large number of such lasers, in principle it is possible to construct a laser equal to or larger than an output attained in other wavelengths. Since an incoherent laser beam is inevitably formed in this method, there is also an advantageous effect of easing laser beam formation.
The laser of the wavelength in the visible region has an oscillation mode that is a continuous wave mode or a quasi-continuous wave mode. In the case where the laser of the wavelength in the visible region has a pulse oscillation mode other than the continuous wave mode or the quasi-continuous wave mode, the amorphous silicon layer 14 is discontinuously irradiated with laser light, making it impossible to constantly maintain the amorphous silicon layer 14 in a molten state. Here, the quasi-continuous wave mode is included because the molten state can be maintained by applying a pulse to the amorphous silicon layer 14 for reheating before the amorphous silicon layer 14 is cooled to its melting point or below. That is, the quasi-continuous wave mode is preferably used in such a manner that a pulse is applied to the amorphous silicon layer 14 for reheating before the amorphous silicon layer 14 is cooled to its melting point or below, thereby maintaining the molten state of the amorphous silicon layer 14. Moreover, the laser of the wavelength in the visible region may be a solid-state laser device, or a laser device that uses a semiconductor laser element. Any of these devices is preferable because laser light can be controlled accurately. It is also preferable that a variation in irradiation energy density of the laser of the wavelength in the visible region on the amorphous silicon layer 14 is less than approximately 5%, in order to form the crystalline silicon layer 15 of uniform crystallinity. By forming the crystalline silicon layer 15 of uniform crystallinity, original design characteristics of the thin-film transistor can be attained, and also uniform characteristics can be achieved.
The amorphous silicon layer 14 is made of amorphous silicon a-Si, and formed on the gate insulation layer 13. The amorphous silicon layer 14 preferably has a film thickness of 35 nm to 55 nm, and more preferably has a film thickness of 40 nm to 45 nm. That is, there is an appropriate range of the film thickness of the amorphous silicon layer 14 in the case of forming the crystalline silicon layer 15 by laser annealing crystallization. This appropriate range is defined by predetermined relational expressions, based on a technical idea described later. The following description is based on an assumption that the gate insulation layer 13 is made of the stacked structure of the silicon oxide layer 13a and the silicon nitride layer 13b, as noted earlier.
In detail, variables for representing the relational expressions are defined first. Let X be a value obtained by dividing an optical film thickness of the amorphous silicon layer 14 by the wavelength of the laser light, where the optical film thickness of the amorphous silicon layer 14 is a result of multiplying the film thickness of the amorphous silicon layer 14 by a refractive index of the amorphous silicon layer 14. Let Y be a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, where the silicon oxide layer converted optical film thickness is a value obtained by dividing a sum of an optical film thickness of the silicon oxide layer 13a and an optical film thickness of the silicon nitride layer 13b by a refractive index of the silicon oxide layer 13a, the optical film thickness of the silicon oxide layer 13a being a result of multiplying the film thickness of the silicon oxide layer 13a by the refractive index of the silicon oxide layer 13a, and the optical film thickness of the silicon nitride layer 13b being a result of multiplying the film thickness of the silicon nitride layer 13b by a refractive index of the silicon nitride layer 13b. 
Moreover, let ρSi and cSi be respectively a density and a specific heat of the amorphous silicon layer 14, and dc, ρG, and cG be respectively the film thickness, a density, and a specific heat of the gate electrode 12. Further, let AG be a maximum absorptance of the gate electrode 12 when the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region) and the amorphous silicon layer 14 not located above the gate electrode 12 (i.e. in the second region) have an equal light absorptance for the laser light. Let ΔA′ be a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG).
This being so, the appropriate range of the film thickness of the gate insulation layer 13 and the appropriate range of the film thickness of the amorphous silicon layer 14 are determined using X, Y, and ΔA′ defined above. In detail, it is preferable that the film thickness of the silicon oxide layer 13a, the film thickness of the silicon nitride layer 13b, and the film thickness of the amorphous silicon layer 14 satisfy X and Y that are in ranges defined by the following (Expression 1) to (Expression 6).

Y≧0.264+14.444×ΔA′  (Expression 1)

X≦0.729−67.777×ΔA′  (Expression 2)

Y≦−0.388X+0.584−21.124×ΔA′  (Expression 3)

Y≦0.427−28.519×ΔA′  (Expression 4)

X≧0.344+32.963×ΔA′  (Expression 5)

Y≧−0.388X+0.457+21.412×ΔA′,  (Expression 6)

An example of more preferable numerical ranges of X and Y defined above is given below. In detail, it is more preferable that the film thickness of the silicon oxide layer 13a, the film thickness of the silicon nitride layer 13b, and the film thickness of the amorphous silicon layer 14 satisfy X and Y that are in ranges defined by the following (Expression 7) and (Expression 8).

0.442≦X≦0.559  (Expression 7)

0.310≦Y≦0.341  (Expression 8)

The amorphous silicon layer 16 is formed on the crystalline silicon layer 15. Thus, the thin-film transistor 100 has a channel layer of a structure in which the amorphous silicon layer 16 is formed on the crystalline silicon layer 15.
The n+ silicon layer 17 is formed so as to cover the gate insulation layer 13 and side surfaces of the amorphous silicon layer 16 and the crystalline silicon layer 15.
The source and drain electrodes 18 are formed on the n+ silicon layer 17, and made of, for example, a metal material including: metal such as Mo or an Mo alloy; metal such as titanium (Ti) or aluminum (Al), or an Al alloy; metal such as copper (Cu) or a Cu alloy; or metal such as silver (Ag), chromium (Cr), tantalum (Ta), tungsten (W), or the like.
The thin-film transistor 100 has the structure described above.
FIG. 3 is a diagram showing an equivalent circuit of the display device in the embodiment of the present invention.
The organic light-emitting display device shown in FIG. 3 includes a switching transistor 1, a drive transistor 2, a data line 3, a scan line 4, a current supply line 5, a capacitor 6, and an organic EL element 7.
The switching transistor 1 is connected to the data line 3, the scan line 4, and the capacitor 6.
The drive transistor 2 corresponds to, for example, the thin-film transistor 100 shown in FIG. 2, and is connected to the current supply line 5, the capacitor 6, and the organic EL element 7.
The data line 3 is a wire through which data (a magnitude of a voltage) for determining brightness of a pixel of the organic EL element 7 is transmitted to the pixel of the organic EL element 7.
The scan line 4 is a wire through which data for determining switching (ON/OFF) of the pixel of the organic EL element 7 is transmitted to the pixel of the organic EL element 7.
The current supply line 5 is a wire for supplying a large current to the drive transistor 2.
The capacitor 6 holds a voltage value (charge) for a fixed time.
The organic light-emitting display device has the structure described above.
The following describes a manufacturing method of the aforementioned thin-film transistor 100.
FIG. 4 is a flowchart showing a manufacturing process of the thin-film transistor in the organic light-emitting display device in the embodiment of the present invention. Though a plurality of thin-film transistors 100 are manufactured at the same time, the following describes a method of manufacturing one thin-film transistor for simplicity's sake. FIGS. 5A to 5J are diagrams for describing the manufacturing method of the thin-film transistor in the organic light-emitting display device in the embodiment of the present invention. FIG. 6 is a diagram schematically showing laser annealing in Step S14 in FIG. 4.
First, the substrate 10 is provided, and the undercoat layer 11 is formed on the substrate 10 (Step S10). Next, the gate electrode 12 is formed on the undercoat layer 11 (Step S11).
In detail, the undercoat layer 11 is deposited on the substrate 10 by plasma CVD (Chemical Vapor Deposition). Following this, a metal film for the gate electrode 12 is deposited by sputtering, and photolithography and etching are performed to form the gate electrode 12 in the thin-film transistor 100 (FIG. 5A). Here, the gate electrode 12 is typically made of a metal material such as Mo or a Mo alloy (e.g. MoW (molybdenum-tungsten alloy)).
Next, the gate insulation layer 13 is formed on the gate electrode 12 (Step S12). After this, the amorphous silicon layer 14 is formed on the gate insulation layer 13 (Step S13).
In detail, by plasma CVD, the silicon nitride layer 13b is formed on the gate electrode 12 so as to cover the undercoat layer 11 and the gate electrode 12, and the silicon oxide layer 13a is formed on the silicon nitride layer 13b to thereby form the gate insulation layer 13 (FIG. 5B). The amorphous silicon layer 14 is continuously deposited on the deposited gate insulation layer 13 (FIG. 5C).
For example, the gate insulation layer 13 is formed with the film thickness so as to have a substantially same capacitance as a capacitance of the silicon oxide layer 13a of 100 nm to 140 nm in film thickness. The film thickness of the amorphous silicon layer 14 is 35 nm to 55 nm as an example, and preferably 40 nm to 45 nm. In detail, it is preferable that the film thickness of the silicon oxide layer 13a, the film thickness of the silicon nitride layer 13b, and the film thickness of the amorphous silicon layer 14 satisfy X and Y that are in the ranges defined by (Expression 1) to (Expression 6), as mentioned above. In more detail, let ASi1 be the laser light absorptance of the amorphous silicon layer 14 located above the region where the gate electrode 12 is formed (i.e. in the first region), and ASi1′ be a normalized absorptance obtained by dividing the absorptance ASi1 by the film thickness dSi of the amorphous silicon layer 14. Let ASi2 be the laser light absorptance of the amorphous silicon layer 14 located above the region where the gate electrode 12 is not formed (i.e. in the second region), and ASi2′ be a normalized absorptance obtained by dividing the absorptance ASi2 by the film thickness dSi of the amorphous silicon, layer 14. This being the case, a difference ASi1−ASi2′ is equal to or less than a value −ΔA′ defined in the following description. In other words, the gate insulation layer 13 and the amorphous silicon layer 14 having the respective film thicknesses that satisfy a relational expression of (Expression 9) are formed in Steps S12 and S13.

ASi1−ASi2′≦−ΔA′  (Expression 9)

Though detailed description will be given later, these absorptances of the amorphous silicon layer 14 are derived from optical calculation using, as parameters, the film thickness and an optical constant of the amorphous silicon layer 14, the structure, the film thickness, and an optical constant of the gate insulation layer 13, an optical constant of the metal material forming the underlying gate electrode 12, and an optical constant of the substrate 10, while taking multiple interference of the laser light into consideration.
Next, the amorphous silicon layer 14 is changed into the crystalline silicon layer 15 by laser annealing (Step S14). In detail, while moving a predetermined laser of 405 nm to 488 nm in wavelength in a given direction relative to the substrate 10, the amorphous silicon layer 14 is crystallized using laser light emitted from the predetermined laser, to produce the crystalline silicon layer 15. In more detail, first, dehydrogenation is performed on the formed amorphous silicon layer 14. After this, the amorphous silicon layer 14 is changed into polycrystalline form (including microcrystalline form) by laser annealing, as a result of which the crystalline silicon layer 15 is formed (FIG. 5D).
The laser light source used for laser irradiation in this laser annealing is the laser of the wavelength in the visible region, as mentioned above. The laser of the wavelength in the visible region is a laser of approximately 380 nm to 780 nm in wavelength, preferably a laser of 405 nm to 488 nm in wavelength, and more preferably a blue laser of 445 nm to 455 nm in wavelength. The laser of the wavelength in the visible region has an oscillation mode that is a continuous wave mode or a quasi-continuous wave mode. Moreover, the laser of the wavelength in the visible region may include a solid-state laser device, or a laser device that uses a semiconductor laser element. A variation in irradiation energy density of the laser of the wavelength in the visible region on the amorphous silicon layer 14 is less than approximately 5%.
In Step S14, i.e. in the process from FIGS. 5C to 5D, the crystalline silicon layer 15 is produced by irradiating the amorphous silicon layer 14 with linearly focused laser light, as shown in FIG. 6. There are specifically two methods for such irradiation. In one method, an irradiation position of linearly focused laser light is fixed, and a stage carrying the substrate 10 where the amorphous silicon layer 14 is formed is moved. In the other method, the stage is fixed, and the irradiation position of the laser light is moved. In both methods, the amorphous silicon layer 14 is irradiated while moving the laser light relative to the amorphous silicon layer 14. The amorphous silicon layer 14 irradiated with the laser light in this way absorbs energy of the laser light and increases in temperature so as to be crystallized, and as a result becomes the crystalline silicon layer 15.
Following this, the second amorphous silicon layer 16 is formed (Step S15), and the silicon layer in the channel region of the thin-film transistor 100 is patterned (Step S16).
In detail, the second amorphous silicon layer 16 is formed on the gate insulation layer 13 by plasma CVD (FIG. 5E). The silicon film layer (the crystalline silicon layer 15 and the amorphous silicon layer 16) is then patterned so that the channel region of the thin-film transistor 100 remains, and portions of the amorphous silicon layer 16 and the crystalline silicon layer 15 to be removed are removed by etching (FIG. 5F). This enables a desired channel layer to be formed in the thin-film transistor 100.
Next, the n+ silicon layer 17 and the source and drain electrodes 18 are deposited (Step S17).
In detail, the n+ silicon layer 17 is deposited so as to cover the gate insulation layer 13 and the side surfaces of the amorphous silicon layer 16 and the crystalline silicon layer 15, by plasma CVD (FIG. 5G). The metal for the source and drain electrodes 18 is then deposited on the n+ silicon layer 17 by sputtering (FIG. 5H). Here, the source and drain electrodes 18 are made of a metal material including: metal such as Mo or an Mo alloy; metal such as titanium (Ti) or aluminum (Al), or an Al alloy; metal such as copper (Cu) or a Cu alloy; or metal such as silver (Ag), chromium (Cr), tantalum (Ta), tungsten (W), or the like.
Next, the source and drain electrodes 18 are patterned (Step S18). After this, the n+ silicon layer 17 is etched (Step S19). In this etching, the second amorphous silicon layer 16 is partially etched (Step S20).
In detail, the source and drain electrodes 18 are formed by photolithography and etching (FIG. 5I). In addition, the n+ silicon layer 17 is etched, and also the amorphous silicon layer 16 in the channel region of the thin-film transistor 100 is partially etched (FIG. 5J). In other words, the amorphous silicon layer 16 is channel-etched so that the amorphous silicon layer 16 in the channel region of the thin-film transistor 100 partially remains.
The thin-film transistor 100 is manufactured in this way.
As described above, the thin-film transistor 100 in this embodiment is formed as a poly-Si TFT having the bottom-gate structure. When manufacturing the thin-film transistor 100, the gate insulation layer 13 and the amorphous silicon layer 14 are deposited with the respective film thicknesses that satisfy the aforementioned relational expressions. The amorphous silicon layer 14 made of a a-Si film is then crystallized by laser annealing using, for example, a blue laser, and as a result changed into the crystalline silicon layer 15 made of poly-Si. Here, the gate electrode 12 can be brought into a thermally saturated state before the laser light reaches the amorphous silicon layer 14 corresponding to the channel region of the thin-film transistor 100. This enables uniform crystallization of the crystalline silicon layer 15 corresponding to the eventually created channel region.
That is, there are the appropriate ranges of the film thicknesses of the gate insulation layer 13 and the amorphous silicon layer 14 in the case of forming the crystalline silicon layer 15 by laser annealing crystallization.
This mechanism is described below.
Typically, when the amorphous silicon layer is irradiated with laser light, there is a correlation between a reached temperature of the amorphous silicon layer by heat generation and a degree of crystallinity of the crystalline silicon layer after crystallization. A higher reached temperature of the amorphous silicon layer by heat generation leads to a higher degree of crystallinity of the crystalline silicon layer formed as a result of crystallization. In view of this, for sufficient and uniform crystallization of the amorphous silicon layer in the first region (located above the region where the gate electrode is formed) in the thin-film transistor, it is necessary to ensure a uniform distribution of the reached temperature of the amorphous silicon layer in the first region in the thin-film transistor by heat generation.
In the thin-film transistor of the bottom-gate structure, however, the gate electrode is located below the amorphous silicon layer via the gate insulation layer, where the metal forming the gate electrode has a higher heat conductivity than the gate insulation layer. Accordingly, heat of the amorphous silicon layer generated by laser light irradiation is instantly transmitted to the gate electrode via the gate insulation layer. This causes an area where heat generation is insufficient to be created in the amorphous silicon layer located above the region where the gate electrode is formed, making the reached temperature of the amorphous silicon layer not uniform. For this reason, non-uniform crystallinity (non-uniform crystallization) occurs in the crystalline silicon layer after crystallization as shown in FIG. 1.
To avoid such a phenomenon that induces non-uniform crystallinity, it is desirable to thermally saturate the gate electrode before the laser light reaches the first region in the thin-film transistor, as described later. In view of this, the thin-film transistor 100 of the aforementioned structure is manufactured in this embodiment. That is, the amorphous silicon layer 14 and the gate insulation layer 13 are formed with the respective film thicknesses so as to satisfy X and Y in the ranges defined above. This allows the amorphous silicon layer 14 located above the region where the gate electrode 12 is not formed (i.e. in the second region) to generate more heat than the amorphous silicon layer 14 located above the region where the gate electrode 12 is formed (i.e. in the first region).
In other words, the amorphous silicon layer 14 and the gate insulation layer 13 are formed with the respective film thicknesses so as to satisfy X and Y in the ranges defined above, in the structure of the thin-film transistor 100 in this embodiment. In such a structure, heat generated in the amorphous silicon layer 14 located above the region where the gate electrode 12 is not formed (i.e. in the second region) by laser light irradiation is transmitted to the gate electrode 12 to cause an increase in temperature of the gate electrode 12, before the laser light reaches the amorphous silicon layer 14 located above the region where the gate electrode 12 is formed (i.e. in the first region). Thus, the gate electrode 12 is preheated before the laser light reaches. This is because, when the amorphous silicon layer 14 in the second region is irradiated with the laser light to generate heat, the temperature is higher in the second region than in the first region where the laser light has not reached yet due to the aforementioned structure, so that heat generated in the amorphous silicon layer 14 in the second region is transmitted to the gate electrode 12 and increases the temperature of the gate electrode 12. Subsequently, when the laser light reaches the first region, the amorphous silicon layer 14 in the first region generates heat, and heat corresponding to a heating value of the amorphous silicon layer 14 in the first region is transmitted to the gate electrode 12 (laser light heating). The gate electrode 12 is heated by both this laser light heating and the preheating mentioned earlier, and as a result thermally saturated. Here, thermally saturating the gate electrode 12 means that the in-plane temperature of the gate electrode 12 is made uniform.
Thus, according to the structure of the thin-film transistor in this embodiment, the gate electrode 12 can be thermally saturated when crystallizing the amorphous silicon layer 14. This provides an advantageous effect of producing the crystalline silicon layer 15 of uniform crystallinity, because heat by laser light for crystallizing the amorphous silicon layer 14 is used to form the crystalline silicon layer 15 without being absorbed by the gate electrode 12.
The following describes a method of calculating ΔA′. As noted above, the advantageous effects of this embodiment can be achieved when the difference in normalized absorptance for the laser light between the amorphous silicon layer 14 located above the region where the gate electrode 12 is formed (i.e. in the first region) and the amorphous silicon layer 14 located above the region where the gate electrode 12 is not formed (i.e. in the second region) is equal to or less than −ΔA′.
It is assumed here that 100% of energy of the laser light absorbed by the amorphous silicon layer 14 contributes to heat generation of the amorphous silicon layer 14, with energy of the laser light per unit area being denoted as an energy density E. In the following description, the amorphous silicon layer 14 located above the region where the gate electrode 12 is formed (i.e. in the first region) is referred to as the amorphous silicon layer 14 in the first region, whereas the amorphous silicon layer 14 located above the region where the gate electrode 12 is not formed (i.e. in the second region) is referred to as the amorphous silicon layer 14 in the second region. Let ASi1 be the absorptance of the amorphous silicon layer 14 in the first region for the wavelength of the laser light, and QSi1 be the heating value (per unit area) of the amorphous silicon layer 14 as a result of absorbing the laser light. Let ASi2 be the absorptance of the amorphous silicon layer 14 in the second region for the wavelength of the laser light, and QSi2 be the heating value (per unit area) of the amorphous silicon layer 14 as a result of absorbing the laser light. Moreover, in the structure in which the gate insulation layer 13 is formed on the gate electrode 12 and the amorphous silicon layer 14 is formed on the gate insulation layer 13, let AG be the laser light absorptance of the gate electrode 12, and QG be the heating value (per unit area) of the gate electrode 12 as a result of absorbing the laser light.
Suppose, when the amorphous silicon layer 14 and the gate insulation layer 13 have predetermined film thicknesses, the absorptance of the amorphous silicon layer 14 in the first region for the wavelength of the laser light and the absorptance of the amorphous silicon layer 14 in the second region for the wavelength of the laser light are equal to each other, i.e. ASi1=ASi2. In such a case, QSi1=QSi2. In actuality, however, light passing through the amorphous silicon layer 14 is also absorbed by the gate electrode 12 and so the gate electrode 12 generates heat, too (QG>0). Hence, the amorphous silicon layer 14 in the first region has a higher heat generation temperature than the amorphous silicon layer 14 in the second region.
The above suggests that, when the heating value of the amorphous silicon layer 14 in the second region is equal to or higher than a total sum of the heating value of the amorphous silicon layer 14 in the first region and the heating value of the gate electrode 12, the heat generation temperature of the amorphous silicon layer 14 in the second region is equal to or higher than the heat generation temperature of the amorphous silicon layer 14 in the first region. This relation can be represented by (Expression 10).

QSi1+QG≦QSi2  (Expression 10)

Modifying (Expression 10) yields (Expression 11).

QSi1−QSi2≦−QG  (Expression 11)

When the film thickness, the density, and the specific heat of the amorphous silicon layer 14 are respectively denoted by dSi, ρSi, and cSi and the film thickness, the density, and the specific heat of the gate electrode 12 are respectively denoted by dG, ρG, and cG, the heating value of the amorphous silicon layer 14 in the first region, the heating value of the amorphous silicon layer 14 in the second region, and the heating value of the gate electrode 12 can be expressed as follows.

QSi1=E×ASi1/(dSi×ρSi×cSi)

QSi2=E×ASi2/(dSi×ρSi×cSi)

QG=E×AG/(dG×ρG×cG)

Substituting these expressions into (Expression 11) and rearranging (Expression 11) yields (Expression 12).

(ASi1−ASi2)/dSi≦−(AG/dG)×(ρSi×cSi)/(ρG×cG)  (Expression 12)

Here, the result of dividing the absorptance by the film thickness is defined as the normalized absorptance, so that ASi1/dSi=ASi1′ and ASi2/dSi=ASi2′. In addition, the right side of (Expression 12) is defined as −ΔA′. Since (Expression 12) can be written as ASi1′ ASi2′≦−ΔA′, (Expression 9) is derived.
(Expression 9) indicates the following. When the film thickness of the amorphous silicon layer 14 and the film thickness of the gate insulation layer 13 satisfy the condition that the difference between the normalized absorptance of the amorphous silicon layer 14 in the first region and the normalized absorptance of the amorphous silicon layer 14 in the second region is equal to or less than the value defined as −ΔA′, the heat generation temperature of the amorphous silicon layer 14 in the second region is equal to or higher than the heat generation temperature of the amorphous silicon layer 14 in the first region. By forming the amorphous silicon layer 14 and the gate insulation layer 13 with the respective film thicknesses that satisfy this condition, in the case of laser annealing (crystallizing) the amorphous silicon layer 14 using, for example, a blue laser, the influence of heat absorption and heat transmission by the gate electrode 12 on the crystallization can be reduced. Hence, the distribution of the reached temperature of the amorphous silicon layer 14 in the first region in the thin-film transistor 100 by heat generation can be made uniform.
In this way, the crystalline silicon layer 15 can be produced by sufficiently and uniformly crystallizing the amorphous silicon layer 14 in the first region in the thin-film transistor 100 without depending on the wavelength of the laser light and the material and the film thickness of the gate electrode 12, as indicated by (Expression 9).
As described above, by forming the gate insulation layer 13 and the amorphous silicon layer 14 with the respective film thicknesses so as to satisfy the aforementioned condition, the crystalline silicon layer 15 of uniform crystallinity can be produced even with various laser light wavelengths and gate electrode materials and film thicknesses. A variation in crystallinity in the crystalline silicon layer 15 formed above the gate electrode 12 can be reduced to achieve stable crystallization, without a particular change in the structure of the thin-film transistor 100 such as the pattern shape of the gate electrode 12. As a result, a variation in characteristics of the thin-film transistor 100 that uses the crystalline silicon layer 15 can be suppressed. This provides an advantageous effect of improving display quality of a display device such as a LCD or an OLED even in the case where the display device is increased in resolution.
Though an example where the amorphous silicon layer is crystallized using linearly focused laser light is described here, the present invention may also be applied to spot laser light (circular, elliptic, and so on). In this case, a laser light scan method suitable for crystallization is preferably employed.
As described above, according to the manufacturing method of the thin-film transistor 100 in this embodiment, the film thickness of the amorphous silicon layer 14 and the film thickness of the gate insulation layer 13 satisfy the aforementioned condition to ensure a uniform distribution of the reached temperature of the amorphous silicon layer 14 in the first region by heat generation, as a result of which the amorphous silicon layer 14 in the first region can be sufficiently and uniformly crystallized.
The condition to be satisfied by the film thickness of the amorphous silicon layer 14 and the film thickness of the gate insulation layer 13 is described in detail below, by way of an example.
EXAMPLE
A calculation method is described first.
FIGS. 7A and 7B are diagrams for describing a method of calculating an amplitude reflectance and an amplitude transmittance.
FIGS. 7A and 7B each show a multilayer model structure that models the structure of the thin-film transistor 100 shown in FIG. 2. A model structure shown in FIG. 7A includes a layer 401 having a complex refractive index N1, a layer 402 having a complex refractive index N2, a layer 403 having a complex refractive index N3, a layer 404 having a complex refractive index N4, and a substrate layer 405 having a complex refractive index N5. In this model structure, the layers 404, 403, 402, and 401 are formed on the substrate layer 405 in this order. A model structure shown in FIG. 7B is a model structure in which the layer 404 in FIG. 7A is omitted. A region having a complex refractive index N0 in each of FIGS. 7A and 7B is outside the model structure, on a side where the laser light enters the model structure. For instance, this region is air. In such a case, the region has a refractive index of 1 and an extinction coefficient of 0.
The substrate layer 405 is an insulation substrate made of, for example, transparent glass or quartz, has a refractive index of 1.47 as an example, and corresponds to the substrate 10 shown in FIG. 5A. The layer 404 has a refractive index of 3.103 and an extinction coefficient of 3.717 as an example, made of MoW with a film thickness of 50 nm, and corresponds to the gate electrode 12 shown in FIG. 5A. The layer 403 is made of silicon nitride (SiNx) having a refractive index of 1.947 and an extinction coefficient of 0 as an example. The layer 402 is made of silicon oxide (SiOx) having a refractive index of 1.477 and an extinction coefficient of 0 as an example. A stacked film of the layers 403 and 402 corresponds to the gate insulation layer 13 shown in FIG. 5B. The layer 401 corresponds to the amorphous silicon layer 14 having a refractive index of 5.359 and an extinction coefficient of 1.370 as an example.
Note that a layer corresponding to the undercoat layer 11 is omitted in this model structure, for the following reason. Given that the undercoat layer 11 is a transparent layer and does not absorb the laser light, the film thickness of the undercoat layer 11 does not affect the result of calculation. Accordingly, the following calculation is performed using the model structure in which the layer corresponding to the undercoat layer 11 is omitted.
As shown in FIGS. 7A and 7B, r01 denotes an amplitude reflection coefficient for light entering the layer 401 from outside, r12 denotes an amplitude reflection coefficient for light entering the layer 402 from the layer 401, r23 denotes an amplitude reflection coefficient for light entering the layer 403 from the layer 402, r34 denotes an amplitude reflection coefficient for light entering the layer 404 from the layer 403, and r35 denotes an amplitude reflection coefficient for light entering the substrate layer 405 from the layer 403. Meanwhile, t01 denotes an amplitude transmission coefficient for light entering the layer 401 from outside, t12 denotes an amplitude transmission coefficient for light entering the layer 402 from the layer 401, t23 denotes an amplitude transmission coefficient for light entering the layer 403 from the layer 402, t34 denotes an amplitude transmission coefficient for light entering the layer 404 from the layer 403, and t35 denotes an amplitude transmission coefficient for light entering the substrate layer 405 from the layer 403.
Further, r01234 (R1), r1234 (R2), and r234 (R3) each denote an amplitude reflection coefficient of all layers located above a region where the layer 404 corresponding to the gate electrode 12 is formed (i.e. in the first region). In detail, r234 (R3) denotes an amplitude reflection coefficient when the layers 404 and 403 are regarded as one layer. Likewise, r1234 (R2) denotes an amplitude reflection coefficient when the layers 404, 403, and 402 are regarded as one layer, and r01234 (R1) denotes an amplitude reflection coefficient when the layers 404, 403, 402, and 401 are regarded as one layer. Meanwhile, t01234 (T1), t1234 (T2), and t234 (T3) each denote an amplitude transmission coefficient of all layers in the first region. In detail, t234 (T3) denotes an amplitude transmission coefficient when the layers 404 and 403 are regarded as one layer. Likewise, t1234 (T2) denotes an amplitude transmission coefficient when the layers 404, 403, and 402 are regarded as one layer, and t01234 (T1) denotes an amplitude transmission coefficient when the layers 404, 403, 402, and 401 are regarded as one layer.
As shown in FIG. 7B, r01235 r1235 (R2′), and r235 (R3′) each denote an amplitude reflection coefficient of all layers located above a region where the layer 404 corresponding to the gate electrode 12 is not formed (i.e. in the second region). In detail, r235 (R3′) denotes an amplitude reflection coefficient when the substrate layer 405 and the layer 403 are regarded as one layer. Likewise, r1235 (R2′) denotes an amplitude reflection coefficient when the substrate layer 405 and the layers 403 and 402 are regarded as one layer, and r01235 (R1′) denotes an amplitude reflection coefficient when the substrate layer 405 and the layers 403, 402, and 401 are regarded as one layer. Meanwhile, t01235 t1235 and t235 (T3′) each denote an amplitude transmission coefficient of all layers in the second region. In detail, t235 (T3′) denotes an amplitude transmission coefficient when the substrate layer 405 and the layer 403 are regarded as one layer. Likewise, t1235 (T2′) denotes an amplitude transmission coefficient when the substrate layer 405 and the layers 403 and 402 are regarded as one layer, and t01235 (T1′) denotes an amplitude transmission coefficient when the substrate layer 405 and the layers 403, 402, and 401 are regarded as one layer.
The amplitude reflection coefficient and the amplitude transmission coefficient of all layers in the first region can be represented by the following (Expression 13) to (Expression 18).




  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          1
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          01234
        
        =
        
          
            
              r
              01
            
            +
            
              
                r
                1234
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      1
                    
                  
                  )
                
              
            
          
          
            1
            +
            
              
                r
                01
              
              ⁢
              
                r
                1234
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      1
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          13
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          2
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          1234
        
        =
        
          
            
              r
              12
            
            ⁢
            
              r
              234
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  2
                  ⁢
                  
                    β
                    2
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                12
              
              ⁢
              
                r
                234
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      2
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          14
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          3
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          234
        
        =
        
          
            
              r
              23
            
            +
            
              
                r
                34
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
          
          
            1
            +
            
              
                r
                23
              
              ⁢
              
                r
                34
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          15
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          4
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          01234
        
        =
        
          
            
              t
              01
            
            ⁢
            
              t
              1234
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    β
                    1
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                01
              
              ⁢
              
                r
                1234
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      β
                      1
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          16
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          5
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          1234
        
        =
        
          
            
              t
              12
            
            ⁢
            
              t
              1234
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    β
                    2
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                12
              
              ⁢
              
                r
                1234
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      2
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          17
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          6
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          234
        
        =
        
          
            
              t
              23
            
            ⁢
            
              t
              34
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    β
                    3
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                23
              
              ⁢
              
                r
                34
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          18
        
        )
      
    
  




On the other hand, the amplitude reflection coefficient and the amplitude transmission coefficient of all layers in the second region can be represented by the following (Expression 19) to (Expression 24).




  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          7
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          01235
        
        =
        
          
            
              r
              01
            
            ⁢
            
              r
              1235
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  2
                  ⁢
                  
                    β
                    1
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                01
              
              ⁢
              
                r
                1235
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      1
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          19
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          8
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          1235
        
        =
        
          
            
              r
              12
            
            +
            
              
                r
                235
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      2
                    
                  
                  )
                
              
            
          
          
            1
            +
            
              
                r
                12
              
              ⁢
              
                r
                235
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      2
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          20
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          9
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          235
        
        =
        
          
            
              r
              23
            
            +
            
              
                r
                35
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
          
          
            1
            +
            
              
                r
                23
              
              ⁢
              
                r
                35
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          21
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          10
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          01235
        
        =
        
          
            
              t
              01
            
            ⁢
            
              t
              1235
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    β
                    1
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                01
              
              ⁢
              
                r
                1235
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      1
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          22
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          11
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          1235
        
        =
        
          
            
              t
              12
            
            ⁢
            
              t
              235
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  
                    -
                    i
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    β
                    2
                  
                
                )
              
            
          
          
            1
            +
            
              
                r
                12
              
              ⁢
              
                r
                235
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      β
                      2
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          23
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          12
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          
            t
            235
          
          =
          
            
              
                t
                23
              
              ⁢
              
                t
                35
              
              ⁢
              
                exp
                ⁡
                
                  (
                  
                    
                      -
                      i
                    
                    ⁢
                    
                      
                    
                    ⁢
                    
                      β
                      3
                    
                  
                  )
                
              
            
            
              1
              +
              
                
                  r
                  23
                
                ⁢
                
                  r
                  35
                
                ⁢
                
                  exp
                  ⁡
                  
                    (
                    
                      -
                      
                        i2β
                        3
                      
                    
                    )
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        Here
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          24
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          13
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          β
          1
        
        =
        
          2
          ⁢
          π
          ⁢
          
            
          
          ⁢
          
            d
            1
          
          ⁢
          
            N
            1
          
          ⁢
          cos
          ⁢
          
            
          
          ⁢
          
            
              θ
              1
            
            /
            λ
          
        
      
    
    
      
        
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          14
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          β
          2
        
        =
        
          2
          ⁢
          π
          ⁢
          
            
          
          ⁢
          
            d
            2
          
          ⁢
          
            N
            2
          
          ⁢
          cos
          ⁢
          
            
          
          ⁢
          
            
              θ
              2
            
            /
            λ
          
        
      
    
    
      
        
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          15
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          β
          3
        
        =
        
          2
          ⁢
          π
          ⁢
          
            
          
          ⁢
          
            d
            3
          
          ⁢
          
            N
            3
          
          ⁢
          cos
          ⁢
          
            
          
          ⁢
          
            
              θ
              3
            
            /
            λ
          
        
      
    
    
      
        
      
    
  




where d is the film thickness of each layer, θ is the angle of incidence/transmission in each layer, and λ is the wavelength of the laser light.
θ can be calculated according to Snell's law in the following manner.

N0 sin θ0=N1 sin θ1=N2 sin θ2=N3 sin θ3=N4 sin θ4=N5 sin θ5  [Math. 16]

The amplitude reflection coefficients r0l, r12, r23, r34, and r35 and the amplitude transmission coefficients t01, t12, t23, t34, and t35 of the individual layers can be calculated using the following (Expression 25) to (Expression 34).




  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          17
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          01
        
        =
        
          
            
              
                N
                0
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
            -
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                0
              
            
          
          
            
              
                N
                0
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
            +
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                0
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          25
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          18
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          12
        
        =
        
          
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
            -
            
              
                N
                2
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
          
          
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
            +
            
              
                N
                2
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          26
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          19
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          23
        
        =
        
          
            
              
                N
                2
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
            -
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
          
          
            
              
                N
                2
              
              ⁢
              
                
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
            +
            
              
                N
                
                  3
                  ⁢
                  
                    
                  
                
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          27
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          20
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          34
        
        =
        
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                4
              
            
            -
            
              
                N
                4
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                4
              
            
            +
            
              
                N
                4
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          28
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          21
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          r
          35
        
        =
        
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                5
              
            
            -
            
              
                N
                5
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                5
              
            
            +
            
              
                N
                5
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          29
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          22
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          01
        
        =
        
          
            2
            ⁢
            
              N
              0
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            
              θ
              1
            
          
          
            
              
                N
                0
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
            +
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                0
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          30
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          23
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          12
        
        =
        
          
            2
            ⁢
            
              N
              1
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            
              θ
              2
            
          
          
            
              
                N
                1
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
            +
            
              
                N
                2
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                1
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          31
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          24
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          23
        
        =
        
          
            2
            ⁢
            
              N
              2
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            
              θ
              3
            
          
          
            
              
                N
                2
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
            +
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                2
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          32
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          25
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          34
        
        =
        
          
            2
            ⁢
            
              N
              3
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            
              θ
              4
            
          
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                4
              
            
            +
            
              
                N
                4
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          33
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          26
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          t
          35
        
        =
        
          
            2
            ⁢
            
              N
              3
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            
              θ
              5
            
          
          
            
              
                N
                3
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                5
              
            
            +
            
              
                N
                5
              
              ⁢
              cos
              ⁢
              
                
              
              ⁢
              
                θ
                3
              
            
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          34
        
        )
      
    
  




It is assumed here that the light is monochromatic laser light, and p-polarized.
Following this, the amplitude reflection coefficient and the amplitude transmission coefficient of all layers in the first region are calculated as follows, using the aforementioned expressions. First, r234 is calculated by substituting (Expression 27) and (Expression 28) into (Expression 15). Next, r1234 is calculated by substituting (Expression 26) and r234 into (Expression 14). Next, r01234 is calculated by substituting (Expression 25) and r1234 into (Expression 13). Next, t234 is calculated by substituting (Expression 27), (Expression 28), (Expression 32), and (Expression 33) into (Expression 18). Next, t1234 is calculated by substituting (Expression 26), (Expression 31), r234, and t234 into (Expression 17). Next, t01234 is calculated by substituting (Expression 25), (Expression 30), r1234, and t1234 into (Expression 16).
Moreover, the amplitude reflection coefficient and the amplitude transmission coefficient of all layers in the second region are calculated as follows. First, r235 is calculated by substituting (Expression 27) and (Expression 29) into (Expression 21). Next, r1235 is calculated by substituting (Expression 26) and r235 into (Expression 20). Next, r01235 is calculated by substituting (Expression 25) and r1235 into (Expression 19). Next, t235 is calculated by substituting (Expression 27), (Expression 29), (Expression 32), and (Expression 34) into (Expression 24). Next, t1235 is calculated by substituting (Expression 26), (Expression 31), r235, and t235 into (Expression 23). Next, t01235 is calculated by substituting (Expression 25), (Expression 30), r1235, and t1235 into (Expression 22).
The reflectances R1, R2, and R3 and the transmittances T1, T2, and T3 of the layers in the first region are then calculated according to (Expression 35) to (Expression 40).




  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          27
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          1
        
        =
        
          
            
            
              r
              01234
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          35
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          28
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          2
        
        =
        
          
            
            
              r
              1234
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          36
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          29
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          3
        
        =
        
          
            
            
              r
              234
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          37
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          30
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          1
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      4
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  0
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      0
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  4
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                01234
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          38
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          31
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          2
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      4
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  1
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      1
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  4
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                1234
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          39
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          32
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          3
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      4
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  4
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      2
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  4
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                234
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          40
        
        )
      
    
  




The reflectances R1′, R2′, and R3′ and the transmittances T1′, T2′, and T3′ of the layers in the second region are calculated according to (Expression 41) to (Expression 46).




  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          33
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          1
          ′
        
        =
        
          
            
            
              r
              01235
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          41
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          34
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          2
          ′
        
        =
        
          
            
            
              r
              1235
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          42
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          35
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          R
          3
          ′
        
        =
        
          
            
            
              r
              235
            
            
          
          2
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          43
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          36
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          1
          ′
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      5
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  0
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      0
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  5
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                01235
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          44
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          37
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          2
          ′
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      5
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  1
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      1
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  5
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                1235
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          45
        
        )
      
    
  
  
    
      
        [
        
          Math
          .
          
            
          
          ⁢
          38
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          T
          
            3
            ⁢
            
              
            
          
          ′
        
        =
        
          
            (
            
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      5
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  2
                
              
              
                
                  Re
                  ⁡
                  
                    (
                    
                      N
                      2
                    
                    )
                  
                
                ⁢
                cos
                ⁢
                
                  
                
                ⁢
                
                  θ
                  5
                
              
            
            )
          
          ⁢
          
            
              
              
                t
                235
              
              
            
            2
          
        
      
    
    
      
        (
        
          Expression
          ⁢
          
            
          
          ⁢
          46
        
        )
      
    
  




Lastly, the light absorptance ASi1 of the amorphous silicon layer in the first region can be calculated according to (Expression 47).

[Math. 39]

ASi1=1−(R1+T1)  (Expression 47)

Likewise, the light absorptance ASi2 of the amorphous silicon layer in the second region can be calculated according to (Expression 48)

[Math. 40]

ASi2=1−(R1′+T1′)  (Expression 48)

Thus, the value obtained by subtracting the normalized absorptance ASi2′ of the amorphous silicon layer in the second region from the normalized absorptance ASi1′ of the amorphous silicon layer in the first region can be calculated using the film thickness dSi of the amorphous silicon layer.
In the case where laser light (mainly, blue laser light) of the wavelength λ (405 nm≦λ≦488 nm) enters the model structures shown in FIGS. 7A and 7B perpendicularly, i.e. at the incidence angle θ0 in a range where θ0=0 or sin θ0=0 approximately holds, the normalized absorptance of the amorphous silicon layer in the first region and the normalized absorptance of the amorphous silicon layer in the second region for the laser light are calculated to find their difference, using the aforementioned calculation method. Note that the same calculation result is obtained even when the laser light is s-polarized.
FIG. 8 is a diagram showing that there are the appropriate film thickness ranges of the gate insulation layer 13 and the amorphous silicon layer 14 in the case of forming the crystalline silicon layer 15 by laser annealing crystallization. In detail, FIG. 8 is a contour diagram showing a result of calculating the normalized absorptance difference ASi1′−ASi2′ between the amorphous silicon layer 14 in the first region and the amorphous silicon layer 14 in the second region, in the case of changing each of the film thickness of the amorphous silicon layer 14 and the film thickness of the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b using the model structures shown in FIGS. 7A and 7B. A horizontal axis represents the value (nSi×dSi)/λ obtained by dividing the optical film thickness of the amorphous silicon layer 14 by the laser light wavelength λ, where the optical film thickness of the amorphous silicon layer 14 is a result of multiplying the refractive index nSi of the amorphous silicon layer 14 by the film thickness dSi of the amorphous silicon layer 14. A vertical axis represents the value (nSiO×dSiO+nSiN×dSiN)/nSiO/λ obtained by dividing (nSiO×dSiO+nSiN×dSiN)/nSiO by the laser light wavelength λ, where (nSiO×dSiO+nSiN×dSiN)/nSiO is an optical film thickness obtained by converting the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b by the refractive index nSiO of the silicon oxide layer 13a. Here, dSiO denotes the film thickness of the silicon oxide layer 13a, nSiN denotes the refractive index of the silicon nitride layer 13b, and dSiN denotes the film thickness of the silicon nitride layer 13b. 
In the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b in the model structures, the film thickness of the silicon oxide layer 13a and the film thickness of the silicon nitride layer 13b are changed so that the stacked film has a constant total capacitance. In detail, let εSiO and εSiN be respectively relative permittivities of the silicon oxide layer 13a and the silicon nitride layer 13b, and ε0 be a vacuum permittivity. Then the film thickness of the silicon oxide layer 13a and the film thickness of the silicon nitride layer 13b are changed so that the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b has a constant total capacitance ctotal=ε0/(dSiO/εSiO+dSiN/εSiN) per unit area.
The value in the horizontal axis in FIG. 8 can be converted to the film thickness of the amorphous silicon layer 14, through the use of the refractive index of the amorphous silicon layer 14 when λ=405 nm as an example. FIG. 9 is a diagram showing an example of a result of converting the value in the horizontal axis in FIG. 8 to the film thickness of the amorphous silicon layer 14. The film thickness of the amorphous silicon layer 14 converted from the value in the horizontal axis in FIG. 8 when λ=405 nm, when λ=445 nm, when λ=455 nm, and when λ=488 nm is shown in FIG. 9.
In addition, the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b that constitute the gate insulation layer 13 can be calculated from the value in the vertical axis in FIG. 8, through the use of the refractive index of each of the silicon oxide layer 13a and the silicon nitride layer 13b when λ=405 nm as an example. FIGS. 10A to 10D are diagrams each showing an example of a result of converting the value in the vertical axis in FIG. 8 to the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b that constitute the gate insulation layer 13. The film thickness of the silicon oxide layer 13a and the film thickness of the silicon nitride layer 13b calculated when λ=455 nm are shown in FIG. 10A. Likewise, the film thickness of the silicon oxide layer 13a and the film thickness of the silicon nitride layer 13b calculated when λ=405 nm, when λ=445 nm, and when λ=488 nm are shown respectively in FIGS. 10B, 10C, and 10D. Here, the relative permittivity of the silicon oxide layer 13a and the relative permittivity of the silicon nitride layer 13b are calculated at 4.1 and 7.9, respectively. C in the drawings denotes the total capacitance ctotal of the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b, indicating that the total capacitance is fixed at a capacitance C of a film thickness in the case where the gate insulation layer 13 is made of a silicon oxide single layer. For example, C=140 nm indicates that the total capacitance is a capacitance in the case where the gate insulation layer 13 is made of a silicon oxide single layer of 140 nm. Likewise, C=120 nm and C=100 nm respectively indicate that the total capacitance is a capacitance in the case where the gate insulation layer 13 is made of a silicon oxide single layer of 120 nm and 100 nm.
In FIG. 8, an area on and inside a contour represented by −ΔA′ is an area where the normalized absorptance difference ASi1′−ASi2′ between the amorphous silicon layer 14 in the first region and the amorphous silicon layer 14 in the second region is equal to or less than −ΔA′. In other words, a dotted curve in FIG. 8 represents a contour where the normalized absorptance difference is −0.0003. That is, the normalized absorptance difference in the area on and inside the curve is equal to or less than −0.0003. This area is calculated from the film thicknesses of the amorphous silicon layer 14 and the gate insulation layer 13, the optical constants of the amorphous silicon layer 14 and the gate insulation layer 13, and the optical constants of the gate electrode 12 and the substrate 10, according to the aforementioned expressions (calculation method). When the calculated normalized absorptance difference ASi1′−ASi2′ between the amorphous silicon layer 14 in the first region and the amorphous silicon layer 14 in the second region is equal to or less than −ΔA′, a uniform distribution of the reached temperature of the amorphous silicon layer 14 in the first region in the thin-film transistor 100 by heat generation can be attained. As a result, the amorphous silicon layer 14 in the first region is sufficiently and uniformly crystallized to become the crystalline silicon layer 15.
FIG. 11 is a diagram used for calculating the appropriate film thickness ranges of the gate insulation layer 13 and the amorphous silicon layer 14 in FIG. 8.
In FIG. 11, X denotes the value obtained by dividing the optical film thickness of the amorphous silicon layer 14 by the wavelength of the laser light, and Y denotes the value obtained by dividing, by the wavelength of the laser light, the optical film thickness which is the result of converting the stacked film of the silicon oxide layer 13a and the silicon nitride layer 13b by the refractive index of the silicon oxide layer 13a. These X and Y are the same as those defined earlier. The area on and inside the contour represented by −ΔA′ is approximated by an expression, using X and Y. That is, the area can be represented by a product of sets denoted by L1 to L6.

L1∩L2∩L3∩L4∩L5∩L6  [Math. 41]

L1 to L6 can be written as follows, which respectively correspond to (Expression 1) to (Expression 6) mentioned above.

L1: Y≧0.264+14.444×ΔA′

L2: X≦5 0.729−67.777×ΔA′

L3: Y≦−0.388X+0.584−21.124×ΔA′

L4: Y≦0.427−28.519×ΔA′

L5: X≧0.344+32.963×ΔA′

L6: Y≧−0.388X+0.457+21.412×ΔA′

Note that ΔA′ is defined as ΔA′=(AG/dG)×(ρSi×cSi)/(ρG×cG) as mentioned above, where ρSi and cSi are respectively the density and the specific heat of the amorphous silicon layer 14, and dG, ρG, and cc are respectively the film thickness, the density, and the specific heat of the gate electrode 12.
Next, consider the case of applying blue laser light of 455 nm in wavelength perpendicularly from above the model structures shown in FIGS. 7A and 7B. Suppose the amorphous silicon layer 14 has a density of 2340 (kg/m3) and a specific heat of 1252 (J/(kg·K)), and the gate electrode 12 is MoW with a film thickness of 50 nm, a density of 11720 (kg/m3), and a specific heat of 226.4 (J/(kg·K)). In this case, it is assumed that the absorptance of the amorphous silicon layer 14 in the first region for the wavelength of the laser light and the absorptance of the amorphous silicon layer 14 in the second region for the wavelength of the laser light are equal to each other, that is, ASi1=ASi2. The maximum absorptance AG of the gate electrode 12 is calculated using the film thickness of the amorphous silicon layer 14 and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b that constitute the gate insulation layer 13 when ASi1=ASi2 and the aforementioned optical expressions (Expression 13) to (Expression 48). As a result, AG=0.014. From this, ΔA′ is calculated at 0.0003. Note that AG is obtained from a relational expression AG=T1×T2×T3×(1−RG). RG is a reflectance of the gate electrode 12 in the case where silicon nitride is used as a medium, where RG={(nSiN−nG)2+kG2}/{(nSiN+nG)2+kG2}. Here, nSiN, is the refractive index of silicon nitride, nG is the refractive index of the gate electrode 12, and kG is the extinction coefficient of the gate electrode 12. Thus, ΔA′ is calculated at 0.0003. This value is used to determine the range defined by the product of sets denoted by aforementioned L1 to L6 expressed as follows.

L1∩L2∩L3∩L4∩L5∩L6  [Math. 42]

A simulation is performed on positional dependency of the maximum reached temperature of the surface of the amorphous silicon layer 14 when the models shown in FIGS. 7A and 7B are perpendicularly irradiated and scanned with blue laser light of λ=455 nm. FIG. 12 shows a model used for the simulation. As shown in FIG. 12, the model includes a substrate 510, a gate electrode 512, a silicon nitride layer 513b, a silicon oxide layer 513a, and an amorphous silicon layer 514. In the model, the gate electrode 512 has a length of 30 μm in a laser scan direction, and the amorphous silicon layer 514 and the gate electrode 512 have physical properties corresponding to the aforementioned values.
FIG. 13 is a diagram showing film thickness condition points in FIG. 8 which are subject to the simulation. In detail, points 1 to 12 (stars 1 to 12) marked with a star sign (⋆) in FIG. 13 represent film thickness conditions which are subject to the simulation. The normalized absorptance difference ASi1′−ASi2′ at the stars 1, 7, 8, and 12 is more than −ΔA′ (=−0.0003), whereas the normalized absorptance difference ASi1′−ASi2′ at the stars 2, 3, 4, 5, 6, 9, 10, and 11 is less than −ΔA′. That is, the stars 2, 3, 4, 5, 6, 9, 10, and 11 are located in the area on and inside the dotted line in FIG. 13.
For instance, at the star 1, the film thickness of the amorphous silicon layer 14 is 30 nm, and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 100 nm/36.1 nm. This is an example corresponding to the case where λ=455 nm and the capacitance of the stacked film of the silicon oxide film and the silicon nitride film is equal to a capacitance of a silicon oxide single film of 120 nm in film thickness. Likewise, at the stars 2 to 7, the film thickness of the amorphous silicon layer 14 is respectively 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, and 60 nm, and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 100 nm/36.1 nm. At the stars 8 to 12, the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are respectively 115.0 nm/9.0 nm, 110.0 nm/18.0 nm, 90.0 nm/54.1 nm, 80.0 nm/72.2 nm, and 70.0 nm/90.2 nm, and the film thickness of the amorphous silicon layer 14 is 40 nm.
FIGS. 14 and 15 are diagrams showing results of simulating the positional dependency of the maximum reached temperature of the surface of the amorphous silicon layer 14 in the first region and the second region. A horizontal axis represents a position coordinate, whereas a vertical axis represents a maximum reached temperature of the surface of the amorphous silicon layer 14. FIG. 14 shows a simulation result for the film thickness conditions at the stars 1 to 7 shown in FIG. 13. In detail, FIG. 14 shows a simulation result when the film thickness of the amorphous silicon layer 14 is changed while fixing the film thickness of the gate insulation layer 13, at the stars 1 to 7 shown in FIG. 13. FIG. 15 shows a simulation result for the film thickness conditions at the stars 8, 9, 3, 10, 11, and 12 shown in FIG. 13. In detail, FIG. 15 shows a simulation result when the film thicknesses of the silicon oxide layer 13a and of the silicon nitride layer 13b that constitute the gate insulation layer 13 are changed while fixing the film thickness of the amorphous silicon layer 14, at the stars 8, 9, 3, 10, 11, and 12 shown in FIG. 13.
As shown in FIG. 14, in each of the film thickness conditions at the stars 1 and 7, a curve indicating the maximum reached temperature of the surface of the amorphous silicon layer 14 is not flat in the first region located above the gate electrode 12. In each of the film thickness conditions at the stars 2 to 6, on the other hand, a curve indicating the maximum reached temperature of the surface of the amorphous silicon layer 14 is flat in the first region located above the gate electrode 12. As shown in FIG. 15, in each of the film thickness conditions at the stars 8 and 12, a curve indicating the maximum reached temperature of the surface of the amorphous silicon layer 14 is not flat in the first region located above the gate electrode 12. In each of the film thickness conditions at the stars 9, 3, 10, and 11, on the other hand, a curve indicating the maximum reached temperature of the surface of the amorphous silicon layer 14 is flat in the first region located above the gate electrode 12.
These simulation results demonstrate that, when the film thickness of the amorphous silicon layer 14 and the film thickness of the gate insulation layer 13 satisfy such a normalized absorptance difference ASi1′−ASi2′ between the amorphous silicon layer 14 in the first region and the amorphous silicon layer 14 in the second region that is in the area on and inside the contour represented by −ΔA′, a uniform distribution of the reached temperature of the amorphous silicon layer 14 in the first region in the thin-film transistor 100 by heat generation can be attained. As a result, the amorphous silicon layer 14 in the first region in the thin-film transistor 100 can be sufficiently and uniformly crystallized to produce the crystalline silicon layer 15.
Note that FIG. 11 also shows, as a more preferable area, an area F in the area on and inside the contour represented by −ΔA′ (i.e. in the area enclosed with the dotted line).
The area F shown in FIG. 11 is a more preferable area in the area enclosed with the dotted line. This is because, by forming the silicon nitride layer 13b, the silicon oxide layer 13a, and the amorphous silicon layer 14 in the thin-film transistor 100 with the respective film thicknesses in a range that satisfies a conditional expression defined by the area F, it is possible to achieve an advantageous effect of producing the crystalline silicon layer 15 in which a variation in crystallinity is suppressed, even when the film thicknesses change from the target film thicknesses by approximately 10%. Thus, the range that satisfies the conditional expression defined by the area F is preferable because a process margin is allowed.
The following describes a result of verifying that the range that satisfies the conditional expression defined by the area F has the process margin.
FIGS. 16A to 16D show results of calculating the absorptance of silicon in the first region and the second region, when the film thickness of the amorphous silicon layer 14 is changed while maintaining the constant total capacitance and fixing the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b. 
FIG. 16A is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer 14 is 35 nm in film thickness. That is, FIG. 16A is a diagram for verifying the process margin in the case where the film thickness of the amorphous silicon layer 14 is 35 nm while maintaining C=120 nm and fixing the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b at 100 nm/36.1 nm. In FIG. 16A, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 35 nm/100 nm/36.1 nm are set as center film thicknesses, and the absorption of silicon in the first region and the second region in the case of changing the film thicknesses of the silicon oxide layer 13a, the silicon nitride layer 13b, and the amorphous silicon layer 14 from the center film thicknesses by ±10% (using film thickness levels of 3×3×3=27 as samples) is calculated. In FIG. 16A, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b are shown as a-Si/SiO/SiN.
Likewise, FIG. 16B is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer 14 is 37.5 nm in film thickness. FIG. 16C is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer 14 is 47.5 nm in film thickness. FIG. 16D is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the amorphous silicon layer 14 is 50 nm in film thickness.
That is, FIG. 16B is a diagram for verifying the process margin in the case where the film thickness of the amorphous silicon layer 14 is 37.5 nm while maintaining C=120 nm and fixing the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b at 100 nm/36.1 nm. In FIG. 16B, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 37.5 nm/100 nm/36.1 nm are set as center film thicknesses, and the absorption of silicon in the first region and the second region in the case of changing the film thicknesses of the silicon oxide layer 13a, the silicon nitride layer 13b, and the amorphous silicon layer 14 by ±10% is calculated.
Likewise, in FIG. 16C, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 47.5 nm/100 nm/36.1 nm are set as center film thicknesses. In FIG. 16D, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 50 nm/100 nm/36.1 nm are set as center film thicknesses.
FIGS. 17A to 17E show results of calculating the absorptance of silicon in the first region and the second region when the film thickness of the gate insulation layer 13 made of the silicon oxide film and the silicon nitride film is changed while fixing the film thickness of the amorphous silicon layer 14 at 42.5 nm.
FIG. 17A is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the total capacitance of the gate insulation layer 13 is constant (C=120 nm). That is, FIG. 17A is a diagram for verifying the process margin in the case where the total capacitance of the gate insulation layer 13 is C=120 nm and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 110 nm/18.0 nm while fixing the film thickness of the amorphous silicon layer 14 at 42.5 nm. In FIG. 17A, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 42.5 nm/110 nm/18.0 nm are set as center film thicknesses, and the absorption of silicon in the first region and the second region in the case of changing the film thicknesses of the silicon oxide layer 13a, the silicon nitride layer 13b, and the amorphous silicon layer 14 from the center film thicknesses by ±10% is calculated.
Likewise, FIG. 17B is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the total capacitance of the gate insulation layer 13 is C=120 nm and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 105 nm/27.1 nm. FIG. 17C is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the total capacitance of the gate insulation layer 13 is C=120 nm and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 100 nm/36.1 nm. FIG. 17D is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the total capacitance of the gate insulation layer 13 is C=120 nm and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 95 nm/45.1 nm. FIG. 17E is a diagram showing a result of calculating the absorptance of silicon in the first region and the second region in the case where the total capacitance of the gate insulation layer 13 is C=120 nm and the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are 90 nm/54.1 nm.
In FIG. 17B, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 42.5 nm/105 nm/27.1 nm are set as center film thicknesses. In FIG. 17C, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 42.5 nm/100 nm/36.1 nm are set as center film thicknesses. In FIG. 17D, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 42.5 nm/95 nm/45.1 nm are set as center film thicknesses. In FIG. 17E, the film thicknesses of the amorphous silicon layer 14, the silicon oxide layer 13a, and the silicon nitride layer 13b of 42.5 nm/90 nm/54.1 nm are set as center film thicknesses.
Whether or not the process margin is allowed can be verified by checking whether or not there are many film thickness levels at which the absorptance of silicon is higher in the second region (not located above the gate electrode) than in the first region (located above the gate electrode) in FIGS. 16A to 17E.
In FIGS. 16A, 16D, 17A, and 17E, the absorptance of silicon is higher in the first region (located above the gate electrode) than in the second region (not located above the gate electrode), at film thickness levels (three film thickness levels) in areas enclosed with circles. In FIGS. 17C and 17D, on the other hand, the absorptance of silicon is higher in the second region (not located above the gate electrode) than in the first region (located above the gate electrode), at all film thickness levels. In FIGS. 16B, 16C, and 17B, the absorptance of silicon is higher in the second region (not located above the gate electrode) than in the first region (located above the gate electrode), at almost all film thickness levels. In detail, the absorptance of silicon is higher in the first region (located above the gate electrode) than in the second region (not located above the gate electrode), only at one film thickness level (film thickness level in an area enclosed with a circle) far from the center film thicknesses (i.e. having a large amount of change from the center film thicknesses).
These results demonstrate that the range that satisfies the conditional expression defined by the area F, in which the film thicknesses of the silicon oxide layer 13a and the silicon nitride layer 13b are in a range from 105 nm/27.1 nm to 95 nm/45.1 nm and the film thickness of the amorphous silicon layer 14 is in a range from 37.5 nm to 47.5 nm, has the process margin. That is, in the range of the preferable area F, the crystalline silicon layer 15 in which a variation in crystallinity is suppressed can be produced even when the film thicknesses of the silicon oxide layer 13a, the silicon nitride layer 13b, and the amorphous silicon layer 14 change from their target film thicknesses by approximately 10%.
This is summarized as follows. Typically, in the case where the gate electrode is located below the amorphous silicon layer via the gate insulation layer in the laser crystallization process, insufficient and non-uniform heat generation of the amorphous silicon layer located above the gate electrode is caused by heat absorption and heat transmission by the gate electrode. This leads to a variation in crystallinity in the resulting crystalline silicon layer. By depositing the amorphous silicon layer and its underlying insulation layer in the aforementioned film thickness ranges, however, crystallization can be performed while suppressing the influence of heat absorption and heat transmission by the gate electrode in the laser crystallization process, as shown in FIG. 18A. Hence, the thin-film transistor (TFT) including the amorphous silicon layer and its underlying gate insulation layer can exhibit uniform thin-film transistor characteristics. FIG. 18B is a diagram showing crystallinity of the crystalline silicon layer in the case of performing laser annealing crystallization on a conventional structure using the solid-state laser in the visible region, for comparison. Meanwhile, FIG. 18A is a diagram showing crystallinity of the crystalline silicon layer in the case of performing laser annealing crystallization on the structure of the embodiment of the present invention using the solid-state laser in the visible region. FIGS. 18A and 18B show an example where the energy density of the laser light per unit time is 80 KW/cm2, and a laser scan speed is 400 mm/s. In the conventional structure, there are a region crystallized in a crystalline grain size of 50 nm to 70 nm, a region crystallized in a crystalline grain size of 100 nm to 200 nm, and a region crystallized in a crystalline grain size of 200 nm to 500 nm. In the structure of the embodiment of the present invention, on the other hand, crystallization is uniformly performed in a crystalline grain size of 100 nm to 200 nm.
FIG. 19 is a diagram for describing advantageous effects of the embodiment of the present invention. In FIG. 19, the region other than the gate electrode 12, namely, the heat generation of the amorphous silicon layer 14 not located above the gate electrode 12 (i.e. in the second region), is utilized as a means of thermally saturating the gate electrode 12. In more detail, by setting the film thickness of the amorphous silicon layer 14 and the film thickness of the gate insulation layer 13 in the appropriate ranges, a difference in light interference effect depending on whether or not the gate electrode 12 is present is exploited so that (1) the amorphous silicon layer 14 not located above the gate electrode 12 has a higher light absorptance than the amorphous silicon layer 14 located above the gate electrode 12, that is, the amorphous silicon layer 14 not located above the gate electrode 12 (i.e. in the second region) generates more heat than the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region) when laser annealing is performed, and also (2) the silicon thin film located above the gate electrode 12 (i.e. in the first region) has a higher heat generation temperature than a melting point of silicon.
Owing to the advantageous effect (1), heat generated in the amorphous silicon layer 14 in the second region can be transmitted to and absorbed by the gate electrode 12. This allows the gate electrode 12 to be thermally saturated before the laser light anneals the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region). Hence, the influence of heat absorption and heat transmission by the gate electrode 12 on the crystallization of the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region) can be reduced. Moreover, owing to the advantageous effect (2), even in the case where the silicon thin film not located above the gate electrode 12 (i.e. in the second region) has an excessively higher light absorptance than the silicon thin film located above the gate electrode 12 (i.e. in the first region), that is, even in the case where the amorphous silicon layer 14 not located above the gate electrode 12 (i.e. in the second region) generates excessively more heat than the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region), both the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region) and the amorphous silicon layer 14 not located above the gate electrode 12 (i.e. in the second region) melt to become a molten silicon layer, as a result of which the heat conductivity of the amorphous silicon layer 14 increases to a substantially same level as a heat conductivity of metal typically used as the gate electrode 12.
Accordingly, heat generated from the molten silicon layer not located above the gate electrode 12 (i.e. in the second region) is mainly transmitted to the molten silicon layer located above the gate electrode 12 (i.e. in the first region), and thus kept from being excessively absorbed by the gate electrode 12 via the gate insulation layer 13. Therefore, the temperature distribution of the gate electrode 12 is kept from deterioration, and so the heat generation temperature distribution of the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region) is unaffected.
Thus, the combination of the advantageous effects (1) and (2) ensures a uniform heat generation temperature distribution of the amorphous silicon layer 14 located above the gate electrode 12 (i.e. in the first region). This leads to an advantageous effect of ensuring a uniform crystal structure in the crystalline silicon layer 15 produced by crystallization.
As described above, according to the present invention, it is possible to realize a thin-film transistor device manufacturing method, a thin-film transistor, and a display device using the thin-film transistor in which a crystalline silicon film of stable crystallinity can be formed using a laser of a wavelength in the visible region. In detail, it is possible to realize a thin-film transistor device manufacturing method, a thin-film transistor, and a display device using the thin-film transistor in which a crystalline silicon layer of stable crystallinity can be formed using a laser of a wavelength in the visible region by forming a silicon thin film and a gate insulation layer with respective film thicknesses that satisfy a predetermined condition, without a need for a particular change in thin-film transistor structure such as a gate electrode pattern shape.
Moreover, a display device of high image quality with uniform TFT characteristics can be realized in the case where the thin-film transistor according to the present invention is used in a display device shown in FIG. 20. With such improvement in display quality, increased yields and reduced costs can be achieved, too.
The present invention achieves the advantageous effects merely by setting the aforementioned range of film thickness condition, without a need for a particular change in thin-film transistor structure such as a gate electrode pattern shape. Thus, the present invention is superior to the conventional art in that design flexibility is ensured even in the case of, for example, manufacturing a display device of a higher resolution.
Though the thin-film transistor device manufacturing method, the thin-film transistor, and the display device using the thin-film transistor according to the present invention have been described by way of the embodiment, the present invention is not limited to the embodiment. Modifications obtained by applying various changes conceivable by those skilled in the art to the embodiment and any combinations of components in different embodiments are also included in the present invention without departing from the scope of the present invention.
Although only an exemplary embodiment of the present invention has been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiment without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention.
INDUSTRIAL APPLICABILITY
The present invention is applicable to a thin-film transistor device manufacturing method, a thin-film transistor, and a display device including a liquid crystal panel or an EL panel such as an organic EL panel using the thin-film transistor. The present invention is particularly applicable to, for example, manufacturing of a display device including a liquid crystal panel or an EL panel such as an organic EL panel of high image quality with uniform TFT characteristics because, in the case where a gate electrode is located below an amorphous silicon layer via a gate insulation film in a laser crystallization process, stable crystallization can be performed while suppressing an influence of heat absorption and heat transmission by the gate electrode.

## Claims

1. A thin-film transistor device manufacturing method, comprising:
providing a substrate;
forming a plurality of gate electrodes above the substrate;
forming a silicon nitride layer on the plurality of gate electrodes;
forming a silicon oxide layer on the silicon nitride layer;
forming an amorphous silicon layer on the silicon oxide layer;
crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, to produce a crystalline silicon layer; and
forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes,
wherein a film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 1 to 6:


Y≧0.264+14.444×ΔA′  Expression 1



X≦0.729−67.777×ΔA′  Expression 2



Y≦−0.388X+0.584−21.124×ΔA′  Expression 3



Y≦0.427−28.519×ΔA′  Expression 4



X≧0.344+32.963×ΔA′  Expression 5



Y≧−0.388X+0.457+21.412×ΔA′,  Expression 6


where X is a value obtained by dividing an optical film thickness of the amorphous silicon layer by the wavelength of the laser light, the optical film thickness of the amorphous silicon layer being a result of multiplying the film thickness of the amorphous silicon layer by a refractive index of the amorphous silicon layer,
Y is a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, the silicon oxide layer converted optical film thickness being a value obtained by dividing a sum of an optical film thickness of the silicon oxide layer and an optical film thickness of the silicon nitride layer by a refractive index of the silicon oxide layer, the optical film thickness of the silicon oxide layer being a result of multiplying the film thickness of the silicon oxide layer by the refractive index of the silicon oxide layer, and the optical film thickness of the silicon nitride layer being a result of multiplying the film thickness of the silicon nitride layer by a refractive index of the silicon nitride layer, and
ΔA′ is a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG), where ρSi and cSi are respectively a density and a specific heat of the amorphous silicon layer, dG, ρG, and cG are respectively a film thickness, a density, and a specific heat of the gate electrode, and AG is a maximum absorptance of the gate electrode when the amorphous silicon layer located above the gate electrode and the amorphous silicon layer not located above the gate electrode have an equal light absorptance for the laser light.

2. The thin-film transistor device manufacturing method according to claim 1,
wherein, in said crystallizing of the amorphous silicon layer, the predetermined laser emits the laser light in an oscillation mode that is a continuous wave mode or a quasi-continuous wave mode.

3. The thin-film transistor device manufacturing method according to claim 1,
wherein the predetermined laser includes a solid-state laser device.

4. The thin-film transistor device manufacturing method according to claim 1,
wherein the predetermined laser includes a laser device that uses a semiconductor laser element.

5. The thin-film transistor device manufacturing method according to claim 1,
wherein, in said crystallizing of the amorphous silicon layer, a variation in irradiation energy density of the laser light on the amorphous silicon layer is less than approximately 5%.

6. The thin-film transistor device manufacturing method according to claim 1,
wherein, in said forming of the silicon nitride layer and said forming of the silicon oxide layer, the silicon nitride layer and the silicon oxide layer are formed with the respective film thicknesses so that a capacitance of a series capacitor composed of the silicon nitride layer and the silicon oxide layer is equal to a capacitance of a silicon oxide single layer of 100 nm to 140 nm in film thickness.

7. The thin-film transistor device manufacturing method according to claim 1,
wherein the film thickness of the silicon oxide layer, the film thickness of the silicon nitride layer, and the film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 7 and 8:


0.442≦X≦0.559  Expression 7



0.310≦Y≦0.341.  Expression 8

8. The thin-film transistor device manufacturing method according to claim 6,
wherein the wavelength of the predetermined laser is 445 nm to 455 nm.

9. The thin-film transistor device manufacturing method according to claim 6,
wherein the film thickness of the amorphous silicon layer is in a range of 40 nm to 45 nm.

10. The thin-film transistor device manufacturing method according to claim 1,
wherein said forming of the plurality of gate electrodes includes:
forming an undercoat layer made of silicon oxide, on the substrate; and
forming the plurality of gate electrodes on the undercoat layer.

11. A thin-film transistor device comprising:
a substrate;
a plurality of gate electrodes formed above said substrate;
a silicon nitride layer formed on said plurality of gate electrodes;
a silicon oxide layer formed on said silicon nitride layer;
a crystalline silicon layer formed on said silicon oxide layer; and
a source electrode and a drain electrode formed on said crystalline silicon layer in a region that corresponds to each of said plurality of gate electrodes,
wherein said crystalline silicon layer is produced by forming an amorphous silicon layer on said silicon oxide layer and then crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to said substrate, and
a film thickness of said silicon oxide layer, a film thickness of said silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy X and Y that are in ranges defined by Expressions 1 to 6:


Y≧0.264+14.444×ΔA′  Expression 1



X≦0.729−67.777×ΔA′  Expression 2



Y≦−0.388X+0.584−21.124×ΔA′  Expression 3



Y≦0.427−28.519×ΔA′  Expression 4



X≧0.344+32.963×ΔA′  Expression 5



Y≧−0.388X+0.457+21.412×ΔA′,  Expression 6


where X is a value obtained by dividing an optical film thickness of the amorphous silicon layer by the wavelength of the laser light, the optical film thickness of the amorphous silicon layer being a result of multiplying the film thickness of the amorphous silicon layer by a refractive index of the amorphous silicon layer,
Y is a value obtained by dividing a silicon oxide layer converted optical film thickness by the wavelength of the laser light, the silicon oxide layer converted optical film thickness being a value obtained by dividing a sum of an optical film thickness of said silicon oxide layer and an optical film thickness of said silicon nitride layer by a refractive index of said silicon oxide layer, the optical film thickness of said silicon oxide layer being a result of multiplying the film thickness of said silicon oxide layer by the refractive index of said silicon oxide layer, and the optical film thickness of said silicon nitride layer being a result of multiplying the film thickness of said silicon nitride layer by a refractive index of said silicon nitride layer, and
ΔA′ is a value calculated according to an expression (AG/dG)×(ρSi×cSi)/(ρG×cG), where ρSi and cSi are respectively a density and a specific heat of the amorphous silicon layer, dG, ρG, and cG are respectively a film thickness, a density, and a specific heat of said gate electrode, and AG is a maximum absorptance of said gate electrode when the amorphous silicon layer located above said gate electrode and the amorphous silicon layer not located above said gate electrode have an equal light absorptance for the laser light.

12. A display device comprising a liquid crystal panel or an EL panel, said display device comprising
the thin-film transistor device according to claim 11,
wherein said thin-film transistor device drives said liquid crystal panel or said EL panel.

13. The display device according to claim 12,
wherein said EL panel is an organic EL panel.

14. A thin-film transistor device manufacturing method, comprising:
providing a substrate;
forming a plurality of gate electrodes above the substrate;
forming a silicon nitride layer on the plurality of gate electrodes;
forming a silicon oxide layer on the silicon nitride layer;
forming an amorphous silicon layer on the silicon oxide layer;
crystallizing the amorphous silicon layer using laser light emitted from a predetermined laser of 405 nm to 488 nm in wavelength while moving the predetermined laser in a given direction relative to the substrate, to produce a crystalline silicon layer; and
forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes,
wherein said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the amorphous silicon layer are performed so that, in said crystallizing of the amorphous silicon layer, when the amorphous silicon layer is irradiated with the laser light, a maximum reached temperature of the amorphous silicon layer in a region not located above the gate electrode is higher than a maximum reached temperature of the amorphous silicon layer in a region located above the gate electrode and also the amorphous silicon layer in the region located above the gate electrode has a substantially uniform maximum reached temperature, the region not located above the gate electrode being upstream in the direction of the relative movement of the predetermined laser.

15. The thin-film transistor device manufacturing method according to claim 14,
wherein in said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the amorphous silicon layer, the gate electrode, the silicon nitride layer, the silicon oxide layer, and the amorphous silicon layer are formed with respective film thicknesses so that, in said crystallizing of the amorphous silicon layer, when the amorphous silicon layer is irradiated with the laser light, the maximum reached temperature of the amorphous silicon layer in the region not located above the gate electrode is higher than the maximum reached temperature of the amorphous silicon layer in the region located above the gate electrode and also the amorphous silicon layer in the region located above the gate electrode has the substantially uniform maximum reached temperature, the region not located above the gate electrode being upstream in the direction of the relative movement of the predetermined laser.

16. A thin-film transistor device manufacturing method, comprising:
providing a substrate;
forming a gate electrode above the substrate;
forming a silicon nitride layer on the gate electrode;
forming a silicon oxide layer on the silicon nitride layer;
forming a semiconductor material layer that includes a semiconductor material, on the silicon oxide layer;
crystallizing the semiconductor material by irradiating the semiconductor material layer with predetermined laser light of 405 nm to 488 nm in wavelength, to produce a semiconductor layer; and
forming a source electrode and a drain electrode on the semiconductor layer in a second region that does not correspond to the gate electrode, the second region being different from a first region that corresponds to the gate electrode,
wherein said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the semiconductor material layer are performed so that a heating value of the semiconductor material layer in the second region per unit volume is higher than a heating value of the semiconductor material layer in the first region per unit volume, and
in said crystallizing of the semiconductor material, heat generated in the semiconductor material layer in the first region by the irradiation with the predetermined laser light and transmitted to and absorbed by the gate electrode is accumulated in the gate electrode without being diffused into the semiconductor material layer in the second region, and a part having a uniform temperature distribution is formed in the semiconductor material layer in the first region generating the heat, to crystallize the semiconductor material.

17. The thin-film transistor device manufacturing method according to claim 16,
wherein in said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the semiconductor material layer, the gate electrode, the silicon nitride layer, the silicon oxide layer, and the semiconductor material layer are formed with respective film thicknesses so that the heating value of the semiconductor material layer in the second region per unit volume is higher than the heating value of the semiconductor material layer in the first region per unit volume.

18. The thin-film transistor device manufacturing method according to claim 16,
wherein the second region of the semiconductor material layer is a region upstream and downstream of the first region of the semiconductor material layer, in a direction in which the predetermined laser light is moved relative to the substrate in said crystallizing of the semiconductor material.

19. The thin-film transistor device manufacturing method according to claim 16,
wherein said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the semiconductor material layer are performed so that, in said crystallizing of the semiconductor material, a difference between the heating value of the semiconductor material layer in the second region per unit volume and the heating value of the semiconductor material layer in the first region per unit volume is equal to or more than a heating value of the gate electrode per unit volume.

20. The thin-film transistor device manufacturing method according to claim 16,
wherein said forming of the plurality of gate electrodes, said forming of the silicon nitride layer, said forming of the silicon oxide layer, and said forming of the semiconductor material layer are performed so that, in said crystallizing of the semiconductor material, the part having the uniform temperature distribution is formed in the semiconductor material layer in the first region at a ratio of 0.8 to 1.0 in size to the first region.