# Patent

## Title
Display apparatus

## Abstract

A display apparatus includes: a display panel that includes display elements having a current-driven light-emitting portion and that displays an image on the basis of a video signal; and a luminance correcting unit that corrects the luminance of the display elements when the display panel displays an image by correcting a gradation value of an input signal and outputting the corrected input signal as the video signal. The luminance correcting unit includes an operating time conversion factor holder, a reference operating time calculator, an accumulated reference operating time storage, a reference curve storage, a gradation correction value holder, and a video signal generator.

## Background
FIELD
The present disclosure relates to a display apparatus, and more particularly, to a display apparatus that can compensate for a temporal variation in luminance of a display element.
BACKGROUND
Display elements having a light-emitting portion and display apparatuses having such display elements are widely known. For example, a display element (hereinafter, also simply abbreviated as an organic EL display element) having an organic electroluminescence light-emitting portion using the electroluminescence (hereinafter, also abbreviated as EL) of an organic material has attracted attention as a display element capable of emitting light with high luminance through low-voltage DC driving.
Similarly to a liquid crystal display, for example, in a display apparatus (hereinafter, also simply abbreviated as an organic EL display apparatus) including organic EL display elements, a simple matrix type and an active matrix type are widely known as a driving type. The active matrix type has a disadvantage that the structure is complicated but has an advantage that the luminance of an image can be enhanced. The organic EL display element driven by an active matrix driving method includes a light-emitting portion constructed by an organic layer including a light-emitting layer and a driving circuit driving the light-emitting portion.
As a circuit driving an organic electroluminescence light-emitting portion (hereinafter, also simply abbreviated as a light-emitting portion), for example, a driving circuit (referred to as a 2Tr/1C driving circuit) including two transistors and a capacitor is widely known from JP-A-2007-310311 and the like. The 2Tr/1C driving circuit includes two transistors of a writing transistor TRW and a driving transistor TRD and one capacitor C1, as shown in FIG. 3.
The operation of the organic EL display element including the 2Tr/1C driving circuit will be described in brief below. As shown in the timing diagram of FIG. 22, a threshold voltage cancelling process is performed in period TP(2)3 and period TP(2)5. Then, a writing process is performed in period TP(2)7 and a drain current Ids flowing from the drain region of the driving transistor TRD to the source region flows in the light-emitting portion ELP in period TP(2)8. Basically, the organic EL display element emits light with a luminance corresponding to the product of the emission efficiency of the light-emitting portion ELP and the value of the drain current Ids flowing in the light-emitting portion ELP.
The operation of the organic EL display element including the 2Tr/1C driving circuit will be described later in detail with reference to FIG. 22 and FIGS. 24A to 29.
In general, in a display apparatus, the luminance becomes lower as the operating time becomes longer. In the display apparatus using the organic EL display elements, the fall in luminance due to a temporal variation in the emission efficiency of a light-emitting portion is observed. Therefore, in the display apparatus, when a single pattern is displayed for a long time, a so-called burn-in phenomenon where a variation in luminance due to the displayed pattern is observed or the like may occur. For example, as shown in FIG. 32A, the display apparatus is made to operate for a long time in a state where characters are displayed (in white) on the upper-right part of a display area EA of the organic EL display apparatus and all areas other than the characters are displayed in black. Thereafter, when the entire display area EA is displayed in white, the luminance of the upper-right part in which the characters have been displayed in the display area EA is relatively lowered as shown in FIG. 32B, which is recognized as an unnecessary pattern. In this way, when the burn-in phenomenon occurs, the display quality of the display apparatus is lowered.
SUMMARY
The fall in display quality of a display apparatus due to the burn-in phenomenon can be solved by controlling display elements so as to compensate for the fall in luminance due to the burn-in when driving the display elements in which the burn-in occurs. However, the fall in emission efficiency, for example, in a light-emitting portion of an organic EL display element depends on histories of the luminance of a displayed image and an operating time. In a method of measuring temporal variation data of operation histories plural times in advance and compensating for the fall in the luminance due to the burn-in phenomenon with reference to a table storing the measured temporal variation data, there is a problem in that the scale of the control circuit increases and the control is complicated.
Therefore, it is desirable to provide a display apparatus which can compensate for a fall in luminance due to the burn-in phenomenon without individually storing a history of luminance of a displayed image and a history of an operating time as data but by reflecting the histories or to provide a display apparatus driving method which can compensate for the fall in luminance due to the burn-in phenomenon by reflecting the histories.
An embodiment of the present disclosure is directed to a display apparatus including: a display panel that includes display elements having a current-driven light-emitting portion and that displays an image on the basis of a video signal; and a luminance correcting unit that corrects the luminance of the display elements when the display panel displays an image by correcting a gradation value of an input signal and outputting the corrected input signal as the video signal, wherein the luminance correcting unit includes an operating time conversion factor holder that stores as an operating time conversion factor the ratio of the values of operating times until the temporal variation in luminance reaches a certain value by causing each display element to operate on the basis of the video signal of various gradation values and the value of an operating time until the temporal variation in luminance reaches the certain value by causing each display element to operate on the basis of the video signal of a predetermined reference gradation value, a reference operating time calculator that calculates the value of a reference operating time in which the temporal variation in luminance of each display element when the corresponding display element operates for a predetermined unit time on the basis of the video signal is equal to the temporal variation in luminance of each display element when it is assumed that the corresponding display element operates on the basis of the video signal of the predetermined reference gradation value by multiplying the value of the operating time conversion factor corresponding to the gradation value of the video signal by the value of the unit time, an accumulated reference operating time storage that stores an accumulated reference operating time obtained by accumulating the value of the reference operating time calculated by the reference operating time calculator for each display element, a reference curve storage that stores a reference curve representing the relationship between the operating time of each display element and the temporal variation in luminance of the corresponding display element when the corresponding display element operates on the basis of the video signal of the predetermined reference gradation value, a gradation correction value holder that calculates a gradation correction value used to compensate for the temporal variation in luminance of each display element with reference to the accumulated reference operating time storage and the reference curve storage and that stores the gradation correction value corresponding to the respective display elements, and a video signal generator that corrects the gradation value of the input signal corresponding to the respective display elements on the basis of the gradation correction values stored in the gradation correction value holder and that outputs the corrected input signal as the video signal, wherein the display panel includes a dummy display element not contributing to the display of an image, and wherein the operating time conversion factor holder includes an operating time conversion factor updating section that updates the operating time conversion factor by comparing the value of the reference curve with the operating time and the temporal variation in luminance when the dummy element operates on the basis of the video signal of a predetermined gradation value.
In the display apparatus according to the embodiment of the present disclosure, it is possible to compensate for the fall in luminance due to a burn-in phenomenon by not individually storing a history of luminance of a displayed image and a history of an operating time as data but reflecting the histories. Since the operating time conversion factor holder updates the operating time conversion factor by comparing the value of the reference curve with the operating time and the temporal variation in luminance when the dummy display element operates on the basis of the video signal of a constant gradation value, it is possible to perform a control depending on the characteristic unevenness of the display panel.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a conceptual diagram illustrating a display apparatus according to Example 1.
FIG. 2 is a block diagram schematically illustrating the configuration of a luminance correcting unit.
FIG. 3 is an equivalent circuit diagram of a display element constituting a display panel.
FIG. 4A is a partial sectional view schematically illustrating a part including a display element in the display panel.
FIG. 4B is a partial sectional view schematically illustrating a part including a dummy display element in the display panel.
FIG. 5A is a graph illustrating the relationship between the value of a video signal voltage in a display element in an initial state and the luminance value of the display element.
FIG. 5B is a graph illustrating the relationship between the value of a video signal voltage in a display element in which a temporal variation occurs and the luminance value of the display element.
FIG. 6 is a graph schematically illustrating the relationship between an accumulated operating time when a display element is made to operate on the basis of video signals of various gradation values and the relative luminance variation of the display element due to the temporal variation.
FIG. 7 is a graph schematically illustrating the relationship between an operating time when a display element is made to operate while changing a gradation value of a video signal and the relative luminance variation of the display element due to the temporal variation.
FIG. 8 is a diagram schematically illustrating the correspondence between graph parts indicated by reference signs CL1, CL2, CL3, CL4, CL5, and CL6 in FIG. 7 and the graph shown in FIG. 6.
FIG. 9 is a graph schematically illustrating the relationship between an accumulated operating time until the relative luminance variation of a display element due to the temporal variation reaches a certain value “β” by causing a display element to operate on the basis of a video signal and the gradation value of the video signal.
FIG. 10 is a graph schematically illustrating a method of converting the operating time when a display element is made to operate on the basis of the operation history shown in FIG. 7 into a reference operating time when it is assumed that the display element is made to operate on the basis of a video signal of a predetermined gradation value.
FIG. 11 is a graph illustrating the relationship between a gradation value of a video signal and an operating time conversion factor.
FIG. 12 is a block diagram schematically illustrating the configuration of a luminance correcting unit in a reference example.
FIG. 13 is a graph schematically illustrating data stored in a reference curve storage.
FIG. 14 is a graph schematically illustrating data stored in an operating time conversion factor holder.
FIG. 15 is a graph schematically illustrating data stored in an accumulated reference operating time storage.
FIG. 16 is a graph schematically illustrating the operation of a gradation correction value calculator of a gradation correction value holder.
FIG. 17 is a graph schematically illustrating the operation of a gradation correction value storage of the gradation correction value holder.
FIG. 18 is a graph schematically illustrating a method of comparing the value of a reference curve with the measured value of a dummy display element.
FIG. 19 is a graph schematically illustrating updated data stored in the operating time conversion factor holder.
FIG. 20 is a graph schematically illustrating the method of comparing the value of a reference curve with the measured value of a dummy display element.
FIG. 21 is a graph schematically illustrating the updated data stored in the operating time conversion factor holder.
FIG. 22 is a timing diagram schematically illustrating the operation of a display element in a display apparatus driving method according to Example 1 or Example 2.
FIG. 23 is a timing diagram schematically illustrating the operation of a dummy display element in the display apparatus driving method according to Example 1 or Example 2.
FIGS. 24A and 24B are diagrams schematically illustrating ON/OFF states of transistors in a driving circuit of a display element.
FIGS. 25A and 25B are diagrams schematically illustrating the ON/OFF states of the transistors in the driving circuit of the display element subsequently to FIG. 24B.
FIGS. 26A and 26B are diagrams schematically illustrating the ON/OFF states of the transistors in the driving circuit of the display element subsequently to FIG. 25B.
FIGS. 27A and 27B are diagrams schematically illustrating the ON/OFF states of the transistors in the driving circuit of the display element subsequently to FIG. 26B.
FIGS. 28A and 28B are diagrams schematically illustrating the ON/OFF states of the transistors in the driving circuit of the display element subsequently to FIG. 27B.
FIG. 29 is a diagram schematically illustrating the ON/OFF states of the transistors in the driving circuit of the display element subsequently to FIG. 28B.
FIG. 30 is an equivalent circuit diagram of a display element including a driving circuit.
FIG. 31 is an equivalent circuit diagram of a display element including a driving circuit.
FIGS. 32A and 32B are schematic front views of a display area illustrating a burn-in phenomenon in a display apparatus.



DETAILED DESCRIPTION
Hereinafter, examples of the present disclosure will be described with reference to the accompanying drawings. The present disclosure is not limited to the examples and various numerical values and materials in the embodiments are only examples. In the following description, like elements or elements having like functions will be referenced by like reference signs and descriptions thereof will not be repeated. The description will be made in the following order.
1. General Explanation of Display Apparatus and Display Apparatus Driving Method
2. Example 1
3. Example 2 (Others)
[General Explanation of Display Apparatus and Display Apparatus Driving Method]
From the viewpoint of digital control, it is preferable that the values of an input signal and a video signal vary in steps expressed by powers of 2. In the display apparatus and the display apparatus driving method according to the embodiment of the present disclosure, the gradation value of the video signal may be greater than the maximum value of the gradation value of the input signal.
For example, an input signal can be subjected to an 8-bit gradation control and a video signal can be subjected to a gradation control greater than 8 bits. For example, a configuration in which the video signal is subjected to a 9-bit control can be considered, but the present disclosure is not limited to this example.
In the display apparatus according to the embodiment of the present disclosure, as the unit time becomes shorter, the precision in burn-in compensation becomes further improved but the processing load of the luminance correcting unit also becomes greater. The unit time can be appropriately set depending on the specification of the display apparatus.
For example, a time given as the reciprocal of a display frame rate, that is, a time occupied by a so-called one frame period, can be set as the unit time. Alternatively, a time occupied by a period including a predetermined number of frame periods can be set as the unit time. In the latter case, video signals of various gradation values are supplied to one display element in the unit time. In this case, for example, it has only to be configured to refer to only the gradation value in the first frame period of the unit time.
In the display apparatus according to the embodiment of the present disclosure, an operating time conversion factor updating section can be configured to update an operating time conversion factor every predetermined operating time.
It may be configured to update the operating time conversion factor, for example, whenever the display apparatus operates for an hour or it may be configuration to update the operating conversion factor whenever the display apparatus operates for 10 hours. In general, as the unit time becomes shorter, the precision in burn-in compensation becomes more improved but the processing load of the luminance correcting unit also becomes greater. The unit time can be appropriately set depending on the specification of the display apparatus.
In the display apparatus according to the embodiment of the present disclosure, the operating time conversion factor updating section may update the operating time conversion factor by comparing the values of the reference curves with the operating times and the temporal variations in luminance of a plurality of the dummy display elements operating on the basis of different gradation values.
Specifically, it can be configured to update the value of the operating time conversion factor, for example, by interpolating the data obtained by comparing the values of the reference curve with the operating times and the temporal variations in luminance of plural dummy display elements.
In the display apparatus according to the embodiment of the present disclosure, the operating time conversion factor updating section may update the operating time conversion factor by comparing with the value of the reference curve with the operating time and the temporal variation in luminance of the dummy display element operating on the basis of a single gradation value.
Specifically, it can be configured to update the value of the operating time conversion factor by storing an operating time conversion factor of an initial state in the operating time conversion factor holder, acquiring a predetermined coefficient on the basis of data obtained by comparing the value of the reference curve with the operating time and the temporal variation in luminance of a dummy display element operating on a single gradation value, and multiplying the operating time conversion factor of the initial state by the acquired factor.
It is preferable that the dummy display element is arranged in a part surrounding a display area. The temporal variation of the dummy display element can be obtained by processing luminance information from an optical sensor disposed to face the dummy display element.
A widely-known sensor such as a photo-diode or a photo-transistor can be used as the optical sensor. For example, an optical sensor which is a member independent of the display panel may be disposed to correspond to the dummy display element. Alternatively, an optical sensor may be incorporated into the display panel, for example, using the same type of semiconductor element such as the semiconductor element (for example, transistors constituting a driving circuit driving a light-emitting portion) constituting a display element.
In the display apparatus having the above-mentioned preferable configurations, a reference operating time calculator, an accumulated reference operating time storage, a reference curve storage, a gradation correction value holder, a video signal generator, and an operating time conversion factor updating section of the luminance correcting unit can be constructed by widely-known circuit elements. The same is true of various circuits such as a power supply circuit, a scanning circuit, and a signal output circuit to be described later.
The display apparatus according to the embodiment of the present disclosure having the above-mentioned various configurations may have a so-called monochrome display configuration or a color display configuration.
In case of the color display configuration, one pixel can include plural sub-pixels, and for example, one pixel can include three sub-pixels of a red light-emitting sub-pixel, a green light-emitting sub-pixel, and a blue light-emitting sub-pixel. A group (such as a group additionally including a sub-pixel emitting white light to improve the luminance, a group additionally including a sub-pixel complementary color light to extend the color reproduction range, a group additionally including a sub-pixel emitting yellow light to extend the color reproduction range, and a group additionally including sub-pixels emitting yellow and cyan to extend the color reproduction range) including one or more types of sub-pixels in addition to the three types of sub-pixels may be configured.
Examples of pixel values in the display apparatus include several image-display resolutions such as VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024), U-XGA (1600, 1200), HD-TV (1920, 1080), and Q-XGA (2048, 1536), (1920, 1035), (720, 480), and (1280, 960), but the pixel values are not limited to these values.
In the display apparatus according to the embodiment of the present disclosure, examples of a current-driven light-emitting portion constituting a display element include an organic electroluminescence light-emitting portion, an LED light-emitting portion, and a semiconductor laser light-emitting portion. These light-emitting portions can be formed using widely-known materials or methods. From the viewpoint of construction of a flat panel display apparatus, the light-emitting portion is preferably formed of the organic electroluminescence light-emitting portion. The organic electroluminescence light-emitting portion may be of a top emission type or a bottom emission type. The organic electroluminescence light-emitting portion can include an anode electrode, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode electrode.
The display elements of the display panel are formed in a certain plane (for example, on a base) and the respective light-emitting portions are formed above the driving circuit driving the corresponding light-emitting portion, for example, with an interlayer insulating layer interposed therebetween.
An example of the transistors constituting the driving circuit driving the light-emitting portion is an n-channel thin film transistor (TFT). The transistor constituting the driving circuit may be of an enhancement type or a depression type. The n-channel transistor may have an LDD (Lightly Doped Drain) structure formed therein. In some cases, the LDD structure may be asymmetric. For example, since large current flows in a driving transistor at the time of light emission of the corresponding display element, the LDD structure may be formed in only one source/drain region serving as the drain region at the time of emission of light. For example, a p-channel thin film transistor may be used.
A capacitor constituting the driving circuit can include one electrode, the other electrode, and a dielectric layer interposed between the electrodes. The transistor and the capacitor constituting the driving circuit are formed in a certain plane (for example, on a base) and the light-emitting portion is formed above the transistor and the capacitor constituting the driving circuit, for example, when an interlayer insulating layer interposed therebetween. The other source/drain region of the driving transistor is connected to one end (such as the anode electrode of the light-emitting portion) of the light-emitting portion, for example, via a contact hole. The transistor may be formed in a semiconductor substrate.
Examples of the material of the base or a substrate to be described later include polymer materials having flexibility, such as polyethersulfone (PES), polyimide, polycarbonate (PC), and polyethylene terephthalate (PET), in addition to glass materials such as high strain point glass, soda glass (Na2O.CaO.SiO2), borosilicate glass (Na2O.B2O3.SiO2) forsterite (2MgO.SiO2), and solder glass (Na2O.PbO.SiO2). The surface of the base or the substrate may be various coated. The materials of the base and the substrate may be equal to or different from each other. When the base and the substrate formed of a polymer material having flexibility are used, a flexible display apparatus can be constructed.
In the display apparatus, various wires such as scanning lines, data lines, and power supply lines may have widely-known configurations or structures.
In two source/drain regions of one transistor, the term “one source/drain region” may be used to mean a source/drain region connected to a power source. If a transistor is in the ON state, it means that a channel is formed between the source/drain regions. It is not considered whether a current flow from one source/drain region of the transistor to the other source/drain region. On the other hand, if a transistor is in the OFF state, it means that a channel is not formed between the source/drain regions. The source/drain region can be formed of a conductive material such as polysilicon containing impurities or amorphous silicon or may be formed of metal, alloy, conductive particles, stacked structures thereof, or a layer including an organic material (conductive polymer).
Conditions in various expressions in this specification are satisfied when the expressions are substantially valid as well as when the expressions are mathematically strictly valid. Regarding the validation of the expressions, a variety of unevenness caused in designing or manufacturing the display elements or the display apparatus is allowable.
In timing diagrams used in the below description, the lengths (time length) of the horizontal axis representing various periods are schematic and do not show the ratios of the time lengths of the periods. The same is trued in the vertical axis. The waveforms in the timing diagram are also schematic.
EXAMPLE 1
Example 1 relates to a display apparatus and a display apparatus driving method according to an embodiment of the present disclosure.
FIG. 1 is a conceptual diagram illustrating the display apparatus according to Example 1. The display apparatus according to Example 1 includes a display panel 20 in which display elements 10 each having a current-driven light-emitting portion are arranged and that displays an image on a video signal VDSig and a luminance correcting unit 110 that corrects the luminance of the display elements 10 when displaying an image on the display panel 20 by correcting the gradation value of the input signal vDSig and outputting the corrected input signal as the video signal VDSig. In Example 1, the light-emitting portion is constructed by an organic electroluminescence light-emitting portion.
An area (display area) in which the display panel 20 displays an image includes total N×M display elements 10 of N display elements in the first direction (the X direction in FIG. 1 which is also referred to as a row direction) and M display elements in the second direction (the Y direction in FIG. 1 which is also referred to as a column direction) which are arranged in a two-dimensional matrix. The number of rows of the display elements 10 in the display area is M and the number of display elements 10 in each row is N. 3×4 display elements 10 are shown in FIG. 1, which is only an example.
The display panel 20 includes plural (M) scanning lines SCL being connected to a scanning circuit 101 and extending in the first direction, plural (N) data lines DTL being connected to a main signal output circuit 102A of a signal output circuit 102 and extending in the second direction, and plural (M) power supply lines PS1 being connected to a power supply unit 100 and extending in the first direction. The display elements 10 in the m-th row (where m=1, 2, . . . , M) are connected to the m-th scanning line SCLm and the m-th power supply line PS1m and constitute a display element row. The display elements 10 in the n-th column (where n=1, 2, N) are connected to the n-th data line DTLn.
The display panel 20 includes dummy display elements 10Dmy not contributing the display of an image and a dummy data line DTLDmy which is connected to a dummy signal output circuit 102B of the signal output circuit 102 and which extends in the second direction. The dummy display elements 10Dmy have the same configuration as the display elements 10, except that they do not contribute to the display of an image.
For example, P (where P is a natural number) dummy display elements 10Dmy are arranged in the second direction with a predetermined gap spaced from the display elements 10 in the N-th column not shown. The dummy display elements 10Dmy are disposed in an invalid area surrounding the display area. The arrangement of the dummy display elements 10Dmy is not limited to this example, but can be appropriately set depending on the design or specification of the display apparatus.
The dummy data line DTLDmy is connected to all the dummy display elements 10Dmy. The dummy display element 10Dmy in the p-th row (where p=1, 2, . . . , P) is connected to the p-th scanning line SCL and the p-th power supply line PS1.
Therefore, the display elements 10 and the dummy display element 10Dmy in the first row are scanned through the use of the first scanning line SCL and the display elements 10 and the dummy display element 10Dmy in the second row are scanned through the use of the second scanning line SCL. The same is true of the display elements 10 and the dummy display elements 10Dmy in the other rows.
The display apparatus 1 includes an optical sensor 120 constructed by, for example, a photo-transistor. As shown in FIG. 4B, the optical sensor 120 is disposed on the display panel 20 so as to face the dummy display element 10Dmy. The luminance information of the optical sensor 120 is transmitted to the luminance correcting unit 110.
The power supply unit 100 and the scanning circuit 101 can have widely-known configurations or structures.
The signal output circuit 102 includes a D/A converter or a latch circuit not shown. The main signal output circuit 102A of the signal output circuit 102 generates a video signal voltage VSig based on the gradation value of a video signal VDSig, holds the video signal voltage VSig corresponding to one row, and supplies the video signal voltage VSig to N data lines DTL. The signal output circuit 102 includes a selector circuit not shown and is switched between a state where the video signal voltage VSig is supplied to the data lines DTL and a state where a reference voltage VOfs is supplied to the data lines DTL by the switching of the selector circuit.
On the other hand, the dummy signal output circuit 102B of the signal output circuit 102 generates a video signal voltage (dummy video signal voltage) VDmy, for example, on the basis of a video signal (dummy video signal) VDDmy of a predetermined gradation value generated therein and supplies the dummy video signal voltage to the dummy data line DTLDmy. The video signal VDDmy is a signal of a predetermined gradation value corresponding to the dummy display elements 10Dmy and is generated regardless of the input signal vDSig. The signal output circuit is switched between a state where the video signal voltage VDmy is supplied to the dummy data lines DTLDmy and a state where a reference voltage VOfs is supplied to the data line DTLDmy by the switching of the selector circuit.
The power supply unit 100, the scanning circuit 101, and the signal output circuit 102 can be constructed using widely-known circuit elements and the like.
The display apparatus 1 according to Example 1 is a monochrome display apparatus including plural display elements 10 (for example, N×M=640×480). Each display element 10 constitutes a pixel. In the display area, the pixel are arrange in a two-dimensional matrix in the row direction and the column direction.
The display apparatus 1 is line-sequentially scanned by rows by a scanning signal from the scanning circuit 101. A display element 10 located at the n-th position of the M-th row is hereinafter referred to as a (n, m)-th display element 10 or a (n, m)-th pixel. The input signal vDSig corresponding to the (n, m)-th display element 10 is represented by vDSig(n,m) and the video signal voltage VSig, which is corrected by the luminance correcting unit 110, corresponding to the (n, m)-th display element 10 is represented by VDSig(n,m). The video signal voltage based on the video signal VDSig(n,m) is represented by VSig(n,m) and the video signal voltage based on the video signal VDDmy is represented by VDmy.
As described above, the luminance correcting unit 110 corrects the gradation value of the input signal vDSig and outputs the corrected input signal as the video signal VDSig.
For purposes of ease of explanation, it is assumed that the number of gradation bits of the input signal vDSig is 8 bits. The gradation value of the input signal vDSig is one of 0 to 255 depending on the luminance of an image to be displayed. Here, it is assumed that the luminance of the image to be displayed becomes higher as the gradation value becomes greater.
It is assumed that the number of gradation bits of the video signal VDSig is 9 bits. The gradation value of the video signal VDSig is one of 0 to 511 depending on the temporal variation of the display element 10 and the gradation value of the input signal vDSig. The display element 10 in the initial state, that is, the display element 10 in which the luminance variation due to the temporal variation does not occur, is supplied with the video signal VDSig of the same gradation value as the gradation value of the input signal vDSig from the luminance correcting unit 110.
Similarly to the video signal VDSig, it is assumed that the number of gradation bits of the video signal VDDmy is 9 bits. As described above, the dummy display elements 10Dmy in the first to P-th rows are also scanned with the scanning of the display elements 10 in the first to P-th rows. For purposes of ease of explanation, in Example 1, it is assumed that P=5, the dummy display element 10Dmy in the first row operates on the basis of the video signal VDDmy of a gradation value 100, and the dummy display element 10Dmy in the second row operates on the basis of the video signal VDDmy of a gradation value 200. The dummy display element 10Dmy in the third row operates on the basis of the video signal VDDmy of a gradation value 300, the dummy display element 10Dmy in the fourth row operates on the basis of the video signal VDDmy of a gradation value 400, and the dummy display element 10Dmy in the fifth row operates on the basis of the video signal VDDmy of a gradation value 500.
FIG. 2 is a block diagram schematically illustrating the configuration of the luminance correcting unit. The operation of the luminance correcting unit 110 will be described in detail later with reference to FIGS. 12 to 19. The luminance correcting unit 110 will be schematically described below.
The luminance correcting unit 110 includes an operating time conversion factor holder 113, a reference operating time calculator 112, an accumulated reference operating time storage 114, a reference curve storage 116, a gradation correction value holder 115, and a video signal generator 111. These are constructed by a calculation circuit or a memory device (memory) and can be constructed by widely-known circuit elements.
The operating time conversion factor holder 113 stores as an operating time conversion factor the ratio of the values of the operating times until the temporal variation in luminance reaches a certain value by causing each display element 10 to operate on the basis of the video signal VDSig of various gradation values and the value of an operating time until the temporal variation in luminance by causing the corresponding display element 10 to operate on the basis of the video signal VDSig of the predetermined reference gradation value.
The operating time conversion factor holder 113 includes an operating time conversion factor storage 113A and an operating time conversion factor updating section 113B. The operating time conversion factor updating section 1133 updates the operating time conversion factor stored in the operating time conversion factor storage 113A by comparing the values of the reference curve stored in the reference curve storage 116 with the operating time and the temporal variation in luminance when the dummy display elements 10Dmy operate on the basis of the video signal VDDmy of a constant gradation value. Specifically, the operating time conversion factor storage 113A stores functions fCSC—APT, which are sequentially updated, indicating the relationship of the graph of FIG. 19 as a table. The operating time conversion factor updating section 113B is constructed by a calculation circuit or the like and the operating time conversion factor storage 113A is constructed by a memory device such as a rewritable nonvolatile memory.
The reference operating time calculator 112 calculates the value of a reference operating time in which the temporal variation in luminance of each display element 10 when the corresponding display element 10 operates for a predetermined unit time on the basis of the video signal VDSig is equal to the temporal variation in luminance of the corresponding display element 10 when it is assumed that the corresponding display element 10 operates on the basis of the video signal VDSig of a predetermined reference gradation value, by multiplying the value of the operating time conversion factor corresponding to the gradation value of the video signal VDSig by the value of a unit time. The “predetermined unit time” and the “predetermined reference gradation value” will be described later.
The accumulated reference operating time storage 114 stores an accumulated reference operating time obtained by accumulating the value of the reference operating time calculated by the reference operating time calculator for each display element 10. The accumulated reference operating time is a value reflecting the operation history of the display apparatus 1 and is not reset by turning off the display apparatus 1 or the like. The accumulated reference operating time storage 114 is constructed by a rewritable nonvolatile memory device including memory areas corresponding to the display elements 10 and stores the data shown in FIG. 15. The accumulated reference operating time storage 114 includes a memory area represented by reference sign AP in FIG. 15 so as to store the accumulated value of the values of the operating time of the dummy display elements 10Dmy.
The reference curve storage 116 stores a reference curve representing the relationship between the operating time of each display element 10 and the temporal variation in luminance of the corresponding display element 10 when the corresponding display element 10 operates on the basis of the video signal VDSig of the predetermined reference gradation value. Specifically, the reference curve storage 116 stores functions fREF representing the reference curve shown in FIG. 13 as a table in advance.
The functions fREF are determined in advance on the basis of data measured or the like by the use of a display apparatus with the same specification.
In Example 1, the “predetermined unit time” is defined as the time occupied by a so-called one frame period and the “predetermined reference gradation value” is set to 200, but the present disclosure is not limited to these set values. These set values can be appropriately selected depending on the design of the display apparatus.
The gradation correction value holder 115 calculates a correction value of a gradation value used to compensate for the temporal variation in luminance of each display element 10 with reference to the accumulated reference operating time storage 114 and the reference curve storage 116 and stores the correction value of the gradation value corresponding to each display element 10. The gradation correction value holder 115 includes a gradation correction value calculator 115A and a gradation correction value storage 115B. The gradation correction value calculator 115A is constructed by a calculation circuit. The gradation correction value storage 115B includes memory areas corresponding to the display elements 10, is constructed by a rewritable memory device, and stores the data shown in FIG. 17.
The video signal generator 111 corrects the gradation value of the input signal vDSig corresponding to each display element 10 on the basis of the correction value of the gradation value held by the gradation correction value holder 115 and outputs the corrected input signal as the video signal VDSig.
Hitherto, the luminance correcting unit 110 has been schematically described. The configuration of the display apparatus 1 will be described below.
FIG. 3 is an equivalent circuit diagram of a display element constituting the display panel.
Each display element 10 includes a current-driven light-emitting portion ELP and a driving circuit 11. The driving circuit 11 includes at least a driving transistor TRD having a gate electrode and source/drain regions and a capacitor C. A current flows in the light-emitting portion ELP via the source/drain regions of the driving transistor TRD. Although described later in detail with reference FIG. 4A, the display element 10 has a structure in which a driving circuit 11 and a light-emitting portion ELP connected to the driving circuit 11 are stacked. Since the dummy display element 10Dmy has the same configuration as the display element 10, the configuration of the dummy display element 10Dmy will not be described as long as not particularly requested.
The driving circuit 11 further includes a writing transistor TRW in addition to the driving transistor TRD. The driving transistor TRD and the writing transistor TRW are formed of an n-channel TFT. For example, the writing transistor TRW may be formed of a p-channel TFT. The driving circuit 11 may further include another transistor, for example, as shown in FIGS. 30 and 31.
The capacitor C1 is used to maintain a voltage (a so-called gate-source voltage) of the gate electrode with respect to the source region of the driving transistor TRD. In this case, the “source region” means a source/drain region serving as the “source region” when the light-emitting portion ELP emits light. When the display element 10 is in an emission state, one source/drain region (the region connected to the power supply line PS1 in FIG. 3) of the driving transistor TRD serves as a drain region and the other source/drain region (the region connected to an end of the light-emitting portion ELP, that is, the anode electrode) serves as a source region. One electrode and the other electrode of the capacitor C1 are connected to the other source/drain region and the gate electrode of the driving transistor TRD, respectively.
The writing transistor TRW includes a gate electrode connected to the scanning line SCL, one source/drain region connected to the data line DTL, and the other source/drain region connected to the gate electrode of the driving transistor TRD.
The gate electrode of the driving transistor TRD constitutes a first node ND1 in which the other source/drain region of the writing transistor TRW is connected to the other electrode of the capacitor C1. The other source/drain region of the driving transistor TRD constitutes a second node ND2 in which one electrode of the capacitor C1 are connected to the anode electrode of the light-emitting portion ELP.
The other end (specifically, the cathode electrode) of the light-emitting portion ELP is connected to a second power supply line PS2. As shown in FIG. 1, a second power supply line PS2 is common to all the display elements 10 and all the dummy display elements 10Dmy.
A predetermined voltage Vcat is supplied to the cathode electrode of the light-emitting portion ELP form the second power supply line PS2. The capacitance of the light-emitting portion ELP is represented by reference sign CEL. The threshold voltage necessary for the emission of light of the light-emitting portion ELP is represented by Vth-EL. That is, when a voltage equal to or higher than Vth-EL is applied across the anode electrode and the cathode electrode of the light-emitting portion ELP, the light-emitting portion ELP emits light.
The light-emitting portion ELP has, for example, a widely-known configuration or structure including an anode electrode, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode electrode.
The driving transistor TRD shown in FIG. 3 is set in voltage so as to operate in a saturated region when the display element 10 is in the emission state, and is driven so as for the drain current Ids to flow as expressed by Expression 1. As described above, when the display element 10 is in the emission state, one source/drain region of the driving transistor TRD serves a drain region and the other source/drain region thereof serves as a source region. For purposes of ease of explanation, one source/drain region of the driving transistor TRD may be simply referred to as a drain region and the other source/drain region may be simply referred to as a source region. The reference signs are defined as follows.
μ: effective mobility
L: channel length
W: channel width
Vgs: voltage of gate electrode relative to source region
Vth: threshold voltage
Cox: (specific dielectric constant of gate insulating layer)×(dielectric constant of vacuum)/(thickness of gate insulating layer)

k≡(1⁄2)·(W/L)·Cox 

Ids=k·μ·(Vgs−Vth)2  (1)

By causing the drain current Ids to flow in the light-emitting portion ELP, the light-emitting portion ELP of the display element 10 emits light. The emission intensity of the light-emitting portion ELP of the display element 10 is controlled depending on the magnitude of the drain current Ids.
The ON/OFF state of the writing transistor TRW is controlled by the scanning signal from the scanning line SCL connected to the gate electrode of the writing transistor TRW, that is, the scanning signal from the scanning circuit 101.
Various signals or voltages are applied to one source/drain region of the writing transistor TRW from the data line DTL on the basis of the operation of the main signal output circuit 102A of the signal output circuit 102. Specifically, a video signal voltage VSig and a predetermined reference voltage Vofs are applied thereto from the signal output circuit 102. In addition to the video signal voltage VSig and the reference voltage Vofs, other voltages may be applied thereto.
Various signals or voltages are applied to one source/drain region of the writing transistor TRW in the dummy display element 10Dmy from the dummy data line DTLDmy on the basis of the operation of the dummy signal output circuit 102B of the signal output circuit 102. Specifically, a video signal voltage VDmy and a predetermined reference voltage Vofs are applied thereto from the dummy signal output circuit 102B.
The display apparatus 1 is line-sequentially scanned by rows by the scanning signals from the scanning circuit 101. In each horizontal scanning period, the reference voltage Vofs is first supplied to the data lines DTL and the video signal voltage VSig is supplied thereto.
Similarly to the dummy data line 10Dmy, in each horizontal scanning period, the reference voltage Vofs is first supplied to the data lines DTL and the video signal voltage VDmy is supplied thereto. In Example 1, there is no dummy display element 10Dmy in the sixth or subsequent rows. For purposes of ease of explanation, substantially the same voltage as the reference voltage VOfs is applied as the video signal voltage VDmy when scanning the sixth or subsequent rows.
FIG. 4A is a partial sectional view schematically illustrating a part including a display element in the display panel. The transistors TRD and TRW and the capacitor C1 of the driving circuit 11 are formed on a base 20 and the light-emitting portion ELP is formed above the transistors TRD and TRW and the capacitor C1 of the driving circuit 11, for example, with an interlayer insulating layer 40 interposed therebetween. The other source/drain region of the driving transistor TRD is connected to the anode electrode of the light-emitting portion ELP via a contact hole. In FIG. 4A, only the driving transistor TRD is shown. The other transistors are not shown.
FIG. 4B is a partial sectional view schematically illustrating a part including a dummy display element in the display panel. The configuration of the dummy display element 10Dmy is the same as the display element 10, except that the dummy display element is disposed in an invalid area surrounding the display area. The optical sensor 120 constructed, for example, by a photo-transistor is mounted on a transparent substrate 22 to be described later so as to face the dummy display element 10Dmy.
The configuration of the display element 10 will be specifically described below with reference to FIG. 4A. The driving transistor TRD includes a gate electrode 31, a gate insulating layer 32, source/drain regions 35 and 35 formed in a semiconductor layer 33, and a channel formation region 34 corresponding to a part of the semiconductor layer 33 between the source/drain regions 35 and 35. On the other hand, the capacitor C1 includes the other electrode 36, a dielectric layer formed of an extension of the gate insulating layer 32, and one electrode 37. The gate electrode 31, a part of the gate insulating layer 32, and the other electrode 36 of the capacitor C1 are formed on the base 21. One source/drain region 35 of the driving transistor TRD is connected to a wire 38 (corresponding to the power supply line PS1) and the other source/drain region 35 is connected to one electrode 37. The driving transistor TRD and the capacitor C1 are covered with an interlayer insulating layer 40 and a light-emitting portion ELP including an anode electrode 51, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode electrode 53 is formed on the interlayer insulating layer 40. In the drawing, the hole transport layer, the light-emitting layer, and the electron transport layer are shown as a single layer 52. A second interlayer insulating layer 54 is formed on the interlayer insulating layer 40 not provided with the light-emitting portion ELP, a transparent substrate 22 is disposed on the second interlayer insulating layer 54 and the cathode electrode 53, and light emitted from the light-emitting layer is output to the outside via the substrate 22. One electrode 37 and the anode electrode 51 are connected to each other via a contact hole formed in the interlayer insulating layer 40. The cathode electrode 53 is connected to a wire 39 (corresponding to the second power supply line PS2) formed on the extension of the gate insulating layer 32 via contact holes 56 and 55 formed in the second interlayer insulating layer 54 and the interlayer insulating layer 40.
A method of manufacturing the display apparatus 1 including the display panel 20 will be described below. First, various wires such as the scanning lines SCL, the electrodes constituting the capacitor C1, the transistors formed of a semiconductor layer, the interlayer insulating layers, the contact holes, and the like are appropriately formed on the base 21 by the use of widely-known methods. By performing film forming and patterning processes by the use of widely-known methods, the light-emitting portions ELP arranged in a matrix are formed. The periphery of the base 21 and the substrate 22 having been subjected to the above-mentioned processes are sealed and the optical sensor 120 is attached onto the substrate 22, for example, with an adhesive so as to face the dummy display element 10Dmy. Thereafter, the inside is connected to external circuits, whereby a display apparatus 1 is obtained.
A method of driving the display apparatus 1 according to Example 1 (hereinafter, also simply abbreviated as a driving method according to Example 1) will be described below. The display frame rate of the display apparatus 1 is set to FR (/sec). The display elements 10 constituting N pixels arranged in the m-th row are simultaneously driven. In other words, in N display elements 10 arranged in the first direction, the emission/non-emission times thereof are controlled in the units of rows to which the display elements belong. The scanning period of each row when line-sequentially scanning the display apparatus 1 by rows, that is, one horizontal scanning period (so-called 1H), is less than (1/FR)×(1/M) sec.
In the following description, the values of voltages or potentials are as follows. However, these values are only examples and the voltages or potentials are not limited to these values.
VSig: video signal voltage, 0 volts (gradation value 0) to 10 volts (gradation value 511)
VDmy: video signal voltage, with values corresponding to the video signals VDDmy of gradation values 100, 200, 300, 400, and 500
Vofs: reference voltage to be applied to the gate electrode (first node ND1) of a driving transistor TRD, 0 volts
VCC-H: driving voltage causing a current to flow in a light-emitting portion ELP, 20 volts
VCC-L: initializing voltage for initializing a potential of the other source/drain region (second node ND2) of a driving transistor TRD, −10 volts
Vth: threshold voltage of a driving transistor TRD, 3 volts
Vcat voltage applied to a cathode electrode of a light-emitting portion ELP, 0 volts
Vth-EL: threshold voltage of a light-emitting portion ELP, 4 volts
The operation of the (n, m)-th display element 10 will be described in detail later with reference FIGS. 22 to 29. First, the principle of the temporal variation in luminance of a display element 10 and a method of compensating for the temporal variation in luminance will be described.
As described in the BACKGROUND, a threshold voltage cancelling process is performed in period TP(2)3 and period TP(2)5 shown in FIG. 22. Then, a writing process is performed in period TP(2)7 and the drain current Ids flowing from the drain region to the source region of a driving transistor TRD flows in a light-emitting portion ELP period TP(2)8, whereby the light-emitting portion ELP emits light. The drain current Ids flowing in the light-emitting portion ELP of the (n, m)-th display element 10 can be expressed by Expression 5.

Ids=k·μ·(Vsig—m−VOfs−ΔV)2  (5)

In Expression 5, “VSig—m,” represents the video signal voltage VSig(n,m) of the (n, m)-th display element 10 and “ΔV” represents a potential increment ΔV (potential correction value) of the second node ND2. The potential correction value ΔV will be described in detail later with reference to FIG. 28B.
For purposes of ease of explanation, it is assumed that the value of “ΔV” is sufficiently smaller than VSig—m. As described above, since VOfs is 0 volts, Expression 5 can be modified to Expression 5′.

Ids=k·μ·VSig—m2  (5′)

As can be seen from Expression 5′, the drain current Ids is proportional to the square of the value of the video signal voltage VSig(n,m). The light-emitting element 10 emits light with the luminance corresponding to the product of the emission efficiency of the light-emitting portion ELP and the value of the drain current Ids flowing in the light-emitting portion ELP. Accordingly, the value of the video signal voltage VSig is basically set to be proportional to the square root of the gradation value of the video signal VDSig.
FIG. 5A is a graph illustrating the relationship between the value of the video signal voltage in the display element in the initial state and the luminance value of the display element.
In FIG. 5A, the horizontal axis represents the value of the video signal voltage VSig. In the horizontal axis, the gradation values of the corresponding video signals VDSig are described within [ ]. The same is true of FIG. 5B to be described later. In the other drawings, the numerical value described within [ ] represents a gradation value.
When the coefficient determined depending on the emission efficiency in the initial state of the light-emitting portion ELP is defined as αIni along with the coefficients “k” and “μ”, the luminance LU can be expressed by an expression such as LU=(VDSig−ΔD)×αIni. Here, “ΔD” represents a so-called black gradation and is determined depending on the specification or design of the display apparatus 1. When VDSig<ΔD, the value of LU in the expression is negative (−) but the LU in this case is considered as “0”.
For purposes of ease of explanation, it is assumed that the value of ΔD is 0. In this case, an expression LU=VDSig×αIni is established. For example, when αIni=1.2 is assumed and an image is displayed on the basis of the video signal VDSig of a gradation value 500 in the display apparatus in the initial state, the luminance of the image is substantially 600 cd/m2. In Example 1, the maximum luminance value in the specification of the display apparatus 1 is 255×αIni.
FIG. 5B is a graph illustrating the relationship between the value of the video signal voltage in a display element in which the temporal variation occurs and the luminance value of the display element.
The display element 10 in which the temporal variation occurs is lower in luminance than that in the initial state. Specifically, as shown in FIG. 5B, the characteristic curve after the temporal variation is slower than the initial characteristic curve. As the temporal variation proceeds, the characteristic curve becomes slower.
When the coefficient determined depending on the emission efficiency after the temporal variation in the light-emitting portion ELP is defined as αTdc along with the coefficients “k” and “μ”, the luminance LU can be expressed by an expression such as LU=VDSig×αTdc. Here, αTdc<αIni is valid. In order to compensate for the temporal variation in luminance of the display element 10, the display element 10 has only to operate by multiplying the gradation value of the video signal VDSig by αIni/αTdc.
Hitherto, the principle of the method of compensating for the temporal variation in luminance of a display element 10 has been described. The temporal variation in luminance of a display element 10 depends on the histories of the luminance of an image displayed by the display apparatus 1 and the operating time. The temporal variation in luminance of a display element 10 varies depending on the display elements 10. Therefore, to compensate for a burn-in phenomenon of the display apparatus 1, it is necessary to control the gradation value of the video signal VDSig for each display element 10.
The compensation of the burn-in phenomenon in the display apparatus 1 will be schematically described with reference to FIG. 2. The reference operating time calculator 112 calculates the value of the reference operating time by multiplying the value in the operating time conversion actor holder 113 corresponding to the gradation value of the video signal VDSig by the value of a unit time. The accumulated reference operating time storage 114 stores the value obtained by accumulating the value of the reference operating time calculated by the reference operating time calculator 112. The correction value of the gradation value corresponding to each display element 10 is calculated with reference to the reference curve storage 116 on the basis of the data stored in the accumulated reference operating time storage 114. The gradation value of the input signal vDSig is corrected on the basis of the correction value of the gradation value and the corrected input signal is output as a video signal VDSig.
The compensation of the burn-in in the display apparatus 1 will be described below in detail. First, the method of calculating the reference operating time when the temperature condition is constant will be described with reference to FIGS. 6 to 11. Then, for purposes of ease of understanding of the present disclosure, the operation of a reference example in which the operating time conversion factor is not updated will be described with reference to FIGS. 12 to 17. Thereafter, the operation in an example in which the operating time conversion actor is updated will be described with reference FIGS. 2, 18, and 19.
FIG. 6 is a graph schematically illustrating the relationship between the accumulated operating time when a display element is made to operate on the basis of the video signals of various gradation values and the relative variation in luminance of the display element due to the temporal variation.
The graph shown in FIG. 6 will be described in detail. By the use of the display apparatus 1 in the initial state, first to sixth areas included in the display area are made to operate on the basis of the video signals VDSig of gradation values 50, 100, 200, 300, 400, and 500, and the length of the accumulated operating time and the ratios of the luminance after the temporal variation to the luminance in the initial state of the display elements 10 constituting the first to sixth regions are measured. The length of the accumulated operating time is plot as the value of the horizontal axis and the ratios of the luminance after the temporal variation to the luminance in the initial state of the display elements 10 divided into the first to sixth regions are plotted as the value of the vertical axis. Since it is necessary to maintain the gradation value of the video signal VDSig at the above-mentioned gradation values, the luminance correcting unit 110 shown in FIG. 1 is not made to operate, the video signals VDSig of the gradation values are generated by a particular circuit and are supplied to the signal output circuit 102, and then the measurement is performed.
The value of the vertical axis in the graph shown in FIG. 6 corresponds to the ratio of the coefficient αTdc and the coefficient αIni. As can be clearly seen from the graph, the relative variation in luminance to the luminance in the initial state increases as the gradation value of the video signal VDSig increases. Similarly, the relative variation in luminance to the luminance in the initial state increases as the accumulated operating time increases.
Therefore, the luminance variation in a display element 10 depends on the gradation value of the video signal VDSig when the display element 10 operates and the length of the operating time. The temporal variation when the display element 10 is made to operate while changing the gradation value of the video signal VDSig will be described below with reference to FIG. 7.
FIG. 7 is a graph schematically illustrating the relationship between the operating time and the relative luminance variation of the display element due to the temporal variation when the display element is made to operate while changing the gradation value of the video signal.
Specifically, the graph shown in FIG. 7 is a graph in which the length of the accumulated operating time is plotted as the value of the horizontal axis and the ratio of the luminance after the temporal variation to the luminance in the initial state of the display element 10 is plotted as the value of the vertical axis on the basis of data when the display element 10 is made to operate on the basis of the video signals VDSig of the gradation value 50 for the operating time DT1, the gradation value 100 for the operating time DT2, the gradation value 200 for the operating time DT3, the gradation value 300 for the operating time DT4, the gradation value 400 for the operating time DT5, and the gradation value 500 for the operating time DT6 by the use of the display apparatus 1 in the initial state. As described with reference to FIG. 6, the luminance correcting unit 110 shown in FIG. 1 is not made to operate, the video signals VDSig of the gradation values are generated by a particular circuit and are supplied to the signal output circuit 102, and then the measurement is performed.
In FIG. 7, reference signs PT1, PT2, PT3, PT4,'PT5, and PT6 represent the value of the accumulated operating time at that time. Time PT6 is the total sum of the lengths of the operating time DT1 to the operating time DT6.
In FIG. 7, the values of the vertical axis corresponding to PT1, PT2, PT3, PT4, PT5, and PT6 are represented by RA(PT1), RA(PT2), RA(PT3), RA(PT4), RA(PT5), and RA(PT6), respectively. In the graph shown in FIG. 7, the part from time 0 to time PT1, the part from time PT1 to time PT2, the part from PT2 to time PT3, the part from PT3 to time PT4, the part from PT4 to time PT5, and the part from PT5 to time PT6 are represented by reference signs CL1, CL2, CL3, CL4, CL5, and CL6, respectively. The graph shown in FIG. 7 can be said to be obtained by appropriately connecting the parts of the graph shown in FIG. 6.
FIG. 8 is a diagram schematically illustrating the correspondence between the graph parts represented by the reference signs CL1, CL2, CL3, CL4, CL5, and CL6 in FIG. 7 and the graph shown in FIG. 6.
As shown in FIG. 8, the graph part represented by reference sign CL1 in FIG. 7 corresponds to the part when the vertical axis in the range of 1 to RA(PT1) in the graph of the gradation value 50 in FIG. 6. The graph part represented by reference sign CL2 corresponds to the part when the vertical axis in the range of RA(PT1) to RA(PT2) in the graph of the gradation value 100 in FIG. 6. The graph part represented by reference sign CL3 corresponds to the part when the vertical axis in the range of RA(PT2) to RA(PT3) in the graph of the gradation value 200 in FIG. 6.
Similarly, the graph part represented by reference sign CL4 in FIG. 7 corresponds to the part when the vertical axis in the range of RA(PT3) to RA(PT4) in the graph of the gradation value 300 in FIG. 6. The graph part represented by reference sign CL5 corresponds to the part when the vertical axis in the range of RA(PT4) to RA(PT5) in the graph of the gradation value 400 in FIG. 6. The graph part represented by reference sign CL6 corresponds to the part when the vertical axis in the range of RA(PT5) to RA(PT6) in the graph of the gradation value 500 in FIG. 6.
On the other hand, the temporal variation in luminance of the display element 10 at time PT6 shown in FIG. 7 corresponds to the temporal variation in luminance of the display element 10 when it is assumed that the display element 10 is made to operate on the basis of the video signal VDSig of the gradation value 200 from time 0 to time PT6′. Time PT6′ represents the accumulated reference operating time when the value of the vertical axis is RA(PT6) in the graph of the gradation value 200 shown in FIG. 6.
Therefore, when the value of time PT6′ (the accumulated reference operating time) can be calculated on the basis of the operation history shown in FIG. 7, the temporal variation in luminance of the display element 10 at time PT6 shown in FIG. 7 can be calculated on the basis of the value of time PT6′ and the curve of the gradation 200 shown in FIG. 6.
The accumulated reference operating time PT6′ can be calculated on the basis of the lengths of the operating times DT1 to DT6 shown in FIG. 7 and a predetermined coefficient (the operating time conversion factor) in which the gradation value of the video signal VDSig is reflected. The operating time conversion coefficient will be described below with reference to FIGS. 9 to 11.
FIG. 9 is a graph schematically illustrating the relationship between the accumulated operating time and the gradation value of the video signal VDSig until the relative luminance variation of the display element 10 due to the temporal variation reaches a certain value “β” by causing the display element 10 to operate on the basis of the video signal VDSig. The graphs corresponding to the gradation values are the same as the graphs shown in FIG. 6. In addition, 1>β>0 is satisfied.
In FIG. 9, reference sign ETt1—500 represents the accumulated operating time when the value of the vertical axis is “β” at the gradation value 500 and reference sign ETt1—400 represents the accumulated operating time when the value of the vertical axis is “β” at the gradation value 400. The same is true of reference signs ETt1—300, ETt1—200, ETt1—100, and ETt1—50.
The mutual ratio of the accumulated operating times ETt1—500, ETt1—400, ETt1—300, ETt1—200, ETt1—100, ETt1—50 is substantially constant regardless of the value of “β”. Conversely, it is considered that the display element 10 varies with ages so as to satisfy such a condition.
FIG. 10 is a graph schematically illustrating the method of converting the operating time when a display element 10 is made to operate on the basis of the operation history shown in FIG. 7 into the reference operating time when it is assumed that the display element is made to operate on the basis of the video signal of a predetermined reference gradation value, that is, the gradation value 200.
The reference operating times DT1′, DT2′, DT3′, DT4′, DT5′, and DT6′ shown in FIG. 10 correspond to the values into which the operating times DT1, DT2, DT3, DT4, DT5, and DT6 shown in FIG. 7 are converted.
For example, the reference operating time DT1′ can be calculated by DT1′=DT1·(ETt1—200/ETt1—50). (ETt1—200/ETt1—50) corresponds to the operating time conversion factor at the gradation value 50.
Similarly, the reference operating time DT2′ can be calculated by DT2′=DT2·(ETt1—200/ETt1—100). (ETt1—200/ETt1—100) corresponds to the operating time conversion factor at the gradation value 100.
The reference operating times DT3′, DT4′, DT5′ and DT6′ can be calculated in the same way as described above.
That is, the reference operating times DT3′, DT4′, DT5′, and DT6′ can be calculated by DT3·(ETt1—200/ETt1—200), DT4·(ETt1—200/ETt1—300), DT5·(ETt1—200/ETt1—400) and DT6·(ETt1—200/ETt1—500) respectively. The operating time conversion factors at the gradation values 200, 300, 400, and 500 are given as (ETt1—200/ETt1—200), (ETt1—200, ETt1—300), and (ETt1—200/ETt1—400), (ETt1—200/ETt1—500). The accumulated reference operating time PT6′ can be calculated as the total sum of DT1′, DT2′, DT3′, DT4′, DT5′ and DT6′.
The operating time conversion factor varies depending on the gradation value. FIG. 11 is a graph illustrating the relationship between the gradation value of the video signal and the operating time conversion factor.
As described above, the reference operating time can be calculated by multiplying the actual operating time by the operating time conversion factor.
For purposes of ease of understanding of the present disclosure, the operation of a reference example in which the operating time conversion factor is not updated will be described below with reference to FIGS. 12 to 17.
FIG. 12 is a block diagram schematically illustrating the configuration of a luminance correcting unit used in the reference example.
The configuration of the luminance correcting unit 110′ shown in FIG. 12 is the same as the luminance correcting unit 110 shown in FIG. 2, except that an operating time conversion coefficient holder 113′ does not include the operating time conversion factor updating section and the table stored in the operating time conversion factor storage 113A′ is not updated.
FIG. 13 is a graph schematically illustrating data stored in the reference curve storage.
The reference curve storage 116 shown in FIG. 2 or 12 stores the functions fREF representing the reference curve shown in FIG. 13 as a table in advance. This reference curve indicates the curve at the gradation value 200 in FIG. 9.
FIG. 14 is a graph schematically illustrating the data stored in the operating time conversion factor holder.
The operating time conversion factor holder 113′ shown in FIG. 12 stores the functions fCSC representing the relationship shown in FIG. 14 as a table in advance. This indicates the relationship between the gradation value of the video signal VDSig and the operating time conversion factor, which is shown in FIG. 11.
FIG. 15 is a diagram schematically illustrating data stored in the accumulated reference operating time storage.
The accumulated reference operating time storage 114 shown in FIG. 2 or 12 includes the memory areas corresponding to the display elements 10, is constructed by a rewritable nonvolatile memory device, and stores data SP(1, 1) to SP(N, M) indicating the accumulated reference operating time and being shown in FIG. 15. Although not necessary for the operation in the reference example, the accumulated reference operating time storage 114 stores data AP indicating the accumulated operating time of the dummy display elements 10Dmy.
FIG. 17 is a diagram schematically illustrating data stored in the gradation correction value storage of the gradation correction value holder.
The gradation correction value storage 115B shown in FIG. 2 or 12 includes memory areas corresponding to the display elements 10, is constructed by a rewritable memory device, and stores data LC(1, 1) to LC(N, M) indicating the correction values of the gradation values and being shown in FIG. 17.
The driving method according to the reference example includes a luminance correcting step of correcting the luminance of the display elements 10 when displaying an image on the display panel 20 by correcting the gradation value of the input signal vDSig on the basis of the operation of the luminance correcting unit 110′ and outputting the corrected input signal as the video signal VDSig, and the luminance correcting step includes: a reference operating time calculating step of calculating the value of a reference operating time in which the temporal variation in luminance of each display element 10 when the corresponding display element 10 operates for a predetermined unit time on the basis of the video signal VDSig is equal to the temporal variation in luminance of each display element 10 when it is assumed that the corresponding display element 10 operates on the basis of the video signal VDSig of a predetermined reference gradation value; an accumulated reference operating time storing step of storing an accumulated reference operating time obtained by accumulating the calculated value of the reference operating time for each display element 10; a gradation correction value holding step of calculating a correction value of a gradation value used to compensate for the temporal variation in luminance of each display element 10 with reference to a reference curve representing the relationship between the operating time of each display element 10 and the temporal variation in luminance of the corresponding display element 10 when the corresponding display element 10 operates on the basis of the video signal VDSig of a predetermined reference gradation value under the predetermined temperature condition on the basis of the accumulated reference operating time and holding the correction value of the gradation value corresponding to the respective display elements 10; and a video signal generating step of correcting the gradation value of the input signal vDSig corresponding to the respective display element on the basis of the correction values of the gradation values and outputting the corrected input signal as the video signal VDSig.
Here, in the display apparatus 1 in which the luminance correcting unit 110 is replaced with the luminance correcting unit 110′, the luminance correcting step for the (n, m)-th display element 10 when the display of the first to (Q−1)-th frames is ended cumulatively from the initial state of the display apparatus 1 and the writing process of displaying the Q-th (where Q is a natural number equal to or greater than 2) frame is performed will be described below.
The input signal vDSig and the video signal VDSig in the q-th frame (where q=1, 2, . . . , Q) of the (n, m)-th display element 10 are represented by vDSig(n, m)—q and VDSig(n, m)—q. When the q-th frame is displayed, the data representing the accumulated reference operating time corresponding to the (n, m)-th display element 10 is expressed by SP (n, m)—q. As described above, the time occupied by a so-called one frame period is represented by reference sign TF. In the initial state, “0” as an initial value is stored in advance in data SP (1, 1) to SP (N, M) and data AP and “1” as an initial value is stored in advance in data LC (1, 1) to LC (N, M).
In the (Q−1)-th display frame, the reference operating time calculator 112 shown in FIG. 2 performs the reference operating time calculating step on the basis of the video signal VDSig(n, m)—Q−1.
Specifically, the reference operating time calculator 112 calculates the function value fCSC (VDSig(n, m)—Q−1) with reference to the operating time conversion factor storage 113 on the basis of the video signal VDSig(n, m)—Q−1. The calculation of the reference operating time=TF·fTAC(WPT—Q−1)·fCSC (VDSig(n, m)—Q−1) is performed for the (Q−1)-th display frame.
The accumulated reference operating time storage 114 performs the accumulated reference operating time storing step of storing the accumulated reference operating time which is obtained by accumulating the reference operating time calculated by the reference operating time calculator 112 for each display element 10.
Specifically, in the (Q−1)-th display frame, the accumulated reference operating time storage 114 adds the reference operating time in the (Q−1)-th display frame to the previous data SP(n, m)—Q−2. Specifically, the calculation of SP(n, m)—Q−1=SP(n, m)—Q−2+TF·fCSC(VDSig(n, m)—Q−1) is performed. Accordingly, the accumulated reference operating time which is obtained by accumulating the reference operating time calculated by the reference operating time calculator 112 for each display element 10 is stored in the accumulated reference operating time storage 114.
Although not necessary for the operation in the reference example, the accumulated reference operating time storage 114 stores data AP indicating the accumulated operating time of the dummy display elements 10Dmy. Specifically, the calculation of AP—Q−1=AP—Q−2+TF is calculated. The data AP indicates the actual value of the accumulated operating time of the display apparatus 1.
The gradation correction value holder 115 performs the gradation correction value storing step of storing the correction value of the gradation value corresponding to each display element 10.
FIG. 16 is a graph schematically illustrating the operation of the gradation correction value calculator 115A of the gradation correction value holder 115.
Specifically, the gradation correction value calculator 115A calculates the function value fREF(SP(n, m)—Q−1) with reference to the reference curve storage 116 (see FIG. 16) on the basis of the data SP(n, m)—Q−1 stored in the accumulated reference operating time storage 114. The reciprocal of the function value fREF(SP(n, m)—Q−1) is stored as the correction value of the gradation value in the data LC(n, m)—Q−1 of the gradation correction value storage 115B.
The video signal generator 111 performs the video signal generating step of correcting the gradation value of the input signal vDSig corresponding to each display element 10 on the basis of the correction value of the gradation value and outputting the corrected input signal as the video signal VDSig.
That is, just before the Q-th frame, the accumulated reference operating time storage 114 stores data SP(1,1)—Q−1 to SP(N, M)—Q−1 and the gradation correction value storage 115B of the gradation correction value holder 115 stores data LC (1, 1)—Q−1 to LC(N, M)—Q−1.
The video signal generator 111 performs the calculation of the video signal VDSig(n, m)—Q=VDSig(n, m)—Q·LC(n, m)—Q−1 with reference to the input signal vDSig(n, m)—Q and the data LC (n, m)—Q−1 in the gradation correction value storage 115B and supplies the generated video signal VDSig(n, m)—Q to the signal output circuit 102.
Then, the Q-th frame display is performed. Thereafter, the above-mentioned operation is repeatedly performed in the (Q+1)-th frame or the frames subsequent thereto.
In the driving method according to the reference example, the reference operating time is calculated with reference to the operating time conversion factor holder 113, the calculated value is stored as the accumulated reference operating time, and the correction value of the gradation value is calculated with reference to the reference curve storage 116 on the basis of the accumulated reference operating time. The gradation value of the video signal VDSig is reflected in the reference operating time.
Therefore, the history of the gradation value of the video signal VDSig is reflected in the accumulated reference operating time in which the value of the reference operating time is accumulated. Accordingly, it is possible to compensate for the variation in luminance due to the temporal variation.
The operation in the reference example in which the operating time conversion factor is not updated has been described hitherto.
In practice, the display panels 20 are not even in the operating time conversion factor. When the operating time conversion factor stored in advance in the operating time conversion factor storage 113A′ is different from the actual operating time conversion factor indicated by the display panel 20, the precision in compensating for the variation in luminance decreases. In the operation in Example 1, since the operating time conversion factor is updated on the basis of the variation in luminance of the dummy display elements 10Dmy, it is possible to compensate for the variation in luminance to cope with the unevenness by the display panels 20. The operation when the operating time conversion factor is updated will be described below.
The operating time conversion factor updating section 113B shown in FIG. 2 updates the operating time conversion factor every predetermined time. That is, the operating time conversion factor updating section 113B acquires the luminance information of the dummy display elements 10Dmy from the optical sensor 120 with reference to the data AP of the accumulated reference operating time storage 114 whenever the value of the data AP increases, for example, by one hour. The operating time conversion factor updating section 113B updates the operating time conversion factor by comparing the value of the reference curve with the measured value of the dummy display elements 10Dmy.
In Example 1, the operating time conversion factor updating section 113B updates the value of the operating time conversion factor by comparing the operating time and the temporal variation in luminance of the plural dummy display elements 10Dmy operating on the basis of different gradation values with the values of the reference curve fREF.
FIG. 18 is a graph schematically illustrating the method of comparing the measured values of the dummy display elements with the values of the reference curve.
The comparison of the measured values of the dummy display elements 10Dmy with the values of the reference curve will be described below in detail. When the value of the data AP reaches a certain value APT at which the updating operation should be performed, the operating time conversion factor updating section 113B calculates the ratio of the luminance value to the luminance value of the initial state of the dummy display element 10Dmy on the basis of the luminance information from the optical sensor 120. This ratio corresponds to the above-mentioned αTdc/αIni. In FIG. 18, the ratios of the dummy display element 10Dmy operating on the basis of the video signal VDDmy of the gradation values 100, 200, 300, 400, and 500 are represented by reference signs βAPT—100, βAPT—200, βAPT—300, βAPT—400, and βAPT—500.
The operating time conversion factor updating section 113B compares the reference curve fREF stored in the reference curve storage 116 with the values of βAPT—100, βAPT—200, βAPT—300, βAPT—400, and βAPT—500 and calculates the values of the horizontal axis of the reference curve fREF when the value of the vertical axis is βAPT—100, βAPT—200, βAPT—300, βAPT—400, and βAPT—500. The values of the horizontal axis corresponding to the values of βAPT—100, βAPT—200, βAPT—300, βAPT—400, and βAPT—500 are represented by reference signs ETAPT—100, ETAPT—200, ETAPT—300, ETAPT—400 and ETAPT—500.
FIG. 18 shows an example where the temporal variation of the dummy display element 10Dmy operating at the gradation value 200 is slower than the reference curve fREF. In this case, the temporal variation in luminance of the display panel 20 is slower than assumed. The operating time conversion factor updating section 113B updates the value so as to reduce the operating time conversion factor.
Specifically, the operating time conversion factor updating section 113B calculates the values of ETAPT—100/APT, ETAPT—200/APT, ETAPT—300/APT, ETAPT—400/APT, and ETAPT—500/APT. These values are set as new operating time conversion factors at the gradation values 100, 200, 300, 400, and 500 and are interpolated to determine a nes function fCSC—APT. By storing the function fCSC—APT in the operating time conversion factor storage 113A, the operating time conversion factors are updated. FIG. 19 is a graph schematically illustrating the updated data stored in the operating time conversion factor holder.
In Example 1, since the operating time conversion factors are updated on the basis of the temporal variation of the dummy display elements 10Dmy, it is possible to compensate for the temporal variation depending on the individual difference of the display panels 20. Therefore, it is possible to perform a control with higher precision.
It has been stated above that the display apparatus 1 is a monochrome display apparatus, but a color display apparatus may be used. In this case, for example, when the tendency of the temporal variation of a display element 10 varies depending on emission colors, the operating time conversion factor holder 113 and the reference curve storage 116 shown in FIG. 2 have only to be individually provided for each emission color. The dummy display elements 10Dmy and the optical sensor have only to be individually provided for each emission color.
The compensation of the burn-in in the display apparatus 1 has been described in detail above. The details of the operation except for the burn-in compensation of the (n, m)-th display element 10 are similar in Example 1 and Example 2 to be described later. For purposes of ease of explanation, the operation other than the burn-in compensation of the (n, m)-th display element 10 will be described in detail in the second half of Expression 2.
EXAMPLE 2
Example 2 also relates to a display apparatus and a display apparatus driving method according to the embodiment of the present disclosure.
In Example 1, the operating time conversion factors are updated on the basis of the luminance information of the dummy display elements 10Dmy operating on the basis of the video signals of different gradation values. On the contrary, in Example 2, the operating time conversion factor is updated on the basis of the luminance information of the dummy display elements 10Dmy operating on the basis of a video signal of a single gradation value.
The configuration of the display apparatus according to Example 2 is basically the same as the configuration of the display apparatus 1 according to Example 1. Accordingly, the conceptual diagram of the display apparatus or the conceptual diagram of the luminance correcting unit will not be shown. The driving method according to Example 2 is equal to the driving method according to Example 1, except that the method of updating the operating time conversion actor is different. Therefore, the description will be centered on the method of updating the operating time conversion factor.
As shown in FIG. 19 which is referred to in Example 1, the updated function fCSC—APT indicates a curve obtained by changing the values of the function fCSC at a constant ratio. Therefore, in Example 2, the operating time conversion factor is updated by calculating the value of the operating time conversion factor in the luminance on the basis of the luminance information of the dummy display elements 10Dmy operating on the basis of a video signal VDDmy of a single gradation value and applying a predetermined coefficient to the function fCSC depending on the calculated value.
FIG. 20 is a graph schematically illustrating the method of comparing the measured values of the dummy display elements with the values of the reference curve.
In Example 2, the operating time conversion factor updating section 113B compares the values of reference signs RAPT 200 obtained on the basis of the luminance information of the dummy display elements 10Dmy operating at the gradation value 200 with the reference curve fREF stored in the reference curve storage 116 and calculates the value of the horizontal axis ETAPT—200 when the value of the vertical axis is βAPT—200.
When the value of the function fCSC at the gradation value 200 is defined as fCSC(200), the operating time conversion actor is updated by setting the function fCSC—APT to (ETAPT—200/APT)/fCSC(200)·fCSC and storing the function fCSC—APT in the operating time conversion factor storage 113A. FIG. 21 is a graph schematically illustrating the updated data stored in the operating time conversion factor storage.
In Example 2, since the operating time conversion factor is updated on the basis of the luminance information of the dummy display elements 10Dmy operating on the basis of a video signal VDDmy of a single gradation value, it is possible to simplify the updating control, compared with Example 1.
The display apparatus according to Example 2 may be a color display apparatus. In this case, for example, when the tendency of the temporal variation of a display element 10 varies depending on emission colors, the operating time conversion factor holder 113 and the reference curve storage 116 shown in FIG. 2 have only to be individually provided for each emission color. The dummy display elements 10Dmy and the optical sensor have only to be individually provided for each emission color.
The details of the operation except for the burn-in compensation of the (n, m)-th display element 10 will be described below with reference to FIG. 22, FIGS. 24A and 24B, FIGS. 25A and 25B, FIGS. 26A and 26B, FIGS. 27A and 27B, FIGS. 28A and 28B, and FIG. 29. FIG. 23 is a timing diagram schematically illustrating the operation of the dummy display element. The detailed operation of the dummy display element 10Dmy will not be described, since the following description can be appropriately replaced. In the drawings or the following description, for purposes of ease of explanation, the video signal voltage VSig(n, m) corresponding to the (n, m)-th display element 10 is defined as VSig—m.
[Period TP(2)−1] (see FIGS. 22 and 24A)
Period TP(2)−1 indicates, for example, the operation in the previous display frame and is a period of time in which the (n, m)-th display element 10 is in an emission state after the previous processes are ended. That is, a drain current Ids′ based on Expression 5′ flows in the light-emitting portion ELP of the display element 10 of the (n, m)-th pixel and the luminance of the display element 10 of the (n, m)-th pixel has a value corresponding to the drain current Ids′. Here, the writing transistor TRW is in the OFF state and the driving transistor TRD is in the ON state. The emission state of the (n, m)-th display element 10 is maintained just before the horizontal scanning period of the display elements 10 in the (m+m′)-th row is started.
As described above, the data line DTLn is supplied with the reference voltage VOfs and the video signal voltage VSig to correspond to the respective horizontal scanning periods. However, the writing transistor TRW is in the OFF state. Accordingly, even when the potential (voltage) of the data line DTLin varies in period TP(2)−1, the potentials of the first node ND1 and the second node ND2 do not vary (a potential variation due to the capacitive coupling of a parasitic capacitor or the like may be caused in practice but can be neglected in general). The same is true in period TP(2)0.
Periods TP(2)0 to TP(2)6 shown in FIG. 22 are operation periods just before the next writing process is performed after the previous processes are ended and the emission state is then ended. In periods TP(2)0 to TP(2)7, the (n, m)-th display element 10 is basically in the non-emission state. As shown in FIG. 22, period TP(2)5, period TP(2)6, and period TP(2)7 are included the m-th horizontal scanning period Hm.
In Periods TP(2)3 and TP(2)5, in a state where the reference voltage VOfs is applied to the gate electrode of the driving transistor TRD from the data line DTLn via the writing transistor TRW turned on by the scanning signal from the scanning line SCL, the threshold voltage cancelling process of applying the driving voltage VCC-H to the other source/drain region of the driving transistor TRD from the power supply line PS1 and thus causing the potential of the other source/drain region of the driving transistor TRD to get close to the potential obtained by subtracting the threshold voltage of the driving transistor TRD from the reference voltage VOfs is performed.
In the following description, it is stated that the threshold voltage cancelling process is performed in plural horizontal scanning periods, that is, in the (m−1)-th horizontal scanning period and the m-th horizontal scanning period Hm, which does not limit the present disclosure.
In period TP(2)1, the initializing voltage VCC-L of which the difference from the reference voltage VOfs is greater than the threshold voltage of the driving transistor TRD is applied to one source/drain region of the driving transistor from the power supply line PS1 and the reference voltage VOfs is applied to the gate electrode of the driving transistor TRD from the data line DTLn via the writing transistor TRW turned on by the scanning signal from the scanning line SCLm, whereby the potential of the gate electrode of the driving transistor TRD and the potential of the other source/drain region of the driving transistor TRD are initialized.
In FIG. 22, it is assumed that period TP(2)1 corresponds to a reference voltage period (a period in which the reference voltage VOfs is applied to the data line DTL) in the (m−2)-th horizontal scanning period Hm−2, period TP(2)3 corresponds to the reference voltage period in the (m−1)-th horizontal scanning period and period TP(2)5 corresponds to the reference voltage period in the m-th horizontal scanning period Hm.
The operations in periods TP(2)0 to period TP(2)8 will be described below with reference to FIG. 22 and the like.
[Period TP(2)0] (see FIGS. 22 and 24B)
The operation in period TP(2)0 is an operation, for example, from the previous display frame to the present display frame. That is, period TP(2)0 is a period from the start of the (m+m′)-th horizontal scanning period Hm+m′ in the previous display frame to the end of the (m−3)-th horizontal scanning period in the present display frame. In period TP(2)0, the (n, m)-th display element 10 is in the non-emission state. At the start of period TP(2)0, the voltage supplied from the power supply unit 100 to the power supply line PS1m is changed from the driving voltage VCC-H to the initializing voltage VCC-L. As a result, the potential of the second node ND2 is lower to VCC-L and a backward voltage is applied across the anode electrode and the cathode electrode of the light-emitting portion ELP, whereby the light-emitting portion ELP is changed to the non-emission state. The potential of the first node ND1 (the gate electrode of the driving transistor TRD) in a floating state is lowered to follow the lowering in potential of the second node ND2.
[Period TP(2)1] (see FIGS. 22 and 25A)
The (m−2)-th horizontal scanning period Hm−2 in the present display frame is started. In period TP(2)1, the scanning line SCLm is changed to a high level and the writing transistor TRW of the display element 10 is changed to the ON state. The voltage supplied from the main signal output circuit 102 to the data line DTLn is the reference voltage VOfs. As a result, the potential of the first node ND1 is VOfs (0 volts). Since the initializing voltage VCC-L is applied to the second node ND2 from the power supply line PS1m by the operation of the power supply unit 100, the potential of the second node ND2 is kept at VCC-L (−10 volts).
Since the potential difference between the first node ND1 and the second node ND2 is 10 volts and the threshold voltage Vth of the driving transistor TRD is 3 volts, the driving transistor TRD is in the ON state. The potential difference between the second node ND2 and the cathode electrode of the light-emitting portion ELP is −10 volts, which is not greater than the threshold voltage Vth-EL of the light-emitting portion ELP. Accordingly, the potential of the first node ND1 and the potential of the second node ND2 are initialized.
[Period TP(2)2] (see FIGS. 22 and 25B)
In period TP(2)2, the scanning line SCLm is changed to a low level. The writing transistor TRW of the display element 10 is changed to the OFF state. The potentials of the first node ND1 and the second node ND2 are basically maintained in the previous state.
[Period TP(2)3] (see FIGS. 22 and 26A)
In period TP(2)3, the first threshold voltage cancelling process is performed. The scanning line SCLm is changed to a high level to turn on the writing transistor TRW of the display element 10. The voltage supplied from the main signal output circuit 102 to the data line DTLn is the reference voltage VOFs. The potential of the first node ND1 is VOfs (0 volts).
The voltage supplied from the power supply unit 100 to the power supply line PS1m is switched to the voltage VCC-L to the driving voltage VCC-H. As a result, the potential of the first node ND1 is not changed (VOfs=0 is maintained) but the potential of the second node ND2 is changed to the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the reference voltage VOfs. That is, the potential of the second node ND2 is raised.
When period TP(2)3 is sufficiently long, the potential difference between the gate electrode and the other source/drain region of the driving transistor TRD reaches Vth and the driving transistor TRD is changed to the OFF state. That is, the potential of the second node ND2 gets close to (VOfs−Vth) and finally becomes (VOfs−Vth). In the example shown in FIG. 22, the length of period TP(2)3 is insufficient to change the potential of the second node ND2 and the potential of the second node ND2 reaches a certain potential V1 satisfying the relation of VCC-L<V1<(VOfs−Vth) at the end of period TP(2)3.
[Period TP(2)4] (see FIGS. 22 and 26B)
In period TP(2)4, the scanning line SCLm is changed to the low level to turn off the writing transistor TRW of the display element 10. As a result, the first node ND1 is in the floating state.
Since the driving voltage VCC-H is applied to one source/drain region of the driving transistor TRD from the power supply unit 100, the potential of the second node ND2 rises from the potential V1 to a certain potential V2. On the other hand, since the gate electrode of the driving transistor TRD is in the floating state and the capacitor C1 is present, a bootstrap operation occurs in the gate electrode of the driving transistor TRD. Accordingly, the potential of the first node ND1 rises to follow the potential variation of the second node ND2.
As the premise of the operation in period TP(2)5, the potential of the second node ND2 should be lower than (VOfs−Vth) at the start of period TP(2)5. The length of period TP(2)4 is basically determined so as to satisfy the condition of V2<(VOfs−Vth).
[Period TP(2)5] (see FIG. 22 and FIGS. 27A and 27B)
In period TP(2)5, the second threshold voltage cancelling process is performed. The writing transistor TRW of the display element 10 is turned on by the scanning signal from the scanning line SCLm. The voltage supplied from the signal output circuit 102 to the data line DLTn is the reference voltage VOfs. The potential of the first node ND1 is returned again to VOfs (0 volts) from the potential rising due to the bootstrap operation (see FIG. 27A).
Here, the value of the capacitor C1 is represented by c1 and the value of the capacitor CEL of the light-emitting portion ELP is represented by CEL. The value of the parasitic capacitor between the gate electrode of the driving transistor TRD and the other source/drain region is represented by cgs. When the capacitance between the first node ND1 and the second node ND2 is represented by reference sign cA, cA=c1+cgs is established. When the capacitance between the second node ND2 and the second power supply line PS2 is represented by reference sign cB, cB=cED is established. An additional capacitor may be connected in parallel to both ends of the light-emitting portion ELP, but in this case, the capacitance of the additional capacitor is added to the c2.
When the potential of the first node ND1 varies, the potential difference between the first node ND1 and the second node ND2 varies. That is, charges based on the potential variation of the first node ND1 are distributed on the basis of the capacitance between the first node ND1 and the second node ND2 and the capacitance between the second node ND2 and the second power supply line PS2. However, when the value cb (=cEL) is sufficiently larger than the value cA (=c1+cgs), the potential variation of the second node ND2 is small. In general, the value cEL of the capacitor CEL of the light-emitting portion ELP is larger than the value c1 of the capacitor C1 and the value cgs of the parasitic capacitor of the driving transistor TRD. In the following description, the potential variation of the second node ND2 caused by the potential variation of the first node ND1 is not considered. In the driving timing diagram shown in FIG. 22, the potential variation of the second node ND2 caused by the potential variation of the first node ND1 is not considered.
Since the driving voltage VCC-H is applied to one source/drain region of the driving transistor TRD from the power supply unit 100, the potential of the second node ND2 varies to the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the reference voltage VOfs.That is, the potential of the second node ND2 rises from the potential V2 and varies to the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the reference voltage VOFs. When the potential difference between the gate electrode of the driving transistor TRD and the other source/drain region reaches Vth, the driving transistor TRD is turned off (see FIG. 27B). In this state, the potential of the second node ND2 is approximately (VOfs−Vth). Here, when. Expression 2 is guaranteed, that is, when the potential is selected and determined to satisfy Expression 2, the light-emitting portion ELP does not emit light.

(VOfs−Vth)<(Vth-EL+VCat)  (2)

In period TP(2)5, the potential of the second node ND2 finally reaches (VOfs-Vth). That is, the potential of the second node ND2 is determined depending on only the threshold voltage Vth of the driving transistor TRD and the reference voltage VOfs. The potential of the second node is independent of the threshold voltage Vth-EL of the light-emitting portion ELP. At the end of period TP(2)5, the writing transistor TRW is changed from the ON state to the OFF state on the basis of the scanning signal from the scanning line SCLm.
[Period TP(2)6] (see FIGS. 22 and 28A)
In the state where the writing transistor TRW is maintained in the OFF state, the video signal voltage VSig—m instead of the reference voltage VOfs is supplied to an end of the data line DTLn from the signal output circuit 102. When the driving transistor TRD is in the OFF state in period TP(2)5r the potentials of the first node ND1 and the second node ND2 do not vary in practice (a potential variation due to the capacitive coupling of a parasitic capacitor or the like may be caused in practice but can be neglected in general). When the driving transistor TRD does not reach the OFF state in the threshold voltage cancelling process performed in period TP(2)5, the bootstrap operation is caused in period TP(2)6 and thus the potentials of the first node ND1 and the second node ND2 slightly rise.
[Period TP(2)7] (see FIGS. 22 and 28B)
In period TP(2)7, the writing transistor TRW of the display element 10 is changed to the ON state by the scanning signal from the scanning line SCLm. The video signal voltage VSig—m is applied to the gate electrode of the writing transistor TRW from the driving transistor DTLn.
In the above-mentioned writing process, in the state where the driving voltage VCC-H is applied to one source/drain region of the driving transistor TRD from the power supply unit 100, the video signal voltage VSig is applied to the gate electrode of the driving transistor TRD. Accordingly, as shown in FIG. 22, the potential of the second node ND2 in the display element 10 varies in period TP(2)7. Specifically, the potential of the second node ND2 rises. The increment of the potential is represented by reference sign ΔV.
When the potential of the gate electrode (the first node ND1) of the driving transistor TRD is represented by Vg and the potential of the other source/drain region (the second node ND2) of the driving transistor TRD is represented by Vs, the value of Vg and the value of Vs are as follows without considering the rising of the potential of the second node ND2. The potential difference between the first node ND1 and the second node ND2, that is, the potential difference Vgs between the gate electrode of the driving transistor TRD and the other source/drain region serving as a source region can be expressed by Expression 3.

Vg=VSig—m 

Vs≈VOfs−Vth 

Vgs≈VSig—m−(VOfs−Vth)  (3)

That is, Vgs obtained in the writing process on the driving transistor TRD depends on only the video signal voltage VSig—m used to control the luminance of the light-emitting portion ELP, the threshold voltage Vth of the driving transistor TRD, and the reference voltage VOfs. Vgs is independent of the threshold voltage Vth-EL of the light-emitting portion ELP.
The increment (ΔV) of the potential of the second node ND2 will be described below. In the driving method according to Example 1 or Example 2, the writing process is performed in the state where the driving voltage VCC-H is applied to one source/drain region of the driving transistor TRD of the display element 10. Accordingly, a mobility correcting process of changing the potential of the other source/drain region of the driving transistor TRD of the display element 10 is performed together.
When the driving transistor TRD is constructed by a thin film transistor or the like, it is difficult to avoid the unevenness in mobility μ between transistors. Accordingly, even when the video signal voltages VSig having the same value are applied to the gate electrodes of plural driving transistors TRD having the unevenness in mobility μ, the drain current Ids flowing in a driving transistor TRD having large mobility μ and the drain current Ids flowing in a driving transistor TRD having small mobility μ have a difference. When such a difference occurs, the screen uniformity of the display apparatus 1 is damaged.
In the above-mentioned driving method, the video signal voltage VSig is applied to the gate electrode of the driving transistor TRD in the state where one source/drain region of the driving transistor TRD is supplied with the driving voltage Vec-H from the power supply unit 100. Accordingly, as shown in FIG. 22, the potential of the second node ND2 rises in the writing process. When the mobility μ of the driving transistor TRD is great, the increment ΔV (potential correction value) of the potential (that is, the potential of the second node ND2) in the other source/drain region of the driving transistor TRD increases. Conversely, when the value of the mobility μ of the driving transistor TRD is small, the increment ΔV of the potential in the other source/drain region of the driving transistor TRD decreases. Here, the potential difference Vgs between the gate electrode of the driving transistor TRD and the other source/drain region serving as a source region is modified from Expression 3 to Expression 4.

Vgs≈VSig—m−(VOfs−Vth)−ΔV  (4)

The length of the scanning signal period in which the video signal voltage VSig is written can be determined depending on the design of the display element 10 or the display apparatus 1. It is assumed that the length of the scanning signal period is determined so that the potential (VOfs−Vth+ΔV) in the other source/drain region of the driving transistor TRD at that time satisfies Expression 2′.
In the display element 10, the light-emitting portion ELP does not emit light in period TP(2)7. By this mobility correcting process, the deviation of the coefficient k (≡(1⁄2)·(W/L)−Cox) is simultaneously performed.

(VOfs−Vth+ΔV)<(Vth-EL+VCat)  (2′)

[Period TP(2)8] (see FIGS. 22 and 29)

The state where one source/drain region of the driving transistor TRD is supplied with the driving voltage VCC-H from the power supply unit 100 is maintained. In the display apparatus 10, the voltage corresponding to the video signal voltage VSig—m is stored in the capacitor C1 by the writing process. Since the supply of the scanning signal from the scanning line is ended, the writing transistor TRW is turned off. Accordingly, by stopping the application of the video signal voltage VSig—m, to the gate electrode of the driving transistor TRD, a current corresponding to the value of the voltage stored in the capacitor C1 by the writing process flows in the light-emitting portion ELP via the driving transistor TRD, whereby the light-emitting portion ELP emits light.
The operation of the display element 10 will be described below in more detail. The state where the driving voltage VCC-H is applied to one source/drain region of the driving transistor TRD from the power supply unit 100 is maintained and the first node ND1 is electrically separated from the data line DLTn. Accordingly, the potential of the second node ND2 rises as a result.
As described above, since the gate electrode of the driving transistor TRD is in the floating state and the capacitor C1 is present, the same phenomenon as occurring in a so-called bootstrap circuit occurs in the gate electrode of the driving transistor TRD and the potential of the first node ND1 also rises. As a result, the potential difference Vg, between the gate electrode of the driving transistor TRD and the other source/drain region serving as a source region is maintained as the value expressed by Expression 4.
Since the potential of the second node ND2 rises and becomes greater than (Vth-EL+VCat), the light-emitting portion ELP starts its emission of light. At this time, since the current flowing in the light-emitting portion ELP is the drain current Ids flowing from the drain region to the source region of the driving transistor TRD, the current can be expressed by Expression 1. Here, In Expressions 1 and 4, Expression 1 can be modified into Expression 5.

Ids=k·μ·(VSig—m−VOfs−ΔV)2  (5)

Therefore, when the reference voltage VOfs is set to 0 volts, the current Ids flowing in the light-emitting portion ELP is proportional to the square of the value obtained by subtracting the value of the potential correction value ΔV based on the mobility μ of the driving transistor TRD from the value of the video signal voltage VSig—m used to control the luminance of the light-emitting portion ELP. In other words, the current Ids flowing in the light-emitting portion ELP does not depend on the threshold voltage Vth-EL of the light-emitting portion ELP and the threshold voltage Vth of the driving transistor TRD. That is, the emission intensity (luminance) of the light-emitting portion ELP is not affected by the threshold voltage Vth-EL of the light-emitting portion ELP and the threshold voltage Vth of the driving transistor TRD. The luminance of the (n, m)-th display element 10 has a value corresponding to the current Ids.
In addition, as the driving transistor TRD has greater mobility μ, the potential correction value ΔV increases and thus the value of the left side Vgs of Expression 4 decreases. Accordingly, in Expression 5, since the value of (VSig—m−VOfs−ΔV)2 decreases as the value of the mobility μ increases, the unevenness of the drain current Ids due to the unevenness (unevenness in k) of the mobility μ of the driving transistor TRD can be corrected. As a result, it is possible to correct the unevenness of luminance of the light-emitting portion ELP due to the unevenness (and the unevenness in k) of the mobility μ.
The emission state of the light-emitting portion ELP is maintained to the (m+m′-1)-th horizontal scanning period. The end of the (m+m′-1)-th horizontal scanning period corresponds to the end of period TP(2)−1. Here, “m′” satisfies the relation of 1<m′<M and is a value predetermined in the display apparatus 1. In other words, the light-emitting portion ELP is driven from the start of period TP(2)8 to just before the (m+m′)-th horizontal scanning period Hm+m′ and this period serves as the emission period.
While the present disclosure has been described with reference to the preferable example, the present disclosure is not limited to the example. The configuration of structure of the display apparatus, the steps of the method of manufacturing the display apparatus, and the steps of the method of driving the display apparatus, which are described herein, are only examples and can be appropriately modified.
For example, it has been stated in the examples that the driving transistor TRD is of an n-channel type. However, when the driving transistor TRD is of a p-channel type, the anode electrode and the cathode electrode of the light-emitting portion ELP have only to be exchanged. In this configuration, since the direction in which the drain current flows is changed, the value of the voltage supplied to the power supply line PS1 or the like can be appropriately changed.
As shown in FIG. 30, the driving circuit 11 of the display element 10 may include a transistor (first transistor TR1) connected to the first node ND1. In the first transistor TR1, one source/drain region is supplied with the reference voltage VOfs and the other source/drain region is connected to the first node ND1. A control signal from a first-transistor control circuit 103 is applied to the gate electrode of the first transistor TR1 via a first-transistor control line AZ1 to control the ON/OFF state of the first transistor TR1. Accordingly, it is possible to set the potential of the first node ND1.
The driving circuit 11 of the display element 10 may include another transistor in addition to the first transistor TR1. FIG. 31 shows a configuration in which a second transistor TR2 and a third transistor TR3 are additionally provided. In the second transistor TR2, one source/drain region is supplied with the initializing voltage VCC-L and the other source/drain region is connected to the second node ND2. A control signal from a second-transistor control circuit 104 is applied to the gate electrode of the second transistor TR2 via a second-transistor control line AZ2 to control the ON/OFF state of the second transistor TR2. Accordingly, it is possible to initialize the potential of the second node ND2. The third transistor TR3 is connected between one source/drain region of the driving transistor TRD and the power supply line PS1, and a control signal from a third-transistor control circuit 105 is applied to the gate electrode of the third transistor TR3 via a third-transistor control line CL.
The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-279004 filed in the Japan Patent Office on Dec. 15, 2010, the entire content of which is hereby incorporated by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

## Claims

1. A display apparatus comprising:
a display panel that includes display elements having a current-driven light-emitting portion and that displays an image on the basis of a video signal; and
a luminance correcting unit that corrects the luminance of the display elements when the display panel displays an image by correcting a gradation value of an input signal and outputting the corrected input signal as the video signal,
wherein the luminance correcting unit includes
an operating time conversion factor holder that stores as an operating time conversion factor the ratio of the values of operating times until the temporal variation in luminance reaches a certain value by causing each display element to operate on the basis of the video signal of various gradation values and the value of an operating time until the temporal variation in luminance reaches the certain value by causing each display element to operate on the basis of the video signal of a predetermined reference gradation value,
a reference operating time calculator that calculates the value of a reference operating time in which the temporal variation in luminance of each display element when the corresponding display element operates for a predetermined unit time on the basis of the video signal is equal to the temporal variation in luminance of each display element when it is assumed that the corresponding display element operates on the basis of the video signal of the predetermined reference gradation value by multiplying the value of the operating time conversion factor corresponding to the gradation value of the video signal by the value of the unit time,
an accumulated reference operating time storage that stores an accumulated reference operating time obtained by accumulating the value of the reference operating time calculated by the reference operating time calculator for each display element,
a reference curve storage that stores a reference curve representing the relationship between the operating time of each display element and the temporal variation in luminance of the corresponding display element when the corresponding display element operates on the basis of the video signal of the predetermined reference gradation value,
a gradation correction value holder that calculates a gradation correction value used to compensate for the temporal variation in luminance of each display element with reference to the accumulated reference operating time storage and the reference curve storage and that stores the gradation correction value corresponding to the respective display elements, and
a video signal generator that corrects the gradation value of the input signal corresponding to the respective display elements on the basis of the gradation correction values stored in the gradation correction value holder and that outputs the corrected input signal as the video signal,

wherein the display panel includes a dummy display element not contributing to the display of an image, and
wherein the operating time conversion factor holder includes an operating time conversion factor updating section that updates the operating time conversion factor by comparing the value of the reference curve with the operating time and the temporal variation in luminance when the dummy element operates on the basis of the video signal of a predetermined gradation value.

2. The display apparatus according to claim 1, wherein the operating time conversion factor updating section updates the operating time conversion factor every predetermined time.

3. The display apparatus according to claim 2, wherein the operating time conversion factor updating section updates the value of the operating time conversion factor by comparing the values of the reference curves with the operating times and the temporal variations in luminance of a plurality of the dummy display elements operating on the basis of different gradation values.

4. The display apparatus according to claim 2, wherein the operating time conversion factor updating section updates the value of the operating time conversion factor by comparing with the value of the reference curve with the operating time and the temporal variation in luminance of the dummy display element operating on the basis of a single gradation value.

5. The display apparatus according to claim 1, wherein the light-emitting portion is formed of an organic electroluminescence light-emitting portion.

6. A display apparatus comprising:
a display panel that includes display elements arranged therein and that displays an image on the basis of a video signal; and
a correction unit that corrects a gradation value of an input signal and that outputs the corrected input signal as the video signal,
wherein the correction unit includes
a factor holder that stores as a factor the ratio of a temporal variation in luminance of each display element at various gradation values and a temporal variation in luminance of the corresponding display element at a predetermined reference gradation value,
a calculator that calculates the value of a reference operating time on the basis of the factor corresponding to a gradation value and the value of a unit time,
a time storage that stores an accumulated reference operating time obtained by accumulating the value of the reference operating time for each display element,

a storage that stores a reference curve representing the relationship between the operating time and the temporal variation in luminance of each display element at the predetermined reference gradation value,
a correction value holder that calculates a gradation correction value on the basis of the accumulated reference operating time and the reference curve, and
a generator that corrects the gradation value of the input signal on the basis of the gradation correction value,
wherein the display panel includes a dummy display element not contributing to the display of an image, and
wherein the factor holder includes an updating section that updates the factor by comparing the reference curve with the operating time and the temporal variation in luminance of the dummy display element.

7. The display apparatus according to claim 6, wherein the updating section updates the factor by comparing the values of the reference curves with the operating times and the temporal variations in luminance of a plurality of the dummy display elements operating on the basis of different gradation values.

8. The display apparatus according to claim 6, wherein the updating section updates the value of the operating time conversion factor by comparing with the value of the reference curve with the operating time and the temporal variation in luminance of the dummy display element operating on the basis of a single gradation value.