# Patent

## Title
Method and apparatus for measuring operating characteristics in a load control device

## Abstract

A load control device, such as an electronic ballast, for controlling the power delivered from an AC power source to an electrical load, such as one or more fluorescent lamps, comprises a power converter having an inductor and a power switching device coupled to the inductor, a load control circuit adapted to be coupled to the electrical load, and a control circuit operable to calculate an average input power of the load control device. The control circuit may be operable to calculate a cumulative output power of the power converter while the ballast is preheating filaments of the lamps, and to subsequently determine a fault condition in the lamps in response to the calculated cumulative output power of the power converter. Further, the control circuit may be operable to transmit a digital message including the calculated average input power of the load control device.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of commonly-assigned U.S. patent application Ser. No. 13/212,556, filed Aug. 18, 2011, which is a non-provisional application of U.S. Provisional Application No. 61/374,792, filed Aug. 18, 2010, both entitled METHOD AND APPARATUS FOR MEASURING OPERATING CHARACTERISTICS IN A LOAD CONTROL DEVICE, the entire disclosures of which are hereby incorporated by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a load control device for controlling the amount of power delivered to an electrical load, specifically, to an electronic dimming ballast for a gas discharge lamp that is able to measure a number of operating characteristics, and to determine that a fault condition in the lamp in response to the measured operating characteristic.
2. Description of the Related Art
A load control device is operable to control the amount of power delivered from an alternating-current (AC) power source to an electrical load, such as a lighting load or a motor load. Typical load control devices include, for example, dimmer switches for lighting loads, electronic ballasts for gas discharge lamps, light-emitting diode (LED) drivers for LED light sources, and motor control devices for motor loads. Some prior art load control device have included power measurement circuits for measuring an input current of the load control device. For example, the power measurement circuit may comprise a current transformer coupled in series with a hot terminal of the load control device for sensing the input current as described in greater detail in commonly-assigned U.S. Pat. No. 6,528,957, issued Mar. 4, 2003, entitled POWER/ENERGY MANAGEMENT CONTROL SYSTEM, the entire disclosure of which is hereby incorporated by reference. Since current transformers tend to be large and expensive, some prior art lighting control devices have estimated the magnitude of the input current in dependence upon the present intensity of the controlled lighting load as described in commonly-assigned U.S. patent application Ser. No. 12/550,972, filed Aug. 31, 2009, entitled METHOD OF LOAD SHEDDING TO REDUCE THE TOTAL POWER CONSUMPTION OF A LOAD CONTROL SYSTEM, the entire disclosure of which is hereby incorporated by reference.
However, there is a need for a load control device that is more accurately able to measure operating characteristics (such as input power) without requiring a current transformer.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a load control device for controlling the power delivered from an AC power source to an electrical load comprises a power converter having an inductor and a power switching device coupled to the inductor, a load control circuit adapted to be coupled to the electrical load, and a control circuit operable to calculate an average input power of the load control device. The inductor of the power converter charges when the power switching device is conductive and to discharges when the power switching device is non-conductive. The control circuit is operatively coupled to the power switching device of the power converter for controlling the length of an on time for which the power switching device is rendered conductive to generate a DC bus voltage. The load control circuit receives the bus voltage and controls the power delivered to load. The control circuit is operatively coupled to the load control circuit for controlling the power delivered to the lamp, and receives a control signal representative of an instantaneous magnitude of an AC line voltage of the AC power source. The control circuit uses the on time, the instantaneous magnitude of the AC line voltage, and an inductance of the inductor of the power converter to calculate the average input power of the load control device.
According to another embodiment of the present invention, an electronic ballast for driving one or more gas discharge lamps from an AC power source comprises a boost converter for generating a DC bus voltage, an inverter circuit for converting the bus voltage to a high-frequency AC voltage, a resonant tank for coupling the high-frequency AC voltage to the lamps, and a control circuit operable to calculate a cumulative output power of the boost converter while the ballast is preheating filaments of the lamps, and to subsequently determine a fault condition in the lamps. The boost converter comprises an inductor and a power switching device coupled to the inductor, such that the inductor is operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive. The control circuit is operatively coupled to the power switching device of the boost converter for controlling the length of an on time for which the power switching device is controlled to be conducive. The control circuit is operatively coupled to the load control circuit for controlling the power delivered to the lamps, and receives a control signal representative of an instantaneous magnitude of an AC line voltage of the AC power source. The control circuit uses the on time, the instantaneous magnitude of the AC line voltage, and an inductance of the inductor of the boost converter to calculate the cumulative output power of the boost converter while the ballast is preheating filaments of the lamps. The control circuit determines the fault condition in the lamps in response to the cumulative output power calculated while the ballast circuit is preheating filaments of the lamps.
In addition, a method of detecting a fault condition in one or more gas discharge lamps driven by an electronic ballast is described herein. The method comprises: (1) selectively rendering a power switching device of a boost converter of the ballast conductive and non-conductive to generate a DC bus voltage, such that an inductor of the boost converter is operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive; (2) adjusting the length of an on time for which the power switching device is conductive; (3) converting the bus voltage to a high-frequency AC voltage; (4) coupling the high-frequency AC voltage to the lamps; (5) preheating filaments of the lamps prior to attempting to strike the lamps; (6) calculating a cumulative output power of the boost converter while preheating filaments of the lamps by using the on time, an instantaneous magnitude of an AC line voltage of the AC power source, and an inductance of the inductor of the boost converter; and (7) detecting the fault condition in the lamps in response to the cumulative output power calculated while preheating filaments of the lamps.
According to another embodiment of the present invention, an electronic ballast for driving a gas discharge lamp from an AC power source comprises a boost converter for generating a DC bus voltage, an inverter circuit for converting the bus voltage to a high-frequency AC voltage, a resonant tank for coupling the high-frequency AC voltage to the lamp, a control circuit operable to calculate an average input power of the ballast, and a communication circuit for transmitting a digital message including the calculated average input power of the ballast. The control circuit uses the on time, an instantaneous magnitude of an AC line voltage of the AC power source, and an inductance of an inductor of the boost converter to calculate the average input power of the ballast, and subsequently transmits the digital message including the calculated average input power of the ballast via the communication circuit.
Further, a method of transmitting a digital message from a load control device for controlling the power delivered from an AC power source to an electrical load is also described herein. The method comprises: (1) selectively rendering a power switching device of a power converter of the load control device conductive and non-conductive to generate a DC bus voltage, such that an inductor of the power converter is operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive; (2) adjusting the length of an on time for which the power switching device is conductive; (3) converting the bus voltage to a high-frequency AC voltage; (4) coupling the high-frequency AC voltage to the lamps; (5) calculating an input power of the boost converter using the on time, an instantaneous magnitude of an AC line voltage of the AC power source, and an inductance of the inductor of the boost converter; and (6) transmitting a digital message including the calculated average input power of the load control device.
Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in greater detail in the following detailed description with reference to the drawings in which:
FIG. 1 is a simplified block diagram of an electronic dimming ballast for driving a gas discharge lamp according to a first embodiment of the present invention;
FIG. 2 is a simplified schematic diagram of a boost convert and an inverter circuit of the ballast of FIG. 1;
FIG. 3 shows example timing diagrams of an inductor current and a bus voltage control signal of the boost converter of FIG. 2 when the boost converter is operating in critical conduction mode;
FIG. 4 shows example timing diagrams of the inductor current and the bus voltage control signal of the boost converter of FIG. 2 when the boost converter is operating in discontinuous conduction mode;
FIG. 5 is an example plot a delay time of the boost converter of FIG. 2 with respect to a target intensity of the lamp;
FIG. 6 shows example timing diagrams of the magnitude of a load voltage, an operating frequency, and a bus voltage of the ballast of FIG. 1 while striking the lamp;
FIG. 7 is a simplified flowchart of a bus voltage control procedure executed periodically by a microprocessor of the ballast of FIG. 1;
FIG. 8A is a simplified flowchart of a boost converter control procedure executed periodically by the microprocessor of the ballast of FIG. 1;
FIG. 8B is a simplified flowchart of a power calculation procedure executed periodically by the microprocessor of the ballast of FIG. 1;
FIG. 9 is a simplified flowchart of a command procedure that is executed by the microprocessor of the ballast of FIG. 1 when a command to control the lamp is received;
FIG. 10 is a simplified flowchart of a lamp strike routine that is executed by the microprocessor of the ballast of FIG. 1 when the ballast receives a command to turn the lamp on;
FIG. 11 is a simplified flowchart of a fault detection procedure executed periodically by the microprocessor of the ballast of FIG. 1;
FIG. 12A is a simplified flowchart of a boost converter control procedure executed periodically by the microprocessor of the ballast of FIG. 1 according to a second embodiment of the present invention;
FIG. 12B is a simplified flowchart of a power calculation procedure executed periodically by the microprocessor of the ballast of FIG. 1 according to the second embodiment of the present invention;
FIG. 13 is a simplified block diagram of a light-emitting diode (LED) driver for controlling the intensity of an LED light source according to a third embodiment of the present invention; and
FIG. 14 is a simplified flowchart of a command procedure executed by a microprocessor of the LED driver of FIG. 16 when a command to control the LED light source is received.



DETAILED DESCRIPTION OF THE INVENTION
The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed.
FIG. 1 is a simplified block diagram of a load control device, e.g., an electronic dimming ballast 100, according to a first embodiment of the present invention. The ballast 100 comprises a hot terminal H and a neutral terminal N that are adapted to be coupled to an alternating-current (AC) power source (not shown) for receiving an AC mains line voltage VAC, (e.g. 120 VAC @ 60 Hz), such that the ballast 100 conducts an input current IIN from the AC power source. Alternatively, the AC mains line voltage VAC could have a magnitude of 240 VAC or 277 VAC. The ballast 100 is adapted to be coupled between the AC power source and a lighting load, such as a gas discharge lamp (e.g., a fluorescent lamp 105), such that the ballast is operable to control the amount of power delivered to the lamp and thus the intensity of the lamp. While only one lamp 105 is shown in FIG. 1, the ballast 100 may be operable to control the intensities of multiple lamps coupled in series or in parallel with the output of the ballast. The ballast 100 comprises an RFI (radio frequency interference) filter circuit 110 for minimizing the noise provided on the AC mains, and a rectifier circuit 120 for generating a rectified voltage VRECT from the AC mains line voltage VAC.
The ballast 100 further comprises a power converter, e.g., a boost converter 130, which generates a direct-current (DC) bus voltage VBUS across a bus capacitor CBUS. The bus voltage VBUS has, for example, a magnitude (e.g., 465 V) that is greater than the peak magnitude VPK of the AC mains line voltage VAC (e.g., approximately 170 volts when the AC mains line voltage VAC has a magnitude of 120 VAC). The boost converter 130 also operates as a power-factor correction (PFC) circuit for improving the power factor of the ballast 100. Alternatively, the power converter of the ballast 100 could comprise, for example, a buck converter, a buck-boost converter, a flyback converter, a buck-boost flyback converter, a single-ended primary-inductor converter (SEPIC), a Ćuk converter, or other suitable power converter circuit.
The ballast 100 further comprises a load control circuit 140 for controlling the amount of power delivered to the lamp 105. According to the first embodiment of the present invention, the load control circuit 140 comprises a ballast circuit including an inverter circuit 150 for converting the DC bus voltage VBUS to a high-frequency AC voltage (e.g., a square-wave voltage VSQ), and a resonant tank circuit 155 for coupling the high-frequency AC voltage generated by the inverter circuit to filaments of the lamp 105. The resonant tank circuit 155 may comprise a resonant inductor (not shown) and a resonant capacitor (not shown), which are characterized by a resonant frequency fRES. The resonant inductor is adapted to be coupled in series between the inverter circuit 150 and the lamp 105, while the resonant capacitor is adapted to be coupled in parallel with the lamp.
Prior to striking the lamp 105, the filaments must be heated during a preheat mode to extend lamp life. Accordingly, the resonant tank circuit 155 comprises a plurality of filament windings (not shown) that are magnetically coupled to the resonant inductor for generating filament voltages for heating the filaments of the lamp 105 during the preheat mode. An example of a ballast having a circuit for heating the filaments of a fluorescent lamp is described in greater detail in U.S. Pat. No. 7,586,268, issued Sep. 8, 2009, titled APPARATUS AND METHOD FOR CONTROLLING THE FILAMENT VOLTAGE IN AN ELECTRONIC DIMMING BALLAST, the entire disclosure of which is hereby incorporated by reference.
The ballast 100 further comprises a control circuit, e.g., a microprocessor 160, for controlling the intensity of the lamp 105 to a target intensity LTARGET between a low-end (i.e., minimum) intensity LLE (e.g., approximately 1%) and a high-end (i.e., maximum) intensity LHE (e.g., approximately 100%). The microprocessor 160 may alternatively be implemented as a microcontroller, a programmable logic device (PLD), an application specific integrated circuit (ASIC), or any suitable type of controller or control circuit. The ballast 100 also comprises a memory 170, which is coupled to the microprocessor 160 for storing the target intensity LTARGET and other operational characteristics of the ballast. The memory 170 may be implemented as an external integrated circuit (IC) or as an internal circuit of the microprocessor 160. A power supply 172 receives the bus voltage VBUS and generates a DC supply voltage VCC (e.g., approximately five volts) for powering the microprocessor 160 and other low-voltage circuitry of the ballast 100. The ballast 100 further comprises a resistive divider including two resistors R174, R176, which are coupled in series between the rectified voltage VRECT and circuit common and may have, for example, resistances of approximately 996 kΩ and 6.49 kΩ, respectively. A line voltage control signal VLINE is generated at the junction of the two resistors R174, R176 and is representative of the magnitude of the rectified voltage VRECT. The line voltage control signal VLINE is provided to the microprocessor 160, such that the microprocessor is operable to determine the magnitude of rectified voltage VRECT and the AC mains line voltage VAC from the magnitude of the line voltage control signal VLINE.
The microprocessor 160 is coupled to the inverter circuit 150 and provides a drive control signal VDRIVE to the inverter circuit for controlling the magnitude of a load voltage VLOAD generated across the lamp 105 and the magnitude of a load current ILOAD conducted through the lamp. The microprocessor 160 may control one or both of two operational parameters of the inverter circuit 150 (e.g., an operating frequency fOP and an operating duty cycle DCOP) to thus control the magnitudes of the load voltage VLOAD and the load current ILOAD. The microprocessor 160 controls the inverter circuit 150 to illuminate the lamp 105 during an on mode, and extinguishes the lamp 105 during an off mode. In addition, the microprocessor 160 is operable to control the inverter circuit 150 so as to adjust (i.e., dim) the intensity of the lamp 105 during the on mode. The microprocessor 160 receives a load current feedback signal VFB-ILOAD, which is generated by a load current measurement circuit 180 and is representative of the magnitude of the load current ILOAD. The microprocessor 160 also receives a load voltage feedback signal VFB-VLOAD, which is generated by a load voltage measurement circuit 182 and is representative of the magnitude of the load voltage VLOAD.
The microprocessor 160 is further coupled to the boost converter 130 for controlling the magnitude of the bus voltage VBUS to a target bus voltage VB-TARGET. Specifically, the microprocessor 160 provides a bus voltage control signal VB-CNTL to the boost converter 130 for adjusting the magnitude of the bus voltage VBUS in response to a bus voltage feedback signal VB-FB and a zero-current feedback signal VB-ZC as will be described in greater detail below. The microprocessor 160 is operable to adjust the bus voltage VBUS to different magnitudes during different operating modes of the ballast 100 (i.e., the off mode, the preheat mode, and the on mode).
The ballast 100 may comprise a phase-control circuit 190 for receiving a phase-control voltage VPC (e.g., a forward or reverse phase-control signal) from a standard phase-control dimmer (not shown). The microprocessor 160 is coupled to the phase-control circuit 190, such that the microprocessor is operable to determine the target intensity LTARGET for the lamp 105 from the phase-control voltage VPC. The ballast 100 may also comprise a communication circuit 192, which is coupled to the microprocessor 160 and allows the ballast to communicate (i.e., transmit and receive digital messages) with the other control devices on a communication link (not shown), e.g., a wired communication link or a wireless communication link, such as a radio-frequency (RF) or an infrared (IR) communication link. Examples of ballasts having communication circuits are described in greater detail in commonly-assigned U.S. Pat. No. 7,489,090, issued Feb. 10, 2009, entitled ELECTRONIC BALLAST HAVING ADAPTIVE FREQUENCY SHIFTING; U.S. Pat. No. 7,528,554, issued May 5, 2009, entitled ELECTRONIC BALLAST HAVING A BOOST CONVERTER WITH AN IMPROVED RANGE OF OUTPUT POWER; and U.S. Pat. No. 7,764,479, issued Jul. 27, 2010, entitled COMMUNICATION CIRCUIT FOR A DIGITAL ELECTRONIC DIMMING BALLAST, the entire disclosures of which are hereby incorporated by reference.
FIG. 2 is a simplified schematic diagram of the boost converter 130 and the inverter circuit 150. The inverter circuit 150 comprises first and second series-connected switching devices (e.g., FETs Q250, Q252) and an inverter control circuit 254, which controls the FETs in response to the drive control signal VDRIVE from the microprocessor 160. The inverter control circuit 254 may comprise, for example, an integrated circuit (IC), such as part number NCP5111, manufactured by On Semiconductor. The inverter control circuit 254 may control the FETs Q250, Q252 using a “d(1−d)” complementary switching scheme, in which the first FET Q250 has a duty cycle of d (i.e., equal to the operating duty cycle DCOP) and the second FET Q252 has a duty cycle of 1−d, such that only one FET is conducting at a time. When the first FET Q250 is conductive, the output of the inverter circuit 150 is pulled up towards the bus voltage VBUS. When the second FET Q252 is conductive, the output of the inverter circuit 150 is pulled down towards circuit common. The magnitude of the load current ILOAD conducted through the lamp 105 is controlled by adjusting the operating frequency fOP and/or the duty cycle DCOP of the high-frequency square-wave voltage VSQ generated by the inverter circuit 150.
The boost converter 130 comprises an inductor L210, which receives the rectified voltage VRECT from the rectifier circuit 120, conducts an inductor current IL, and has an inductance L210 of, for example, approximately 0.81 mH. The inductor L210 is coupled to the bus capacitor CBUS via a diode D212. A power switching device, e.g., a field-effect transistor (FET) Q214 is coupled in series electrical connection between the junction of the inductor L210 and the diode D212 and circuit common, and is controlled to be conductive and non-conductive, so as to generate the bus voltage VBUS across the bus capacitor CBUS. The FET Q214 could alternatively be implemented with a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), or any suitable transistor. A resistor divider is coupled across the bus capacitor CBUS and comprises two resistors R216, 8218, which have, for example, resistances of approximately 1392 kΩ and 10 kΩ, respectively. The bus voltage feedback signal VB-FB is generated at the junction of the resistor R216, 8218, such that the magnitude of the bus voltage feedback signal VB-FB is representative of the magnitude of the bus voltage VBUS.
As shown in FIG. 2, the microprocessor 160 is operatively coupled to the FET Q214 of the boost converter 130 for directly controlling the FET Q214 to be conductive and non-conductive to selectively charge and discharge the inductor L210 and generate the bus voltage VBUS across the bus capacitor CBUS. The boost converter 130 comprises a drive circuit 220, which is coupled to a gate of the FET Q214 for rendering the FET conductive and non-conductive in response to the bus voltage control signal VB-CNTL from the microprocessor 160. The microprocessor 160 controls the bus voltage control signal VB-CNTL to adjust a power-conversion-drive level of the FET Q214 for controlling how long the FET Q214 is rendered conductive and thus the magnitude of the bus voltage VBUS.
The drive circuit 220 comprises FET Q221 having a gate that receives the bus voltage control signal VB-CNTL from the microprocessor 160 and is coupled to the DC supply voltage VCC through a resistor 8222 (e.g., having a resistance of approximately 10 kΩ). The drain of the FET Q221 is also coupled to the DC supply voltage VCC through a resistor R223, which has, for example, a resistance of approximately 6.04 kΩ. The junction of the FET Q221 and the resistor R223 is coupled to the bases of an NPN bipolar junction transistor Q224 and a PNP bipolar junction transistor R225. The emitters of the transistor Q224, Q225 are coupled together through a resistor R226 (e.g., having a resistance of approximately 100Ω). The junction of the emitter of the transistor Q225 and the resistor 8226 is coupled to the gate of the FET Q214. A diode D228 is coupled between the gate of the FET Q214 and the DC supply voltage VCC, while a diode D229 is coupled between circuit common and the gate of the FET Q214. When the bus voltage control signal VB-CNTL is driven high towards the DC supply voltage VCC, the FET Q221 and thus the transistor Q225 are rendered conductive, thus pulling the gate of the FET Q214 down towards circuit common, such that the FET Q214 is rendered non-conductive. When the bus voltage control signal VB-CNTL is driven low towards circuit common, the FET Q221 is rendered non-conductive, and the transistor Q224 pulls the gate of the FET Q214 up towards the DC supply voltage VCC, thus rendering the FET Q214 conductive.
The boost converter 130 also comprises an over-current protection circuit 230, which operates to render the FET Q214 non-conductive in the event of an over-current condition in the FET. The over-current protection circuit 230 comprises a sense resistor 8232 that is coupled in series with the FET Q214 and has a resistance of, for example, approximately 0.075Ω. The voltage generated across the sense resistor 8232 is coupled to the base of an NPN bipolar junction transistor Q233 via a resistor 8234 (e.g., having a resistance of approximately 392Ω). The base of the transistor Q233 is also coupled to circuit common through a resistor R235 (e.g., having a resistance of approximately 4.02Ω) and a capacitor C236 (e.g., having a capacitance of approximately 1000 pF). The collector of the transistor Q233 is coupled to the junction of the transistor Q224, 225 of the drive circuit 220 through a resistor 8238 (e.g., having a resistance of approximately 22.1 kΩ). The junction of the transistor Q233 and the resistor 8238 is coupled to the base of a PNP bipolar junction transistor Q239. When the voltage across the sense resistor 8232 exceeds a predetermined over-current threshold voltage (i.e., as a result of an over-current condition in the FET Q214, e.g., approximately 10 amps), the transistor Q233 is rendered conductive, thus pulling the bases of the transistors Q224, Q225 down towards circuit common and rendering the FET Q214 non-conductive. At this time, the transistor Q239 is also rendered conductive, thus latching the transistor Q233 in the conductive state until the present drive pulse ends (i.e., the gate of the FET Q214 is driven low).
The boost converter 130 further comprises a zero-current detect circuit 240, which generates the zero-current feedback signal VB-ZC when the magnitude of the voltage induced by the inductor L210 collapses to approximately zero volts to indicate when the magnitude of the inductor current IL conducted by the inductor is approximately zero amps. The zero-current detect circuit 240 comprises a control winding 242 that is magnetically coupled to the inductor L210. The control winding 242 is coupled in series with two resistors 8244, 8245, which each have, for example, resistances of approximately 22 kΩ. The junction of the resistor R244, 8245, is coupled to the base of an NPN bipolar junction transistor Q246. The collector of the transistor Q246 is coupled to the DC supply voltage VCC through a resistor R248 (e.g., having a resistance of approximately 2.15 kΩ), such that the zero-current feedback signal VB-ZC is generated at the collector of the transistor. When the voltage across the inductor L210 is greater than approximately zero volts, a voltage is produced across the control winding 242 and the transistor Q246 is rendered conductive, thus driving the zero-current feedback signal VB-ZC down towards circuit common. When the magnitude of the inductor current IL drops to approximately zero amps, the transistor Q246 is rendered non-conductive and the zero-current feedback signal VB-ZC is pulled up towards the DC supply voltage VCC.
The microprocessor 160 controls the FET Q214 to selectively operate the boost converter 130 in critical conduction and discontinuous conduction modes. FIG. 3 shows example timing diagrams of the inductor current IL and the bus voltage control signal VB-CNTL when the boost converter 130 is operating in the critical conduction mode. In critical conduction mode, the FET Q214 is controlled to be conductive when the inductor current IL drops to zero amps. The FET Q214 is maintained conductive for an on time TON, such that the inductor current IL increases in magnitude with respect to time during the on time TON and rises to a peak inductor current IL-PK. The FET Q214 is then controlled to be non-conductive for an off time TOFF, such that the inductor current IL decreases in magnitude with respect to time until the magnitude of the inductor current IL reaches zero amps, at which time the FET Q214 is once again rendered conductive. FIG. 4 shows example timing diagrams of the inductor current IL and the bus voltage control signal VB-CNTL when the boost converter 130 is operating in the discontinuous conduction mode. In the discontinuous mode, the FET Q214 is controlled to be conductive for the on time TON and to be non-conductive for the off time TOFF. However, when the inductor current IL drops to approximately zero amps, the FET Q214 is maintained non-conductive for a delay time TDELAY, such that the inductor current IL does not begin to increase in magnitude, but remains at approximately zero amps. While not shown in FIG. 3, there may be some oscillations in the inductor current IL during the delay time TDELAY after the FET Q214 is rendered non-conductive.
According to an embodiment of the present invention, the microprocessor 160 is operable to calculate an average input power PIN-AVE of the ballast 100 using the inductance of the inductor L210, the magnitudes of the bus voltage VBUS and the rectified voltage VRECT, and the lengths of the on time TON and the delay time TDELAY. The microprocessor 160 may transmit the average input power PIN-AVE of the ballast 100 to, for example, a central controller (not shown) via the communication circuit 192. In addition, the microprocessor 160 may be operable to calculate an average output power POUT-AVE of the boost converter 130 while the ballast 100 is preheating the filaments of the lamp 105, and to detect a fault condition in the lamp 105 in response to the average output power POUT-AVE as will be described in greater detail below.
The microprocessor 160 is operable to adjust the length of the on time TON in response to the magnitude of the bus voltage VBUS (i.e., as determined from the bus voltage feedback signal VB-FB) to thus adjust the magnitude of the bus voltage. Specifically, the microprocessor 160 is operable to increase the on time TON to increase the magnitude of the bus voltage VBUS and to decrease the on time TON to decrease the magnitude of the bus voltage VBUS. The microprocessor 160 does not control the on time TON to be greater than a maximum on time TON-MAX (e.g., approximately 23 microseconds).
The microprocessor 160 is operable to control the delay time TDELAY in response to the target intensity LTARGET of the lamp 105. FIG. 5 is an example plot of the length of the delay time TDELAY with respect to the target intensity LTARGET of the lamp 105. Above a delay time threshold intensity LD-TH (e.g., approximately 60%), the microprocessor 160 controls the delay time TDELAY to be approximately zero seconds. When the target intensity LTARGET of the lamp 105 is greater than the delay time threshold intensity LD-TH, the microprocessor 160 adjusts the delay time TDELAY linearly with respect to the target intensity LTARGET as shown in FIG. 5.
The microprocessor 160 is operable to adjust the bus voltage VBUS to different magnitudes during different operating modes of the ballast 100 (e.g., the off mode, the preheat mode, and the on mode). FIG. 6 shows example timing diagrams of the magnitude of the load voltage VLOAD, the operating frequency fOP, and the bus voltage VBUS while the microprocessor 160 is striking the lamp 105. When the lamp 105 is off (i.e., in the off mode), the microprocessor 160 controls the boost converter 130 to maintain the bus voltage VBUS at an off-bus-voltage magnitude VB-OFF, which is greater than zero volts and may be, for example, equal to approximately 205 volts when the AC mains line voltage VAC has a nominal magnitude of 120 VAC. Since the boost converter 130 is not off, but is generating the bus voltage VBUS, during the off mode, the ballast 100 is able to quickly illuminate (i.e., strike) the lamp 105. Alternatively, the off-bus-voltage magnitude VB-OFF may be equal to approximately 430 volts when the AC mains line voltage VAC has a magnitude of 277 VAC. In addition, the boost converter 130 could be turned off when the lamp 105 is off, such that the magnitude of the bus voltage VBUS is equal to approximately the peak magnitude VPK of the AC mains line voltage VAC (i.e., approximately 170 volts when the AC mains line voltage VAC has a magnitude of 120 VAC), and the ballast 100 consumes even less power.
After receiving a command to strike the lamp 105 (i.e., at time t1 in FIG. 6), the microprocessor 160 first preheats the filaments of the lamp 105 for a preheat time period TPREHEAT (e.g., approximately one second) during the preheat mode. Specifically, the microprocessor 160 controls the operating frequency fOP of the inverter circuit 150 to adjust the load voltage VLOAD to a predetermined preheat load voltage VL-PRE, such that the operating frequency fOP is approximately equal to a preheat frequency fPREHEAT, e.g., approximately 130 kHz, during the preheat mode. In addition, the microprocessor 160 controls the bus voltage VBUS to a preheat-bus-voltage magnitude VB-PRE during the preheat mode. The preheat-bus-voltage magnitude VB-PRE is greater than the off-bus-voltage magnitude VB-OFF, and may be, for example, approximately 500 volts, such that the magnitude of the bus voltage VBUS provided to the resonant tank circuit 155 is great enough to appropriately heat the filaments of the lamp 105 during the preheat mode, but does not exceed the rated voltage of the bus capacitor CBUS. Specifically, when the magnitude of the bus voltage VBUS is at the preheat-bus-voltage magnitude VB-PRE, the ratio of the voltage across the resonant inductor of the resonant tank circuit 155 with respect to the voltage across the resonant capacitor increases, such that the ratio of the magnitudes of the filament voltages with respect to the magnitude of the load voltage VLOAD generated across the lamp 105) also increases. Since there is a relatively low voltage across the lamp 105, the lamp does not glow or strike during the preheat time period TPREHEAT.
After preheating the filaments of the lamp 105 (i.e., after the preheat time period TPREHEAT at time t2 in FIG. 6), the microprocessor 160 sweeps the operating frequency fOP of the inverter circuit 150 down from the preheat frequency fPRE towards the resonant frequency fRES of the resonant tank circuit 155, such that the magnitude of the load voltage VLOAD increases until the lamp 105 strikes (i.e., at time t3 in FIG. 6). When the lamp 105 strikes, the magnitude of the load voltage VLOAD decreases and the magnitude of the load current ILOAD increases, such that the microprocessor 160 is able to detect the lamp strike in response to the load voltage feedback signal VFB-VLOAD and the load current feedback signal VFB-ILOAD. While the lamp 105 is illuminated (i.e., in the on mode), the microprocessor 160 adjusts the magnitude of the bus voltage VBUS to an on-bus-voltage magnitude VON-BUS, for example, approximately 465 volts, which is less than the preheat-bus-voltage magnitude VB-PRE, but greater than the off-bus-voltage magnitude VB-OFF. In other words, the magnitude of the bus voltage VBUS is largest during the preheat mode, and smallest when the lamp 105 is off, such that the ballast 100 consumes less power.
In addition, the microprocessor 160 is operable to preemptively adjust the power-conversion-drive level of the FET Q214 to begin adjusting the magnitude of the bus voltage VBUS prior to changing modes of operation. When attempting to strike the lamp 105, the microprocessor 160 is operable to control the boost converter 130 (i.e., at time t1 in FIG. 6) to begin increasing the magnitude of the bus voltage VBUS from the off-bus-voltage magnitude VB-OFF to the preheat-bus-voltage magnitude VB-PRE prior to controlling the inverter circuit 150 to adjust the operating frequency fOP to the preheat frequency fPRE. For example, the microprocessor 160 monitors the magnitude of the bus voltage VBUS after adjusting the power-conversion-drive level of the FET Q214, and may control the inverter circuit 150 to begin preheating the filaments of the lamp 105 when the magnitude of the bus voltage VBUS is equal to approximately the preheat-bus-voltage magnitude VB-PRE, such that a predetermined turn-on preload time period TPRELOAD-ON exists between when the microprocessor 160 adjusts the power-conversion-drive level of the FET Q214 and when the microprocessor adjusts the operating frequency fOP to the preheat frequency fPRE (as shown in FIG. 6). Accordingly, the length of the turn-on preload time period TPRELOAD-ON may not be the same each time that the lamp is turned on. Alternatively, the microprocessor 160 may wait for a predetermined turn-on preload time period TPRELOAD-ON (e.g., approximately 50 milliseconds) after adjusting the target bus voltage VB-TARGET before adjusting the operating frequency fOP.
The microprocessor 160 may be operable to detect a fault condition in the load (i.e., in the lamps 105 connected to the ballast 100) in response to the calculated average output power POUT-AVE of the boost converter 130 while the ballast 100 is preheating the filaments of the lamp 105 (i.e., during the preheat time period TPREHEAT). The microprocessor 160 is able to confirm that the correct type and number of lamps are connect to the ballast 100 if the average output power POUT-AVE of the boost converter 130 is within predetermined thresholds (i.e., limits) PT1, PT2. The values of the predetermined thresholds PT1, PT2 may be chosen to ensure that the correct type and number of lamps are connected to the ballast 100. Specifically, the predetermined thresholds PT1, PT2 may be equal to the minimum possible average power draw and the maximum average possible power draw, respectively, in the filaments of the correct type and number of lamps during the preheat time period TPREHEAT. For example, the predetermined thresholds PT1, PT2 may be approximately 2.5 W and 3.5 W, respectively, for a single-lamp ballast.
If the average output power POUT-AVE is outside the predetermined thresholds PT1, PT2, the microprocessor 160 is operable to determine that a fault condition exists in the lamps. For example, the microprocessor 160 may be operable to determine that at least one of the lamps 105 is the wrong lamp type, a wrong number of lamps are connected to the ballast 100 (e.g., at least one of the lamps missing), and/or at least one of the lamps has a broken filament if the average output power POUT-AVE is outside the predetermined thresholds PT1, PT2. After determining that a fault condition exists in the lamps 105 while preheating the filaments, the microprocessor 160 does not attempt to strike the lamps and keeps the lamps turned off. Alternatively, the microprocessor 160 could use a cumulative output power POUT-CUM accumulated during the preheat time period TPREHEAT to determine that a fault condition exists in the lamps.
Different lamp types may also have different power consumptions near the high-end intensity LHE. Accordingly, the microprocessor 160 is operable to measure the average output power POUT-AVE during a predetermined time period TFAULT (e.g., approximately one second) when the target intensity LTARGET is at the high-end intensity LHE, and to determine that a fault condition exits in the lamps 105 (i.e., at least one of the lamp is the wrong lamp type) if the average output power POUT-AVE during the predetermined time period TFAULT is outside predetermined thresholds PT3, PT4, as will be described in greater detail below with reference to FIG. 11. The predetermined thresholds PT3, PT4 may be equal to the minimum possible average power draw and the maximum possible average power draw, respectively, of the correct type and number of lamps at the high-end intensity LHE during the predetermined time period TFAULT. For example, the predetermined thresholds PT3, PT4 may be approximately 40 W and 60 W, respectively, for a ballast driving a 54-W lamp with a ballast factor of 1.00.
FIG. 7 is a simplified flowchart of a bus voltage control procedure 300 executed periodically by the microprocessor 160 (e.g., approximately every 104 microseconds). The microprocessor 160 first calculate a bus voltage error eBUS at step 310 by subtracting the target bus voltage VB-TARGET from the bus voltage VBUS (as determined from the bus voltage feedback signal VB-FB), i.e.,

eBUS=VBUS−VB-TARGET.  (Equation 1)

If the bus voltage error eBUS is greater than zero at step 312 (i.e., the magnitude of the bus voltage VBUS is greater than the target bus voltage VB-TARGET), the microprocessor 160 decreases the on time TON at step 314 by processing a digital implementation of a frequency-domain transfer function G(s), e.g.,





  
    
      
        
          
            G
            ⁡
            
              (
              s
              )
            
          
          =
          
            
              K
              ·
              
                (
                
                  s
                  +
                  a
                
                )
              
            
            
              s
              ⁡
              
                (
                
                  s
                  +
                  b
                
                )
              
            
          
        
        ,
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        )
      
    
  




where a equals approximately 17, b equals approximately 96.7, and K equals approximately −258. Other values of a, b, and K may be needed based upon the voltage conversion ratios as well known in the art. If the bus voltage error eBUS is less than zero at step 316 (i.e., the magnitude of the bus voltage VBUS is less than the target bus voltage VB-TARGET), the microprocessor 160 increases the on time TON using a transfer function G(s) at step 318. If the on time TON is greater than the maximum on time TON-MAX at step 320, the microprocessor 160 limits the on time TON to the maximum on time TON-MAX at step 322, and the bus voltage control procedure 300 exits.

FIG. 8A is a simplified flowchart of a boost converter control procedure 400 executed periodically by the microprocessor 160 (e.g., approximately every 104 microseconds). The microprocessor 160 uses an on timer and a delay timer to keep track of the time periods of the inductor current IL and the bus voltage control signal VB-CNTL shown in FIGS. 3 and 4. If the delay timer has just expired at step 410 (i.e., at the end of the delay time TDELAY), the microprocessor 160 initializes the on timer to the present value of the on time TON (i.e., as determined from the bus voltage control procedure 300 of FIG. 7) and starts the on timer decreasing in value with respect to time at step 412. The microprocessor 160 then drives the bus voltage control signal VB-CNTL low towards circuit common at step 414 (such that the FET Q214 of the boost converter 130 is rendered conductive), and the boost converter control procedure 400 exits. Accordingly, the inductor current IL increases in magnitude with respect to time during the on time TON as shown in FIGS. 3 and 4.
When the on timer expires at step 416 (i.e., at the end of the on time TON), the microprocessor 160 drives the bus voltage control signal VB-CNTL high towards the DC supply voltage VCC at step 418, such that the FET Q214 of the boost converter 130 is rendered non-conductive and the inductor current IL begins decreasing in magnitude with respect to time.
When the magnitude of the inductor current IL drops to zero amps (as determined from the zero-current feedback signal VB-ZC from the boost converter 130) at step 420, the microprocessor 160 determines if the delay time TDELAY is presently equal to zero seconds at step 422. If the delay time TDELAY is not equal to zero seconds at step 422, the microprocessor 160 initializes the delay timer with the present value of the delay time TDELAY (as determined from the bus voltage control procedure 300 of FIG. 7) and starts the delay timer decreasing in value with respect to time at step 424, before the boost converter control procedure 400 exits. The microprocessor 160 will render the FET Q214 of the boost converter 130 conductive at step 414 when the delay timer expires at step 410. If the delay time TDELAY is equal to zero seconds at step 422 when the magnitude of the inductor current IL drops to zero amps at step 420, the microprocessor 160 starts the on timer at step 412 and drives the bus voltage control signal VB-CNTL low towards circuit common at step 414 to render the FET Q214 conductive, before the boost converter control procedure 400 exits.
FIG. 8B is a simplified flowchart of a power calculation procedure 450 that is executed periodically by the microprocessor 160 at a sampling period TSAMP (e.g., approximately every 104 microseconds). First, the microprocessor 160 samples the line voltage control signal VLINE to determine the magnitude of the rectified voltage VRECT at step 452. At step 454, the microprocessor 160 calculates the magnitude of the peak inductor current IL-PK for the present sampling period, i.e.,

IL-PK=VRECT·TON/L210.  (Equation 3)

The microprocessor 160 then calculates an instantaneous input power PINST of the ballast 100 at step 456, i.e.,





  
    
      
        
          
            P
            INST
          
          =
          
            
              
                V
                RECT
              
              ·
              
                I
                
                  L
                  ⁢
                  
                    -
                  
                  ⁢
                  PK
                
              
            
            
              1
              +
              
                
                  
                    T
                    DELAY
                  
                  
                    T
                    ON
                  
                
                ·
                
                  
                    
                      V
                      BUS
                    
                    -
                    
                      V
                      RECT
                    
                  
                  
                    V
                    BUS
                  
                
              
            
          
        
        ,
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          4
        
        )
      
    
  




using the lengths of the on time TON and the delay time TDELAY that are presently being used to control the FET Q214 of the boost converter 130. At step 458, the microprocessor 160 uses a running average to calculate the average input power PIN-AVE of the ballast 100 using the instantaneous power PINST calculated at step 454.

The microprocessor is then operable to calculate the cumulative output power POUT-CUM of the boost converter 130 at step 460, i.e.,

POUT-CUM=POUT-CUM+PINST−PLOSS,  (Equation 5)

where PLOSS is a constant representing the power loss due to the power dissipated in the boost converter 130 and due to a propagation delay in the turn-on of the FET Q214 (e.g., approximately 5% of the output power of the boost converter 130 at the high-end intensity LHE, i.e., approximately 6 W for a ballast driving two 54-W lamps). The microprocessor 160 is operable to use the value calculated at step 460 to determine the cumulative output power POUT-CUM of the boost converter 130 while preheating the filaments of the lamp 105 (i.e., during the preheat time period TPREHEAT) to thus determine if the correct number and type of lamps are connected to the ballast 100 and/or to determine if any of the lamps are missing or faulty (as will be described in greater detail below with reference to FIG. 10). The power loss constant PLOSS could alternatively be a variable value, for example, dependent upon the magnitude of the AC mains lines voltage VAC as determined from the magnitude of the rectified voltage VRECT.

According to an alternative embodiment of the present invention, the microprocessor 160 is only operable to control the boost converter 130 to operate in critical conduction mode. Since the delay time TDELAY will always be zero seconds, the microprocessor 160 is operable to use a simplified equation to calculate the instantaneous input power PINST, i.e.,

PINST=1⁄2·VRECT·IL-PK,  (Equation 6)

at step 454 of the power calculation procedure 450.

FIG. 9 is a simplified flowchart of a command procedure 500 that is executed by the microprocessor 160 when a command to control the lamp 105 is received via the phase-control circuit 190 or the communication circuit 192 at step 510. If the received command is a command to turn the lamp 105 off at step 512, the microprocessor 160 first stores the present target intensity LTARGET of the lamp in the memory 170 at step 514, controls the target intensity LTARGET of the lamp 105 to 0% (i.e., to turn the lamp off) at step 520, and adjusts the drive control signal VDRIVE to the inverter circuit 150 to turn the lamp off at step 522, before the command procedure 500 exits.
If the microprocessor 160 has received a command to turn the lamp 105 on at step 524, and the lamp is not already on at step 525, the microprocessor executes a lamp strike routine 600 to attempt to strike the lamp (which will be described in greater detail below with reference to FIG. 10). If the lamp 105 is already on at step 525, the microprocessor 160 does not attempt to strike the lamp again as part of the lamp strike routine 600. The microprocessor 160 then adjusts the delay time TDELAY in response to the target intensity LTARGET of the lamp 105. Specifically, if the target intensity LTARGET is greater than or equal to the delay time threshold intensity LD-TH at step 526, the microprocessor 160 sets the delay time TDELAY equal to zero seconds at step 528, and the command procedure 500 exits. If the target intensity LTARGET is less than the delay time threshold intensity LD-TH at step 526, the microprocessor 160 adjusts the delay time TDELAY in response to target intensity LTARGET at step 530 (e.g., as shown in FIG. 5), and the command procedure 500 exits.
If the microprocessor 160 has received a command to adjust the target intensity LTARGET of the lamp 105 on at step 532, the microprocessor stores the new target intensity LTARGET (from the received command) in the memory 170, and adjusts the drive control signal VDRIVE to the inverter circuit 150 at step 534, so as to control the intensity of the lamp 105 to the target intensity LTARGET received with the command. The microprocessor 160 then controls the length of the delay time TDELAY at steps 526-530, before the command procedure 500 exits. If the microprocessor 160 has received a command to transmit the average input power PIN-AVE at step 536, the microprocessor transmits at step 538 a digital message including the average input power PIN-AVE (as calculated at step 458 of the power calculation procedure 450), and the command procedure 500 exits.
FIG. 10 is a simplified flowchart of the lamp strike routine 600 that is executed by the microprocessor 160 when the ballast 100 receives a command to turn the lamp 105 on at step 520 of the command procedure 500. The microprocessor 160 first controls the target bus voltage VB-TARGET to the preheat-bus-voltage magnitude VB-PRE at step 610, such that the microprocessor will begin adjusting the on time TON (as part of the boost converter control procedure 400) to control the magnitude of the bus voltage VBUS up to the preheat-bus-voltage magnitude VB-PRE. The microprocessor 160 then waits until the magnitude of the bus voltage VBUS is equal to approximately the preheat-bus-voltage magnitude VB-PRE (i.e., for the turn-on preload time period PPRELOAD-ON) at step 612, before starting a preheat timer at step 614 and controlling the operating frequency fOP of the inverter circuit 150 to the preheat frequency fPREHEAT (i.e., approximately 130 kHz) at step 616. Alternatively, the microprocessor 160 could adjust the operating frequency fOP of the inverter circuit 150 in response to the magnitude of the load voltage feedback signal VFB-VLOAD while preheating the filaments of the lamp 105, so as to control the magnitude of the load voltage VLOAD to the predetermined preheat load voltage VL-PRE (as shown in FIG. 6).
The microprocessor 160 accumulates the cumulative output power POUT-CUM of the boost converter 130 during the preheat time period TPREHEAT in order to calculate the average output power POUT-AVE to thus determine if the correct number and type of lamps are connected to the ballast 100 and/or to determine if any of the lamps are missing or faulty. Accordingly, the microprocessor 160 resets the value of the cumulative output power POUT-CUM to zero Watts at step 618, and waits for the length of the preheat time period PPREHEAT at step 620, while continuing to accumulate the cumulative output power POUT-CUM (i.e., at step 460 of the power calculation procedure 450). The microprocessor 160 then ramps the operating duty cycle DCOP up from an initial duty cycle (e.g., approximately 0%) to a preheat duty cycle DCPREHEAT (e.g., approximately 50%) over a ramp time period TRAMP (e.g., approximately 50 milliseconds) at step 620, and then waits for the end of the preheat time period TPREHEAT at step 622.
After the end of the preheat time period TPREHEAT at step 622 (as determined from the preheat timer), the microprocessor 160 calculates the average output power POUT-AVE during the preheat time period TPREHEAT at step 624, i.e.,

POUT-AVE=POUT-CUM/NSAMP,  (Equation 7)

where NSAMP is the number of samples during the preheat time period, i.e.,

NSAMP=TPREHEAT/TSAMP.  (Equation 8)

If the average output power POUT-AVE during the preheat time period TPREHEAT outside of the predetermined thresholds PT1, PT2 at step 626, the microprocessor 160 turns off the lamp 105 by controlling the target intensity LTARGET of the lamp to 0% at step 628, and adjusting the drive control signal VDRIVE to the inverter circuit 150 at step 630. Accordingly, the lamp strike routine 600 exits without striking the lamp.

If the cumulative output power POUT is greater than or equal to the first predetermined threshold PT1 and is less than or equal to the second predetermined threshold PT2 at step 626, the microprocessor 160 attempts to strike the lamp 105. Specifically, the microprocessor 160 initializes a strike timeout period TS-TO to, for example, approximately 10 msec, and starts the strike timeout timer decreasing with respect to time at step 632, and controls the operating frequency fOP towards a strike target frequency (e.g., approximately 50 kHz) by decreasing the operating frequency fOP by a predetermined frequency value ΔfOP (e.g., approximately 150 Hz) at step 634. In addition, the microprocessor 160 may also increase the duty cycle DCOP of the inverter circuit 150 towards a strike target duty cycle (e.g., approximately 35%) by a predetermined increment (e.g., approximately 1%) at step 634. The microprocessor 160 continues to decrease the operating frequency fOP by the predetermined frequency value ΔfOP at step 634 until the lamp strikes at step 636 or the strike timeout timer expires at step 638. When the strike timeout timer expires at step 638, the microprocessor 160 waits for a sleep time period TSLEEP (e.g., approximately five seconds) at step 640 and then starts the lamp strike routine 600 over again to try to strike the lamp 105 once again. When the lamp 105 has been struck at step 636, the microprocessor 160 controls the target bus voltage VB-TARGET to the on-bus-voltage magnitude VB-ON at step 638, recalls the target intensity LTARGET from the memory 170 at step 640, and adjusts the drive control signal VDRIVE in response to the target intensity LTARGET at step 642, before the lamp strike routine 600 exits.
FIG. 11 is a simplified flowchart of a fault detection procedure 700 executed periodically by the microprocessor 160 (e.g., approximately every second) in order to determine if a fault condition exits in the lamps 105 (i.e., at least one of the lamp is the wrong lamp type). If the target intensity LTARGET is at the high-end intensity LHE at step 710, the microprocessor 160 resets the value of the cumulative output power POUT-CUM to zero Watts at step 712, and waits for the length of the predetermined time period TFAULT at step 714, while continuing to accumulate the cumulative output power POUT-CUM (i.e., at step 460 of the power calculation procedure 450). At step 715, the microprocessor 160 calculates the average output power POUT-AVE during the predetermined time period TFAULT, where NSAMP is the number of samples during the predetermined time period TFAULT. If the average output power POUT-AVE during the predetermined time period TFAULT is within the predetermined limits PT3, PT4 at step 716, the fault detection procedure 700 simply exits (i.e., the correct number and type of lamps 105 are connected to the ballast 100). However, if the average output power POUT-AVE is outside the predetermined limits PT3, PT4 at step 716, the microprocessor 160 determines that a fault condition exists at the lamps 105 and turns the lamps 105 off by storing the present target intensity LTARGET of the lamp in the memory 170 at step 718, controlling the target intensity LTARGET of the lamp 105 to 0% at step 720, and adjusting the drive control signal VDRIVE to the inverter circuit 150 to turn the lamp off at step 722.
According to a second embodiment of the present invention, the microprocessor 160 is operable to measure the length of the off time TOFF and to use the length of the off time TOFF to calculate the instantaneous input power PINST of the ballast 100 and the cumulative output power POUT-CUM of the boost converter 130. FIG. 12A is a simplified flowchart of a boost converter control procedure 400′ executed periodically by the microprocessor 160 (e.g., approximately every 104 microseconds) according to the second embodiment of the present invention. The boost converter control procedure 400′ of the second embodiment is very similar to the boost converter control procedure 400 of the first embodiment (as shown in FIG. 8A). However, at the end of the on time TON at step 416, the microprocessor 160 initializes the off timer to zero seconds and starts the off timer increasing in value with respect to time at step 426′. When the magnitude of the inductor current IL drops to zero amps at step 420, the microprocessor 160 sets the off time TOFF equal to the present value of the off timer at step 428′. The microprocessor 160 will use the off time TOFF from step 428′ to calculate the instantaneous input power PINST of the ballast 100 and the cumulative output power POUT-CUM of the boost converter 130.
FIG. 12B is a simplified flowchart of a power calculation procedure 450′ that is executed periodically by the microprocessor 160 at the sampling period TSAMP (i.e., every 104 microseconds) according to the second embodiment of the present invention. The power calculation procedure 450′ of the second embodiment is very similar to the power calculation procedure 450 of the first embodiment (as shown in FIG. 8B). However, the microprocessor 160 calculates a total time period TTOTAL for present switching cycle of the inductor current IL at step 462′ by adding the on time TON (from step 314 of the bus voltage control procedure 300), the off time TOFF (from step 428′ of the boost converter control procedure 400′), and the delay time TDELAY (from steps 528, 530 of the command procedure 500), i.e.,

TTOTAL=TON+TOFF+TDELAY.  (Equation 9)

At step 464′, the microprocessor 160 calculates the instantaneous input power PINST of the ballast 100, i.e.,





  
    
      
        
          P
          INST
        
        =
        
          
            1
            2
          
          ⁢
          
            
              (
              
                
                  
                    T
                    ON
                  
                  
                    T
                    TOTAL
                  
                
                +
                
                  
                    T
                    OFF
                  
                  
                    T
                    TOTAL
                  
                
              
              )
            
            ·
            
              V
              RECT
            
            ·
            
              
                I
                
                  L
                  ⁢
                  
                    -
                  
                  ⁢
                  PK
                
              
              .
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          10
        
        )
      
    
  




The microprocessor 160 calculates the average input power PIN-AVE of the ballast 100 at step 458, and the cumulative output power POUT-CUM of the boost converter 130 at step 460.

FIG. 13 is a simplified block diagram of a light-emitting diode (LED) driver 800 for controlling the intensity of an LED light source 805 (e.g., an LED light engine) according to a third embodiment of the present invention. The LED driver 800 includes many similar functional blocks as the electronic dimming ballast 100 of the first embodiment (as shown in FIG. 1). However, the LED driver 800 includes a load control circuit 840 comprising an LED drive circuit 850, which receives the bus voltage VBUS and controls the amount of power delivered to the LED light source 805 so as to control the intensity of the LED light source. The LED drive circuit 850 may comprise, for example, a controllable-impedance circuit (such as a linear regulator) or a switching regulator (such as a buck converter). A control circuit, e.g., a microprocessor 860, provides the drive control signal VDRIVE to the LED drive circuit 850 for controlling at least one of the magnitude of a load current ILOAD conducted through the LED light source 805 and the magnitude of a load voltage VLOAD produced across the LED light source, so as to adjust the intensity of the LED light source. Examples of LED drivers are described in greater detail in commonly-assigned U.S. patent application Ser. No. 12/813,908, filed Jun. 11, 2010, entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosure of which is hereby incorporated by reference.
The LED driver 800 also includes a power converter 830, which may comprise the boost converter 130 of the first embodiment. The microprocessor 860 is coupled to the power converter 830 for adjusting the magnitude of the bus voltage VBUS using the bus voltage control procedure 300 (shown in FIG. 7) and the boost converter control procedure 400 (shown in FIG. 8A). Alternatively, the power converter 830 may comprise, for example, a buck converter, a buck-boost converter, a flyback converter, a buck-boost flyback converter, a single-ended primary-inductor converter (SEPIC), a Ćuk converter, or other suitable power converter circuit.
The microprocessor 860 is operable to control the magnitude of the bus voltage VBUS to the on-bus-voltage magnitude VB-ON when the LED light source 805 is on and to the off-bus-voltage magnitude VB-OFF when the LED light source is off. In addition, the microprocessor 860 preemptively adjusts the power-conversion-drive level of the power converter 830 prior to changing modes of operation. Specifically, the microprocessor 860 adjusts the target bus voltage VB-TARGET to the on-bus-voltage magnitude VB-ON, and then waits for the turn-on preload time period VPRELOAD-ON before turning on the LED light source 805. The microprocessor 860 is further operable to adjust the target bus voltage VB-TARGET to the off-bus-voltage magnitude VB-OFF, and then wait for a turn-off preload time period TPRELOAD-OFF, before turning off the LED light source 805. Further, the microprocessor 860 may be operable to determine that the LED light source 805 has been removed (i.e., decoupled from the LED drive circuit 850) or has filed while the LED driver 800 is energized and running in response to detecting a large, instantaneous drop in the magnitude of the load current ILOAD. The microprocessor 860 may then be operable adjust the magnitude of the bus voltage VBUS to the off-bus-voltage magnitude VB-OFF, and wait for the turn-off preload time period TPRELOAD-OFF, before turning off the LED light source 805. In addition, the LED driver 800 may be operable to control the magnitude of the bus voltage VBUS in response to a rated operating voltage of the LED light source 805, or in response to a voltage developed across the LED drive circuit 850 in order to optimize the amount of power consumed in the LED driver 800 as described in the previously-referenced application Ser. No. 12/813,908.
FIG. 14 is a simplified flowchart of a command procedure 900 executed by the microprocessor 860 according to the third embodiment of the present invention when a command to control the LED light source 805 is received by the LED driver 800. The command procedure 900 of the third embodiment is very similar to the command procedure 500 of the first embodiment (as shown in FIG. 9). However, when the LED light source 805 is turned on at step 524, the microprocessor 860 controls the target bus voltage VB-TARGET to the on-bus-voltage magnitude VB-ON at step 950, such that the microprocessor will begin adjusting the power-conversion-drive level of the power converter 830 (i.e., the on time TON) to control the magnitude of the bus voltage VBUS up to the on-bus-voltage magnitude VB-ON. The microprocessor 860 waits for the turn-on preload time period TPRELOAD-ON at step 952 and adjusts the drive control signal VDRIVE to the LED drive circuit 850 at step 954 to control the intensity of the LED light source 805 to the target intensity LTARGET (e.g., as received with the command or as stored in the memory 170), before the command procedure 900 exits.
In addition, when the LED lighting source 805 is turned off at step 512, the microprocessor 860 controls the target bus voltage VB-TARGET to the off-bus-voltage magnitude VB-OFF at step 960, to begin adjusting the power-conversion-drive level of the boost converter 130 (i.e., the on time TON), so as to bring the magnitude of the bus voltage VBUS down to the off-bus-voltage magnitude VB-OFF. The microprocessor 860 then waits for the turn-off preload time period TPRELOAD-OFF at step 962, before controlling the target intensity LTARGET to 0% (i.e., turning the LED light source 805 off) at step 520, and adjusting the drive control signal VDRIVE to the inverter circuit 150 to turn the lamp off at step 522.
Alternatively, the hot terminal H of the ballast 100 of the first and second embodiments and the LED driver 800 of the third embodiment could be adapted to receive the phase-control signal VPC rather than the full AC mains line voltage VAC, such that the ballast and the LED driver are operable to both receive power and determine the target intensity LTARGET from the phase-control signal VPC. An example of a load control device that receives both power and control information from a single terminal is described in greater detail in commonly-assigned U.S. patent application Ser. No. 12/704,781, filed Feb. 12, 2010, entitled HYBRID LIGHT SOURCE, the entire disclosure of which is hereby incorporated by reference.
While the present invention has been described with reference to the ballast 100 and the LED driver 800, the methods of controlling the magnitude of the bus voltage VBUS of a power converter described herein may be used in other types of load control devices, such as, for example, a dimmer switch for a lighting load, an electronic switch, a switching circuit including a relay, a controllable plug-in module adapted to be plugged into an electrical receptacle, a controllable screw-in module adapted to be screwed into the electrical socket (e.g., an Edison socket) of a lamp, a motor speed control device, or a motorized window treatment.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

## Claims

1. A load control device for controlling the power delivered from a power source to an electrical load, the load control device comprising:
a power converter for generating a bus voltage, the power converter comprising an inductor and a power switching device coupled to the inductor, the inductor operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive, the power switching device controlled to be conducive for an on time;
a load control circuit receiving the bus voltage and adapted to be coupled to the electrical load for controlling the power delivered to load; and
a control circuit operatively coupled to the load control circuit for controlling the power delivered to the lamp, the control circuit receiving a control signal representative of an instantaneous magnitude of a source voltage of the power source, the control circuit operatively coupled to the power switching device of the power converter for controlling the length of the on time;
wherein the control circuit is configured to determine an average input power of the load control device using the on time of the power switching device of the power converter and the instantaneous magnitude of the source voltage.

2. The load control device of claim 1, wherein the control circuit is configured to calculate a peak magnitude of an inductor current conducted through the inductor of the power converter using the on time of the power switching device of the power converter, the instantaneous magnitude of the source voltage, and an inductance of the inductor of the power converter.

3. The load control device of claim 2, wherein the inductor current increases in magnitude during the on time while the power switching device is conductive and, after the on time, decreases in magnitude during an off time while the power switching device is non-conductive until the magnitude of the inductor current drops to approximately zero amps.

4. The load control device of claim 3, wherein the power switching device is maintained non-conductive for a delay time after the off time.

5. The load control device of claim 4, wherein the control circuit is configured to calculate the average input power using the instantaneous magnitude of the source voltage, the peak magnitude of the inductor current, and the lengths of the on time and the delay time.

6. The load control device of claim 4, wherein the control circuit is configured to calculate the average input power using the instantaneous magnitude of the source voltage, the peak magnitude of the inductor current, and the lengths of the on time, the off time, and the delay time.

7. The load control device of claim 3, wherein the control circuit is configured to calculate the average input power using the instantaneous magnitude of the source voltage, the peak magnitude of the inductor current, and the lengths of the on time and the off time.

8. The load control device of claim 2, wherein the control circuit is configured to calculate the average input power using the on time, the instantaneous magnitude of the source voltage, and the peak magnitude of the inductor current.

9. The load control device of claim 2, wherein the control circuit is configured to calculate an instantaneous input power of the load control device using the on time of the power switching device of the power converter, the instantaneous magnitude of the source voltage, and the peak magnitude of the inductor current, the control circuit configured to use a running average to calculate the average input from the instantaneous input power.

10. The load control device of claim 1, wherein the control circuit is configured to determine an instantaneous input power of the load control device, and to use a running average to calculate the average input from the instantaneous input power.

11. The load control device of claim 1, further comprising:
a communication circuit coupled to the control circuit, such that the control circuit is configured to transmit a digital message including the average input power of the load control device.

12. The load control device of claim 1, wherein the power converter comprises a boost converter.

13. The load control device of claim 1, wherein the electrical load comprises a gas discharge lamp and the load control circuit comprises a ballast circuit for controlling the intensity of the lamp.

14. The load control device of claim 1, wherein the electrical load comprises an LED light source and the load control circuit comprises an LED drive circuit for controlling the intensity of the LED light source.

15. A load control device for controlling the power delivered from a power source to an electrical load, the load control device comprising:
a power converter for generating a bus voltage, the power converter comprising an inductor and a power switching device coupled to the inductor, such that the inductor is operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive, the power switching device controlled to be conducive for an on time;
a load control circuit receiving the bus voltage and adapted to be coupled to the electrical load for controlling the power delivered to load; and
a control circuit operatively coupled to the load control circuit for controlling the power delivered to the lamp, the control circuit receiving a control signal representative of an instantaneous magnitude of a source voltage of the power source, the control circuit operatively coupled to the power switching device of the power converter for controlling the length of the on time; and
a communication circuit coupled to the control circuit for transmitting and receiving digital messages;
wherein the control circuit is configured to determine an average input power of the load control device using the on time of the power switching device of the power converter and the instantaneous magnitude of the source voltage, the control circuit configured to transmit a digital message including the average input power of the load control device via the communication circuit.

16. The load control device of claim 15, wherein the control circuit is configured to calculate a peak magnitude of an inductor current conducted through the inductor of the power converter using the on time of the power switching device of the power converter, the instantaneous magnitude of the source voltage, and an inductance of the inductor of the power converter.

17. The load control device of claim 16, wherein the control circuit is configured to calculate the average input power using the on time of the power switching device of the power converter, the instantaneous magnitude of the source voltage, and the peak magnitude of the inductor current.

18. The load control device of claim 15, wherein the control circuit is configured to determine an instantaneous input power of the load control device, and to use a running average to calculate the average input from the instantaneous input power.

19. The load control device of claim 15, wherein the power converter comprises a boost converter.

20. The load control device of claim 15, wherein the electrical load comprises a gas discharge lamp and the load control circuit comprises a ballast circuit for controlling the intensity of the lamp.

21. The load control device of claim 15, wherein the electrical load comprises an LED light source and the load control circuit comprises an LED drive circuit for controlling the intensity of the LED light source.

22. A method of transmitting a digital message from a load control device for controlling the power delivered from a power source to an electrical load, the load control device comprising a power converter having an inductor and a power switching device coupled to the inductor, the method comprising:
selectively rendering the power switching device conductive and non-conductive to generate a bus voltage, such that the inductor is operable to charge when the power switching device is conductive and to discharge when the power switching device is non-conductive;
adjusting the length of an on time for which the power switching device is conductive;
converting the bus voltage to a high-frequency AC voltage;
coupling the high-frequency AC voltage to the lamps;
calculating an input power of the boost converter using the on time of the power switching device and an instantaneous magnitude of a source voltage of the power source; and
transmitting a digital message including the calculated average input power of the load control device.