# Patent

## Title
Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom

## Abstract

Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This non-provisional application claims the benefit of U.S. Provisional Application No. 61/589,773, entitled “FLEXIBLY ORDERED TRANSISTOR ISOLATION PROCESS COMPATIBLE WITH BOTH DDC AND DOPED CHANNEL TRANSISTOR MANUFACTURE” and filed Jan. 23, 2012, the contents of which are hereby incorporated by reference in their entirety.


FIELD OF THE INVENTION
The present technology relates to processes for manufacturing integrated circuits, and more specifically to processes for manufacturing integrated circuits with different channel doping transistor architectures and devices therefrom.
BACKGROUND
Modern integrated circuit (IC) die, such as a System on a Chip (SoC), may include millions of MOS transistors on the same die. These transistors are not necessarily identical in structure or use, but rather are divided into multiple blocks of transistor device types with different operational characteristics. Common transistors include analog/digital transistors, high/normal/low frequency transistors, transistors configured to mimic older transistor designs (i.e. legacy transistors), transistors designed to work at distinct voltages, and low/high power transistors, for which the transistors may be of planar MOS type and may be NMOS and PMOS. Alternative transistor designs may be DDC, FinFET or other designs. However, process flows that allow for multiple transistor device types on the same wafer or die are generally difficult to develop and can have relatively low yields. Further, such process flows tend to be extremely sensitive to changes in processes, equipment, and other manufacturing factors. Thus, manufacturers typically limit the types of transistors available on a single die and are resistant to altering manufacturing processes, equipment, or other factors. For this reason, manufacturers would prefer to implement transistors on a common process integration platform, for instance, all transistors being planar MOS type. Additionally, upgrading SoC designs to accommodate improved transistor designs, manufacturing equipment, or processes is generally not preferred due to the expense and risk of new circuit designs that are likely necessary. In view of the foregoing, designers of SoCs and other types of multi-transistor ICs often resort to reusing otherwise inferior or older transistor device types and processes in order to reduce costs and risks for the design and manufacturing of such ICs. The designer is forced to compromise performance and functionality for the sake of cost and manufacturability.



BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a schematic illustration of a processing scheme that can support manufacture of multiple transistor device types in accordance with the present technology;
FIG. 2 is a schematic illustration comparing and contrasting a conventional processing scheme and an improved low temperature processing scheme that can support manufacture of multiple transistor device types in accordance with the present technology;
FIG. 3 is a schematic illustration of exemplary mask layouts for multiple transistor device types, including solely DDC transistor device types, or solely doped channel transistor device types, or combinations of DDC and doped channel transistors;
FIG. 4 illustrates representative and distinct transistor device types that can be supported on the wafer and die;
FIG. 5 is an illustration of selected process steps in formation of a blanket epitaxial channel transistor;
FIG. 6 illustrates a schematic of a deeply depleted channel (DDC) device and doping concentrations therein;
FIGS. 7A and 7B schematically illustrate selected structures of an SoC with at least two distinct device types separated by an isolation structure, and having separate Vt settings achieved by varied screen layer thickness and depth;
FIGS. 8A and 8B schematically illustrate selected structures of another SoC with at least two distinct device types separated by an isolation structure, and having separate Vt settings achieved by varied screen layer thickness and depth;
FIG. 9 is an illustration of selected process steps in formation of a blanket epitaxial channel transistor in accordance with an alternate embodiment; and
FIG. 10 shows a plot illustrating how gate work function selection can also be used in conjunction with varying channel/screen/threshold voltage set layer dopant concentration to adjust threshold voltage.



DETAILED DESCRIPTION
The present technology is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the instant invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. However, the present technology can be implemented without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present technology is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present technology.
The challenge with advancing planar MOS transistors to support more modern SoC designs is the limitation of conventional MOS transistors' ability to continue to scale down voltage as transistor densities increase. A large process-related contributing factor to the scaling constraints is random dopant fluctuation in the transistor channel, thus limiting the ability to reduce threshold voltage of the device for reliable reduction in supply voltage. A solution for the random dopant fluctuation problem in the context of preferred CMOS process integration is to use deeply depleted channel (DDC) transistors.
For modern nanometer scale transistors, shallow trench isolation (STI) is typically used to provide device isolation. A typical STI process involves etching trenches with relatively steep sidewalls into the substrate on which the device will be built. The sidewalls are typically coated with liner layers, and the trench is thereafter filled with an electrically insulating dielectric. In a silicon-based process, the insulating fill dielectric is commonly a silicon oxide deposited by chemical vapor deposition. In most conventional process flows, STI is performed only once and early in a wafer processing flow, prior to the formation of the transistor channels. Such a process, commonly referred to as “STI-first” or “isolation first” process, is typically implemented using an optimized high-temperature process, followed by the creation of wells, channel doping, gate formation, and source and drain implants, optionally with halo and other implants, to set threshold voltage and control short channel effects. The STI process is typically performed at high temperatures (over 900 degrees Celsius, with 1000 degree Celsius plus temperatures being often used) that. In the case of a DDC transistor process, preferably, the STI is performed later in the wafer processing flow, that is, after the formation of the transistor channels where the wells are doped and then the screen and threshold voltage doping steps are performed, and then a blanket epitaxial silicon layer is deposited thereon. Preferably, the STI structures are formed using a relatively low temperature (LT) process after the blanket epitaxial silicon layer is formed. The LT STI process is selected to assure proper step coverage and quality of the STI without causing unwanted diffusion of the DDC dopant structures.
Exemplary STI-last or isolation-last structures and processes are more completely described in U.S. Pat. No. 8,273,617, entitled “Electronic Devices and Systems, and Methods for Making and Using the Same”, U.S. patent application Ser. No. 12/971,884, entitled “Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof”, and U.S. patent application Ser. No. 12/971,955, entitled “Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof”, all of which are herein incorporated by reference in their entirety.
In addition to STI, other process flows involving high temperature may be used. For instance, in DRAM processes, several high temperature steps may be used to integrate structures into the substrate, for instance, the trench capacitor. Typically, DRAM integrated circuits include periphery circuits that include digital logic. The periphery circuits may use STI, typically at an elevated temperature that otherwise is compatible with the DRAM cell process flow thermal budgets.
Some IC designers may prefer to integrate device types having different designs, to take advantage of the strengths of particular devices or to be able to reuse existing circuit designs in certain SoC areas and only redesign or port a circuit design in other SoC areas. For instance, IC designers may wish to use DDC transistors only in the SRAM blocks or only in the digital logic (or both) while using other transistors, for instance, conventional CMOS, FinFET or other transistors, on other SoC portions.
The present technology provides various structures and processes that can be used for effectively integrating different transistor designs across a process platform. In some embodiments, the present technology in effect uses “STI last” for some devices, for instance, DDC devices, and “STI first” for other devices, with all STI processes being kept at a reduced temperature. In other embodiments, the order of forming devices may be switched; that is, the non-DDC devices may be formed first at least through the high temperature process steps, then masked off, and then the DDC devices may be formed, in part or all the way through and including the gate and source and drain sequences. A bifurcated process is described in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation process, and other devices may be formed thereafter. Effectively, this results in an IC in which some transistor types are manufactured from a STI-first process perspective and some from a STI-last process perspective, but without the need for separate STI processes. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets. Alternatively, the present technology includes a bifurcated process in which the high-temperature steps are performed first, for instance, high temperature STI or high temperature trench capacitor, then the DDC devices are formed at reduced temperature.
The present technology allows for low cost, high reliability manufacture of various device types and in particular, device types that are distinguished by threshold voltage of a transistor. For example, certain logic transistors may require a low threshold voltage (low Vt) for high speed switching, while other transistors on the same die may have a high threshold voltage that greatly reduces off-state leakage. A range of Vt values can be implemented using the present technology if it is desired to achieve a range of Vt values by combining DDC transistors with other transistor designs. Although the exemplary embodiments will be discussed herein primarily with respect to STI device isolation processes, it should be noted that the present technology is not limited in this regard. Rather, any other known or future device isolation processes can be used with the present technology. Additionally, although the context is provided as DDC transistors with conventional planar CMOS transistors, other combinations of transistor designs can be substituted within the scheme described herein with some transistors being fabricated from an “STI last” perspective and other transistors being fabricated from an “STI first” perspective on the same wafer. Further, an embodiment includes a hybrid, bifurcated process wherein the “STI first” or other such high temperature process, for instance, trench capacitors, are performed first, in portions of the wafer, and later, the DDC devices are fabricated in their wafer regions at a reduced temperature.
In some embodiments, a low temperature STI process can be used to limit the amount of dopant diffusion of any dopants introduced prior to the STI process, as noted above. Note that reference to a “low temperature” STI process refers to an STI process that is generally carried out at reduced temperatures compared with the standard, but how “low” the temperature is for low temperature STI is relative and not absolute and the particular temperature conditions selected for the STI are variable. In general, the temperature of a “low temperature” process will be selected based on the thermal cycle needs for the transistor channels fabricated prior to the STI process.
Although the preceding discussion is directed to the use of LT STI processes, the various embodiments are not limited in this regard. In other embodiments, a high temperature STI process, for instance, at temperatures of approximately 1200 degrees C. or more, can be used in some embodiments. In such embodiments, such STI processes are used in conjunction with adequate diffusion blocking steps in order to avoid unwanted migration of dopants formed prior to the STI process. For example, buffer layers or carbon or any other diffusion inhibiting species can be used to block migration of dopants to allow for an elevated temperature for the STI process. As a result, the amount of diffusion of dopants incorporated prior to performing STI can be limited by incorporating such diffusion inhibiting species, despite the high thermal budget of the high temperature STI process. Still further, a high temperature STI process may be used first, prior to formation of DDC structures which may be formed in their own selected regions in a subsequent step, while the high temperature regions are masked off.
As noted above, certain types of transistors benefit from a STI-last process, such as DDC and for that matter, slightly doped channel (SDC) transistors. In a typical process flow for such transistors, a well is formed and then the top of the well is further doped to form a heavily doped layer, i.e., a screening layer. Then, a threshold voltage (Vt) adjust layer may be incorporated. Then, a blanket epitaxial layer is deposited on the wafer, extending across multiple dies and transistor die blocks. The blanket epitaxial layer (blanket epi) forms a new surface for the wafer. Additional dopants can then be introduced to further adjust the Vt, for instance, to form SDC transistors or to form the doped channels for conventional transistors. In certain embodiments, the screening layers, Vt adjust layers, or other transistor structures can be formed with minimal implant energies to reduce scattering, and with precision because of the lack of STI structures to otherwise set up for proximity effects. Note that a dopant diffusion inhibitor such as a carbon buffer layer can be added to limit dopant migration. Such devices benefit from an STI-last process for many reasons, for instance, by using STI-last, blanket epitaxial deposition can be used to achieve a uniform channel thickness particularly in those areas of DDC and SDC doped regions where the depth of the doped screen and Vt adjust layers affect the Vt set.
Although the present technology will be described primarily with respect to STI-last processes for DDC and SDC transistors, it is noted that other types of devices can be manufactured using the present technology. For example, certain FinFET devices can be integrated with the present technology, such as those described in International Application No. PCT/US12/49531, entitled “Semiconductor Devices Having Fin Structures and Fabrication Methods Thereof” and which is herein incorporated by reference in its entirety.
Optionally, in some embodiments, during the remainder of wafer processing, various device temperature dependent dopant profiles resulting from global or selective (e.g. masked rapid thermal annealing) can be formed at least in part from differential out-diffusion of the screen layer into the epitaxial channel layer. This provides distinct transistor devices with different channel thickness and dopant concentration.
In some embodiments, halo implants, channel implants or other suitable techniques can be used to dope the channel as required to form conventional, doped channel transistors. For practical reasons, a designer may opt for using conventional transistors for portions of the SoC so that the pre-existing circuit-designs can be reused with no to minimal conversion of the circuit-designs for the new semiconductor process. Inefficient and unreliable doped channel transistors that have been designed in can be used in conjunction with DDC or SDC transistors used in other blocks. The doped channel transistors can be updated and modified later to incorporate power efficient DDC type transistors.
FIG. 1 is a schematic illustrating certain features of representative process 10 capable of forming a basis for manufacture of transistors with or without a doped channel. Device types that can be manufactured by the illustrated process can include, but are not limited to, doped or undoped DDC transistors, SDC transistors, conventional bulk planar CMOS transistors, or other transistors such as FinFET. Applications for such varied transistors include digital or analog, high or low power, or high or low speed, achieved by high, low, or regular or no threshold voltage set. The transistors may be statically or dynamically body biased and/or be used for specialty applications such as power management, high speed signal transfer, latches, clocks, oscillators, SRAM, capacitor coupled DRAM, or combinations of the foregoing or other applications. Device types are primarily distinguished by threshold voltage, but each device type has its own mobility, transconductance, linearity, noise, power, application (e.g. signal processing or data storage), leakage or any other characteristic of interest. Since modern SoCs or other complex electronic die may require dozens of different device types for operation, structures that can be readily modified to form various transistor devices using an easily integrated process are advantageous for yield and reliability and cost.
Process 10 includes performing various pre-gate processes 12, including various combinations of implants, blanket epi formation, and STI formation and sequences. Thereafter, a gate module 13 can be performed, followed by post-gate implants 14, e.g., halo (as needed) and LDD implants. Finally, additional processes 15 can be performed, such as space formation, source/drain implants, and salicidation and other metallization processes.
As generally shown in FIG. 1 by variations of 12 at 12A-12D, certain steps of process 10 can be optional, reordered, modified, or omitted entirely to form the various types of transistors. For example, 12A represents a pre-gate process for limited to a low temperature (LT) STI formation process (LT STI process) followed by well implants, to form standard transistors. 12B represents a pre-gate process consisting of well implants, followed by blanket epi formation (optionally with blanket epi dopant implants or diffusions, followed by a LT STI process for forming DDC or SDC transistors. 12C represents a pre-gate process including first well implants, followed by a LT STI process, and subsequently second well implants. Finally, 12D represents pre-gate process including well implants followed by blanket epi formation. Thereafter a LT STI process is performed, followed by blanket epi implants. As illustrated above, the pre-gate processes can be configured such that transistors can be formed with or without an epitaxial layer capable of forming at least a portion of the channel. If an epitaxial layer is grown, it can be processed so that all or part of the epitaxial layer is undoped or slightly doped, as further discussed below. These representative pre-gate processes are presented only for illustrative purposes. In the various embodiments, any other pre-gate processes can be used.
Moreover, the process 10 shows that other processes (at 13, 14, and 15) can also include steps that are optional, reordered, modified or omitted as well. For example, the gate module 13 allows for polysilicon gate, metal gates, or any other type of gate structures to be formed. Post-gate implants 14 allows for using halo implants, additional threshold voltage setting implants, logic/memory implants, or any other types of implants, depending on device types for the IC.
Additionally, a combination of options can be used at 12, 13, 14, and 15. For example, SRAM devices can be formed by an initial well implant, followed by epitaxial layer deposition, and dopant diffusion into part of the epitaxial layer, with shallow trench isolation then being performed as part of an STI-last process module. After gate oxidation, lightly doped drains (LDD) can be formed, but care is taken to minimize dopant migration into the epitaxial channel by omitting halo implants, threshold voltage implants, or other processing techniques that could promote or allow dopant contamination of the channel. In contrast, a high threshold voltage transistor with a doped channel can require halo implants after an initial low temperature STI and well implant processing (bracket 12A). As will be appreciated, other process module combinations suggested by the Figures and disclosed herein are also available to manufacture a broad range of device types.
Although some embodiments rely on the lowering of the processing temperatures for STI formation, in other embodiments, the LT STI process can be combined with other low temperature processes to further lower the thermal budget. Thus, in some embodiments, manufacture of certain known transistor types or future transistor types for which STI-last processes are preferred but that require even lower thermal budgets can be provided by an overall lowering of the thermal budget. This is discussed in further detail with respect to FIG. 2.
FIG. 2 is a schematic illustration comparing and contrasting a conventional, high temperature (HT) processing flow 20 and an improved low temperature processing flow 22 that can support manufacture of multiple transistor device types in accordance with the present technology. In processing flow 20 the high thermal budget steps (>900 degrees Celsius) are identified by shading in FIG. 2. These include the steps for STI, well implant anneal, Insulator Liner, LDD implant anneal, and S/D implant. Well implants, gate formation, first spacer formation, LDD implants, second space formation, source/drain implants, stress memorization technology (SMT), salicide formation, and contact etching stop layer (CESL) formation are typically performed using low thermal budget processes.
In process flow 22, instead of using high temperature processing, low temperature processing of preferably less than 900 degrees Celsius can be used for STI and as well for any of the well anneals, LDD anneals, S/D anneals, and gate/gate oxide (Gox) processing, or any of the other HT steps from process flow 20. In the various embodiments, the temperature can be higher than 900 degrees Celsius, yet still provide low temperature processing. As noted above, for the process to be considered “low temperature”, the temperature of the anneals is reduced by comparison to avoid migration of dopants—the “low temperature” can be higher with incorporation of migration stop layers, for instance, or by the selection of dopants that are not so diffusing, or both. Accordingly, as used herein with respect to a process, the terms “low temperature” or “LT” shall refer to a process performed at a temperature that provides little or no migration of at least one dopant species introduced prior to the STI process.
Typically, bulk wafer processing temperatures in a LT process flow are maintained between 600 and 950 degrees Celsius, with temperatures below 900 degrees Celsius being preferred, though temperatures as high as 1100 degrees Celsius can be tolerated at reduced anneal time. Put another way, since the major concern regarding increased thermal budgets is the diffusion of species, LT processes can encompass higher temperature processes (>900 degrees Celsius) but performed over short periods of time. For example, rapid thermal annealing (RTA) using laser, flash lamps or other rapid heating processes can transiently raise surface temperature of the wafer on a millisecond to multiple second time scale. However, RTA temperatures up to 1000 degrees Celsius (with less than 950 degrees Celsius preferred), laser heating temperatures up to 1300 degrees Celsius, and spike temperatures up to 1100 (with less than 1060 degrees Celsius preferred) are acceptable for short times, as long as bulk wafer temperatures remains below 950 degrees Celsius. However, even if transient high temperature annealing schemes such as RTA or laser annealing are used for certain process steps, use of a true low wafer bulk temperature processing scheme is preferred to reduce dopant migration or diffusion and help ensure desired dopant profiles are maintained.
The following Table 1 illustrates some example temperature ranges and processing conditions used to manufacture a representative DDC device as part of a LT process flow. As will be understood, in the following Table 1, specific process steps, temperatures, and times can be adjusted to suit available tooling, device types, and process nodes. Generally, as device size decreases, the temperatures and times used to process wafers will also decrease.







TABLE 1







Exemplary LT Process Conditions for Manufacturing DDC Devices









Process Step
Thickness
Process Conditions (temp/time)














Pad Oxide
1.5-10
nm
ISSG
800-820 C. 5-60 sec


Pad Nitride
5-150 
nm
Furnace
<900 C.










STI Etch

Chemical 





Etch












Liner Oxide
1-5 
nm
ISSG
800-820 C. 5-50 sec










Gap-Fill Densification

HDP
None


(Either HDP or HARP or

HARP
700-800 C., 


hybrid can be used)


30-200 min or





800-850 C. <60 sec


GOX1, GOX2

ISSG
850-900 C. 10-





40 sec




Furnace
725-775 C. 5-





60 min


GOX3

ISSG
850-900 C. 5-





30 sec









Gate nitridation
DPN
<700 C.


Gate Anneal (post nitridation anneal)
PNA
800-900 C.









The process conditions listed above are provided for illustrative purposes only. In the various embodiments, other process conditions can be specified to provide LT processes.

In the case of adoption of a LT STI process, alone or in combination with any other low temperature processes, the actual order of the doping steps with respect to the STI process can vary depending on the device types to be manufactured on the same wafer or die or the device types that are planned to be manufactured using the same or similar process conditions. However, the various embodiments do not require the implementation of DDC or SDC devices or for that matter, performing any steps prior to the LT STI process. Rather, in some embodiments, manufacturers can adopt a LT process for IC designs irrespective of whether the LT process is used for DDC or SDC. For instance, a semiconductor manufacturer may elect to implement a LT process and sometime thereafter, incorporate DDC or SDC transistors therein. Preferably, the LT process is used to secure the dopant profiles desired for the transistor channels. Certain transistor channels can be formed before STI; other transistor channels can be formed after STI. A blanket epitaxial layer facilitates the finalization of the channel formation or serves as a substrate for channels after epitaxial formation. STI is formed after blanket epitaxial growth but, for those transistor channels formed post STI, such transistor channels in effect use an “STI first” process. In the case of incorporating DDC devices, the process flow adds masking steps for performing pre-STI implants, including screening layer implants and Vt adjust implants, and then forming of blanket epi. Thereafter, the STI and other previously existing steps can be performed without significantly affecting the performance of the DDC device. In this way, a SoC design can be updated to be formed entirely or in part of DDC transistors.
To illustrate the variety of devices easily manufactured via low temperature processing and a flexible positioning of well implants and STI isolation in the overall process timing, FIG. 3 is provided. FIG. 3 is a schematic illustrating a mask flow and layout 30 for SoC dies accommodating various transistor types and corresponding STI timing. The dies resulting from such mask flows can include, but are not limited to, die having only DDC transistor device types, or alternatively, transistor device types (including doped channel transistors) in several different combinations with DDC. In FIG. 3, a masking position of a screen implant is generally indicated, while position of PMOS and NMOS, DDC or non-DDC transistor blocks of HVt or SVt core logic, SRAM, and analog are shown. Combinable transistor devices include other types of planar devices including legacy doped-channel devices, as well as modern three-dimensional gate devices including FinFET transistors that are built upwards from a pre-formed channel as a substrate.
As another example of transistor manufacture on a wafer supporting multiple die, FIG. 4 shows semiconductor wafer 400 having a semiconducting surface supporting multiple die 442 with multiple device combinations. As previously discussed, each die can support multiple transistor device types, and the device types can be manufactured alone or in combination with each other, permitting the creation of a complex system on a chip (SoC) or similar die that optionally include analog, digital, legacy or improved transistors such as described in this disclosure. For example, four useful device blocks in a single die are illustrated as follows: block 444 outlines a collection of deeply depleted channel (DDC) transistors; block 445 outlines slightly depleted channel (SDC) transistors with some channel doping which can be achieved either by separate channel implant or by way of a controlled out-diffusion of previously-implanted dopants; block 446 outlines conventional channel doped transistors; and block 447 outlines undoped channel analog transistors. As will be appreciated, these transistor types are representative and not intended to limit the type of transistor device types that can be usefully formed on a die or wafer. The wafer 400 includes a substrate 402 (typically silicon), a lightly p-doped silicon layer 404 that can be secondarily implanted with optional anti-punchthrough (APT) layer (not shown), a screening layer, and an epitaxial blanket layer 406 of silicon, silicon germanium, or other suitable channel material grown after implantation of dopants in layer 406. For purposes of facilitating the description of the embodiments relating to the flexible low-temperature STI process herein, when multiple devices are presented, the devices described will be planar and ranging from DDC devices to legacy planar devices. The embodiments can be used in the context of the same type of devices, however. It shall be further understood that the embodiments presented herein are extendable and can be used in a wider range of device types including DDC, SDC, legacy, JFET, planar bipolar, and three-dimensional gate structures.
To better understand possible processing variations for the present technology, another embodiment of a portion of a transistor manufacturing process is illustrated by FIG. 5. FIG. 5 is a flowchart of steps in an exemplary method 500 for manufacturing transistors. Method 500 begins with step 502 in which a wafer is masked with a “zero layer” alignment mask. This can be performed via a series of masking, photolithography, and etch processes. Thereafter, at step 504, an N-well can be formed. Optionally, this step can also include forming a deep N-well in combination with a conventional N-well. After the N-wells are formed at step 504, a highly doped screen layer and/or Vt set implant for devices in the N-wells can be performed at step 506. These implants can be performed using the same or different dopant species. Optionally, dopant species with increased or decreased silicon diffusivity can be selected. Thereafter at step 508, the N-well is masked and the P-well is implanted. After the P-wells are formed at step 508, a highly doped screen layer and/or Vt set implant for devices in the P-wells can be performed at step 510. These implants can be performed using the same or different dopant species. Optionally, dopant species with increased or decreased silicon diffusivity can be selected. Optionally, other well implants such as an APT implant can also be formed in the respective P and N-wells, before or after the respective screen layer implantations at steps 506 and 510. Each of the foregoing steps can be performed by a combination of masking, photolithography, and/or etch steps, followed by implantation steps and subsequent cleaning steps. Additional steps not described here can also be performed to provide the implants listed above in appropriate regions.
Next, at step 512, a capping silicon blanket epi is deposited or grown across the entire substrate to a preselected thickness. The preselected thickness can be such that it enables a degree of planarizing down from the top surface during subsequent processes (as needed, preferably using chemical mechanical polish) and provides a sufficient maximum silicon channel thickness for selected devices to be DDC devices. Typically the blanket epi is silicon, but silicon germanium or other non-silicon in-situ deposited atoms can also be added to the epitaxial layer either across the substrate or at a preselected device location using masks.
At step 512 or prior to, an optional carbon or other migration stop layer can be formed. In some embodiments, carbon can be implanted into the surface region of the doped wells prior to forming the blanket epi. In other embodiments, carbon or other diffusion inhibiting species can be incorporated into the blanket epi. In either case, the presence of carbon or other diffusion inhibiting species between the doped wells and the blanket epi inhibits the diffusion upward of the implanted species in subsequent steps. For example, carbon or other diffusion blocking species can be provided when a LT STI process is not possible or available.
Following the formation of the blanket epi at step 512, the LT STI process can be performed at step 514. As noted above, this involves forming trenches as isolation structures between devices or wells via patterning and etching. Thereafter, the trenches are filled with electrically insulating materials. In some embodiments, an optional temperature cycling may then be performed before, after, or during the STI process to cause the screen layer dopants in certain devices to migrate selected distances upward into the silicon channel. The distance upward can be determined by the temperature and time of the thermal cycling, as well as the extent of diffusion inhibiting or diffusion enhancing materials contained in the devices.
Gate structures, spacers, contacts, stress implants, tensile films, dielectric coatings, and the like are then formed, resulting in operable transistors. For example, at step 516, gate structures can be formed. The formation of these gate structures can be preceded or followed by processes to complete the legacy transistors. For example, additional channel doping can be done at step 516 using halo implants after formation of the gate structures and/or traditional channel implants before the gate structure is formed. Finally any additional steps for completing the transistors and the die can be performed at step 518, such as spacers, metallization, etc.
As noted above, the aforementioned methods of manufacture are particularly advantageous for DDC devices. Various advantages and possible process variations for forming DDC devices are discussed in U.S. Pat. No. 8,273,617, entitled “Electronic Devices and Systems, and Methods for Making and Using the Same”, U.S. patent application Ser. No. 12/971,884, entitled “Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof”, and U.S. patent application Ser. No. 12/971,955, entitled “Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof”, all of which are herein incorporated by reference in their entirety.
One example of a DDC device that can be manufactured with LT STI and low temperature anneals according to the present technology is illustrated in FIG. 6. A DDC transistor includes a gate, source, and drain that together define a channel. In operation, the channel is deeply depleted, forming what can be described as deeply depleted channel with depletion depth under the gate set by a highly doped screening layer. As noted, while the channel is substantially undoped, the epitaxial layer may include simple or complex layering with different dopant concentrations. This doped layering can optionally include a distinct threshold voltage set layer with a dopant concentration less than that of the screening layer, positioned between the gate and the screening layer. A threshold voltage set layer permits small adjustments in operational threshold voltage of the DDC transistor and can be formed by out diffusion from the screen layer, in-situ or delta doping during epitaxial growth, with tightly controlled implants onto the screening layer prior to the epitaxial layer formation, or through the epitaxial layer using a dose and energy selected to result in a threshold voltage set layer embedded a pre-defined distance below the gate. In particular, that portion of the channel adjacent to the gate should remain undoped. Now turning to FIG. 6, there is shown, an exemplary DDC transistor 100 including STI regions 101 and a gate 102, which can be made of any preselected gate material such as polysilicon or a metal gate and an epitaxially grown layer (indicated by bracket label 120) that can support multiple doped layers having substantially different dopant concentrations (with channel layer 104 and an optional threshold voltage set layer 106 being shown). All layers are supported on substrate portion 116 built in bulk silicon 114, such as a silicon substrate. In substrate portion 116, a screen layer 108 is defined, at the surface of substrate portion 116, having a dopant density greater than any layers in epitaxially grown layer 120. Optionally, APT 110 or well/deep well layers 112 are also defined in substrate 116 below the screen layer 108. Vt set layer 106 is directly above screen layer 108. Relative dopant concentration between the gate 102 and the bulk substrate region 114 are indicated by adjacent graph 130, which shows the successively decreasing dopant concentration above and below the screen layer 108 to form a stepped, notched profile.
In device 100, the threshold voltage of transistor 100 can be set, at least in part, by appropriate selection of the thickness of epitaxial layer 120, as well as the positioning, concentrations and thicknesses of one or more dopant layers of varying dopant concentration into the epitaxial layer 120, the presence or absence of lightly doped drains extending into the channel (not shown), or material selection of the metal gate. Implanted dopants can include conventional P or N type dopants in varying concentrations and with varying silicon diffusivity, counter-dopants, or atoms/techniques selected to modify silicon crystal structure or act as dopant diffusion inhibiting (e.g. carbon) or enhancement agents/mechanisms (rapid thermal transient enhanced diffusion, crystal structure changes, silicidation).
In certain embodiments, a single blanket epitaxial layer 120 is formed having a constant thickness and used across the wafer to 1) extend across multiple device types, 2) to extend across multiple blocks of differing device types on a die, 3) to extend across the entire die, or 4) to extend across the entire wafer without making any adjustments to the thickness of the deposited epitaxial layer. To assure best epitaxial layer thickness consistency, a blanket epitaxial layer across the entire wafer or at least across significant portions of die on a wafer is preferred. If local thickness changes to the epitaxial layer are required, then such adjustments can be made by selective etching and/or selective epitaxial growth (e.g. to form, for example, raised source/drains). However, the distance between the gate and the screen can also be specifically varied by controlled diffusion of pre-implanted dopants, so that the effective thickness of the epitaxial layer for a given transistor channel can be modulated. Additionally, channel or halo dopant implants can be used with or without a pre-existing screen to achieve a preselected device type with selected operating characteristics such as threshold voltage.
In certain embodiments, the screening layer 108 is doped to have a concentration between about 5×1018 dopant atoms per cm3 and about 1×1020 dopant atoms per cm3, significantly more than the dopant concentration of the undoped channel layer 104. The channel layer 104 can have a dopant concentration on the order of 1×1017 dopant atoms per cm3, and at least slightly less than the dopant concentration of the optional voltage threshold set layer 106. In the various embodiments, the exact dopant concentrations and screening layer depths can be selected to achieve or improve desired operating characteristics, or to take into account available transistor manufacturing processes and process conditions. In any event, the screening layer thickness and dopant concentration and distance from the gate are defined to form a reservoir of dopants to screen the well from the channel and define the depletion depth when a voltage is applied to the gate, while at the same time minimizing the junction leakage.
As shown in FIG. 6, APT layer 110 can optionally be formed beneath the screening layer 108 to further help control leakage. Typically, an APT layer is formed by direct implant into a lightly doped well, but such a layer can also be formed by out diffusion from the screening layer, via in-situ growth, or other known processes. The APT layer has a dopant concentration less than the screening layer, typically set between about 1×1018 dopant atoms per cm3 and about 1×1019 dopant atoms per cm3. In addition, the APT layer dopant concentration is set higher than the overall dopant concentration of the well substrate. In the various embodiments, the exact dopant concentrations and depths can be modified to improve desired operating characteristics of the transistor, or to take in to account available transistor manufacturing processes and process conditions.
As described above, the threshold voltage set layer 106 is positioned above the screening layer 108 and preferably extending across and contacting the screening layer 108. Typically, such a layer is formed as a thin, doped layer. In certain embodiments, delta doping, controlled in-situ deposition, or atomic layer deposition can be used to form a plane of dopants that is substantially parallel and vertically offset with respect to the screening layer. Alternatively, the threshold voltage set layer 106 can be accomplished by way of controlled diffusion of screen dopant material upward a distance into the channel layer 104 to a preselected depth below the gate 102. Suitably varying dopant concentration, thickness, and separation from the gate 102 and the screening layer 108 allows for controlled and fine adjustments of threshold voltage in the operating transistor. In some embodiments, a positioning the screening layer 108 so that it abuts the source and drain and is above the bottom of the source and drain but below the LDD helps to simultaneously enable a stable threshold voltage while controlling junction leakage and other metrics. In certain embodiments, the threshold voltage set layer is doped to have a concentration between about 1×1018 dopant atoms per cm3 and about 1×1019 dopant atoms per cm3. The threshold voltage set layer can be formed by several different processes, including 1) in-situ epitaxial doping, 2) epitaxial growth of a thin layer of silicon followed by a tightly controlled dopant implant (e.g. delta doping), 3) epitaxial growth of a thin layer of silicon followed by dopant diffusion of atoms from the screening layer, 4) deep screen implants coupled with shallow surface doping by plasma doping or other suitable technique, followed by epitaxial growth, 5) by any combination of these processes (e.g. epitaxial growth of silicon followed by both dopant implant and diffusion from the screening layer).
The channel contacts and extends between the source and the drain, and supports movement of mobile charge carriers between the source and the drain. Channel thickness in the undoped portion can typically range from 5 to 50 nanometers, with exact thickness being dependent on desired transistor operating characteristics and transistor design node. For example, a 20 nm gate length transistor will typically have a thinner channel thickness than a 45 nm gate length transistor. In certain embodiments, dopant migration resistant layers of carbon, germanium, or the like can be applied along with or above the screen layer to further limit dopant migration.
In some embodiments, it may be desirable to use transistors having more legacy or standard transistor-characteristics instead of DDC in certain portions of SoCs. However, desired Vt control with mobility, DIBL and drive current and other effects more characteristic of DDC would be sacrificed. A reasonable alternative in some embodiments, then, is to use SDC transistors. SDC transistors can be designed for higher Vt settings compared to DDC devices, and can provide improved functionality over legacy or standard devices.
SDC transistors typically use a screen layer and epitaxial layer as a starting point, as in the case of DDC. However, an SDC transistor is distinct from a DDC transistor in that implants, in-situ epitaxial growth, deliberate screen layer out-diffusion, or other dopant positioning method is used to purposely place a significant amount of dopants in the epitaxial layer but not to such levels as would be the case for legacy or standard transistors. With SDC transistors, most, if not all, of the channel layer 104 will be doped to a certain extent, in contrast to the undoped channel layer of a DDC transistor. The concentration and uniformity of dopants can vary, but the doping concentration for the channel layer 104 will be a concentration between that of the undoped channel layer in DDC transistors and the highly doped channel layer in conventional or legacy transistors. An SDC transistor is distinct from conventional or legacy transistors not only in the dopant concentrations and structure but also in certain fundamental characteristics of the transistor, namely, better Vt control, lower DIBL, and higher drive current. However, as will be appreciated, while mobility in the channel and Vt variations for an SDC transistor are improved relative to a conventional transistor, an SDC transistor will not generally have as high mobility as comparable DDC devices. Further, Vt variations in SDC transistors, locally, globally, or both, will generally not be as low as that observed in a comparable DDC transistors. However, SDC easily integrates with a DDC a process flow.
A doped channel transistor (also known herein as “conventional” or “legacy” transistor) is generally a conventional field effect transistor that is characterized by having dopants in the channel, either by way of halo dopants or channel implants or both, so as to set threshold voltage. Threshold voltage implants, channel dopant implants, and halo implants can all be used in the foregoing process to build legacy transistors while using a low-temperature STI process. Such legacy devices are preferably formed after the low-temperature isolation regions are created, though if a channel implant is used, the channel implant can optionally occur before the STI process or can be done after the STIs are formed. The undoped blanket epi is formed prior to STI. For the conventional transistors, the undoped blanket epi serves as the substrate for the transistor channel. While legacy transistors have significantly inferior mobility, reduced drive current and increased DIBL and increased noise as compared to DDC or SDC transistors, die that incorporate legacy transistors into pre-ordained areas can be practical for avoiding additional work to port circuit blocks. In additional to a doped channel transistor, embodiments herein contemplate forming other types of devices, for instance, DRAM, flash memory, analog and other devices that may traditionally include the use of high temperature processes, together with DDC and/or SDC devices.
FIGS. 7A and 7B schematically illustrate selected structures, processing steps, and an exemplary resulting dopant profile in a SoC 200 during manufacture. In particular, FIGS. 7A and 7B show exemplary structures and processing steps prior to STI and after STI, respectively.
As seen in FIG. 7A, the devices are constructed on a common substrate 216. The substrate 216 can be implanted with dopants to provide an initial dopant profile 202. The dopant profile 202 roughly defines layers that will result post-processing in at least three distinct layers, including the screen layer 204, APT layer 205, and well 207, all supported on substrate 216. The dopant concentration typically peaks at or near the surface of substrate 216 in the screen layer 204. For those devices where screen layer 204 should not be allowed to migrate upward, an optional capping layer made of carbon or other diffusion inhibiting material can be doped on top of or within the screen layer 204.
As seen in FIG. 7A, a blanket epi layer 206 is subsequently grown on substrate 216. The blanket epi layer 206 can be intrinsic silicon, silicon germanium, or other channel material. Thereafter, an STI process can be applied to form STI regions 208 and can be used to define at least two distinct device types 210 and 220 separated by STI regions 208, as shown in FIG. 7B. Note that although not shown, a Vt set layer can be incorporated into device 210 to create a stepped or notched dopant profile. Further tuning of Vt can be achieved as desired by varying screen layer thickness and depth, by way of a separately defined implantation step or a combination of both, preferably before formation of blanket epi layer 206 but fine adjustments to Vt can be made after epi layer 206 is formed.
Before or after forming of STI regions 208, portions of the blanket epi layer 206 that will respectively form different devices types 210 and 220 in FIG. 7B can be differentially treated with constant or graded profile carbon or other diffusion inhibiting or diffusion enhancing implants. The thermal cycles (including optional rapid thermal processing) for annealing are specially designed to minimize diffusion of dopants or to achieve preselected migration levels of the dopants for one or more devices to result in channel doping characteristics specific to the devices. To further control the degree of diffusion, a low temperature STI recipe should be used. The thermal or annealing cycles can also be selected to minimize dopant migration, though in certain processing cases if desired, the thermal or annealing cycles can serve to allow for a controlled diffusion to result in a pre-selected dopant profile in the channel, with some portion of the channel remaining undoped, as specified for the desired device characteristics. The controlled diffusion is achievable because of the differential carbon concentrations for selected devices, so that upward diffusion of the screen and ultimate thickness of the screen layer and resulting channel layers 214 to 224 in FIG. 7B (which will be positioned between the gate and the screen layer in the finished transistor) are different for different devices.
Alternatively or in addition, the process can be implemented to result in device 210 and preferably, STI 208, and then, additional dopant species can be implanted in selected portions of the blanket epi 206 to form device 220. In both alternatives, different dopant profiles 212 and 222 in the transistor channel are achieved. As can be observed, the diffusion of dopants results in the screen layer 204 slightly increasing in thickness (as indicated respectively by the length differential between arrows 204A and 204B) for device 210. In contrast, the screen layer 204 significantly increases in thickness for device 220 (as indicated respectively by the length differential between arrows 204C and 204D). Afterwards, the process proceeds to formation of gate and source/drain structures (not shown) to form the transistor devices 210 and 220.
Applying the same operating conditions to devices 210 and 220 with such variations in thickness of the screen layer 204 will result in device groupings having distinct threshold voltages, despite sharing the same epitaxially grown channel, the same thermal processing/anneal conditions, and having similar gate lengths. However, those devices that are formed to result in DDC or SDC transistors will have noticeably better threshold voltage variation compared to the legacy transistor devices.
As another example, FIGS. 8A and 8B schematically illustrate selected structures, processing steps, and dopant profiles in the manufacture of a SoC 300. Similar to FIGS. 7A and 7B, FIGS. 8A and 8B show the processes, structures, and dopant profiles before and after an STI process, respectively. Specifically, FIGS. 8A and 8B illustrate one configuration for including DDC devices and legacy devices on a same die.
As seen in FIG. 8A, the devices are constructed on a common substrate 316. The substrate 316 can be implanted with dopants to provide an initial dopant profile 302. The dopant profile 302 roughly defines layers that will result post-processing in at least three distinct layers, including the screen layer 304 (with screen thickness 304A), APT layer 305, and well 307, all supported on substrate 316. Alternatively, for the legacy devices, the screen layer 304 can be omitted. The dopant concentration typically peaks at or near the surface of substrate 316 in the screen layer 304, and as will be appreciated, one or more dopants having different diffusivity characteristics can be co-implanted. For those devices where screen layer 304 should not be allowed to migrate upward, an optional capping layer made of carbon or other diffusion inhibiting material can be doped on top of the screen layer 304.
As seen in FIG. 8A, a blanket epi layer 306 is grown on substrate 316. The blanket epi layer 306 can be intrinsic silicon, silicon germanium, or other channel material. Thereafter, an STI process can be applied to more STI regions 308 and can be used to define at least two distinct device types 310 and 320 separated by STI regions 308, as shown in FIG. 8B
For the at least two distinct device types 310 and 320 separated by isolation structure 308, separate Vt settings can be achieved by way of a screen layer concentration and depth from the gate for device 310, and by way of channel or halo dopants or both, for device 320.
As seen in FIGS. 8A and 8B, an STI process is performed such that the STI extends through blanket epi layer 306, screen layer 304, APT layer 305, and at least a portion of well 307 to define STI regions 308. Note that the epitaxial layer 306 can be intrinsic silicon, silicon germanium, or other channel material. The STI can be formed using, for example, a low temperature or high temperature process including a combination of trench etch, liner formation and dielectric fill. Further, before or after STI regions 308 are formed, portions of the epitaxial layer 306 that respectively form device types 310 and 320 can be differentially treated with constant or graded profile carbon or other diffusion inhibiting or enhancing implants.
For the exemplary device 310, a carbon migration stop layer at a sufficient concentration can be used such that the upward diffusion of the screen and ultimate thickness of the screen layer and channel layer 314 for device can be defined. For example, as shown in FIG. 8B, an intermediate threshold set layer 309 can be defined having an intermediate dopant concentration between the doping concentration of the channel 314 and screen 304 (with screen 304 being somewhat expanded into the epitaxial layer 306) by either implant of dopants onto screen 304 or by diffusion during thermal cycling to result in a doped layer having a thickness 304B.
Thermal cycling is then carried out so that dopants 304D diffuse upward to form at least the foundation for a legacy transistor channel. The wafer can then be masked to protect that portion of the substrate having devices 310-, and additional dopant species can be implanted 321 solely in the portion of the substrate that to form device 320. In addition, direct channel or halo implants 321 (after formation of the gate) can be used to dope the channel of device 320.
In effect, the differences between effective diffusivity and implant conditions can result in different dopant profiles and are respectively illustrated as profile 312 and 322, with the screen layer 304 (if present) moderately increasing in thickness for device 310, and additionally forming an intermediate threshold voltage set layer 309. In contrast, the thickness of screen layer 304 greatly increases in thickness (as shown by the difference between 304C and 304D) for device 320 to substantially eliminate the previously undoped regions in blanket epi layer 306. Effectively, this forms a transistor having operation properties similar to a traditional channel doped legacy transistor.
After formation of gate and source/drain structures to form the transistor devices (not shown) and applying the same operating conditions, the device 320 will have a significantly different higher threshold voltage (high Vt) as compared to device 310 (regular Vt) because of the differing screen and channel dopant conditions, even while otherwise sharing the same thermal processing/anneal conditions, doping conditions, and having similar dimensions.
To better understand design selection parameters, required transistor structures, and suitable processes for manufacture of transistors having differing threshold voltages, the following Table, Figures, and Examples are provided. In the following table, a range of suitable materials, operating parameters, and the like are described for commonly required transistor device types that can be constructed according the present disclosure. In Table 2, C1, C2, and C3 refer to ranges of layer concentrations for the respective channel, voltage threshold set layer, and screen layer as indicated in FIGS. 1, t1, t2, and t3 respectively refer to thickness of the channel, voltage threshold set layer, and screen layer, and LVT, RVT and HVT respectively refer to a low Vt, a regular Vt, and a high Vt device.







TABLE 2







Target Parameters and Processing Conditions for Different Transistor types.












LVT
RVT
HVT
SRAM





VT range
[0.2 V-0.4 V]
[0.3-0.5 V]
[0.4-0.6 V]
[0.4-0.6 V]


Target doping
t1 [10-15 nm]
t1 [5-10 nm]
t1 [0-5 nm]
t1 [10-15 nm]


profile
t2 [0-5 nm]
t2 [5-10 nm]
t2 [10-15 nm]
t2 [0-5 nm]



C1 [0-1e17]
C1 [0-1e17]
C1 [0-1e17]
C1 [0-1e17]



C2 [1e17-1e18]
C2 [1e17-1e18]
C2 [1e17-1e18]
C2 [1e17-1e18]



C3 [1e18-1e19]
C3 [1e18-1e19]
C3 [1e18-1e19]
C3 [1e18-1e19]


Gate Stack
nMOS: N, 
nMOS: N, 
nMOS: N,
PMOS/NMOS 



pMOS: P
pMOS: P
pMOS: P
metal swap


Carbon in
Energy [1-5 keV]
Energy [1-5 keV]
Preferably no C
Energy [1-5 keV]


screen (nMOS)
Dose [3e14-2e15]
Dose [0-3e14]

Dose [3e14-2e15]


Screen dopant
nMOS: B, BF2, In
nMOS: B, BF2
nMOS: B, BF2
nMOS: B, BF2, In


species
pMOS: Sb
pMOS: Sb or As
pMOS: As
pMOS: Sb


Epitaxy
Undoped or 
Undoped
Undoped
Undoped, 



C-doped


or C-doped


Additional Halo
Preferably 0
dose: 
Dose: 
Preferably 0


implantation

[5e12-2e13]
[1e13-4e13]



Channel
Si or SiGe
Si or SiGe channel
Si or SiGe
Si


material
channel (pMOS)
(pMOS)
channel (pMOS)









An alternative embodiment to afore-described hybrid STI-first, STI-last flow is provided by the flow 900 in FIG. 9. The flow starts with a substrate 901. On the substrate, “high temperature” (HT) processes are performed only in selected regions 903. For instance, if the selected regions include forming legacy devices, the HT steps may be HT STI. In other instances, the HT steps may be relating to forming portions of a DRAM cell or flash memory block. When the HT structural portions are complete, the HT regions are blocked off with a mask 905. Then, optionally, the LT regions can be etched back 907 in anticipation of a to-be-formed epitaxial film. The etch-back can be minimal, simply to prepare the substrate to cleanly form the epitaxial film, or the etch-back can be more pronounced, in other words, etched sufficiently deeply so that when the epitaxial film is formed, the top surface can be more easily made planar. At step 909, the desired doping is performed. For instance, for NMOS DDC, there may be ion implantation of boron-species together with a carbon buffer layer created using a germanium pre-amorphization. For PMOS DDC, there may be ion implantation of antimony-species. To further prevent dopants from moving, particularly in the NMOS DDC regions, the ion implantation may be preceded with a thin layer of in-situ boron doped epitaxial silicon which may be formed selectively to the PMOS regions or formed on both the NMOS and PMOS regions with subsequent counterdoping to be done in the PMOS regions with extra arsenic or antimony or both. Instead of or in addition to DDC dopant profiles, SDC doping may be performed—for instance, using a more mobile dopant species in addition to the screen layer. After the DDC/SDC dopants have been emplaced, a film, preferably epitaxial silicon, is then formed in the LT regions 911, while keeping the HT regions sufficiently masked. Note that while epitaxial silicon is the preferred film, other films may be formed so as to serve as a substrate for the LT device, for instance, III/V semiconductors. During the LT process steps, care is taken to keep within a pre-selected thermal budget. The thermal budget is driven by the need to create and maintain the desired dopant profile for the DDC/SDC devices. The thermal budget may be higher, for instance, if DDC is used for PMOS only and SDC is used for NMOS. Or, with sufficient carbon or other migration stop techniques, a higher thermal budget may be used. After the epitaxial layer is formed, STI structures are created 913. Note that STI structures may be created in the LT regions only, or, if STI structures are desired in other parts of the die, the HT mask may be removed and LT STI may be formed in the other selected regions. Note further that other isolation structures alternative to shallow-trench style may also be used. Following formation of the isolation structures 913, the substrate processing can be completed by way of the other steps 915, for instance, formation of gate structures, source and drain, etc. While the flow of FIG. 9 involves using extra masks because of the formation of the high-temperature structures followed by formation of the low-temperature structures, the flow provides a flexibility around integrating low temperature processes when the high-temperature processes are to remain in place. The flow is useful for integrating DDC structures into an otherwise high-temperature process flow. However, the flow can be used in other device contexts beyond or alternative to DDC, where some devices should be formed using reduced temperatures while other devices should be formed at higher temperatures.
Now turning to FIG. 10, there is shown a plot demonstrating how gate work function selection can also be used in conjunction with varying channel/screen/threshold voltage set layer dopant concentration to adjust threshold voltage of various devices. Gate work function selection is particularly implementable using certain metal gate materials. For instance, TiN having a mid-gap work function of approximately 4.6 eV can be used as the metal material. The TiN work function can be adjusted as desired by selective nitridation or other means, thereby allowing for still another set point against which the transistor devices can be targeted using changes in screening layer concentrations, screen layer thickness and/or channel thickness. In FIG. 10, a PMOS device can require a certain metal selection, determinable by matching the desired work function to a desired Vt. This same metal can be used in at least some other device types by varying channel thickness, material, changing concentration and thickness of screen and/or threshold voltage layers, providing a design selection spread that can encompass, for example, a high Vt and a regular Vt device. This technique, known herein and in the Figures as a metal mid-gap reuse, allows for use of the same mask/metal in two or more devices, simplifying and speeding manufacture. A variation on this technique is metal swap, where the metal type which may or may not be a mid-gap work-function metal for a given NMOS and PMOS pair is swapped for the next NMOS and PMOS pair, with as much re-use of previously used metal material as possible. While metal mid-gap reuse techniques can allow for various threshold voltage settings for given device types with substantially the same metal type requirements, even greater Vt setting flexibility is possible when used in conjunction with well implant adjustments. For example, a SoC with SRAM transistors in the bit cell can have well dopants implanted before shallow trench isolation (STI). The screening layer is implanted before shallow trench isolation and a low doped or undoped epitaxial silicon layer is grown on top of the screen layer. A threshold voltage setting region is achieved by diffusion from the screen layer or by way of a pre-selected implant recipe performed before or after the epitaxial layer is grown. Then, the STI module is performed using a low-temperature liner. Following STI, if legacy devices are desired, then halo implants can be performed after gate formation into the undoped epitaxial layer to create a legacy device. Using low temperature processing, the channel under the gate may remain undoped, be slightly doped, or be heavily doped depending on the device operational specifications. In certain embodiments, a separate Vt set layer below an undoped channel may be provided by in-situ dopant implantation during growth, or selective diffusion of high diffusivity dopants from the screen.
Transistors created according to the foregoing embodiments, structures, and processes can be formed on the die alone or in combination with other transistor types. Certain of the transistors formed according to the disclosed structures and processes, namely, embodiments of DDC and SDC transistors, can have a reduced mismatch arising from scattered or random dopant variations as compared to conventional MOS analog or digital transistors. The ability to combine DDC and SDC transistors with other devices and cell structures is particularly important for allowing for improved circuit performance on certain die regions, for instance, SRAM, while sustaining cell structures in other areas, for instance, legacy devices to support legacy circuitry, or DRAM or flash memory or other blocks.
While various embodiments of the present technology have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present technology should not be limited by any of the above-described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

## Claims

1. A method of manufacture of an integrated circuit, comprising the steps of:
providing a substrate;
fabricating at least a portion of first integrated structures in at least one first area of the substrate using a first process that includes forming at least one of a trench capacitor, at least a part of a flash memory cell structure, or a first shallow trench isolation structure;
fabricating at least a portion of second integrated structures in at least one second area of the substrate, the fabricating of the portion of the second integrated structures comprising defining at least a first targeted dopant profile in the at least one second area and forming an epitaxial layer on the at least one second area, the first target dopant profile comprising a first section with a first doping concentration at a surface of the at least one second area defining a heavily doped screening layer and a second section below the first section with a second doping concentration less than the first doping concentration defining a well layer, wherein the fabrication of the portion of the second integrated structures includes using a second process that is at a reduced thermal budget compared with the first process; and
completing the first and second integrated structures to form the integrated circuit.

2. The method of claim 1, wherein the step of fabricating the portion of second integrated structures further comprises forming isolation structures in the epitaxial layer.

3. The method of claim 2, wherein the step of fabricating the portion of second integrated structures further includes the step of etching the at least one second area of the substrate to a preselected depth prior to forming the epitaxial layer.

4. The method of claim 1, wherein the step of fabricating the portion of second integrated structures includes forming doped regions using ion implantation in a process selected to result in the first target dopant profile.

5. The method of claim 4, wherein the step of fabricating a portion of second integrated structures includes etching the at least one second area of the substrate to a preselected depth prior to the forming of the doped regions, and forming an epitaxial layer after the forming of the doped regions.