# Patent

## Title
Single-pole component manufacturing

## Abstract

The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of U.S. application Ser. No. 10/168,040, entitled “SINGLE-POLE COMPONENT MANUFACTURING,” filed on Sep. 16, 2002 now U.S. Pat. No. 6,903,413, which prior application is herein incorporated by reference in its entirety.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of single-pole components in vertical monolithic form. The following description more specifically relates to components of Schottky diode type made in vertical form in silicon substrates.
2. Discussion of the Related Art
FIG. 1 illustrates a conventional Schottky diode structure. Such a structure includes a semiconductor substrate 1, typically made of heavily-doped single-crystal silicon of a first conductivity type, generally N type. A cathode layer 2 covers substrate 1. It is N-type doped, but more lightly than substrate 1. A metal layer 3 forms a Schottky contact with N-type cathode 2.
The thickness of layer 2 is chosen to determine the reverse breakdown voltage of the Schottky diode.
FIG. 2 illustrates the variation of the electric field E across the thickness of the structure shown in FIG. 1, along an axis A–A′. For clarity, the different portions of curve 10 of FIG. 2 have been connected by dotted lines to the corresponding regions of FIG. 1.
In such a homogeneous structure, the field variation per thickness unit is proportional to the doping level. In other words, the field decreases all the faster as the doping is heavy. It thus very rapidly drops to a zero value in substrate 1. Since the breakdown voltage corresponds to the surface included between the axes and curve 10, to obtain a high breakdown voltage, the doping of layer 2 must be minimized and its thickness must be maximized.
In the manufacturing of single-pole components, opposite constraints have to be considered. Single-pole components, such as the diode shown in FIG. 1, must indeed have as small a resistance (Ron) as possible, while having as high a breakdown voltage as possible when reverse biased. Minimizing the on-state resistance of a single-pole component imposes minimizing the thickness of the most lightly doped layer (layer 2) and maximizing the doping of this layer.
To optimize the breakdown voltage without modifying resistance Ron, structures of the type of that in FIG. 3 have been provided. In FIG. 3, a vertical Schottky diode includes a single-crystal silicon semiconductor substrate 31, heavily doped of a first conductivity type, for example, type N, and coated with a layer 32. Layer 32 is formed of the same semiconductor material as substrate 31 and is of same doping type, but more lightly doped. Layer 32 is intended for forming the cathode of the Schottky diode. A metal layer 33 covers layer 32. The metal forming layer 33 is chosen to form a Schottky contact with N-type silicon 32.
Layer 32 includes very heavily-doped P-type silicon regions or “islands” 34. Islands 34 are distributed over at least one horizontal level (over two levels in the example of FIG. 3).
Islands 34 are separate and buried in layer 32. The islands 34 of different horizontal levels are substantially distributed on same vertical lines.
FIG. 4 illustrates the variation profile of electric field E across the thickness of a structure similar to that in FIG. 3. More specifically, the profile of FIG. 4 is observed along axis A–A′ of FIG. 3.
As appears from the comparison of FIGS. 2 and 4, the insertion of heavily-doped P-type “islands” 34 in the structure of FIG. 3 modifies the variation of field E per thickness unit. Since islands 34 are much more heavily doped than N-type layer 32, there are more negative charges created in islands 34 than there are positive charges in layer 2. The field thus increases back in each of the horizontal areas including islands 34. By setting the doping and the number of islands 34, the space charge area can be almost indefinitely widened. In reverse biasing, the cathode formed by layer 32 and islands 34 thus generally behaves as a quasi-intrinsic layer. In average, the electric field variation per thickness unit thus strongly decreases. Thus, for a given doping level of layer 32, the breakdown voltage is increased, as illustrated by the increase of the surface delimited by the axes and the curve of FIG. 4 as compared to the corresponding surface of FIG. 2.
Accordingly, the structure of FIG. 3 enables obtaining single-pole components of given breakdown voltage with a resistance Ron smaller than that of a conventional structure.
The practical implementation of such a structure with islands is described, for example, in German patent 19,815,907 issued on May 27, 1999, in patent applications DE 19,631,872 and WO99/26,296, and in French patent 2,361,750 issued on Mar. 10, 1978. These different documents provide obtaining a structure similar to that in FIG. 3 by performing implantations/diffusions during a growth epitaxy of layer 32.
The repeated interruptions of the epitaxial growth are a disadvantage of such an implementation. Indeed, thick layer 32 thus obtained has an irregular structure. Such structure irregularities alter the performances of the final component.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel method for manufacturing single-pole components of vertical type having a determined breakdown voltage and having a reduced on-state resistance. The present invention also aims at the obtained components.
To achieve these objects, the present invention provides a single-pole component of vertical type, including regions of a first conductivity type buried in a thick layer of a second conductivity type, said regions being distributed over at least one same horizontal level and being independent from one another, and the independent regions of which underlie an insulating material.
According to an embodiment of the present invention, the component includes at least two levels, the independent regions of successive levels being substantially vertically aligned.
According to an embodiment of the present invention, the independent regions are rings.
According to an embodiment of the present invention, the deepest level includes non ring-shaped regions.
The present invention also provides a method for manufacturing a single-pole component of vertical type in a silicon substrate of a given conductivity type, including the steps of:
a) forming openings in a thick silicon layer covering the substrate, doped of the same conductivity type as said substrate, but more lightly;
b) coating the walls and bottoms of the openings with a silicon oxide layer;
c) forming, by implantation/diffusion through the opening bottoms, regions of the conductivity type opposite to that of the substrate; and
d) filling the openings with an insulating material.
According to an embodiment of the present invention, before step d) of filling the openings, steps a) to c) are repeated at least once, the initial openings being continued into the thick silicon layer.
According to an embodiment of the present invention, the silicon layer of the same given type of conductivity as the substrate is intended for forming the cathode of a Schottky diode.
According to an embodiment of the present invention, the silicon layer of same conductivity type as the substrate is intended for forming the drain of a MOS transistor.
The foregoing and other objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, in which:



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates, in a partial simplified cross-section view, a conventional Schottky diode structure;
FIG. 2 illustrates the variation of the electric field across the thickness of the structure of FIG. 1;
FIG. 3 illustrates, in a partial simplified cross-section view, the structure of a Schottky diode having a determined breakdown voltage and a reduced on-state resistance;
FIG. 4 illustrates the variation of the electric field across the thickness of the structure of FIG. 3; and
FIGS. 5A to 5D are partial simplified cross-section views of a Schottky diode at different steps of a manufacturing process according to the present invention.
For clarity, the same elements have been designated with the same references in the different drawings. Further, as usual in the representation of integrated circuits, the drawings are not to scale.
FIGS. 5A to 5D illustrate steps of a manufacturing method of a vertical monolithic Schottky diode according to the present invention.



DETAILED DESCRIPTION
As illustrated in FIG. 5A, a substrate 61 is initially covered with a single-crystal silicon layer 62, of same doping type, for example N, as substrate 61. Layer 62, intended for forming the cathode of the Schottky diode, is more lightly doped than substrate 61. Layer 62 is etched, by means of a mask 65, to form openings 66. Substrate 61 and layer 62 are obtained by any appropriate method. For example, layer 62 may result from an epitaxial growth on substrate 61, or substrate 61 and layer 62 may initially be a same semiconductor region, the doping differences then resulting from implantation-diffusion operations.
At the next steps, illustrated in FIG. 5B, an insulating layer 67, for example a silicon oxide layer (SiO2), is formed on the walls and at the bottom of openings 66. Then, a P-type dopant that penetrates into the silicon at the bottom of openings 66 is implanted, after which a heating is performed to form heavily-doped P-type regions 641.
At the next steps, illustrated in FIG. 5C, layer 67, regions 641, and layer 62 are anisotropically etched, to form openings 68 that continue openings 66. The upper portion of each of openings 68 is thus surrounded with a diffused ring 641. Then, the walls and bottoms of openings 68 are covered with a thin insulating layer 69, for example silicon oxide.
The implantation operations previously described in relation with FIG. 5B are then repeated to form heavily-doped P-type regions 642.
At the next steps, illustrated in FIG. 5D, openings 66–68 are filled with an insulating material 70. Then, mask 65 is removed and the structure thus obtained is planarized. Finally, a metal layer 63 adapted to ensuring a Schottky contact with layer 62 is deposited over the entire structure.
Before ending, in accordance with the steps described in relation with FIG. 5D, the structure formation by removing mask 65, filling openings 66–68 with material 70, and depositing a metal layer 63, the steps described in relation with FIG. 5C could be repeated several times, to form several horizontal levels of heavily-doped P-type rings similar to rings 641.
It should be noted that the intermediary rings and the underlying regions form islands according to the preceding definition. They thus provide the corresponding advantages, previously discussed in relation with FIGS. 3 and 4.
An advantage of the method according to the present invention and of the resulting structure, previously described in relation with FIG. 5D, is the forming of a homogeneous cathode region 62.
Those skilled in the art will know how to adapt the number, the dimensions, the positions, and the doping of the different rings 641, 642 to the desired performances. As an example, according to prior art, to obtain a breakdown voltage of approximately 600 volts, a cathode layer (2, FIG. 1) of a thickness of approximately 40 μm and of a doping level on the order of 2.2·1014 atoms/cm3 may be used, which results in an on-state resistance of approximately 6.7 Ω·mm2. According to the present invention, by using groups of three P-type rings doped at approximately 3.5·1017 atoms/cm3, vertically spaced apart by 10 μm around silicon oxide columns of a 1-μm width, for a same breakdown voltage of 600 V with an epitaxied layer (62, FIG. 5D) of a same thickness on the order of 40 μm, the cathode doping could be increased to a value on the order of some 1015 atoms/cm3, which results in an on-state resistance of approximately 3 Ω·mm2.
It should be noted that it has been chosen to describe as a non-limiting example the present invention in relation with FIG. 6 applied to the forming of silicon islands in the cathode of a Schottky diode. It would however be possible to implement a method aiming at forming in the drain of a MOS transistor, around vertical columns of an insulating material, very heavily-doped P-type silicon rings, similarly to the method previously described in relation with FIGS. 5A–D.
Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the operations described in relation with FIG. 5D can be carried out according to any appropriate sequence. Thus, after filling openings 66–68, layer 65 may be removed and the structure may be planarized in a single step by means of a chem-mech polishing (CMP) method.
Further, the present invention applies to the forming in vertical form of any type of single-pole component, be it to reduce its on-state resistance for a given breakdown voltage, or to improve its breakdown voltage without increasing its on-state resistance.

## Claims

1. A method of manufacturing a single-pole component of vertical type in a silicon substrate of a first conductivity type, comprising the steps of:
a) forming openings in a thick silicon layer of the first conductivity type covering the substrate, the thick silicon layer being more lightly doped than the substrate;
b) coating walls and bottoms of the openings with a silicon oxide layer;
c) forming, by implantation/diffusion through the bottoms of the openings, regions of a second conductivity type opposite to that of the substrate; and
d) filling the openings with an insulating material.

2. The method of claim 1, wherein, before step d), steps a), b) and c) are repeated at least once, with the openings being continued into the thick silicon layer.

3. The method of claim 2, wherein the thick silicon layer forms a cathode of a Schottky diode.

4. The method of claim 2, wherein the thick silicon layer forms a drain of a MOS transistor.

5. The method of claim 1, wherein the thick silicon layer forms a cathode of a Schottky diode.

6. The method of claim 1, wherein the thick silicon layer forms a drain of a MOS transistor.

7. The method of claim 1, wherein at least one of the openings extends into the thick silicon layer from an upper surface thereof.

8. A method of making a single pole component, comprising:
providing a substrate of a first conductivity type;
providing a layer of the first conductivity type on the substrate, the layer being more lightly doped than the substrate;
forming first openings that extend into the layer from an upper surface thereof;
coating the first openings with an insulating layer;
penetrating the layer at bottom surfaces of the first openings to form first buried regions of a second conductivity different than the first conductivity; and
filling the first openings with an insulating material to form columns of insulating material.

9. The method of claim 8, further comprising:
forming second openings that extend into the layer from bottom surfaces of the first openings;
coating the second openings with an insulating layer;
penetrating the layer at bottom surfaces of the second openings to form second buried regions of a conductivity different than the first conductivity; and
filling the second openings with an insulating material to form columns of insulating material.

10. The method of claim 9, wherein the first buried regions comprise rings positioned around the columns of insulating material and the second buried regions are adjacent to the bottom surfaces of the second openings.

11. The method of claim 9, wherein the first and second buried regions are distributed over first and second horizontal levels, respectively, of the layer.

12. The method of claim 8, wherein providing the substrate and providing the layer comprise providing a silicon substrate and a silicon layer.

13. The method of claim 12, wherein the substrate and the layer are N type and wherein the first buried regions are P type.

14. The method of claim 8, wherein providing the layer comprise providing a cathode of a Schottky diode.

15. The method of claim 8, wherein providing the layer comprises providing a drain of an MOS transistor.