# Patent

## Title
Pulse width-modulated driving method for an electric motor with zero-crossing compensation

## Abstract

A pulse width-modulated (PWM) driving method is provided for a PWM motor control system with zero-crossing compensation. The PWM driving method includes controlling each carrier generator of first, second and third PWM generators to generate a carrier offset between each of first, second and third carrier signals, at least when a current flowing in a respective phase of an alternating current (AC) motor of the PWM motor control system is between +/−10 mA, such that a voltage between respective nodes and a reference point of respective half-bridges of the PWM motor control system are offset to obtain a variable common mode voltage each time respective PWM signals are in an off-state, at least when the respective current is crossing zero.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit to European Patent Application No. EP 21185490.6, filed on Jul. 14, 2021, which is hereby incorporated by reference herein.
FIELD
The present invention relates a pulse width-modulated (PWM) driving method for driving an electric motor with zero-crossing compensation to reduce the unwanted current-wave distortion of the driving current of the motor. The disclosed method may further comprise deadtime compensation to further reduce the current-wave distortion.
BACKGROUND
In PWM-inverter-controlled AC motor drives, deadtime or time delay must be inserted in switching signals to prevent a short circuit in each of the inverter half-bridges. Although this time delay guarantees safe operation of the inverter, it causes substantial distortion in the output voltages. It results in a momentary loss of control, and the output voltage deviates from the reference voltage. Since this is repeated for every switching operation, its effect may become significant. This effect is still apparent even with the fast-switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and others. There is therefore a need for efficient deadtime compensation for the improvement of the performance of PWM inverters in order to avoid or at least reduce the undesirable speed ripple and limit cycle oscillations around a desired position of the motor. Several approaches have been developed for deadtime compensation in order to reduce the unwanted current-wave distortion of the driving current of the motor.
As an example, US 2004/0037097 discloses a method for compensating deadtime non-linearity in a solid switch device comprising the following steps: receiving a PWM signal at a first time point; receiving a current feedback from an output of the solid switch device, wherein the solid switch device comprises a plurality of switch components; detecting a polarity change in the feedback current at a second time point; detecting a rising edge of the PWM signal at a third time point; determining whether the feedback current has a positive or a negative polarity subsequent to the detected polarity change; and if the feedback current has a positive polarity subsequent to the detected polarity change, outputting a first control signal to activate a first switch component of the solid switch device at a predetermined delay after the third time point.
Although US 2004/0037097 acknowledges that due to the deadtime effect, the voltage distortion becomes more severe at the point of current polarity change, more commonly known as “zero crossing”, the negative effect of zero crossing is not addressed albeit it contributes, as the deadtime effect, to the current-wave distortion.
L. Ben-Brahim, “On the Compensation of Dead Time and Zero-Current Crossing for a PWM-Inverter-Controlled AC Servo Drive,” IEEE Transaction on industrial electronics Vol. 51, No. 5 (October 2004) proposed a method of zero-crossing and dead-time compensation based on angle domain repetitive control.
SUMMARY
In an embodiment, the present invention provides a pulse width-modulated (PWM) driving method for a PWM motor control system with zero-crossing compensation. The PWM motor control system comprises a three-phase alternating current (AC) motor, a power inverter comprising a first, a second and a third half-bridge, each half-bridge comprising a first transistor connected to a common given voltage and a second transistor connected to a reference point, each phase of the AC motor being connected to respective nodes of a corresponding half-bridge, and a controller comprising a first, a second and a third PWM generator comprising a first, a second and a third carrier generator respectively configured to generate a first, a second and a third carrier signal respectively for generating a first, a second and a third PWM signal, each PWM generator further comprising a deadtime generator configured to transform the respective PWM signal into a first and a second inverted square wave signal with deadtimes to control respectively the first and second transistors of the respective half-bridges. The method comprising controlling each carrier generator of the respective first, second and third PWM generators to generate a carrier offset between each of the first, second and third carrier signals, at least when a current flowing in the respective phase of the AC motor is between +/−10 mA, such that a voltage between the respective nodes and the reference point of the respective half-bridges are offset to obtain a variable common mode voltage each time the respective PWM signals are in an off-state, at least when the respective current is crossing zero.



BRIEF DESCRIPTION OF THE DRAWINGS
Subject matter of the present disclosure will be described in even greater detail below based on the exemplary figures. All features described and/or illustrated herein can be used alone or combined in different combinations. The features and advantages of various embodiments will become apparent by reading the following detailed description with reference to the attached drawings, which illustrate the following:
FIG. 1 shows a partial schematic view of a PWM motor control system of an exemplary embodiment of the invention;
FIG. 2 shows a PWM signal with the insertion of deadtimes in the PWM signal to prevent a short circuit in one-phase leg of a PWM inverter according to the prior art;
FIG. 3a shows a PWM signal with deadtimes according to the prior art versus a modified PWM signal with deadtime compensation according to an exemplary embodiment of the invention when the polarity of the current in one phase load of the motor is positive;
FIG. 3b shows a PWM signal with deadtimes according to the prior art versus a modified PWM signal with deadtime compensation according to an exemplary embodiment of the invention when the polarity of the current in one phase load of the motor is negative;
FIG. 4a shows a period of the PWM signal, and the corresponding common mode voltage, the node voltage of one half-bridge of the power inverter, the voltage across one phase load and the resulting current in that phase for a scenario in which the conventional PWM scheme of FIG. 2;
FIG. 4b shows a similar view of FIG. 4a for a scenario in which a zero-crossing compensation algorithm is used according to an exemplary embodiment of the invention;
FIG. 4c shows a similar view of FIG. 4b for a scenario in which a zero-crossing compensation algorithm is used together with a deadtime compensation algorithm based on FIGS. 3a and 3b according to an exemplary embodiment of the invention;
FIG. 5a shows three carrier signals of respective PWM generators offset from each other by a constant offset according to an embodiment of the invention;
FIG. 5b shows the node voltage of respective half-bridge when offsetting the three carrier signals as shown in FIG. 5a; 
FIG. 5c shows the resulting common mode voltage of the AC motor;
FIG. 6a shows a graph of the current curves measured on each inductive load of a three-phase electric motor with no deadtime and zero-crossing algorithm compensation;
FIG. 6b shows a similar graph of FIG. 6a when a deadtime compensation algorithm is used according to the exemplary embodiment shown in FIG. 4b, and
FIG. 6c shows a similar graph of FIG. 6b when a deadtime compensation algorithm is used together with the zero-crossing compensation algorithm according to an exemplary embodiment shown in FIG. 4c. 



DETAILED DESCRIPTION
In an embodiment, the present invention provides an alternative PWM driving method for driving an electric motor with zero-crossing time compensation. In the same or another embodiment, the present invention provides a PWM driving method which further compensate the deadtime negative effect.
These improvements are achieved according to an embodiment of the present invention by means of a PWM driving method for a PWM motor control system with zero-crossing compensation. The PWM motor control system comprises: a three-phase AC motor, a power inverter comprising three half-bridges, wherein each half-bridge comprises a first transistor connected to a common given voltage a second transistor connected to a reference point, each phase load of the AC motor being connected to respective node of the corresponding half-bridge, and a controller. The controller comprises three PWM generators having respectively a first, a second and a third carrier generator configured to generate a first, a second and a third carrier signal respectively for generating a first, a second and a third PWM signal. Each PWM generator further comprises a deadtime generator configured to transform each PWM signal into a first and a second inverted square wave control signal with deadtimes to control respectively said first and second transistors of respective half-bridges.
The method according to an embodiment comprises controlling each carrier generator of respective first, second and third PWM generators to generate a carrier offset between each of said first, second and third carrier signals, at least when the current flowing in respective phase of the AC motor is between −10 mA and +10 mA, such that the voltage between the node and the reference point of the respective half-bridges are offset to obtain a variable common mode voltage each time the respective PWM signals are in an off-state, at least when said current is crossing zero.
The term “offset” within the context of the present disclosure should be understood as a delay in time. The term “when the current is crossing zero” within the context of the present disclosure should be understood as when the current is between +/−10 mA.
In an embodiment, the carrier offset is generated at all times when the motor is operating.
In an embodiment, the carrier offset is constant between each of the three carrier signals.
In an embodiment, the carrier offset is between 0.4 and 8 μs, preferably around 2 μs.
In an embodiment, the frequency of each carrier signal is between 5 kHz and 200 kHz, preferably around 20 kHz.
In an embodiment, the variable common mode voltage is a staircase-shaped ramp voltage.
In an embodiment, the staircase-shaped ramp voltage comprises a negative ramp slope and a positive ramp slope.
In an embodiment, the PWM driving method further comprises the step of determining the current sign of the current for each phase load of the three-phase AC motor. A first and a second square wave control signals to control respectively the first and second transistors of respective first, second and third half-bridges are computed as follows:

    
    
        When the current sign of the current in respective phase load of the three-phase AC motor is positive, the falling and rising edges of the first control signal are each offset by a first deadtime with respect to the corresponding falling and rising edges of the corresponding PWM signal to control the first transistor of respective first, second and third half-bridges. The rising edges of the second control signal are offset by a second deadtime, with respect to corresponding falling edges of the corresponding PWM signal. The second deadtime is longer than the first deadtime, preferably two times longer. The falling edges of the second control signal are not offset, with respect to the corresponding rising edges of the corresponding PWM signal, in order to control the second transistor of respective first, second and third half-bridges.
        When the current sign of the current in respective phase load of the three-phase AC motor is negative, the falling edges of the first control signal is not offset with respect to the corresponding falling edges of the corresponding PWM signal, and the rising edges of the first control signal are offset, with respect to the corresponding rising edges of the corresponding PWM signal, by the second deadtime. The rising and falling edges of the second control signal are each offset, with respect to the corresponding falling edges and rising edges of the corresponding PWM signal, by the first deadtime which shorter than the second deadtime, preferably two times shorter.
    
    


In an embodiment, when the current sign of the current in respective phase load of the three-phase AC motor is negative, the second control signal, to control the second transistor of respective half-bridges, is an inverted delayed replica of first, second and third PWM signals respectively. And when the current sign of the current in respective phase load of the three-phase AC motor is positive, the first control signal, to control the first transistor of respective half-bridges, is a delayed replica of first, second and third PWM signals respectively.
In an embodiment, the node voltage of respective half-bridges of the power inverter is a delayed replica of first, second and third PWM signals respectively when the current sign of the current in respective phase load of the three-phase AC motor is positive or negative.
A PWM motor control system 10 is shown in FIG. 1. The PWM motor control system comprises a controller 20 which may be for example a field-programmable gate array (FPGA) controller, a power inverter 30 and a three-phase AC motor 40. The controller 20 comprises a PWM generator and a dead-time generator for driving each phase load of the three-phase AC motor 40. The controller 20 is configured and connected to develop the necessary voltage out of the power inverter 30 such that, when applied to the motor 40, the desired current and torque are generated. Because these voltages are related to the position and speed of the motor, the position and speed of the rotor are determined. A rotor position encoder (not shown) is connected to the motor 40 to detect the position of the rotor. The signal of the position encoder is fed-back to the control to adapt the PWM signal as required.
The power inverter 30 comprises three half-bridges comprising each a first transistor T1; T3; T5 connected to a common given voltage, which may be for example a positive bus voltage, and a second transistor T2, T4, T6 connected to a reference point, which may be the ground. The reference point of each half-bridge may be connected together to a negative bus voltage according to an alternative embodiment. The gates of both the first and second transistors T1, T2; T3, T4; T5, T6 of respective half-bridge of the power inverter 30 are driven by a first, a second and a third gate driver 32a, 32b, 32c of the power inverter 30.
The controller 20 comprises three PWM generators 21a, 21b, 21c and three dead-time generators 22a, 22b, 22c, i.e. one generator and one dead-time generator per phase load. Each PWM generator comprises a carrier generator 24a, 24b, 24c configured to generate a carrier signal PWMcar1, PWMcar2, PWMcar3 which is fed into a comparator together with a reference signal α1, α2, α3 to output from a comparator a PWM signal PWM1, PWM2, PWM3. The reference signals α1, α2, α3 are typically sinusoidal waveforms computed by a processor (not shown) to control the motor speed and torque. The reference signals α1, α2, α3 must be shifted by 120° from each other to control each phase load of the three-phase motor 40 adequately.
The deadtime generators 22a, 22b, 22c are configured to transform the corresponding PWM signal PWM1, PWM2, PWM3 into a first and a second inverted square wave control signal with deadtimes td1, td2 as depicted in FIGS. 3a, 3b. The magnitude of the first and second control signals is increased by respective gate drivers 32a, 32b, 32c of the power inverter 30 in order to control respectively the first and second transistors T1, T2; T3, T4; T5, T6 of each of the three half-bridges.
As previously mentioned, the deadtime generator is essential to ensure a period during a switching transition when both output of the two transistors of each half-bridge are driven into a cut-off mode and both are “off” to avoid any short-circuit through the half-bridges of the inverter. The deadtime may be for example between 100 ns and 2 μs, preferably around 500 ns, and should be determined based on the selected transistor type.
As shown in FIG. 2, during the deadtime td shown in grey of a conventional PWM signals to drive alternatively transistors T1 and T2 of one half-bridge to control one phase load of the motor 40, the node output voltage is determined by the current sign and hence, by the diode that is driven on by the load current.
In order to address the voltage losses and to linearize the signals at the outputs of the power inverter 30, the controller 20 modifies the conventional PWM scheme to compensate the deadtime negative effect as per the following modified PWM scheme. The current sign of the currents I1, I2, I3 flowing in respective load phase is first determined, and the PWM scheme is modified accordingly as shown in FIGS. 3a and 3b according to an embodiment. The currents I1, I2, I3 are typically measured using current sensors inserted between the inverter nodes and the motor phase loads.
Referring to FIG. 3a, when the polarity of the current in the respective load phase is positive, the on-time of the first transistor T1; T3; T5 of each half-bridge controlling the corresponding phase of the three-phase AC motor 40 is increased. This is achieved by delaying the falling and rising edges of respective PWM1, PWM2, PWM3 signals (FIG. 1) by a first deadtime td1 such that the first control signal VgT1 applied to the gate of the first transistor T1 is a replica of the PWM1 signal with rising edges and falling edges delayed with respect to corresponding rising edges and falling edges of the PWM1 signal by the first deadtime td1, which may last for example 500 ns. The rising edges of the second control signal VgT2 is delayed with respect to the corresponding rising edges of the PWM1 signal by a second deadtime td2 whose length may be for example twice the length of the first deadtime td1, which may last for example 1 μs, while the falling edges of the second control signal are not offset with respect to the corresponding rising edges of the PWM1 signal.
Referring to FIG. 3a, when the polarity of the current I1, I2, I3 in the respective load phase is negative, the falling edges of the first control signal VgT1 is not offset with respect to the corresponding falling edges of the PWM1 signal and the rising edges of said first control signal are offset by the second deadtime td2 with respect to the corresponding rising edges of the PWM1 signal. The rising and falling edges of the second control signal VgT2 are each offset with respect to the corresponding falling and rising edges of the PWM1 signal by the first dead-time td1, which is shorter than said second deadtime td2, preferably two times shorter.
Controlling the gate of each transistor as described above ensures that the node voltage Vol as shown in FIGS. 3a and 3b is always a delayed replica of the PWM1 signal. Signals PWM2 and PWM3 are controlled individually, but the voltage waveforms applied to the gate of transistors T3 and T4 of the second half-bridge and to the gate of transistors T5 and T6 of the third half-bridge are similar to the voltage waveforms VgT1 and VgT2 applied to the first and second transistors T1, T2 of the first half-bridge for positive and negative currents as depicted in FIGS. 3a and 3b. These driving waveforms significantly reduce non-linearity between the PWM duty-cycle input and the obtained voltage output.
As already mentioned, voltage distortion also occurs at the point of polarity change, more commonly referred to as zero crossing. When the current is crossing zero, during dead-time td, the freewheeling diodes D1-D6 cannot turn on. In this situation, the output node of the half-bridge is floating and its voltage is determined by design parasitic. It becomes problematic when the motor is at standstill and all the phases are pulsing following the PWM with 50% duty cycle. Since the PWM motor system 10 is balanced, the common mode voltage Vcm will always have the same waveform as the load phase voltages Vph1, Vph2, Vph3.
In this situation, no voltage can be applied as shown in FIG. 4a. The current I1 being zero, the output node is floating during the deadtime td which causes the output current I1 to remain at zero current until the second pulse is generated. However, since the second pulse is still small in time, the magnitude of the current generated during the second pulse is not sufficient to bring the current at the next transition and the problem repeats again.
In order to overcome this problem, each carrier generator 24a, 24b, 24c of respective first, second and third PWM generators 21a, 21b, 21c are controlled to generate a carrier offset between each of the first, second and third carrier signals PWMcar1, PWMcar2, PWMcar3, as shown in FIG. 5a, such that the voltage Vph1, Vph2, Vph3 between the node n1, n2, n3 and the ground GNDPWR of the respective half-bridges are offset (FIG. 5b) to obtain a variable common mode voltage VCM each time the respective PWM signals PWM1, PWM2, PWM3 are in an off-state.
The carrier offset is preferably generated at all times when the motor is operating although it can be generated, according to an embodiment, only when the current I1, I2, I3 in respective load phase is crossing zero, i.e. when the current is for example between +/−10 mA.
The carrier offset may be for example between 0.4 and 8 μs, preferably around 2 μs in order to obtain the shifted square waves voltages Vph1, Vph2, Vph3. The carrier offset is typically determined according to the selected deadtime, for example between 2 and 6 times the deadtime, preferably around 4 times the deadtime. The resulting common voltage VCM resembles a staircase-shaped ramp voltage as shown in FIG. 5c. 
Referring now to FIG. 4b, at the falling edge of the phase voltage Vol, the current I1 is still zero. However, as the common mode voltage Vcm is no longer the same as the phase voltage Vph1, a current pulse is generated on the motor load, reducing the error.
In a preferred embodiment, both the deadtime compensation PWM scheme as previously described, and the zero-crossing compensation are applied to further reduce the error when the current is crossing zero as shown in FIG. 4c. In FIGS. 4a to 4c, the theoretical load voltage, which would be obtained without the deadtime negative effect, is shown versus the real load voltage obtained due to the floating node induced by the deadtimes.
The deadtime and the zero-crossing compensations significantly reduce the unwanted current-wave distortions of the driving current of the motor as shown in FIGS. 6a to 6c. FIG. 6b shows that the current curves measured on each inductive load of the AC motor when using the deadtime compensation algorithm alone have significant less current-wave distortions when compared to corresponding current curves when no deadtime compensation is performed. FIG. 6c shows that the current curves measured on each inductive load of the AC motor when using the deadtime compensation algorithm together with the zero-crossing compensation algorithm have even less current-wave distortions when compared to the corresponding curves of FIG. 6b where only the deadtime compensation algorithm is used.
While subject matter of the present disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. Any statement made herein characterizing the invention is also to be considered illustrative or exemplary and not restrictive as the invention is defined by the claims. It will be understood that changes and modifications may be made, by those of ordinary skill in the art, within the scope of the following claims, which may include any combination of features from different embodiments described above.
The terms used in the claims should be construed to have the broadest reasonable interpretation consistent with the foregoing description. For example, the use of the article “a” or “the” in introducing an element should not be interpreted as being exclusive of a plurality of elements. Likewise, the recitation of “or” should be interpreted as being inclusive, such that the recitation of “A or B” is not exclusive of “A and B,” unless it is clear from the context or the foregoing description that only one of A and B is intended. Further, the recitation of “at least one of A, B and C” should be interpreted as one or more of a group of elements consisting of A, B and C, and should not be interpreted as requiring at least one of each of the listed elements A, B and C, regardless of whether A, B and C are related as categories or otherwise. Moreover, the recitation of “A, B and/or C” or “at least one of A, B or C” should be interpreted as including any singular entity from the listed elements, e.g., A, any subset from the listed elements, e.g., A and B, or the entire list of elements A, B and C.

## Claims

1. A pulse width-modulated (PWM) driving method for a PWM motor control system with zero-crossing compensation, wherein the PWM motor control system comprises a three-phase alternating current (AC) motor, a power inverter comprising a first, a second and a third half-bridge, each half-bridge comprising a first transistor connected to a common given voltage and a second transistor connected to a reference point, each phase of the AC motor being connected to respective nodes of a corresponding half-bridge, and a controller comprising a first, a second and a third PWM generator respectively comprising a first, a second and a third carrier generator respectively configured to generate a first, a second and a third carrier signal respectively for generating a first, a second and a third PWM signal, each PWM generator further comprising a deadtime generator configured to transform the respective PWM signal into a first and a second inverted square wave signal with deadtimes to control respectively the first and second transistors of the respective half-bridges, the method comprising:
controlling each carrier generator of the respective first, second and third PWM generators to generate a carrier offset between each of the first, second and third carrier signals, at least when a current flowing in the respective phase of the AC motor is between +/−10 mA, such that a voltage between the respective nodes and the reference point of the respective half-bridges are offset to obtain a variable common mode voltage each time the respective PWM signals are in an off-state, at least when the respective current is crossing zero.

2. The PWM driving method according to claim 1, wherein the carrier offset is generated at all times.

3. The PWM driving method according to claim 1, wherein the carrier offset is constant between each of the carrier signals.

4. The PWM driving method according to claim 3, wherein the carrier offset is between 0.4 and 8 μs.

5. The PWM driving method according to claim 3, wherein the carrier offset is around 2 μs.

6. The PWM driving method according to claim 1, wherein the frequency of each carrier signal is between 5 kHz and 200 kHz.

7. The PWM driving method according to claim 6, wherein the frequency of each carrier signal is around 20 kHz.

8. The PWM driving method according to claim 1, wherein the variable common mode voltage is a staircase-shaped ramp voltage.

9. The PWM driving method according to claim 8, wherein the staircase-shaped ramp voltage comprises a negative ramp slope and a positive ramp slope.

10. The PWM driving method according to claim 1, further comprising:
determining a current sign of the respective current for each phase load of the three-phase AC motor, and
wherein a first and a second square wave control signal to control respectively the first and second transistors of the respective half-bridges are computed as follows:
when the current sign of the respective current in the respective load phase of the three-phase AC motor is positive, falling and rising edges of the first control signal are each offset by a first deadtime with respect to corresponding falling and rising edges of the corresponding PWM signal to control the first transistor of the respective half-bridges, while rising edges of the second control signal are offset by a second dead-time with respect to corresponding falling edges of the corresponding PWM signal, the second deadtime being longer than the first dead-time, and falling edges of the second control signal being not offset with respect to corresponding rising edges of the corresponding PWM signal in order to control the second transistor of the respective half-bridges, and
when the current sign of the respective current in the respective load phase of the three-phase AC motor is negative, the falling edges of the first control signal are not offset with respect to the corresponding falling edges of the corresponding PWM signal, and the rising edges of the first control signal are offset, with respect to the corresponding rising edges of the corresponding PWM signal, by the second deadtime, while the rising and falling edges of the second control signal are each offset, with respect to the corresponding falling edges and rising edges of the corresponding PWM signal, by the first deadtime which is shorter than the second deadtime.

11. The PWM driving method according to claim 10, wherein the second deadtime is two times longer than the first deadtime.

12. The PWM driving method according to claim 10, wherein the second control signal, to control the second transistor of respective half-bridges, is an inverted delayed replica of the first, second and third PWM signals respectively when the current sign of the current in the respective load phase of the three-phase AC motor is negative, and wherein the first control signal, to control the first transistor of respective half-bridges, is a delayed replica of first, second and third PWM signals respectively when the current sign of the current in the respective load phase of the three-phase AC motor is positive.

13. The PWM driving method according to claim 10, wherein a node voltage of the respective half-bridges of the power inverter is a delayed replica of the first, second and third PWM signals respectively when the current sign of the current in the respective phase load of the three-phase AC motor is positive or negative.