# Patent

## Title
Voltage-controlled gain-cell magnetic memory

## Abstract

The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

## Background
GOVERNMENT SUPPORT
This invention was made with government funds under Agreement No. HR0011-18-3-0004 awarded by The Defense Advanced Research Projects Agency (DARPA). The U.S. Government has certain rights in this invention.


FIELD OF THE DISCLOSURE
The technology of the disclosure relates generally to electronic data storage and, more particularly, to a magnetic memory structure with a voltage-controlled gain-cell configuration.
BACKGROUND
Many different technologies are used to create electronic data storage (“memory”) elements for storing programs and data in binary form in electronic devices. Memory element technologies are characterized by their access times (i.e., read and write delay), density, power utilization, and volatility in the absence of power. Technologies that excel in one or more of these characteristics are typically inferior in other respects. As a result, different memory element technologies are used for different purposes, according to their particular characteristics. FIG. 1 illustrates comparisons of read/write speed and density of various electronic data storage technologies. As shown in FIG. 1, static random access memory (RAM) (SRAM) technology can have a fast read/write speed, which is beneficial for use with a high-speed processor, but the high speed is obtained at the expense of a large area needed for the multiple transistors of which each SRAM cell is comprised, as well as the other components of an SRAM array. Dynamic RAM (DRAM) is more dense, but not as fast as high-speed SRAM. Unfortunately, both SRAM and DRAM elements are volatile, meaning that the data stored therein is lost when power is removed. In contrast, a high-density non-volatile memory (NVM) such as NAND has been developed for long-term storage, but the long access time of NVM storage is too slow for use in high-speed processor applications. Spin-Transfer Torque (STT) magnetic RAM (MRAM) is an example of memory that can have a much faster read/write speed (i.e., short access latency) than NAND, and is non-volatile, so no power is required to preserve the data stored therein. However, the STT-MRAM has a low density, which requires a large area for implementation.
FIG. 2 illustrates comparisons of write energy consumption and write latency of existing MRAM technologies. As shown in FIG. 2, embedded SRAM (eSRAM) can have a fast write speed with a small amount of energy consumption. However, eSRAM elements are volatile and will lose data stored therein when power is removed. In addition, although the STT-MRAM can achieve a relatively fast write speed and is non-volatile, the STT-MRAM requires high current density for switching a magnetization direction of the free magnetic layer, causing high power consumption and less bit density than is preferred for mobile devices.
Accordingly, there is an object of the present disclosure to provide an improved non-volatile memory structure, which can achieve high speed read/write speed with high-density, without sacrificing power consumption. In addition, there is also a need to implement the non-volatile memory structure in a cost effective and controllable manner.
SUMMARY
The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration. The disclosed magnetic memory structure includes a two-terminal memory resistive device with a first terminal connected to a bit line (BL), a first transistor connected in series between a second terminal of the memory resistive device and a first source line (SL), and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device, a drain connected to a bias voltage power, and a source connected to a second SL. Herein, when the memory resistive device exhibits the ‘1’ state, a gate voltage at the gate of the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage at the gate of the second transistor is larger than the threshold voltage of the second transistor.
In one embodiment of the magnetic memory structure, the memory resistive device is configured to switch between the ‘1’ state and a ‘0’ state by applying voltage pulses, which have different amplitudes with a same polarity.
In one embodiment of the magnetic memory structure, corresponding to the ‘0’ state and the ‘1’ state, a current flowing through the second transistor changes between 103 times and 109 times in amplitude.
In one embodiment of the magnetic memory structure, the first SL and the second SL are connected to ground.
According to one embodiment, the magnetic memory structure further includes a resistor, which is connected in series between the drain of the second transistor and the bias voltage power.
In one embodiment of the magnetic memory structure, each of the first transistor and the second transistor is implemented with one of bulk complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI) technologies, Fin field-effect transistors (FETs), and negative-capacitance (NC) FETs.
In one embodiment of the magnetic memory structure, a magnetoresistance (MR) change of the memory resistive device is between 20%-40% between the ‘0’ state and the ‘1’ state.
In one embodiment of the magnetic memory structure, the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ). The memory resistive device includes a fixed magnetic layer, a free magnetic layer, and a resonant tunnel barrier disposed between the fixed magnetic layer and the free magnetic layer. Herein, when the memory resistive device exhibits the ‘1’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is parallel, and when the memory resistive device exhibits the ‘0’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel.
In one embodiment of the magnetic memory structure, the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer is parallel in response to a first BL voltage applied to the BL. The magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel in response to a second BL voltage applied to the BL. The first BL voltage and the second BL voltage have different amplitudes and a same polarity.
In one embodiment of the magnetic memory structure, the first BL voltage and the second BL voltage change interlayer exchange coupling (IEC) between the fixed magnetic layer and the free magnetic layer of the REC MTJ above a threshold, at which the magnetization direction of the free magnetic layer is determined by the magnetization direction of the fixed magnetic layer.
In one embodiment of the magnetic memory structure, the fixed magnetic layer and the free magnetic layer each comprises one of iron (Fe), cobalt (Co), nickel (Ni), lanthanum strontium manganite (LSMO), cobalt iron boron (CoFeB), and cobalt iron (CoFe).
In one embodiment of the magnetic memory structure, the fixed magnetic layer has a thickness in a range of 5 nm to 100 nm, and the free magnetic layer has a thickness in a range of 1 nm to 3 nm.
In one embodiment of the magnetic memory structure, the resonant tunnel barrier includes a spacer layer disposed between the fixed magnetic layer and the free magnetic layer, a first oxide layer disposed between the fixed magnetic layer and the spacer layer, and a second oxide layer disposed between the spacer layer and the free magnetic layer.
In one embodiment of the magnetic memory structure, the spacer layer comprises one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi). The first oxide layer and the second oxide layer each comprise one of magnesium oxide (MgO), magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx), iron oxide (Fe2O3), titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), rhodium oxide (Rh2O3), tantalum oxide (Ta2O3), vanadium oxide (V2O5), aluminum oxide (Al2O3), and hafnium oxide (HfO2).
In one embodiment of the magnetic memory structure, the first oxide layer and the second oxide layer each has a thickness in a range of 0.5 nm to 3 nm, and the spacer layer has a thickness in a range of 0.1 nm to 4 nm.
In one embodiment of the magnetic memory structure, the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ). The memory resistive device includes a fixed magnetic layer, a free magnetic layer, and a resonant tunnel barrier providing a quantum well between the fixed magnetic layer and the free magnetic layer. Herein, when the memory resistive device exhibits the ‘1’ state, an interlayer exchange coupling (IEC) in the resonant tunnel barrier achieves a first IEC peak. When the memory resistive device exhibits the ‘0’ state, the IEC in the resonant tunnel barrier achieves a second IEC peak. The first IEC peak and the second IEC peak have different polarities.
In one embodiment of the magnetic memory structure, the first IEC peak is achieved in response to a first BL voltage applied to the BL, the second IEC peak is achieved in response to a second BL voltage applied to the BL, and the first BL voltage and the second BL voltage have different magnitudes and a same polarity.
In another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.



BRIEF DESCRIPTION OF THE DRAWING FIGURES
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
FIG. 1 provides a graph comparing read/write speed and density of various electronic data storage technologies.
FIG. 2 provides a graph comparing energy consumption and write latency of existing magnetic random access memory (MRAM) technologies.
FIG. 3 provides a schematic diagram of a magnetic memory structure that employs current induced spin-transfer torque (STT).
FIG. 4 provides a schematic diagram of a magnetic memory structure including a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ).
FIGS. 5A-5D provide characteristics of the REC-MTJ illustrated in FIG. 4.
FIG. 6 provides a schematic diagram of an exemplary magnetic memory structure with a voltage-controlled gain-cell configuration according to one embodiment of the present disclosure.
FIGS. 7A-7F provide operation simulations of the exemplary magnetic memory structure illustrated in FIG. 6.
FIGS. 8A and 8B illustrate comparisons of energy consumption and latency of the exemplary magnetic memory structure illustrated in FIG. 6 with existing MRAM technologies.



It will be understood that for clear illustrations, FIGS. 1-8B may not be drawn to scale.
DETAILED DESCRIPTION
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.
Electronic data stored in a magnetic memory structure can remain stable for a long period of time in the absence of a power source, unlike static random access memory (RAM) (SRAM) and dynamic RAM (DRAM) which lose data when power is removed. Existing magnetic RAM (MRAM) technologies employing current-induced spin-transfer torque (STT) or spin-orbit toque (SOT), however, require a large current density for switching a magnetization direction, which limits advancements in energy efficiency and bit density.
FIG. 3 provides a schematic diagram of a conventional STT-MRAM 300 that includes a magnetic tunnel junction (MTJ) 302 as a bit storage unit and a controlled transistor 304 to select the bit. The MTJ 302 employs STT to control a magnetization direction of a free magnetic layer 306 relative to a magnetization direction of a fixed magnetic layer 308 that is separated from the free magnetic layer 306 by an oxide layer 310. The magnetization direction of the free magnetic layer 306 can be set parallel to the magnetization direction of the fixed magnetic layer 308 by a current through the oxide layer 310 in a first direction (e.g., from the fixed magnetic layer 308 to the free magnetic layer 306). The magnetization direction of the free magnetic layer 306 can be set antiparallel to a direction of the fixed magnetic layer 308 by reversing the direction of the current (e.g., from the free magnetic layer 306 to the fixed magnetic layer 308).
The MTJ 302 is connected in series with the controlled transistor 304. A gate of the controlled transistor 304 is connected to a word line (WL), an open terminal of the MTJ 302 (i.e., a terminal at the fixed magnetic layer 308) is connected to a bit line (BL), and an open terminal of the controlled transistor 304 (i.e., a terminal at a source of the controlled transistor 304) is connected to a source line (SL). A WL voltage VWL is applied at the WL to turn on the controlled transistor 304 and select the bit, if the WL voltage VWL is larger than a threshold voltage VTH of the controlled transistor 304.
To write information ‘0’ into the MTJ 302, a write voltage is applied at the BL, while the SL is at a relatively lower voltage (e.g., 0V). As such, a write current flows from the MTJ 302 to the controlled transistor 304. Usually, the write voltage is provided such that the controlled transistor 304 is in a saturation region. To write information ‘1’ into the MTJ 302, the write voltage now needs to be applied at the SL, while the BL is now at a lower voltage (e.g., 0V). As such, the write current now flows from the controlled transistor 304 to the MTJ 302. Note that, for the write ‘0’ operation, the MTJ 302 acts like a drain resistance of the controlled transistor 304, while for the write ‘1’ operation, the MTJ 302 acts like a source resistance of the controlled transistor 304. This configuration change creates an asymmetry in the write current due to the source degeneration. For read-out of the MTJ 302, a read voltage, which is smaller than the write voltage, is applied at the BL, while the SL is at lower voltage (e.g., 0 V). As such, a read-out current flows from the MTJ 302 to the controlled transistor 304. The read-out is enabled using a current-sense amplifier (not shown) that senses the current change (e.g., change of the read-out current) in the controlled transistor 304 due to the magnetoresistance (MR) change between ‘0’ and ‘1’ states. Typically, the MTJ 302 has a baseline resistance smaller than 10 kΩ, and exhibits a MR change of 200% between ‘0’ and ‘1’ states (between antiparallel and parallel conditions of the magnetization direction of the free magnetic layer 306 and the magnetization direction of the fixed magnetic layer 308). Herein, the baseline resistance refers to a resistance of the MTJ 302.
Due to the high current density required to change a magnetization direction using STT, a large amount of power will be consumed by the MTJ 302. The large power requirement limits packaging density, and the high current density can cause reliability problems by breaking down the oxide layer 310. A problem with STT MRAM technology is that the write time for switching the magnetization direction is inversely related to the write current required to switch the device. In other words, to decrease the switching time (e.g., reduce write access latency), the write current must be increased. Thus, reducing the large write current (e.g., reducing the write voltage) to save power and/or increase density results in slower write access times.
Furthermore, in order to have a large write current at a reasonable write voltage applied to the MTJ 302, the MTJ 302 needs to have a relatively low baseline resistance (e.g., <10 kΩ). The smaller baseline resistance corresponds to the fact that the oxide layer 310 needs to be relatively thin (e.g. <1 nm). Usage of a thin oxide layer creates reliability issues, involving oxide breakdowns, pinholes, etc. In addition, to accommodate the large write current, the controlled transistor 304 needs to be a large transistor, which significantly limits the density scaling.
FIG. 4 provides a schematic diagram of a magnetic memory structure 400 including a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ) 402 as a bit storage unit and a controlled transistor 404 to select the bit. Unlike the MTJ 302 only having one oxide layer 310 between the free magnetic layer 306 and the fixed magnetic layer 308, the REC-MTJ 402 includes a resonant tunnel barrier 405 between a free magnetic layer 406 and a fixed magnetic layer 408. The resonant tunnel barrier 405 includes two oxide layers 410 and a spacer layer 412. The spacer layer 412 is disposed between the fixed magnetic layer 408 and the free magnetic layer 406. A first oxide layer 410-1 is disposed between the fixed magnetic layer 408 and the spacer layer 412, and a second oxide layer 410-2 is disposed between the spacer layer 412 and the free magnetic layer 406.
The REC-MTJ 402 is able to employ interlayer exchange coupling (IEC) between the free magnetic layer 406 and the fixed magnetic layer 408 to switch a direction of magnetization in the free magnetic layer 406 under the control of an applied electric field with a significantly lower current density than is required in the MTJ 302. The spacer layer 412 exhibits a large IEC while the oxide layers 410 provide tunnel barriers. The resonant tunnel barrier 405 (i.e., a combination of the spacer layer 412 and the oxide layers 410) forms a quantum-well (QW) between the free and fixed magnetic layers 406 and 408 with discrete energy states above the equilibrium Fermi level. When an electric field is applied in a direction across the REC-MTJ 402, the tunnel barriers become transparent to the wave functions of the magnetic layers 406 and 408 at the levels of the discrete energy states via a resonant tunneling phenomenon. This transparency allows the IEC between the fixed magnetic layer 408 and the free magnetic layer 406 to control the magnetization direction of the free magnetic layer 406 to be parallel or antiparallel to the magnetization direction of the fixed magnetic layer 408 depending on the magnitude of the applied electric field in the direction of the electric field. Different magnitudes of the electric field induce different signs (i.e., polarities) of IEC. Herein, a positive sign of IEC refers to a switching that will yield an antiparallel alignment, and a negative sign of IEC refers to a switching that will yield a parallel alignment. The IEC can be measured as an energy density in units of Joules per square meter. A magnitude of the IEC required to achieve magnetization switching is defined by a threshold value. The IEC threshold value is independent of a parameter describing a Gilbert damping and a parameter for indicating magnets having either in-plane or perpendicular anisotropies of the free magnetic layer, unlike existing MRAM technologies. The threshold value can be controlled by selection of materials, cross-sectional area, and thicknesses of the composite layer. However, the switching time of the magnetic memory structure herein can be optimized by the Gilbert damping and magnetic anisotropy.
FIGS. 5A-5D provide detailed characteristics of the REC-MTJ 402 illustrated in FIG. 4. FIG. 5A illustrates barriers 502 created by the oxide layers 410 and discrete energy states 504 that are possible in a QW 506 formed in the resonant tunnel barrier 405 of the REC-MTJ 402. The discrete energy states 504 are above the Fermi level EF. The QW 506 is formed in the resonant tunnel barrier 405 between the free and fixed magnetic layers 406 and 408 of the REC-MTJ 402. Below the equilibrium Fermi level EF, majority/minority spin-dependent QWs with discrete energy levels exist within the spacer layer 412.
The oxide layers 410 create the barriers 502 having a height ΔBC above the Fermi level EF. The barriers 502 impede the flow of electrons across the spacer layer 412, forming the QW 716. However, due to resonant tunneling phenomena, a transmission coefficient across the oxide layers 410 is increased at the discrete energy states 504 to allow a stronger interaction between the wave functions of the free and fixed magnetic layers 406 and 408. A MTJ threshold voltage VTH-MTJ is a voltage required to achieve high transmission across the oxide layers 410 via the discrete energy states 504 within the QW 506, to induce an IEC strength greater than the switching threshold value. A magnitude or strength of the IEC depends on the wave function interaction at all quantum energy states in the QW 506, including those below the Fermi level EF, and those above the Fermi level EF achieved by the application of the electric field based on a voltage VREC-MTJ applied across the REC-MTJ 402. The current density in the REC-MTJ 402 depends only on the quantum energy states in the QW 506, within the separation between two contact Fermi levels. Consequently, the current density flowing in the REC-MTJ 402 is much lower than in the MTJ 302 used in the STT technology, when a voltage or an electric field is applied to achieve an IEC strength greater than the switching threshold.
FIG. 5B illustrates the IEC (having a magnitude JEX) in the resonant tunnel barrier 405 in FIG. 5A oscillating between positive and negative values and shows the IEC peaks increasing in magnitude with an increase in the electric field applied in a direction based on the voltage VREC-MTJ. The IEC increases significantly when the voltage VREC-MTJ causes the electron energy within the QW 506 to achieve one of the energy states 504. The sign of the IEC changes polarity between peaks (i.e., at each energy state 504 reached due to the applied electric field). Therefore, the IEC oscillates between positive and negative values that increase in magnitude with an applied voltage VREC-MTJ.
In the example in FIG. 5B, when the voltage VREC-MTJ is at P0 level (e.g., 0 V), there is negligible transmission of electron wave functions across the oxide layers 410 of the REC-MTJ 402, the IEC is also negligible. When the voltage VREC-MTJ is raised to P1 level (e.g., 1.0 V), a sizable positive IEC is achieved via energy states of the QW 506. With a positive IEC at the voltage level P1, there should be an anti-ferromagnetic coupling between the free magnetic layer 406 and the fixed magnetic layer 408. However, magnetization switching does not occur in the REC-MTJ 402 until the magnitude of the IEC reaches a switching threshold, which is defined by a threshold value of an energy density of IEC. The switching threshold is attained by the voltage VREC-MTJ. In other words, the magnitude of the IEC is below the switching threshold at the voltage of 1.0 volts at voltage level P1, so the IEC is not strong enough to cause the direction of magnetization in the free magnetic layer 406 to be switched by the magnetization of the fixed magnetic layer 408.
As the voltage VREC-MTJ is increased from 1.0 V, the IEC magnitude initially decreases and then becomes an increasing negative value. When the voltage VREC-MTJ reaches 1.3 V at voltage level P2, another IEC peak with negative polarity is achieved via energy states 504 of the QW 506. With a negative IEC, there should be a ferromagnetic coupling between the free magnetic layer 406 and the fixed magnetic layer 408. The magnitude of the IEC is above the switching threshold at voltage level P2, and the IEC has a negative value, so ferromagnetic coupling causes the direction of magnetization of the free magnetic layer 406 to switch to become parallel to the direction of magnetization of the fixed magnetic layer 408, or causes the direction of magnetization of the free magnetic layer 406 to remain parallel to the direction of magnetization of the fixed magnetic layer 408 if already parallel.
When the voltage VREC-MTJ reaches 1.6 V at voltage level P3, another IEC peak with positive polarity is achieved via energy states 504 of the QW 506. With a positive IEC, there should be an anti-ferromagnetic coupling between the free magnetic layer 504 and the fixed magnetic layer 506. At the voltage level P3, with a positive IEC that is above the switching threshold, the direction of magnetization of the free magnetic layer 406 will switch to become antiparallel to the direction of the magnetization of the fixed magnetic layer 408 or the direction of magnetization of the free magnetic layer 406 will remain antiparallel to the direction of magnetization of the fixed magnetic layer 408 if already antiparallel.
Unlike magnetization switching by STT, employing voltage-controlled IEC to switch a magnetization direction of the free magnetic layer 406 in the REC-MTJ 402 does not require a change in the polarity of the applied voltage VREC-MTJ. The switching does not depend on the polarity of the applied voltage VREC-MTJ but depends on the magnitude of the voltage VREC-MTJ. This aspect is shown in the results of a simulation provided in FIG. 5C.
In the example in the simulation provided in FIG. 5C, the fixed magnetic layer 408 is formed of cobalt iron boron (CoFeB) having a thickness of 10 nm. The free magnetic layer 406 is formed of CoFeB having a thickness of 1 nm. The oxide layers 410 are formed of magnesium oxide (MgO) having a thickness of about 1 nm. The spacer layer 412 is formed of ruthenium (Ru) having a thickness of 0.8 nm. However, the REC-MTJ 402 disclosed herein is not limited to the materials and dimensions of the example of FIG. 5C. For example, the fixed magnetic layer 408 and the free magnetic layer 406 may each be formed from any one of iron (Fe), cobalt (Co), nickel (Ni), lanthanum strontium manganite (LSMO), CoFeB, CoFe, and the like. The fixed magnetic layer 408 may have a thickness in the range of 5 to 100 nm, and the free magnetic layer 406 may have a thickness in the range of 1 to 3 nm. The first and second oxide layers 410 may each be formed of any one of MgO, magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx) (thermally grown), iron oxide (Fe2O3), titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), rhodium oxide (Rh2O3), tantalum oxide (Ta2O3), vanadium oxide (V2O5), aluminum oxide (Al2O3), and hafnium oxide (HfO2). The first and second oxide layers 410 may each have a thickness in the range of 0.5 to 3 nm. The spacer layer 412 may be formed of any one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi). The spacer layer 412 may have a thickness in the range of 0.1 to 4 nm.
FIG. 5C illustrates a simulation of pulses of the voltage VREC-MTJ creating an electric field in a direction (e.g., through the resonant tunnel barrier 405) across the REC-MTJ 402. The voltage levels of the pulses in FIG. 5C correspond approximately with the voltage levels P3, P2, and P1 shown in FIG. 5B. FIG. 5C also includes a corresponding graph of the magnetization directions of the free magnetic layer 406 and the fixed magnetic layer 408 over time T.
In the example in FIG. 5C, the simulation starts at time T=0 ns with the voltage VREC-MTJ=0 V, at which there is negligible IEC in the resonant tunnel barrier 405, and an initial condition in which the directions of magnetization of the respective magnetic layers 406 and 408 are parallel to each other (e.g., both at magnetization of 1). The IEC is negligible at time 0 due to the barriers 502 created by the oxide layers 410 in FIG. 4. At the voltage VREC-MTJ of 0 V, the direction of magnetization of the free magnetic layer 406 will remain stable.
At time T=10 ns, the voltage VREC-MTJ is raised to 1.6 V, which corresponds to a positive IEC (anti-ferromagnetic) and the magnitude is above the switching threshold. After a minimum switching time TIEC (not shown), the IEC causes the direction of the magnetization of the free magnetic layer 406 to switch from being parallel to being antiparallel to the direction of magnetization of the fixed magnetic layer 408 (e.g., fixed magnetic layer at magnetization of 1, while free magnetic layer at magnetization of −1). After a certain time greater than the minimum switching time TIEC, the voltage VREC-MTJ returns to 0 V, at which the direction of magnetization of the free magnetic layer 406 will remain stable until application of another voltage VREC-MTJ greater than the MTJ threshold voltage VTH-MTJ.
At time T=25 ns, the voltage VREC-MTJ is raised to 1.3 V, which corresponds to a negative IEC (ferromagnetic) and the magnitude is above the switching threshold. After the minimum switching time TIEC, the IEC causes the direction of the magnetization of the free magnetic layer 406 to switch back from being antiparallel to being parallel to the direction of the magnetization of the fixed magnetic layer 408 (e.g., both at magnetization of 1). After a certain time greater than the minimum switching time TIEC, the voltage VREC-MTJ returns to 0 V, where the direction of magnetization of the free magnetic layer 406 will remain stable until application of another voltage VREC-MTJ greater than the MTJ threshold voltage VTH-MTJ.
At time T=40 ns, the voltage VREC-MTJ is raised from 0 V to 1.0 V, which corresponds to a positive IEC (anti-ferromagnetic), but the magnitude of the IEC is below the switching threshold. Thus, the direction of magnetization of the free magnetic layer 406 remains unchanged (i.e., parallel to the direction of magnetization of the fixed magnetic layer 408). Herein, the REC-MTJ 402 is configured to switch the magnetization direction of the free magnetic layer 406 relative to the magnetization direction of the fixed magnetic layer 408 from antiparallel to parallel in response to the voltage VREC-MTJ at P3 level, and from parallel to antiparallel in response to the voltage VREC-MTJ at P2 level.
The voltage levels P2 and P3 are shown in FIG. 5C as square waves having instantaneous rise times and fall times. In practice, the rise times of the voltage VREC-MTJ should be approximately 10 ps and the fall times should be approximately 10 ps. The voltage VREC-MTJ corresponding to voltage level P3 at a higher energy state 504 of the QW 506 should be reduced quickly to 0 V to avoid unintentionally changing the magnetization direction. For example, if the voltage VREC-MTJ is raised to 1.6 V to set the magnetization directions to be antiparallel, and the voltage VREC-MTJ then decreases slowly, such that the voltage VREC-MTJ is near 1.3 V for at least the minimum switching time TIEC, the magnetization of the free layer 406 could unintentionally return to a parallel state (e.g., corresponding to voltage level P2).
As discussed above, the magnetization direction of the free magnetic layer 406 may be switched by IEC in the presence of a voltage-controlled electric field corresponding to a discrete energy state 504 of the QW 506 formed by the resonant tunnel barrier 405. The pulses of the voltage VREC-MTJ illustrated in FIG. 5C provide an IEC with a magnitude above a switching threshold and a duration of at least a minimum switching time TIEC required for switching the magnetization direction.
For the REC-MTJ 402, the magnitude of the voltage VREC-MTJ decreases as the thickness of the spacer layer 412 is increased. Thus, in the REC-MTJ 402, the magnetization direction of the free magnetic layer 406 relative to the magnetization direction of the fixed magnetic layer 408 corresponds to the magnitude of the voltage VREC-MTJ between the fixed magnetic layer 408 and the free magnetic layer 406, and the magnitude of the voltage VREC-MTJ is inversely related to the thickness of the spacer layer 412. However, increasing the thickness of the spacer layer 412 increases the distance between the fixed magnetic layer 408 and the free magnetic layer 406; hence the IEC strength decreases.
In addition, the magnitudes of the voltage VREC-MTJ for observing the IEC peaks depend on a width of the QW 506, which corresponds to the thickness of the spacer layer 412. Specifically, the magnitudes of the voltage VREC-MTJ for observing the IEC peaks decrease with an increase in the width of the QW 506, and the magnitudes of the voltage VREC-MTJ for observing the IEC peaks are inversely related to the thickness of the spacer layer 412. Furthermore, the voltage VREC-MTJ required to maintain a particular magnitude of IEC increases with the height ΔBC of the QW 506. That is, the magnitude of the IEC diminishes with an increase in height ΔBC of the QW 506, even in the presence of a higher magnitude level of the voltage VREC-MTJ.
The electrical resistance of the REC-MTJ 402 in the condition that the magnetization directions of the fixed and free magnetic layers 408 and 406 are antiparallel is higher than the electrical resistance of the REC-MTJ 402 in the condition that the magnetization directions of the fixed and free magnetic layers 408 and 406 are parallel. The parallel or antiparallel state represents a binary value, and binary data is written into the REC-MTJ 402 by setting the relative magnetization directions to be parallel or antiparallel.
FIG. 5D illustrates MR of the REC-MTJ 402, which exhibits voltage-dependent oscillation due to the resonant tunneling. For the materials combination considered here (the fixed magnetic layer 408 formed of Co having a thickness of 10 nm, the free magnetic layer 406 formed of Co having a thickness of 1 nm, the oxide layers 410 formed of MgO having a thickness of about 1 nm, and the spacer layer 412 formed of Ru having a thickness of 0.8 nm). The REC-MTJ 402 exhibits a MR change about 20%-40% between ‘0’ and ‘1’ states (between antiparallel and parallel conditions of the magnetization direction of the free magnetic layer 406 and the magnetization direction of the fixed magnetic layer 408). Note that the MR is higher for a smaller operating voltage, which is in a read operating voltage region. IEC, however, is lower for a larger operating voltage, which is a write operating voltage region. Thus, the read and write operating voltage regions are decoupled.
Compared to the MTJ 302, the REC-MTJ 402 does not need a change in the voltage polarity across itself to achieve the ‘0’ and ‘1’ states, requires a lower current density (e.g., <104 A/cm2) for fast switching between the ‘0’ and ‘1’ states, and enables the read and write operating voltage regions to be well-separated.
The REC-MTJ 402 is connected in series with the controlled transistor 404 at a connection node NCON. A gate of the controlled transistor 404 is connected to a WL, an open terminal of the REC-MTJ 402 (i.e., a terminal at the fixed magnetic layer 408) is connected to a BL, and an open terminal of the controlled transistor 404 (i.e., a terminal at a source of the controlled transistor 404) is connected to a SL. The voltage VREC-MTJ is a voltage between the BL and the connection node NCON. In order to achieve low magnitudes of the voltage VREC-MTJ for observing the IEC peaks, the spacer layer 412 needs a relatively large thickness, and consequently has a very large baseline resistance >10 M. Herein, the baseline resistance refers to a resistance of the REC-MTJ 402. Notice that although the REC-MTJ 402 only exhibits an about 20-40% MR change, but the change is based on the very large baseline resistance >10 M. Therefore, the 20-40% MR change is still enough to produce a reasonable voltage change across the REC MTJ 402 and the controlled transistor 404 for read-out.
However, it is difficult to use a single transistor to select a bit, since most of the applied voltage drops across the high resistance REC-MTJ 402, and an unphysically large voltage is needed to drive the transistor to saturation.
FIG. 6 provides an exemplary magnetic memory structure 600 with a voltage-controlled gain-cell configuration and utilizing the REC-MTJ 402 according to one embodiment of the present disclosure. Besides the REC-MTJ 402, the magnetic memory structure 600 further includes a first transistor 602, a second transistor 604, and a resistor 606 (with a resistance Ro) to form a gain-cell configuration. Herein, the magnetic memory structure 600 is a new REC-MRAM with a voltage-controlled gain-cell configuration.
In detail, the REC-MTJ 402 with a large baseline resistance (e.g., >10 MΩ) is connected in series with the first transistor 602 at a connection node NCON. A gate of the first transistor 602 is connected to a WL, an open terminal of the REC-MTJ 402 (i.e., a terminal at the fixed magnetic layer 408) is connected to a BL, and an open terminal of the first transistor 602 (i.e., a terminal at a source of the first transistor 602) is connected to a first SL1. A gate of the second transistor 604 is connected to the connection node NCON. A drain of the second transistor 604 is connected to a bias voltage power with a voltage VDD via the resistor 606, and a source of the second transistor 604 is connected to a second SL2. An output voltage VOUT of the magnetic memory structure 600 is provided at the drain of the second transistor 604. The first and second transistors 604 and 606 can be implemented with any emerging transistor technologies with any semiconductor material, e.g., bulk complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI) technologies, Fin field-effect transistors (FETs), negative-capacitance (NC) FETs, etc.
At the BL, a BL voltage VBL is provided to provide a power supply to the REC-MTJ 402 and the first transistor 604. A WL voltage VWL is applied at the WL to turn on the first transistor 602 to provide a gate voltage VX to the second transistor 604, if the WL voltage VWL is larger than a first threshold voltage VTH1 of the first transistor 602. The bias voltage VDD and the resistor 606 are designed, such that the bias voltage VDD appears as the output voltage VOUT when the gate voltage VX is smaller than a second threshold voltage VTH2 of the second transistor 604, and a voltage at the second SL2 appears as the output voltage VOUT when the gate voltage VX is larger than the second threshold voltage VTH2 of the second transistor 604. In a non-limited example, the bias voltage VDD=1 V, the resistor 606 is 100 kΩ, and the first and second SL1 and SL2 are connected to ground.
For a write operation, the WL voltage VWL is set such that conductance of the first transistor 602 increases and the majority of the BL voltage VBL drops across the REC-MTJ 402, and the gate voltage VX is very close to the voltage level of the first SL1. As such, the second transistor 604 is off during the write operation. The BL voltage VBL can be set to two different amplitudes (with a same polarity) so as to switch the free magnetic layer 406 and the fixed magnetic layer 408 of the REC-MTJ 402 to antiparallel and parallel conditions, and consequently achieve bidirectional switching. In a non-limited example, the WL voltage VWL is set to 1.2V, and the BL voltage VBL is set to 2 V and 1.6 V (the voltage VREC-MTJ across the REC-MTJ 402 is about 1.6 V and 1.3 V) for writing ‘1’ and ‘0’ operations (antiparallel and parallel conditions) respectively. Note that the current through the REC-MTJ 402 is very low during switching, and hence, the REC-MTJ 402 can be scaling down without the reliability issue. In addition, the first transistor 602 does not need to accommodate a large current and consequently does not need to be very large in size (different from the case in the STT-MRAM 300), which is attractive for further density scaling in MRAM technology.
On the other hand, for a read-operation, the WL voltage VWL is set such that the first transistor 602 is in a triode region and acts like a linear resistor. In this read-operation, the series connection of the REC-MTJ 402 and the first transistor 602 acts like a voltage divider. Therefore, the BL voltage VBL drops across REC-MTJ 402 and the first transistor 602 according to their resistances. The I-V characteristics of the first transistor 602 in the triode region is governed by:



 
  
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where μn is the mobility of the channel of the first transistor 602, Cox=εox/tox is a gate capacitance per unit area of the first transistor 602, εox is the permittivity of the gate oxide, tox is the thickness of the gate oxide, W is the width of the first transistor 602, L is the channel length of the first transistor 602, VTH1 is the threshold voltage of the first transistor 602 and VDS is the voltage across the drain and source of the first transistor 602. The resistance of the first transistor 602 in the triode region is roughly given by VDS/I1. In order to make the resistance of the first transistor 602 comparable to the large baseline resistance of the REC-MTJ 402, a very low



 
  
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is needed.

For the read operation, in a non-limited example, the WL voltage VWL is set to 0.6 V. The BL voltage VBL is divided between the REC MTJ 402 and the first transistor 602, such that, at the connection node NCON, the gate voltage VX<VTH2 (i.e., the threshold voltage of the second transistor 604) or VX>VTH2, when the REC-MTJ 402 corresponds to ‘1’ state (antiparallel condition) or ‘0’ state (parallel condition) respectively. It is because when the magnetization direction of the free magnetic layer 406 is parallel to the magnetization direction of the fixed magnetic layer 408, the resistance of the REC MTJ 402 will be relatively small, and the gate voltage VX will be relatively large (>VTH2). When the magnetization direction of the free magnetic layer 406 is antiparallel to the magnetization direction of the fixed magnetic layer 408, the resistance of the REC MTJ 402 will be relatively large, and the gate voltage VX will be relatively small (<VTH2). Thus, depending on the magnetization state (antiparallel condition or parallel condition), the second transistor 604 is either on or off with the output voltage VOUT about 0 V or VDD, respectively. As such, an output current I2 flowing through the second transistor 604 will significantly change. The read-out is enabled by sensing the current change of the output current I2 to determine the ‘0’ state or ‘1’ state of the REC MTJ 402.
FIGS. 7A-7F provide operation simulations of the magnetic memory structure 600 illustrated in FIG. 6. In this example, 45 nm NMOS are used as transistors with W=150 nm and L=500 nm for the first transistor 602, and W=150 nm and L=45 nm for the second transistor 604, the resistance Ro of the resistor 606 is set to 100 kΩ, the bias voltage VDD is set to 1V, and the SL1 and SL2 are connected to ground. However, the operation of the magnetic memory structure 600 is not limited to these parameters and various other combinations are possible.
The operation simulation shown in FIGS. 7A-7F performs 5 operation steps within 25 ns, 5 ns for each operation step. The initial condition of the magnetization direction of the free magnetic layer 406 is parallel to the magnetization direction of the fixed magnetic layer 408 (magnetization M=1), and the REC MTJ 402 is at a ‘1’ state. A read operation is applied in a first operation step (i.e., 0-5 ns), where the WL voltage VWL=0.6V with 5 ns time width and the BL voltage VBL=0.6V with 4.2 ns time width. Herein, the applied WL voltage VWL makes the first transistor 602 is in a triode region and acts like a linear resistor. As described above, when the REC-MTJ 402 corresponds to ‘1’ state (i.e., at the parallel condition), the gate voltage VX for the second transistor 604 is smaller than the threshold voltage VTH2. Therefore, the second transistor 604 is off, the output voltage VOUT is about VDD (about 1V in this example), and the output current I2 is about 10 nA. This first operation step confirms that the magnets are parallel, and the storage magnet is ‘1’.
In a second operation step (i.e., 5-10 ns), a write ‘0’ operation is performed, where the WL voltage VWL=1.2 V with 5 ns time width and the BL voltage VBL=2 V with 4.2 ns time width. A majority of the BL voltage VBL (about 1.6 V) drops across the REC-MTJ 402, and induces REC (JEX>0), which switches the magnetization direction of the free magnetic layer 406 antiparallel to the magnetization direction of the fixed magnetic layer 408 (magnetization M=−1) and switches the REC MTJ 402 to a ‘0’ state.
This write ‘0’ operation is followed by another read operation in a third operation step (i.e., 10-15 ns), where the WL voltage VWL=0.6V with 5 ns time width and the BL voltage VBL=0.6V with 4.2 ns time width. Herein, the magnetization direction of the free magnetic layer 406 is antiparallel to the magnetization direction of the fixed magnetic layer 408 (magnetization M=−1), and the REC MTJ 402 is at a ‘0’ state. As describe above, when the REC-MTJ 402 corresponds to ‘0’ state, (i.e., at the antiparallel condition), the gate voltage VX for the second transistor 604 is larger than the threshold voltage VTH2. Therefore, the second transistor 604 is turned on by the gate voltage VX, the output voltage VOUT is about 0V, and the output current I2 is about 10 μA. Note that the output current I2 through the second transistor 604 changes at least 103 times between the ‘0’ and ‘1’ states. Such a large separation of the two states is achieved by the magnetic memory structure 600 with this voltage-controlled gain-cell configuration.
Next, in a fourth operation step (i.e., 15-20 ns), a write ‘1’ operation is performed using the WL voltage VWL=1.2 V with 5 ns time width and the BL voltage VBL=1.6 V with 4.2 ns time width, which switches the magnetization direction of the free magnetic layer 406 parallel to the magnetization direction of the fixed magnetic layer 408 (magnetization M=1) and switches the REC MTJ 402 to a ‘1’ state.
Finally, the write ‘1’ operation is followed by a third read operation in a fifth operation step (i.e., 20-25 ns), where the WL voltage VWL=0.6V with 5 ns time width and the BL voltage VBL=0.6V with 4.2 ns time width. Herein, the magnetization direction of the free magnetic layer 406 is parallel the magnetization direction of the fixed magnetic layer 408 (magnetization M=1), and the REC MTJ 402 is at a ‘1’ state. Similar to the first read operation, the gate voltage VX for the second transistor 604 is smaller than the threshold voltage VTH2. Therefore, the second transistor 604 is off, the output voltage VOUT is about VDD (about 1V in this example), and the output current I2 is about 10 nA. This fifth operation step also confirms that the output current I2 through the second transistor 604 changes at least 103 times between the ‘0’ and ‘1’ states.
FIG. 8A illustrates comparisons of write energy consumption and write latency of the exemplary magnetic memory structure 600 (i.e., new REC-MRAM) and existing MRAM technologies. For non-volatile memory structures, the magnetic memory structure 600 with the REC MTJ 402 has a shortest write delay (about 1.2 ns) with a lowest write energy consumption (about 30 fJ). Compared to the volatile dynamic random access memory (DRAM), the magnetic memory structure 600 with the REC MTJ 402 has a shorter write delay and comparable write energy consumption. In addition, compared to the static random access memory (SRAM), the magnetic memory structure 600 with the REC MTJ 402 has a longer write delay and higher write energy, however, the SRAM is volatile and requires a large device area.
FIG. 8B illustrates comparisons of read energy consumption and read latency of the exemplary magnetic memory structure 600 (i.e., new REC-MRAM) and existing MRAM technologies. For non-volatile memory structures, the magnetic memory structure 600 with the REC MTJ 402 has a shortest read delay (about 0.6-1.1 ns) with a lowest write energy consumption (about 7-40 fJ). Compared to the volatile DRAM, the magnetic memory structure 600 with the REC MTJ 402 has a shorter read delay and lower read energy consumption. In addition, compared to the SRAM, the magnetic memory structure 600 with the REC MTJ 402 has a longer read delay and comparable read energy consumption, however, the SRAM is volatile and requires a large device area.
In summary, the non-volatile magnetic memory structure 600 exhibits attractive energy consumption and latency performances. In addition, in the magnetic memory structure 600, the REC MTJ 402 does not have reliability issues due to a thin oxide layer and is compatible with the small transistors due to low current density. Furthermore, the magnetic memory structure 600 offers a significant read-out current change between 103 times and 109 times (at least 103 times change in this example) depending on the CMOS technology used. The smaller transistors and large-read margins are attractive for further density scaling. In the present disclosure, the magnetic memory structure 600 exhibits an efficient read-out scheme by utilizing the REC MTJ 402. However, the REC MTJ 402 can be replaced by any one two-terminal memory resistive device, which has a large baseline resistance (e.g., >10 MΩ), requires voltage pulses (with same polarity) to switch between two memory state (e.g., between the parallel state and the antiparallel state, or between the ‘1’ state and the ‘0’ state), and exhibits a resistance change between the two memory states.
It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

## Claims

1. A magnetic memory structure, comprising:
a two-terminal memory resistive device with a first terminal connected to a bit line (BL), wherein:
the memory resistive device has a baseline resistance larger than 10 MΩ; and
the memory resistive device is eligible to exhibit a ‘1’ state and a ‘0’ state, and exhibit a resistance change between the ‘1’ state and the ‘0’ state;

a first transistor connected in series between a second terminal of the memory resistive device and a first source line (SL); and
a second transistor having a gate connected to the second terminal of the memory resistive device, a drain connected to a bias voltage power, and a source connected to a second SL, wherein:
when the memory resistive device exhibits the ‘1’ state, a gate voltage at the gate of the second transistor is smaller than a threshold voltage of the second transistor; and
when the memory resistive device exhibits the ‘0’ state, the gate voltage at the gate of the second transistor is larger than the threshold voltage of the second transistor.

2. The magnetic memory structure of claim 1, the memory resistive device is configured to switch between the ‘1’ state and a ‘0’ state by applying voltage pulses, which have different amplitudes with a same polarity.

3. The magnetic memory structure of claim 1, wherein corresponding to the ‘0’ state and the ‘1’ state, a current flowing through the second transistor changes between 103 times and 109 times in amplitude.

4. The magnetic memory structure of claim 1, wherein the first SL and the second SL are connected to ground.

5. The magnetic memory structure of claim 1 further comprising a resistor, which is connected in series between the drain of the second transistor and the bias voltage power.

6. The magnetic memory structure of claim 1, wherein each of the first transistor and the second transistor is implemented with one of bulk complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI) technologies, Fin field-effect transistors (FETs), and negative-capacitance (NC) FETs.

7. The magnetic memory structure of claim 1, wherein a magnetoresistance (MR) change of the memory resistive device is between 20%-40% between the ‘0’ state and the ‘1’ state.

8. The magnetic memory structure of claim 1, wherein the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ), and comprises:
a fixed magnetic layer;
a free magnetic layer; and
a resonant tunnel barrier disposed between the fixed magnetic layer and the free magnetic layer, wherein:
when the memory resistive device exhibits the ‘1’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is parallel; and
when the memory resistive device exhibits the ‘0’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel.

9. The magnetic memory structure of claim 8, wherein:
the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer is parallel in response to a first BL voltage applied to the BL;
the magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel in response to a second BL voltage applied to the BL; and
the first BL voltage and the second BL voltage have different amplitudes and a same polarity.

10. The magnetic memory structure of claim 9, wherein the first BL voltage and the second BL voltage change interlayer exchange coupling (IEC) between the fixed magnetic layer and the free magnetic layer of the REC MTJ above a threshold, at which the magnetization direction of the free magnetic layer is determined by the magnetization direction of the fixed magnetic layer.

11. The magnetic memory structure of claim 8, wherein the fixed magnetic layer and the free magnetic layer each comprises one of iron (Fe), cobalt (Co), nickel (Ni), lanthanum strontium manganite (LSMO), cobalt iron boron (CoFeB), and cobalt iron (CoFe).

12. The magnetic memory structure of claim 11, wherein the fixed magnetic layer has a thickness in a range of 5 nm to 100 nm, and the free magnetic layer has a thickness in a range of 1 nm to 3 nm.

13. The magnetic memory structure of claim 8, wherein the resonant tunnel barrier comprises:
a spacer layer disposed between the fixed magnetic layer and the free magnetic layer;
a first oxide layer disposed between the fixed magnetic layer and the spacer layer; and
a second oxide layer disposed between the spacer layer and the free magnetic layer.

14. The magnetic memory structure of claim 13, wherein:
the spacer layer comprises one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi); and
the first oxide layer and the second oxide layer each comprise one of magnesium oxide (MgO), magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx), iron oxide (Fe2O3), titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), rhodium oxide (Rh2O3), tantalum oxide (Ta2O3), vanadium oxide (V2O5), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

15. The magnetic memory structure of claim 14, wherein the first oxide layer and the second oxide layer each has a thickness in a range of 0.5 nm to 3 nm, and the spacer layer has a thickness in a range of 0.1 nm to 4 nm.

16. The magnetic memory structure of claim 1, wherein the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ), and comprises:
a fixed magnetic layer;
a free magnetic layer; and
a resonant tunnel barrier providing a quantum well between the fixed magnetic layer and the free magnetic layer, wherein:
when the memory resistive device exhibits the ‘1’ state, an interlayer exchange coupling (IEC) in the resonant tunnel barrier achieves a first IEC peak;
when the memory resistive device exhibits the ‘0’ state, the IEC in the resonant tunnel barrier achieves a second IEC peak; and
the first IEC peak and the second IEC peak have different polarities.

17. The magnetic memory structure of claim 16, wherein:
the first IEC peak is achieved in response to a first BL voltage applied to the BL;
the second IEC peak is achieved in response to a second BL voltage applied to the BL; and
the first BL voltage and the second BL voltage have different amplitudes and a same polarity.

18. The magnetic memory structure of claim 16, wherein the resonant tunnel barrier comprises:
a spacer layer disposed between the fixed magnetic layer and the free magnetic layer;
a first oxide layer disposed between the fixed magnetic layer and the spacer layer; and
a second oxide layer disposed between the spacer layer and the free magnetic layer.

19. The magnetic memory structure of claim 18, wherein:
the spacer layer comprises one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi); and
the first oxide layer and the second oxide layer each comprise one of magnesium oxide (MgO), magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx), iron oxide (Fe2O3), titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), rhodium oxide (Rh2O3), tantalum oxide (Ta2O3), vanadium oxide (V2O5), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

20. The magnetic memory structure of claim 19, wherein the first oxide layer and the second oxide layer each has a thickness in a range of 0.5 nm to 3 nm, and the spacer layer has a thickness in a range of 0.1 nm to 4 nm.