# Patent

## Title
Circuit and method for evaluation overload condition in flyback converter

## Abstract

A circuit and a method for evaluating a load condition in a flyback converter are disclosed. A first current source is used for providing a preset current ISUM equal to a sum of the off current value IOFF and the blanking current value ILEB to charge a first capacitor, and a second current source is used for providing a reference current IREF to charge a second capacitor. A comparator receives a voltage applied on the first capacitor at its positive input end and a voltage applied on the second capacitor at its negative input end. The output current transmitted to the load by the flyback converter is varied to the change of the preset current ISUM, as such the load condition is detected by the comparison result generated by the comparator.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of a Chinese patent application number 201410791004.6 filed Dec. 17, 2014 by a common inventor of this Application. The entire Disclosure made in the Chinese patent application number 201410791004.6 is hereby incorporated by reference.
TECHNICAL FIELD
The present invention relates to a power conversion system, and in particular, to the detection and evaluation of the output current in a voltage flyback converter applied in a power supply to decide whether the converter accesses into an overload condition.
BACKGROUND ART
Conventional power conversion systems generally use a power switching in constant voltage or a constant current mode. In a power conversion system, switch element on the primary winding of a transformer is turned on or off periodically producing a current flowing through the primary winding of the transformer, thus the energy at the primary side is transferred to the secondary side, and the AC current generated on a secondary winding is rectified and filtered while passing through an injection diode and a capacitor and converted into a direct current supplied to the load. However, the prior art is facing a problem in accurate evaluation of the output current provided to the load, especially in a Continuous Conduction Mode (CCM) and a Discontinuous Conduction Mode (DCM). Furthermore, the prior art is facing a problem in setting an output current basis to decide whether a flyback voltage converter accesses into an overload condition.



BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of this invention are described in more detail with reference to the accompanying drawings. However, the accompanying drawings are for the purpose of descriptions and illustrations only and do not impose limitation to the scope of the present invention:
FIG. 1 shows a simplified circuit drawing of a flyback converter of the present invention.
FIG. 2A shows waveform of a primary current and waveform of a secondary current controlled by a main switch driven by a control signal while in CCM.
FIG. 2B shows the waveform of the primary current and waveform of the secondary current controlled by the main switch driven by a control signal in DCM.
FIG. 3 shows the waveform of a leading edge blanking signal LEB used for shielding the initial spike of the leading edge of a sensing signal at the moment the main switch is driven to turn on.
FIG. 4A to FIG. 4C show the stepped current waveforms of the primary current and the secondary current in the CCM.
FIG. 5A to FIG. 5C show the triangular current waveforms of the primary current and the 15 secondary current in the DCM.
FIG. 6A to FIG. 6D show a conventional calculation circuit for calculating the average output current.
FIG. 7 shows a calculation circuit for detecting and summing an off current value and a blanking current value.
FIG. 8 shows an overload detection circuit of the prevent invention for calculating the average output current and deciding whether it is overload.
FIG. 9 shows a waveform of a second capacitor charged in the whole cycle.
FIG. 10 shows a waveform of the second capacitor charged in a half of the cycle.
FIG. 11 shows the change in output results of a monostable multivibrator from the light load to the heavy load in a DCM.
FIG. 12 shows the change in the output results of the monostable multivibrator from the light load to the heavy load in a CCM.
FIG. 13 shows circuit diagrams of the detection module and sample-and-hold latch of the calculation circuit in FIG. 7.



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 1 shows a circuit diagram of a flyback voltage converter of the present invention, which includes a main switch QM at the primary side, such as a power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), having a drain as an input terminal, a source as an output terminal, and a gate as a control terminal. The main switch QM receives a control signal sent by a main control module 102 at its control terminal and correspondingly turns on or off thus controlling the current flowing through a primary winding 130A of a transformer 130 of the flyback converter to transmit the energy at the primary side to the secondary side. The primary winding 130A receives a DC input voltage VIN, which can be obtained by the rectification of a supply AC voltage VAC through a bridge rectifier and other rectifying elements. The transformer 130 also includes a secondary winding 130B for delivering an output voltage VOUT and an auxiliary winding 130C for detecting a voltage condition produced on the secondary winding 130B. The polarity of the auxiliary winding 130C and that of the secondary winding 130B are the same but are opposite to that of the primary winding 130A. One end of the auxiliary winding 130C is grounded and the other end is connected to the anode of a diode DAUX, while the cathode of the diode DAUX is connected to a capacitor CAUX, so that the AC voltage produced on the auxiliary winding 130C is rectified to charge the capacitor CAUX as an auxiliary power supply, so that a voltage VCC stored on the capacitor CAUX is related to and is proportional with the output voltage VOUT, and the voltage VCC can separately provide a DC voltage source for the main control module 102. The secondary winding 130B is connected with a diode DO and a capacitor for CO of a rectifier—filter circuit for producing the output voltage VOUT of the flyback converter. The DC output voltage VOUT is applied on a load RL and thus generates an output current IOUT flowing through the load RL. In a feedback loop of the converter, a sensing resistor RS is connected between the source of the main switch QM and the ground. The sensing resistor RS is used for sensing and detecting a primary current IP flowing through the primary winding 130A and providing a feedback voltage that equals a product of the primary current IP and the resistance of the inductive resistor RS, i.e., a voltage sensing signal VCS. The primary current IP can be used for representing a secondary current IS flowing through the secondary winding 130B, and the functional relationship between the primary current IP and secondary current IS will be described in detail later. A sensing port CS of the main control module 102 detects the primary current IP of the primary winding 130A using the sensing resistor RS in real time as a basis to decide whether it is necessary to adjust the control signal to control the on/off state of the main switch QM. The topology and operation mode of the flyback converter are well known in the art, thus the circuit diagram and the specific operation mode will not be described here.
As shown in FIG. 2A, in the continuous conduction mode (CCM), the main switch QM is driven to turn on/off by a control signal such as a pulse width modulation (PWM) signal and likes. In FIG. 2A, the waveform of a primary current IP1 flowing through the primary winding 130A, the waveform of a secondary current IS1 flowing through the secondary winding 130B, and the waveform of a differential voltage VDS1 between the drain and the source of the main switch QM are shown. At the initial stage of the on time period TON of the main switch QM, the primary current IP1 has a step leading edge and begins to increase linearly from the leading edge, and at the off period TOFF of the main switch QM, the secondary current IS1 is an attenuating triangular wave. Thus in the following cycle at the instance when the main switch QM is about to turn on, there is still current remain in the secondary winding 130B, i.e. in the following cycle when the main switch QM turns on, the energy stored in the transformer 130 is not completely drained.
FIG. 2B shows the waveform of a primary current IP2 flowing through the primary winding 130A, the waveform of a secondary current IS2 flowing through the secondary winding 130B, and the waveform of a differential voltage VDS2 between the drain and the source of the main switch QM in the discontinuous condition mode (DCM) of the converter. As shown in this figure under the DCM, the primary current IP2 does not have a step leading edge, and the secondary current IS2 is a direct attenuating triangular wave during the off time TOFF of the main switch QM, which is attenuated to zero at the end of the TOFF before the start of the next cycle, and the energy of the main switch QM stored in the primary winding 130A during the on period has been completely transferred to the load by the secondary winding 130B before the start of the next cycle. A difference between the DCM and the CCM in any cycle is that the secondary current IS2 will reduce to zero when the control signal turns off the main switch QM, and a period of dwell-time TD will exist between the time when the primary current IS2 reduces to zero and the start of the next cycle (i.e., the moment the main switch QM is turned on again).
As shown in FIG. 3, a leading edge blanking signal LEB, which is well known in the art, is implemented to prevent unnecessary incorrect trigger during the detection of the primary current IP since the primary current IP often has a initial pulse peak at the instance the main switch QM in the primary current loop. The initial spike will be fed back to the main control module 102 at the sensing port CS, and if the sensing resistor RS connected in series with the primary winding captures the current value and uses it as the sensing signal VCS to control the on/off state of the power switch, causing a false trigger action due to an unexpected initial spike 355 of the sensing signal VCS in FIG. 3 thus further initiating an over-current protection system, so that the main control module 102 will not send the PWM signal and erroneously turning off the power main switch QM to protect the power switch and/or the entire flyback converter even though there is no actual over-current condition. A variable or fixed leading edge blanking signal LEB generated by the conventional leading edge blanking circuit is used for eliminating such risks of false trigger, and the signal can be coupled to the control terminal of the main switch QM to ensure the main switch QM is not erroneously turned off during the period in which the leading edge blanking signal LEB is at high level, and the current signal is sampled on the sensing resistor RS after the leading edge blanking signal LEB is ended to capture a true and precise initial value of the sensing signal VCS, and thereby shielding the initial pulse peak of the primary current IP at the moment the main switch QM is turned on. The conventional power design instruction manuals disclose the design of a leading edge blanking circuit, and for more detailed description, U.S. Pat. Nos. 8,278,830 and 8,300,431 and other literature can also used as references.
Referring to FIG. 4A to FIG. 4C, when the flyback converter enters into the CCM, the control signal will drive the main switch QM to turn on at the initial time t11 of a cycle. Due to the remaining energy in the transformer 130, the primary current IP quickly jumps from zero to an initial leading edge value IPV at the moment the main switch QM is turned on, which is an initial step leading edge value greater than zero. In the following period from t11 to t13, as the control signal continues to drive the main switch QM to be on, the primary current IP continues to gradually increase at a linear rate from the leading edge initial value IPV. It should be noted that at the time t13, the control signal changes from a high level to a low level and intends to turn off the main switch QM, however the primary current does not drop immediately, but during the period of the delay time TP from t13 to t14, the primary current IP rises to the maximum peak current IPP at the same rate as that in the period from t11 to t13, and quickly drops from the peak value IPP to zero at the time t14 at the end of the delay time TP. As shown in FIG. 4B to FIG. 4C, in the period from t14 to t15, the control signal drives the main switch QM to turn off completely, and the stored energy in the primary winding 130A of the transformer 130 begins to be transmitted to the secondary winding 130B at time t14, while the secondary current IS flowing through the secondary winding 130B jumps from zero to the maximum current peak value ISP at the time t14, at this time, the polarity of the winding on the transformer 130 with the same marking is opposite with that of the different marking, so that the flyback voltage of the secondary winding 130B enables the rectifier diode DO in FIG. 1 to be forward bias to charge the output capacitor CO and to provide the load current, and the secondary current is gradually decreases at a constant rate in the period of time from t14 to t15. The cycle is ended at time t15, and the main switch QM is turned on again in the following cycle, but at this time the secondary current IS has an end state trailing edge final value ISV, which is an end state step value greater than zero. After time t15, the main switch QM is turned on again in the following cycle, and the secondary current IS drops from the end state trailing edge final value ISV to zero. For the CCM operation, the period from time t11 to time t15 can be viewed as a complete cycle TS, in which the period from time t11 to time t14 can be defined as the on-period TON during which the main switch QM is turned on, the period from time t14 to time t15 can be defined as the off-period TOFF in which the main switch QM is turned off, the duty ratio DB1 of the switch should be TON dividing the sum (TON+TOFF) of the on-period and the off-period, i.e., DB1=TON/(TON+TOFF).
The ratio of the number of turns NP of the primary winding 130A and the number of turns NS of the secondary winding 130B is set as N, where the peak current ISP of the secondary current IS at the secondary winding is equal to N×IPP, and the end state trailing edge value ISV of the secondary current IS at the secondary winding is equal to N×IPV. In the CCM of the flyback converter, the output current IO provided to the load RL meets the following function relationship:




  
    
      
        
          I
          O
        
        =
        
          
            
              
                I
                SP
              
              +
              
                I
                SF
              
            
            2
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          I
          O
        
        =
        
          
            
              N
              ×
              
                (
                
                  
                    I
                    PP
                  
                  +
                  
                    I
                    PV
                  
                
                )
              
            
            2
          
          ×
          
            (
            
              1
              -
              
                D
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            )
          
        
      
    
    
      
        (
        2
        )
      
    
  




Referring to FIG. 4A and FIG. 4C, at the time t13, the logic state of the control signal is intentionally changed from high level to low level thus driving the main switch QM to turn off, causing the primary current IP having an off current value IOFF, which is a transient value. As mentioned above, in the period of delay time TP from time t13 to time t14, the off current value IOFF is not the maximum value of the primary current IP, the primary current does not drop immediately even though the control signal has been changed from high level to low level at the time t13 thus turning off the main switch QM, but in fact, in the period from t13 to t14, the primary current IP continues to increase from the off current value IOFF, with a rate same as that of the period from the initial leading edge value IPV to the off current value IOFF, until the current IP reaches to the maximum value of the peak current IPP as shown in the peak of a dotted line in FIG. 4A. After the delay time TP is ended and the off-period TOFF starts, the main switch QM is turned off, the primary current IP quickly drops to zero from the peak current IPP at the time t14.
Referring to FIG. 3, at the time t12 the leading edge blanking signal LEB is changed from the high level to the low level ending its active state, a current value of the primary current IP is sampled as a blanking current value ILEB, which is an intermediate current value, and the primary current IP increases from the initial leading edge value IPV (leading edge step value) to the blanking current value ILEB initial with a rate of increment is totally the same as that of the primary current IP rises from the off current value IOFF to the peak current IPP. In a complete cycle, the length of time TLEB between the time t11 when the control signal drives the main switch QM on to the time t12 when the leading edge blanking signal LEB is ended is equal to the delay time TP between the time t13 when the control signal drives the main switch QM to turn off and the time t14 when the primary current IP rises to the peak current IPP, i.e., TLEB=TP. In addition, as shown in FIG. 4A, a current difference value ΔI1 between the peak current value IPP and the off current value IOFF is further defined, as such the current relationship can be calculated from geometric perspective of FIG. 4A as IPP=IOFF+ΔI1 and IPV=ILEB−ΔI1, then:

IPP+IPV=(IOFF+ΔI1)+(ILEB−ΔI1)  (3)

IPP+IPV=IOFF+ILEB  (4)

Substituting equation (4) into the equation (2), the output current IO in the CCM can be obtained:





  
    
      
        
          
            I
            O
          
          =
          
            
              
                N
                ×
                
                  (
                  
                    
                      I
                      OFF
                    
                    +
                    
                      I
                      LEB
                    
                  
                  )
                
              
              2
            
            ×
            
              
                T
                OFF
              
              
                T
                S
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            where
            ⁢
            
              
            
            ⁢
            
              T
              S
            
          
          =
          
            
              T
              ON
            
            +
            
              T
              OFF
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Neither IPP nor ISV is included in the expression of the secondary side output current IO shown in equation (5). Because the degree of overshoot and the overshoot peak value are difficult to detect and measure by the circuit in reality, thus it is almost impossible to rely on IPP or ISV for the calculation of the output current IO and equation (5) is a good solution to this problem in CCM.

Referring to FIG. 5A to FIG. 5C, when the flyback converter enters into the DCM, the control signal drives the main switch QM to turn on at the starting time t21 of one cycle. Since there is no remaining energy in the transformer 130 from the previous cycle, the initial leading edge value IPV of the primary current is almost zero at the moment the main switch QM is turned on, which is completely different from the initial step value greater than zero in the CCM. In the period from t21 to t23, as the control signal continues to drive the main switch QM turning on, the primary current IP gradually rises up in the constant rate from the initial leading edge value IPV of zero. At time t23, the control signal changes form the logic high level to the logic low level thus turning off the main switch QM, and similarly as mentioned above in the CCM the primary current does not drop down immediately, and instead in the period of the delay time TP from t23 to t24, the primary current IP rises to the maximum peak current IPP at the same rate of the period from t2, to t23, and then quickly drops to zero from the peak value IPP at the time t24 when the delay time TP is ended.
Referring to FIG. 5B and FIG. 5C, after the delay time TP is ended and in the period from t24 to t25, the control signal drives the main switch QM to turn off completely, and at the time t24 the primary winding 130A of the transformer 130 starts to transfer the stored energy to the secondary winding 130B, thus the secondary current IS flowing through the secondary winding 130B jumps from zero to the maximum current peak value ISP at the time t24, and the polarity of similarly marked end and that of the differently marked end of the windings of the transformer 130 are opposite, so that the flyback voltage of the secondary winding 130B enables the rectifier diode Do in FIG. 1 to be forward bias to charge the output capacitor CO and to provide the load current, and then the secondary current gradually decrease to zero at a constant rate in the period from t24 to t25. Another difference between the DCM and the CCM is that when the cycle is not ended, at the time t25, the secondary current IS has an end trailing edge value ISV of zero, in other words, the secondary current IS has decreased to zero at the end of the off-period TOFF before the start of the next cycle, and the energy stored in the primary winding 130A during the on-period of the main switch QM has been completely transferred to the load by the secondary winding 130B before the start of the next cycle. In FIG. 5C, the secondary current IS drops to zero at the end of the off-period TOFF when the control signal turns off the main switch QM. A period of dwell-time TD exists between the time t25 when the secondary current IS reduces to zero and the time t26 when the current cycle ended. The next cycle starts after time t26, so the dwell-time TD is between the time t25 when the secondary current IS reduces to zero and the time the main switch QM is turned on again in the next cycle. Specifically for the flyback converter in the DCM, the time t21 to time t26 can be viewed as a complete cycle TS, which includes a period from the time t21 to time t24 defined as the on-period TON in which the main switch QM is turned on, a period from the time t24 to time t25 defined as the off-period TOFF in which the main switch QM is turned off, and a period from the time t25 to time t26 viewed as the dwell-time TD in which the main switch QM is also turned off, as such the duty ratio DB2 of the switch at the primary side should be TON dividing the sum of the on-period TON, the off-period TOFF and the dwell-time TD, or DB2=TON/(TON+TOFF+TD).
The ratio of the number of turns NP of the primary winding 130A and the number of turns NS of the secondary winding 130B is set as N, where the peak current ISP of the secondary current IS at the secondary winding is equal to N×IPP, and the end trailing edge value ISV of the secondary current IS at the secondary winding is equal to zero. In the DCM of the flyback converter, the output current IO provided to the load RL meets the following function relationship:




  
    
      
        
          I
          O
        
        =
        
          
            
              
                I
                SP
              
              +
              
                I
                SV
              
            
            2
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          I
          O
        
        =
        
          
            
              N
              ×
              
                (
                
                  
                    I
                    PP
                  
                  +
                  
                    I
                    PV
                  
                
                )
              
            
            2
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




As shown in FIG. 5A and FIG. 5C, at time t23, the control signal changes from logic high level to logic low level driving the main switch QM to turn off causing the primary current IP having the off current value IOFF at the moment the control signal changing its logical state. In the period of the delay time TP from time t23 to time t24, the off current value IOFF does not reach the maximum value IPP of the primary current IP, and even at time t13 when the logical state of the control signal tends to turn off the main switch QM, the primary current IP does not drop immediately, but in fact, in the period from t23 to t24, the primary current IP continues to rise up from the off current value IOFF, with the rate same as that when it rises from the initial leading edge value IPV to the off current value IOFF, until the current IP reaching the maximum value of the peak current IPP, as shown by the vertex of a dotted line in FIG. 5A. Once the delay time TP is ended and the off-period TOFF starts at time t24, the main switch QM is completely turned off, the primary current IP really begins to quickly reduce to zero from the peak current IPP.
Referring to FIG. 5C, at time t22 when the leading edge blanking signal LEB changes from high level to low level ending its active state, a transient intermediate current value of the primary current IP is sampled as the blanking current value ILEB, where the rate of increment when the primary current IP rises from the initial leading edge value IPV (zero value) to the blanking current value ILEB is totally the same as that when the primary current IP rises from the off current value IOFF to the peak current IPP. In a complete cycle, the period between the time t21 when the control signal drives the main switch QM to turn on to the time t22 when the blanking signal LEB is ended is defined TLEB equal to the delay time TP, which is the period between the time t23 when the control signal drives to turn off the main switch QM and the time t24 when the primary current IP rises to the peak IPP, i.e., TLEB=TP; furthermore, a difference value ΔI2 between the peak current IPP and the off current value IOFF is further defined, and the current relationship can be calculated with the geometric perspective of FIG. 5A, and thus IPP=IOFF+ΔI2 and IPV=ILEB−ΔI2 can be further obtained.

IPP+IPV=(IOFF+ΔI2)+(ILEB−ΔI2)  (8)

IPP+IPV=IOFF+ILEB  (9)

If equation (9) is substituted into equation (7), the final expression of the output current IO in the DCM can be obtained, wherein the cycle TS equals to TON+TOFF+TD:





  
    
      
        
          I
          O
        
        =
        
          
            
              N
              ×
              
                (
                
                  
                    I
                    OFF
                  
                  +
                  
                    I
                    LEB
                  
                
                )
              
            
            2
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




Although the overshoot degree of the primary peak current IPP or the secondary end trailing edge current ISV are difficult to capture or detect, the equation (10) provides a good solution to this problem in the DCM, as the formula for calculating the output current IO does not contain the current value IPP or ISV.
With the cycle TS defined differently above in the CCM and the DCM, the formula (5) and the formula (10) can be expressed as:




  
    
      
        
          
            I
            O
          
          N
        
        =
        
          
            
              
                I
                OFF
              
              +
              
                I
                LEB
              
            
            2
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        
          
            I
            O
          
          N
        
        =
        
          
            I
            SUM
          
          ×
          
            
              T
              OFF
            
            
              T
              S
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




To decide whether the output current IO in the formula (5) and the formula (10) exceed a preset output current value due to overloading, (ISUM×TOFF)/TS needs to be evaluated to conform the formula (12), where the preset current ISUM equals to (ILEB+IOFF)/2. According to the formula (12), the calculation of the output current value IO only needs to capture the average current ISUM and the off-period TOFF of a complete cycle TS, so as the product of the average current ISUM multiplying with (TOFF/TS) is completely calculated. FIG. 6A to FIG. 6D show the conventional calculation circuits for calculating the average current ISUM, in which the voltage converted from the ISUM is compared with a reference value to determine whether the ISUM meets the requirements.
As shown in FIG. 6A, the circuit for calculating the average current ISUM includes a current source 271 supplying a current with the current value of ISUM and a switch SW10 connected between the current source 271 and the ground, only turned off during off-period TOFF of each cycle TS but turned on in the remaining time, so that the current source 271 provides a forward bias current through a diode 301, which includes the anode connected to a common node 281 between the current source 271 and the switch SW10, in the off-period TOFF but releases to the ground through the switch SW10 in the remaining time of the cycle TS, as such the average current of ISUM×(TOFF/TS) is obtained at the cathode of the diode 301. The circuit shown in FIG. 6B is basically the same as that in FIG. 6A, which includes a voltage V1 controlled by a switch SW11 and the diode 301 generating a current equivalent to the ISUM, where the switch SW11 controls the current generated through the diode 301 in only off-period TOFF of a cycle.
The circuit shown in FIG. 6C is basically the same as that in FIG. 6A excepting that a transconductance amplifier 302 is replaced for the diode 301 in FIG. 6A. A switch SW12 is only turned off in the off-period TOFF in each cycle Ts and is turned on in the remaining time, so that the current ISUM supplied by the current source 271 flows to a resistor R23 in the time TOFF, where one end of the resistor R23 is connected to the node 281 and also to the positive input end of the transconductance amplifier 302 and the negative input end of the transconductance amplifier 302 is connected to the grounded, thereby generating the average current of ISUM×TOFF/TS at the output end of the transconductance amplifier 302.
The circuit shown in FIG. 6D is basically the same as that in FIG. 6B excepting that the transconductance amplifier 302 is replaced for the diode 301 in FIG. 6B. A switch SW13 is only turned off in the off-period TOFF in each cycle Ts and is turned on in the remaining time, so that a voltage V2 is supplied to the positive input end of the transconductance amplifier 302 during the off-period TOFF and the average current of ISUM×TOFF/TS is obtained at the output end of the transconductance amplifier 302.
FIG. 7 shows a calculation circuit for calculating the average current of the present invention. As shown in this figure, a calculation circuit 280 is used for calculating the output current transmitting to the load by the secondary winding 130B in a flyback converter. The calculating circuit 280 includes a detection module 201 for detecting and capturing the primary current IP flowing through the primary winding 130A in a form of the sensing signal VCS crossing the sensing resistor RS since the primary current flowing through the sensing resistor RS at a certain time multiples with the resistance value of the sensing resistor RS resulting into the corresponding sensing signal VCS. Detection module 201 is also used as a current detector to selectively detect the precise values of the blanking current value ILEB and the off current value IOFF at the appropriate time. A circuit diagram of the detection module 201 of the circulating circuit 280 is shown in FIG. 13.
As shown in FIG. 13, in the detection module 201, a DC power supply voltage VDD is applied at a node 105 providing an operating voltage for the voltage-current converter 110 having an input end connected to a common node 101 of the sensing resistor RS connected to the source terminal of the main switch QM, which is mentioned above in FIG. 1. The voltage-current converter 110 is also referred as the first voltage-current converter. A conversion resistor R12 is connected between the output end of the voltage-current converter 110 and the ground, so that the voltage-current converter 110 will convert the sensing voltage VCS sent to its input terminal to an intermediate current that flows through the conversion resister R12 producing a voltage at a node 121 at the ungrounded end of the conversion resistor R12. As an option, a resistor R10 may be connected between the common node 101 and the input end of the voltage-current converter 110, and a capacitor C1 is connected between the input end of the voltage-current converter 110 and the ground, thus providing a relatively smooth sensing signal VCS transmitted to the input end of the voltage-current converter 110. As another option, an regulating resistor R11 with a variable resistance may be connected between the node 121 and the ground, where the regulating resistor R11 and the conversion resistor R12 of the detection module 201 are connected in parallel between the node 121 and the ground so that the total resistance between the node 121 and the ground becomes adjustable through the regulating resistor R1.
The detection module 201 also includes a first voltage follower 111 and a second voltage follower 112, where the positive input ends of the first voltage follower 111 and the second voltage follower 112 are connected with the node 121 at the ungrounded end of the conversion resistor R12, and the negative input end of the first voltage follower 111 is connected to its output end, while the negative input end of the second voltage follower 112 is connected to its output end. Each of the first voltage follower 111 and the second voltage follower 112 generates a voltage corresponding to the voltage applied at its positive input end. The first voltage follower 111 and the second voltage follower 112 are used as the input buffers that have a high input impedance for connecting with the signal source, since the high input impedance can isolate the level of interaction between input and output, and a low output impedance for reducing the capture time of the sensing signal VCS. The first voltage follower 111 and the second voltage follower 112 are operational amplifiers configured as the voltage followers or unity-gain buffers. In addition, as mentioned above, the sensing signal VCS needs to be captured at the appropriate time. Therefore, the detection module 201 further includes a switch SW1 referred as a first switch and a switch SW2 referred as a second switch, where the switch SW1 is connected between the output end of the first voltage follower 111 and a sample-and-hold latch 202, and the switch SW2 is also connected between the output end of the second voltage follower 112 and the sample-and-hold latch 202. The switch SW1, the switch SW2 and others that will be described later are all three-terminal electronic switches, each of which includes an input terminal and an output terminal opposite the input terminal and a control terminal for controlling the on or off between the input terminal and the output terminal. The electronic switches can be P-type or N-type MOS transistors, bipolar transistors, junction transistors or a combination thereof.
In the CCM, the detection module 201 detects a sensing signal VCS-LEB at corresponding to the time t12 in FIG. 4C at node 101 at one end of the sensing resistor RS. In addition to shielding the initial spike 355 of the sensing signal VCS, the leading edge blanking signal LEB also connects to the node 103 of the control terminal of the switch SW2, as such the switch SW2 is turned on when the leading edge blanking signal LEB has the logic high level and the change in the primary current IP is represented by the sensing signal VCS at the node 101. In any cycle, in the period TLEB from time t11 when the main switch QM is turned on to the time t12 when the leading edge blanking signal LEB changes from the high level to the low level, the primary current IP accordingly increases from the leading edge initial value IPV at time t11 to the blanking current value ILEB at the time t12, thus the change of the sensing signal VCS at the node 101 is detected by the detection module 201, then the voltage-current converter 110 will reconvert the current converted from the sensing signal VCS to a voltage applied at the node 121 at the ungrounded end of the conversion resistor R12. Specifically, although the dynamic sensing signal VCS is always transmitted to the voltage-current converter 110 in the time TLEB, but when the leading edge blanking signal LEB changes from high level to low level to turn off the switch SW2, the second voltage follower 112 is unable to convert the voltage at node 121 into the current after the time t12 and before the leading edge blanking signal LEB changes from low level to high level in the next cycle. At time t12, the sensing signal VCS-LEB of the blanking current value ILEB is fed to the input end of the voltage-current converter 110 and is converted to an intermediate transient current IM flowing through the conversion resistor R12; hence the intermediate transient current IM is further converted into the voltage drop crossing the conversion resistor R12, which equals to the voltage sensing signal VCS-LEB, while the second voltage follower 112 converts the voltage applied on the conversion resistor R12, i.e., the voltage applied at node 121, into a voltage that equals to the sensing signal VCS-LEB at its output end. After the leading edge blanking signal LEB changes from high level to low level, the final out voltage generated by the second voltage follower 112 in one cycle Ts is set to the level of the voltage sensing signal VCS-LEB corresponding to the time t12. The final out voltage generated by the second voltage follower 112 is sent to a second storage capacitor C3 of the sample-and-hold latch (S/H) 202 in the calculation circuit 280 to charge the second storage capacitor C3, and the switch SW2 is connected between one end of the second storage capacitor C3 at node 123 and the output end of the second voltage follower 112, while the other end of the second storage capacitor C3 is grounded. The second storage capacitor C3 is charged with the voltage equivalent to the voltage sensing signal VCS-LEB, thus the second storage capacitor C3 holds and stores the information of the blanking current value ILEB flowing through the primary winding 130A at time t12, and the stored information represents the voltage value VCS-LEB applied at node 123 at one end of the second storage capacitor C3.
Still in the CCM, the detection module 201 also detects a sensing signal VCS-OFF corresponding to the time t13 in FIG. 4C at node 101 at one end of the sensing resistor RS. The control signal, such as PWM, not only drives the control terminal of the main switch QM, but also drives the control terminal of the switch SW1, therefore the switch SW1 is always turned on when the control signal has the logic high level; otherwise, the switch SW1 is turned off. With gradually increasing of the primary current IP, the value of the primary current IP is totally reflected by the sensing signal VCS at node 101. In any cycle, in the period from time t11 when the main switch QM is turned on to time t13 when the control signal changes from the high level to the low level, the primary current IP accordingly increases from the leading edge initial value IPV to the off current value IOFF at time t13, thus the corresponding change of the sensing signal VCS is detected by the detection module 201 at node 101, and the voltage-current converter 110 reconverts the current value converted from the sensing signal VCS to a voltage value at node 121 at the ungrounded end of the conversion resistor R12. Specifically, although the dynamic sensing signal VCS is transmitted to the voltage-current converter 110 in the period from time t1 to time t13 in the CCM, and when the control signal changes from the high level to the low level to turn off the switch SW1, after the time t13 and before the control signal changes from low level to the high level in the next cycle, the first voltage follower 111 cannot convert the voltage value at node 121 into the current. The sensing signal VCS-LEB corresponding to time t13 representing the off current value IOFF is fed into the input end of the voltage-current converter 110 and is converted to the intermediate transient current IM flowing through the transfer resistor R12; then, the intermediate transient current IM is further converted into a voltage crossing the conversion resistor R12, which equals to the voltage sensing signal VCS-OFF, while the first voltage follower 111 further converts the voltage applied on the conversion resistor R12, i.e., the voltage at the node 121, into a final output voltage that equals to the sensing signal VCS-OFF at its output. The final output voltage generated by the first voltage follower 111 in one cycle Ts is set to the level of the voltage sensing signal VCS-OFF corresponding to the time t13. The output voltage generated from the output end of the first voltage follower 111 is transmitted to a first storage capacitor C2 of the sample-and-hold latch 202, and the switch SW1 is connected between one end of the first storage capacitor C2 at node 122 and the output end of the first voltage follower 111, while the other end of the first storage capacitor C2 is grounded. The output voltage equivalent to the voltage sensing signal VCS-OFF charges the first storage capacitor C2, thus the first storage capacitor C2 holds and stores the information of the off current value IOFF flowing through the primary winding 130A corresponding to time t13, and the stored information is considered as the voltage value VCS-OFF applied at node 122 at the ungrounded end of the first storage capacitor C2.
The same method using the detection module 201 to capture the blanking current value ILEB at time t12 and the off current value IOFF at time t13 and store in the sample-and-hold latch 202 in the CCM is also applied to capture the blanking current value ILEB at time t22 and the off current value IOFF at time t23 and stores in the sample-and-hold latch 202 in the DCM.
In the DCM, the detection module 201 detects the sensing signal VCS-LEB corresponding to the time t22 in FIG. 5C at the node 101 at one end of the sensing resistor RS. The leading edge blanking signal LEB is applied to the node 103 at the control terminal of the switch SW2, and the switch SW2 is turned on when the leading edge blanking signal LEB is at the logic high level. In a cycle, in the period TLEB from the time t21 when the main switch QM is turned on to the time t22 when the leading edge blanking signal LEB changes from the high level to the low level, the primary current IP accordingly increases from the leading edge initial value IPV of zero at time t21 to the blanking current value ILEB at time t22. Although the dynamic sensing signal is always sent to the voltage-current converter 110 in the time TLEB, and the leading edge blanking signal LEB changes from high level to low level to turn off the switch SW2 at time t22, after the time t22 and before the leading edge blanking signal LEB changes from low level to high level in the next cycle, the second voltage follower 112 cannot convert the voltage value at the node 121 into the current. Further, the sensing signal VCS-LEB corresponding to the time t22 representing the blanking current value ILEB is sent to the input end of the voltage-current converter 110 and is converted to the intermediate transient current IM flowing through the conversion resistor R12; thus, the intermediate transient current IM is further converted into the voltage crossing the conversion resistor R12, while the second voltage follower 112 further converts the voltage applied on the conversion resistor R12, i.e., the voltage applied at node 121, into a voltage that equals to the sensing signal VCS-LEB at its output. The final output voltage generated by the second voltage follower 112 in one cycle Ts is set to the level of the voltage sensing signal VCS-LEB corresponding to the time t22. The voltage generated from the second voltage follower 112 and equivalent to the sensing signal VCS-LEB is transmitted to the second storage capacitor C3 to charge the second storage capacitor C3, therefore the second storage capacitor C3 holds and stores the information of the off current value ILEB flowing through the primary winding 130A corresponding to the time t23, and the stored information is considered as the voltage value VCS-LEB applied at the node 123 at the ungrounded end of the second storage capacitor C3.
Still in the DCM, the detection module 201 also detects the sensing signal VCS-OFF corresponding to the time t23 in FIG. 5C at the node 101 at one end of the inductive resistor RS. The control signal is sent to the control terminal of the switch SW1, and the switch SW1 is turned on when the control signal is at the logic high level. In a period from time t21 when the main switch QM is turned on to time t23 when the control signal LEB changes from the high level to the low level, the primary current IP accordingly increases from the leading edge initial value IPV of zero at time t21 to the off current value IOFF at time t23. Although the dynamic sensing signal VCS is always fed to the voltage-current converter 110 from the time t21 to the time t23, when the control signal changes from the high level to the low level to turn off the switch SW1, after the time t23 and before the control signal changes from low level to the high level in the next cycle, the first voltage follower 111 is unable to convert the voltage value at node 121 to a current. Further, the sensing signal VCS-OFF corresponding to the time t23 representing the off current value IOFF is sent to the input end of the voltage-current converter 110 and is converted to the intermediate transient current IM flowing through the transfer resistor R12; thus, the intermediate transient current IM is further converted into the voltage crossing the conversion resistor R12, while the first voltage follower 111 further converts the voltage applied on the conversion resistor R12, i.e., the voltage applied at the node 121, into a voltage that equals to the sensing signal VCS-OFF at its output. The final output voltage generated by the first voltage follower 111 in one cycle Ts is set to the level of the voltage sensing signal VCS-OFF corresponding to the time t23. The final output voltage generated by the first voltage follower 111 and equivalent to the sensing signal VCS-OFF is transmitted to the first storage capacitor C2 to charge the first storage capacitor C2, therefore the first storage capacitor C2 holds and stores the information of the off current value IOFF flowing through the primary winding 130A corresponding to the time t23, and the stored information is considered as the voltage value VCS-OFF applied at the node 122 at the ungrounded end of the first storage capacitor C2.
Referring to FIG. 7, the calculation circuit 280 further includes a current summing unit 203 that includes two voltage-current converters 113 and 114, which are accordingly referred as the second voltage-current converter and the third voltage-current converter. A DC power voltage VDD is applied to a node 106 and a node 107 providing operating voltage for the voltage-current converter 113 and the voltage-current converter 114, and a summing resistor R14 with a resistance of RSUM is connected between the output end of the voltage-current converter 113 and the ground. The input end of the voltage-current converter 113 is connected to the node 122 at one end of the first storage capacitor C2 (shown in FIG. 13), and the information of off current value IOFF stored in the first storage capacitor C2 is transmitted to the voltage-current converter 113 in a form of the voltage value VCS-OFF, then the information of off current value IOFF is converted by the voltage-current converter 113 to a current that equals to the initial off current value IOFF. The output ends of the voltage-current converter 113 and the voltage-current converter 114 are connected together at a common node 124 at the ungrounded end of the summing resistor R14, and the other end of the summing resistor R14 is grounded. The input end of the voltage-current converter 114 is connected to the node 123 at one end of the second storage capacitor C3 (shown in FIG. 13), and the information of blanking current value ILEB stored in the second storage capacitor C3 is transmitted to the voltage-current converter 114 in a form of the voltage VCS-LEB, thus the information of blanking current value ILEB is converted by the voltage-current converter 114 to a current that equals to the initial blanking current value ILEB. As such, the total current flowing through the summing resistor R14 is equal to the sum of the off current value IOFF and the blanking current value ILEB, i.e., ILEB+IOFF. In addition, the current summing unit 203 further includes a third voltage follower 128 having the positive input end connected to the node 124 and the negative input end connected to its output end. The resistance RSUM of the summing resistor R14 is adjusted so that the output voltage VTRS of the third voltage follower 128 can be adjustable, VTRS=RSUM×(ILEB+IOFF), where the preset current ISUM equals a factor of the sum (ILEB+IOFF), in other words, the preset current ISUM can be set to be equal to K×(ILEB+IOFF). K is a positive constant, for example the preset current ISUM is equal to 0.5×(ILEB+IOFF). In addition, the voltage VTRS generated by the third voltage follower 128 is measurable, and the sum of the off current value IOFF and the blanking current value ILEB contained in the preset current ISUM can be equivalently converted from the voltage VTRS.
Referring to FIG. 8, in an overload detection circuit 350 for detecting the load condition, between the voltage source VDD and the ground, a first branch includes a current source 315 providing a current value ISUM, a switch SW21 and a first capacitor C11 all connected in series, where one end of the switch SW21 is connected with the current source 315 while the other end is connected to a node 311 at one end of the first capacitor C11, and the other end of the first capacitor C11 is grounded. The current value ISUM provided by the current source 315 is controlled by the output of FIG. 7 and the circuit configuration is well known in the art therefore will not be described here. In addition, between the voltage source VDD and the grounded end, a second branch includes a current source 316 providing a reference current value IREF, a switch SW22 and a second capacitor C12 all connected in series, where one end of the switch SW22 is connected with the current source 316 while the other end is connected to a node 316 at one end of the second capacitor C12, and the other end of the second capacitor C12 is grounded. The overload detection circuit 350 further comprises a comparator 328 having the positive input end connected to a common node 311 of the switch SW21 and the first capacitor C11 and the negative input end connected to a common node 312 of the switch SW22 and the second capacitor C12, and the comparator 328 is mainly used for comparing the voltage of the first capacitor C11 with that of the second capacitor C12.
As shown in FIG. 9, the first capacitor C11 in FIG. 8 is charged by the preset current ISUM provided by the current source 315, which can be either a single preset current ISUM or a multiple of the preset current ISUM, and the second capacitor C12 in FIG. 8 is charged by the reference current IREF provided by the current source 316, which can be either a single reference current IREF or a multiple of the reference current IREF. The overload output current also leads to the increase of the preset current ISUM, so the load condition can be evaluated at the output end of the comparator 328. The time for charging the first capacitor C11 and the second capacitor C12 in each cycle is relatively flexible, if the second capacitor C12 is continuously charged in the whole cycle, as shown in FIG. 9, for example, in the DCM, the voltage V312 (i.e., the voltage value at the node 312) of the second capacitor C12 and the voltage V311 (i.e., the voltage value at the node 311) are crossed during the off-period TOFF, when the capacitor is not charged completely, however the comparator 328 will display a comparison result. Furthermore, at the end of the cycle TS, when the second capacitor C12 is charged completely, the comparison of the voltage V312 and the voltage V311 is stopped thus the comparator 328 generates the final comparison result. In an optional embodiment, the first capacitor C11 and the second capacitor C12 will instantaneously discharge the stored energy (not shown) at the end of one cycle and before charging in the next cycle. For example, in the overload detection circuit 350, a three-terminal electronic switch SW31 is connected in parallel to the first capacitor C11 and a three-terminal electronic switches SW32 is connected in parallel with the second capacitor C12, where the control ends of the switch SW31 and the switch SW32 synchronously receive a period clock signal (CLKP) that drives the switch SW31 and the switch SW32 to turn on at the time before the beginning of each cycle Ts or at the end of each cycle, as such the first capacitor C11 and the second capacitor C12 can be synchronously discharged when the switch SW31 connected between the node 311 and the ground and the switch SW32 connected between the node 312 and the ground are turned on. In an option, in each cycle, these electronic switches can be trigged by the control signal driving the main switch QM to discharge the capacitors C11 and C12 to the ground.
Referring to FIG. 10 according to a preferred embodiment of the prevent invention, the second capacitor C12 is not charged in the whole cycle TS, and a driving signal CTL2 transmitted to the control terminal of the switch SW22 controlling the switch SW22 turning on in a half of a cycle Ts (i.e., Ts/2) and off in the other haft, therefore the second capacitor C12 is charged in the period from the beginning of each cycle Ts to the time TS/2, and is not charged in the period between the time TS/2 to the end of the cycle Ts. In order to calculate the product of the preset current ISUM multiplying with TOFF/TS, a control signal CTL1 transmitted to the control terminal of the switch SW21 to turn on in the off period TOFF of the cycle Ts and turn off at the other times, thus the first capacitor C11 is charged from the beginning of the off period TOFF and is completely charged at the end of the off period TOFF. In the DCM, the first capacitor C11 is not charged in the on period TON and the dwell time TD. Similarly, in the CCM, the first capacitor C11 is only charged in the off period TOFF and is not charged in the on period TON. The waveform of the voltage V311 at the node 311 and that of the voltage V312 at the node 312 are shown in FIG. 10. In this embodiment, the charging time of the second capacitor C12 is shortened to a half of a cycle Ts (i.e., Ts/2), in order to keep the same final charge amount as in the whole cycle, the second capacitor C12 must be charged by a current of 2×IREF, so that the charge amount in the half of cycle is equal (2×IREF)×(TS/2) that is equal to the charge amount of IREF×TS in the whole cycle. Thus, the comparison result of the voltage V311 and the voltage V312 from the comparator 328 is not limited to the end time of one cycle, for example, the comparison result may also be made before the end of the off period TOFF, without causing a misoperation.
For example in the DCM, the reference current IREF is kept constant and the actual preset current ISUM is gradually increased, at the end of the off period TOFF, when the first capacitor C11 has been charged for a period time of TOFF, the comparator 328 starts generating the first high level result taken as a critical condition in which the voltage V311 is exactly equal to the voltage V312, in other words, the charge amount of IREF×TS of the second capacitor C12 at the end of time TS/2 is equal to the charge amount of the first capacitor C11 at the end of the off time TOFF. This critical condition is also appropriate to the CCM, but only a difference from the DCM is that the dwell time is not needed to be considered. Under such condition, a rated current value ISUM1 of the preset current at the time is set to meet the following function relationship:




  
    
      
        
          
            
              T
              OFF
            
            ×
            
              I
              
                SUM
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          
            C
            11
          
        
        =
        
          
            
              
                T
                S
              
              2
            
            ×
            
              (
              
                2
                ×
                
                  I
                  REF
                
              
              )
            
          
          
            C
            12
          
        
      
    
    
      
        (
        13
        )
      
    
  
  
    
      
        
          I
          
            SUM
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              T
              S
            
            
              T
              OFF
            
          
          ×
          
            I
            REF
          
          ×
          
            
              C
              11
            
            
              C
              12
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




If the capacitances of the first capacitor C11 and the second capacitor C12 are the same, the rated current value ISUM1 equals to (IREF×TS)÷TOFF. The ISUM1 is a critical value, and when the actual preset current ISUM is greater than ISUM1, or the actual output current IO is greater than (N×IREF×C11)÷C12, for example, the load in the DCM of FIG. 11, before the end of each off period TOFF, i.e., before the falling edge of the driving signal CTL1, the comparator 328 will start outputting the high level until the end of the cycle when the voltage V311 is greater than the voltage V312. The output end of the comparator 328 is connected to the input end of one monostable multivibrator 329, as shown in FIG. 8, thus the rising edge of the comparison result will trigger the monostable multivibrator 329 to send a high level signal before the end of the off period TOFF of each cycle. The output end of the monostable multivibrator 329 is connected to a counter 330 used for receiving an OC (over current) signal sent by the monostable multivibrator 329 at its CLK end, if the counter 330 receive the OC signal of the high level in several consecutive cycles with the total time length exceeding one preset time, the counter 330 detects that the converter accesses into the overloading condition, and thus send an overload protection signal OLP to turn off the whole power device.
On the contrary, the voltage V311 will not exceed the voltage V312 when the actual preset current ISUM is less than the rated value ISUM, or the actual output current IO is less than (N×IREF×C11)÷C12, for example, the load is in the light load condition in the DCM as shown in FIG. 11. Under such situation, the comparator 328 will not generate the high level result, nor trigger the monostable multivibrator 329 to send the logic high level signal, thus the counter 330 will not send the overload protection signal OLP. Similarly, the rated current value ISUM1 is also set in the CCM, but the difference from the DCM is that the cycle TS of the DCM also contains the dwell time TD. As the actual preset current ISUM is greater than the ISUM1, or the output current IO is greater than (N×IREF×C11)÷C12, for example, the load is heavy as shown in FIG. 12, the off period TOFF is ended earlier, and the comparator 328 start generating the high level signal until the end of the cycle as the voltage V311 is greater than the voltage V312, thus the OC signal sent by the monostable multivibrator 329 is triggered to have high level before the off period TOFF of each cycle is ended. As mentioned above, the output end of the monostable multivibrator 329 is connected to the counter 330 used for receiving the over current signal OC at its CLK end, and if the counter 330 receives the high level signal OC in several consecutive cycles with the total time exceeding one preset time, the counter 330 send an overload protection signal OLP to turn off the whole power device. Conversely, in the CCM mode, the voltage V311 will not exceed the voltage V312 as the actual preset current ISUM is less than the rated value ISUM1, or the actual output current IO is less than (N×IREF×C11)÷C12, for example the load is in the light load condition in the in FIG. 12. Therefore, under such situation, the comparator 328 in each cycle will not generate the high level signal, nor trigger the monostable multivibrator 329 to send the logic high level signal, so the counter 330 will not send the overload protection signal OLP.
While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”

## Claims

1. A circuit for evaluating a load condition in a flyback converter comprises:
a detection module detecting a primary current flowing through a sensing resistor connecting in series with a primary winding, wherein the detection module captures an off current value IOFF flowing through the sensing resistor when a main switch driven by a control signal for controlling on or off of the primary winding is turned off, and a blanking current value ILEB flowing through the sensing resistor when an active state of a leading edge blanking signal for shielding an initial spike of the primary current ends;
a first current source providing a preset current ISUM related to a sum of the off current value IOFF and the blanking current value ILEB;
a second current source providing a reference current;
a first capacitor having a capacitance C11 charged by the first current source and a second capacitor having a capacitance C12 charged by the second current source; and
a comparator having a positive input end receiving a voltage of the first capacitor and a negative input end receiving a voltage of the second capacitor,
wherein a comparison result generated by the comparator provides the load condition when the preset current ISUM varies due to an output current transmitted to the load by the flyback converter varies.

2. The circuit for evaluating the load condition in the flyback converter of claim 1, wherein the preset current ISUM equals to a half of the sum of the off current value IOFF and the blanking current value ILEB.

3. The circuit for evaluating the load condition in the flyback converter of claim 1 further comprises a first switch connected between the first current source and the first capacitor, wherein the switch is turned on during an off period TOFF in each switching cycle Ts of the main switch, and is turned off in the remaining time of each said switching cycle.

4. The circuit for evaluating the load condition in the flyback converter of claim 3, wherein the flyback converter is in an overload condition when the preset current ISUM exceeds a rated current value ISUM1 that meets the following function relationship:




  
    I
    
      SUM
      ⁢
      
        
      
      ⁢
      1
    
  
  =
  
    
      
        T
        S
      
      
        T
        OFF
      
    
    ×
    
      I
      REF
    
    ×
    
      
        C
        11
      
      
        C
        12
      
    
  



where IREF is the reference current provided by the second current source.

5. The circuit for evaluating the load condition in the flyback converter of claim 4, wherein when the preset current ISUM exceeds the rated current value ISUM1, the comparison result of the comparator changes from a low level to a high level in the off period TOFF of the main switch in each cycle TS, or
when the preset current ISUM is lower than the rated current value ISUM1, the comparison result of the comparator in each cycle Ts remains at the low level.

6. The circuit for evaluating the load condition in the flyback converter of claim 5 further comprises a monostable multivibrator receiving the comparison result from the comparator and a counter connecting with the monostable multivibrator, wherein the monostable multivibrator is trigged to generate a high level signal sent to the counter when a rising edge of the comparison result changes from the low level to the high level, and the counter generates an overloading protection signal representing the load changing into a heavy load condition when the counter receives the high level signal generated by the monostable multivibrator in a plurality of continuous cycles.

7. The circuit for evaluating the load condition in the flyback converter of claim 3 further comprises a second switch connected between the second current source and the second capacitor, wherein the second switch is turned on at a moment the main switch starts to turn on in each cycle and is turned off at a half of each cycle; wherein
the second current source provides the reference current 2×IREF, such that the voltage of the second capacitor charged by the second current source at half of a cycle time TS equals:





  
    
      
        
          T
          S
        
        2
      
      ×
      
        (
        
          2
          ×
          
            I
            REF
          
        
        )
      
    
    
      C
      12
    
  
  =
  
    
      
        
          T
          S
        
        ×
        
          I
          REF
        
      
      
        C
        12
      
    
    .

8. The circuit for evaluating the load condition in the flyback converter of claim 7, wherein the capacitance C11 of the first capacitor equals to the capacitance C12 of the second capacitor.

9. The circuit for evaluating the load condition in the flyback converter of claim 1 further comprising a third switch connecting in parallel with the first capacitor and a fourth switch connecting in parallel with the second capacitor, wherein the third switch and the fourth switch are turned on at an end of each cycle to synchronously discharge the first capacitor and the second capacitor.

10. The circuit for evaluating the load condition in the flyback converter of claim 1 further comprises a sample-and-hold latch, wherein the detection module comprises a first voltage-current converter receiving a voltage sensing signal representing the primary current flowing through the sensing resistor and converting the voltage sensing signal representing the primary current into an intermediate current flowing through a conversion resistor connecting between an output end of the first voltage-current converter and ground;
the detection module converts an voltage applied on the conversion resistor into a voltage sensing signal corresponding to the off current value IOFF transmitting to the sample-and-hold latch for storage at a moment the main switch is turned off; and
the detection module converts the voltage applied on the conversion resistor into a voltage sensing signal corresponding to the blanking current value ILEB transmitting to the sample-and-hold latch for storage at a moment the active state of the leading edge blanking signal ends.

11. The circuit for evaluating the load condition in the flyback converter of claim 10, wherein the detection module comprises a first voltage follower having a positive input end connected with the output end of the first voltage-current converter; and
a fifth switch driven by the control signal is connected between an output end of the first voltage follower and one end of a first storage capacitor of the sample-and-hold latch, wherein the fifth switch is turned off synchronously at a moment the control signal changes from a first state to a second state to turn off the main switch, and the first voltage follower converts a voltage produced from the intermediate current flowing through the conversion resistor into the voltage sensing signal corresponding to the off current value IOFF, and stored in the first storage capacitor.

12. The circuit for evaluating the load condition in the flyback converter of claim 10, wherein the detection module comprises a second voltage follower having a positive input end connected with the output end of the first voltage-current converter; and
a sixth switch driven by a leading edge blanking signal is connected between an output end of the second voltage follower and one end of a second storage capacitor of the sample-and-hold latch, the sixth switch is turned off synchronously at a moment the leading edge blanking signal changes from a first state to a second state, wherein the second voltage follower converts a voltage produced from the intermediate current flowing through the conversion resistor into the voltage sensing signal corresponding to the blanking current value ILEB and stored in the second storage capacitor.

13. The circuit for evaluating the load condition in the flyback converter of claim 10 further comprises a current summing unit, wherein the current summing unit comprises:
a second voltage-current converter for restoring and converting the voltage sensing signal corresponding to the off current value IOFF stored in the sample-and-hold latch into a current equal to the off current value IOFF at an output end of the second voltage-current converter;
a third voltage-current converter for restoring and converting the voltage sensing signal corresponding to the blanking current value ILEB stored in the sample-and-hold latch into a current equal to the blanking current value ILEB at an output end of the third voltage-current converter;
the current generated by the second voltage-current converter and the current generated by third voltage-current converter are converged to a common node and are transmitted to a summing resistor between the common node and ground; and
a third voltage follower having a positive input end connected to the common node for generating a voltage VTRS equal to (ILEB+IOFF) multiplying with a resistance value RSUM of the summing resistor, wherein the preset current ISUM related to the sum of the off current value IOFF and the blanking current value ILEB is captured.

14. A circuit for evaluating a load condition in a flyback converter comprises:
a first current source providing a preset current ISUM related to a sum of an off current value IOFF and a blanking current value ILEB, wherein the off current value IOFF is a primary current flowing through a sensing resistor connecting in series with a primary winding when a main switch driven by a control signal for controlling on or off of the primary winding is turned off, and the blanking current value ILEB is the primary current flowing through the sensing resistor when an active state of a leading edge blanking signal for shielding an initial spike of the primary current ends;
a second current source providing a reference current;
a first capacitor having a capacitance C11 charged by the first current source and a second capacitor having a capacitance C12 charged by the second current source; and
a comparator having a positive input end receiving a voltage of the first capacitor and a negative input end receiving a voltage of the second capacitor,
wherein a comparison result generated by the comparator provides the load condition when the preset current ISUM varies due to an output current transmitted to the load by the flyback converter varies.

15. The circuit for evaluating the load condition in the flyback converter of claim 14, wherein the preset current ISUM equals to a half of the sum of the off current value IOFF and the blanking current value ILEB.

16. The circuit for evaluating the load condition in the flyback converter of claim 14 further comprises a first switch connected between the first current source and the first capacitor, wherein the switch is turned on during an off period TOFF in each switching cycle Ts of the main switch, and is turned off in the remaining time of each said switching cycle.

17. The circuit for evaluating the load condition in the flyback converter of claim 16, wherein the flyback converter is in an overload condition when the preset current ISUM exceeds a rated current value ISUM1 that meets the following function relationship:




  
    I
    
      SUM
      ⁢
      
        
      
      ⁢
      1
    
  
  =
  
    
      
        T
        S
      
      
        T
        OFF
      
    
    ×
    
      I
      REF
    
    ×
    
      
        C
        11
      
      
        C
        12
      
    
  



where IREF is the reference current provided by the second current source.

18. The circuit for evaluating the load condition in the flyback converter of claim 17, wherein when the preset current ISUM exceeds the rated current value ISUM1, the comparison result of the comparator changes from a low level to a high level in the off period TOFF of the main switch in each cycle TS, or
when the preset current ISUM is lower than the rated current value ISUM1, the comparison result of the comparator in each cycle Ts remains at the low level.

19. The circuit for evaluating the load condition in the flyback converter of claim 18 further comprises a monostable multivibrator receiving the comparison result from the comparator and a counter connecting with the monostable multivibrator, wherein the monostable multivibrator is trigged to generate a high level signal sent to the counter when a rising edge of the comparison result changes from the low level to the high level, and the counter generates an overloading protection signal representing the load changing into a heavy load condition when the counter receives the high level signal generated by the monostable multivibrator in a plurality of continuous cycles.

20. The circuit for evaluating the load condition in the flyback converter of claim 16 further comprises a second switch connected between the second current source and the second capacitor, wherein the second switch is turned on at a moment the main switch starts to turn on in each cycle and is turned off at a half of each cycle; wherein
the second current source provides the reference current 2×IREF, such that the voltage of the second capacitor charged by the second current source at half of a cycle time TS equals:





  
    
      
        
          T
          S
        
        2
      
      ×
      
        (
        
          2
          ×
          
            I
            REF
          
        
        )
      
    
    
      C
      12
    
  
  =
  
    
      
        
          T
          S
        
        ×
        
          I
          REF
        
      
      
        C
        12
      
    
    .

21. The circuit for evaluating the load condition in the flyback converter of claim 20, wherein the capacitance C11 of the first capacitor equals to the capacitance C12 of the second capacitor.

22. The circuit for evaluating the load condition in the flyback converter of claim 14 further comprising a third switch connecting in parallel with the first capacitor and a fourth switch connecting in parallel with the second capacitor, wherein the third switch and the fourth switch are turned on at an end of each cycle to synchronously discharge the first capacitor and the second capacitor.