# Patent

## Title
Transmitting apparatus and interleaving method thereof

## Abstract

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

## Background
BACKGROUND
1. Field
Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.
2. Description of the Related Art
In the 21st century information-oriented society, broadcasting communication services are moving into an era of digitalization, multi-channel, wideband, and high quality. In particular, as higher quality digital televisions, portable multimedia players (PMPs) and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.
In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with more robust encoding, decoding and receiving performance.
SUMMARY
One or more exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it is understood that one or more exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.
One or more exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined group from among a plurality of groups of a Low Density Parity Check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.
According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus which may include: an encoder configured to generate an LDPC codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.
Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of Nldpc and Kldpc and determined to satisfy Qldpc=(Nldpc−Kldpc)/M. Qldpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nldpc may be a length of the LDPC codeword, and Kldpc may be a length of information word bits of the LDPC codeword.
The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to perform group interleaving on the parity-interleaved LDPC codeward by dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bits group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.
The group interleaver may be configured to rearrange the order of the plurality of bit groups in bits group wise by using Equation 15.
In Equation 15, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 1024-QAM, and the code rate is 12/15, π(j) may be defined as in table 13.
The block interleaver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bits group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bits group wise in a row direction.
The block interleaver may be configured to serially write, in the plurality of columns, at least one bit group which is writable in the plurality of columns in bits group wise from among the plurality of bit groups, and divide and write bit groups other than the at least one bit group from among the plurality of bit groups in an area of the plurality of columns other than an area where the at least some bit group is written in the plurality of columns in bits group wise.
According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus which may include: generating an LDPC codeword by LDPC encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the mapping comprises mapping bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.
Each of the plurality of bit groups may be formed of 360 bits, and M may be a common divisor of Nldpc and Kldpc and may be determined to satisfy Qldpc=(Nldpc−Kldpc)/M. Qldpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nldpc may be a length of the LDPC codeword, and Kldpc may be a length of information word bits of the LDPC codeword.
The interleaving may include: interleaving parity bits of the LDPC codeword; group interleaving on the parity-interleaved LDPC codeward by dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bits group wise; and; and interleaving the plurality of bit groups the order of which is rearranged.
The rearranging in bits group wise may include rearranging the order of the plurality of bit groups in bits group wise by using Equation 15.
In Equation 15, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 1024-QAM, and the code rate is 12/15, π(j) may be defined as in table 13.
The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bits group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bits group wise in a row direction.
The interleaving the plurality of bit groups may include: serially writing, in the plurality of columns, at least one bit group which is writable in the plurality of columns in bits group wise from among the plurality of bit groups; and dividing and writing bit groups other than the at least one bit group from among the plurality of bit groups in an area of the plurality of columns other than an area where the at least some bit group is written in the plurality of columns in bits group wise.
According to various exemplary embodiments as described above, improved decoding and receiving performance can be provided.



BRIEF DESCRIPTION OF THE DRAWINGS
The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:
FIGS. 1A to 12 are views to illustrate a transmitting apparatus according to exemplary embodiments;
FIGS. 13 to 18 are views to illustrate a receiving apparatus according to exemplary embodiments;
FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment;
FIGS. 20 and 21 are views to illustrate a configuration of a parity check matrix according to various exemplary embodiments;
FIG. 22 is a block diagram to illustrate a configuration of an interleaver according to an exemplary embodiment;
FIGS. 23 to 25 are views to illustrate a method for processing an LDPC codeword on a group basis according to exemplary embodiments;
FIGS. 26 to 30 are views to illustrate a configuration of a block interleaver and an interleaving method according to exemplary embodiments;
FIG. 31 is a view to illustrate an operation of a demultiplexer according to an exemplary embodiment;
FIG. 32 is a block diagram to illustrate a configuration of an interleaver according to another exemplary embodiment;
FIGS. 33-35 are views to illustrate a configuration of a block-row interleaver and an interleaving method according to exemplary embodiments;
FIG. 36 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;
FIGS. 37 and 39 are block diagrams to illustrate a configuration of a deinterleaver according to exemplary embodiments;
FIG. 38 is a view to illustrate a deinterleaving method of a block deinterleaver according to an exemplary embodiment;
FIG. 40 is a flowchart to illustrate an interleaving method according to an exemplary embodiment;
FIG. 41 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment;
FIG. 42 is a block diagram illustrating a demodulator according to an exemplary embodiment; and
FIG. 43 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.



DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.
In the following description, the same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.
FIG. 1A is provided to explain transmitting apparatus according to an exemplary embodiment.
According to FIG. 1A, a transmitting apparatus 10000 according to an exemplary embodiment may include an Input Formatting Block(or part) 11000, 11000-1, a BIT Interleaved and Coded Modulation (BICM) block 12000, 12000-1, a Framing/Interleaving block 13000, 13000-1 and a Waveform Generation block 14000, 14000-1.
The transmitting apparatus 10000 according to an exemplary embodiment illustrated in FIG. 1A includes normative blocks shown by solid lines and informative blocks shown by dotted lines. Here, the blocks shown by solid lines are normal blocks, and the blocks shown by dotted lines are blocks which may be used when implementing an informative MIMO.
The Input Formatting block 11000, 11000-1 generates a baseband frame (BBFRAME) from an input stream of data to be serviced. Herein, the input stream may be a transport stream (TS), Internet protocol (IP) stream, a generic stream (GS), a generic stream encapsulation (GSE), etc.
The BICM block 12000, 12000-1 determines a forward error correction (FEC) coding rate and a constellation order depending on a region where the data to be serviced will be transmitted (e.g., a fixed PHY frame or mobile PHY frame), and then, performs encoding. Signaling information on the data to be serviced may be encoded through a separate BICM encoder (not illustrated) or encoded by sharing the BICM encoder 12000, 12000-1 with the data to be serviced, depending on a system implementation.
The Framing/Interleaving block 13000, 13000-1 combines time interleaved data with signaling information to generate a transmission frame.
The Waveform Generation block 14000, 14000-1 generates an OFDM signal in the time domain on the generated transmission frame, modulates the generated OFDM signal to a radio frequency (RF) signal and transmits the modulated RF signal to a receiver.
FIGS. 1B and 1C are provided to explain methods of multiplexing according to an exemplary embodiment.
FIG. 1B illustrates a block diagram to implement a Time Division Multiplexing according to an exemplary embodiment.
In the TDM system architecture, there are four main blocks (or parts): the Input Formatting block 11000, the BICM block 12000, the Framing/Interleaving block 13000, and the Waveform Generation block 14000.
Data is input and formatted in the Input Formatting block, and forward error correction applied and mapped to constellations in the BICM block 12000. Interleaving, both time and frequency, and frame creation done in the Framing/Interleaving block 13000. Subsequently, the output waveform is created in the Waveform Generation block 14000.
FIG. 2B illustrates a block diagram to implement a Layered Division Multiplexing (LDM) according to another exemplary embodiment.
In the LDM system architecture, there are several different blocks compared with the TDM system architecture. Specifically, there are two separate Input Formatting blocks 11000, 11000-1 and BICM blocks 12000, 12000-1, one for each of the layers in LDM. These are combined before the Framing/Interleaving block 13000 in the LDM Injection block. The Waveform Generation block 14000 is similar to TDM.
FIG. 2 is a block diagram which illustrates detailed configuration of the Input Formatting block illustrated in FIG. 1A.
As illustrated in FIG. 2, the Input Formatting block 11000 consists of three blocks which control packets distributed into PLPs. Specifically, the Input Formatting block 11000 includes a packet encapsulation and compression block 11100, a baseband framing block 11200 and a scheduler block 11300.
Input data packets input to the Input Formatting block 11000 can consist of various types, but at the encapsulation operation these different types of packets become generic packets which configure baseband frames. Here, the format of generic packets is variable. It is possible to easily extract the length of the generic packet from the packet itself without additional information. The maximum length of the generic packet is 64 kB. The maximum length of the generic packet, including header, is four bytes. Generic packets must be of integer byte length.
The scheduler 11200 receives an input stream of encapsulated generic packets and forms them into physical layer pipes (PLPs), in the form of baseband frames. In the above-mentioned TDM system there may be only one PLP, called single PLP or S-PLP, or there may be multiple PLPs, called M-PLP. One service cannot use more than four PLPs. In the case of an LDM system consisting of two layers, two PLPs are used, one for each layer.
The scheduler 11200 receives encapsulated input packet streams and directs how these packets are allocated to physical layer resources. Specifically, the scheduler 11200 directs how the baseband framing block will output baseband frames.
The functional assets of the Scheduler 11200 are defined by data size(s) and time(s). The physical layer can deliver portions of data at these discrete times. The scheduler 11200 uses the inputs and information including encapsulated data packets, quality of service metadata for the encapsulated data packets, a system buffer model, constraints and configuration from system management, and creates a conforming solution in terms of configuration of the physical layer parameters. The corresponding solution is subject to the configuration and control parameters and the aggregate spectrum available.
Meanwhile, the operation of the Scheduler 11200 is constrained by combination of dynamic, quasi-static, and static configurations. The definition of these constraints is left to implementation.
In addition, for each service a maximum of four PLPs shall be used. Multiple services consisting of multiple time interleaving blocks may be constructed, up to a total maximum of 64 PLPs for bandwidths of 6, 7 or 8 MHz. The baseband framing block 11300, as illustrated in FIG. 3A, consists of three blocks, baseband frame construction 3100, 3100-1, . . . 3100-n, baseband frame header construction block 3200, 3200-1, . . . 3200-n, and the baseband frame scrambling block 3300, 3300-1, . . . 3300-n. In a M-PLP operation, the baseband framing block creates multiple PLPs as necessary.
A baseband frame 3500, as illustrated in FIG. 3B, consists of a baseband frame header 3500-1 and payload 3500-2 consisting of generic packets. Baseband frames have fixed length Kpayload. Generic packets 3610-3650 shall be mapped to baseband frames 3500 in order. If generic packets 3610-3650 do not completely fit within a baseband frame, packets are split between the current baseband frame and the next baseband frame. Packet splits shall be in byte units only.
The baseband frame header construction block 3200, 3200-1, . . . 3200-n configures the baseband frame header. The baseband frame header 3500-1, as illustrated in FIG. 3B, is composed of three parts, including the base header 3710, the optional header (or option field 3720) and the extension field 3730. Here, the base header 3710 appears in every baseband frame, and the optional header 3720 and the extension field 3730 may not be present in every time.
The main feature of the base header 3710 is to provide a pointer including an offset value in bytes as an initiation of the next generic packet within the baseband frame. When the generic packet initiates the baseband frame, the pointer value becomes zero. If there is no generic packet which is initiated within the baseband frame, the pointer value is 8191, and a 2-byte base header may be used.
The extension field (or extension header) 3730 may be used later, for example, for the baseband frame packet counter, baseband frame time stamping, and additional signaling, etc.
The baseband frame scrambling block 3300, 3300-1, . . . 3300-n scrambles the baseband frame.
In order to ensure that the payload data when mapped to constellations does not always map to the same point, such as when the payload mapped to constellations consists of a repetitive sequence, the payload data shall always be scrambled before forward error correction encoding.
The scrambling sequences shall be generated by a 16-bit shift register that has 9 feedback taps. Eight of the shift register outputs are selected as a fixed randomizing byte, where each bit from t his byte is used to individually XOR the corresponding input data. The data bits are XORed MSB to MSB and so on until LSB to LSB. The generator polynomial is G(x)=1+X+X3+X6+X7+X11+X12+X13+X16.
FIG. 4 illustrates a shift register of a PRBS encoder for scrambling a baseband according to an exemplary embodiment, wherein loading of the sequence into the PRBS register, as illustrated in FIG. 4 and shall be initiated at the start of every baseband frame.
FIG. 5 is a block diagram provided to explain detailed configuration of the BICM block illustrated in FIG. 1A.
As illustrated in FIG. 5, the BICM block includes the FEC block 14100, 14100-1, . . . , 14100-n, Bit Interleaver block 14200, 14200-1, . . . , 14200-n and Mapper blocks 14300, 14300-1, . . . , 14300-n. 
The input to the FEC block 1400, 14100-1, . . . , 14100-n is a Baseband frame, of length Kpayload, and the output from the FEC block is a FEC frame. The FEC block 14100, 14100-1, . . . , 14100-n is implemented by concatenation of an outer code and an inner code with the information part. The FEC frame has length Ninner. There are two different lengths of LDPC code defined: Ninner=64800 bits and Ninner=16200 bits
The outer code is realized as one of either Bose, Ray-Chaudhuri and Hocquenghem (BCH) outer code, a Cyclic Redundancy Check (CRC) or other code. The inner code is realized as a Low Density Parity Check (LDPC) code. Both BCH and LDPC FEC codes are systematic codes where the information part I contained within the codeword. The resulting codeword is thus a concatenation of information or payload part, BCH or CRC parities and LDPC parities, as shown in FIG. 6A.
The use of LDPC code is mandatory and is used to provide the redundancy needed for the code detection. There are two different LDPC structures that are defined, these are called Type A and Type B. Type A has a code structure that shows better performance at low code rates while Type B code structure shows better performance at high code rates. In general Ninner=64800 bit codes are expected to be employed. However, for applications where latency is critical, or a simpler encoder/decoder structure is preferred, Ninner=16200 bit codes may also be used.
The outer code and CRC consist of adding Mouter bits to the input baseband frame. The outer BCH code is used to lower the inherent LDPC error floor by correcting a predefined number of bit errors. When using BCH codes the length of Mouter is 192 bits (Ninner=64800 bit codes) and 168 bits (for Ninner=16200 bit codes). When using CRC the length of Mouter is 32 bits. When neither BCH nor CRC are used the length of Mouter is zero. The outer code may be omitted if it is determined that the error correcting capability of the inner code is sufficient for the application. When there is no outer code the structure of the FEC frame is as shown in FIG. 6B.
FIG. 7 is a block diagram provided to explain detailed configuration of the Bit Interleaver block illustrated in FIG. 6.
The LDPC codeword of the LDPC encoder, i.e., a FEC Frame, shall be bit interleaved by a Bit Interleaver block 14200. The Bit Interleaver block 14200 includes a parity interleaver 14210, a group-wise interleaver 14220 and a block interleaver 14230. Here, the parity interleaver is not used for Type A and is only used for Type B codes.
The parity interleaver 14210 converts the staircase structure of the parity-part of the LDPC parity-check matrix into a quasi-cyclic structure similar to the information-part of the matrix.
Meanwhile, the parity interleaved LDPC coded bits are split into Ngroup=Ninner/360 bit groups, and the group-wise interleaver 14220 rearranges the bit groups.
The block interleaver 14230 block interleaves the group-wise interleaved LDPC codeword.
Specifically, the block interleaver 14230 divides a plurality of columns into part 1 and part 2 based on the number of columns of the block interleaver 14230 and the number of bits of the bit groups. In addition, the block interleaver 14230 writes the bits into each column configuring part 1 column wise, and subsequently writes the bits into each column configuring part 2 column wise, and then reads out row wise the bits written in each column.
In this case, the bits constituting the bit groups in the part 1 may be written into the same column, and the bits constituting the bit groups in the part 2 may be written into at least two columns.
Back to FIG. 5, the Mapper block 14300, 14300-1, . . . , 14300-n maps FEC encoded and bit interleaved bits to complex valued quadrature amplitude modulation (QAM) constellation points. For the highest robustness level, quaternary phase shift keying (QPSK) is used. For higher order constellations (16-QAM up to 4096-QAM), non-uniform constellations are defined and the constellations are customized for each code rate.
Each FEC frame shall be mapped to a FEC block by first de-multiplexing the input bits into parallel data cell words and then mapping these cell words into constellation values.
FIG. 8 is a block diagram provided to explain detailed configuration of a Framing/Interleaving block illustrated in FIG. 1A.
As illustrated in FIG. 8, the Framing/Interleaving block 14300 includes a time interleaving block 14310, a framing block 14320 and a frequency interleaving block 14330.
The input to the time interleaving block 14310 and the framing block 14320 may consist of M-PLPs however the output of the framing block 14320 is OFDM symbols, which are arranged in frames. The frequency interleaver included in the frequency interleaving block 14330 operates an OFDM symbols.
The time interleaver (TI) configuration included in the time interleaving block 14310 depends on the number of PLPs used. When there is only a single PLP or when LDM is used, a sheer convolutional interleaver is used, while for multiple PLP a hybrid interleaver consisting of a cell interleaver, a block interleaver and a convolutional interleaver is used. The input to the time interleaving block 14310 is a stream of cells output from the mapper block (FIG. 5, 14300, 14300-1, . . . , 14300-n), and the output of the time interleaving block 14310 is also a stream of time-interleaved cells.
FIG. 9A illustrates the time interleaving block for a single PLP (S-PLP), and it consists of a convolutional interleaver only.
FIG. 9B illustrates the time interleaving block for a plurality of PLPs (M-PLP), and it can be divided in several sub-blocks as illustrated.
The framing block 14320 maps the interleaved frames onto at least one transmitter frame. The framing block 14320, specifically, receives inputs (e.g. data cell) from at least one physical layer pipes and outputs symbols.
In addition, the framing block 14320 creates at least one special symbol known as preamble symbols. These symbols undergo the same processing in the waveform block mentioned later.
FIG. 10 is a view illustrating an example of a transmission frame according to an exemplary embodiment.
As illustrated in FIG. 10, the transmission frame consists of three parts, the bootstrap, preamble and data payload. Each of the three parts consists of at least one symbol.
Meanwhile, the purpose of the frequency interleaving block 14330 is to ensure that sustained interference in one part of the spectrum will not degrade the performance of a particular PLP disproportionately compared to other PLPs. The frequency interleaver 14330, operating on the all the data cells of one OFDM symbol, maps the data cells from the framining block 14320 onto the N data carriers.
FIG. 11 is a block diagram provided to explain detailed configuration of a Waveform Generation block illustrated in FIG. 1A.
As illustrated in FIG. 11, the Waveform Generation block 14000 includes a pilot inserting block 14100, a MISO block 14200, an IFFT block 14300, a PAPR block 14400, a GI inserting block 14500 and a bootstrap block 14600.
The pilot inserting block 14100 inserts a pilot to various cells within the OFDM frame.
Various cells within the OFDM frame are modulated with reference information whose transmitted value is known to the receiver.
Cells containing the reference information are transmitted at a boosted power level. The cells are called scattered, continual, edge, preamble or frame-closing pilot cells. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol.
The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, transmission mode identification and can also be used to follow the phase noise.
The pilots are modulated according to reference information, and the reference sequence is applied to all the pilots (e.g. scattered, continual edge, preamble and frame closing pilots) in every symbol including preamble and the frame-closing symbol of the frame.
The reference information, taken from the reference sequence, is transmitted in scattered pilot cells in every symbol except the preamble and the frame-closing symbol of the frame.
In addition to the scattered pilots described above, a number of continual pilots are inserted in every symbol of the frame except for Preamble and the frame-closing symbol. The number and location of continual pilots depends on both the FFT size and scattered pilot pattern in use.
The MISO block 14200 applies a MISO processing.
The Transmit Diversity Code Filter Set is a MISO pre-distortion technique that artificially decorrelates signals from multiple transmitters in a Single Frequency Network in order to minimize potential destructive interference. Linear frequency domain filters are used so that the compensation in the receiver can be implemented as part of the equalizer process. The filter design is based on creating all-pass filters with minimized cross-correlation over all filter pairs under the constraints of the number of transmitters Mε{2,3,4} and the time domain span of the filters Nε{64,256}. The longer time domain span filters will increase the decorrelation level, but the effective guard interval length will be decreased by the filter time domain span and this should be taken into consideration when choosing a filter set for a particular network topology.
The IFFT block 14300 specifies the OFDM structure to use for each transmission mode. The transmitted signal is organized in frames. Each frame has a duration of TF, and consists of LF OFDM symbols. N frames constitute one super-frame. Each symbol is constituted by a set of Ktotal carriers transmitted with a duration TS. Each symbol is composed of a useful part with duration TU and a guard interval with a duration Δ. The guard interval consists of a cyclic continuation of the useful part, TU, and is inserted before it.
The PAPR block 14400 applies the Peak to Average Power Reduction technique.
The GI inserting block 14500 inserts the guard interval into each frame.
The bootstrap block 14600 prefixes the bootstrap signal to the front of each frame.
FIG. 12 is a block diagram provided to explain a configuration of signaling information according to an exemplary embodiment.
The input processing block 11000 includes a scheduler 11200. The BICM block 15000 includes an L1 signaling generator 15100, an FEC encoder 15200-1 and 15200-2, a bit interleaver 15300-2, a demux 15400-2, constellation mappers 15500-1 and 15500-2. The L1 signaling generator 15100 may be included in the input processing block 11000, according to an exemplary embodiment.
An n number of service data are mapped to a PLP0 to a PLPn respectively. The scheduler 11200 determines a position, modulation and coding rate for each PLP in order to map a plurality of PLPs to a physical layer of T2. In other words, the scheduler 11200 generates L1 signaling information. The scheduler 11200 may output dynamic field information among L1 post signaling information of a current frame, using the raming/Interleavingblock 13000 (FIG. 1) which may be referred to as a frame builder. Further, the scheduler 11200 may transmit the L1 signaling information to the BICM block 15000. The L1 signaling information includes L1 pre signaling information and L1 post signaling information.
The L1 signaling generator 15100 may differentiate the L1 pre signaling information from the L1 post signaling information to output them. The FEC encoders 15200-1 and 15200-2 perform respective encoding operations which include shortening and puncturing for the L1 pre signaling information and the L1 post signaling information. The bit interleaver 15300-2 performs interleaving by bit for the encoded L1 post signaling information. The demux 15400-2 controls robustness of bits by modifying an order of bits constituting cells and outputs the cells which include bits. Two constellation mappers 15500-1 and 15500-2 map the L1 pre signaling information and the L1 post signaling information to constellations, respectively. The L1 pre signaling information and the L1 post signaling information processed through the above described processes are output to be included in each frame by the Framing/Interleaving block 13000 (FIG. 1).
FIG. 13 illustrates a structure of an receiving apparatus according to an embodiment of the present invention.
The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can correspond to the apparatus 10000 for transmitting broadcast signals, described with reference to FIG. 1. The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can include a synchronization & demodulation module 21000, a frame parsing module 22000, a demapping & decoding module 23000, an output processor 24000 and a signaling decoding module 25000. A description will be given of operation of each module of the apparatus 20000 for receiving broadcast signals.
The synchronization & demodulation module 21000 can receive input signals through m Rx antennas, perform signal detection and synchronization with respect to a system corresponding to the apparatus 20000 for receiving broadcast signals and carry out demodulation corresponding to a reverse procedure of the procedure performed by the apparatus 10000 for transmitting broadcast signals.
The frame parsing module 22000 can parse input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus 10000 for transmitting broadcast signals performs interleaving, the frame parsing module 22000 can carry out deinterleaving corresponding to a reverse procedure of interleaving. In this case, the positions of a signal and data that need to be extracted can be obtained by decoding data output from the signaling decoding module 25200 to restore scheduling information generated by the apparatus 10000 for transmitting broadcast signals.
The demapping & decoding module 23000 can convert the input signals into bit domain data and then deinterleave the same as necessary. The demapping & decoding module 23000 can perform demapping for mapping applied for transmission efficiency and correct an error generated on a transmission channel through decoding. In this case, the demapping & decoding module 23000 can obtain transmission parameters necessary for demapping and decoding by decoding the data output from the signaling decoding module 25000.
The output processor 24000 can perform reverse procedures of various compression/signal processing procedures which are applied by the apparatus 10000 for transmitting broadcast signals to improve transmission efficiency. In this case, the output processor 24000 can acquire necessary control information from data output from the signaling decoding module 25000. The output of the output processor 24000 corresponds to a signal input to the apparatus 10000 for transmitting broadcast signals and may be MPEG-TSs, IP streams (v4 or v6) and generic streams.
The signaling decoding module 25000 can obtain PLS information from the signal demodulated by the synchronization & demodulation module 21000. As described above, the frame parsing module 22000, demapping & decoding module 23000 and output processor 24000 can execute functions thereof using the data output from the signaling decoding module 25000.
FIG. 14 illustrates a synchronization & demodulation module according to an embodiment of the present invention.
As shown in FIG. 14, the synchronization & demodulation module 21000 according to an embodiment of the present invention corresponds to a synchronization & demodulation module of an apparatus 20000 for receiving broadcast signals using m Rx antennas and can include m processing blocks for demodulating signals respectively input through m paths. The m processing blocks can perform the same processing procedure. A description will be given of operation of the first processing block 21000 from among the m processing blocks.
The first processing block 21000 can include a tuner 21100, an ADC block 21200, a preamble detector 21300, a guard sequence detector 21400, a waveform transform block 21500, a time/frequency synchronization block 21600, a reference signal detector 21700, a channel equalizer 21800 and an inverse waveform transform block 21900.
The tuner 21100 can select a desired frequency band, compensate for the magnitude of a received signal and output the compensated signal to the ADC block 21200.
The ADC block 21200 can convert the signal output from the tuner 21100 into a digital signal.
The preamble detector 21300 can detect a preamble (or preamble signal or preamble symbol) in order to check whether or not the digital signal is a signal of the system corresponding to the apparatus 20000 for receiving broadcast signals. In this case, the preamble detector 21300 can decode basic transmission parameters received through the preamble.
The guard sequence detector 21400 can detect a guard sequence in the digital signal. The time/frequency synchronization block 21600 can perform time/frequency synchronization using the detected guard sequence and the channel equalizer 21800 can estimate a channel through a received/restored sequence using the detected guard sequence.
The waveform transform block 21500 can perform a reverse operation of inverse waveform transform when the apparatus 10000 for transmitting broadcast signals has performed inverse waveform transform. When the broadcast transmission/reception system according to one embodiment of the present invention is a multi-carrier system, the waveform transform block 21500 can perform FFT. Furthermore, when the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 may not be used if a received time domain signal is processed in the frequency domain or processed in the time domain.
The time/frequency synchronization block 21600 can receive output data of the preamble detector 21300, guard sequence detector 21400 and reference signal detector 21700 and perform time synchronization and carrier frequency synchronization including guard sequence detection and block window positioning on a detected signal. Here, the time/frequency synchronization block 21600 can feed back the output signal of the waveform transform block 21500 for frequency synchronization.
The reference signal detector 21700 can detect a received reference signal. Accordingly, the apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can perform synchronization or channel estimation.
The channel equalizer 21800 can estimate a transmission channel from each Tx antenna to each Rx antenna from the guard sequence or reference signal and perform channel equalization for received data using the estimated channel.
The inverse waveform transform block 21900 may restore the original received data domain when the waveform transform block 21500 performs waveform transform for efficient synchronization and channel estimation/equalization. If the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 can perform FFT in order to carry out synchronization/channel estimation/equalization in the frequency domain and the inverse waveform transform block 21900 can perform IFFT on the channel-equalized signal to restore transmitted data symbols. If the broadcast transmission/reception system according to an embodiment of the present invention is a multi-carrier system, the inverse waveform transform block 21900 may not be used.
The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.
FIG. 15 illustrates a frame parsing module according to an embodiment of the present invention.
As shown in FIG. 15, the frame parsing module 22000 according to an embodiment of the present invention can include at least one block interleaver 22100 and at least one cell demapper 22200.
The block interleaver 22100 can deinterleave data input through data paths of the m Rx antennas and processed by the synchronization & demodulation module 21000 on a signal block basis. In this case, if the apparatus 10000 for transmitting broadcast signals performs pair-wise interleaving, the block interleaver 22100 can process two consecutive pieces of data as a pair for each input path. Accordingly, the block interleaver 22100 can output two consecutive pieces of data even when deinterleaving has been performed. Furthermore, the block interleaver 22100 can perform a reverse operation of the interleaving operation performed by the apparatus 10000 for transmitting broadcast signals to output data in the original order.
The cell demapper 22200 can extract cells corresponding to common data, cells corresponding to data pipes and cells corresponding to PLS data from received signal frames. The cell demapper 22200 can merge data distributed and transmitted and output the same as a stream as necessary. When two consecutive pieces of cell input data are processed as a pair and mapped in the apparatus 10000 for transmitting broadcast signals, the cell demapper 22200 can perform pair-wise cell demapping for processing two consecutive input cells as one unit as a reverse procedure of the mapping operation of the apparatus 10000 for transmitting broadcast signals.
In addition, the cell demapper 22200 can extract PLS signaling data received through the current frame as PLS-pre & PLS-post data and output the PLS-pre & PLS-post data.
The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.
FIG. 16 illustrates a demapping & decoding module according to an embodiment of the present invention.
The demapping & decoding module 23000 shown in FIG. 16 can perform a reverse operation of the operation of the bit interleaved and coded & modulation module illustrated in FIG. 1.
The bit interleaved and coded & modulation module of the apparatus 10000 for transmitting broadcast signals according to an embodiment of the present invention can process input data pipes by independently applying SISO, MISO and MIMO thereto for respective paths, as described above. Accordingly, the demapping & decoding module 23000 illustrated in FIG. 16 can include blocks for processing data output from the frame parsing module according to SISO, MISO and MIMO in response to the apparatus 10000 for transmitting broadcast signals.
As shown in FIG. 16, the demapping & decoding module 23000 according to an embodiment of the present invention can include a first block 23100 for SISO, a second block 23200 for MISO, a third block 23300 for MIMO and a fourth block 23400 for processing the PLS-pre/PLS-post information. The demapping & decoding module 23000 shown in FIG. 16 is exemplary and may include only the first block 23100 and the fourth block 23400, only the second block 23200 and the fourth block 23400 or only the third block 23300 and the fourth block 23400 according to design. That is, the demapping & decoding module 23000 can include blocks for processing data pipes equally or differently according to design.
A description will be given of each block of the demapping & decoding module 23000.
The first block 23100 processes an input data pipe according to SISO and can include a time deinterleaver block 23110, a cell deinterleaver block 23120, a constellation demapper block 23130, a cell-to-bit mux block 23140, a bit deinterleaver block 23150 and an FEC decoder block 23160.
The time deinterleaver block 23110 can perform a reverse process of the process performed by the time interleaving block 14310 illustrated in FIG. 8. That is, the time deinterleaver block 23110 can deinterleave input symbols interleaved in the time domain into original positions thereof.
The cell deinterleaver block 23120 can perform a reverse process of the process performed by the cell interleaver block illustrated in FIG. 9a. That is, the cell deinterleaver block 23120 can deinterleave positions of cells spread in one FEC block into original positions thereof. The cell deinterleaver block 23120 may be omitted.
The constellation demapper block 23130 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5. That is, the constellation demapper block 23130 can demap a symbol domain input signal to bit domain data. In addition, the constellation demapper block 23130 may perform hard decision and output decided bit data. Furthermore, the constellation demapper block 23130 may output a log-likelihood ratio (LLR) of each bit, which corresponds to a soft decision value or probability value. If the apparatus 10000 for transmitting broadcast signals applies a rotated constellation in order to obtain additional diversity gain, the constellation demapper block 23130 can perform 2-dimensional LLR demapping corresponding to the rotated constellation. Here, the constellation demapper block 23130 can calculate the LLR such that a delay applied by the apparatus 10000 for transmitting broadcast signals to the I or Q component can be compensated.
The cell-to-bit mux block 23140 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5. That is, the cell-to-bit mux block 23140 can restore bit data mapped to the original bit streams.
The bit deinterleaver block 23150 can perform a reverse process of the process performed by the bit interleaver 12200 illustrated in FIG. 5. That is, the bit deinterleaver block 23150 can deinterleave the bit streams output from the cell-to-bit mux block 23140 in the original order.
The FEC decoder block 23460 can perform a reverse process of the process performed by the FEC encoder 12100 illustrated in FIG. 5. That is, the FEC decoder block 23460 can correct an error generated on a transmission channel by performing LDPC decoding and BCH decoding.
The second block 23200 processes an input data pipe according to MISO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the first block 23100, as shown in FIG. 16. However, the second block 23200 is distinguished from the first block 23100 in that the second block 23200 further includes a MISO decoding block 23210. The second block 23200 performs the same procedure including time deinterleaving operation to outputting operation as the first block 23100 and thus description of the corresponding blocks is omitted.
The MISO decoding block 11110 can perform a reverse operation of the operation of the MISO processing in the apparatus 10000 for transmitting broadcast signals. If the broadcast transmission/reception system according to an embodiment of the present invention uses STBC, the MISO decoding block 11110 can perform Alamouti decoding.
The third block 23300 processes an input data pipe according to MIMO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the second block 23200, as shown in FIG. 16. However, the third block 23300 is distinguished from the second block 23200 in that the third block 23300 further includes a MIMO decoding block 23310. The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the third block 23300 are identical to those of the corresponding blocks included in the first and second blocks 23100 and 23200 although functions thereof may be different from the first and second blocks 23100 and 23200.
The MIMO decoding block 23310 can receive output data of the cell deinterleaver for input signals of the m Rx antennas and perform MIMO decoding as a reverse operation of the operation of the MIMO processing in the apparatus 10000 for transmitting broadcast signals. The MIMO decoding block 23310 can perform maximum likelihood decoding to obtain optimal decoding performance or carry out sphere decoding with reduced complexity. Otherwise, the MIMO decoding block 23310 can achieve improved decoding performance by performing MMSE detection or carrying out iterative decoding with MMSE detection.
The fourth block 23400 processes the PLS-pre/PLS-post information and can perform SISO or MISO decoding.
The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the fourth block 23400 are identical to those of the corresponding blocks of the first, second and third blocks 23100, 23200 and 23300 although functions thereof may be different from the first, second and third blocks 23100, 23200 and 23300.
The shortened/punctured FEC decoder 23410 can perform de-shortening and de-puncturing on data shortened/punctured according to PLS data length and then carry out FEC decoding thereon. In this case, the FEC decoder used for data pipes can also be used for PLS. Accordingly, additional FEC decoder hardware for the PLS only is not needed and thus system design is simplified and efficient coding is achieved.
The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.
The demapping & decoding module according to an embodiment of the present invention can output data pipes and PLS information processed for the respective paths to the output processor, as illustrated in FIG. 16.
FIGS. 17 and 18 illustrate output processors according to embodiments of the present invention.
FIG. 17 illustrates an output processor 24000 according to an embodiment of the present invention. The output processor 24000 illustrated in FIG. 17 receives a single data pipe output from the demapping & decoding module and outputs a single output stream.
The output processor 24000 shown in FIG. 17 can include a BB scrambler block 24100, a padding removal block 24200, a CRC-8 decoder block 24300 and a BB frame processor block 24400.
The BB scrambler block 24100 can descramble an input bit stream by generating the same PRBS as that used in the apparatus for transmitting broadcast signals for the input bit stream and carrying out an XOR operation on the PRBS and the bit stream.
The padding removal block 24200 can remove padding bits inserted by the apparatus for transmitting broadcast signals as necessary.
The CRC-8 decoder block 24300 can check a block error by performing CRC decoding on the bit stream received from the padding removal block 24200.
The BB frame processor block 24400 can decode information transmitted through a BB frame header and restore MPEG-TSs, IP streams (v4 or v6) or generic streams using the decoded information.
The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.
FIG. 18 illustrates an output processor according to another embodiment of the present invention. The output processor 24000 shown in FIG. 18 receives multiple data pipes output from the demapping & decoding module. Decoding multiple data pipes can include a process of merging common data commonly applicable to a plurality of data pipes and data pipes related thereto and decoding the same or a process of simultaneously decoding a plurality of services or service components (including a scalable video service) by the apparatus for receiving broadcast signals.
The output processor 24000 shown in FIG. 18 can include a BB descrambler block, a padding removal block, a CRC-8 decoder block and a BB frame processor block as the output processor illustrated in FIG. 17. The basic roles of these blocks correspond to those of the blocks described with reference to FIG. 17 although operations thereof may differ from those of the blocks illustrated in FIG. 17.
A de-jitter buffer block 24500 included in the output processor shown in FIG. 18 can compensate for a delay, inserted by the apparatus for transmitting broadcast signals for synchronization of multiple data pipes, according to a restored TTO (time to output) parameter.
A null packet insertion block 24600 can restore a null packet removed from a stream with reference to a restored DNP (deleted null packet) and output common data.
A TS clock regeneration block 24700 can restore time synchronization of output packets based on ISCR (input stream time reference) information.
A TS recombining block 24800 can recombine the common data and data pipes related thereto, output from the null packet insertion block 24600, to restore the original MPEG-TSs, IP streams (v4 or v6) or generic streams. The TTO, DNT and ISCR information can be obtained through the BB frame header.
An in-band signaling decoding block 24900 can decode and output in-band physical layer signaling information transmitted through a padding bit field in each FEC frame of a data pipe.
The output processor shown in FIG. 18 can BB-descramble the PLS-pre information and PLS-post information respectively input through a PLS-pre path and a PLS-post path and decode the descrambled data to restore the original PLS data. The restored PLS data is delivered to a system controller included in the apparatus for receiving broadcast signals. The system controller can provide parameters necessary for the synchronization & demodulation module, frame parsing module, demapping & decoding module and output processor module of the apparatus for receiving broadcast signals.
The above-described blocks may be omitted or replaced by blocks having similar r identical functions according to design.
FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 19, the transmitting apparatus 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or a constellation mapper).
The encoder 110 generates a Low Density Parity Check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. The encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.
Specifically, the encoder 110 LDPC-encodes information word (or information) bits to generate the LDPC codeword which is formed of the information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used as the information word bits. Also, since the LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.
The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of Nldpc number of bits, and includes Kldpc number of information word bits and Nparity=Nldpc−Kldpc number of parity bits.
In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·CT=0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.
For the LDPC encoding, the transmitting apparatus 100 may include a separate memory and may pre-store parity check matrices of various formats.
For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.
Hereinafter, a parity check matrix according to various exemplary embodiments will be explained in detail with reference to the drawings. In the parity check matrix, elements other than elements with 1 have 0.
For example, the parity check matrix according to an exemplary embodiment may have the configuration of FIGS. 20 and 21.
Referring to FIG. 10, the parity check matrix 200 is formed of an information word submatrix (or information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits. In the parity check matrix 200, elements other than elements with 1 have 0.
The information word submatrix 210 includes Kldpc number of columns and the parity submatrix 220 includes Nparity=Nldpc−Kldpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220, Nparity=Nldpc−Kldpc.
In addition, in the parity check matrix 200, Nldpc is a length of an LDPC codeword, Kldpc is a length of information word bits, and Nparity=Nldpc−Kldpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.
Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.
The information word submatrix 210 includes Kldpc number of columns (that is, 0th column to (Kldpc−1)th column), and follows the following rules:
First, M number of columns from among Kldpc number of columns of the information word submatrix 210 belong to a same group, and Kldpc number of columns is divided into Kldpc/M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Qldpc or Qldpc number of bits. That is, Qldpc may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200.
Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Qldpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210. Also, M is a common divisor of Nldpc and Kldpc and is determined to satisfy Qldpc=(Nldpc−Kldpc)/M. Here, M and Qldpc are integers and Kldpc/M is also an integer. M and Qldpc may have various values according to the length of the LDPC codeword and a code rate (CR) or a coding rate.
For example, when M=360 and the length of the LDPC codeword, Nldpc, is 64800, Qldpc may be defined as in Table 1 presented below, and, when M=360 and the length Nldpc of the LDPC codeword is 16200, Qldpc may be defined as in Table 2 presented below.












TABLE 1







Code Rate
Nldpc
M
Qldpc









5/15
64800
360
120



6/15
64800
360
108



7/15
64800
360
 96



8/15
64800
360
 84



9/15
64800
360
 72



10/15 
64800
360
 60



11/15 
64800
360
 48



12/15 
64800
360
 36



13/15 
64800
360
 24






















TABLE 2







Code Rate
Nldpc
M
Qldpc









5/15
16200
360
30



6/15
16200
360
27



7/15
16200
360
24



8/15
16200
360
21



9/15
16200
360
18



10/15 
16200
360
15



11/15 
16200
360
12



12/15 
16200
360
 9



13/15 
16200
360
 6










Second, when the degree of the 0th column of the ith column group (i=0, 1, . . . , Kldpc/M−1) is Di (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0th column of the ith column group is Ri,0(0), Ri,0(1), . . . , Ri,0D−1), an index Ri,j(k) of a row where kth 1 is located in the jth column in the ith column group is determined by following Equation 1:

Ri,j(k)=Ri,(j−1)(k)+Qldpc mod(Nldpc−Kldpc)  (1),

where k=0, 1, 2, . . . Di−1; i=0, 1, . . . , Kldpc/M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

Ri,j(k)={Ri,0(k)+(j mod M)×Qldpc} mod(Nldpc−Kldpc)  (2),

where k=0, 1, 2, . . . Di−1; i=0, 1, . . . , Kldpc/M−1; and j=1, 2, . . . , M−1. Since j=1, 2, . . . , M−1, (j mod M) of Equation 2 may be regarded as j.

In the above equations, Ri,j(k) is an index of a row where kth 1 is located in the jth column in the ith column group, Nldpc is a length of an LDPC codeword, Kldpc is a length of information word bits, Di is a degree of columns belonging to the ith column group, M is the number of columns belonging to a single column group, and Qldpc is a size by which each column in the column group is cyclic-shifted.
As a result, referring to these equations, when only Ri,0(k) is known, the index Ri,j(k) of the row where the kth 1 is located in the jth column in the ith column group can be known. Therefore, when the index value of the row where the kth 1 is located in the 0th column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 20 (that is, in the information word submatrix 210 of the parity check matrix 200) can be known.
According to the above-described rules, all of the columns belonging to the ith column group have the same degree Di. Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.
For example, when Nldpc is 30, Kldpc is 15, and Qldpc is 3, position information of the row where 1 is located in the 0th column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight−1 position sequence”.

R1,0(1)=1,R1,0(2)=2,R1,0(3)=8,R1,0(4)=10,

R2,0(1)=0,R2,0(2)=9,R2,0(3)=13,

R3,0(1)=0,R3,0(2)=14.  (3),

where Ri,j(k) is an index of a row where kth 1 is located in the jth column in the ith column group.

The weight−1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0th column of each column group may be briefly expressed as in Table 3 presented below:











TABLE 3










1 2 8 10





0 9 13





0 14










Table 3 shows positions of elements having value 1 in the parity check matrix, and the ith weight−1 position sequence is expressed by indexes of rows where 1 is located in the 0th column belonging to the ith column group.
The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 8 presented below, based on the above descriptions.
Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the 0th column of the ith column group of the information word submatrix 210. That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0th column of each of the plurality of column groups may be defined by Tables 4 to 8.
Herein, the indexes of the rows where 1 is located in the 0th column of the ith column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.
For example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0th column of the ith column group of the information word submatrix 210 are as shown in Table 4 presented below:








TABLE 4






Index of row where 1 is 


i
located in the 0th column of the ith column group
















0
1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764



14123 21576 23946 24533 25376 25667 26836 31799 34173 35462



36153 36740 37085 37152 37468 37658


1
4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512



21319 23663 25628 27208 31333 32219 33003 33239 33447 36200



36473 36938 37201 37283 37495 38642


2
16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067



11017 11366 13136 13354 15379 18934 20199 24522 26172 28666



30386 32714 36390 37015 37162


3
700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561



18745 21625 22137 23693 24340 24966 25015 26995 28586



28895 29687 33938 34520 34858 37056 38297


4
159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836



14954 15594 16623 18065 19249 22394 22677 23408 23731 24076



24776 27007 28222 30343 38371


5
3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536



20218 21921 28599 29445 29758 29968 31014 32027 33685



34378 35867 36323 36728 36870 38335 38623


6
1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164



15665 18444 19470 20313 21189 24371 26431 26999 28086 28251



29261 31981 34015 35850 36129 37186


7
111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919



14127 15515 15711 17061 19024 21195 22902 23727 24401



24608 25111 25228 27338 35398 37794 38196


8
961 3035 7174 7948 13355 13607 14971 18189 18339 18665



18875 19142 20615 21136 21309 21758 23366 24745 25849



25982 27583 30006 31118 32106 36469 36583 37920


9
2990 3549 4273 4808 5707 6021 6509 7456 8240 10044



12262 12660 13085 14750 15680 16049 21587 23997 25803



28343 28693 34393 34860 35490 36021 37737 38296


10
955 4323 5145 6885 8123 9730 11840 12216 19194 20313



23056 24248 24830 25268 26617 26801 28557 29753 30745



31450 31973 32839 33025 33296 35710 37366 37509


11
264 605 4181 4483 5156 7238 8863 10939 11251 12964



16254 17511 20017 22395 22818 23261 23422 24064 26329



27723 28186 30434 31956 33971 34372 36764 38123


12
520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783



11933 16336 17193 17320 19035 20606 23579 23769 24123



24966 27866 32457 34011 34499 36620 37526


13
10106 10637 10906 34242


14
1856 15100 19378 21848


15
943 11191 27806 29411


16
4575 6359 13629 19383


17
4476 4953 18782 24313


18
5441 6381 21840 35943


19
9638 9763 12546 30120


20
9587 10626 11047 25700


21
4088 15298 28768 35047


22
2332 6363 8782 28863


23
4625 4933 28298 30289


24
3541 4918 18257 31746


25
1221 25233 26757 34892


26
8150 16677 27934 30021


27
8500 25016 33043 38070


28
7374 10207 16189 35811


29
611 18480 20064 38261


30
25416 27352 36089 38469


31
1667 17614 25839 32776


32
4118 12481 21912 37945


33
5573 13222 23619 31271


34
18271 26251 27182 30587


35
14690 26430 26799 34355


36
13688 16040 20716 34558


37
2740 14957 23436 32540


38
3491 14365 14681 36858


39
4796 6238 25203 27854


40
1731 12816 17344 26025


41
19182 21662 23742 27872


42
6502 13641 17509 34713


43
12246 12372 16746 27452


44
1589 21528 30621 34003


45
12328 20515 30651 31432


46
3415 22656 23427 36395


47
632 5209 25958 31085


48
619 3690 19648 37778


49
9528 13581 26965 36447


50
2147 26249 26968 28776


51
15698 18209 30683


52
1132 19888 34111


53
4608 25513 38874


54
475 1729 34100


55
7348 32277 38587


56
182 16473 33082


57
3865 9678 21265


58
4447 20151 27618


59
6335 14371 38711


60
704 9695 28858


61
4856 9757 30546


62
1993 19361 30732


63
756 28000 29138


64
3821 24076 31813


65
4611 12326 32291


66
7628 21515 34995


67
1246 13294 30068


68
6466 33233 35865


69
14484 23274 38150


70
21269 36411 37450


71
23129 26195 37653









In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0th column of the ith column group of the information word submatrix 210 are as shown in Table 5 presented below:








TABLE 5






Index of row where 1 is 


i
located in the 0th column of the ith column group
















0
2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521



12083 16610 18361 20321 24601 27420 28206 29788


1
2739 8244 8891 9157 12624 12973 15534 16622 16919 18402



18780 19854 20220 20543 22306 25540 27478 27678 28053


2
1727 2268 6246 7815 9010 9556 10134 10472 11389 14599



15719 16204 17342 17666 18850 22058 25579 25860 29207


3
28 1346 3721 5565 7019 9240 12355 13109 14800 16040



16839 17369 17631 19357 19473 19891 20381 23911 29683


4
869 2450 4386 5316 6160 7107 10362 11132 11271 13149



16397 16532 17113 19894 22043 22784 27383 28615 28804


5
508 4292 5831 8559 10044 10412 11283 14810 15888 17243



17538 19903 20528 22090 22652 27235 27384 28208 28485


6
389 2248 5840 6043 7000 9054 11075 11760 12217 12565



13587 15403 19422 19528 21493 25142 27777 28566 28702


7
1015 2002 5764 6777 9346 9629 11039 11153 12690 13068



13990 16841 17702 20021 24106 26300 29332 30081 30196


8
1480 3084 3467 4401 4798 5187 7851 11368 12323 14325



14546 16360 17158 18010 21333 25612 26556 26906 27005


9
6925 8876 12392 14529 15253 15437 19226 19950 20321



23021 23651 24393 24653 26668 27205 28269 28529 29041



29292


10
2547 3404 3538 4666 5126 5468 7695 8799 14732 15072



15881 17410 18971 19609 19717 22150 24941 27908 29018


11
888 1581 2311 5511 7218 9107 10454 12252 13662 15714



15894 17025 18671 24304 25316 25556 28489 28977 29212


12
1047 1494 1718 4645 5030 6811 7868 8146 10611 15767



17682 18391 22614 23021 23763 25478 26491 29088



29757


13
59 1781 1900 3814 4121 8044 8906 9175 11156 14841



15789 16033 16755 17292 18550 19310 22505 29567



29850


14
1952 3057 4399 9476 10171 10769 11335 11569 15002



19501 20621 22642 23452 24360 25109 25290 25828



28505 29122


15
2895 3070 3437 4764 4905 6670 9244 11845 13352



13573 13975 14600 15871 17996 19672 20079



20579 25327 27958


16
612 1528 2004 4244 4599 4926 5843 7684 10122 10443



12267 14368 18413 19058 22985 24257 26202 26596



27899


17
1361 2195 4146 6708 7158 7538 9138 9998 14862



15359 16076 18925 21401 21573 22503 24146 24247



27778 29312


18
5229 6235 7134 7655 9139 13527 15408 16058 16705



18320 19909 20901 22238 22437 23654 25131 27550



28247 29903


19
697 2035 4887 5275 6909 9166 11805 15338 16381



18403 20425 20688 21547 24590 25171 26726 28848



29224 29412


20
5379 17329 22659 23062


21
11814 14759 22329 22936


22
2423 2811 10296 12727


23
8460 15260 16769 17290


24
14191 14608 29536 30187


25
7103 10069 20111 22850


26
4285 15413 26448 29069


27
548 2137 9189 10928


28
4581 7077 23382 23949


29
3942 17248 19486 27922


30
8668 10230 16922 26678


31
6158 9980 13788 28198


32
12422 16076 24206 29887


33
8778 10649 18747 22111


34
21029 22677 27150 28980


35
7918 15423 27672 27803


36
5927 18086 23525


37
3397 15058 30224


38
24016 25880 26268


39
1096 4775 7912


40
3259 17301 20802


41
129 8396 15132


42
17825 28119 28676


43
2343 8382 28840


44
3907 18374 20939


45
1132 1290 8786


46
1481 4710 28846


47
2185 3705 26834


48
5496 15681 21854


49
12697 13407 22178


50
12788 21227 22894


51
629 2854 6232


52
2289 18227 27458


53
7593 21935 23001


54
3836 7081 12282


55
7925 18440 23135


56
497 6342 9717


57
11199 22046 30067


58
12572 28045 28990


59
1240 2023 10933


60
19566 20629 25186


61
6442 13303 28813


62
4765 10572 16180


63
552 19301 24286


64
6782 18480 21383


65
11267 12288 15758


66
771 5652 15531


67
16131 20047 25649


68
13227 23035 24450


69
4839 13467 27488


70
2852 4677 22993


71
2504 28116 29524


72
12518 17374 24267


73
1222 11859 27922


74
9660 17286 18261


75
232 11296 29978


76
9750 11165 16295


77
4894 9505 23622


78
10861 11980 14110


79
2128 15883 22836


80
6274 17243 21989


81
10866 13202 22517


82
11159 16111 21608


83
3719 18787 22100


84
1756 2020 23901


85
20913 29473 30103


86
2729 15091 26976


87
4410 8217 12963


88
5395 24564 28235


89
3859 17909 23051


90
5733 26005 29797


91
1935 3492 29773


92
11903 21380 29914


93
6091 10469 29997


94
2895 8930 15594


95
1827 10028 20070









In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the ith column group of the information word submatrix 210 are defined as shown in Table 6 or 7 below.








TABLE 6






Index of row where 1 is 


i
located in the 0th column of the ith column group
















0
979 1423 4166 4609 6341 8258 10334 10548 14098 14514 



17051 17333 17653 17830 17990


1
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721



18600 18791 19079 19697 19840


2
3243 6894 7950 10539 12042 13233 13938 14752 16449 



16727 17025 18297 18796 19400 21577


3
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580



16651 17007 17309 19415 19845


4
155 4598 10201 10975 11086 11296 12713 15364 15978



16395 17542 18164 18451 18612 20617


5
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450



15438 16223 16370 17308 18634


6
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003



14304 14937 15767 18402 21502


7
199 3066 6446 6849 8973 9536 10452 12857 13675 15913



16717 17654 19802 20115 21579


8
312 870 2095 2586 5517 6196 6757 7311 7368 13046



15384 18576 20349 21424 21587


9
985 1591 3248 3509 3706 3847 6174 6276 7864 9033



13618 15675 16446 18355 18843


10
975 3774 4083 5825 6166 7218 7633 9657 10103 13052



14240 17320 18126 19544 20208


11
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752



11512 15171 17523 20481 21059


12
167 315 1824 2325 2640 2868 6070 6597 7016 8109



9815 11608 16142 17912 19625


13
1298 1896 3039 4303 4690 8787 12241 13600 14478



15492 16602 17115 17913 19466 20597


14
568 3695 6045 6624 8131 8404 8590 9059 9246 11570



14336 18657 18941 19218 21506


15
228 1889 1967 2299 3011 5074 7044 7596 7689 9534



10244 10697 11691 17902 21410


16
1330 1579 1739 2234 3701 3865 5713 6677 7263



11172 12143 12765 17121 20011 21436


17
303 1668 2501 4925 5778 5985 9635 10140 10820



11779 11849 12058 15650 20426 20527


18
698 2484 3071 3219 4054 4125 5663 5939 6928



7086 8054 12173 16280 17945 19302


19
232 1619 3040 4901 7438 8135 9117 9233 10131



13321 17347 17436 18193 18586 19929


20
12 3721 6254 6609 7880 8139 10437 12262 13928



14065 14149 15032 15694 16264 18883


21
482 915 1548 1637 6687 9338 10163 11768 11970



15524 15695 17386 18787 19210 19340


22
1291 2500 4109 4511 5099 5194 10014 13165



13256 13972 15409 16113 16214 18584 20998


23
1761 4778 7444 7740 8129 8341 8931 9136 9207



10003 10678 13959 17673 18194 20990


24
3060 3522 5361 5692 6833 8342 8792 11023 11211



11548 11914 13987 15442 15541 19707


25
1322 2348 2970 5632 6349 7577 8782 9113 9267



9376 12042 12943 16680 16970 21321


26
6785 11960 21455


27
1223 15672 19550


28
5976 11335 20385


29
2818 9387 15317


30
2763 3554 18102


31
5230 11489 18997


32
5809 15779 20674


33
2620 17838 18533


34
3025 9342 9931


35
3728 5337 12142


36
2520 6666 9164


37
12892 15307 20912


38
10736 12393 16539


39
1075 2407 12853


40
4921 5411 18206


41
5955 15647 16838


42
6384 10336 19266


43
429 10421 17266


44
4880 10431 12208


45
2910 11895 12442


46
7366 18362 18772


47
4341 7903 14994


48
4564 6714 7378


49
4639 8652 18871


50
15787 18048 20246


51
3241 11079 13640


52
1559 2936 15881


53
2737 6349 10881


54
10394 16107 17073


55
8207 9043 12874


56
7805 16058 17905


57
11189 15767 17764


58
5823 12923 14316


59
11080 20390 20924


60
568 8263 17411


61
1845 3557 6562


62
2890 10936 14756


63
9031 14220 21517


64
3529 12955 15902


65
413 6750 8735


66
6784 12092 16421


67
12019 13794 15308


68
12588 15378 17676


69
8067 14589 19304


70
1244 5877 6085


71
15897 19349 19993


72
1426 2394 12264


73
3456 8931 12075


74
13342 15273 20351


75
9138 13352 20798


76
7031 7626 14081


77
4280 4507 15617


78
4170 10569 14335


79
3839 7514 16578


80
4688 12815 18782


81
4861 7858 9435


82
605 5445 12912


83
2280 4734 7311


84
6668 8128 12638


85
3733 10621 19534


86
13933 18316 19341


87
1786 3037 21566


88
2202 13239 16432


89
4882 5808 9300


90
4580 8484 16754


91
14630 17502 18269


92
6889 11119 12447


93
8162 9078 16330


94
6538 17851 18100


95
17763 19793 20816


96
2183 11907 17567


97
6640 14428 15175


98
877 12035 14081


99
1336 6468 12328


100
5948 9146 12003


101
3782 5699 12445


102
1770 7946 8244


103
7384 12639 14989


104
1469 11586 20959


105
7943 10450 15907


106
5005 8153 10035


107
17750 18826 21513


108
4725 8041 10112


109
3837 16266 17376


110
11340 17361 17512


111
1269 4611 4774


112
2322 10813 16157


113
16752 16843 18959


114
70 4325 18753


115
3165 8153 15384


116
160 8045 16823


117
14112 16724 16792


118
4291 7667 18176


119
5943 19879 20721

















TABLE 7






Index of row where 1 is 


i
located in the 0th column of the ith column group
















0
316 1271 3692 9495 12147 12849 14928 16671 16938 17864



19108 20502 21097 21115


1
2341 2559 2643 2816 2865 5137 5331 7000 7523 8023 10439



10797 13208 15041


2
5556 6858 7677 10162 10207 11349 12321 12398 14787 15743



15859 15952 19313 20879


3
349 573 910 2702 3654 6214 9246 9353 10638 11772 14447



14953 16620 19888


4
204 1390 2887 3855 6230 6533 7443 7876 9299 10291



10896 13960 18287 20086


5
541 2429 2838 7144 8523 8637 10490 10585 11074 12074



15762 16812 17900 18548


6
733 1659 3838 5323 5805 7882 9429 10682 13697 16909



18846 19587 19592 20904


7
1134 2136 4631 4653 4718 5197 10410 11666 14996 15305



16048 17417 18960 20303


8
734 1001 1283 4959 10016 10176 10973 11578 12051 15550



15915 19022 19430 20121


9
745 4057 5855 9885 10594 10989 13156 13219 13351 13631



13685 14577 17713 20386


10
968 1446 2130 2502 3092 3787 5323 8104 8418 9998 11681



13972 17747 17929


11
3020 3857 5275 5786 6319 8608 11943 14062 17144 17752



18001 18453 19311 21414


12
709 747 1038 2181 5320 8292 10584 10859 13964 15009



15277 16953 20675 21509


13
1663 3247 5003 5760 7186 7360 10346 14211 14717 14792



15155 16128 17355 17970


14
516 578 1914 6147 9419 11148 11434 13289 13325 13332



19106 19257 20962 21556


15
5009 5632 6531 9430 9886 10621 11765 13969 16178



16413 18110 18249 20616 20759


16
457 2686 3318 4608 5620 5858 6480 7430 9602 12691



14664 18777 20152 20848


17
33 2877 5334 6851 7907 8654 10688 15401 16123 17942



17969 18747 18931 20224


18
87 897 7636 8663 11425 12288 12672 14199 16435 17615



17950 18953 19667 20281


19
1042 1832 2545 2719 2947 3672 3700 6249 6398 6833



11114 14283 17694 20477


20
326 488 2662 2880 3009 5357 6587 8882 11604 14374



18781 19051 19057 20508


21
854 1294 2436 2852 4903 6466 7761 9072 9564 10321



13638 15658 16946 19119


22
194 899 1711 2408 2786 5391 7108 8079 8716 11453



17303 19484 20989 21389


23
1631 3121 3994 5005 7810 8850 10315 10589 13407



17162 18624 18758 19311 20301


24
736 2424 4792 5600 6370 10061 16053 16775 18600


25
1254 8163 8876 9157 12141 14587 16545 17175 18191


26
388 6641 8974 10607 10716 14477 16825 17191 18400


27
5578 6082 6824 7360 7745 8655 11402 11665 12428


28
3603 8729 13463 14698 15210 19112 19550 20727 21052


29
48 1732 3805 5158 15442 16909 19854 21071 21579


30
11707 14014 21531


31
1542 4133 4925


32
10083 13505 21198


33
14300 15765 16752


34
778 1237 11215


35
1325 3199 14534


36
2007 14510 20599


37
1996 5881 16429


38
5111 15018 15980


39
4989 10681 12810


40
3763 10715 16515


41
2259 10080 15642


42
9032 11319 21305


43
3915 15213 20884


44
11150 15022 20201


45
1147 6749 19625


46
12139 12939 18870


47
3840 4634 10244


48
1018 10231 17720


49
2708 13056 13393


50
5781 11588 18888


51
1345 2036 5252


52
5908 8143 15141


53
1804 13693 18640


54
10433 13965 16950


55
9568 10122 15945


56
547 6722 14015


57
321 12844 14095


58
2632 10513 14936


59
6369 11995 20321


60
9920 19136 21529


61
1990 2726 10183


62
5763 12118 15467


63
503 10006 19564


64
9839 11942 194752


65
11205 13552 15389


66
8841 13797 19697


67
124 6053 18224


68
6477 14406 21146


69
1224 8027 16011


70
3046 4422 17717


71
739 12308 17760


72
4014 4130 7835


73
2266 5652 11981


74
2711 7970 18317


75
2196 15229 17217


76
8636 13302 16764


77
5612 15010 16657


78
615 1249 4369


79
3821 12073 18506


80
1066 16522 21536


81
11307 18363 19740


82
3240 8560 10391


83
3124 11424 20779


84
1604 8861 17394


85
2083 7400 8093


86
3218 7454 9155


87
9855 15998 20533


88
316 2850 20652


89
5583 9768 10333


90
7147 7713 18339


91
12607 17428 21418


92
14216 16954 18164


93
8477 15970 18488


94
1632 8032 9751


95
4573 9080 13507


96
11747 12441 13876


97
1183 15605 16675


98
4408 10264 17109


99
5495 7882 12150


100
1010 3763 5065


101
9828 18054 21599


102
6342 7353 15358


103
6362 9462 19999


104
7184 13693 17622


105
4343 4654 10995


106
7099 8466 18520


107
11505 14395 15138


108
6779 16691 18726


109
7146 12644 20196


110
5865 16728 19634


111
4657 8714 21246


112
4580 5279 18750


113
3767 6620 18905


114
9209 13093 17575


115
12486 15875 19791


116
8046 14636 17491


117
2120 4643 13206


118
6186 9675 12601


119
784 5770 21585









In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the ith column group of the information word submatrix 210 are defined as shown in Table 8 below.








TABLE 8






Index of row where 1 is 


i
located in the 0th column of the ith column group
















0
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737



8632 8940 9725


1
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367



10042 11242 12917


2
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681



11811 11886 12089 12909


3
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092



11139 11256 12201 12383


4
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863



9201 11294 11376 12184


5
27 101 197 290 871 1727 3911 5411 6676 8701 9350



10310 10798 12439


6
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165



10184 10824 11278 12669


7
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037



10353 10583 11118 12762


8
73 1594 2146 2715 3501 3572 3639 3725 6959 7187



8406 10120 10507 10691


9
240 732 1215 2185 2788 2830 3499 3881 4197 4991



6425 7061 9756 10491


10
831 1568 1828 3424 4319 4516 4639 6018 9702



10203 10417 11240 11518 12458


11
2024 2970 3048 3638 3676 4152 5284 5779 5926



9426 9945 10873 11787 11837


12
1049 1218 1651 2328 3493 4363 5750 6483 7613



8782 9738 9803 11744 11937


13
1193 2060 2289 2964 3478 4592 4756 6709 7162



8231 8326 11140 11908 12243


14
978 2120 2439 3338 3850 4589 6567 8745 9656



9708 10161 10542 10711 12639


15
2403 2938 3117 3247 3711 5593 5844 5932 7801



10152 10226 11498 12162 12941


16
1781 2229 2276 2533 3582 3951 5279 5774 7930



9824 10920 11038 12340 12440


17
289 384 1980 2230 3464 3873 5958 8656 8942



9006 10175 11425 11745 12530


18
155 354 1090 1330 2002 2236 3559 3705 4922



5958 6576 8564 9972 12760


19
303 876 2059 2142 5244 5330 6644 7576 8614



9598 10410 10718 11033 12957


20
3449 3617 4408 4602 4727 6182 8835 8928 9372



9644 10237 10747 11655 12747


21
811 2565 2820 8677 8974 9632 11069 11548



11839 12107 12411 12695 12812 12890


22
972 4123 4943 6385 6449 7339 7477 8379 9177



9359 10074 11709 12552 12831


23
842 973 1541 2262 2905 5276 6758 7099 7894



8128 8325 8663 8875 10050


24
474 791 968 3902 4924 4965 5085 5908 6109



6329 7931 9038 9401 10568


25
1397 4461 4658 5911 6037 7127 7318 8678



8924 9000 9473 9602 10446 12692


26
1334 7571 12881


27
1393 1447 7972


28
633 1257 10597


29
4843 5102 11056


30
3294 8015 10513


31
1108 10374 10546


32
5353 7824 10111


33
3398 7674 8569


34
7719 9478 10503


35
2997 9418 9581


36
5777 6519 11229


37
1966 5214 9899


38
6 4088 5827


39
836 9248 9612


40
483 7229 7548


41
7865 8289 9804


42
2915 11098 11900


43
6180 7096 9481


44
1431 6786 8924


45
748 6757 8625


46
3312 4475 7204


47
1852 8958 11020


48
1915 2903 4006


49
6776 10886 12531


50
2594 9998 12742


51
159 2002 12079


52
853 3281 3762


53
5201 5798 6413


54
3882 6062 12047


55
4133 6775 9657


56
228 6874 11183


57
7433 10728 10864


58
7735 8073 12734


59
2844 4621 11779


60
3909 7103 12804


61
6002 9704 11060


62
5864 6856 7681


63
3652 5869 7605


64
2546 2657 4461


65
2423 4203 9111


66
244 1855 4691


67
1106 2178 6371


68
391 1617 10126


69
250 9259 10603


70
3435 4614 6924


71
1742 8045 9529


72
7667 8875 11451


73
4023 6108 6911


74
8621 10184 11650


75
6726 10861 12348


76
3228 6302 7388


77
1 1137 5358


78
381 2424 8537


79
3256 7508 10044


80
1980 2219 4569


81
2468 5699 10319


82
2803 3314 12808


83
8578 9642 11533


84
829 4585 7923


85
59 329 5575


86
1067 5709 6867


87
1175 4744 12219


88
109 2518 6756


89
2105 10626 11153


90
5192 10696 10749


91
6260 7641 8233


92
2998 3094 11214


93
3398 6466 11494


94
6574 10448 12160


95
2734 10755 12780


96
1028 7958 10825


97
8545 8602 10793


98
392 3398 11417


99
6639 9291 12571


100
1067 7919 8934


101
1064 2848 12753


102
6076 8656 12690


103
5504 6193 10171


104
1951 7156 7356


105
4389 4780 7889


106
526 4804 9141


107
1238 3648 10464


108
2587 5624 12557


109
5560 5903 11963


110
1134 2570 3297


111
10041 11583 12157


112
1263 9585 12912


113
3744 7898 10646


114
45 9074 10315


115
1051 6188 10038


116
2242 8394 12712


117
3598 9025 12651


118
2295 3540 5610


119
1914 4378 12423


120
1766 3635 12759


121
5177 9586 11143


122
943 3590 11649


123
4864 6905 10454


124
5852 6042 10421


125
6095 8285 12349


126
2070 7171 8563


127
718 12234 12716


128
512 10667 11353


129
3629 6485 7040


130
2880 8865 11466


131
4490 10220 11796


132
5440 8819 9103


133
5262 7543 12411


134
516 7779 10940


135
2515 5843 9202


136
4684 5994 10586


137
573 2270 3324


138
7870 8317 10322


139
6856 7638 12909


140
1583 7669 10781


141
8141 9085 12555


142
3903 5485 9992


143
4467 11998 12904









In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the position of 1 in the information word submatrix 210 may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
According to an exemplary embodiment, even when an order of numbers, i.e., indexes, in a sequence corresponding to the ith column group of the parity check matrix 200 as shown in the above-described Tables 4 to 8 is changed, the changed parity check matrix is a parity check matrix used for the same LDPC code. Therefore, a case in which the order of numbers in the sequence corresponding to the ith column group in Tables 4 to 8 is changed is also covered by the present inventive concept.
In addition, even when an arrangement order of sequences corresponding to each column group shown in Tables 4 to 8 is changed, cycle characteristics on a graph of the LDPC code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 8 is changed is also covered by the present inventive concept.
In addition, even when a multiple of Qldpc is equally added to all sequences corresponding to a certain column group in Tables 4 to 8, the cycle characteristics on the graph of the LDPC code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Qldpc to the sequences shown in Tables 4 to 8 is also covered by the present inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Qldpc to a given sequence is greater than or equal to (Nldpc−Kldpc), a value obtained by applying a modulo operation for (Nldpc−Kldpc) to the resulting value should be applied instead.
Once positions of the rows where 1 exists in the 0th column of the ith 1 column group of the information word submatrix 210 are defined as shown in Tables 4 to 8, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0th column are cyclic-shifted by Qldpc in the next column.
For example, in the case of Table 4, in the 0th column of the 0th column group of the information word submatrix 210, 1 exists in the 1606th row, 3402nd row, 4961st row, . . . .
In this case, since Qldpc=(Nldpc−Kldpc)/M=(64800−25920)/360=108, the indexes of the rows where 1 is located in the 1st column of the 0th column group may be 1714(=1606+108), 3510(=3402+108), 5069(=4961+108), . . . , and the indexes of the rows where 1 is located in the 2nd column of the 0th column group may be 1822(=1714+108), 3618(=3510+108), 5177(=5069+108) . . . .
In the above-described method, the indexes of the rows where 1 is located in all columns of each column group may be defined.
The parity submatrix 220 of the parity check matrix 200 shown in FIG. 20 may be defined as follows:
The parity submatrix 220 includes Nldpc−Kldpc number of columns (that is, Kldpcth column to (Nldpc−1)th column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (Nldpc−1)th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.
As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 8, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.
When the columns and rows of the parity check matrix 200 shown in FIG. 20 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 20 may be changed to a parity check matrix 300 shown in FIG. 21.

Qldpc·i+jM·j+i(0≦i<M,0≦j<Qldpc)  (4)

Kldpc+Qldpc·k+lKldpc+M·l+k(0≦k<M,0≦l<Qldpc)  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.
In the case of the row permutation, regarding the Xth row, i and j satisfying X=Qldpc×i+j are calculated and the Xth row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7th row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7th row is permutated to the 13th row (10×1+3=13).
When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 20 may be converted into the parity check matrix of FIG. 21.
Referring to FIG. 21, the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.
Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of matrix units of M×M. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300.
Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of Nqc_column=Nldpc/M number of column blocks and Nqc_row=Nparity/M number of row blocks.
Hereinafter, the submatrix of M×M will be explained.
First, the (Nqc_column−1)th column block of the 0th row block A 330 has the format of Equation 6 presented below:




  
    
      
        A
        =
        
          [
          
            
              
                0
              
              
                0
              
              
                ...
              
              
                0
              
              
                0
              
            
            
              
                1
              
              
                0
              
              
                ...
              
              
                0
              
              
                0
              
            
            
              
                0
              
              
                1
              
              
                ...
              
              
                0
              
              
                0
              
            
            
              
                ⋮
              
              
                ⋮
              
              
                ⋮
              
              
                ⋮
              
              
                ⋮
              
            
            
              
                0
              
              
                0
              
              
                ...
              
              
                1
              
              
                0
              
            
          
          ]
        
      
    
    
      
        (
        6
        )
      
    
  




As described above, A 330 is an M×M matrix, values of the 0th row and the (M−1)th column are all “0”, and, regarding 0≦i≦(M−2), the (i+1)th row of the ith column is “1” and the other values are “0”.
Second, regarding 0≦i≦(Nldpc−Kldpc)/M−1 in the parity submatrix 320, the ith row block of the (Kldpc/M+i)th column block is configured by a unit matrix IM×M 340. In addition, regarding 0≦i≦(Nldpc−Kldpc)/M−2, the (i+1)th row block of the (Kldpc/M+i)th column block is configured by a unit matrix IM×M 340.
Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, Paij, or an added format of the cyclic-shifted matrix Paij of the cyclic matrix P (or an overlapping format).
For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:




  
    
      
        P
        =
        
          [
          
            
              
                0
              
              
                1
              
              
                0
              
              
                
                  
                
              
              
                0
              
            
            
              
                0
              
              
                0
              
              
                1
              
              
                ...
              
              
                0
              
            
            
              
                ⋮
              
              
                ⋮
              
              
                ⋮
              
              
                
                  
                
              
              
                ⋮
              
            
            
              
                0
              
              
                0
              
              
                0
              
              
                ...
              
              
                1
              
            
            
              
                1
              
              
                0
              
              
                0
              
              
                
                  
                
              
              
                0
              
            
          
          ]
        
      
    
    
      
        (
        7
        )
      
    
  




The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When aij is 0, the cyclic matrix P, that is, P0 indicates a unit matrix IM×M, and when aij is ∞, P∞ is a zero matrix.
A submatrix existing where the ith row block and the jth column block intersect in the parity check matrix 300 of FIG. 21 may be Paij. Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300, the total number of columns is Nldpc=M×Nqc_column, and the total number of rows is Nparity=M×Nqc_row. That is, the parity check matrix 300 is formed of Nqc_column number of “column blocks” and Nqc_row number of “row blocks”.
Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 20 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 4 by way of an example will be explained for the convenience of explanation.
First, when information word bits having the length of Kldpc are [i0, i1, i2, . . . , iKldpc−1], and parity bits having the length of Nldpc−Kldpc are [p0, p1, p2, . . . PNldpc−Kidpc−1], the LDPC encoding is performed by the following process.
Step 1) Parity bits are initialized as ‘0’. That is, p0=p1=p2= . . . =pNldpc−Kldpc−1=0.
Step 2) The 0th information word bit i0 is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of Table 4 as the index of the parity bit. This may be expressed by Equation 8 presented below:

P1606=P1606⊕i0 P24533=P24533⊕i0 

P3402=P3402⊕i0 P25376=P25376⊕i0 

P4961=P4961⊕i0 P25667=P25667⊕i0 

P6751=P6751⊕i0 P26836=P26836⊕i0 

P7132=P7132⊕i0 P31799=P31799⊕i0 

P11516=P11516⊕i0 P34173=P34173⊕i0 

P12300=P12300⊕i0 P35462=P35462⊕i0 

P12482=P12482⊕i0 P36153=P36153⊕i0 

P12592=P12592⊕i0 P36740=P36740⊕i0 

P13342=P13342⊕i0 P37085=P37085⊕i0 

P13764=P13764⊕i0 P37152=P37152⊕i0 

P14123=P1412⊕i0 P37468=P37468⊕i0 

P21576=P21576⊕i0 P37658=P37658⊕i0 

P23946=P23946⊕i0  (8)

Herein, i0 is a 0th information word bit, pi is an parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.
Step 3) The other 359 information word bits im (m=1, 2, . . . , 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of i0. In this case, the address of the parity bit may be determined based on Equation 9 presented below:

(x+(m mod 360)×Qldpc)mod(Nldpc−Kldpc)  (9)

In the above, x is an address of a parity bit accumulator corresponding to the information word bit i0, and Qldpc is a size by which each column is cyclic shifted in the information word submatrix, and may be 108 in the case of Table 4. In addition, since m=1, 2, . . . , 359, (m mod 360) in Equation 9 may be regarded as m.
As a result, information word bits im (m=1, 2, . . . , 359) are accumulated in the parity bits having addresses of the parity bits calculated based on Equation 9 as the indexes, respectively. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit

P1714=P1714⊕i1 P24641=P24641⊕i1 

P3510=P3510⊕i1 P25484=P25484⊕i1 

P5069=P5069⊕i1 P25775=P25775⊕i1 

P6859=P6859⊕i1 P26944=P26944⊕i1 

P7240=P7240⊕i1 P31907=P31907⊕i1 

P11624=P11624⊕i1 P34281=P34281⊕i1 

P12408=P12408⊕i1 P35570=P35570⊕i1 

P12590=P12590⊕i1 P36261=P36261⊕i1 

P12700=P12700⊕i1 P36848=P36848⊕i1 

P13450=P13450⊕i1 P37193=P37193⊕i1 

P13872=P13872⊕i1 P37260=P37260⊕i1 

P14231=P14231⊕i1 P37576=P37576⊕i1 

P21684=P21684⊕i1 P37576=P37576⊕i1 

P24054=P24054⊕i1  (10)

Herein, i1 is a 1st information word bit, pi is an ith parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.
Step 4) The 360th information word bits i360 is accumulated in a parity bit having an address of the parity bit defined in the 2nd row (that is, the row of i=1) of Table 4 as the index of the parity bit.
Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i360 are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit i360.
Step 6) Steps 4 and 5 described above are repeated for all of the column groups of Table 4.
Step 7) As a result, a parity bit pi is calculated based on Equation 11 presented below. In this case, i is initialized as 1.

pi=pi⊕pi−1i=1,2, . . . ,Nldpc−Kldpc−1  (11)

In Equation 11, pi is an ith parity bit, Nldpc is a length of an LDPC codeword, Kldpc is a length of an information word of the LDPC codeword, and ⊕ is a binary operation.
As a result, the encoder 110 may calculate the parity bits according to the above-described method.
Referring back to FIG. 19, the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.
In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix having the information word submatrix defined by Tables 4 to 8 and the parity submatrix having the dual diagonal configuration (that is, the parity check matrix shown in FIG. 20), or may perform the LDPC encoding by using the parity check matrix which is row and column permutated from the parity check matrix of FIG. 20 based on Equation 4 and Equation 5 (that is, the parity check matrix having the configuration of FIG. 21).
In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as the LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.
In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating an LDPC codeword.
The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on various interleaving rules.
In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map the bit included in the predetermined group from among the plurality of bit groups constituting the LDPC codeword onto the predetermined bit of the modulation symbol.
Hereinafter, the interleaving rules used in the interleaver 120 will be explained in detail according to cases.
Exemplary Embodiment 1
Case in which a Block Interleaver is Used
According to a first exemplary embodiment, the interleaver 120 may interleave the LDPC codeword in the method as described below, such that the bit included in a predetermined bit group from among the plurality of bit groups constituting the interleaved LDPC codeword is mapped onto a predetermined bit of a modulation symbol. This will be explained below in detail with reference to FIG. 22.
FIG. 22 is a block diagram to illustrate the a configuration of an interleaver according to an exemplary embodiment. Referring to FIG. 22, the interleaver 120 may include a parity interleaver 121, a group interleaver 122 (or a group-wise interleaver 122), a group twist interleaver 123 and a block interleaver 124.
The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.
Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 20, the parity interleaver 121 may interleave only the parity bits of the LDPC codeword, among the information word bits and the partiy bits of the LDPC codeword, by using Equations 12 presented below:

ui=ci for 0≦i<Kldpc, and

uKldpc+M·t+s=cKldpc+Qldpc·s+1 for 0≦s<M,0≦t<Qldpc  (12),

where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210, that is, the number of columns included in a column group (for example, M=360), and Qldpc is a size by which each column is cyclic-shifted in the information word submatrix 210. That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c0, c1, . . . , cNldpc−1), and outputs U=(u0, u1, . . . , uNldpc−1).

The LDPC codeword which is parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).
For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.
Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the ith LDPC codeword bit, ci (i=0, 1, . . . , Nldpc−1) and the ith column of the parity check matrix should be a “0” vector. Accordingly, the ith LDPC codeword bit may be regarded as corresponding to the ith column of the parity check matrix.
In the case of the parity check matrix 200 of FIG. 20, M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).
In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.
However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 21, parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.
The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups in bits group wise (group units). That is, the group interleaver 122 may interleave the plurality of bit groups in bits group wise.
To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups by using Equation 13 or Equation 14 presented below.




  
    
      
        
          X
          j
        
        =
        
          
            
              {
              
                
                  
                    
                      u
                      k
                    
                    |
                    j
                  
                  =
                  
                    ⌊
                    
                      k
                      360
                    
                    ⌋
                  
                
                ,
                
                  0
                  ≤
                  k
                  <
                  
                    N
                    ldpc
                  
                
              
              }
            
            ⁢
            for
            ⁢
            
              
            
            ⁢
            0
          
          ≤
          j
          <
          
            N
            group
          
        
      
    
    
      
        (
        13
        )
      
    
  




Xj={uk|360×j≦k<360×(j+1),0≦k<Nldpc} for 0≦j<Ngroup  (14)

where Ngroup is the total number of bit groups, Xj is the jth bit group, and uk is the kth LDPC codeword bit input to the group interleaver 122. In addition,




  ⌊
  
    k
    360
  
  ⌋




is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.
The LDPC codeword which is divided into the plurality of bit groups may be expressed as shown in FIG. 23.
Referring to FIG. 23, the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, each of the bit groups may be formed of bits corresponding to each of the column groups of the parity check matrix.
Specifically, since the LDPC codeword is divided by M number of continuous bits, Kldpc number of information word bits are divided into (Kldpc/M) number of bit groups, and Nldpc−Kldpc number of parity bits are divided into (Nldpc−Kldpc)/M number of bit groups. Accordingly, the LDPC codeword may be divided into (Nldpc/M) number of bit groups in total.
For example, when M=360 and the length Nldpc of the LDPC codeword is 64800, the number of bit groups Ngroups is 180 (=64800/360), and, when the length Nldpc of the LDPC codeword is 16200, the number of bit groups Ngroup is 45 (16200/360).
As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.
In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.
For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of an aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.
In the following explanation, the number of bits constituting a bit group is M by way of an example, for the convenience of explanation.
Thereafter, the group interleaver 122 interleaves the LDPC codeword in bits group wise. Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bits group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC codeword and rearranges the order of the plurality of bit groups constituting the LDPC codeword in bits group wise.
According to an exemplary embodiment, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise such that bit groups including bits mapped onto a same modulation symbol from among the plurality of bit groups are spaced apart from one another at a predetermined interval.
In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by considering at least one of the number of rows and columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at the predetermined interval.
To achieve this, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 15 presented below:

Yj=Xπ(j)(0≦j<Ngroup)  (15),

where Xj is the jth bit group before group interleaving, and Yj is the jth bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate, and a modulation method. That is, π(j) denotes a permutation order for group wise interleaving.

Accordingly, Xπ(j) is a π(j)th bit group before group interleaving, and Equation 15 means that the pre-interleaving π(j)th bit group is interleaved into the jth bit group.
According to an exemplary embodiment, an example of π(j) may be defined as in Tables 9 to 13 presented below.
In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bits group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 64800 and the code rate of 6/15 in Tables 9 to 13 presented below, for example, by using π(j) defined as shown in Table 9.
For example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 1024-Quadrature Amplitude Modulation (QAM), π(j) may be defined as in Table 9 presented below.








TABLE 9








Order of bits group to be block irterleaved



π(j) (0 ≦ j < 180)































0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

































j-th block of
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


Group-wise
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


interleaver
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91


output
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j) th block of
66
21
51
55
54
24
33
12
70
63
47
65
145
8
0
57
23
71
59
14
40
42
62


Group wise
56
2
43
64
58
67
53
68
61
39
52
69
1
12
31
161
38
30
19
17
18
4
41


interleaver
25
44
136
29
36
26
126
177
15
37
148
9
13
45
46
152
50
49
27
77
60
35
48


Groupwisc
178
28
34
106
127
76
131
105
138
75
130
101
167
117
173
113
108
92
135
124
121
97
149


input
143
81
32
96
3
78
107
86
98
16
162
150
111
158
172
139
74
142
166
7
5
119
20



144
151
90
11
156
100
175
83
155
159
128
88
87
93
103
94
140
165
6
137
157
10
85



141
129
146
122
73
112
132
125
174
169
168
79
84
118
179
147
91
160
163
115
89
80
102



104
134
82
95
133
164
154
120
110
170
114
153
72
109
171
176
99
116
123









In the case of Table 9, Equation 15 may be expressed as Y0=Xπ(0)=X66, Y1=Xπ(1)=X21, Y2=Xπ(2)=X51, . . . , Y178=Xπ(178)=X116, and Y179=Xπ(179)=X123. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 66th bit group to the 0th bit group, the 21st bit group to the 1st bit group, the 51st bit group to the 2nd bit group, . . . , the 116th bit group to the 178th bit group, and the 123rd bit group to the 179th bit group. Herein, the changing the Ath bit group to the Bth bit group means rearranging the order of bit groups so that the Ath bit group is to be the Bth bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 10 presented below.







TABLE 10







Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)































0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

































j-th block of
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


Group-wise
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


interleaver
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91


output
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
77
48
82
51
57
69
65
6
71
90
84
81
50
88
61
55
53
73
39
13
79
75
41


Group-wise
18
38
89
49
93
36
64
47
40
42
76
70
56
3
72
2
54
52
145
19
78
80
63


interleaver
87
67
86
10
1
58
17
14
175
91
68
85
94
15
43
74
60
66
37
92
4
9
16


input
83
46
44
102
30
112
122
110
29
20
105
138
101
174
33
137
136
131
166
59
34
62
125



28
26
45
24
23
21
157
98
35
95
22
32
103
27
113
31
119
173
168
118
120
114
149



159
155
179
160
161
130
123
172
139
124
153
0
109
167
128
107
117
147
177
96
164
152
11



148
158
129
163
176
151
171
8
106
144
150
169
108
162
143
111
141
133
178
134
146
99
132



142
104
115
135
121
100
12
170
156
126
5
127
154
97
140
116
165
7
25









In the case of Table 10, Equation 15 may be expressed as Y0=Xπ(0)=X77, Y1=Xπ(1)=X48, Y2=Xπ(2)=X82, . . . , Y178=Xπ(178)=X7, and Y179=Xπ(179)=X25. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 77th bit group to the 0th bit group, the 48th bit group to the 1st bit group, the 82nd bit group to the 2nd bit group, . . . , the 7th bit group to the 178th bit group, and the 25th bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 11 presented below. In particular, when the encoder 110 performs LDPC encoding based on the parity check matrix defined by Table 6, the group interleaver 122 may perform group interleaving by using π(j) defined as in Table 11 presented below:







TABLE 11





Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
7
58
108
59
1
14
54
115
57
29
64
65
8
101
113
60
46
104
87
9
93
81
94


Group-wise
71
106
50
44
15
52
4
100
90
111
77
89
92
S
82
10
116
109
75
91
47
80
99


interleaver
103
30
105
76
107
88
95
28
66
102
25
39
78
53
118
112
0
83
22
36
51
55
85


input
86
45
119
23
79
35
72
33
98
40
38
24
63
73
20
48
27
96
68
26
110
42
12



41
97
2
21
61
117
70
62
34
11
67
37
49
114
56
32
149
163
173
159
132
170
179



69
139
133
154
160
128
168
84
171
162
31
43
135
123
178
130
127
145
157
176
177
140
151



134
126
18
129
137
74
148
147
167
136
164
146
153
138
161
6
143
124
17
174
131
175
165



150
16
172
3
155
169
142
156
120
122
19
144
158
13
152
141
166
125
121









In the case of Table 11, Equation 15 may be expressed as Y0=Xπ(0)=X7, Y1=Xπ(1)=X58, Y2=Xπ(2)=X108, . . . , Y178=Xπ(178)=X125, and Y179=Xπ(179)=X121. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 7th bit group to the 0th bit group, the 58th bit group to the 1st bit group, the 108th bit group to the 2nd bit group, . . . , the 125th bit group to the 178th bit group, and the 121st bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 12 presented below. In particular, when the encoder 110 performs LDPC encoding based on the parity check matrix defined by Table 7, the group interleaver 122 may perform group interleaving by using π(j) defined as in Table 12 presented below:







TABLE 12





Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
111
45
78
97
75
63
35
15
9
25
39
94
24
84
100
49
44
41
32
101
82
23
79


Group-wise
68
98
31
107
19
110
48
58
71
87
43
62
85
70
95
57
10
50
99
118
73
27
12


interleaver
1
17
61
55
90
56
14
47
77
2
117
20
74
106
83
102
109
113
72
88
115
37
30


input
116
29
26
54
38
60
111
59
105
67
103
0
80
64
4
91
66
46
108
33
104
93
7



42
51
40
119
8
21
81
76
112
28
34
36
86
69
92
53
122
126
131
160
154
6
22



142
141
136
157
162
123
159
150
171
174
137
65
13
177
166
139
167
172
176
153
89
152
168



135
52
170
138
127
96
165
156
148
179
163
3
133
143
121
132
169
147
173
155
149
178
158



16
144
128
11
175
134
124
130
146
161
145
120
129
164
125
5
151
18
140









In the case of Table 12, Equation 15 may be expressed as Y0=Xπ(0)=X111, Y1=Xπ(1)=X45, Y2=Xπ(2)=X78, . . . , Y178=Xπ(178)=X18, and Y179=Xπ(179)=X140. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 111th bit group to the 0th bit group, the 45th bit group to the 1st bit group, the 78th bit group to the 2nd bit group, . . . , the 18th bit group to the 178th bit group, and the 140th bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 13 presented below.







TABLE 13





Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
91
19
11
106
14
40
20
67
32
22
31
23
78
68
79
141
117
95
88
136
52
121
1


Group-wise
133
4
2
71
122
38
12
69
111
81
82
58
46
112
60
33
73
53
92
75
48
47
110


interleaver
80
76
138
87
85
65
130
57
102
83
64
86
100
39
49
125
108
119
6
118
35
61
71


input
30
45
94
26
116
98
37
55
44
70
25
7
34
114
135
128
137
84
51
28
97
27
89



29
62
50
139
56
109
77
59
127
142
96
105
99
90
13
124
120
115
126
143
149
74
41



178
129
18
131
42
165
101
134
36
140
132
103
72
164
93
54
166
43
123
113
0
154
10



63
107
162
157
66
104
17
147
167
174
179
3
173
160
155
161
152
156
177
24
170
9
159



16
15
148
5
146
163
172
175
151
169
176
150
153
171
158
168
144
8
145









In the case of Table 13, Equation 15 may be expressed as Y0=Xπ(0)=X91, Y1=Xπ(1)=X19, Y2=Xπ(2)=X11, . . . , Y178=Xπ(178)=X8, and Y179=Xπ(179)=X145. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 91st bit group to the 0th bit group, the 19th bit group to the 1st bit group, the 11th bit group to the 2nd bit group, . . . , the 8th bit group to the 178th bit group, and the 145th bit group to the 179th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 15 and Tables 9 to 13.
“j-th block of Group-wise Interleaver output” in Tables 9 to 13 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bits group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 9 to 13 in relation to π(j).
π(j) defined as shown in Tables 9 to 13 may be arranged according to the code rates as shown in Table 14 presented below:












TABLE 14






(CR 6/15)
(CR 8/15)
(CR 10/15)
(CR 10/15)
(CR 12/15)


j-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of


Group-wise
Group-wise
Group-wise
Group-wise
Group-wise
Group-wise


Interleaver
Interleaver
Interleaver
Interleaver
Interleaver
Interleaver


output
input
input
input
input
input




















0
66
77
7
111
91


1
21
48
58
45
19


2
51
82
108
78
11


3
55
51
59
97
106


4
54
57
1
75
14


5
24
69
14
63
40


6
33
65
54
35
20


7
12
6
115
15
67


8
70
71
57
9
32


9
63
90
29
25
22


10
47
84
64
39
31


11
65
81
65
94
23


12
145
50
8
24
78


13
8
88
101
84
68


14
0
61
113
100
79


15
57
55
60
49
141


16
23
53
46
44
117


17
71
73
104
41
95


18
59
39
87
32
88


19
14
13
9
101
136


20
40
79
93
82
52


21
42
75
81
23
121


22
62
41
94
79
1


23
56
18
71
68
133


24
2
38
106
98
4


25
43
89
50
31
2


26
64
49
44
107
21


27
58
93
15
19
122


28
67
36
52
110
38


29
53
64
4
48
12


30
68
47
100
58
69


31
61
40
90
71
111


32
39
42
111
87
81


33
52
76
77
43
82


34
69
70
89
62
58


35
1
56
92
85
46


36
22
3
5
70
112


37
31
72
82
95
60


38
161
2
10
57
33


39
38
54
116
10
73


40
30
52
109
50
53


41
19
145
75
99
92


42
17
19
91
118
75


43
18
78
47
73
48


44
4
80
80
27
47


45
41
63
99
12
110


46
25
87
103
1
80


47
44
67
30
17
76


48
136
86
105
61
138


49
29
10
76
55
87


50
36
1
107
90
85


51
26
58
88
56
65


52
126
17
95
14
130


53
177
14
28
47
57


54
15
175
66
77
102


55
37
91
102
2
83


56
148
68
25
117
64


57
9
85
39
20
86


58
13
94
78
74
100


59
45
15
53
106
39


60
46
43
118
83
49


61
152
74
112
102
125


62
50
60
0
109
108


63
49
66
83
113
119


64
27
37
22
72
6


65
77
92
36
88
118


66
60
4
51
115
35


67
35
9
55
37
61


68
48
16
85
30
71


69
178
83
86
116
30


70
28
46
45
29
45


71
34
44
119
26
94


72
106
102
23
54
26


73
127
30
79
38
116


74
76
112
35
60
98


75
131
122
72
114
37


76
105
110
33
59
55


77
138
29
98
105
44


78
75
20
40
67
70


79
130
105
38
103
25


80
101
138
24
0
7


81
167
101
63
80
34


82
117
174
73
64
114


83
173
33
20
4
135


84
113
137
48
91
128


85
108
136
27
66
137


86
92
131
96
46
84


87
135
166
68
108
51


88
124
59
26
33
28


89
121
34
110
104
97


90
97
62
42
93
27


91
149
125
12
7
89


92
143
28
41
42
29


93
81
26
97
51
62


94
32
45
2
40
50


95
96
24
21
119
139


96
3
23
61
8
56


97
78
21
117
21
109


98
107
157
70
81
77


99
86
98
62
76
59


100
98
35
34
112
127


101
16
95
11
28
142


102
162
22
67
34
96


103
150
32
37
36
105


104
111
103
49
86
99


105
158
27
114
69
90


106
172
113
56
92
13


107
139
31
32
53
124


108
74
119
149
122
120


109
142
173
163
126
115


110
166
168
173
131
126


111
7
118
159
160
143


112
5
120
132
154
149


113
119
114
170
6
74


114
20
149
179
22
41


115
144
159
69
142
178


116
151
155
139
141
129


117
90
179
133
136
18


118
11
160
154
157
131


119
156
161
160
162
42


120
100
130
128
123
165


121
175
123
168
159
101


122
83
172
84
150
134


123
155
139
171
171
36


124
159
124
162
174
140


125
128
153
31
137
132


126
88
0
43
65
103


127
87
109
135
13
72


128
93
167
123
177
164


129
103
128
178
166
93


130
94
107
130
139
54


131
140
117
127
167
166


132
165
147
145
172
43


133
6
177
157
176
123


134
137
96
176
153
113


135
157
164
177
89
0


136
10
152
140
152
154


137
85
11
151
168
10


138
141
148
134
135
63


139
129
158
126
52
107


140
146
129
18
170
162


141
122
163
129
138
157


142
73
176
137
127
66


143
112
151
74
96
104


144
132
171
148
165
17


145
125
8
147
156
147


146
174
106
167
148
167


147
169
144
136
179
174


148
168
150
164
163
179


149
79
169
146
3
3


150
84
108
153
133
173


151
118
162
138
143
160


152
179
143
161
121
155


153
147
111
6
132
161


154
91
141
143
169
152


155
160
133
124
147
156


156
163
178
17
173
177


157
115
134
174
155
24


158
89
146
131
149
170


159
80
99
175
178
9


160
102
132
165
158
159


161
104
142
150
16
16


162
134
104
16
144
15


163
82
115
172
128
148


164
95
135
3
11
5


165
133
121
155
175
146


166
164
100
169
134
163


167
154
12
142
124
172


168
120
170
156
130
175


169
110
156
120
146
151


170
170
126
122
161
169


171
114
5
19
145
176


172
153
127
144
120
150


173
72
154
158
129
153


174
109
97
13
164
171


175
171
140
152
125
158


176
176
116
141
5
168


177
99
165
166
151
144


178
116
7
125
18
8


179
123
25
121
140
145









“j-th block of Group-wise Interleaver output” in Table 14 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122. Referring to Table 14, it can be seen that Table 14 is arrangement of data described in Tables 9 to 13 according to the code rates.
The group interleaver 122 may interleave the LDPC codeword in bits group wise by using Equation 16 presented below:

Yπ(j)=Xj(0≦j<Ngroup)  (16),

where Xj is the jth bit group before group interleaving, and Yj is the jth bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate, and a modulation method.

Accordingly, Xj is a jth bit group before group interleaving, and Equation 16 means that the pre-interleaving jth bit group is interleaved into the π(j)th bit group.
According to another exemplary embodiment, an example of π(j) may be defined as in Tables 15 to 19 presented below.
In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bits group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 64800 and the code rate of 6/15 in Tables 15 to 19 presented below, for example, by using π(j) defined as shown in Table 15.
For example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 15 presented below.










Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
14
35
24
96
44
112
133
111
13
57
136
118
7
58
19
54
101
42
43
41
114
1
36


Group-wise
16
5
46
51
64
70
49
40
37
91
6
71
67
50
55
39
32
20
45
21
25
47
59


interleaver
60
10
68
63
62
2
33
29
4
3
23
15
27
18
66
31
22
9
26
11
0
28
30


input
34
8
17
173
142
108
78
74
65
97
149
159
93
163
122
150
137
99
127
126
158
117
154



86
128
130
164
95
90
100
177
120
80
160
129
161
76
72
98
85
174
169
104
143
84
171



157
178
82
151
113
168
89
141
179
88
145
52
73
125
139
79
75
144
165
162
87
48
134



77
107
131
138
109
92
115
12
140
153
56
91
103
116
61
172
167
123
119
135
105
124
155



38
102
156
166
132
110
81
148
147
170
175
106
83
146
121
176
53
69
152









In the case of Table 15, Equation 16 may be expressed as X0=Yπ(0)=Y14, X1=Yπ(1)=Y35, X2=Yπ(2)=Y24, . . . , X178=Yπ(178)=Y69, and X179=Yπ(179)=Y152. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 14th bit group, the 1st bit group to the 35th bit group, the 2nd bit group to the 24th bit group, . . . , the 178th bit group to the 69th bit group, and the 179th bit group to the 152nd bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 16 presented below.










Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
126
50
38
36
66
171
7
178
145
67
49
137
167
19
53
59
68
52
23
42
78
97
102


Group-wise
96
95
179
93
105
92
77
73
107
103
83
89
100
28
64
24
18
31
22
32
60
71
94


interleaver
70
30
1
26
12
3
40
16
39
15
35
4
51
88
62
14
90
45
29
6
63
47
56


input
5
34
8
37
17
61
21
33
0
43
20
44
11
2
69
10
57
48
46
13
25
9
55



65
27
58
101
134
174
99
159
166
81
72
104
162
79
146
130
150
127
76
153
74
106
113



163
176
131
111
108
112
165
75
121
124
91
170
172
129
140
120
86
160
155
157
164
85
84



80
123
175
154
161
152
147
41
158
132
138
114
148
143
136
125
173
116
169
98
139
115
118



119
151
141
135
177
87
128
110
149
168
144
122
109
82
54
142
133
156
117









In the case of Table 16, Equation 16 may be expressed as X0=Yπ(0)=Y126, X1=Yπ(1)=Y50, X2=Yπ(2)=Y38, . . . , X178=Yπ(178)=Y156, and X179=Yπ(179)=Y117. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 126th bit group, the 1st bit group to the 50th bit group, the 2nd bit group to the 38th bit group, . . . , the 178th bit group to the 156th bit group, and the 179th bit group to the 117th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 17 presented below. In particular, when the encoder 110 performs LDPC encoding based on the parity check matrix defined by Table 6, the group interleaver 122 may perform group interleaving by using π(j) defined as in Table 17 presented below:










Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
62
4
94
164
29
36
153
0
12
19
38
101
91
174
5
27
162
156
140
171
83
95
64


Group-wise
72
80
56
88
85
53
9
47
125
107
76
100
74
65
103
79
57
78
92
90
126
26
70


interleaver
16
43
84
104
25
66
28
59
6
67
106
8
1
3
15
96
99
81
10
11
54
102
87


input
115
98
23
75
82
143
41
49
33
58
73
44
21
37
63
122
68
69
18
51
34
31
42



35
20
22
52
86
93
77
45
30
13
55
46
17
48
24
50
2
40
89
32
61
14
105



7
39
97
60
71
169
179
170
128
155
178
139
131
120
141
130
158
112
117
138
127
147
142



151
116
136
176
167
154
172
132
149
145
144
108
161
137
175
150
118
165
168
133
173
111
119



152
124
109
148
160
177
146
121
166
113
123
163
110
157
159
134
135
129
114









In the case of Table 17, Equation 16 may be expressed as X0=Yπ(0)=Y62, X1=Yπ(1)=Y4, X2=Yπ(2)=Y94, . . . , X178=Yπ(178)=Y129, and X179=Yπ(179)=Y114. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 62nd bit group, the 1st bit group to the 4th bit group, the 2nd bit group to the 94th bit group, . . . , the 178th bit group to the 129th bit group, and the 179th bit group to the 114th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 18 presented below. In particular, when the encoder 110 performs LDPC encoding based on the parity check matrix defined by Table 7, the group interleaver 122 may perform group interleaving by using π(j) defined as in Table 18 presented below:










Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
80
46
55
149
83
176
113
91
96
8
39
164
45
127
52
7
161
47
178
27
57
97
114


Group-wise
21
12
9
71
44
101
70
68
25
18
88
102
6
103
67
73
10
94
17
92
33
16
1


interleaver
86
53
29
15
40
93
139
107
72
49
51
38
30
76
74
48
34
5
82
126
85
78
23


input
105
36
31
64
43
58
4
99
54
2
22
81
98
20
60
13
35
104
32
65
135
50
84



106
90
11
37
143
3
24
41
14
19
61
79
89
77
59
26
87
62
28
0
100
63
75



66
69
56
42
95
172
152
108
120
167
175
109
142
163
173
168
110
153
150
166
138
117
125



141
130
179
116
115
151
162
171
169
155
146
158
122
177
136
134
112
157
145
118
160
121
111



170
119
148
174
144
129
131
137
154
140
123
132
156
124
165
133
128
159
147









In the case of Table 18, Equation 16 may be expressed as X0=Yπ(0)=Y80, X1=Yπ(1)=Y46, X2=Yπ(2)=Y55, . . . , X178=Yπ(178)=Y159, and X179=Y7(179)=Y147. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 80th bit group, the 1st bit group to the 46th bit group, the 2nd bit group to the 55th bit group, . . . , the 178th bit group to the 159th bit group, and the 179th bit group to the 147th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 19 presented below.










Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of
135
22
25
149
24
164
64
80
178
159
137
2
29
106
4
162
161
144
117
1
6
26
9


Group-wise
11
157
79
72
90
88
92
69
10
8
38
81
66
123
75
28
59
5
114
119
132
77
70


interleaver
35
44
43
60
94
87
20
40
130
76
96
53
34
99
37
67
93
138
56
51
142
7
13


input
30
78
68
127
39
113
42
47
98
12
14
46
32
33
55
86
50
57
49
18
91
105
0



41
129
71
17
102
89
74
104
58
121
54
126
143
103
3
139
62
97
45
31
36
134
82



109
76
16
65
63
108
21
27
133
107
61
110
100
84
116
52
118
125
23
122
83
19
85



48
95
124
15
101
111
177
179
165
145
163
112
172
169
154
173
136
152
155
141
175
160
151



153
140
166
128
120
131
146
176
170
158
174
167
150
147
168
171
156
115
148









In the case of Table 19, Equation 16 may be expressed as X0=Yπ(0)=Y135, X1=Yπ(1)=Y22, X2=Yπ(2)=Y25, . . . , X178=Yπ(178)=Y115, and X179=Yπ(179)=Y148. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 135th bit group, the 1st bit group to the 22nd bit group, the 2nd bit group to the 25th bit group, . . . , the 178th bit group to the 115th bit group, and the 179th bit group to the 148th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 16 and Tables 15 to 19.
“j-th block of Group-wise Interleaver input” in Tables 15 to 19 indicates the j-th bit group input to the group interleaver 122 before interleaving, and “π(j)-th block of Group-wise Interleaver output” indicates the π(j)-th bit group output from the group interleaver 122 after interleaving.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bits group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 15 to 19 in relation to π(j).
π(j) defined as shown in Tables 15 to 19 may be arranged according to the code rates as shown in Table 20:












TABLE 20






(CR 6/15)
(CR 8/15)
(CR 10/15)
(CR 10/15)
(CR 12/15)


j-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of


Group-wise
Group-wise
Group-wise
Group-wise
Group-wise
Group-wise


Interleaver
Interleaver
Interleaver
Interleaver
Interleaver
Interleaver


input
output
output
output
output
output




















0
14
126
62
80
135


1
35
50
4
46
22


2
24
38
94
55
25


3
96
36
164
149
149


4
44
66
29
83
24


5
112
171
36
176
164


6
133
7
153
113
64


7
111
178
0
91
80


8
13
145
12
96
178


9
57
67
19
8
159


10
136
49
38
39
137


11
118
137
101
164
2


12
7
167
91
45
29


13
58
19
174
127
106


14
19
53
5
52
4


15
54
59
27
7
162


16
101
68
162
161
161


17
42
52
156
47
144


18
43
23
140
178
117


19
41
42
171
27
1


20
114
78
83
57
6


21
1
97
95
97
26


22
36
102
64
114
9


23
16
96
72
21
11


24
5
95
80
12
157


25
46
179
56
9
79


26
51
93
88
71
72


27
64
105
85
44
90


28
70
92
53
101
88


29
49
77
9
70
92


30
40
73
47
68
69


31
37
107
125
25
10


32
94
103
107
18
8


33
6
83
76
88
38


34
71
89
100
102
81


35
67
100
74
6
66


36
50
28
65
103
123


37
55
64
103
67
75


38
39
24
79
73
28


39
32
18
57
10
59


40
20
31
78
94
5


41
45
22
92
17
114


42
21
32
90
92
119


43
25
60
126
33
132


44
47
71
26
16
77


45
59
94
70
1
70


46
60
70
16
86
35


47
10
30
43
53
44


48
68
1
84
29
43


49
63
26
104
15
60


50
62
12
25
40
94


51
2
3
66
93
87


52
33
40
28
139
20


53
29
16
59
107
40


54
4
39
6
72
130


55
3
15
67
49
76


56
23
35
106
51
96


57
15
4
8
38
53


58
27
51
1
30
34


59
18
88
3
76
99


60
66
62
15
74
37


61
31
14
96
48
67


62
22
90
99
34
93


63
9
45
81
5
138


64
26
29
10
82
56


65
11
6
11
126
51


66
0
63
54
85
142


67
28
47
102
78
7


68
30
56
87
23
13


69
34
5
115
105
30


70
8
34
98
36
78


71
17
8
23
31
68


72
173
37
75
64
127


73
142
17
82
43
39


74
108
61
143
58
113


75
78
21
41
4
42


76
74
33
49
99
47


77
65
0
33
54
98


78
97
43
58
2
12


79
149
20
73
22
14


80
159
44
44
81
46


81
93
11
21
98
32


82
163
2
37
20
33


83
122
69
63
60
55


84
150
10
122
13
86


85
137
57
68
35
50


86
99
48
69
104
57


87
127
46
18
32
49


88
126
13
51
65
18


89
158
25
34
135
91


90
117
9
31
50
105


91
154
55
42
84
0


92
86
65
35
106
41


93
128
27
20
90
129


94
130
58
22
11
71


95
164
101
52
37
17


96
95
134
86
143
102


97
90
174
93
3
89


98
100
99
77
24
74


99
177
159
45
41
104


100
120
166
30
14
58


101
80
81
13
19
121


102
160
72
55
61
54


103
129
104
46
79
126


104
161
162
17
89
143


105
76
79
48
77
103


106
72
146
24
59
3


107
98
130
50
26
139


108
85
150
2
87
62


109
174
127
40
62
97


110
169
76
89
28
45


111
104
153
32
0
31


112
143
74
61
100
36


113
84
106
14
63
134


114
171
113
105
75
82


115
157
163
7
66
109


116
178
176
39
69
73


117
82
131
97
56
16


118
151
111
60
42
65


119
113
108
71
95
63


120
168
112
169
172
108


121
89
165
179
152
21


122
141
75
170
108
27


123
179
121
128
120
133


124
88
124
155
167
107


125
145
91
178
175
61


126
52
170
139
109
110


127
73
172
131
142
100


128
125
129
120
163
84


129
139
140
141
173
116


130
79
120
130
168
52


131
75
86
158
110
118


132
144
160
112
153
125


133
165
155
117
150
23


134
162
157
138
166
122


135
87
164
127
138
83


136
48
85
147
117
19


137
134
84
142
125
85


138
77
80
151
141
48


139
107
123
116
130
95


140
131
175
136
179
124


141
138
154
176
116
15


142
109
161
167
115
101


143
92
152
154
151
111


144
115
147
172
162
177


145
12
41
132
171
179


146
140
158
149
169
165


147
153
132
145
155
145


148
56
138
144
146
163


149
91
114
108
158
112


150
103
148
161
122
172


151
116
143
137
177
169


152
61
136
175
136
154


153
172
125
150
134
173


154
167
173
118
112
136


155
123
116
165
157
152


156
119
169
168
145
155


157
135
98
133
118
141


158
105
139
173
160
175


159
124
115
111
121
160


160
155
118
119
111
151


161
38
119
152
170
153


162
102
151
124
119
140


163
156
141
109
148
166


164
166
135
148
174
128


165
132
177
160
144
120


166
110
87
177
129
131


167
81
128
146
131
146


168
148
110
121
137
176


169
147
149
166
154
170


170
170
168
113
140
158


171
175
144
123
123
174


172
106
122
163
132
167


173
83
109
110
156
150


174
146
82
157
124
147


175
121
54
159
165
168


176
176
142
134
133
171


177
53
133
135
128
156


178
69
156
129
159
115


179
152
117
114
147
148









Table 14 is the case in which group interleaving is performed using Equation 15 and π(j) is applied as an index of an input bit group, and Table 20 is the case in which group interleaving is performed using Equation 16 and π(j) is applied as an index of an output bit group. Therefore, Tables 14 and 20 have an inverse relationship with each other.
The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 24. Comparing the LDPC codeword of FIG. 24 and the LDPC codeword of FIG. 23 before group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.
That is, as shown in FIGS. 23 and 24, the groups of the LDPC codeword are arranged in order of bit group X0, bit group X1, . . . , bit group XNgroup−1 before being group-interleaved, and are arranged in an order of bit group Y0, bit group Y1, . . . , bit group YNgroup−1 after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 9 to 20.
The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange an order of bits in a same bit group by changing the order of the bits in the same bit group.
In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.
For example, as shown in FIG. 25, the group twist interleaver 123 may cyclic-shift bits included in the bit group Y1 to the right by 1 bit. In this case, the bits located in the 0th position, the 1st position, the 2nd position, . . . , the 358th position, and the 359th position in the bit group Y1 as shown in FIG. 25 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359th position before being cyclic-shifted is located in the front of the bit group Y1 and the bits located in the 0th position, the 1st position, the 2nd position, . . . , the 358th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.
In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.
For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y1 to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y2 to the right by 3 bits.
However, the group twist interleaver 123 may be omitted according to circumstances.
In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122.
The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bits group wise (or group units). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows, and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.
In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bits group wise. Specifically, the block interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.
Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bits group wise, dividing bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.
Here, the number of bit groups which are interleaved in bits group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group. In other words, the block interleaver 124 may determine bit groups which are to be interleaved in bits group wise considering at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group, interleave the corresponding bit groups in bits group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bits group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.
Meanwhile, interleaving bit groups in bits group wise (or in bit group units) means that bits included in a same bit group are written in a same column. In other words, the block interleaver 124, in case of bit groups which are interleaved in bits group wise, may not divide the bits included in the same bit groups and instead write the bits in the same column. However, in case of bit groups which are not interleaved in bits group wise, may divide bits in at least one of these bit groups or each of these bit groups and write the bits in different columns.
Accordingly, the number of rows constituting the first part is an integer multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in this bit group.
In addition, in all bit groups interleaved by the first part, bits included in a same bit group are written and interleaved in a same column of the first part, and in at least one group interleaved by the second part, bits are divided and written in at least two columns of the second part.
The interleaving method will be described later.
Meanwhile, the group twist interleaver 123 changes only an order of bits in a bit group and does not change the order of bit groups by interleaving. Accordingly, an order of bit groups to be block-interleaved by the block interleaver 124, that is, the order of the bit groups to be input to the block interleaver 124, may be determined by the group interleaver 122. For example, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 9 to 20.
As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bits group wise by using the plurality of columns each including the plurality of rows.
In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.
In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, and may perform interleaving.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bits group wise without dividing each of the plurality of columns into parts.
Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bits group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bits group wise in a row direction.
In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups, which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124, on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.
Hereinafter, the bit group located in the position after being interleaved by the group interleaver 122 will be referred to as group Yj.
For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R1 number of rows. In addition, it is assumed that the LDPC codeword is formed of Ngroup number of bit groups and the number of bit groups Ngroup is an integer multiple of C.
In this case, when the quotient obtained by dividing Ngroup number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A (=Ngroup/C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A (=Ngroup/C) number of bit groups on each column serially in the column direction and reading bits written on each column in the row direction.
For example, as shown in FIG. 26, the block interleaver 124 writes bits included in bit group Y0, bit group bit group YA−1 in the 1st column from the 1st row to the Rith row, writes bits included in bit group YA, bit group YA+1, . . . , bit group Y2A−1 in the 2nd column from the 1st row to the R1th row, . . . , and writes bits included in bit group YCA−A, bit group YCA−A+1, . . . , bit group YCA−1 in the column C from the 1st row to the Rith row. The block interleaver 124 may read the bits written in each row of the plurality of columns in the row direction.
Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC codeword in bits group wise.
However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may divide each column into two parts and interleave a part of the plurality of bit groups of the LDPC codeword in bits group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bits group wise, but interleaved by being divided according to the number of columns.
Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.
In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of rows and columns of the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the bit groups.
Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC codeword and the number of bits included in each bit group. For example, when an LDPC codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.
Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.
Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits constituting at least one bit group, which can be written in each column in bits group wise, from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.
In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits constituting at least some bit groups, which can be written in each of the plurality of columns in bits group wise, from among the plurality of bit groups of the LDPC codeword. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124. In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.
That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bits group wise, and the second part including the other rows.
Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each bit group.
In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.
Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.
That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups, which can be written in each of the plurality of columns in bits group wise among the plurality of bit groups constituting the LDPC codeword, in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups and writing these divided bits in the plurality of columns of the second part in the column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in the row direction.
In this case, the block interleaver 124 may interleave by dividing the other bit groups from among the plurality of bit groups constituting the LDPC codeword based on the number of columns constituting the block interleaver 124.
Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of the plurality of columns constituting the second part in the column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in the row direction.
That is, the block interleaver 124 may divide the bits included in the other bit groups among the plurality of bit groups of the LDPC codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in the column direction.
For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R1 number of rows. In addition, it is assumed that the LDPC codeword is formed of Ngroup number of bit groups, the number of bit groups Ngroup is not an integer multiple of C, and A×C+1=Ngroup (A is an integer greater than 0). In other words, it is assumed that when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.
In this case, as shown in FIGS. 27 and 28, the block interleaver 124 may divide each column into a first part including R1 number of rows and a second part including R2 number of rows. In this case, R1 may correspond to the number of bits included in bit groups which can be written in each column in bits group wise, and R2 may be R1 subtracted from the number of rows of each column.
That is, in the above-described example, the number of bit groups which can be written in each column in bits group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as A×M number.
In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bits group wise, that is, A number of bit groups, in the first part of each column in the column direction.
That is, as shown in FIGS. 27 and 28, the block interleaver 124 writes the bits included in each of bit group Y0, bit group Y1, . . . , group YA−1 in the 1st to R1th rows of the first part of the 1st column, writes bits included in each of bit group YA, bit group YA+1, . . . bit group Y2A−1 in the 1st to R1th rows of the first part of the 2nd column, . . . , writes bits included in each of bit group YCA−A, bit group YCA−A+1, . . . , bit group YCA−1 in the 1st to R1th rows of the first part of the column C.
As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bits group wise in the first part of each column in bits group wise.
In other words, in the above exemplary embodiment, the bits included in each of bit group (Y0), bit group (Y1), . . . , bit group (YA−1) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (YA), bit group (YA+1), . . . , bit group (Y2A−1) may not be divided and all of the bits may be written in the second column, . . . , and the bits included in each of bit group (YCA−A), bit group (YCA−A+1), . . . , group (YCA−1) may not be divided and all of the bits may be written in the C column. As such, bits included in a same bit group in all bit groups interleaved by the first part are written in a same column of the first part.
Thereafter, the block interleaver 124 divides the bits included in the groups other than the bit groups written in the first part of each column from among the plurality of bit groups, and writes these bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other bit groups such that a same number of bits are written in the second part of each column in the column direction. Here, an order of writing bits in the first part and the second part may be reversed. That is, bits may be written in the second part ahead of the first part according to an exemplary embodiment.
In the above-described example, since A×C+1=Ngroup, when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group YNgroup−1 of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group YNgroup−1 into C number of sub bit groups as shown in FIG. 27, and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (YNgroup−1) are divided by C) in the second part of each column serially.
The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.
That is, the block interleaver 124 writes the bits in the 1st to R2th rows of the second part of the 1st column, writes the bits in the 1st to R2th rows of the second part of the 2nd column, . . . , and writes the bits in the 1st to R2th rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 27.
That is, in the second part, bits constituting a bit group may not be written in a same column and may be written in a plurality of columns. In other words, in the above example, the last bit group (YNgroup−1) is formed of M number of bits and thus, the bits included in the last bit group (YNgroup−1) may be divided by M/C and written in each column. That is, the bits included in the last bit group (YNgroup−1) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.
Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.
In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second parts in the row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.
Specifically, referring to FIG. 28, the block interleaver 124 writes the bits from the 1st row of the second part in the 1st column to the 1st row of the second part in the column C, writes the bits from the 2nd row of the second part in the 1st column to the 2nd row of the second part in the column C, . . . , and writes the bits from the R2th row of the second part in the 1st column to the R2th row of the second part in the column C.
On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 27 and 28, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.
Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bits group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bits group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.
As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGS. 26 to 28.
In particular, in the case of FIG. 27, the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, Bit Error Rate (BER)/Frame Error Rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.
However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 28. That is, since the block interleaver 124 writes and read the bits included in the bit group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the bit group which does not belong to the first part is not changed and these bits are output to the modulator 130 serially. In this case, the bits included in the bit group which does not belong to the first part may be output serially to be mapped onto a modulation symbol.
In FIGS. 27 and 28, the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the number of bit groups constituting the LDPC codeword, the number of bits constituting each of the bit groups, the number of columns and rows of the block interleaver, the number of transmission antennas, etc.
The block interleaver 124 may have a configuration as shown in Tables 21 and 22 presented below:







TABLE 21







Nidpc = 64800














QPSK
16 QAM
64 QAM
256 QAM
1024 QAM
4096 QAM
















C
2
4
6
8
10
12


R1
32400
16200
10800
7920
6480
5400


R2
0
0
0
180
0
0
















TABLE 22







Nidpc = 16200














QPSK
16 QAM
64 QAM
256 QAM
1024 QAM
4096 QAM
















C
2
4
6
8
10
12


R1
7920
3960
2520
1800
1440
1080


R2
180
90
180
225
180
270









Herein, C (or NC) is the number of columns of the block interleaver 124, R1 is the number of rows constituting the first part in each column, and R2 is the number of rows constituting the second part in each column.
Referring to Tables 21 and 22, C is the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of a plurality of columns.
For example, when the length Nldpc of the LDPC codeword is 64800 and the modulation method is 1024-QAM, the block interleaver 124 is formed of 10 columns as the modulation order is 10 in the case of 1024-QAM, and each column is formed of as many rows as R1+R2=6480(=64800/10).
Meanwhile, referring to Tables 21 and 22, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R1 corresponds to the number of rows constituting each column, and R2 is 0. In addition, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R1 number of rows, and the second part formed of R2 number of rows.
When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol as shown in Tables 21 and 22, bits included in a same bit group are mapped onto a single bit of each modulation symbol.
For example, when Nldpc=64800 and the modulation method is 1024-QAM, the block interleaver 124 may be formed of 10 columns each including 6480 rows. In this case, the bits included in each of the plurality of bit groups are written in the 10 columns and bits written in the same row in each column are output serially. In this case, since 10 bits constitute a single modulation symbol in the modulation method of 1024-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1st column may be mapped onto a first bit of each modulation symbol.
Referring to Tables 21 and 22, the total number of rows of the block interleaver 124, that is, R1+R2, is Nldpc/C.
In addition, the number of rows of the first part, R1, is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └Ngroup/C┘×M, and the number of rows of the second part, R2, may be Nldpc/C−R1. Herein, └Ngroup/C┘ is the largest integer below Ngroup/C. Since R1 is an integer multiple of the number of bits included in each group, M, bits may be written in R1 in bit groups wise.
In addition, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns, it can be seen from Tables 21 and 22 that the block interleaver 124 interleaves by dividing each column into two parts.
Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is an integer multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns, each column is divided into two parts.
For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 21. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360 (=180) bit groups.
When the modulation method is 1024-QAM, the block interleaver 124 may be formed of 10 columns and each column may have 64800/10 (=6480) rows.
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/10 (=18), bits can be written in each column in bits group wise without dividing each column into two parts. That is, bits included in 18 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 18×360 (=6480) bits can be written in each column.
However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8 (=8100) rows.
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bits group wise.
In this case, since the bits should be written in the first part of each column in bits group wise, the number of bit groups which can be written in the first part of each column in bits group wise is 22 which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360 (=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.
The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100−7920 (=180) rows.
In this case, bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.
Specifically, since 22×8 (=176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180−176 (=4) (for example, a bit group Y176, bit group Y177, bit group Y178, and bit group Y179 from among bit group Y0, bit group Y1, bit group Y2, . . . , bit group Y178, and bit group Y179 constituting the LDPC codeword).
Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the bit groups constituting the LDPC codeword in the second part of each column serially.
That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y176 in the 1st row to the 180th row of the second part of the 1st column in the column direction, and may write the other 180 bits in the 1st row to the 180th row of the second part of the 2nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y177 in the 1st row to the 180th row of the second part of the 3rd column in the column direction, and may write the other 180 bits in the 1st row to the 180th row of the second part of the 4th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y178 in the 1st row to the 180th row of the second part of the 5th column in the column direction, and may write the other 180 bits in the 1st row to the 180th row of the second part of the 6th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y179 in the 1st row to the 180th row of the second part of the 7th column in the column direction, and may write the other 180 bits in the 1st row to the 180th row of the second part of the 8th column in the column direction.
Accordingly, bits included in a bit group which has not been written in the first part and remains are not written in a same column in the second part and may be divided and written in a plurality of columns.
Hereinafter, the block interleaver 124 of FIG. 22 according to an exemplary embodiment will be explained in detail with reference to FIG. 29.
In a group-interleaved LDPC codeword (v0, v1, . . . , vNldpc−1), Yj is continuously arranged like V={Y0, Y1, . . . YNgroup−1}.
The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 29. In this case, the block interleaver 124 divides a plurality of columns into the first part (Part 1) and the second part (Part 2) based on the number of columns of the block interleaver 124 and the number of bits of a bit group. In this case, in the first part, bits constituting a bit group may be written in a same column, and in the second part, bits constituting a bit group may be written in a plurality of columns (i.e. bits constituting a bit group may be written in at least two columns).
Specifically, input bits vi are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits vi are written serially into the block interleaver column-wise starting in the first part and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, each bit included in a same bit group in the first part may be mapped onto a single bit of each modulation symbol.
In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 23 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 23 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, Nr1 and the number of rows of the second part, Nr2, is equal to Nldpc/NC (herein, NC is the number of columns). In addition, since Nr1(=└Ngroup/Nc┘×360) is a multiple of 360, a multiple of bits groups may be written in the first part.










TABLE 23








Rows in Part 1 Nr1
Rows in Part 2 Nr2














N1dpc = 
N1dpc = 
N1dpc = 
N1dpc = 
Columns 


Modulation
64800
16200
64800
16200
Nc















QPSIK
32400
7920
0
180
2


16-QAM
16200
3960
0
90
4


64-QAM
10800
2520
0
180
6


256-QAM
7920
1800
180
225
8


1024-QAM
6480
1440
0
180
10


4096-QAM
5400
1080
0
270
12









Hereinafter, an operation of the block interleaver 124 will be explained in detail.
Specifically, as shown in FIG. 29, the input bit vi (0≦i<NC×Nr1) is written in an ri row of a ci column of the first part of the block interleaver 124. Herein, ci and ri are




  
    c
    i
  
  ⁢
  
    ⌊
    
      i
      
        N
        
          r
          ⁢
          
            
          
          ⁢
          1
        
      
    
    ⌋
  




and ri=(i mod Nr1), respectively.

In addition, the input bit vi (NC×Nr1≦i<Nldpc) is written in an ri row of ci column of the second part of the block interleaver 124. Herein, ci and ri satisfy




  
    c
    i
  
  =
  
    ⌊
    
      
        (
        
          i
          -
          
            
              N
              c
            
            ×
            
              N
              
                r
                ⁢
                
                  
                
                ⁢
                1
              
            
          
        
        )
      
      
        N
        
          r
          ⁢
          
            
          
          ⁢
          2
        
      
    
    ⌋
  




and ri=Nr1+{(i−NC×Nr1)mod Nr2}, respectively.

An output bit qj (0≦j<Nidpc) is read from a cj column of an rj row. Herein, rj and cj satisfy




  
    r
    j
  
  =
  
    ⌊
    
      j
      
        N
        c
      
    
    ⌋
  




and cj=(j mod NC), respectively.

For example, when the length Nldpc of the LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be (q0, q2, . . . ,q63357, q63358, q63359, q63360, q63361, . . . , q64799)=(v0, v7920, v15840, . . . , v47519, v55439, v63359, v63360, v63540, . . . , v64796). Here, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.
Hereinafter, an interleaving operation of the block interleaver 124 will be explained in detail.
The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bits group wise in the column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bits group wise in the row direction.
In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC codeword divided by the number of columns.
For example, when the modulation method is 1024-QAM, the block interleaver 124 may be formed of 10 columns. In this case, when the length Nldpc of the LDPC codeword is 64800, the number of rows is 6480 (=64800/10).
Hereinafter, a method for interleaving the plurality of bit groups in bits group wise by the block interleaver 124 will be explained in detail.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bits group wise.
For example, when the modulation method is 1024-QAM and the length Nldpc of the LDPC codeword is 64800, the block interleaver 124 may be formed of 10 columns each including 6480 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length Nldpc of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=10) when the modulation method is 1024-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.
As described above, when the number of bit groups of the LDPC codeword is an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may not divide each column into parts and may interleave by writing, in each of the plurality of columns serially in the column direction, the bits included in the bit groups which correspond to the quotient when the number of bits groups of the LDPC codeword is divided by the number of columns of the block interleaver 124, and reading each row of the plurality of columns in which the bits are written in the row direction.
For example, as shown in FIG. 30, the block interleaver 124 writes bits included in each of bit group Y0, bit group Y1, . . . , bit group Y17 in the 1st row to 6480th row of the first column, writes bits included in each of bit group Y18, bit group Y19, . . . , bit group Y35 in the 1st row to 6480th row of the second column, . . . , and writes the bits included in each of bit group Y162, bit group Y163, . . . , bit group Y179 in the 1st row to 6480th row of the 10th column. In addition, the block interleaver 124 may read the bits written in each row of the 10 columns serially in the row direction.
As described above, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups in bits group wise, and accordingly, bits belonging to a same bit group may be written in a same column.
As described above, the block interleaver 124 may interleave the plurality of bit groups of the LDPC codeword in the methods described above with reference to FIGS. 26 to 30.
When the number of columns constituting the block interleaver 124 has the same value as the modulation degree as in the above-described example, bits included in a same bit group may be mapped onto a single bit of each modulation symbol.
However, this is merely an example and bits included in a same bit group may be mapped onto two bits of each modulation symbol. In this case, the block interleaver 124 may have a configuration as shown in Tables 24 and 25 presented below. In this case, the number of columns constituting the block interleaver 124 may be a half of the modulation order as shown in Tables 24 and 25.







TABLE 24







Nidpc = 64800














QPSK
16 QAM
64 QAM
256 QAM
1024 QAM
4096 QAM
















C
2
4
6
8
10
12


R1
64800
32400
21600
16200
12960
10800


R2
0
0
0
0
0
0
















TABLE 25







Nidpc = 16200














QPSK
16 QAM
64 QAM
256 QAM
1024 QAM
4096 QAM
















C
2
4
6
8
10
12


R1
16200
7920
5400
3960
3240
2520


R2
0
180
0
90
0
180









Herein, C (or NO is the number of columns of the block interleaver 124, R1 is the number of rows constituting the first part in each column, and R2 is the number of rows constituting the second part in each column.
Referring to Tables 24 and 25, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R1 corresponds to the number of rows constituting each column, and R2 is 0. In addition, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the bit groups by dividing each column into the first part formed of R1 number of rows, and the second part formed of R2 number of rows.
When the number of columns of the block interleaver 124 is a half of the number of bits constituting the modulation symbol as shown in Tables 24 and 25, bits included in a same bit group may be mapped onto two bits of each modulation symbol.
For example, when Nldpc=64800 and the modulation method is 1024-QAM, the block interleaver 124 may be formed of five (5) columns each including 12960 rows. In this case, a plurality of bit groups constituting an LDPC codeword are written in the five (5) columns in bits group wise and bits written in the same row in respective columns are output serially. In this case, since 10 bits constitute a single modulation symbol in the modulation method of 1024-QAM, bits output from the two rows constitute a single modulation symbol. Accordingly, bits included in a same bit group, that is, bits output from one column, may be mapped onto two bits of a single modulation symbol. For example, bits included in a bit group written in the first column may be mapped onto bits existing in two certain positions of a single modulation symbol.
Referring back to FIG. 19, the modulator 130 maps the interleaved LDPC codeword onto a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.
In this case, the modulator 130 may generate a modulation symbol using bits included in each of a plurality of bit groups.
In other words, as described above, bits included in different bit groups may be written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by mapping bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol may belong to a different group.
For example, it is assumed that a modulation symbol is formed of C number of bits. In this case, bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol formed of C number of bits may belong to C number of different groups.
Hereinbelow, the above feature will be described in greater detail.
First, the modulator 130 may demultiplex the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.
A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).
For example, as shown in FIG. 31, the demultiplexer (not shown) receives an LDPC codeword Q=(q0, q1, q2, . . . ) output from the interleaver 120, outputs the received LDPC codeword bits to a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.
Herein, the number of substreams, Nsubstreams, may be equal to the number of bits constituting a modulation symbol, ηMOD. Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting the modulation symbol (that is, a modulation order).
ηMOD may vary according to a modulation method and then number of cells generated may vary according to the length Nldpc of the LDPC codeword as shown in Table 26.










TABLE 26







Number of output
Number of output




data cells for N1dcp =
data cells for N1dcp =


Modulation mode
ηMOD
64 800
16 200


















QPSK
2
32 400
8 100


16-QAM
4
16 200
4 050


64-QAM
6
10 800
2 700


256-QAM
8
 8 100
2 025


1024-QAM
10
 6 480
1 620









In this case, bits having a same index in each of the plurality of substreams may constitute a same cell. Accordingly, cells may be configured like (y0,0, y1,0, . . . , yηMOD−1,0)=(q0, q1, qηMOD−1), (y0,1, y1,1, . . . , yηMOD−1,1)=(qηMOD, qηMOD+1, . . . , q2×ηMOD−1), . . . .
As described above, the number of substreams, Nsubstreams, is equal to the number of bits constituting a modulation symbol, ηMOD, and the number of bits constituting each cell may be equal to the number of bits constituting the modulation symbol.
The demultiplexer (not shown) may demultiplex input LDPC codeword bits in various methods. That is, the demultiplexer (not shown) may change an order of the LDPC codeword bits and output the bits to each of the plurality of substreams, or may output the bits to each of the plurality of streams serially without changing the order of the LDPC codeword bits. These operations may be determined according to the number of columns used for interleaving in the block interleaver 124.
Specifically, when the block interleaver 124 includes as many columns as half of the number of bits constituting the modulation symbol, the demultiplexer (not shown) may change the order of the input LDPC codeword bits and output the bits to each of the plurality of substreams. An example of a method for changing the order is illustrated in Table 27 presented below:








TABLE 27







Modulation format
QPSM









input bit
0
1


di mod Nsubstreams




ouput bit-number
0
1








Modulation format
16 QAM











input bit
0
1
2
3


di mod Nsubstreams






ouput bit-number
0
2
1
3








Modulation format
64 QAM













input bit
0
1
2
2
4
5


di mod Nsubstreams








ouput bit-number
0
3
1
4
2
5








Modulation format
256 QAM















input bit
0
1
2
3
4
5
6
7


di mod Nsubstreams










ouput bit-number
0
4
1
5
2
6
3
7








Modulation format
1024 QAM

















input bit
0
1
2
3
4
5
6
7
8
9


di mod Nsubstreams












ouput bit-number
0
5
1
6
2
7
3
5
4
9








Modulation format
4096 QAM



















input bit
0
1
2
3
4
5
6
7
8
9
10
11


di mod Nsubstreams














ouput bit-number
0
6
1
7
2
6
3
9
4
10
5
11









According to Table 27, when the modulation method is 1024-QAM for example, the number of substreams is 10 since the number of bits constituting a modulation symbol is 10 in the case of 1024-QAM. In this case, the demultiplexer (not shown) may output, from among the serially input bits, bits with an index i satisfying i mod 10=0 to the 0th substream, bits with an index i satisfying i mod 10=1 to the 5th substream, bits with an index i satisfying i mode 10=2 to the 1st substream, bits with an index i satisfying i mode 10=3 to the 6th substream, bits with an index i satisfying i mode 10=4 to the 2nd substream, bits with an index i satisfying i mode 10=5 to the 7th substream, bits with an index i satisfying i mode 10=6 to the 3rd substream, bits with an index i satisfying i mode 10=7 to the 8th substream, bits with an index i satisfying i mode 10=8 to the 4th substream, and bits with an index i satisfying i mode 10=9 to the 9th substream.
Accordingly, the LDPC codeword bits input to the demultiplexer (not shown), (q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, . . . ), may be output as cells like (y0,0, y1,0, y2,0, y3,0, y4,0, y5,0, y6,0, y7,0, y8,0, y9,0)=(q0, q5, q1, q6, q2, q7, q3, q8, q4, q9), (y0,1, y1,1, y2,1, y3,1, y4,1, y5,1, y6,1, y7,1, y8,1, y9,1)=(q10, q15, q11, q16, q12, q17, q13, q18, q14, q19) . . . .
When the block interleaver 124 includes the same number of columns as the number of bits constituting a modulation symbol, the demultiplexer (not shown) may output the input LDPC codeword bits to each of the plurality of streams serially without changing the order of the bits. That is, as shown in FIG. 31, the demultiplexer (not shown) may output the input LDPC codeword bits (q0, q1, q2, . . . ) to each of the substreams serially, and accordingly, each cell may be configured as (y0,o, y1,0, . . . , yηMOD−1,0)=(q0, q1, . . . , qηMOD−1), (y0,1, y1,1, . . . , yηMOD−1,1)=(qηMOD, qηMOD+1, . . . , q2+ηMOD−1), . . . .
For example, when the modulation method is 1024-QPSK, the number of bits constituting a modulation symbol, ηMOD, is 10 and thus the number of substreams, Nsubstreams, is 10, and cells may be configured like (y0,o, y1,0, y2,0, y3,0, y4,0, y5,0, y6,0, y7,0, y8,0, y9,0)=(q0, q1, q2, q3, q4, q5, q6, q7, q8, q9), (y0,1, y1,1, y2,1, y3,1, y4,1, y5,1, y6,1, y7,1, y8,1, y9,1)=(q10, q11, q12, q13, q14, q15, q16, q17, q18, q19), . . . (y0,2, y1,2, y2,2, y3,2, y4,2, y5,2, y6,2, y7,2, y8,2, y9,2)=(q20, q21, q22, q23, q24, q25, q26, q27, q28, q29)
In the above-described example, the demultiplexer (not shown) may output the input LDPC codeword bits to each of the plurality of substreams serially without changing the order of the LDPC codeword bits. However, this is merely an example. According to an exemplary embodiment, when the block interleaver 124 includes the same number of columns as the number of bits of the modulation symbol, the demultiplexer (not shown) may be omitted.
The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols. However, when the demultiplexer (not shown) is omitted as described, the modulator 130 may map the LDPC codeword bits output from the interleaver 120, that is, the block-interleaved LDPC codeword bits, onto the modulation symbols.
Specifically, the modulator 130 may modulate the bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the number of bits constituting the modulation symbol, ηMOD, may be 2, 4, 6, 8, 10 and 12, respectively.
In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting a modulation symbol, the modulator 130 may generate the modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, a modulation symbol corresponds to a constellation point on the constellation.
However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by mapping ηMOD number of bits onto the constellation points serially according to a modulation method.
The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method. For example, the modulator 130 may modulate bits output from the demultiplexer (not shown) in various modulation methods such as non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024-QAM, non-uniform 4096-QAM, etc.
In the non-uniform constellation method, once a constellation point of the first quadrant is defined, constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set is −conj(X) in the case of the second quadrant, is conj(X) in the case of the third quadrant, and is −(X) in the case of the fourth quadrant.
That is, once the first quadrant is defined, the other quadrants may be expressed as follows:

    
    
        1 Quarter (first quadrant)=X
        2 Quarter (second quadrant)=−conj(X)
        3 Quarter (third quadrant)=conj(X)
        4 Quarter (fourth quadrant)=−X
    
    


Specifically, when the non-uniform M-QAM is used, M number of constellation points may be defined as z={z0, z1, zM−1}. In this case, when the constellation points existing in the first quadrant are defined as {x0, x1, x2, . . . , xM/4−1}, z may be defined as follows:

    
    
        from z0 to zM/4−1=from x0 to xM/4 
        from zM/4 to z2×M/4−1=−conj (from x0 to xM/4)
        from z2×M/4 to z3×M/4−1=conj (from x0 to xM/4)
        from z3×M/4 to z4×M/4−1=−(from x0 to xM/4)
    
    


Accordingly, the modulator 130 may map the bits [y0, . . . , ym−1] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto zL having an index of




  L
  =
  
    
      ∑
      
        i
        =
        0
      
      
        m
        -
        1
      
    
    ⁢
    
      
        (
        
          
            y
            1
          
          ×
          
            2
            
              m
              -
              1
            
          
        
        )
      
      .
    
  




An example of the constellation defined according to the non-uniform 1024-QAM method may be expressed as in Table 28 presented below when the code rate is 6/15, 8/15, 10/15, 12/15. In this case, the constellation point of the first quadrant may be defined with reference to Table 28, and the constellation points in the other three quadrants may be defined in the above-described method.











TABLE 28





Label
CR 6/15
CR 8/15
CR 10/15
CR 12/15


(int.)
Constellation
Constellation
Constellation
Constellation



















0
1.5031 + 1.5031i
1.4800 + 1.4800i
1.4377 + 1.4377i
1.3675 + 1.3675i


1
1.5031 + 1.2286i
1.4800 + 1.2281i
1.4377 + 1.2232i
1.3675 + 1.1917i


2
1.2286 + 1.5031i
1.2281 + 1.4800i
1.2232 + 1.4377i
1.1917 + 1.3675i


3
1.2286 + 1.2286i
1.2281 + 1.2281i
1.2232 + 1.2232i
1.1917 + 1.1917i


4
1.5031 + 0.9418i
1.4800 + 0.9212i
1.4377 + 0.9302i
1.3675 + 0.9386i


5
1.5031 + 1.0048i
1.4800 + 1.0349i
1.4377 + 1.0579i
1.3675 + 1.0529i


6
1.2286 + 0.9418i
1.2281 + 0.9212i
1.2232 + 0.9302i
1.1917 + 0.9386i


7
1.2286 + 1.0048i
1.2281 + 1.0349i
1.2232 + 1.0579i
1.1917 + 1.0529i


8
0.9418 + 1.5031i
0.9212 + 1.4800i
0.9302 + 1.4377i
0.9386 + 1.3675i


9
0.9418 + 1.2286i
0.9212 + 1.2281i
0.9302 + 1.2232i
0.9386 + 1.1917i


10
1.0048 + 1.5031i
1.0349 + 1.4800i
1.0579 + 1.4377i
1.0529 + 1.3675i


11
1.0048 + 1.2286i
1.0349 + 1.2281i
1.0579 + 1.2232i
1.0529 + 1.1917i


12
0.9418 + 0.9418i
0.9212 + 0.9212i
0.9302 + 0.9302i
0.9386 + 0.9386i


13
0.9418 + 1.0048i
0.9212 + 1.0349i
0.9302 + 1.0579i
0.9386 + 1.0529i


14
1.0048 + 0.9418i
1.0349 + 0.9212i
1.0579 + 0.9302i
1.0529 + 0.9386i


15
1.0048 + 1.0048i
1.0349 + 1.0349i
1.0579 + 1.0579i
1.0529 + 1.0529i


16
1.5031 + 0.6097i
1.4800 + 0.5810i
1.4377 + 0.5505i
1.3675 + 0.5763i


17
1.5031 + 0.6072i
1.4800 + 0.5872i
1.4377 + 0.6150i
1.3675 + 0.6531i


18
1.2286 + 0.6097i
1.2281 + 0.5810i
1.2232 + 0.5505i
1.1917 + 0.5763i


19
1.2286 + 0.6072i
1.2281 + 0.5872i
1.2232 + 0.6150i
1.1917 + 0.6531i


20
1.5031 + 0.7196i
1.4800 + 0.7604i
1.4377 + 0.8066i
1.3675 + 0.8324i


21
1.5031 + 0.7113i
1.4800 + 0.7213i
1.4377 + 0.7158i
1.3675 + 0.7417i


22
1.2286 + 0.7196i
1.2281 + 0.7604i
1.2232 + 0.8066i
1.1917 + 0.8324i


23
1.2286 + 0.7113i
1.2281 + 0.7213i
1.2232 + 0.7158i
1.1917 + 0.7417i


24
0.9418 + 0.6097i
0.9212 + 0.5810i
0.9302 + 0.5505i
0.9386 + 0.5763i


25
0.9418 + 0.6072i
0.9212 + 0.5872i
0.9302 + 0.6150i
0.9386 + 0.6531i


26
1.0048 + 0.6097i
1.0349 + 0.5810i
1.0579 + 0.5505i
1.0529 + 0.5763i


27
1.0048 + 0.6072i
1.0349 + 0.5872i
1.0579 + 0.6150i
1.0529 + 0.6531i


28
0.9418 + 0.7196i
0.9212 + 0.7604i
0.9302 + 0.8066i
0.9386 + 0.8324i


29
0.9418 + 0.7113i
0.9212 + 0.7213i
0.9302 + 0.7158i
0.9386 + 0.7417i


30
1.0048 + 0.7196i
1.0349 + 0.7604i
1.0579 + 0.8066i
1.0529 + 0.8324i


31
1.0048 + 0.7113i
1.0349 + 0.7213i
1.0579 + 0.7158i
1.0529 + 0.7417i


32
0.6097 + 1.5031i
0.5810 + 1.4800i
0.5505 + 1.4377i
0.5763 + 1.3675i


33
0.6097 + 1.2286i
0.5810 + 1.2281i
0.5505 + 1.2232i
0.5763 + 1.1917i


34
0.6072 + 1.5031i
0.5872 + 1.4800i
0.6150 + 1.4377i
0.6531 + 1.3675i


35
0.6072 + 1.2286i
0.5872 + 1.2281i
0.6150 + 1.2232i
0.6531 + 1.1917i


36
0.6097 + 0.9418i
0.5810 + 0.9212i
0.5505 + 0.9302i
0.5763 + 0.9386i


37
0.6097 + 1.0048i
0.5810 + 1.0349i
0.5505 + 1.0579i
0.5763 + 1.0529i


38
0.6072 + 0.9418i
0.5872 + 0.9212i
0.6150 + 0.9302i
0.6531 + 0.9386i


39
0.6072 + 1.0048i
0.5872 + 1.0349i
0.6150 + 1.0579i
0.6531 + 1.0529i


40
0.7196 + 1.5031i
0.7604 + 1.4800i
0.8066 + 1.4377i
0.8324 + 1.3675i


41
0.7196 + 1.2286i
0.7604 + 1.2281i
0.8066 + 1.2232i
0.8324 + 1.1917i


42
0.7113 + 1.5031i
0.7213 + 1.4800i
0.7158 + 1.4377i
0.7417 + 1.3675i


43
0.7113 + 1.2286i
0.7213 + 1.2281i
0.7158 + 1.2232i
0.7417 + 1.1917i


44
0.7196 + 0.9418i
0.7604 + 0.9212i
0.8066 + 0.9302i
0.8324 + 0.9386i


45
0.7196 + 1.0048i
0.7604 + 1.0349i
0.8066 + 1.0579i
0.8324 + 1.0529i


46
0.7113 + 0.9418i
0.7213 + 0.9212i
0.7158 + 0.9302i
0.7417 + 0.9386i


47
0.7113 + 1.0048i
0.7213 + 1.0349i
0.7158 + 1.0529i
0.7417 + 1.0579i


48
0.6097 + 0.6097i
0.5810 + 0.5810i
0.5505 + 0.5505i
0.5763 + 0.5763i


49
0.6097 + 0.6072i
0.5810 + 0.5872i
0.5505 + 0.6150i
0.5763 + 0.6531i


50
0.6072 + 0.6097i
0.5872 + 0.5810i
0.6150 + 0.5505i
0.6531 + 0.5763i


51
0.6072 + 0.6072i
0.5872 + 0.5872i
0.6150 + 0.6150i
0.6531 + 0.6531i


52
0.6097 + 0.7196i
0.5810 + 0.7604i
0.5505 + 0.8066i
0.5763 + 0.8324i


53
0.6097 + 0.7113i
0.5810 + 0.7213i
0.5505 + 0.7158i
0.5763 + 0.7417i


54
0.6072 + 0.7196i
0.5872 + 0.7604i
0.6150 + 0.8066i
0.6531 + 0.8324i


55
0.6072 + 0.7113i
0.5872 + 0.7213i
0.6150 + 0.7158i
0.6531 + 0.7417i


56
0.7196 + 0.6097i
0.7604 + 0.5810i
0.8066 + 0.5505i
0.8324 + 0.5763i


57
0.7196 + 0.6072i
0.7604 + 0.5872i
0.8066 + 0.6150i
0.8324 + 0.6531i


58
0.7113 + 0.6097i
0.7213 + 0.5810i
0.7158 + 0.5505i
0.7417 + 0.5763i


59
0.7113 + 0.6072i
0.7213 + 0.5872i
0.7158 + 0.6150i
0.7417 + 0.6531i


60
0.7196 + 0.7196i
0.7604 + 0.7604i
0.8066 + 0.8066i
0.8324 + 0.8324i


61
0.7196 + 0.7113i
0.7604 + 0.7213i
0.8066 + 0.7158i
0.8324 + 0.7417i


62
0.7113 + 0.7196i
0.7213 + 0.7604i
0.7158 + 0.8324i
0.7417 + 0.8066i


63
0.7113 + 0.7113i
0.7213 + 0.7213i
0.7158 + 0.7158i
0.7417 + 0.7417i


64
1.5031 + 0.1275i
1.4800 + 0.0773i
1.4377 + 0.0596i
1.3675 + 0.0354i


65
1.5031 + 0.1276i
1.4800 + 0.0773i
1.4377 + 0.0642i
1.3675 + 0.0921i


66
1.2286 + 0.1275i
1.2281 + 0.0773i
1.2232 + 0.0596i
1.1917 + 0.0354i


67
1.2286 + 0.1276i
1.2281 + 0.0773i
1.2232 + 0.0642i
1.1917 + 0.0921i


68
1.5031 + 0.1295i
1.4800 + 0.1614i
1.4377 + 0.1766i
1.3675 + 0.2185i


69
1.5031 + 0.1294i
1.4800 + 0.1614i
1.4377 + 0.1669i
1.3675 + 0.1602i


70
1.2286 + 0.1295i
1.2281 + 0.1614i
1.2232 + 0.1766i
1.1917 + 0.2185i


71
1.2286 + 0.1294i
1.2281 + 0.1614i
1.2232 + 0.1669i
1.1917 + 0.1602i


72
0.9418 + 0.1275i
0.9212 + 0.0773i
0.9302 + 0.0596i
0.9386 + 0.0354i


73
0.9418 + 0.1276i
0.9212 + 0.0773i
0.9302 + 0.0642i
0.9386 + 0.0921i


74
1.0048 + 0.1275i
1.0349 + 0.0773i
1.0579 + 0.0596i
1.0529 + 0.0354i


75
1.0048 + 0.1276i
1.0349 + 0.0773i
1.0579 + 0.0642i
1.0529 + 0.0921i


76
0.9418 + 0.1295i
0.9212 + 0.1614i
0.9302 + 0.1766i
0.9386 + 0.2185i


77
0.9418 + 0.1294i
0.9212 + 0.1614i
0.9302 + 0.1669i
0.9386 + 0.1602i


78
1.0048 + 0.1295i
1.0349 + 0.1614i
1.0579 + 0.1766i
1.0529 + 0.2185i


79
1.0048 + 0.1294i
1.0349 + 0.1614i
1.0579 + 0.1669i
1.0529 + 0.1602i


80
1.5031 + 0.3666i
1.4800 + 0.4163i
1.4377 + 0.4471i
1.3675 + 0.4947i


81
1.5031 + 0.3675i
1.4800 + 0.4159i
1.4377 + 0.4043i
1.3675 + 0.4264i


82
1.2286 + 0.3666i
1.2281 + 0.4163i
1.2232 + 0.4471i
1.1917 + 0.4947i


83
1.2286 + 0.3675i
1.2281 + 0.4159i
1.2232 + 0.4043i
1.1917 + 0.4264i


84
1.5031 + 0.3424i
1.4800 + 0.3086i
1.4377 + 0.2868i
1.3675 + 0.2910i


85
1.5031 + 0.3431i
1.4800 + 0.3085i
1.4377+ 0.3091i
1.3675 + 0.3530i


86
1.2286 + 0.3424i
1.2281 + 0.3086i
1.2232 + 0.2868i
1.1917 + 0.2910i


87
1.2286 + 0.3431i
1.2281 + 0.3085i
1.2232 + 0.3091i
1.1917 + 0.3530i


88
0.9418 + 0.3666i
0.9212 + 0.4163i
0.9302 + 0.4471i
0.9386 + 0.4947i


89
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90
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91
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92
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93
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94
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95
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96
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97
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98
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99
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100
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101
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102
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103
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104
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105
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106
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107
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108
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109
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110
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111
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112
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113
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114
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115
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116
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117
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118
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119
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120
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121
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122
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123
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124
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125
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126
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127
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128
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129
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130
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131
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132
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133
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134
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135
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136
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137
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138
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139
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140
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141
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142
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143
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144
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145
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146
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147
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148
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149
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150
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151
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152
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153
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154
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155
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156
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157
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158
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159
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160
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161
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162
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163
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164
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165
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166
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167
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168
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169
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170
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171
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172
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173
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174
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175
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176
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177
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178
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179
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180
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181
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182
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183
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184
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185
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186
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187
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188
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189
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190
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191
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192
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193
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194
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195
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196
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197
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198
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199
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200
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201
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202
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203
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204
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205
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206
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207
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208
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209
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210
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211
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212
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213
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214
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215
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216
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217
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218
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219
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220
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221
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222
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223
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224
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225
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226
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227
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228
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229
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230
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231
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232
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233
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234
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235
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236
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237
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238
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239
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240
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241
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242
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243
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244
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245
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246
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247
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248
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0.2910 + 0.4947i


249
0.3424 + 0.3675i
0.3086 + 0.4159i
0.2868 + 0.4043i
0.2910 + 0.4264i


250
0.3431 + 0.3666i
0.3085 + 0.4163i
0.3091 + 0.4471i
0.3530 + 0.4947i


251
0.3431 + 0.3675i
0.3085 + 0.4159i
0.3091 + 0.4043i
0.3530 + 0.4264i


252
0.3424 + 0.3424i
0.3086 + 0.3086i
0.2868 + 0.2868i
0.2910 + 0.2910i


253
0.3424 + 0.3431i
0.3086 + 0.3085i
0.2868 + 0.3091i
0.2910 + 0.3530i


254
0.3431 + 0.3424i
0.3085 + 0.3086i
0.3091 + 0.2868i
0.3530 + 0.2910i


255
0.3431 + 0.3431i
0.3085 + 0.3085i
0.3091 + 0.3091i
0.3530 + 0.3530i









Table 28 shows an example of constellation defined according to the non-uniform 1024-QAM. However, this is merely an example. The constellation points may be defined variously in the non-uniform 1024-QAM. In addition, the constellation points may be defined variously in the other modulation methods such as non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 4096-QAM, etc.
The interleaving is performed in the above-described method for the following reasons.
Specifically, when LDPC codeword bits are mapped onto a modulation symbol, the bits may have different reliability (that is, different receiving performance or different probability of reception) according to where the bits are mapped in the modulation symbol. The LDPC codeword bits may have different codeword characteristics according to the configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the column of the parity check matrix, that is, the column degree.
Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits having a specific codeword characteristic onto specific bits in the modulation symbol by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.
For example, it is assumed that the encoder 110 generates an LDPC codeword formed of 64800 bits (Nldpc=64800) by LDPC encoding using a code rate of 6/15, and the modulator 130 uses the non-uniform 1024-QAM modulation method corresponding to the code rate of 6/15 based on Table 28.
In this case, the group interleaver 122 may perform group-interleaving using Equation 15 and Table 9 (or Equation 16 and Table 15). Accordingly, the LDPC codeword formed of bit groups X0 to X179 is interleaved by the group interleaver 122 and the group interleaver 122 may output the bit groups in the order of X66, X21, X51, . . . , X116, X123.
In this case, the number of columns constituting the block interleaver 124 may be 10 and each column may be formed of 6480 (=360×18) rows. That is, the number of rows of the first part may be 6480 and the number of rows of the second part may be 0.
Accordingly, from among the 180 groups constituting the LDPC codeword, 18 bit groups (X66, X21, X51, X55, X54, X24, X33, X12, X70, X63, X47, X65, X145, X8, X0, X57, X23, X71) may be inputted to the first part of the 1st column of the block interleaver 124, 18 bit groups (X59, X14, X40, X42, X62, X56, X2, X43, X64, X58, X67, X53, X68, X61, X39, X52, X69, X1) may be inputted to the first part of the 2nd column of the block interleaver 124, 18 bit groups (X22, X31, X161, X38, X30, X19, X17, X18, X4, X41, X25, X44, X136, X29, X36, X26, X126, X177) may be inputted to the first part of the 3rd column of the block interleaver 124, 18 bit groups (X15, X37, X148, X9, X13, X45, X46, X152, X50, X49, X27, X77, X60, X35, X48, X178, X28, X34) may be inputted to the first part of the 4th column of the block interleaver 124, 18 bit groups (X106, X127, X76, X131, X105, X138, X75, X130, X101, X167, X117, X173, X113, X108, X92, X135, X124, X121) may be inputted to the first part of the 5th column of the block interleaver 124, 18 bit groups (X97, X149, X143, X81, X32, X96, X3, X78, X107, X86, X98, X16, X162, X150, X111, X158, X172, X139) may be inputted to the first part of the 6th column of the block interleaver 124, 18 bit groups (X74, X142, X166, X7, X5, X119, X20, X144, X151, X90, X11, X156, X100, X175, X83, X155, X159, X128) may be inputted to the first part of the 7th column of the block interleaver 124, 18 bit groups (X88, X87, X93, X103, X94, X140, X165, X6, X137, X157, X10, X85, X141, X129, X146, X122, X73, X112) may be inputted to the first part of the 8th column of the block interleaver 124, 18 bit groups (X132, X125, X174, X169, X168, X79, X84, X118, X179, X147, X91, X160, X163, X115, X89, X80, X102, X104) may be inputted to the first part of the 9th column of the block interleaver 124, and 18 bit groups (X134, X82, X95, X133, X164, X154, X120, X110, X170, X114, X153, X72, X109, X171, X176, X99, X116, X123) may be inputted to the first part of the 10th column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may output the inputted bits serially without changing the order of bits.
Accordingly, one bit included in each of the bit groups X66, X59, X22, X15, X106, X97, X74, X88, X132, and X134 may constitute one modulation symbol.
As described above, since a specific bit is mapped onto a specific bit in a modulation symbol through interleaving, a receiver side can achieve high receiving performance and high decoding performance.
That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, the receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance are not received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial receiving performance is excellent, and thus, overall performance is also excellent. However, when many bits showing poor decoding performance are received, error propagation may occur.
Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC codeword bits and reliability of the bits of the modulation symbol, and is transmitted to the receiver side. Accordingly, the receiver side can achieve both the high receiving performance and the high decoding performance.
The above-described group interleaving and block interleaving is merely an example. In addition to the above-described method, other methods for making one bit included in each of the bit groups X66, X59, X22, X15, X106, X97, X74, X88, X132, and X134 constitute one modulation symbol are covered by the inventive concept.
Hereinafter, a method for determining π(j), which is a parameter used for group interleaving, according to various exemplary embodiments, will be explained. First, criteria to be considered are as follows:
Criterion 1) A different interleaving order is used according to a modulation method and a code rate.
Criterion 2) A performance characteristic for each bit group of the LDPC codeword and a performance characteristic for each bit of a modulation symbol should be considered simultaneously.
For example, in the case of the LDPC codeword, the leftmost bits may be good in performance, and the leftmost bits of the modulation symbol may be good in performance. That is, the relative size of receiving performance P(yi) of each of the 10 bits constituting the non-uniform 1024-QAM, y0, y1, y2, y3, y4, y5, y6, y7, y8, and y9, has a relationship of P(y0)=P(y1)≧P(y2)=P(y3)≧P(y4)=P(y5)≧P(y6)=P(y7)≧P(y8)=P(y9)
Therefore, when the length of the LDPC codeword is 64800 and the non-uniform 1024-QAM (or 1024-NUC) is used, onto which bits from among the 10 bits of the non-uniform 1024-QAM the 180 LDPC bit groups are mapped is determined by considering the characteristics of the LDPC codeword and the modulation method simultaneously. In this case, a case having the best estimated performance is determined using a Density evolution method.
That is, a plurality of cases in which 180 bit groups are mapped onto the 10 bits may be considered and a theoretically estimated threshold value may be calculated by applying the density evolution method to each case. When an LDPC code is transmitted as an SNR value, an error probability is 0 in an SNR area greater than the threshold value. Therefore, excellent performance can be guaranteed when the LDPC code is transmitted in the method as in the case of a small threshold value from among the plurality of cases for mapping. However, the method for designing the interleaver 120 based on the density evolution is a theoretical method. Therefore, the interleaver 120 may be designed by verifying the encoding performance based on a really designed parity check matrix and based on a cyclic distribution, in addition to the theoretical method of density evolution.
Meanwhile, when the 180 bits groups are mapped onto the 10 bits, bits groups related to the rows having the same degree in the parity check matrix are grouped into a same group, and, onto which bits from among the 10 1024-QAM bits some of the groups in each group are mapped is determined.
For example, it is assumed that the parity check matrix of the LDPC codeword includes rows having the degrees of 26, 3, and 2, and 14 bit groups, 118 bit groups, and 36 bit groups are related to the rows having the degrees 26, 3, and 2, respectively,
In the case of the non-uniform 1024-QAM method, two bits have the same receiving performance (that is, the same probability of reception) (that is, P(y0)=P(y1), P(y2)=P(y3), P(y4)=P(y5), P(y6)=P(y7), P(y8)=P(y9)), and thus the bit groups may be mapped onto five (5) bits. Therefore, the number of cases where the bit groups are mapped onto the five (5) bits may be expressed as follows:












modulated bits
degree
Number of cases where bits are mapped

















y0, y1
26
14Cx1



3
118Cw1



2
36Cz1


y2, y3
26
14Cx2



3
118Cw2



2
36Cz2


y4, y5
26
14Cx3



3
118Cw3



2
36Cz3


y6, y7
26
14Cx4



3
118Cw4



2
36Cz4


y8, y9
26
14Cx5



3
118Cw5



2
36Cz5


sum

180









That is, regarding the bit groups to be mapped onto y0 and y1, the number of cases where x1 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w1 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z1 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx1+118Cw1+36Cz1.
In addition, regarding the bit groups to be mapped onto y2 and y3, the number of cases where x2 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w2 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z2 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx2+118Cw2+36Cz2.
In addition, regarding the bit groups to be mapped onto y4 and y5, the number of cases where x3 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w3 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z3 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx3+118Cw3+36Cz3.
In addition, regarding the bit groups to be mapped onto y6 and y7, the number of cases where x4 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w4 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z4 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx4+118Cw4+36Cz4.
In addition, regarding the bit groups to be mapped onto y8 and y9, the number of cases where x5 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w5 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z5 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx5+118Cw5+36Cz5.
In this case, x1+x2+x3+x4+x5=14, w1+w2+w3+w4+w5=118, and z1+z2+z3+z4+z5=36.
However, since there are a large number of cases in the above example, it may be difficult to estimate performance for each case through density evolution.
Therefore, the number of cases may be calculated by reducing the number of kinds of receiving performance, and then performance for each case may be estimated through density evolution.
For example, on the assumption that the probability of reception of y0, y1, y2, and y3 is the same and the probability of reception of y4, y5, y6, y7, y8, and y9 is the same as shown in a table presented below, the number of cases where the bit groups are mapped onto three (3) bits may be calculated.












modulated bits
degree
Number of cases where bits are mapped

















y0, y1, y2, y3
23
14Cx1



3
118Cw1



2
36Cz1


y4, y5, y6, y7, y8, y9
26
14Cx2



3
118Cw2



2
36Cz2


sum

180









That is, regarding the bit groups to be mapped onto y0, y1, y2, y3, the number of cases where x1 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w1 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z1 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx1+118Cw1+36Cz1.
In addition, regarding the bit groups to be mapped onto y4, y5, y6, y7, y8, y9, the number of cases where x2 number of bit groups are selected from among the bit groups related to the rows having the degree of 26, w2 number of bit groups are selected from among the bit groups related to the rows having the degree of three (3), and z2 number of bit groups are selected from among the bit groups related to the rows having the degree of two (2) may be 14Cx2+118Cw2+36Cz2.
In this case, x1+x2=14, w1+w2=118, and z1+z2=36.
Thereafter, after the performance for each case is estimated through density devolution, the case which is estimated to have the best performance is selected. That is, how many bit groups should be selected from each of the bit groups related to the rows having the degrees of 26, 3, and 2 and mapped onto y0, y1, y2, y3, and y4, y5, y6, y7, y8, y9 in order to have the best performance is determined through density evolution, and x1, x2, w1, w1, z1, z2 are determined.
Thereafter, the bits which are assumed to have the same receiving performance are determined to have different receiving performance, and the above-described process is repeated.
That is, the number of cases where the bit groups are mapped onto y0, y1, y2, y3 within x1, w1, z1 is calculated based on determined x1, w1, z1, and performance for each case is estimated through density evolution and the case which is estimated to have the best performance is selected.
In addition, the number of cases where the bit groups are mapped onto y4, y5, y6, y7, y8, y9 within x2, w2, z2 is calculated based on determined x2, w2, z2, and performance for each case is estimated through density evolution and the case which is estimated to have the best performance is selected.
Accordingly, how many of the bit groups related to the rows having each of the degrees should be mapped onto the 1024-QAM bits to have the best performance may be determined, and the interleaver 120 may be designed to be able to map a specific group of the LDPC codeword onto a specific bit of the modulation symbol and satisfy the case of the best performance.
In the above-described method, the group interleaving method can be designed.
Hereinbelow, the group interleaver design will be described in greater detail.
Meanwhile, as described above, in that each of bit groups constituting the LDPC codeword correspond to each column group of the parity check matrix, a degree of each column group has an effect on decoding performance of the LDPC codeword.
For example, that a degree of column groups is relatively high indicates that there are relatively larger number of parity check equations which are related to bit groups corresponding to column groups, the bit groups which correspond to column groups having a relatively high degree within a parity check matrix formed of a plurality of column groups may have a greater effect on decoding performance of the LDPC codeword rather than bit groups which correspond to column groups having a relatively low degree. In other words, if column groups having a relatively high degree are not mapped appropriately, the performance of the LDPC codeword will be substantially degraded.
Therefore, the group interleaver may be designed such that a bit group(s) having the highest degree, from among the bit groups constituting the LDPC codeword, is interleaved according to the π(j) and mapped to a specific bit of the modulation symbol (or transmission symbol), and the other bit groups not having the highest degree is randomly mapped to the modulatoin symbol. Under this condition, by observing actual BER/FER performance, the case where the performance of the LDPC codeword is substantially degraded may be avoided
Hereinbelow, a case where the encoder 110 performs LDPC encoding by using the code rate 12/15 to generate an LDPC codeword having the length of 64800, and constitutes a modulation symbol by using 1024-NUC will be described in a greater detail.
In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 8 and the parity submatrix having a dual diagonal configuration.
Accordingly, the parity check matrix is formed of 180 column groups, and from among the 180 column groups, 26 column groups have the degree of 14, 118 column groups have the degree of 3, and 36 column groups have the degree of 2.
Therefore, with respect to only 26 column groups of which the degree is 14, from among the 180 column groups, several π(j) for the 26 column groups may be generated to satisfy a predetermined condition in the group interleaver design, and π(j) for the other column groups may be remain as a blank. The bit groups which correspond to the other column groups may be set to be mapped randomly onto bits constituting a modulation symbol. Then, π(j) for 26 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 26 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.







TABLE 29





Order of bits group to be block interleaved


π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th block of

19
11

14

20


22

23










1


Group-wise

4
2
21


12


















interleaver


















6






input










25
7




























13













18

















0

10









17




3







24

9




16
15

5













8









Meanwhile, Table 29 may be presented as below Table 29-1.












Order of group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
1
2
4
6
9
11
22
24
25
26
29
64
79
80
106
117
135
137
144
149
157
159
161


Group-wise
162
164
178






















interleaver

























output

























π(j)-th 
19
11
14
20
22
23
1
4
2
21
12
6
25
7
13
18
0
10
17
3
24
9
16


block of
15
5
8






















Group-wise

























interleaver

























input









In case of Table 29, Equation 15 may be expressed as Y1=Xπ(1)=X19, Y2=Xπ(2)=X11, Y4=Xπ(4)=X14, . . . , Y162=Xπ(162)=X15, Y164=Xπ(164)=X5, Y178=Xπ(178)=X8.
That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 19th bit group to the 1st bit group, the 11th bit group to the 2th bit group, the 14th bit group to the 4th bit group, . . . , the 15th bit group to the 162th bit group, the 5th bit group to the 164th bit group, and the 8th bit group to the 178th bit group, and by rearranging randomly the other bit groups.
In a case where some bit groups are already fixed, the aforementioned feature is applied in the same manner. In other words, bit groups which correspond to column groups having a relatively high degree from among the other bit groups which are not fixed may have a greater effect on decoding performance of the LDPC codeword than bit groups which correspond to column groups having a relatively low degree. That is, even in the case where degradation of the performance of the LDPC codeword is prevented by fixing the bit groups having the highest degree, the performance of the LDPC codeword may vary according to a method of mapping the other bit groups. Accordingly, a method of mapping bit groups having the next highest degree needs to be selected appropriately, to avoid the case where the performance is relatively poor.
Therefore, in a case where bit groups having the highest degree are already fixed, bit groups having the next highest degree, from among the bit groups constituting the LDPC codeword, may be interleaved according to the π(j) and mapped to a specific bit of a modulation symbol, and the other bit groups may be randomly mapped. Under this condition, by observing actual BER/FER performance, the case where the performance of the LDPC codeword is substantially degraded may be avoided.
Hereinbelow, a case where the encoder 110 performs LDPC encoding by using the code rate 12/15 to generate an LDPC codeword having the length of 64800, and constitutes a modulation symbol by using 1024-NUC will be described in a greater detail.
In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 8 and the parity submatrix having a dual diagonal configuration.
Accordingly, the parity check matrix is formed of 180 column groups, and from among the 180 column groups, 26 column groups have the degree of 14, 118 column groups have the degree of 3, and 36 column groups have the degree of 2.
Therefore, a case where 26 column groups of which the degree is 14 are already fixed as in Table 29, with respect to only 118 column groups of which the degree is 3, from among the other 154 column groups, several π(j) for the 118 column groups may be generated to satisfy a predetermined condition in a group interleaver design, and π(j) for remaining column groups may be remain as a blank. The bit groups which correspond to the other column groups may be set to be mapped randomly onto bits constituting a modulation symbol. Then, π(j) for 118 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 118 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.








TABLE 30






Order of group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 

19
11

14

20


22

23










1


block of

4
2
21


12


















Group-wise


















6






interleaver










25
7













input














13













18

















0

10









17




3







24

9




16
15

5













8

















TABLE 31






Order of group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
91
19
11
106
14
40
20
67
32
22
31
23
78
68
79
141
117
95
88
136
52
121
1


block of
133
4
2
21
122
38
12
69
111
81
82
58
46
112
60
33
73
53
92
75
48
47
110


Group-wise
80
76
138
87
85
65
130
57
102
83
64
86
100
39
49
125
108
119
6
118
35
61
71


interleaver
30
45
94
26
116
98
37
55
44
70
25
7
34
114
135
128
137
84
51
28
97
27
89


input
29
62
50
139
56
109
77
59
127
142
96
105
99
90
13
124
120
115
126
143

74
41




129
18
131
42

101
134
36
140
132
103
72

93
54

43
123
113
0

10



63
107


66
104
17




3







24

9




16
15

5













8









Meanwhile, Table 31 may be presented as below Table 31-1.












Order of group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
113
114
116



117
118
119
121
122
123
124
125
126
127
129
130
132
133
134
135
137
138
139
142
143
144
149



157
159
161
162
164
178



















π(j)-th 
91
19
11
106
14
40
20
67
32
22
31
23
78
68
79
141
117
95
88
136
52
121
1


block of
133
4
2
21
122
38
12
69
111
81
82
58
46
112
60
33
73
53
92
75
48
47
110


Group-wise
80
76
138
87
85
65
130
57
102
83
64
86
100
39
49
125
108
119
6
118
35
61
71


interleaver
30
45
94
26
116
98
37
55
44
70
25
7
34
114
135
128
137
84
51
28
97
27
89


input
29
62
50
139
56
109
77
59
127
142
96
105
99
90
13
124
120
115
126
143
74
41
129



18
131
42
101
134
36
140
132
103
72
93
54
43
123
113
0
10
63
107
66
104
17
3



24
9
16
15
5
8









In case of Table 31, Equation 15 may be expressed as Y0=Xπ(0)=X91, Y1=Xπ(1)=X19, Y2=Xπ(2)=X11, . . . , Y162=Xπ(162)=X15, Y164=Xπ(164)=X5, Y178=Xπ(178)=X8.
That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 91st bit group to the 0th bit group, the 19th bit group to the 1st bit group, the 11th bit group to the 2th bit group, . . . , the 15th bit group to the 162th bit group, the 5th bit group to the 164st bit group, and the 8th bit group to the 178th bit group, and by rearranging randomly the other bit groups.
In the exemplary embodiments described above, the case of performing LDPC encoding based on coding rate of 12/15 and the parity check matrix formed of the information word submatrix defined by Table 8 and the parity submatrix having a dual diagonal configuration is described, but this is merely exemplary, and even in a case of performing LDPC encoding based on different code rates and different parity check matrix, π(j) can be determined based on the aforementioned method.
The transmitting apparatus 200 may transmit the signal mapped onto the constellation to a receiving apparatus (for example, 2700 of FIG. 36). For example, the transmitting apparatus 200 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 2700 through an allocated channel.
Exemplary Embodiment 2
Case in which a Block-Row Interleaver is Used
According to another exemplary embodiment, the interleaver 120 may interleave an LDPC codeword in other methods, different from the methods described in above Exemplary Embodiment 1, and may map bits included in a predetermined bit group from among a plurality of bit groups constituting the interleaved LDPC codeword onto a predetermined bit of a modulation symbol. This will be explained in detail with reference to FIG. 32.
Referring to FIG. 32, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block-row interleaver 125. Herein, the parity interleaver 121 and the group twist interleaver 123 perform the same functions as in Exemplary Embodiment 1 described above, and thus, a detailed description of these elements is omitted.
The group interleaver 122 may divide a parity-interleaved LDPC codeword into a plurality of bit groups, and may rearrange the order of the plurality of bit groups in bits group wise.
In this case, the operation of dividing the parity-interleaved LDPC codeword into the plurality of bit groups is the same as in Exemplary Embodiment 1, and thus, a detailed description thereof is omitted.
The group interleaver 122 interleaves the LDPC codeword in bits group wise. Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups, and may rearrange the plurality of bit groups in bits group wise. That is, the group interleaver 122 may rearrange the order of the plurality of bit groups in the LDPC codeword in group units by changing locations of the plurality of bit groups constituting the LDPC codeword.
Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are serially arranged.
In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by considering at least one of the number of rows and columns of the block-row interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are serially arranged.
To achieve this, the group interleaver 122 may interleave the LDPC codeword in bits group wise by using Equation 17 presented below:

Yj=Xπ(j)(0<j<Ngroup)  (17),

where Xj is the jth bit group before group interleaving, and Yj is the jth bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate, and a modulation method.

Accordingly, Xπ(j) is a π(j)th bit group before group interleaving, and Equation 17 means that the pre-interleaving π(j)th bit group is interleaved into the jth bit group.
According to an exemplary embodiment, an example of π(j) may be defined as in Tables 34 to 38 presented below.
In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bits group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 64800 and the code rate of 6/15 in Tables 34 to 38 presented below, for example, by using π(j) defined as shown in Table 34.
For example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 34 presented below.








TABLE 34






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
S9
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
91
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
66
59
22
15
106
97
74
88
132
134
21
14
31
37
127
149
142
87
125
82
51
40
161


block of
148
76
143
166
93
174
95
55
42
38
9
131
81
7
103
169
133
54
62
30
13
105
32


Group-wise
5
94
168
164
24
56
19
45
138
96
119
140
79
154
33
2
17
46
75
3
20
165
84


interleaver
120
12
43
18
152
130
78
144
6
118
110
70
64
4
50
101
107
151
137
179
170
63
58


input
41
49
167
86
90
157
147
114
47
67
25
27
117
98
11
10
91
153
65
53
44
77
173



16
156
85
160
72
145
68
136
60
113
162
100
141
163
109
8
61
29
35
108
150
175
129



115
171
0
39
36
48
92
111
83
146
89
176
57
92
26
178
135
158
155
122
80
99
23



69
126
28
124
172
159
73
102
116
71
1
177
34
121
139
128
112
101
123









In the case of Table 34, Equation 17 may be expressed as Y0=Xπ(0)=X66, Y1=Xπ(1)=X59, Y2=Xπ(2)=X22, . . . , Y178=Xπ(178)=X104, and Y179=Xπ(179)=X123. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 66th bit group to the 0th bit group, the 59th bit group to the 1st bit group, the 22nd bit group to the 2nd bit group, . . . , the 104th bit group to the 178th bit group, and the 123rd bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 35 presented below.








TABLE 35






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
17
13
14
15
lb
17
18
19
20
21
27


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
6d
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
77
39
3
175
102
62
119
0
171
104
48
13
72
91
30
125
173
109
8
115
82
79
2


block of
68
112
28
168
167
106
135
51
75
54
85
122
26
118
128
144
121
57
41
57
94
110
45


Group-wise
120
107
150
100
69
18
145
15
29
24
114
117
169
12
65
38
19
43
20
23
149
147
108


interleaver
170
6
89
78
74
105
21
159
177
162
156
71
49
80
60
138
157
155
96
143
126
90
93


input
63
66
101
98
179
164
111
5
84
36
87
37
174
35
160
152
141
127
81
64
67
92
33



95
161
11
133
154
50
47
86
4
137
22
130
148
178
97
88
40
10
9
136
32
123
158



134
140
61
42
1
16
131
103
172
129
146
116
55
76
58
83
166
27
139
163
99
165
53



70
17
46
59
113
124
176
132
7
73
56
14
44
34
31
153
151
142
25









In the case of Table 35, Equation 17 may be expressed as Y0=Xπ(0)=X77, Y1=Xπ(1)=X39, Y2=Xπ(2)=X3, . . . , Y178=Xπ(178)=X142, and Y179=Xπ(179)=X25. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 77th bit group to the 0th bit group, the 39th bit group to the 1st bit group, the 3rd bit group to the 2nd bit group, . . . , the 142th bit group to the 178th bit group, and the 25th bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 36 presented below.








TABLE 36






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
7
87
5
66
23
42
149
43
148
16
58
9
82
102
79
12
163
135
147
172
108
93
10


block of
25
35
41
173
123
167
3
59
81
116
39
72
97
159
178
136
155
1
94
109
78
33
2


Group-wise
132
130
164
169
14
71
75
53
98
21
170
127
146
142
54
106
91
118
40
61
179
145
153


interleaver
156
115
50
47
112
32
117
69
157
138
120
57
44
80
0
24
70
139
176
161
122
29
15


input
99
83
63
62
133
177
6
19
64
52
103
22
73
34
154
140
143
144
65
4
30
36
20



11
160
151
124
158
8
100
105
51
48
67
128
134
17
13
101
90
76
55
27
37
168
126



174
152
113
111
107
85
96
49
84
18
131
141
60
77
88
86
68
114
171
129
175
166
46



89
95
45
26
56
162
137
165
125
104
92
28
119
110
32
31
74
150
121









In the case of Table 36, Equation 17 may be expressed as Y0=Xπ(0)=X7, Y1=Xπ(1)=X87, Y2=Xπ(2)=X5, . . . , Y178=Xπ(178)=X150, and Y179=Xπ(179)=X121. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 7th bit group to the 0th bit group, the 87th bit group to the 1st bit group, the 5th bit group to the 2nd bit group, . . . , the 150th bit group to the 178th bit group, and the 121st bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 37 presented below.








TABLE 37






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
111
32
70
77
54
93
122
65
165
144
45
101
95
2
38
7
126
13
156
128
78
82
57


block of
117
60
42
131
177
148
11
97
23
10
20
114
51
160
166
179
175
75
79
50
74
59
40


Group-wise
154
139
163
134
63
68
99
106
105
119
6
167
3
124
35
98
118
83
67
8
22
172
133


interleaver
130
15
31
73
102
103
21
142
176
143
146
9
107
27
109
0
81
141
153
121
161
25
19


input
12
113
80
76
136
89
132
145
39
110
1
72
64
112
157
152
169
120
94
48
17
88
4



28
162
168
147
129
24
58
61
115
91
34
123
135
173
164
84
71
55
37
66
36
159
52



155
125
100
87
90
30
46
86
150
170
149
5
49
43
56
116
108
69
171
138
178
151
44



62
14
29
33
92
174
127
158
18
41
85
47
26
104
53
137
96
16
140









In the case of Table 37, Equation 17 may be expressed as Y0=Xπ(0)=X111, Y1=Xπ(1)=X32, Y2=Xπ(2)=X70, . . . , Y178=Xπ(178)=X16, and Y179=Xπ(179)=X140. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 111th bit group to the 0th bit group, the 32nd bit group to the 1st bit group, the 70th bit group to the 2nd bit group, . . . , the 16th bit group to the 178th bit group, and the 140th bit group to the 179th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 38 presented below.








TABLE 38






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


output
69
70
71
72
73
74
75
76
77
78
79
80
81
81
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
91
88
112
102
26
27
120
103
17
15
19
136
60
83
116
89
115
72
147
148
11
52
33


block of
64
98
29
126
164
167
5
106
121
73
86
37
62
143
93
174
146
14
1
53
100
55
50


Group-wise
149
54
179
163
40
133
92
39
44
139
74
166
3
172
20
4
75
49
70
56
41
43
173


interleaver
175
67
2
48
125
25
109
178
123
160
151
32
21
47
108
7
77
129
113
155
169
22
122


input
110
119
34
59
18
0
161
176
31
38
80
6
114
127
131
154
152
150
23
12
76
118
135



142
42
10
156
153
78
69
138
35
128
96
165
63
177
171
68
111
87
61
137
105
101
107



24
158
79
81
85
71
84
99
134
162
170
168
141
82
65
30
51
90
36
157
9
144
117



58
130
45
28
13
140
66
159
8
95
46
57
94
97
124
132
104
16
145









In the case of Table 38, Equation 17 may be expressed as Y0=Xπ(0)=X91, Y1=Xπ(1)=X88, Y2=Xπ(2)=X112, . . . , Y178=Xπ(178)=X16, and Y179=Xπ(179)=X145. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 91st bit group to the 0th bit group, the 88th bit group to the 1st bit group, the 112th bit group to the 2nd bit group, . . . , the 16th bit group to the 178th bit group, and the 145th bit group to the 179th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 17 and Tables 34 to 38.
“j-th block of Group-wise Interleaver output” in Tables 34 to 38 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bits group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 34 to 38 in relation to π(j).
π(j) defined as shown in Tables 34 to 38 may be arranged according to the code rates as shown in Table 39 presented below:












TABLE 39






(CR 6/15)
(CR 8/15)
(CR 10/15)
(CR 10/15)
(CR 12/15)


j-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of
π(j)-th block of


Group-wise
Group-wise
Group-wise
Group-wise
Group-wise
Group-wise


Interleaver
Interleaver
Interleaver
Interleaver
Interleaver
Interleaver


output
input
input
input
input
input




















0
66
77
7
111
91


1
59
39
87
32
88


2
22
3
5
70
112


3
15
175
66
77
102


4
106
102
23
54
26


5
97
62
42
93
27


6
74
119
149
122
120


7
88
0
43
65
103


8
132
171
148
165
17


9
134
104
16
144
15


10
21
48
58
45
19


11
14
13
9
101
136


12
31
72
82
95
60


13
37
91
102
2
83


14
127
30
79
38
116


15
149
125
12
7
89


16
142
173
163
126
115


17
87
109
135
13
72


18
125
8
147
156
147


19
82
115
172
128
148


20
51
82
108
78
11


21
40
79
93
82
52


22
161
2
10
57
33


23
148
68
25
117
64


24
76
112
35
60
98


25
143
28
41
42
29


26
166
168
173
131
126


27
93
167
123
177
164


28
174
106
167
148
167


29
95
135
3
11
5


30
55
51
59
97
106


31
42
75
81
23
121


32
38
54
116
10
73


33
9
85
39
20
86


34
131
122
72
114
37


35
81
26
97
51
62


36
7
118
159
160
143


37
103
128
178
166
93


38
169
144
136
179
174


39
133
121
155
175
146


40
54
57
1
75
14


41
62
41
94
79
1


42
30
52
109
50
53


43
13
94
78
74
100


44
105
110
33
59
55


45
32
45
2
40
50


46
5
120
132
154
149


47
94
107
130
139
54


48
168
150
164
163
179


49
164
100
169
134
163


50
24
69
14
63
40


51
56
18
71
68
133


52
19
145
75
99
92


53
45
15
53
106
39


54
138
29
98
105
44


55
96
24
21
119
139


56
119
114
170
6
74


57
140
117
127
167
166


58
79
169
146
3
3


59
154
12
142
124
172


60
33
65
54
35
20


61
2
38
106
98
4


62
17
19
91
118
75


63
46
43
118
83
49


64
75
20
40
67
70


65
3
23
61
8
56


66
20
149
179
22
41


67
165
147
145
172
43


68
84
108
153
133
173


69
120
170
156
130
175


70
12
6
115
15
67


71
43
89
50
31
2


72
18
78
47
73
48


73
152
74
112
102
125


74
130
105
38
103
25


75
78
21
117
21
109


76
144
159
69
142
178


77
6
177
157
176
123


78
118
162
138
143
160


79
110
156
120
146
151


80
70
71
57
9
32


81
64
49
44
107
21


82
4
80
80
27
47


83
50
60
0
109
108


84
101
138
24
0
7


85
107
157
70
81
77


86
151
155
139
141
129


87
137
96
176
153
113


88
179
143
161
121
155


89
170
126
122
161
169


90
63
90
29
25
22


91
58
93
15
19
122


92
41
63
99
12
110


93
49
66
83
113
119


94
167
101
63
80
34


95
86
98
62
76
59


96
90
179
133
136
18


97
157
164
177
89
0


98
147
111
6
132
161


99
114
5
19
145
176


100
47
84
64
39
31


101
67
36
52
110
38


102
25
87
103
1
80


103
27
37
22
72
6


104
117
174
73
64
114


105
98
35
34
112
127


106
11
160
154
157
131


107
10
152
140
152
154


108
91
141
143
169
152


109
153
127
144
120
150


110
65
81
65
94
23


111
53
64
4
48
12


112
44
67
30
17
76


113
77
92
36
88
118


114
173
33
20
4
135


115
16
95
11
28
142


116
156
161
160
162
42


117
85
11
151
168
10


118
160
133
124
147
156


119
72
154
158
129
153


120
145
50
8
24
78


121
68
47
100
58
69


122
136
86
105
61
138


123
60
4
51
115
35


124
113
137
48
91
128


125
162
22
67
34
96


126
100
130
128
123
165


127
141
148
134
135
63


128
163
178
17
173
177


129
109
97
13
164
171


130
8
88
101
84
68


131
61
40
90
71
111


132
29
10
76
55
87


133
35
9
55
37
61


134
108
136
27
66
137


135
150
32
37
36
105


136
175
123
168
159
101


137
129
158
126
52
107


138
115
134
174
155
24


139
171
140
152
125
158


140
0
61
113
100
79


141
39
42
111
87
81


142
36
1
107
90
85


143
48
16
85
30
71


144
92
131
96
46
84


145
111
103
49
86
99


146
83
172
84
150
134


147
146
129
18
170
162


148
89
146
131
149
170


149
176
116
141
5
168


150
57
55
60
49
141


151
52
76
77
43
82


152
26
58
88
56
65


153
178
83
86
116
30


154
135
166
68
108
51


155
158
27
114
69
90


156
155
139
171
171
36


157
122
163
129
138
157


158
80
99
175
178
9


159
99
165
166
151
144


160
23
53
46
44
117


161
69
70
89
62
58


162
126
17
95
14
130


163
28
46
45
29
45


164
124
59
26
33
28


165
172
113
56
92
13


166
159
124
162
174
140


167
73
176
137
127
66


168
102
132
165
158
159


169
116
7
125
18
8


170
71
73
104
41
95


171
1
56
92
85
46


172
177
14
28
47
57


173
34
44
119
26
94


174
121
34
110
104
97


175
139
31
32
53
124


176
128
153
31
137
132


177
112
151
74
96
104


178
104
142
150
16
16


179
123
25
121
140
145









“j-th block of Group-wise Interleaver output” in Table 39 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122. Referring to Table 39, it can be seen that Table 39 is the arrangements of data described in Tables 34 to 38 according to the code rates.
The group interleaver 122 may interleave the LDPC codeword in bits group wise by using Equation 18 presented below:

Yπ(j)=Xj(0≦j<Ngroup)  (18),

where Xj is the jth bit group before group interleaving, and Yj is the jth bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate, and a modulation method.

Accordingly, Xj is a jth bit group before group interleaving, and Equation 18 means that the pre-interleaving jth bit group is interleaved into the π(j)th bit group.
According to an exemplary embodiment, an example of π(j) may be defined as in Tables 40 to 44 presented below.
In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bits group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 64800 and the code rate of 6/15 in Tables 40 to 44 presented below, for example, by using π(j) defined as shown in Table 40.
For example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 40 presented below.








TABLE 40






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


input
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
140
171
61
65
82
46
77
36
130
33
107
106
70
43
11
3
115
62
72
52
66
10
2


block of
160
50
102
152
103
163
132
42
12
45
60
173
133
142
143
32
141
21
92
31
71
112
53


Group-wise
63
100
143
93
83
20
151
111
40
30
51
150
91
1
123
131
41
90
81
110
0
101
121


interleaver
161
80
170
119
167
6
64
24
113
75
58
158
35
19
146
68
117
95
17
7
148
96
108


output
144
27
47
29
55
5
105
159
126
84
168
37
178
44
4
85
134
129
79
145
177
124
99



138
169
104
78
56
69
174
157
179
164
18
162
14
176
137
74
34
8
39
9
154
122
87



54
175
57
127
16
25
76
120
147
98
23
15
135
86
73
109
59
156
116
97
155
166
118



22
125
128
49
67
26
94
48
38
89
139
165
114
28
136
149
172
153
88









In the case of Table 40, Equation 18 may be expressed as X0=Yπ(0)=Y140, X1=Yπ(1)=Y171, X2=Yπ(2)=Y61, . . . , X178=Yπ(178)=Y153, and X179=Yπ(179)=Y88. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 140th bit group, the 1st bit group to the 171st bit group, the 2nd bit group to the 61st bit group, . . . , the 178th bit group to the 153rd bit group, and the 179th bit group to the 88th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 41 presented below.








TABLE 41






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
AA
34
AS
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


input
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
7
142
22
2
123
99
70
169
18
133
132
117
59
11
172
53
143
162
51
62
64
75
125


block of
65
55
179
35
155
25
54
14
175
135
114
174
105
101
103
61
1
131
41
141
63
173
45


Group-wise
163
121
10
81
120
30
42
160
32
150
171
40
152
164
83
140
5
92
111
60
93
112
23


interleaver
50
161
80
12
170
73
31
151
0
72
21
82
110
20
153
100
33
122
102
130
71
90
13


output
113
91
43
115
87
129
95
158
49
94
4
145
9
74
28
47
68
17
44
98
24
165
56



19
149
57
36
6
46
39
34
136
166
15
89
109
37
147
126
144
168
118
138
29
134
124



84
156
139
108
178
88
38
52
148
67
117
66
48
177
107
176
119
86
79
85
137
76
106



116
78
157
97
159
154
27
26
58
69
8
146
16
104
0
167
77
128
98









In the case of Table 41, Equation 18 may be expressed as X0=Yπ(0)=Y7, X1=Yπ(1)=Y142, X2=Yπ(2)=Y22, . . . , X178=Yπ(178)=Y128, and X179=Yπ(179)=Y98. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 7th bit group, the 1st bit group to the 142nd bit group, the 2nd bit group to the 22nd bit group, . . . , the 178th bit group to the 128th bit group, and the 179th bit group to the 98th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 42 presented below.








TABLE 42






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


input
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
83
40
45
29
111
2
98
0
120
11
22
115
15
129
50
91
9
128
147
99
114
55
103


block of
4
84
23
164
134
172
90
112
176
175
44
105
24
113
135
74
33
64
25
5
7
81
163


Group-wise
160
72
124
145
71
123
101
53
60
133
165
80
10
30
150
65
95
94
100
110
3
125
154


interleaver
76
85
51
34
104
177
52
132
151
43
14
82
31
12
93
146
143
153
1
152
161
131
62


output
171
21
41
162
144
35
54
92
121
130
13
102
170
122
61
142
20
42
174
141
73
140
155



70
32
75
63
173
79
179
89
27
118
169
137
57
126
157
47
148
46
96
127
17
38
167



78
86
107
149
59
108
109
67
58
18
8
6
178
117
139
68
106
39
69
77
119
36
116



88
166
16
48
168
159
28
136
49
56
156
19
26
138
158
87
97
37
66









In the case of Table 42, Equation 18 may be expressed as X0=Yπ(0)=Y83, X1=Yπ(1)=Y40, X2=Yπ(2)=Y45, . . . , X178=Yπ(178)=Y37, and X179=Yπ(179)=Y66. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 83rd bit group, the 1st bit group to the 40th bit group, the 2nd bit group to the 45th bit group, . . . , the 178th bit group to the 37th bit group, and the 179th bit group to the 66th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 43 presented below.








TABLE 43






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group-wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
55
65
67
58


input
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179






π(j)-th 
84
102
13
58
114
149
56
15
65
80
32
29
92
17
162
70
178
112
169
91
33
75
66


block of
31
120
90
173
82
115
163
143
71
1
164
125
60
135
133
14
100
45
170
25
151
160
10


Group-wise
144
172
111
150
42
35
137
175
4
132
152
22
121
44
24
122
161
50
104
7
134
64
51


interleaver
155
2
131
103
72
43
40
95
3
20
41
94
85
21
63
130
171
145
141
113
97
142
124


output
165
5
110
12
177
30
61
52
140
11
73
74
174
54
53
81
154
83
101
0
105
93
34



123
153
23
62
55
109
88
6
126
59
139
16
167
19
119
69
26
98
68
49
127
96
176



157
47
179
86
76
78
9
99
79
118
28
148
146
159
107
87
46
138
18
106
168
136
36



89
116
48
179
8
37
57
117
108
147
156
67
128
166
39
77
27
158
38









In the case of Table 43, Equation 18 may be expressed as X0=Yπ(0)=Y84, X1=Yπ(1)=Y102, X2=Yπ(2)=Y13, . . . , X178=Yπ(178)=Y158, and X179=Yπ(179)=Y38. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 84th bit group, the 1st bit group to the 102th bit group, the 2nd bit group to the 13th bit group, . . . , the 178th bit group to the 158th bit group, and the 179th bit group to the 38th bit group.
In another example, when the length Nldpc of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 44 presented below.








TABLE 44






Order of bits group to be block interleaved



π(j) (0 ≦ j < 180)






































j-th block of
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


Group wise
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45


interleaver
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68


input
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91



92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114



115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137



138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160



161
162
163
164
165
166
167
168
169
170
171
172
171
174
175
175
177
178
179






π(j)-th 
97
41
71
58
61
29
103
84
169
158
117
20
111
165
40
9
178
8
96
10
60
81
90


block of
110
138
74
4
5
164
25
153
100
80
22
94
123
156
34
101
53
50
66
116
67
54
163


Group-wise
171
82
72
63
45
154
21
42
47
44
65
172
161
95
12
133
35
127
23
152
167
70
130


interleaver
121
64
143
17
32
56
62
112
85
120
140
102
141
151
13
144
142
33
132
1
15
155
0


output
52
37
173
170
125
174
24
1215
43
136
3
7
177
135
30
137
83
75
92
131
2
87
104



16
14
160
113
93
6
31
91
77
175
73
26
105
124
86
162
106
176
51
146
114
11
134



122
55
166
150
115
36
159
179
39
18
19
46
109
79
108
119
107
88
118
157
139
168
78



98
147
49
27
126
57
28
149
89
148
129
59
68
38
69
99
128
76
48









In the case of Table 44, Equation 18 may be expressed as X0=Yπ(0)=Y97, X1=Yπ(1)=Y41, X2=Yπ(2)=Y71, . . . , X178=Yπ(178)=Y76, and X179=Yπ(179)=Y48. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by changing the 0th bit group to the 97th bit group, the 1st bit group to the 41st bit group, the 2nd bit group to the 71st bit group, . . . , the 178th bit group to the 76th bit group, and the 179th bit group to the 48th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 18 and Tables 40 to 44.
“j-th block of Group-wise Interleaver input” in Tables 40 to 44 indicates the j-th bit group input to the group interleaver 122 before interleaving, and “π(j)-th block of Group-wise Interleaver output” indicates the π(j)-th bit group output from the group interleaver 122 after interleaving.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bits group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 40 to 44 in relation to π(j).
π(j) defined as shown in Tables 40 to 44 may be arranged according to the code rates as shown in Table 45:












TABLE 45






(CR 6/15)
(CR 8/15)
(CR 10/15)
(CR 10/15)
(CR 12/15)


j-th block of
π(j)-th block
π(j)-th block
π(j)-th block
π(j)-th block
π(j)-th block


Group-wise
of Group-wise
of Group-wise
of Group-wise
of Group-wise
of Group-wise


Interleaver
Interleaver
Interleaver
Interleaver
Interleaver
Interleaver


input
output
output
output
output
output




















0
140
7
83
84
97


1
171
142
40
102
41


2
61
22
45
13
71


3
65
2
29
58
58


4
82
123
111
114
61


5
46
99
2
149
29


6
77
70
98
56
103


7
36
169
0
15
84


8
130
18
120
65
169


9
33
133
11
80
158


10
107
132
22
32
117


11
106
117
115
29
20


12
70
59
15
92
111


13
43
11
129
17
165


14
11
172
50
162
40


15
3
53
91
70
9


16
115
143
9
178
178


17
62
162
128
112
8


18
72
51
147
169
96


19
52
62
99
91
10


20
66
64
114
33
60


21
10
75
55
75
81


22
2
125
103
66
90


23
160
65
4
31
110


24
50
55
84
120
138


25
102
179
23
90
74


26
152
35
164
173
4


27
103
155
134
82
5


28
163
25
172
115
164


29
132
54
90
163
25


30
42
14
112
143
153


31
12
175
176
71
100


32
45
135
175
1
80


33
60
114
44
164
22


34
173
174
105
125
94


35
133
105
24
60
123


36
142
101
113
135
156


37
13
103
135
133
34


38
32
61
74
14
101


39
141
1
33
100
53


40
21
131
64
45
50


41
92
41
25
170
66


42
31
141
5
25
116


43
71
63
7
151
67


44
112
173
81
160
54


45
53
45
163
10
163


46
63
163
160
144
171


47
100
121
72
172
82


48
143
10
124
111
72


49
93
81
145
150
63


50
83
120
71
42
45


51
20
30
123
35
154


52
151
42
101
137
21


53
111
160
53
175
42


54
40
32
60
4
47


55
30
150
133
132
44


56
51
171
165
152
65


57
150
40
80
22
172


58
91
152
10
121
161


59
1
164
30
44
95


60
123
83
150
24
12


61
131
140
65
122
133


62
41
5
95
161
35


63
90
92
94
50
127


64
81
111
100
104
23


65
110
60
110
7
152


66
0
93
3
134
167


67
101
112
125
64
70


68
121
23
154
51
130


69
161
50
76
155
121


70
80
161
85
2
64


71
170
80
51
131
143


72
119
12
34
103
17


73
167
170
104
72
32


74
6
73
177
43
56


75
64
31
52
40
62


76
24
151
132
95
112


77
113
0
151
3
85


78
75
72
43
20
120


79
58
21
14
41
140


80
158
82
82
94
102


81
35
110
31
85
141


82
19
20
12
21
151


83
146
153
93
63
13


84
68
100
146
130
144


85
117
33
143
171
142


86
95
122
153
145
33


87
17
102
1
141
132


88
7
130
152
113
1


89
148
71
161
97
15


90
96
90
131
142
155


91
108
13
62
124
0


92
144
113
171
165
52


93
27
91
21
5
37


94
47
43
41
110
173


95
29
115
162
12
170


96
55
87
144
177
125


97
5
129
35
30
174


98
105
95
54
61
24


99
159
158
92
52
145


100
126
49
121
140
43


101
84
94
130
11
136


102
168
4
13
73
3


103
37
145
102
74
7


104
178
9
170
174
177


105
44
74
122
54
135


106
4
28
61
53
30


107
85
47
142
81
137


108
134
68
20
154
83


109
129
17
42
83
75


110
79
44
174
101
92


111
145
98
141
0
131


112
177
24
73
105
2


113
124
165
140
93
87


114
99
56
155
34
104


115
138
19
70
123
16


116
169
149
32
153
14


117
104
57
75
23
160


118
78
36
63
62
113


119
56
6
173
55
93


120
69
46
79
109
6


121
174
39
179
88
31


122
157
34
89
6
91


123
179
136
27
126
77


124
164
166
118
59
175


125
18
15
169
139
73


126
162
89
137
16
26


127
14
109
57
167
105


128
176
37
126
19
124


129
137
147
157
119
86


130
74
126
47
69
162


131
34
144
148
26
106


132
8
168
46
98
176


133
39
118
96
68
51


134
9
138
127
49
146


135
154
29
17
127
114


136
122
134
38
96
11


137
87
124
167
176
134


138
54
84
78
157
122


139
175
156
86
47
55


140
57
139
107
179
166


141
127
108
149
86
150


142
16
178
59
76
115


143
25
88
108
78
36


144
76
38
109
9
159


145
120
52
67
99
179


146
147
148
58
79
39


147
98
67
18
118
18


148
23
127
8
28
19


149
15
66
6
148
46


150
135
48
178
146
109


151
86
177
117
159
79


152
73
107
139
107
108


153
109
176
68
87
119


154
59
119
106
46
107


155
156
86
39
138
88


156
116
79
69
18
118


157
97
85
77
106
157


158
155
137
119
168
139


159
166
76
36
136
168


160
118
106
116
36
78


161
22
116
88
89
98


162
125
78
166
116
147


163
128
157
16
48
49


164
49
97
48
129
27


165
67
159
168
8
126


166
26
154
159
37
57


167
94
27
28
57
28


168
48
26
136
117
149


169
38
58
49
108
89


170
89
69
56
147
148


171
139
8
156
156
129


172
165
146
19
67
59


173
114
16
26
128
68


174
28
104
138
166
38


175
136
3
158
39
69


176
149
167
87
77
99


177
172
77
97
27
128


178
153
128
37
158
76


179
88
96
66
38
48









Table 34 is the case in which group interleaving is performed using Equation 17 and π(j) is applied as an index of an input bit group, and Table 40 is the case in which group interleaving is performed using Equation 18 and π(j) is applied as an index of an output bit group. Therefore, Tables 39 and 45 have an inverse relationship with each other.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise by using Equation 18 and Tables 40 to 44.
When the group interleaving is performed in the above-described method, the order of the bit groups constituting the group-interleaved LDPC codeword is different from that of the bit groups of the LDPC codeword group-interleaved based on Tables 9 to 20.
This is because the block-row interleaver 125 is used instead of the block interleaver 124 in the present exemplary embodiment. That is, since the interleaving method used in the block interleaver 124 and the interleaving method used in the block-row interleaver 125 are different from each other, the group interleaver 122 in the present exemplary embodiment may rearrange the order of the plurality of bit groups constituting the LDPC codeword based on Tables 34 to 45.
Specifically, the group interleaver 122 may rearrange the order of the plurality of bit groups in bits group wise such that an arrangement unit, in which at least one bit group including bits to be mapped onto a same modulation symbol is serially arranged in bit group wise, is repeated.
That is, the group interleaver 122 may serially arrange one of a plurality of first bit groups including bits to be mapped onto a first specific location of each modulation symbol, one of a plurality of second bit groups including bits to be mapped onto a second specific location of each modulation symbol, . . . , one of a plurality of nth bit groups including bits to be mapped onto an nth specific location of each modulation symbol, and may arrange the other bit groups repeatedly in the same method.
The block-row interleaver 125 interleaves the plurality of bit groups the order of which has been rearranged. In this case, the block-row interleaver 125 may interleave the plurality of bit groups the order of which has been rearranged in bits group wise by using at least one row including a plurality of columns. This will be explained in detail below with reference to FIGS. 33 to 35.
FIGS. 33 to 35 are views to illustrate a configuration of a block-row interleaver and an interleaving method according to an exemplary embodiment.
First, when Ngroup/m is an integer, the block-row interleaver 125 includes an interleaver 125-1 including m number of rows each including M number of columns as shown in FIG. 33, and the block-row interleaver 125 may interleave by using Ngroup/m number of interleavers 125-1 having the configuration of FIG. 33.
Herein, Ngroup is the total number of bit groups constituting an LDPC codeword. In addition, M is the number of bits included in a single bit group and may be 360, for example. m may be equal to the number of bits constituting a modulation symbol or may be 1⁄2 of the number of bits constituting a modulation symbol. For example, when a non-uniform QAM is used, performance of the bits constituting the modulation symbol is different, and thus, by setting m to be equal to the number of bits constituting the modulation symbol, a single bit group can be mapped onto a single bit of each modulation symbol.
Specifically, the block-row interleaver 125 may interleave by writing each of the plurality of bit groups constituting the LDPC codeword in each row in the row direction in bits group wise, and reading each column of the plurality of rows in which the plurality of bit groups are written in bit group wise in the column direction.
For example, as shown in FIG. 33, the block-row interleaver 125 may write m number of continuous bit groups from among the plurality of bit groups in each of the m number of rows of the interleaver 125-1 in the row direction, and read each column of m number of rows in which the bits are written in the column direction. In this case, as many interleavers 125-1 as the number of bit groups divided by the number of rows, that is, Ngroup/m, may be used.
As described above, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of rows, the block-row interleaver 125 may interleave by writing as many bit groups as the number of rows from among the plurality of bit groups serially.
On the other hand, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of rows, the block-row interleaver 125 may interleave by using N number of interleavers (N is an integer greater than or equal to 2) including a different number of columns.
For example, as shown in FIGS. 34 and 35, the block-row interleaver 125 may interleave by using a first interleaver 125-2 including m number of rows each including M number of columns, and a second interleaver 125-3 including m number of rows each including a×M/m number of columns. Herein, a is Ngroup−└Ngroup/m┘×m, and └Ngroup/m┘ is the largest integer below Ngroup/m.
In this case, the first interleaver 125-2 may be used as many as └Ngroup/m┘ and one second interleaver 125-3 may be used.
Specifically, the block-row interleaver 125 may interleave by writing each of └Ngroup/m┘×m number of bit groups from among the plurality of bit groups constituting the LDPC codeword in each row in the row direction in bits group wise, and reading each column of the plurality of rows in which └Ngroup/m┘×m number of bit groups are written in bits group wise in the column direction.
For example, as shown in FIGS. 34 and 35, the block-row interleaver 125 may write the same m number of continuous bit groups as the number of rows from among └Ngroup/m┘×m number of bit groups in each row of the first interleaver 125-2 in the row direction, and may read each column of the plurality of rows of the first interleaver 125-2 in which m number of bit groups are written in the column direction. In this case, the first interleaver 125-2 having the configuration FIGS. 34 and 35 may be used as many as └Ngroup/m┘.
Thereafter, the block-row interleaver 125 may divide the bits included in bit groups other than the groups written in the first interleaver 125-2, and may write these bits in each row of the second interleaver 125-3 in the row direction. In this case, the same number of bits may be written in each row of the second interleaver 125-3.
For example, as shown in FIG. 34, the block-row interleaver 125 may write, in each of m number of rows of the second interleaver 125-3, a×M/m number of bits from among the bits included in the other bit groups, in the row direction, and may read each column of m number of rows of the second interleaver 125-3 in which the bits are written in the column direction. In this case, one second interleaver 125-3 having the configuration of FIG. 34 may be used.
However, according to another exemplary embodiment, as shown in FIG. 35, the block-row interleaver 125 may write the bits in the first interleaver 125-2 in the same method as explained in FIG. 34, but may write the bits in the second interleaver 125-3 in a method different from that of FIG. 34.
That is, the block-row interleaver 125 may write the bits in the second interleaver 125-3 in the column direction.
For example, as shown in FIG. 35, the block-row interleaver 125 may write the bits included in the bit groups other than the bit groups written in the first interleaver 125-2 in each column of m number of rows each including a×M/m number of columns of the second interleaver 125-3 in the column direction, and may read each column of m number of rows of the second interleaver 125-3 in which the bits are written in the column direction. In this case, one second interleaver 125-3 having the configuration of FIG. 35 may be used.
In the method shown in FIG. 35, the block-row interleaver 125 may interleave by reading in the column direction after writing the bits in the second interleaver in the column direction. Accordingly, the bits included in the bit groups interleaved by the second interleaver are read in the order as they were written and output to the modulator 130. Accordingly, the bits included in the bit groups belonging to the second interleaver are not rearranged by the block-row interleaver 125 and may be mapped onto the modulation symbols serially.
As described above, the block-row interleaver 125 may interleave the plurality of bit groups by using the methods described above with reference to FIGS. 33 to 35.
According to the above-described method, the output of the block-row interleaver 125 may be the same as the output of the block interleaver 124. Specifically, when the block-row interleaver 125 interleaves as shown in FIG. 33, the block-row interleaver 125 may output the same value as that of the block interleaver 124 which interleaves as shown in FIG. 26. In addition, when the block-row interleaver 125 interleaves as shown in FIG. 34, the block-row interleaver 125 may output the same value as that of the block interleaver 124 which interleaves as shown in FIG. 27. In addition, when the block-row interleaver 125 interleaves as shown in FIG. 35, the block-row interleaver 125 may output the same value as that of the block interleaver 124 which interleaves as shown in FIG. 38.
Specifically, when the group interleaver 122 is used based on Equation 15 and the block interleaver 124 is used, and the output bit groups of the group interleaver 122 are Yi(0≦j<Ngroup), and, when the group interleaver 122 is used based on Equation 17 and the block-row interleaver 125 is used, and the output groups of the group interleaver 122 are Zi(0≦j<Ngroup), a relationship between the output bit groups Zi and Yi after group interleaving may be expressed as in Equations 19 and 20, and as a result, the same value may be output from the block interleaver 124:

Zi+m×j=Yα×i+j(0≦i<m,0≦j<α)  (19)

Zi=Yi(α×m≦i<Ngroup)  (20),

where a is └Ngroup/m┘ and is the number of bit groups input to a single column of the first part when the block interleaver 124 is used, and └Ngroup/m┘ is the largest integer below Ngroup/m. Here, m may be equal to the number of bits constituting the modulation symbol or half of the bits constituting the modulation symbol. In addition, m is the number of columns of the block interleaver 124 and m is the number of rows of the block-row interleaver 125.

The case in which group interleaving is performed by the group interleaver 122 based on Equation 15 and then block interleaving is performed by the block interleaver 124, and the case in which group interleaving is performed by the group interleaver 122 based on Equation 16 and then block interleaving is performed by the block interleaver 124 have an inverse relationship with each other.
In addition, the case in which group interleaving is performed by the group interleaver 122 based on Equation 17 and then block-row interleaving is performed by the block-row interleaver 125, and the case in which group interleaving is performed by the group interleaver 122 based on Equation 18 and then block-row interleaving is performed by the block-row interleaver 125 have an inverse relationship with each other.
Accordingly, the modulator 130 may map the bits output from the block-row interleaver 125 onto a modulation symbol in the same method as when the block interleaver 124 is used.
The bit interleaving method suggested in the exemplary embodiments is performed by the parity interleaver 121, the group interleaver 122, the group twist interleaver 123, and the block interleaver 124 as shown in FIG. 22 (the group twist interleaver 123 may be omitted according to circumstances). However, this is merely an example and the bit interleaving method is not limited to three modules or four modules described above.
For example, when the block interleaver is used and the group interleaving method expressed as in Equation 11 is used, regarding the bit groups Xj(0≦j<Ngroup) defined as in Equation 9 and Equation 10, bits belonging to m number of bit groups, for example, {Xπ(i)Xπ(α+i), . . . , Xπ((m−1)×α+i)} (0≦i<α), may constitute a single modulation symbol.
Herein, α is the number of bit groups constituting the first part of the block interleaver, and α=└Ngroup/m┘. In addition, m is the number of columns of the block interleaver and may be equal to the number of bits constituting the modulation symbol or half of the number of bits constituting the modulation symbol.
Therefore, for example, regarding parity-interleaved bits ui, {ux(i)+j, uπ(α+i+j, . . . , uπ((m−1)×α+i)+j} (0<i≦m, 0<j≦M) may constitute a single modulation symbol. As described above, there are various methods for constituting a single modulation symbol.
In addition, the bit interleaving method suggested in the exemplary embodiments is performed by the parity interleaver 121, the group interleaver 122, the group twist interleaver 123, and the block-row interleaver 125 as shown in FIG. 32 (the group twist interleaver 123 may be omitted according to circumstances). However, this is merely an example and the bit interleaving method is not limited to three modules or four modules described above.
For example, when the block-row interleaver is used and the group interleaving method expressed as in Equation 17 is used, regarding the bit groups Xj(0≦j<Ngroup) defined as in Equation 13 and Equation 14, bits belonging to m number of bit groups, for example, {Xπ(m×i), Xπ(m×i+1), . . . , Xπ(m×i+(m−0))} (0≦i<α), may constitute a single modulation symbol.
Herein, α is the number of bit groups constituting the first part of the block interleaver, and α=└Ngroup/m┘. In addition, m is the number of columns of the block interleaver and may be equal to the number of bits constituting the modulation symbol or half of the number of bits constituting the modulation symbol.
Therefore, for example, regarding parity-interleaved bits ui, {uπ(m×i)+j, uπ(m×i+1)+j, . . . , uπ(m×i+(m−1))+j} (0≦i<m, 0<j≦M) may constitute a single modulation symbol. As described above, there are various methods for constituting a single modulation symbol.
The transmitting apparatus 100 may transmit the signal mapped onto the constellation to a receiving apparatus 2700. For example, the transmitting apparatus 100 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 2700 through an allocated channel.
FIG. 36 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 36, the receiving apparatus 2700 includes a demodulator 2710, a multiplexer 2720, a deinterleaver 2730 and a decoder 2740.
The demodulator 2710 receives and demodulates a signal transmitted from the transmitting apparatus 100. Specifically, the demodulator 2710 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 2720. In this case, the demodulator 2710 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100. To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 2700, or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 2700.
The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.
The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.
The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs the value to the deinterleaver 2730.
Specifically, the multiplexer 2720 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100, and performs an operation corresponding to the demultiplexer (not shown). However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 2720 may be omitted from the receiving apparatus 2700.
That is, the multiplexer 2720 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 2710 and outputs the LLR value in the unit of bit.
In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits, the multiplexer 2720 may output the LLR values serially in the unit of bit without changing the order of the LLR values corresponding to the bits of the cell. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits of the cell to perform an inverse operation to the demultiplexing operation of the demultiplexer (not shown) based on Table 27.
The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100, or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 2700.
The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs the values to the decoder 2740.
Specifically, the deinterleaver 2730 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 2730 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.
In this case, the deinterleaver 2730 may include elements as shown in FIG. 37 or 21.
First, as shown in FIG. 37, the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734.
The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs the value to the group twist deinterleaver 2732.
Specifically, the block deinterleaver 2731 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.
That is, the block deinterleaver 2731 may deinterleave by using at least one row formed of a plurality of columns, that is, by writing the LLR value output from the multiplexer 2720 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction.
In this case, when the block interleaver 124 interleaves by dividing a column into two parts, the block deinterleaver 2731 may deinterleave by dividing a row into two parts.
In addition, when the block interleaver 124 performs writing and reading with respect to a bit group which does not belong to the first part in the row direction, the block deinterleaver 2731 may deinterleave by writing and reading a value corresponding to the group which does not belong to the first part in the row direction.
Hereinafter, the block deinterleaver 2731 will be explained with reference to FIG. 38. However, this is merely an example and the block deinterleaver 2731 may be implemented in other methods.
An input LLR vi (0≦i<Nldpc) is written in a ri row and a ci column of the block deinterleaver 2431. Herein, ci=(i mod Nc) and




  
    
      r
      i
    
    =
    
      ⌊
      
        i
        
          N
          c
        
      
      ⌋
    
  
  ,




On the other hand, an output LLR qi(0≦i<Nc×Nr1) is read from a ci column and a ri row of the first part of the block deinterleaver 2431. Herein,




  
    
      c
      i
    
    =
    
      ⌊
      
        i
        
          N
          
            r
            ⁢
            
              
            
            ⁢
            1
          
        
      
      ⌋
    
  
  ,




ri=(i mod Nr1).

In addition, an output LLR qi(Nc×Nr1≦i<Nldpc) is read from a ci column and a ri row of the second part. Herein,




  
    
      c
      i
    
    =
    
      ⌊
      
        
          (
          
            i
            -
            
              
                N
                c
              
              ×
              
                N
                
                  r
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
          )
        
        
          N
          
            r
            ⁢
            
              
            
            ⁢
            2
          
        
      
      ⌋
    
  
  ,




ri=Nr1+{(i−Nc×Nr1) mode Nr2}.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2731 and outputs the value to the group deinterleaver 2733.
Specifically, the group twist deinterleaver 2732 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and may perform the interleaving operation of the group twist interleaver 123 inversely.
That is, the group twist deinterleaver 2732 may rearrange the LLR values of the same group by changing the order of the LLR values existing in the same group. When the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 2732 may be omitted.
The group deinterleaver 2733 (or the group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 2732 and outputs the value to the parity deinterleaver 2734.
Specifically, the group deinterleaver 2733 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.
That is, the group deinterleaver 2733 may rearrange the order of the plurality of bit groups in bits group wise. In this case, the group deinterleaver 2733 may rearrange the order of the plurality of bit groups in bits group wise by applying the interleaving method of Tables 9 to 20 inversely according to a length of the LDPC codeword, a modulation method and a code rate.
The parity deinterleaver 2734 performs parity deinterleaving with respect to the output value of the group deinterleaver 2733 and outputs the value to the decoder 2740.
Specifically, the parity deinterleaver 2734 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 2734 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 may deinterleave the LLR values corresponding to the parity bits in an inverse method of the parity interleaving method of Equation 8.
However, the parity deinterleaver 2734 may be omitted according to the decoding method and implementation of the decoder 2740.
The deinterleaver 2730 may include a block-row deinterleaver 2735, a group twist deinterleaver 2732, a group deinterleaver 2733 and a parity deinterleaver 2734, as shown in FIG. 39. In this case, the group twist deinterleaver 2732 and the parity deinterleaver 2734 perform the same functions as in FIG. 37, and thus, a redundant explanation is omitted.
The block-row deinterleaver 2735 deinterleaves the output value of the multiplexer 2720 and outputs the value to the group twist deinterleaver 2732.
Specifically, the block-row deinterleaver 2735 is an element corresponding to the block-row interleaver 125 provided in the transmitting apparatus 100 and may perform the interleaving operation of the block-row interleaver 125 inversely.
That is, the block-row deinterleaver 2735 may deinterleave by using at least one column formed of a plurality of rows, that is, by writing the LLR values output from the multiplexer 2720 in each column in the column direction and reading each row of the plurality of columns in which the LLR value is written in the column direction.
However, when the block-row interleaver 125 performs writing and reading with respect to a bit group which does not belong to the first part in the column direction, the block-row deinterleaver 2735 may deinterleave by writing and reading a value corresponding to the bit group which does not belong to the first part in the column direction.
The group deinterleaver 2733 deinterleaves the output value of the group twist deinterleaver 2732 and outputs the value to the parity deinterleaver 2734.
Specifically, the group deinterleaver 2733 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.
That is, the group deinterleaver 2733 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 2733 may rearrange the order of the plurality of bit groups in bits group wise by applying the interleaving method of Tables 34 to 45 inversely according to a length of the LDPC codeword, a modulation method and a code rate.
Although the deinterleaver 2730 of FIG. 36 includes three (3) or four (4) elements as shown in FIG. 37 or 39, operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups Xa, Xb, Xc, Xd, Xe, Xf, Xg, Xh, Xi, Xj constitute a single modulation symbol, the deinterleaver 2730 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.
For example, when the code rate is 6/15 and the modulation method is 1024-QAM, the group deinterleaver 2733 may perform deinterleaving based on Table 9.
In this case, bits each of which belongs to each of bit groups X66, X59, X22, X15, X106, X97, X74, X88, X132, X134 constitute a single modulation symbol. Since one bit in each of the bit groups X66, X59, X22, X15, X106, X97, X74, X88, X132, X134 constitutes a single modulation symbol, the deinterleaver 2730 may map bits onto decoding initial values corresponding to the bit groups X66, X59, X22, X15, X106, X97, X74, X88, X132, X134 based on the received single modulation symbol.
The decoder 2740 may perform LDPC decoding by using the output value of the deinterleaver 2730. To achieve this, the decoder 2740 may include an LDPC decoder (not shown) to perform the LDPC decoding.
Specifically, the decoder 2740 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 2730.
For example, the decoder 2740 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.
The decoder 2740 may use a parity check matrix when performing the LDPC decoding. In this case, an information word submatrix in the parity check matrix is defined as in Tables 4 to 20 according to a code rate and a length of the LDPC codeword, and a parity submatrix may have a dual diagonal configuration.
In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 2700 or may be provided by the transmitting apparatus 100.
FIG. 40 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.
First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S3010). In this case, in the LDPC encoding, a parity check matrix in which an information word submatrix is defined by Tables 4 to 8 and a parity submatrix has a dual diagonal configuration (that is, the parity check matrix of FIG. 20) may be used, or a parity check matrix which is row and column permutated from the parity check matrix of FIG. 20 based on Equations 4 and 5 (that is, the configuration of FIG. 21) may be used.
Thereafter, the LDPC codeword is interleaved (S3020).
Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S3030). In this case, bits included in a predetermined number of bit groups from among the plurality of bit groups of the LDPC codeword may be mapped onto a predetermined bit of a modulation symbol.
In this case, each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of Nldpc and Kldpc and may be determined to satisfy Qldpc=(Nldpc−Kldpc)/M. Herein, Qldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nldpc is a length of the LDPC codeword, and Kldpc is a length of information word bits of the LDPC codeword.
Operation S3020 may include interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging the order of the plurality of bit groups in bits group wise, and interleaving the plurality of bit groups the order of which has been rearranged.
Specifically, the order of the plurality of bit groups may be rearranged in bits group wise based on the above-described Equation 15 presented above. In Equation 15, π(j) is determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.
For example, when the LDPC codeword has a length of 64800, the modulation method is 1024-QAM, and the code rate is 6/15, π(j) may be defined as in Table 9 presented above.
In another example, when the LDPC codeword has a length of 64800, the modulation method is 1024-QAM, and the code rate is 8/15, π(j) may be defined as in Table 10 presented above.
In another example, when the LDPC codeword has a length of 64800, the modulation method is 1024-QAM, and the code rate is 12/15, π(j) may be defined as in Table 13 presented above.
However, this is merely an example. π(j) may be defined as in Tables 11 or 12 described above.
In addition, Equation 16 may be used in rearranging the order of the plurality of bit groups in bits group wise. In this case, π(j) may be defined as in Tables 15 to 20 described above.
The plurality of bit groups the order of which has been rearranged may be interleaved by writing the plurality of bit groups in each of the plurality of columns in the column direction in bit group wise, and reading each row of the plurality of columns in which the plurality of bit groups are written in bits group wise in the row direction.
In this case, from among the plurality of bit groups, at least some bit group which can be written in each of the plurality of columns in bits group wise is written in each of the plurality of columns serially, and then, the other bit groups are divided and written in the other areas which remain in each of the plurality of columns after the at least some bit group has been written in bits group wise.
In operation S3020, the interleaving may be performed in other methods in addition to the above-described method.
Specifically, the interleaving may be performed by using Equation 17 and Tables 29 to 34 described above, or may be performed by using Equation 18 and Tables 35 to 40 described above.
In these cases, the order of the plurality of bit groups may be rearranged in bits group wise such that an arrangement unit, in which at least one bit groups including bits to be mapped onto the same modulation symbol is serially arranged in bits group units, is repeated.
When a plurality of bit groups are interleaved, the interleaving may be performed by writing, in each row, at least one bit group including bits to be mapped onto a same modulation symbol from among the plurality of bit groups the order of which has been rearranged, in the row direction, and reading each column of the row in which the at least one bit group is written in the column direction.
FIG. 41 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment.
Referring to FIG. 41, a receiving apparatus 3800 may comprise a controller 3810, an RF receiver 3820, a demodulator 3830 and a service regenerator 3840.
The controller 3810 determines an RF channel and a PLP through which a selected service is transmitted. The RF channel may be identified by a center frequency and a bandwidth, and the PLP may be identified by its PLP ID. A specific service may be transmitted through at least one PLP included in at least one RF channel, for each component constituting the specific service. Hereinafter, for the sake of convenience of explanation, it is assumed that all of data needed to play back one service is transmitted as one PLP which is transmitted through one RF channel. In other words, a service has only one data obtaining path to reproduce the service, and the data obtaining path is identified by an RF channel and a PLP.
The RF receiver 3820 detects an RF signal from an RF channel selected by a controller 3810 and delivers OFDM symbols, which are extracted by performing signal processing on the RF signal, to the demodulator 3830. Herein, the signal processing may include synchronization, channel estimation, equalization, etc. Information required for the signal processing may be a value predetermined by the receiving apparatus 3810 and a transmitter according to use and implementation thereof and included in a predetermined OFDM symbol among the OFDM symbols and then transmitted to the receiving apparatus.
The demodulator 3830 performs signal processing on the OFDM symbols, extracts user packet and delivers the user packet to a service reproducer 3740, and the service reproducer 3840 uses the user packet to reproduce and then output a service selected by a user. Here, a format of the user packet may differ depending on a service implementation method and may be, for example, a TS packet or a IPv4 packet.
FIG. 42 is a block diagram illustrating a demodulator according to an exemplary embodiment.
Referring to FIG. 42, a demodulator 3830 may include a frame demapper 3831, a BICM decoder 3832 for L1 signaling, a controller 3833, a BICM decoder 3834 and an output handler 3835.
The frame demapper 3831 selects a plurality of OFDM cells constituting an FEC block which belongs to a selected PLP in a frame including OFDM symbols, based on control information from the controller 3833, and provides the selected OFDM cells to the BICM decoder 3834. The frame demapper 3831 also selects a plurality of OFDM cells corresponding to at least one FEC block which includes L1 signaling, and delivers the selected OFDM cells to the BICM decoder 3832 for L1 signaling.
The BICM decoder for L1 signaling 3832 performs signal processing on an OFDM cell corresponding to an FEC block which includes L1 signaling, extracts L1 signaling bits and delivers the L1 signaling bits to the controller 3833. In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and a process of using the extracted LLR value to decode the LDPC codeword.
The controller 3833 extracts an L1 signaling table from the L1 signaling bits and uses the L1 signaling table value to control operations of the frame demapper 3831, the BICM decoder 3834 and the output handler 3835. FIG. 42 illustrates that the BICM decoder 3832 for L1 signaling does not use control information of the controller 3833. However, when the L1 signaling has a layer structure similar to the layer structure of the above described L1 pre signaling and L1 post signaling, it is obvious that the BICM decoder 3832 for L1 signaling may be constituted by at least one BICM decoding block, and operation of this BICM decoding block and the frame demapper 3831 may be controlled by L1 signaling information of an upper layer.
The BICM decoder 3834 performs signal processing on the OFDM cells constituting FEC blocks which belong to a selected PLP to extract BBF (Baseband frame)s and delivers the BBFs to the output handler 3835. In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and an operation of using the extracted LLR value to decode the LDPC codeword, which may be performed based on control information output from the controller 3833.
The output handler 3835 performs signal processing on a BBF, extracts a user packet and delivers the extracted user packet to a service reproducer 3840. In this case, the signal processing may be performed based on control information output from the controller 3833.
According to an exemplary embodiment, the output handler 3835 comprises a BBF handler (not shown) which extracts BBP (Baseband packet) from the BBF.
FIG. 43 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.
It is assumed that service information on all services selectable by a user are acquired at an initial scan (S4010) prior to the user's service selection (S4020). Service information may include information on a RF channel and a PLP which transmits data required to reproduce a specific service in a current receiving apparatus. As an example of the service information, program specific information/service information (PSI/SI) in an MPEG2-TS is available, and normally can be achieved through L2 signaling and an upper-layer signaling.
In the initial scan (S4010), comprehensive information on a payload type of PLPs which are transmitted to a specific frequency band. As an example, there may be information on whether every PLP transmitted to the frequency band includes a specific type of data.
When the user selects a service (S4020), the receiving apparatus transforms the selected service to a transmitting frequency and performs RF signaling detection (S4030). In the frequency transforming operation (S4020), the service information may be used.
When an RF signal is detected, the receiving apparatus performs an L1 signaling extracting operation from the detected RF signal (S4050). Then, the receiving apparatus selects a PLP transmitting the selected service, based on the extracted L1 signaling, (S4060) and extracts a BBF from the selected PLP (S4070). In S4060, the service information may be used.
The operation to extract a BBF (S4070) may include an operation of demapping the transmitted frame and selecting OFDM cells included in a PLP, an operation of extracting an LLR value for LDPC coding/decoding from an OFDM cell, and an operation of decoding the LDPC codeword using the extracted LLR value.
The receiving apparatus, using header information of an extracted BBF, extracts a BBP from the BBF (S4080). The receiving apparatus also uses header information of an extracted BBP to extract a user packet from the extracted BBP (S4090). The extracted user packet is used to reproduce the selected service (S4100). In the BBP extraction operation (S4080) and user packet extraction operation (S4090), L1 signaling information extracted in the L1 signaling extraction operation may be used.
According to an exemplary embodiment, the L1 signaling information includes information on types of a user packet transmitted through a corresponding PLP, and information on an operation used to encapsulate the user packet in a BBF. The foregoing information may be used in the user packet extraction operation (S1480). Specifically, this information may be used in an operation of extracting the user packet which is a reverse operation of encapsulation of the user packet in the BBF. In this case, process for extracting user packet from the BBP (restoring null TS packet and inserting TS sync byte) is same as above description.
A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided. The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.
At least one of the components, elements or units represented by a block as illustrated in FIGS. 19, 22, 31, 32, 36, 37 and 39 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of these components, elements or units may be combined into one single component, element or unit which performs all operations or functions of the combined two or more components, elements of units. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.
Although a bus is not illustrated in the block diagrams of the transmitting apparatus and the receiving apparatus, communication may be performed between each element of each apparatus via the bus. In addition, each apparatus may further include a processor such as a Central Processing Unit (CPU) or a microprocessor to perform the above-described various operations.
The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

## Claims

1. A transmitting apparatus comprising:
a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits according to a code rate of 12/15 and a code length of 64800;
an interleaver configured to interleave an LDPC codeword comprising the input bits and the parity bits; and
a mapper configured to map the interleaved LDPC codeword onto constellation points for 1024-QAM,
wherein the interleaver comprises:
a parity interleaver configured to interleave the parity bits; and
a group-wise interleaver configured to split an LDPC codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups and interleave the plurality of bit groups,

wherein the group-wise interleaver is configured to interleave the plurality of bit groups using the following equation:


Yj=Xπ(j)for(0≦j<Ngroup),


where Xj is a jth bit group among the plurality of bit groups, Yj is an interleaved jth bit group, Ngroup is a total number of the plurality of bit groups, and π(j) denotes a permutation order for the group-wise interleaving, and
wherein the π(j) is defined as follows:













Order of group-wise interleaving



π(j) (0 ≦ j < 180)






































Code 
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12/15
91
19
11
106
14
40
20
67
32
22
31
23
78
68
79
141
117
95
88
136
52
121
1



133
4
2
21
122
38
12
69
111
81
82
58
46
112
60
33
73
53
92
75
48
47
110



80
76
138
87
85
65
130
57
102
83
64
86
100
39
49
125
108
119
6
118
35
61
71



30
45
94
26
116
98
37
55
44
70
25
7
34
114
135
128
137
84
51
28
97
27
89



29
62
50
139
56
109
77
59
127
142
96
105
99
90
13
124
120
115
126
143
149
74
41



178
129
18
131
42
165
101
134
36
140
132
103
72
164
93
54
166
43
123
113
0
154
10



63
107
162
157
66
104
17
147
167
174
179
3
173
160
155
161
152
156
177
24
170
9
159.



16
15
148
5
146
163
172
175
151
169
176
150
153
171
158
168
144
8
145

2. The transmitting apparatus of claim 1, wherein each of the plurality of bit groups comprises 360 bits.

3. The transmitting apparatus of claim 1, wherein π(j) is determined based on at least one of the code length, a modulation method for the mapping and the code rate.