EXHIBIT 5

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USOO678 1858B2 

(12) United States Patent (10) Patent No.: US 6,781,858 B2 

Fricke et al. (45) Date of Patent: Aug. 24, 2004 

(54) CUBIC MEMORY ARRAY 5,751,012 A 5/1998 Wolstenholme et al. 

5,821,558 A 10/1998 Han et al. 

(75) Inventors: Peter Fricke, Corvallis, OR (US); Andrew L. Van Brocklin, Corvallis (List continued on next page.) 

OR (US); Daryl Anderson, Corvallis, FOREIGN PATENT DOCUMENTS 

OR (US) EP OO734.86 3/1983 

(73) Assignee: Hewlett-Packard Development E. : A: 3.1999 f2002 

Company, L.P., Houston, TX (US) GB 10O3489 5/1963 

(*) Notice: Subject to any disclaimer, the term of this OTHER PUBLICATIONS 

patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. Victor, W.C. Chan et all “Multiple Layers of CMOS Inte 

grated Circuites Using Recrystallized Silicon Film” IEEE 

Electron Device Letters, V. 22(2), Feb. 2001, pp 77-79. 

(21) Appl. No.: 10/650,895 Thomas H. Lee, “A Vertical Leap for Microchips,” Scientific 

(22) Filed: Aug. 29, 2003 American, Jan. 2002, pp 53–59. 

Esmat Hamdy et al., “Dielectric based antifuses for logic and 

(65) Prior Publication Data memory ICs” IEEE International Electron Devices Meeting, 

IEDM 88, Aug. 1988, pp 786–789. 

Chenming Hu, “Interconnect devices for field program 

Related U.S. Application Data mable gate array.” IEEE International Electron Devices 

Meeting, IEDM 92 Apr. 1992, pp 591-594. 

(63) Continuation of application No. 10/116,213, filed on Apr. 2, Jonathan Green et al., “Antifuse Field Programmable Gate 

2002, now Pat. No. 6,643,159. Arrays”, Proc IEEE vol. 81(7), Jul. 1993, pp 1042–1056. 

Vivek D. Kulkarni et al., “Patterning of Submicron Metal 

US 2004/0042313 A1 Mar. 4, 2004 

7 

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - G11C 5. S.". Features and Pillars in Multil vel Metallization”, J. Elec 

( ) O - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - f s / tochem. Soc. V.135(12), Dec. 1988, pp 3094-3098. 

(58) Field of Search ............................ 365/51, 63, 105, 365/96 Primary Examiner Van Thu Nguyen 

ASSistant Examiner J. H. Hur 

(56) References Cited (74) Attorney, Agent, or Firm Timothy F. Myers 

U.S. PATENT DOCUMENTS (57) ABSTRACT 

3.271,591 A 9/1966. Ovshinsky A cubic memory array is fabricated on a Substrate having a 

3,530,441 A 9/1970. Ovshinsky planar Surface. The cubic memory array includes a plurality 

3,641,516 A 2, 1972 Castrucci et al. of first Select-lines organized in more than one plane parallel 4,287,571 A 9/1981 Chakravarti et al. to the planar Surface. A plurality of Second Select-lines is 4,499,557 A 2/1985 Holmberg et al. formed in pillars disposed orthogonal to the planer Surface 4,599,705 A 7/1986 Holmberg et al. 5,191,550 A 3/1993 Kubota ........................ 365/96 of the Substrate. A plurality of memory cells are respectively 5.335.219 A 8/1994 Ovshinsky et al. coupled to the plurality of first and plurality of Second 

5,475,253 A 12/1995 Look et al. ................. 257/530 Select-lines. 

5,625.220 A 4/1997 Liu et al. 

5,659,500 A 8/1997 Mehrad 67 Claims, 16 Drawing Sheets 

as W 

Substrate 

 

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US 6,781,858 B2 

Page 2 

U.S. PATENT DOCUMENTS 6,185,121 B1 2/2001 O’Neill 

6,185,122 B1 2/2001 Johnson et al. 

5.835,396 A 11/1998 Zhang 6,351,406 B1 2/2002 Johnson et al. 

36. A f Sasd 6,462.977 B2 10/2002 Butz ........................... 365/63 

2- Y/ -- a f eyyedy 6,504,742 B1 1/2003 Tran et al. 6,002,607 A 12/1999 Dvir 2001/0011776 A1 8/2001 Igarashi et al. 6,004.825. A 12/1999 Seyyedy 2001/0055838 A1 12/2001 Walker et al. 

6,026,017 A 2/2000 Wong et al. 2002/0041525 A1 4/2002 But 

6,033,955 A 3/2000 Kuo et al. Z 

6,034.882 A 3/2000 Johnson et al. 

6,111,302 A 8/2000 Zhang et al. * cited by examiner 

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U.S. Patent Aug. 24, 2004 Sheet 1 of 16 US 6,781,858 B2 

32 34 

Address Data 30 

28 

Read/ Column Decoder 

E a Se 18 

18a 18) 18C 

level O 

Wordline 

DeCOder 

20 

Fig. 1 

 

 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 2 of 16 US 6,781,858 B2 

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - W 

22 76.16 (level 1 (54) A. M 

12 

10 

14 (level 0 (52) 

 

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U.S. Patent Aug. 24, 2004 Sheet 3 of 16 US 6,781,858 B2 

 

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U.S. Patent Aug. 24, 2004 Sheet 4 of 16 US 6,781,858 B2 

7 7 

W 

few 

W 

2. 19 

nown Hist 

town LD LD first Iran. it's 

OWO2 

rown 

FOW 

 

 

 

 

 

 

 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 5 of 16 US 6,781,858 B2 

y 2– 

42b 7 W / . W . s 

Middle Vertical Middle Vetical & 

y Electrode Pillar Electrode Pillar 

V bit line bit line 2 

35W5% % 

% 

LD 

----------mm-armesse-a-s-s--rearmummyam 

2. 24a 24C ------------------- 

42a / W x - Middle Wertical Middle Vetical & 

y Electrodel Pillar Electrode Pillar 

g bit line bit line 

Fig O 9 Next Set of 

Vertical Pillars 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 6 of 16 US 6,781,858 B2 

40 

25b 25d 

Middle W Middle W 

lectrode Vertical 42 lectrode Vertical 

Conductor 18b Conductor 

%2. (to 

25a 

< LD 18a %2. 

25C 

( 

42a Middle W 42d Middle W 

lectrode Vertical lectrode Vertical 

Conductor, Conductor 

20a 20b 

Fig. 10 

42b 

 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 7 of 16 US 6,781,858 B2 

50a 

2-ra regal 

22 rigal LD OW ILD ILD 

owan Town tries ity 

 

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U.S. Patent Aug. 24, 2004 Sheet 8 of 16 US 6,781,858 B2 

40 40 23 40 40 40 

23 4 ZAZ. LDV 24a24b % 2 

40 W / W \, 

COLO ) / 

19 18 18b. 19b a Fig. 12 

19a --------------------------------- Y --------------------------- '-----Y - w 

-------------------------------- f-------------------------- ^ 

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40 COLO - 7 

19a 0-1 

COL 1 

 

 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 9 of 16 US 6,781,858 B2 

40 Fig.16 

 

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U.S. Patent Aug. 24, 2004 Sheet 10 of 16 US 6,781,858 B2 

Towa R42s Will 5 

IP, M-23 Yal LD w Fl LD 

Iran. "if" / 2nwall will / El regul M 

Fig. 17 

 

 

 

 

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2d 2 

W 2 W 18b 

Vertical % Vertical 

P 2 Pilar 

Y 2 

2 'ad Wo% i? 

C. 18C 

 illar 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 12 of 16 US 6,781,858 B2 

18a 18b. 

I ILD L // 

ILD W LD W ILD % 54 28°N ILD was rwal LD ILD % 

23b W W 52 

wan Will wn % 

23a 40 rwal W Wil W win 10 

Substrate with Control Elements 

W wall wn Wen % 

ris wril V in E% W in a wra % Wall W wn W Will 

Substrate 

W 

OWC 

23C 

23b 

23a 

Fig. 21 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 13 of 16 US 6,781,858 B2 

18a 18b. 

23C 23f 23i 23 

ROW a2 / ROW c2 

23e Row? 23k 

ROW C1 

23 

t ROW CO 

Fig. 22 34 

Data 

Top Sub-Column connect 

8b. 8a LD 

III 

Pilar Pillar 

-- 

18b 

89 

Bottom Sub-Column connect 

Bitline to sense amp circuitry - - 

via Gate via Gate 

N N N 

\- 60a - 

Si Substrate 

 

 

 

 

 

 

 

 

 

 

 

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U.S. Patent Aug. 24, 2004 Sheet 14 of 16 US 6,781,858 B2 

Computer 

System 

Fig. 25 

 

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U.S. Patent Aug. 24, 2004 Sheet 15 of 16 US 6,781,858 B2 

 

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U.S. Patent Aug. 24, 2004 Sheet 16 of 16 US 6,781,858 B2 

Form an array of Wordlines in a 

plane parallel to a substrate 

Form an array of bitlines 

normal to the Wordline plane 

Form an array of memory cells 

between each WOrdline and 

each bitline 

Fig. 27 

Apply an insulator on a 

Substrate 

Apply a first conductor in a 

plane parallel to Substrate 

Create a Control element on 

the first Conductor 

Apply a second Conductor orthogonal to 

plane of the first conductor 

Create a memory storage element between the 

Second Conductor and the Control element 

Fig. 28 

82 

83 

84 

85 

86 

 

 

 

 

 

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US 6,781,858 B2 

1 

CUBC MEMORY ARRAY 

This is a continuation of application Ser. No. 10/116,213 

filed on Apr. 2, 2002, now U.S. Pat. No. 6,643,159. 

BACKGROUND OF THE INVENTION 

Personal computers, WorkStations, graphic Subsystems of 

displays, electronic games and other electrical devices all 

include memory Systems for Storing data. An ever 

increasing demand exists for larger and faster memory 

Systems. Attributes of memory technologies include data 

access time (i.e. speed), cost, reliability, Size (i.e. density), 

and electrical power dissipation. Several memory technolo 

gies exist Such as Floppy drives, hard drives, CD/DVD 

drives and Semiconductor memories. Semiconductor memo 

ries include DRAMS, SRAMs, ROMs, PROMs, OTPs, 

EEPROMs, FLASH, and VRAM memories to just name a 

few. While microprocessor-processing power (i.e. speed) 

has increase Significantly in keeping with Moore's Law, the 

memory devices that communicate with the microprocessor have only been able to keep up with increasing density and 

not speed. Part of the problem with increasing the Speed of 

memory devices is that as the density of memory cells 

increase within a given memory technology, capacitive 

delays, Sense circuits and conventional memory layout orga 

nizations keep the access time improvements minimal. If the 

access times cannot be improved along with the density improvements made to the memory, the development of 

computer Systems will falter. Therefore a need exists for a 

new memory architecture that not only increases density but 

data access time as well. 

SUMMARY OF THE INVENTION 

A cubic (3D) memory array is fabricated on a substrate 

having a planar Surface. The cubic memory array includes a 

plurality of first Select-lines organized in more than one 

plane parallel to the planar Surface. A plurality of Second 

Select-lines is formed in pillars disposed orthogonal to the 

planer Surface of the Substrate. A plurality of memory cells 

are respectively coupled to the plurality of first and plurality 

of Second Select-lines. 

BRIEF DESCRIPTION OF THE DRAWINGS 

The invention is better understood with reference to the 

following drawings. The elements of the drawings are not 

necessarily to Scale relative to each other. Rather, emphasis 

has instead been placed upon clearly illustrating the inven 

tion. Furthermore, like reference numerals designate corre 

sponding Similar parts through the Several views. 

FIG. 1 is a Schematic of a memory array for at least one 

embodiment of the invention. 

FIG. 2 is a Schematic diagram of the physical layout of a 

memory array in one embodiment of the invention. 

FIG. 3 is a diagram showing an exemplary memory cell 

used in the memory array of FIG. 2. 

FIG. 4 is an exemplary embodiment of the memory cell 

shown in FIG. 3. 

FIG. 5 is another exemplary embodiment of the memory 

cell shown in FIG. 3. 

FIG. 6 is another exemplary embodiment of the memory 

cell shown in FIG. 3. 

FIG. 7 is a partially exploded view of an embodiment of 

the invention for one vertical pillar column and multiple row 

lines. 

15 

25 

35 

40 

45 

50 

55 

60 

65 

2 

FIG. 8 is a partially exploded view of an exemplary 

embodiment of the invention. 

FIG. 9 is a top view of the exemplary embodiment shown 

in FIG. 8. 

FIG. 10 is an exemplary top view of an alternative 

embodiment of the invention using a Serpentine layout. 

FIG. 11 is a partially exploded view of an alternative 

embodiment of the invention. 

FIG. 12 is a perspective view of an alternative embodi 

ment of the invention. 

FIG. 13 is a perspective view of the embodiment shown 

in FIG. 12 having multiple layers of memory cells. 

FIG. 14 is an exemplary embodiment of a set of dual 

memory cells. 

FIG. 15 is another exemplary embodiment of a set of dual 

memory cells. 

FIG. 16 is another exemplary embodiment of a set of dual 

memory cells. 

FIG. 17 is a partially exploded view of an exemplary 

memory array that incorporates the basic structure shown in 

FIG. 12. 

FIG. 18 is a top view of the embodiment shown in FIG. 

17. 

FIG. 19 is a top view of an alternative embodiment of the 

invention using a Serpentine layout with respect to the basic 

structure shown in FIG. 18. 

FIG. 20 is a perspective view of an alternative embodi 

ment of the invention. 

FIG. 21 is a partially exploded view of an alternative 

embodiment of the invention. 

FIG. 22 is a partial schematic of an alternative embodi 

ment using dual memory cells. 

FIG. 23 is a side view of an exemplary embodiment of the 

invention. 

FIG. 24 is a exemplary layout of a memory carrier that 

incorporates at least one embodiment of the invention. 

FIG. 25 is a block diagram of an electronic device, a 

computer System, which incorporates at least one embodi 

ment of the invention. 

FIG. 26 is an exemplary partial perspective View of an 

embodiment of an embedded cubic memory array. 

FIG. 27 is an exemplary flow chart of the basic steps used 

to implement embodiments of the invention. 

FIG. 28 is an exemplary flow chart for the basic steps to 

create a memory cell that incorporates the invention. 

DETAILED DESCRIPTION OF THE 

PREFERRED EMBODIMENT 

The embodiments described herein of a 3D memory architecture utilize a vertical pillar to form either the row or 

column lines used to Select a particular memory cell within 

an array of memory cells. This architecture creates a cubed 

array Structure out of a plurality of memory cells that is very 

Volumetrically Space efficient, faster, and easier to manufac 

ture than previous 3D-architectures that Simply expand conventional cross-point memory arrays by Stacking them. 

One embodiment described herein involves write-once 

arrays, also known as one-time programmable (OTP) 

memory or write-once read-many (WORM) memory. When 

implementing write-once arrays using the Vertical pillars as 

bit-lines (or alternatively word-lines) in a cubic (i.e. having three dimensions, although not each necessarily the same 

length) memory array, a tunnel junction is formed on the 

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US 6,781,858 B2 

3 

vertical pillar at the intersection of the horizontal word-lines 

and the vertical bit-lines. Preferably included in the forma 

tion of the cubic memory array is a control element for each 

Storage element that is physically adjacent to the Storage 

element and in series with it between the horizontal word 

lines and the vertical bit-lines. It should be understood by those of ordinary skill in the art that the word-lines might be 

made vertical and the column lines be made horizontal 

without departing from the Scope and Spirit of the invention. 

For purposes of clarity in describing the invention in this 

application, the vertical Select lines will be referred to as 

columns or bits lines and the horizontal select lines will be 

referred to as word-lines or row lines. Alternatively, the 

horizontal Select lines may be commonly referred to as drive 

lines and the Vertical Select lines as Sense lines. Because the 

orientation of the drive and Sense lines are interchangeable, 

there is in actuality a set of first Select lines and a set of 

Second Select lines that are disposed in Separate planes that 

are orthogonal to each other to form the cubic memory array. 

One of the first or second select lines form a vertical pillar with respect to the plane of the substrate on which the 

memory array is formed. 

A memory array is fabricated on a Substrate that defines 

a plane. The memory array includes a plurality of memory 

cells Stacked vertically. The memory cells include a dielec 

tric layer forming an insulating Surface and a wordline 

disposed parallel to the plane of the Substrate on the dielec 

tric layer. The memory cell preferably has a control element 

Surrounding the Wordline and a memory Storage element 

Surrounding at least a portion of the control element. The 

control element has a first croSS Sectional area. The Storage 

element has a second cross-sectional area. Preferably the 

croSS Sectional area of the Storage element is preferably Substantially Smaller than the croSS Sectional area of the 

control element So that the Storage element can change its 

state while the control element remains unaffected. Prefer 

ably the control element and the Storage element are fabri 

cated as Similar types of devices, for example, tunnel 

junction devices. Alternatively, when a phase-change mate 

rial is used for the Storage element, the cross-sectional area 

of the Storage element may be less, the same, or larger than 

the cross-sectional area of the control element. Preferably, 

the Storage element cross-sectional area is less than the 

control element cross-sectional area in order to minimize 

power and increase the Speed of changing the memory State. 

The memory cell includes a vertical pillar, Substantially 

orthogonal to the plane of the Substrate and contacting the 

memory Storage element. 

With this vertical pillar structured cubic memory array, 

the number of memory Storage elements is only limited by 

the aspect ratio of Semiconductor processes to vertically 

Stack columns, control elements and State change memory 

elements for each pillar. One feature of this architecture is 

that Stacking of multiple cubic arrays allows for larger arrayS 

than that possible with conventional Semiconductor pro 

cesses. With this 3D-architecture of vertical pillars, up to 20 

or more horizontal word-lines can be accessed per each 

vertical bit-line. 

Further, the cubic memory array can be embedded with 

conventional integrated circuits Such as microprocessors, graphic processors, and Storage processors to name a few. 

For instance, a traditional CPU uses large arrays of memory 

for internal level 1 and level 2 cache memory. These cache 

memories typically consume a large area within a traditional 

processor layout. By using a cubic memory array that is 

disposed on top of the processor core computer circuits, a 

Smaller die Size in terms of area is achieved. 

15 

25 

35 

40 

45 

50 

55 

60 

65 

4 

Conventional memory Storage elements are typically implemented as parallel plate structures (or vertical capaci tive wells) whose minimum area is traditionally limited by the minimum Semiconductor photolithography process 

geometries and the need for a transistor based control FET. 

The 3D-architecture disclosed herein allows for the forming of memory Storage elements in contact with the vertical 

pillars at the interSection of the horizontal and Vertical Select 

lines. This formation allows for a memory Storage element 

that has an area determined by the height of the edge of the 

horizontal select lines and the width of the vertical select 

pillar. Therefore, the area of the memory Storage element can 

be greatly reduced in this architecture thus allowing for 

faster acceSS Speeds and less energy required when perform ing a fusing operation for tunnel junction or dielectric 

rupture devices. Further, when the memory Storage element 

is formed using a tunnel junction on the Vertical edges of the 

horizontal and vertical Select lines, the effects of defects 

found in conventional planar tunnel junctions is greatly 

reduced. By having the memory drive and Sense Select lines 

arranged in horizontal and vertical planes, respectively, the 

capacitance between the drive and Sense Select lines is 

reduced. This reduced capacitance allows for faster access 

Speeds for the memory array. 

A cubic memory array of memory cells is created using 

one of any various Semiconductor devices for the Storage 

and control elements that interface to the vertical pillars, which are used as part of the memory Selection circuitry. 

Most implementations of the 3D-architecture will be per 

formed using conventional Semiconductor equipment and 

Silicon Substrates as Starting materials. However, the Semi 

conductor devices of the present invention are applicable to 

a broad range of Semiconductor devices technologies and 

can be fabricated from a variety of Semiconductor materials. 

The following description discusses Several presently pre 

ferred embodiments of the semiconductor devices of the 

present invention as implemented in Silicon Substrates, Since 

the majority of currently available Semiconductor devices 

are fabricated in Silicon Substrates and the most commonly 

encountered applications of the present invention will 

involve silicon Substrates. Nevertheless, the present inven 

tion may also advantageously be employed in gallium 

arsenide, germanium, and other Semiconductor materials. 

Accordingly, the present invention is not intended to be 

limited to those devices fabricated in Silicon Semiconductor 

materials, but will include those devices fabricated in one or more of the available Semiconductor materials and technolo 

gies available to those skilled in the art, Such as thin-film 

transistor (TFT) technology using polysilicon on glass Sub 

Strates. Other Substrates that are useful in producing the 

memory arrays of the invention include plastic and cellulose 

materials. 

It should be noted that the drawings are not true to Scale. 

Further, various parts of the active elements have not been 

drawn to Scale. Certain dimensions have been exaggerated in relation to other dimensions in order to provide a clearer 

illustration and understanding of the present invention. 

In addition, although the embodiments illustrated herein are Sometimes shown in two-dimensional views with vari 

ous regions having depth and width, it should be clearly 

understood that these regions are illustrations of only a 

portion of a device that is actually a three-dimensional 

Structure. Accordingly, these regions will have three 

dimensions, including length, width, and depth, when fab 

ricated on an actual device. Moreover, while the present invention is illustrated by preferred embodiments directed to 

active devices, it is not intended that these illustrations be a 

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US 6,781,858 B2 

S 

limitation on the Scope or applicability of the present inven 

tion. It is not intended that the active devices of the present invention be limited to the physical Structures illustrated. 

These Structures are included to demonstrate the utility and 

application of the present invention to presently preferred 

embodiments. 

FIG. 1 is a schematic diagram of a memory circuit 30 in 

which a plurality of memory cells 22 are formed in an array 

shown here as an exemplary two dimensional 4x4 layout. 

Each memory cell 22 is connected to one of a Set of 

word-lines 20 (20a-20d) shown as rows and one of a set of 

bit-lines 18 (18a–18d) shown as columns. The memory circuit 30 is connected to a set of external address lines 32 

and data lines 34. The address lines 32 contain a location in 

an encoded form (preferably binary) for Selecting a particu 

lar memory cell 22 in the array of memory cells to address. 

The wordline decoder 38 interprets some of the address lines 

to decide which row or wordline the particularly selected 

memory cell 22 is located. Typically, only one wordline is 

Selected and driven to a predetermined Voltage level and the 

other wordlines are typically driven to a ground level. The 

address lines 32 are also used by column decoder 36 to select 

a particular bit-line from bit-lines 18 to interface and decode 

the Selected particular memory cell to at least one of data 

lines 34 by sensing the state of the selected memory cell. The 

memory circuit 30 also includes read/write/erase circuitry 28 

that is connected to the wordline decoder 38 and the column 

decoder 36 to provide the appropriate Voltages and timing to 

the Selected and deselected memory cells 22 during each 

operation. It should be noted that the erase operation might 

not be present on all types of memory circuits 30. 

FIG. 1 also illustrates one exemplary organization of the 

array of memory cells 22 to form an embodiment of a cubic 

memory array. In this example, two levels (or alternatively 

two planes) of memory cells 22 are formed, one upon the 

other. The memory cells of each level are preferably Sub 

Stantially aligned with memory cells in the adjacent level. 

Level 0 (52) includes word-lines 20a and 20c. Level 1 (54) includes word lines 20b and 20d. Level 0 (52) and level 1 

(54) are formed into respective planes that are Substantially 

parallel to a substrate surface. Bit lines 18 (18a–18d) are 

formed in another plane that is orthogonal to the planes of 

the wordlines and the Substrate. Thus each of the bit lines 18 

forms a vertical pillar with respect to a horizontal Sub 

Strate. The orientation chosen is for convenience in describ 

ing the invention and the actual orientation of an embodi 

ment is arbitrary. Other arrangements for Selecting the 

organization of the word-lines and column bitlines into a 

cubic array exist and still meet the Spirit and Scope of the 

invention. 

For example, FIG. 2 is an exemplary physical layout of 

the cubic memory array of FIG. 1 that incorporates the 

invention. Here a Substrate 10, Such as a Silicon Substrate, 

forms a planar Surface 12 in which there may be incorpo 

rated control circuitry Such as column decoder 36, wordline 

decoder 38, and read/write/erase circuitry 28 of FIG. 1. 

Disposed on the planar surface 12 of Substrate 10 is a first 

memory plane 14 (such as level 0 (52)) formed of an array of memory cells 22. The first memory plane 14 has rows of 

memory cells 22 that are connected by word-lines 20 as 

shown. Disposed on the first memory plane 14 is a Second 

memory plane 16 (such as level 1 (54)) of memory cells 22 

that are preferably Substantially aligned with the memory 

cells 22 of the first memory plane 14. The two memory 

planes 14, 16 are interconnected using vertical bit-lines 18 

as shown thereby forming a cubic array of memory. A cubic 

array for the purposes of this disclosure is defined as “having 

15 

25 

35 

40 

45 

50 

55 

60 

65 

6 

three dimensions.” The length of each actual dimension of 

the array may be different quantities and an actual cube of 

three equal lengths may not be formed. However, “cubic' is 

used herein in its alternative meaning of “having three 

dimensions' to refer to the basic box like structure of the 

memory array. Actual dimension lengths will vary depend ing on a designer's choice of the number of memory cells 

per plane and the number of planes to be Stacked. 

By using vertical pillars for at least one of the Select lines 

used to address a memory cell 22, the memory cells 22 can 

be Stacked closer together to increase Volumetric efficiency. 

Further, by taking advantage of the StepS used to create the 

cubic memory array, Simplified memory cells 22 can be 

formed. The memory cells 22 include at least one Storage 

element, usually configurable in an on or off State, or 

containing charge that represents an on or off State. 

Alternatively, memory cells 22 may also Store multiple 

States or charges that represent multiple States So that more 

than one bit of information is Stored per memory cell 22. 

FIG. 3 is a block diagram of a representative memory cell 

22. The memory cell 22 includes a Storage element 24 and a control element 26 in series between wordline 20 and 

bitline 18. In this embodiment, preferably storage element 

24 is an antifuse device, Such as a programmable tunnel 

junction device. The antifuSe device preferably is either a 

dielectric rupture type device or a tunnel junction device. 

However, the Storage element 24 can be any device that 

Stores a memory State that can be read out as a changed value 

in resistance, but preferably a tunnel junction device. The 

tunnel junction can be formed from oxidized metal, ther 

mally grown oxide, or deposited oxides or nitrides. The 

storage element may also be optionally embodied with 

Semiconductor materialS Such as poly Silicon, polycrystalline, amorphous, microcrystalline, metal filament 

electro migration, trap induced hysterisis, ferroelectric 

capacitor, Hall effect, and polysilicon resistors. Other 

embodiments of the Storage element include tunneling magneto-resistive, phase-change materials or capacitive ele 

ments Such as floating gates. 

Preferably control element 26 is a current steering device 

that exhibits non-linear behavior between Voltage applied 

acroSS it and the current flowing through it. Alternatively, the 

control element 26 can have linear behavior Such as when 

implemented using a resistor. Preferably control element 26 

is formed of a tunnel junction device or pn, pin, or Schottky 

diodes. Other diodes that can be used include Zener diodes, 

avalanche diodes, tunnel diodes, and a four layer diode Such 

as an Silicon controlled rectifier. Alternatively, the control 

element can be junction field effect or bipolar transistors. 

The control element 26 is sized sufficiently to carry an 

adequate current Such that the State of Storage element 24 

can be changed. Preferably, this sizing is achieved by having 

the croSS Sectional area of the control element 26 be larger 

than the croSS Sectional area of the Storage element 24. The 

control element 26 and the Storage element 24 are preferably of the same device type, for example tunnel junction 

devices, but optionally, different device types can be used, 

Such as diodes and tunnel junction devices, respectively for 

the control and Storage elements. When the control element 

26 is a diode, it is preferably formed using doped polysilicon, amorphous Silicon, or microcrystalline Silicon. 

Therefore, the control element alternatively is selected from 

a group of options including: a recrystallized Semiconductor, 

an amorphous Semiconductor, a polycrystalline 

Semiconductor, a junction field effect transistor, a junction 

field effect transistor with its gate connected to its Source or 

drain, an insulated gate field effect transistor with its gate 

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7 

connected to its source or drain, a four-layer diode, an NPN 

transistor, and a PNP transistor. 

For example, FIGS. 4-6 are illustrations of just a few 

possible embodiments allowing for fabrication of a memory 

cell 22 used in a cubic memory array. 

For instance, FIG. 4 illustrates a first embodiment of a 

memory cell 22 that shows bit-line 18 as a column of 

material made of preferably tungsten (W) that will prefer 

ably be deposited after the control element 26 and Storage 

element 24 are formed. This bit-line 18 is disposed next to 

an insulating layer of dielectric material (ILD) 40. 

Various materials can be used for ILD 40 and include 

Silicon dioxide, Silicon nitride, Oxynitrides, and tetraethy 

lorthosilicate (TEOS) to just name a few. The ILD can be 

deposited using Several different conventional technologies Such as chemical vapor deposition (CVD), atmospheric 

pressure CVD, low pressure CVD, plasma enhanced CVD, physical vapor deposition (PVD), and sputtering. The ILD 

can be planarized using conventional processes Such as 

chemical mechanical polishing (CMP). ILD 40 is used 

throughout this specification to indicate dielectric filler 

material on one or more layers. The actual dielectric material 

may be composed of one or more of the aforementioned 

materials. 

Disposed on the ILD 40 is a wordline 20 preferably 

formed of a conductive thin-film shown as metal 1, for 

instance, aluminum. The wordline 20 is oxidized, either 

Self-Oxidized, thermally grown, or has a deposited oxide. 

The oxide is preferably formed over the entire exposed portion of the wordline 20, preferably over its entire length. 

Preferably, the thickness of the oxide is less than 100 

Angstroms and more preferably less than 50 AngStroms. 

Over a portion of the oxide, another conductive thin-film, 

shown as metal 2 (preferably aluminum), is deposited and 

patterned to form control element 26, a tunnel junction 

device with metal 1 and metal 2 as its electrodes. Metal 2 is 

also called a middle electrode 42 as it is formed electrically 

between the wordline 20 and the bitline 18. Disposed on 

metal 2 and portions of the oxide where the middle electrode 

42 is not present is another layer of ILD 40. A via is etched 

in ILD 40 to locate the vertical pillar. A portion of the middle 

electrode 42 is preferably oxidized or oxide is deposited 

thereon to form the Storage element 24. Finally, the tungsten 

is deposited to form the bitline 18 and it contacts the oxide 

to form the storage element 24 with the middle electrode 42 

and the bitline 18 as the electrodes. 

Preferably the metal 1 (20) has an oxide layer (alumina 

(Al2O) in the case of an aluminum (Al) conductor) that is 

fabricated directly on the top exposed Surface of the entire 

metal 1. Optionally, the metal 1 (20) and metal 2 (42) are 

formed of aluminum, copper, or Silicide and alloys thereof 

although other conductive metals or Semiconductors can be 

used. The oxide layer interfacing with metal 1 and metal 2 

forms the control element 26. Preferably, the fabrication of 

the oxide layer is performed after metal 1 has been etched to 

allow for coverage over the Sidewalls. A tunnel junction 

control element is typically formed by a metal/oxide/metal 

interface and for Some embodiments may be the preferred 

control element. 

When formed using an oxide layer, the Storage element 24 

preferably utilizes electron tunneling or alternatively dielec 

tric rupture dynamics. Most preferably, the electron tunnel 

ing is direct tunneling thereby requiring that the oxide layer 

thickneSS be minimal, Such as about 5 to about 50 Ang 

Stroms. Such a storage element 24 creates an anti-fuse 

Structure with preferable current/voltage characteristics. At a 

1O 

15 

25 

35 

40 

45 

50 

55 

60 

65 

8 

low Voltage potential acroSS the oxide layer, Such as during reading of the memory cell, the current is in the low 

microampere or nanoampere range and is thus efficient for 

power. When the anti-fuse is programmed by creating fila 

ments through the oxide, the current is in the microampere 

or low milliamp range. This change in current levels creates 

a very good signal to noise ratio for Sensing whether the 

oxide is programmed as a logical 0 or 1 State. While these 

current ranges are examples for 0.18 micron geometry that 

can be achieve currently, the actual current levels will vary depending on the actual proceSS geometry used. At higher 

Voltage potentials, Such as during programming, the oxide 

layer begins to have higher current flows due to the tunnel 

ing current. This tunneling current creates a flow of electrons 

that locally heats the Storage element 24, the oxide, and 

forms the conductive filaments through the oxide. When 

Sufficient energy is forced across the oxide barrier to Suffi 

ciently heat the fusing Site, a conducting filament is formed 

through the oxide and the State of the oxide is changed permanently for a one-time programmable Structure. 

Optionally, the oxide layer can be processed to be a dielec 

tric breakdown device rather than a tunnel junction device. 

Alternative State-change technologies can be used for 

Storage element 24. For example, the Storage element 24 can 

be either a read only LeComber or silicide switch, or a 

read/writeable phase-change material. One method of form 

ing a LeComber Switch is to deposit a thin layer of amor 

phous intrinsic Silicon on metal 1, (in this example, metal 1 

is preferably a layer of Chromium (Cr)). Then a separate metal, Such as gold (Ag) is deposited on the amorphous 

intrinsic Silicon. Before programming, the LeComber Switch 

acts as a reversed biased tunnel diode. Creating an enhanced 

concentrated electric field through the amorphous Silicon 

with the invention will cause a conductive path to form or 

allow for hopping conduction, thus creating the anti-fuse. 

One preferable phase-change material for a read/writeable 

(or write/erase/write) state-change element is germanium telluride (GeTe), which can be reversibly changed from a 

Semiconducting (amorphous) to a metallic (crystalline) State 

by heating and cooling it at a proper rate. For example, if the 

GeTe is doped So that it is p-type when in its Semiconducting 

State and is deposited on top of an n-type Semiconductor 

layer, then a large contrast will be seen in the number of 

carriers Swept across the junction if the GeTe is changed to 

its metallic State. By using GeTe or equivalent phase-change 

material, the memory cell is capable of being read-writeable, 

e.g. being capable of Writing, erasing, Writing many times. 

This function increases the utility of the memory cell 

Structure for Some applications. Other phase-change mate 

rials can be substituted for GeTe and still meet the spirit and 

Scope of the invention. Some examples of other preferable 

phase-change materials are chalcogenide alloys Such as: 

GaSb, InSb, InSe, SbTe, GeSb-Tes, InSbTe, GaSeTe, 

SnSbTe, InSbGe, AgInSbTe, (GeSn)SbTe, GeSb(SeTe), 

Test GeissbS and GeSbTe. 

Other antifuSe Structures are possible Such as Silicide 

Switches. Silicide switches are formed with alternatively 

Stacked Silicon and transition metal thin films that change resistance when programmed. Generally, the programming 

process for a Silicide antifuSe is irreversible. Before writing, 

the Stack of transaction metal and Silicon layerS has a first 

resistance. Appropriate row and column lines are Selected to 

force a current through a Selected memory cell. The current 

passing through the Selected memory cell creates Joule heat 

that triggerS and completes the Silicidation reaction. By 

using the concentrated electric field created by the invention, 

current is focused and thus the Joule heat is concentrated in 

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9 

a Smaller area thereby allowing the programming to be 

completed in less time than without the invention. The 

Silicidation reaction causes the resistance of the Selected 

memory cell to change to a much lower value. To read the 

programmed memory cell, a Small Sense current is Supplied 

to a Selected memory cell and the Voltage drop across the 

Selected memory cell is Sensed. Some preferable Silicide 

compounds are NiSi, NiSi, NiSi, PdSi, PdSi, and Pt.Si, 

and Pt.Si. Other possible transition metals in various com 

pounds with silicon include Ti, V, Cr, Mn, Fe, Co, Zr, Nb, 

Mo, Rh, Hf, Ta, W, and Ir. 

FIG. 5 is an alternative embodiment of that shown in FIG. 

4 but which includes an angled Storage element 25 that 

surrounds at least two edges of middle electrode 42. By Surrounding at least two edges of middle electrode 42 an 

enhanced electric field is formed at the intersection of the 

two edges. When Shorting an antifuse, Such as with tunnel 

junction or dielectric breakdown devices used for angled 

Storage element 25, this enhanced electric field allows for a 

lower programming Voltage or lower current for reduced 

total power, and for a faster programming time. In this 

embodiment, an ILD 40 is placed down on a surface 

adjacent and abutting the bit-line 18, preferably made of 

tungsten (W). When the bit-line 18 is deposited, it forms a 

contact Surface over the angled Storage element 25. By having an angled Storage element, the electric field produced 

when a Voltage is applied between the middle electrode 42 

and the bitline 18 is enhanced, thereby allowing for lower 

power requirements in the form a lower programming 

Voltage, lower programming current, or combination 

thereof. Also, the enhanced electric field provides for faster 

programming speed. Otherwise, the construction of the 

memory cell in FIG. 5 is similar to that described for FIG. 

4. 

FIG. 6 is another embodiment of the memory cell 22 in 

which the control element 26 is formed of a pn junction diode. In this embodiment, an ILD 40 is placed on a surface 

and a first metal, Such as aluminum, is deposited and 

patterned to create the wordline 20. A layer of n silicon 44 

is then deposited over the wordline 20. A subsequent layer 

of p silicon 46 is then deposited over the n silicon 44. The 

combined Silicon is then patterned and etched to create the 

control element 26. An ILD 40 is then deposited or other 

wise applied on the layer of p Silicon 46. A via is etched in 

ILD 40 to locate the vertical bitline 18. The edge of the layer 

of p-silicon 46 that interfaces with the vertical bitline 18 is 

oxidized to create a Silicon dioxide layer for Storage element 

24 preferably less than 100 Angstroms in thickness and more 

preferably less than 50 angstroms in thickness. The vertical 

bitline 18 is then deposited. The storage element 24 has the 

layer of p silicon 46 and the bitline 18 as electrodes and the 

oxide layer as the antifusible material. 

FIG. 7 is an exploded view of one vertical bit-line and 

three horizontal wordlines for one embodiment of the inven 

tion illustrating how a vertical bit-line interfaces to conven 

tional planar Select lines. In this embodiment, a traditional 

horizontal column select line 19 is disposed parallel to the 

Surface on Some Substrate of material, Such as a conventional 

processed Semiconductor wafer. An interface layer of ILD 

40 is deposited on the horizontal column select line 19. A 

vertical bitline 18 is formed next to the ILD 40 and contacts 

the horizontal column select line 19. Then a memory cell 22, 

such as any of those shown in FIGS. 4-6 or other possible implementations, is disposed on the ILD 40. A vertical 

bitline 18 is then formed on the previous vertical bitline 18 

to create the vertical pillar. Second and third memory cells 

22 are deposited on the previous memory cell 22 and the 

15 

25 

35 

40 

45 

50 

55 

60 

65 

10 

vertical bit-lines 18 are deposited on the previous vertical 

bit-line 18 to extend the vertical pillar. 

FIGS. 8 and 9 demonstrate how the cubic array of 

memory is expanded as desired to increase the number of 

memory Storage elements. FIG. 8 is a partially exploded 

View of the components and layers of the cubic memory 

array. FIG. 9 is a top view of the array shown in FIG.8. In 

FIG. 8, a Substrate Surface includes one or more horizontal 

bit lines such as 19a and 19b, here representing column 0 

and column 2 of a memory array. On the horizontal bit lines 

19a and 19b is one or more sets of memory cells, such as 50a 

and 50b. The various horizontal row lines are insulated from 

contact with adjacent horizontal row lines by various layers 

of ILD 40. The vertical bit-lines 18a and 18b are positioned, deposited on, and make contact to the respective horizontal 

bits lines 19a and 19b. An ILD 40 dielectric layer also 

separates the adjacent vertical bit-lines 18a and 18b. The 

vertical bit-lines 18a–18d make contact to the oxide layer 

formed on middle electrodes 42a-d (see FIG. 9). The middle 

electrodes are separated from the horizontal row lines 20a-b 

(FIG. 9) by a control element, preferably a tunnel junction device or diode in memory cell 22. 

FIG. 9 also shows how an additional set of vertical pillar Select lines is placed adjacent to the Second Set of memory 

cells 50b to continue to extend the array. Adjacent to the 

additional set of vertical pillars is another ILD 40 to provide isolation for another Set of memory cells. 

FIG. 10 is an alternative embodiment of the cubic 

memory array in which the horizontal word-lines 20a and 

20b are formed in a Serpentine manner to create angled 

Storage elements 25a-d. These angles in the Serpentine row 

lines create enhanced electrical fields to lower the program ming power, Voltage, current, and time required to program 

the angled Storage elements 25a-d. 

FIG. 11 is a partially exploded view of an alternative 

embodiment of the invention. In this embodiment, a first set 

of memory cells 50a form an intersection with vertical 

pillars bit-lines 18a and 18b. A second set of memory cells 

50b is isolated from the first set of memory cells 50a and 

vertical pillars 18a and 18b by an optional interlayer dielec 

tric (ILD). The second set of memory cells 50b form an 

intersection with vertical pillar bit lines 18c and 18d. Ver 

tical pillar bit-lines 18a and 18c make electrical contact with 

horizontal bit-line 19a. Vertical pillar bit-lines 18b and 18d 

make electrical contact with horizontal bit-line 19b. Illus 

trated in this figure, there are three levels of memory cells 22 

Stacked upon one another vertically. Depending on the 

particular fabrication processes used, it may be difficult to 

keep extending the vertically Stacked layers of memory cells 

22 due to non-planarity of the previously fabricated Surface. 

Therefore, one approach to allowing for additional height is 

to create a layer of ILD (not shown) on top of the formed 

layers of memory cells. This layer of ILD is then planarized 

such as with CMP or other known planarization techniques 

to form a new planar substrate on which horizontal bit-lines 

19c. and 19d are disposed. Further processing of adding 

additional sets of memory cells on the horizontal bit-lines 

19c-d allows for extending the vertical dimension of the 

cubic memory array. 

FIG. 12 is a perspective view of an alternative embodi 

ment of the invention which increases Volumetric efficiency when using antifuSe Storage elements by eliminating the 

Spacer ILD 40 used to Separate the next adjacent horizontal 

word-lines from the present set of vertical pillar bit-lines. In 

this embodiment, a dual memory cell 23 is disposed directly 

between two vertical pillar bit-lines 18a, 18b forming stor 

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11 

age elements 24a and 24b, respectively. Although two 

Storage elements are formed, only one Storage element is 

actually used in a memory array. The other Storage element 

is left unprogrammed (open circuited for an antifuse) and 

only provides an additional capacitive load. Thus more than 

one Storage element contacts the Vertical pillar on a particu 

lar level, however, only one Storage element is actually used. 

FIG. 13 is a perspective view of a stacked implementation 

of the alternative embodiment shown in FIG. 12. In this 

embodiment, a first level 52 is disposed on a horizontal 

bit-lines 19a and 19b. Optionally depending on the process 

used, the first level 52 can be disposed on the surface of the 

substrate and the horizontal bit lines 19a and 19b (shown as 

dashed figures) can be attached to the top of the vertical 

pillars 18a and 18b, respectively. The vertical pillar bit-lines 

18a are 18b are electrically coupled to and contact the 

horizontal bit-lines 19a, 19b, respectively. A second level of 

memory cells 54 is disposed on the first level of memory 

cells 52. A third level of memory cells 56 is disposed on the 

second level of memory cells 54. The vertical pillars 18a and 

18b are preferably formed using tungsten (W) although 

other metal conductors can be used. Storage elements 24a 

and 24b are shown contacting a Single vertical pillar, thus 

Sharing the column Select signal. 

FIGS. 14-16 are exemplary embodiments of a dual 

memory cell 23 used when the Vertical pillars contact more 

than one memory cell per layer. 

For instance, FIG. 14 illustrates a first embodiment of a 

dual memory cell 23 that shows bit-line 18 as a column of 

material made of preferably tungsten (W) that will prefer 

ably be deposited after the control element 26 and Storage 

element 24 are formed. This bit-line 18 is disposed next to 

an insulating layer of dielectric material (ILD) 40. 

Various materials can be used for ILD 40 and include 

Silicon dioxide, Silicon nitride, Oxynitrides, and tetraethy 

lorthosilicate (TEOS) to just name a few. The ILD can be 

deposited using Several different conventional technologies Such as chemical vapor deposition (CVD), atmospheric 

pressure CVD, low pressure CVD, plasma enhanced CVD, physical vapor deposition (PVD), and sputtering. The ILD 

can be planarized using conventional processes Such as 

chemical mechanical polishing (CMP). ILD 40 is used 

throughout this specification to indicate dielectric filler 

material on one or more layers. The actual dielectric material 

may be composed of one or more of the aforementioned 

materials. 

Disposed on the ILD 40 is a wordline 20 preferably 

formed of a conductive thin-film shown as metal 1, for 

instance, aluminum. The wordline 20 is oxidized, either 

Self-Oxidized, thermally grown, or deposited. The oxide is 

preferably formed over the entire exposed portion of the 

wordline 20, preferably over its entire length. Preferably, the 

thickness of the oxide is less than 100 Angstroms and more 

preferably less than 50 Angstroms. Over a portion of the 

oxide, another conductive thin-film, shown as metal 2 

(preferably aluminum), is deposited and patterned to create 

two isolated control elements 26, a tunnel junction device 

with metal 1 and metal 2 as its electrodes. Metal 2 is also 

called a middle electrode 42 as it is formed electrically 

between the wordline 20 and the bitline 18. Disposed on 

metal 2 and portions of the oxide where the middle electrode 

42 is not present is another layer of ILD 40. A via is etched 

in ILD 40 to locate the vertical pillar. A portion of the middle 

electrode 42 is preferably oxidized or oxide is deposited 

thereon to form the Storage element 24. Finally, the tungsten 

is deposited to form the bitline 18 and it contacts the oxide 

15 

25 

35 

40 

45 

50 

55 

60 

65 

12 

to form the storage element 24 with the middle electrode 42 

and the bitline 18 as the electrodes. 

FIG. 15 is an alternative embodiment of dual memory cell 

23 to that shown in FIG. 14 but which includes two angled 

Storage elements 25 that Surround at least two edges of 

middle electrode 42. By Surrounding at least two edges of 

middle electrode 42 an enhanced electric field is formed at 

the interSection of the two edgeS. This enhanced electric 

field allows for lower programming power, Voltage, current, 

or time when shorting an antifuse, Such as with tunnel 

junction or dielectric breakdown devices used for angled 

storage element 25. In this embodiment, an ILD 40 is placed down on a Surface adjacent and abutting the bit-line 18, 

preferably made of tungsten (W). When the bit-line 18 is 

deposited, it forms a contact Surface over the angled Storage 

element 25. By having an angled Storage element, the 

electric field produced when a Voltage is applied between the 

middle electrode 42 and the bit-line 18 is enhanced, thereby allowing for a lower programming Voltage. Otherwise, the 

construction of the memory cell in FIG. 15 is similar to that 

described for FIG. 14. 

FIG. 16 is another embodiment of the dual memory cell 

23 in which the control elements 26 are formed of pn junction diodes. In this embodiment, an ILD 40 is placed on 

a Surface and a first metal, Such as aluminum, is deposited 

and patterned to create the wordline 20. A layer of n silicon 

44 is then deposited over the wordline 20. A subsequent 

layer of p silicon 46 is then deposited over the n silicon 44. 

The combined Silicon is then patterned and etched to create 

two control elements 26. An ILD 40 is then deposited or 

otherwise applied on the layer of p Silicon 46. A via is etched 

in ILD 40 to locate the vertical bitline 18. The edges of the 

layer of p-silicon 46 that interfaces with the vertical bitlines 

18 are oxidized to create a Silicon dioxide layer for Storage 

element 24 preferably less than 100 Angstroms in thickness 

and more preferably less than 50 angStroms in thickness. 

Vertical bitline 18 are then deposited. The storage elements 

24 have the layers of p silicon 46 and the bitlines 18 as 

electrodes and the oxide layer as the anti-fusible material. 

FIG. 17 is a partially exploded view of an embodiment of 

a 3D memory array that incorporates the basic dual memory 

cell 23 shown in FIGS. 12-13. In this embodiment, hori 

Zontal bit-lines 19a and 19b are formed within a Substrate 

surface that defines a plane. Sets of memory cells 50c-d that 

are formed in planes parallel to the plane of the Substrate are 

disposed on the substrate. Vertical bit-lines 18a–18d are 

formed in planes that are perpendicular to the plane of the 

substrate. The vertical bit lines 18a-d are adjacent to and 

make contact with the Storage elements in the respective adjacent set of memory cells 50c-d. Optionally, the cubic 

memory array can be extended by adding an ILD layer (not 

shown) on the set of memory cells and planarizing it to form 

a new Substrate Surface. On this planar Surface, another Set 

of horizontal bit-lines 19.c and 19d are disposed and are 

connected by vias into the top ILD layer to the respective 

vertical pillars 18c and 18d. Further sets of memory cells 

and Vertical bit-lines are then optionally built upon the 

additional Substrate Surface. Because there is no ILD sepa rating a vertical bit line from adjacent Sets of memory cells, 

each vertical bit line is in contact with two storage elements 

per horizontal layer. 

FIG. 18 is a top view of the embodiment of that shown in 

FIG. 17. In this embodiment, the middle electrodes 42c and 

42d contact the vertical pillar bit-lines 18c and 18d, respectively, forming memory Storage elements 24b and 

24c. In addition, because there is no ILD 40 separating the 

next set of middle electrodes 42a and 42b from the vertical 

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13 

pillar bit-lines 18c and 18d, respectively a second set of 

memory Storage elements 24a and 24d are formed. 

FIG. 19 is a top view of an alternative embodiment of that 

shown in FIG. 18 in which serpentine horizontal word-lines 

are used to enhance electric fields to lower the programming 

power, Voltage, current and time of the memory cells that are 

actually programmed. By having two edges form a point or 

corner, the electric field is increased for a given Voltage 

potential between the middle electrodes 42 (42a-42d) and 

the vertical pillar bit-lines 18 (18a–18d). 

FIGS. 20 and 21 are perspective views of alternative 

embodiments of the invention. FIG.22 is a partial schematic 

of the alternative embodiments shown in FIGS. 20 and 21. 

In the embodiment of FIG. 20, rather than routing the 

bit-lines Select Signals using horizontal bit-lines to the 

vertical pillar bit-lines 18a and 18b, the vertical pillar 

bit-lines 18a and 18b make contact with the Substrate 10 

directly to the control transistors 60a and 60b (FIG. 22), 

respectively. The control transistors are fabricated on the 

Substrate using conventional Semiconductor processing and 

can be implemented in various technologies, for example, a 

field effect transistors (FET). Alternatively, the control tran 

Sistors can be replaced with other control elements Such as 

diodes 61a and 61b. Preferably, the control transistors or 

diodes are disposed Substantially beneath or adjacent to the 

vertical pillar bit-lines 18a–b. By having the sense transis 

tors 60a, 60b (FIG. 22) or diodes 61a and 61b distributed 

beneath the vertical pillar bit-lines 18a, 18b respectively, increased Sensing Speed is achieved by reducing capacitive 

loading on the sense lines. Memory cells 23a, 23b, 23c are 

stacked upon one another in first level 52, second level 54, 

and third level 56, respectively. An ILD 40 is placed over the 

last level, third level 56 in this example, to act as a 

passivation layer or as a planar Surface on which to build 

additional layers. 

FIG. 21 is a partially exploded diagram of an alternative 

embodiment in which the cubic array is formed on a 

Substrate that is not necessarily a Semiconductor Substrate. 

In this embodiment, the diodes 61a and 61b are formed after 

the vertical pillars 18a and 18b are formed. The diodes 61a 

and 61b are preferably formed using a ramped doped Silicon 

deposition process. After the diodes 61a and 61b are formed, 

an ILD layer (not shown) is deposited between the diodes 

61a and 61b before depositing the horizontal bitlines 19a 

and 19b. The diodes 61a and 61b may be electrically 

connected to one or more vertical pillars, thus allowing for 

shared diodes. Preferably, the diodes 61a and 61b are sized 

appropriately to provide adequate current during program 

ming without causing failure. 

FIG. 22 shows a partial schematic of the antifuse con 

nection to the word-lines and bit-lines of the wordline 38 and 

column 36 decoders (see FIG. 1). Rows a0-2, b0-2, and c0-2 

are outputs from the wordline decoder 38 (not shown, but 

see FIG. 1) and couple to dual memory cells 23a–23.l. 

Vertical pillar bit-lines 18a, 18b connect to a Switching 

element such as sense transistors 60a and 60b (or alterna 

tively diodes 61a and 61b), respectively which are con 

trolled and input into the column decoder 36. Based on the 

contents of the inputs of address lines 32 coupled into the 

column decoder 36, the sensed data is output on data bus 34. 

FIG. 23 is a sectional view of an alternative embodiment 

of the invention in which the vertical pillar select lines 18a 

and 18b are formed in more than one pillar and intercon 

nected by top sub-column connect 88 and bottom Sub 

column connect 89. The top 88 and bottom 89 sub-column 

drive connects couple to the vertical pillars 18a and 18b 

15 

25 

35 

40 

45 

50 

55 

60 

65 

14 

through vias 48. Because the vertical pillars 18a and 18b 

Short the memory Storage elements 24 on the respective Sides of the pillar, only one Storage element 24 per pillar can 

be accessed at one time. Therefore, every other pillar is 

connected to a Sub-column connect line. Each memory cell 

has a storage element 24 in Series with a control element 26 

that are coupled in Series through a middle electrode 42. The 

vertical pillar 18a or vertical pillar 18b are interconnected to 

a horizontal single bit line 19 that is connected to the sense 

amp circuitry in the column decoder 36 of FIG. 1. This 

interconnection is achieved by enabling one of transistors 

60a or 60b to select the desired vertical pillar 18a and 18b. 

FIG. 24 is an exemplary layout of a memory carrier 70 

that incorporates at least one embodiment of the invention. 

The memory carrier represents any of Several conventional 

Standard or proprietary memory card formats, Such as a 

PCMCIA, PC card, Smart memory, memory stick, digital 

film, ATA, and compact flash to just name a few. The 

memory carrier includes a mechanical interface 72 that 

provides for both mechanical and electrical contact with a 

particular connector for the type of memory carrier Standard 

implemented. An optional electrical interface 74 makes 

electrical coupling with the electrical contacts on the 

mechanical connector 72 and provides the proper Security, address decoding, Voltage translation, write protection, or 

other typical interface functions with a set of memory ICs 80 

that incorporate at least one memory array of the invention. 

A carrier 76, for example a printed circuit board or ceramic 

Substrate, typically is used to physically Support the memory 

ICs 80, electrical interface 74, and mechanical interface 72. 

It will be appreciated to those of known skill in the art that 

Some electrical devices might incorporate the functionality 

of electrical interface 74 thereby obviating its need in 

memory carrier 70. The set of memory ICs 80 may include 

one or more devices. Further, there may be more than one 

type of memory array, such as an OTP memory IC and 

read-writeable memory ICs for memory ICs 80. 

FIG.25 is a block diagram of an electronic device, in this 

example a computer System 90, which incorporates at least 

one embodiment of the invention. In particular for a com 

puter System, Several different electrical devices as shown 

may be incorporated into the package. Here a microproces 

sor 92 is coupled to a memory circuit 94 used to hold 

computer executable instructions and/or user data. Exem 

plary memory circuits 94 include BIOS memory, DRAM 

memory, ROM, and various levels of internal or external 

cache memory just to name a few. The microprocessor 92 is 

also connected to a storage device 96 Such as a hard disk 

drive, floppy drive, CD/DVD drive, tape drive or other mass 

Storage devices Such as those that incorporate Semiconductor 

memory ICs using the invention. The microprocessor 92 

may include the 3D-memory architecture in its internal 

cache memory for instance. The memory 94 may also 

include the 3D-memory architecture in its memory ICs, such 

as in BIOS or other system memory areas such as DRAM 

and ROM circuits. The microprocessor 92 is further con 

nected to a display device 98 that may also incorporate 

memory ICs that utilize the invention. Therefore, in an 

electrical device, there may one or more implementations of 

the invention, thus demonstrating the widespread applica 

bility of the invention to improving existing electrical 

devices. 

For instance, FIG. 26 is an exemplary embodiment of an 

embedded cubic memory array 100 that integrates the 

memory 94, such as level 1 and/or level 2 cache, with the 

microprocessor 92. The embedded cubic memory array 100 

is fabricated on top of the die of microprocessor 92 thereby 

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US 6,781,858 B2 

15 

allowing for a Smaller die area size. Microprocessor 92 

forms a horizontal substrate surface. Preferably, memory 94 

is built of one or more vertical layers of memory cells 22 or 

23 (not shown) to form the embedded cubic memory array 

100. The memory cells 22 or 23 are interconnected by a first 

and Second Set of Select lines. At least one of the Select lines 

is formed within the embedded cubic memory array 100 as 

Vertical pillars. The Sets of Select lines are electrically 

connected to Selection circuitry formed on the die of micro 

processor 92. The microprocessor 92 is electrically attached 

to a package 95 such as with bonding wires 97 or TAB 

circuit technology. After the microprocessor is attached to 

package 95 it is encapsulated (not shown) to provide pro 

tection from contaminants and handling. Although the 

embedded cubic memory array 100 is shown as disposed on 

a microprocessor integrated circuit, those of Skill in the art 

will appreciate that any integrated circuit that utilizes 

memory circuits can be Substituted for the microprocessor 

92. One example would be a graphics display controller. 

FIG. 27 is an exemplary flow chart of the basic steps used 

to implement various embodiments of the invention. In Step 

62, an array of a set of word-lines is formed in a plane that 

is Substantially parallel to a Substrate or other planar Surface. 

In Step 64, an array of a Set of bit-lines is formed Substan 

tially normal to the plane or word-lines or the Substrate 

surface. By forming the bit-lines normal to the plane of the 

Substrate and hence the word-lines, a set of Vertical pillar bit-lines is created. In Step 66, an array of memory cells is 

formed preferably between each respective wordline and 

each bitline, although some intersections of word-lines and 

bit-lines may not contain memory cells if those address 

locations are desired to be unprogrammable. 

FIG. 28 is an exemplary flow chart for the basic steps to 

create a memory cell that incorporates the invention. In Step 

82 an insulator, such as ILD 40, is applied on a substrate 

Surface, preferably Substantially planar. In Step 83, a first 

conductor is applied in a plane parallel to the Substrate to 

form a wordline. In Step 84, a control element is created on 

the first conductor, Such as a tunnel junction device or a 

diode. In Step 85, a Second conductor that is orthogonal 

(normal or perpendicular) to the plane of the first conductor 

is applied to the processed Substrate Surface. In Step 86, a 

memory Storage element is created between the Second 

conductor and the control element. The memory Storage 

element is preferably a tunnel junction antifuSe device but 

other memory Storage elements can be used and Still fall 

within the Scope and Spirit of the invention. 

While the present invention has been particularly shown 

and described with reference to the foregoing preferred and 

alternative embodiments, those skilled in the art will under 

Stand that many variations may be made therein without 

departing from the Spirit and Scope of the invention as 

defined in the following claims. This description of the 

invention should be understood to include all novel and 

non-obvious combinations of elements described herein, and 

claims may be presented in this or a later application to any 

novel and non-obvious combination of these elements. The 

foregoing embodiments are illustrative, and no Single fea 

ture or element is essential to all possible combinations that 

may be claimed in this or a later application. Where the 

claims recite “a” or “a first element of the equivalent 

thereof, Such claims should be understood to include incor 

poration of one or more Such elements, neither requiring nor 

excluding two or more Such elements. 

16 

What is claimed is: 

1. A cubic memory array, comprising, 

a Substrate; 

a plurality of levels of memory cells formed on the 

5 Substrate one level upon the other, the memory cells of 

each level are Substantially aligned with memory cells 

in the adjacent level; 

a plurality of sets of first select lines formed in each of the 

plurality of levels of memory cells substantially parallel 

1O to the Substrate; 

a plurality of Sets of Second Select lines formed in planes orthogonal to the Substrate; and 

at least one Switching element disposed on top of at least 

one of the plurality of Second Select lines 

15 wherein each of the memory cells is adjacent to a respec 

tive first and Second Select line. 

2. The cubic memory array of claim 1, wherein at least 

one of the memory cells Stores multiple States allowing for 

more than one bit of information in the memory cell. 

20 3. The cubic memory array of claim 1, wherein at least 

one of the memory cells includes an antifuse device. 

4. The cubic memory array of claim 1, wherein at least 

one of the memory cells includes a tunnel junction device. 

5. The cubic memory array of claim 1, wherein at least 

25 one of the memory cells includes, 

a storage device having a first cross-sectional area; 

a control element in Series with the Storage device and 

having a Second cross-sectional area greater than the 

first cross-sectional area. 

6. The cubic memory array of claim 1, wherein the 

plurality of Sets of Second Select lines are formed of tung 

Sten. 

7. The cubic memory array of claim 1, wherein at least 

one of the memory cells includes an angled Storage element 

patterned to create an enhanced electric field. 

8. The cubic memory array of claim 1, wherein at least 

one of the memory cells has dual Storage elements and 

wherein only one Storage element is used. 

9. The cubic memory array of claim 1, wherein the 

plurality of Sets of first Select lines are formed in at least a partial Serpentine pattern. 

10. The cubic memory array of claim 1, where at least one 

of the plurality of sets of second select lines are formed from 

an array of Sub-pillars connected by a Subset of Second Select 

lines formed parallel to the Substrate Surface. 

11. A cubic memory array, comprising: 

a Substrate; 

a first plane of an array of memory cells disposed on the 

Substrate; 

a first Set of Select lines forming rows of memory cells on 

the first plane; 

a Second plane of an array of memory cells disposed on 

the first plane and aligned with the array of memory 

55 cells of the first plane; 

a Second Set of Select lines orthogonal to the planer 

Surface interconnecting the first and Second planes of 

memory cells wherein each memory cell is adjacent to 

one of the first Set of Select lines and adjacent to one of 

60 the orthogonal Second Set of Select lines, and 

at least one Switching element disposed on top of one of 

the Second Set of Select lines. 

12. The cubic memory array of claim 11, wherein at least 

one of the memory cells Stores multiple States allowing for 

65 more than one bit of information in the memory cell. 

13. The cubic memory array of claim 11, wherein at least 

one of the memory cells includes an antifuse device. 

35 

40 

45 

50 

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US 6,781,858 B2 

17 

14. The cubic memory array of claim 11, wherein at least 

one of the memory cells includes a tunnel junction device. 

15. The cubic memory array of claim 11, wherein at least 

one of the memory cells includes, 

a storage device having a first cross-sectional area; 

a control element in Series with the Storage device and 

having a Second cross-sectional area greater than the 

first cross-sectional area. 

16. The cubic memory array of claim 11, wherein the 

Second Set of Select lines are formed of tungsten. 

17. The cubic memory array of claim 11, wherein at least 

one of the memory cells includes an angled Storage element 

patterned to create an enhanced electric field. 

18. The cubic memory array of claim 11, wherein at least 

one of the memory cells has dual Storage elements and 

wherein only one Storage element is used. 

19. The cubic memory array of claim 11, wherein the first 

Set of Select lines are formed in at least a partial Serpentine 

pattern. 

20. The cubic memory array of claim 11, wherein at least 

one of the Second Set of Select lines are formed from an array 

of Sub-pillars connected by a Subset of Second Select lines 

formed parallel to the Substrate Surface. 

21. A cubic memory array, comprising: 

a plurality of horizontal Select lines, 

a plurality of Vertical Select lines, 

a plurality of memory cells, each memory cell adjacent to 

a horizontal Select line and adjacent to a vertical Select 

line; and 

at least one Switching element disposed on top of at least 

one of the plurality of vertical Select lines, 

wherein the plurality of memory cells are arranged to 

form planes of horizontal Select lines and planes of 

Vertical Select lines orthogonal to each other. 

22. The cubic memory array of claim 21, wherein at least 

one of the memory cells Stores multiple States allowing for 

more than one bit of information in the memory cell. 

23. The cubic memory array of claim 21, wherein at least 

one of the memory cells includes an antifuse device. 

24. The cubic memory array of claim 21, wherein at least 

one of the memory cells includes a tunnel junction device. 

25. The cubic memory array of claim 21, wherein at least 

one of the memory cells includes, 

a storage device having a first cross-sectional area; 

a control element in Series with the Storage device and 

having a Second cross-sectional area greater than the 

first cross-sectional area. 

26. The cubic memory array of claim 21, wherein the 

Vertical Select lines are formed of tungsten. 

27. The cubic memory array of claim 21, wherein at least 

one of the memory cells includes an angled Storage element 

patterned to create an enhanced electric field. 

28. The cubic memory array of claim 21, wherein at least 

one of the memory cells has dual Storage elements and 

wherein only one Storage element is used. 

29. The cubic memory array of claim 21, wherein the 

horizontal of Select lines are formed in at least a partial Serpentine pattern. 

30. The cubic memory array of claim 21, where at least 

one of the Vertical Select lines are formed from an array of 

Sub-pillars connected by a Subset of Second horizontal Select 

lines. 

31. A cubic memory array, comprising: 

a Substrate having a first Surface 

a horizontal line disposed parallel to first Surface of the 

Substrate; 

1O 

15 

25 

35 

40 

45 

50 

55 

60 

65 

18 

an isolation layer formed on a portion of the horizontal bit 

line; 

a vertical bit line formed next to the isolation layer and 

contacting the horizontal bit line; 

a Switching element disposed on top of the vertical bit 

line; 

a first memory cell having, 

a storage element adjacent to the vertical bit line, 

a control element in Series with the Storage element, 

and 

a first horizontal word line disposed on the isolation layer and contacting the control element; and 

at least one additional memory cell having a Second 

horizontal word line disposed on the first memory cell 

and contacting the Vertical bit line. 

32. The cubic memory array of claim 31, wherein at least 

one of the Storage elements Stores multiple States allowing 

for more than one bit of information in the Storage element. 

33. The cubic memory array of claim 31, wherein at least 

one of the Storage elements is an antifuse device. 

34. The cubic memory array of claim 31, wherein at least 

one of the Storage cells is a tunnel junction device. 

35. The cubic memory array of claim 31, wherein 

the Storage device has a first cross-sectional area; 

the control element has a Second cross-sectional area 

greater than the first croSS-Sectional area. 

36. The cubic memory array of claim 31, wherein the 

Vertical bit line comprises tungsten. 

37. The cubic memory array of claim 31, wherein the 

Storage element comprises an angled Storage element pat 

terned to create an enhanced electric field. 

38. The cubic memory array of claim 31, wherein the 

memory cells has an additional Storage element and wherein 

the additional Storage element is not used to Store informa 

tion. 

39. The cubic memory array of claim 31, wherein the 

horizontal bit line is formed in at least a partial Serpentine 

pattern. 

40. The cubic memory array of claim 31, where the 

vertical bit line is formed from an array of sub-pillars 

connected by a Subset of Second horizontal bit lines. 

41. A cubic memory array, comprising: 

a plurality of horizontal word lines formed in a plurality of layers, 

a plurality Stacked memory cells, each memory cell 

disposed on one of the plurality of horizontal word 

lines, 

a plurality of horizontal too Sub-column connects, 

a plurality of horizontal bottom Sub-column connects, 

a plurality of Vertical bit lines contacting the plurality of 

Stacked memory cells, wherein the vertical bit lines are 

formed in more than one pillar and are interconnected 

by one of the plurality of too Sub-column connects and 

one of the plurality of bottom Sub-column connects, 

wherein the every other pillar is connected to one of a 

too Sub-column connect or a bottom Sub-column con 

nect. 

42. The cubic memory array of claim 41, wherein at least 

one of the Stacked memory cells includes a storage element 

that Stores multiple States allowing for more than one bit of 

information in the Storage element. 

43. The cubic memory array of claim 41, wherein at least 

one of the Stacked memory cells comprises an antifuse 

device. 

44. The cubic memory array of claim 41, wherein at least 

one of the Stacked memory cells comprises a tunnel junction 

device. 

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US 6,781,858 B2 

19 

45. The cubic memory array of claim 41, wherein at least 

one of the Stacked memory cells comprises, 

a storage device having a first cross-sectional area; 

a control element having a Second cross-sectional area 

greater than the first croSS-Sectional area. 

46. The cubic memory array of claim 41, wherein at least 

one of the plurality of Vertical bit lines comprises tungsten. 

47. The cubic memory array of claim 41, wherein at least 

one of the Stacked memory Storage cells comprises an 

angled Storage element patterned to create an enhanced 

electric field. 

48. The cubic memory array of claim 41, wherein the 

Stacked memory cells has an additional Storage element and 

wherein the additional Storage element is not used. 

49. The cubic memory array of claim 41, wherein one of 

the plurality of horizontal word lines is formed in at least a 

partial Serpentine pattern. 

50. A cubic memory array, comprising 

control circuitry; 

a first horizontal Select line; 

a first Set of memory cells adjacent to the first horizontal 

Select line; 

a first Set of Vertical Select lines interSecting with the first 

Set of memory cells, a Second horizontal Select line isolated from the first Set of 

memory cells, 

a Second Set of memory cells adjacent to the Second 

horizontal Select line; 

a Second Set of Vertical Select lines interSecting with the 

Second set of memory cells; 

Switching elements disposed on top of the vertical Select 

lines, 

a set of horizontal bitlines connecting the Switching 

elements to the control circuitry; a third horizontal Select line isolated from and Stacked 

upon the first horizontal Select line; 

a third set of memory cells adjacent to the third horizontal 

Select line; a fourth horizontal Select line isolated from and Stacked 

upon the Second horizontal Select line; and 

a forth set of memory cells adjacent to the fourth hori 

Zontal Select line; 

wherein the first set of vertical select lines intersect with 

the third Set of memory cells, and the Second Set of 

vertical select lines intersect with the fourth set of 

memory cells. 

51. The cubic memory array of claim 50, wherein at least 

one of the memory cells includes a Storage element that 

Stores multiple States allowing for more than one bit of 

information in the Storage element. 

52. The cubic memory array of claim 50, wherein at least 

one of the memory cells comprises an antifuse device. 

53. The cubic memory array of claim 50, wherein at least 

one of the memory cells comprises a tunnel junction device. 

54. The cubic memory array of claim 50, wherein at least 

one of the memory cells comprises, 

a storage device having a first cross-sectional area; 

a control element having a Second cross-sectional area 

greater than the first croSS-Sectional area. 

15 

25 

35 

40 

45 

50 

55 

60 

20 

55. The cubic memory array of claim 50, wherein at least 

one of the vertical Select lines comprises tungsten. 

56. The cubic memory array of claim 50, wherein at least 

one of the memory Storage cells comprises an angled Storage 

element patterned to create an enhanced electric field. 

57. The cubic memory array of claim 50, wherein the 

memory cells has an additional Storage element and wherein 

the additional Storage element is not used. 

58. A cubic memory array, comprising: 

a Substrate; 

a set of horizontal word lines formed parallel to the 

Substrate in a plurality of layers, 

a set of top Sub-column connects, 

a set of bottom Sub-column connects, the top and bottom 

Sub-column connects parallel to the Substrate and 

orthogonal to the Set of horizontal word lines, a set of vertical bitlines wherein the vertical bit lines are 

formed in more than one pillar and are interconnected 

by one of the Set of top Sub-column connects and one 

of the Set of bottom Sub-column connects, 

wherein the every other pillar is connected to one of a top 

Sub-column connect or a bottom Sub-column connect; 

and 

a set of memory cells, each memory cell having, 

a storage element adjacent to a pillar, 

a control element in Series with the Storage element 

connected to a horizontal word line. 

59. The cubic array of claim 58, further comprising: 

control circuitry having Switching elements formed in the 

Substrate; 

a set of horizontal bit lines, each interconnected to every 

other pillar using the Switching elements to Select a 

desired pillar. 

60. The cubic memory array of claim 58, wherein at least 

one of the Storage elements Stores multiple States allowing 

for more than one bit of information in the Storage element. 

61. The cubic memory array of claim 58, wherein at least 

one of the Storage elements is an antifuse device. 

62. The cubic memory array of claim 58, wherein at least 

one of the Storage cells is a tunnel junction device. 

63. The cubic memory array of claim 58, wherein 

the Storage device has a first cross-sectional area; 

the control element has a Second cross-sectional area 

greater than the first croSS-Sectional area. 

64. The cubic memory array of claim 58, wherein the 

Vertical bit line comprises tungsten. 

65. The cubic memory array of claim 58, wherein the 

Storage element comprises an angled Storage element pat 

terned to create an enhanced electric field. 

66. The cubic memory array of claim 58, wherein the 

memory cells has an additional Storage element and wherein 

the additional Storage element is not used to Store informa 

tion. 

67. The cubic memory array of claim 58, wherein the 

horizontal word line is formed in at least a partial Serpentine 

pattern. 

Case 2:23-cv-00445-JRG Document 1-6 Filed 09/27/23 Page 29 of 30 PageID #: 115
UNITED STATES PATENT AND TRADEMARK OFFICE 

CERTIFICATE OF CORRECTION 

PATENT NO. : 6,781,858 B2 Page 1 of 1 

DATED : August 24, 2004 

INVENTOR(S) : Fricke et al. 

It is certified that error appears in the above-identified patent and that said Letters Patent is 

hereby corrected as shown below: 

Column 17 

Line 65, delete "Surface' and insert therefor -- Surface; --. 

Column 18 

Lines 48, 53 and 56, delete “too” and insert therefor -- top --. 

Signed and Sealed this 

Fifth Day of April, 2005 

WDJ 

JON W. DUDAS 

Director of the United States Patent and Trademark Office 

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