# Patent

## Title
Semiconductor device having silicon-germanium layer on fin and method for manufacturing the same

## Abstract

A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

## Background
BACKGROUND
Technical Field
The disclosure relates in general to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having silicon-germanium (SiGe) layer formed on the fin and a method for manufacturing the same.
Description of the Related Art
Electrical properties, reduction of feature size, improvements of the operation efficiency, and the density and the cost per integrated circuit unit are the important goals in the semiconductor technology. The properties of the semiconductor device have to be maintained even improved to meet the requirements of the commercial products in applications. For example, the carrier mobility in the channel of the FinFET should reach a certain level. How to increase the carrier mobility in the channel of the finFET is one of the important issues of the device for the manufacturers.
SUMMARY
The disclosure is directed to a semiconductor device having silicon-germanium (SiGe) layer formed on the fin and a method for manufacturing the same. The proposed structure and method of the present embodiments effectively reduces strain difference between the bottom and the top of the fin, thereby effectively increases the carrier mobility in the fin channel and improving the electrical characteristics of the semiconductor device.
According to one aspect of the present disclosure, a semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.
According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. A substrate with an isolation layer formed thereon is provided, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer. A silicon-germanium (SiGe) layer is formed (such as epitaxially grown) on the top surface and the pair of lateral sidewalls of the fin, wherein the SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on the lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30. Then, a gate stack is formed on the isolation layer and across the top surface and the pair of lateral sidewalls of the fin, wherein the fin extends along a first direction, and the gate stack extends along a second direction different from the first direction.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A-FIG. 1E illustrate a method for manufacturing a semiconductor device according to the first embodiment of the disclosure.
FIG. 2A-FIG. 2F illustrate a method for manufacturing a semiconductor device according to the second embodiment of the disclosure.
FIG. 3A presents a strain distribution of the top and the bottom of the fin according to a conventional semiconductor device.
FIG. 3B presents a strain distribution of the top and the bottom of the fin according to an embodied semiconductor device.



In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
DETAILED DESCRIPTION
In the embodiment of the present disclosure, a semiconductor device and a method for manufacturing the same are provided, by forming (such as epitaxially growing) a silicon-germanium (SiGe) layer on the top surface and the pair of lateral sidewalls of the fin above the isolation layer. In one embodiment, the silicon-germanium (SiGe) layer could be directly formed on the top surface and the pair of lateral sidewalls of the fin above the isolation layer by epitaxial growth using a precursor with particular combination. The present invention can be applied to manufacture different types of the semiconductor devices having fins for reducing the strain difference between the bottom and the top of the fin, thereby increasing the carrier mobility in the channel and improving the electrical characteristics of the semiconductor devices.
Embodiments are provided hereinafter with reference to the accompanying drawings for describing the related procedures and configurations. For example, a semiconductor device having the first gate structures with narrower gate lengths in the first area and the second gate structures with wider gate lengths in the second area is exemplified for illustration. However, the present disclosure is not limited thereto. It is noted that not all embodiments of the invention are shown. The identical and/or similar elements of the embodiments are designated with the same and/or similar reference numerals. Also, it is noted that there may be other embodiments of the present disclosure which are not specifically illustrated. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. It is also important to point out that the illustrations may not necessarily be drawn to scale. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense.
Moreover, use of ordinal terms such as “first”, “second”, “third” etc., in the specification and claims to describe an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.
First Embodiment
FIG. 1A-FIG. 1E illustrate a method for manufacturing a semiconductor device according to the first embodiment of the disclosure. First, a substrate 10 having a fin 12 and an isolation layer 13 formed on the substrate 10 is provided. The fin 12 protrudes up through the isolation layer 13 to form a top surface 120 and a pair of lateral sidewalls 122 of the fin 12 above the isolation layer 13, as shown in FIG. 1A.
Then, a silicon-germanium (SiGe) layer 14 is formed on the top surface 120 and the pair of lateral sidewalls 122 of the fin 12, as shown in FIG. 1B. In the embodiment, the portions 141 and 142 of the SiGe layer 14 are epitaxially grown on the top surface 120 and the pair of lateral sidewalls 122 of the fin 12, respectively.
According to the embodiment, the SiGe layer 14 is grown by using a precursor comprising dichlorosilane (DCS, SiCl2H2) or silane (SiH4) in a flow rate larger than 100 standard cubic centimeters per minute (sccm). In one embodiment, the precursor comprises dichlorosilane or silane in the flow rate larger than 100 sccm but no more than 300 sccm. Furthermore, the precursor may further comprise germane (GeH4) in a flow rate of 200 sccm to 900 sccm, wherein a flow ratio of germane (GeH4) to dichlorosilane (DCS) is in a range of 3 to 8. Also, the precursor may further comprise hydrochloric acid (HCl), wherein a flow ratio of HCl is in a flow rate of 150 sccm to 300 sccm. In one embodiment, a flow ratio of germane (GeH4) to hydrochloric acid (HCl) is in a range of 3 to 8. In one embodiment, the SiGe layer 14 contains 20% to 75% of germanium (Ge).
Moreover, the portion 141 of the SiGe layer 14 formed on the top surface 120 of the fin 12 is thinner than the portion 142 of the SiGe layer 14 formed on the lateral sidewalls 122 of the fin 12. In one embodiment, the portion 141 of the SiGe layer 14 formed on the top surface 120 of the fin 12 has a first thickness t1, while the portion 142 of the SiGe layer 14 formed on the lateral sidewalls 122 of the fin 12 has a second thickness t2. The first thickness t1 of the SiGe layer 14 can be the maximum thickness of the SiGe layer 14 formed on the top surface 120 of the fin 12 (i.e. the maximum thickness of the portion 141). Similarly, the second thickness t2 of the SiGe layer 14 can be a maximum thickness of the SiGe layer 14 formed on the lateral sidewall 122 of the fin 12 (i.e. the maximum thickness of the portion 142). In one embodiment, a ratio of the first thickness t1 to the second thickness t2 (i.e. t1: t2) is in a range from 1:10 to 1:30. Also, in one embodiment, the second thickness t2 of the portion 142 of the SiGe layer 14 formed on one of the pair of lateral sidewalls 122 of the fin 12 is in a range of 20 Å to 50 Å.
Afterwards, a gate stack 16 is formed on the isolation layer 13 and across the top surface 120 and the pair of lateral sidewalls 122 of the fin 12 in the first embodiment, as shown in FIG. 10. In one embodiment, the fin 12 extends along a first direction D1 (such as X-direction), and the gate stack 16 extends along a second direction D2 (such as Y-direction), wherein the second direction D2 is different from the first direction D1; for example, D2 is vertical to D1. Also, in one embodiment, the gate stack 16 includes a gate dielectric layer 161 formed on the isolation layer 13 and a gate electrode layer 162 formed on the gate dielectric layer 161, wherein the gate dielectric layer 161 contacts the SiGe layer 14 formed on the top surface 120 of the fin 12 (i.e. the portion 141 of the SiGe layer 14) and formed on the pair of lateral sidewalls 122 of the fin 12 (i.e. the portion 142 of the SiGe layer 14).
After formation of the gate stack 16, the portions of the fin 12 and the SiGe layer 14 uncovered by the gate stack 16 are removed, so as to form a source region 12RS and a drain region 12RD positioned correspondingly to opposite sides of the fin 12, wherein the opposite sides of the fin 12 are exposed by the gate stack 16, as shown in FIG. 1D. In one embodiment, the source region 12RS comprises a first recessed surface 125-1 below the isolation layer 13, and the drain region 12RD comprises a second recessed surface 125-2 below the isolation layer 13.
After formation of the source region 12RS and the drain region 12RD, a SiGe source 18S is formed at the source region 12RS and a SiGe drain 18D is formed at the drain region 12RD, wherein a channel region RCH is formed between the source region 12RS and the drain region 12RD, as shown in FIG. 1E. For example, the SiGe source 18S is formed on the first recessed surface 125-1 (FIG. 1D) of the source region 12RS, and the SiGe drain 18D is formed on the second recessed surface 125-2 of the drain region 12RD. According to the embodied semiconductor device, the channel region RCH comprises the fin beneath the gate stack 16 and the SiGe layer 14 formed on the top surface 120 and on the pair of lateral sidewalls 122 of the fin 12 above the isolation layer 13.
Moreover, in the first embodiment, at least one (ex: both) of the SiGe source and the SiGe drain 18D contacts and completely shields the surfaces of the SiGe layer 14 formed on the top surface 120 and formed on the pair of lateral sidewalls 122 of the fin 12 exposed by the gate stack 16.
According to the first embodiment, a semiconductor device as shown in FIG. 1E, includes a SiGe layer 14 formed (ex: epitaxially grown) on the top surface 120 and the pair of lateral sidewalls 122 of the fin 12 above the isolation layer 13, a gate stack across the portion 142 of the SiGe layer 14 formed on the lateral sidewalls 122 of the fin 12 and the portion 141 of the SiGe layer 14 formed on the top surface 120 of the fin 12.
Second Embodiment
FIG. 2A-FIG. 2F illustrate a method for manufacturing a semiconductor device according to the second embodiment of the disclosure. In the second embodiment, the method further comprises removing the SiGe layer 14 formed on the top surface 120 of the fin 12 before forming the gate stack 16. The identical elements of the second and first embodiments are designated with the same reference numerals for achieving the purpose of clear illustration. Also, the structural and steps details of the related elements have been described in the first embodiment, and would not be redundantly repeated. For example, details of FIG. 2A-FIG. 2B are identical to FIG. 1A-FIG. 1B.
In the second embodiment, after forming the SiGe layer 14 (including the portions 141 and 142) on the top surface 120 and the pair of lateral sidewalls 122 of the fin 12 as shown in FIG. 2B, the method further comprises removing the portion 141 of the SiGe layer 14 formed on the top surface 120 of the fin 12 (before forming the gate stack 16). Accordingly, the portion 142 of the SiGe layer 14 formed on the pair of lateral sidewalls 122 of the fin 12 is remained after removal of the portion 141 of the SiGe layer 14 (i.e. formed on the top surface 120 of the fin 12). In one embodiment, the portion 141 of the SiGe layer 14 formed on the top surface 120 of the fin 12 can be removed by hydrochloric acid (HCl).
After removal of the portion 141 of the SiGe layer 14, the subsequent procedures of the second embodiment (ex: FIG. 2D-FIG. 2F) are similar to the subsequent procedures of the first embodiment (ex: FIG. 1C-FIG. 1E).
As shown in FIG. 2D, a gate stack 16 is formed on the isolation layer 13 and across the top surface 120 and the pair of lateral sidewalls 122 of the fin 12 in the second embodiment, wherein the gate stack 16 extends along the second direction D2 (such as Y-direction) and the fin 12 extends along the first direction D1 (such as X-direction). In the second embodiment, the gate stack 16 includes a gate dielectric layer 161 formed on the isolation layer 13 and a gate electrode layer 162 formed on the gate dielectric layer 161, wherein the gate dielectric layer 161 contacts the SiGe layer 14 formed on the pair of lateral sidewalls 122 of the fin 12 and contacts the top surface 120 of the fin 12 (since the portion 141 of the SiGe layer 14 has been removed as shown in FIG. 2C).
After formation of the gate stack 16, the source region 12RS and the drain region 12RD positioned correspondingly to opposite sides of the fin 12 are formed, as shown in FIG. 2E. Then, the SiGe source 18S is formed on the first recessed surface 125-1 (FIG. 2E) of the source region 12RS, and the SiGe drain 18D is formed on the second recessed surface 125-2 of the drain region 12RD, as shown in FIG. 2F.
According to the aforementioned description, the SiGe layer 14 formed on the lateral sidewalls 122 of the fin 12 would increase the strain of the bottom of the fin above the isolation layer 13, so that the strain difference between the bottom and the top of the fin 12 can be reduced. Several measurements have been conducted to obtain strain conditions of the fins. The measurement results indicate that a fin without a SiGe layer formed on the lateral sidewalls possesses a top strain much higher than a bottom strain. Large strain difference between the top and bottom of a fin would have considerable effect on the carrier mobility in the channel of the finFET. The measurement results of embodied devices, each comprising a SiGe layer at least formed on the lateral sidewalls of the fin, indicate that the strains of the bottoms of the fins have significantly increased (i.e. the strain difference between the bottom and the top of the fin is significantly reduced), thereby effectively increasing the carrier mobility in the channel.
A set of measurement results is presented for illustration. Please refer to FIG. 3A and FIG. 3B, which respectively present the strain distributions of the tops and the bottoms of the fins according to a conventional semiconductor device and an embodied semiconductor device. A fin without SiGe layer formed on the lateral sidewalls (i.e. conventional semiconductor device) possesses a top strain of about 80 and a bottom strain of about 0 as shown in FIG. 3A, while a fin with a SiGe layer 14 formed on the lateral sidewalls 122 (i.e. an embodied semiconductor device) possesses a top strain of about 80 and a bottom strain of about 50 as shown in FIG. 3B. Accordingly, the strain difference between the bottom and the top of the fin 12 of the embodiment do greatly decrease. Reduced strain difference between the bottom and the top of the fin effectively increases the carrier mobility in the fin channel RCH. Additionally, the SiGe layer 14 formed on the lateral sidewalls 122 of the fin 12 is a thin layer (compared to other components such as the fin 12 and the gate stack 16); in one embodiment, the SiGe layer 14 formed on the lateral sidewalls 122 has a thickness of about 20 Å to 50 Å, and there is no dislocation occurring in the device structure of the embodiment. Thus, the SiGe layer 14 of the embodiment has no bad influence on the properties of the semiconductor device.
Other embodiments with different configurations of known elements in the semiconductor devices can be applicable, and the arrangement depends on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. It is known by people skilled in the art that the shapes or positional relationship of the constituting elements and the procedure details could be adjusted according to the requirements and/or manufacturing steps of the practical applications without departing from the spirit of the disclosure.
While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

## Claims

1. A semiconductor device, comprising:
a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer;
a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the pair of lateral sidewalls of the fin, wherein the SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30; and
a gate stack formed on the isolation layer and across the top surface and the pair of lateral sidewalls of the fin, wherein the fin extends along a first direction, and the gate stack extends along a second direction different from the first direction.

2. The semiconductor device according to claim 1, wherein the first thickness of the SiGe layer is a maximum thickness of the SiGe layer formed on the top surface of the fin, and the second thickness of the SiGe layer is a maximum thickness of the SiGe layer formed on said lateral sidewall of the fin.

3. The semiconductor device according to claim 1, wherein the SiGe layer contains 20% to 75% of germanium (Ge).

4. The semiconductor device according to claim 1, wherein the second thickness of the SiGe layer formed on one of the pair of lateral sidewalls is in a range of 20 Å to 50 Å.

5. The semiconductor device according to claim 1, further comprising:
a source region and a drain region positioned correspondingly to opposite sides of the fin, wherein the opposite sides of the fin are exposed by the gate stack;
a SiGe source formed at the source region and a SiGe drain formed at the drain region,
wherein a channel region is formed between the source region and the drain region.

6. The semiconductor device according to claim 5, wherein the channel region comprises:
the fin beneath the gate stack and above the isolation layer; and
the SiGe layer formed on the top surface and on the pair of lateral sidewalls of the fin.

7. The semiconductor device according to claim 5, wherein one of the SiGe source and the SiGe drain contacts and completely shields surfaces of the SiGe layer formed on the top surface and formed on the pair of lateral sidewalls of the fin exposed by the gate stack.

8. The semiconductor device according to claim 5, wherein the source region comprises a first recessed surface below the isolation layer and the SiGe source is formed on the first recessed surface, and the drain region comprises a second recessed surface below the isolation layer and the SiGe drain is formed on the second recessed surface.

9. The semiconductor device according to claim 1, wherein the gate stack comprises:
a gate dielectric layer, formed on the isolation layer and contacting the SiGe layer formed on the top surface and formed on the pair of lateral sidewalls of the fin; and
a gate electrode layer formed on the gate dielectric layer.