EXHIBIT 16

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 1 of 13 PageID #: 246
Claim 1 

1. A processor 

integrated circuit 

capable of executing 

more than one 

instrnction stream 

compnsmg: 

U.S. Patent No. 678717264 

Identification: Moto Edge1 

1 Additional infiinging products include devices featming ARM DynamIQ, sold or offered for sale by AT&T, including at least the Motorola Edge 

(2022), Edge 20, Edge 20 Pro, Edge 20 Lite, Edge (2021), Edge 20 Fusion, Google Pixel 5, and Google Pixel 4 devices. 

Page I 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 2 of 13 PageID #: 247
Claim 1 Identification: Moto Edge1 

https://www.att.com/buy/phones/motorola-edge-2022.html 

https://www.motorola.com/us/smartphones-motorola-edge-gen-3/p?skuld=979 

See also, https://www.gsmarena.com/motorola_edge_{2022)-11777.php 

(ffl CPU 

Architecture 

Cores 8 

f requency 2500 MHz 

Instruction set ARMv8.2-A 

Process 6 nanometers 

Manufacturing TSMC 

https:/ /nano review. net/en/soc/mediatek-di mensity-1050 

Page2 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 3 of 13 PageID #: 248
Claim 1 

a first processor, 

coupled to fetch 

instrnctions and access 

data through a first 

cache controller; 

Identification: Moto Edge1 

- .. C ")1 .. x • '- o .. " , 1, ,.,, .. ,")•_, ~ '"'" .. '- .. .. , • . : . 11 .. , 1, t ~ r .. R. 1 •. ~ .\. ., '- •._., • ,vith 

support for the ,·8.2 extension. the RAS extens1on. the Load acquire (LDAPR) instructions introduced in 

the ARMv8.3 extension, and the Dot Product instructions introduced in the ARM'v8.4 extension. 

:-he core har, :i LC"(' . L 1 memof\· ~ yqem :ma pn-. :ire LC', c _, , :.._ cache :-he core h 11nplememed 

l!! de •he D··n~mIQ Shared Cmt ,osr· 1 1 L1°le core. nd • lud1l\' conhgur.1ble wnh other core~ 

The following figure shows an ex.ample of a. dua.l-core configuration. 

Cluster 

1~"~'-] 

Cortex-A55 

Gore 1 

DSU 

'----~ 

Ex rn l memory interface+ 

~t+- terrupt interface-~•• 

...._""' Power management and--+ 

....- dock control • 

i,+,,,--- T ; 

""'"Co eS t infrastructure-+ 

Figure A'il-1 Example dual-core configuration wrth homogeneous cores 

ARM® Co1tex®-A55 Core, Revision rlpO, Technical Reference Manual 

Page3 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 4 of 13 PageID #: 249
Claim 1 

a second processor, 

coupled to fetch 

instructions and access 

data through a second 

cache contr·oller; 

A first processor (core) of the 

fom ARM Cortex A-5 5 cores 

is coupled to fetch instructions 

and access data through a 

cache contr·oller of its private 

Ll I and LID caches. 

Identification: Moto Edge1 

DynamlQ cluster 

UTTLEcore(O] LITTLE core[1] big core[4) 

~ I L11 ~ L1 D 1 I L1 l ~ L1 D I 

I 

L 1 I I L 1 D 

--- I L2 

LITTLE core(2] LITTLE core(3] big core[5) 

I L11 ~ L1 D 1 I L1 I ~ L1 D I 

I 

L 1 I I L 1 D 

I L2 

DynamlQ Shared Unit 

Asynchronous bridges 

Snoop Control Unit and L3 cache I ACP interface I 

I L3 cache 11 Snoop filter I 1;:::===o=~n=~~=~==: =~:=ck=~ Debug Block 

Memory interface 11 Peripheral port I 

Figure A1-1 DynamlQ cluster 

ARM® Cortex®-A55 Core, Revision rlpO, Technical Reference Manual, p. Al-26 

Ann® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. Al -20 

Page 4 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 5 of 13 PageID #: 250
Claim 1 Identification: Moto Edge1 

A second processor (core) of the four 

ARM Co11ex A-55 cores is coupled to 

fetch instructions and access data 

through a cache conti·oller of its 

private Ll I and LID caches. 

Cl'uster 

Cortex-A55 

Core 0 

♦ ,External memory interface-.. 

~....,- Interrupt lerface----1111► 

osu "" ower management and...,.. 

. ~--~ ~ ~t-+---- dock FToontro ---~-• l ~ ♦ • CoreSight infrastructure...,._ 

DynamlQ cluster ~----~ LITTLE ccn(0] LITTLE core[1] big core[4) 

; : L1 I ~ L1 D : ~ ~I _L_1_1 -Li-2 -L-1 D~I 

LITTLE core(2] LITTLE core(3] big core[5] 

~ ~ 1~- L-1-,- L~l2_ L1_D~ I 

DynamlQ Shared Unit 

I Asynchronous bridges I 

Snoop Control Unit and L3 cache I ACP interface I 

I L3 cache II Snoop filter I I Debug Block Debug Block interface 

I Memory interface II Peripheral port I 

Figure A1 -1 DynamlQ cluster 

ARM® Cortex®-A55 Core, Revision rlpO, Technical Reference Manual, p. Al-26 

Ann® DvnamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. Al -20 

Page 5 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 6 of 13 PageID #: 251
Claim 1 Identification: Moto Edge1 

a plurality of cache A plurality of cache memo1y blocks exists in the L3 cache shared by all ARM cores in a DynamIQ cluster and 

memo1y blocks; partitioned into groups of 4 cache ways (blocks). 

DynamlQ cluster 

LITTLE core(OJ LITTLE core(1] big core[4] 

I l1 1!L1D 1 I l 1 1!l1D 1 

I 

L1 I I l1 D 

I 

L2 

LITTLE core(2J LITTLE core(3] big core[5] 

I l1 1!L1D 1 I l 1 1!l1D 1 

I 

L1 I I l1 D 

I 

L2 

DynamlO Shared Unit 

I Asynchronous bridges I 

Snoop Control Unit and L3 cache 

I 

ACP interface I 

I L3 cache II Snoop filter I I OebugBlock DebugBlocl< interface 

I 

Memory interface 

II 

Peripheral port I 

Figure A1-1 DynamlQ cluster 

Within the DSU, the L3 cache, the Snoop Control Unit (SCU), internal interfaces to the cores, and 

external interfaces to the SoC are present. 

Ann® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. Al-20 

Page6 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 7 of 13 PageID #: 252
Claim 1 

a high-speed 

interconnect coupling 

the plmality of cache 

memo1y blocks to the 

first and second cache 

controllers such that at 

least one allocable 

cache mem01y block is 

capable of being used 

by the first and second 

cache controllers; and 

Identification: Moto Edge1 

About the L3 cache 

iThe opuon:il L3 oche 1s slmed bY :ill the cores 111 the clmter 

Ann® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. A5-64 

A high-speed interconnect ( e.g., Coherent Interconnect) couples the cache memo1y blocks of shared L3 cache 

to the first and second cache controllers (e.g., of the LID and Lll caches of the first and second cores). 

L3 cache allocation policy 

The L3 cache data allocation policy changes depending on the pattern of dat.a usage. 

Exclusive allocation is used when data is allocated in only one core. L.'-h i._ e lk '- tio1 I'> 1 t 1 hu 

d'\ee,1 1e . 

For example, an initial request from core O allocates data in the Ll or L2 caches but is not allocated in 

the L3 cache. When data is evicted from core 0, the evicted data is allocated in the L3 cache. The 

allocation policy of this cache line is still exclusive. If core O refetches the line, it is allocated in the L 1 or 

L2 caches of core O and removed from the L3 cache, keeping the line exclusive. If core 1 then accesses 

the line for reading, it rema.ins cached in core O and is also allocated in both core 1 and L3 caches. iin this 

case, the line has inclusive allocation. 

Ann® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. A5-65 

Page? 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 8 of 13 PageID #: 253
Claim 1 

a resource allocation 

controller coupled to 

detennine an accessing 

cachemem01y 

controller selected 

from the group 

consisting of the first 

and second cache 

memo1y controllers, 

whereb the accessin 

DynamlQTM Cluster 

Identification: Moto Edge1 

DynamlQTM Cluster 

LITTLE 

Core 

111D 11111.!m 

t 

LITTLE 

Core 

111D 11111.!m 

https://community.ann.com/developer/ip-products/system/b/soc-design-blog/posts/using-po1t able-stimulus-inthe-ann-world-creating-bare-metal-sw-coherency-scenarios 

A resource allocation controller (e.g., pa1t of the Snoop Control Unit and L3 cache) is coupled (e.g., to the 

CLUSTERPARTCR register) to determine an accessing cache memo1y controller selected from the first and 

second cache controllers, whereby the accessing cache memo1y controller is allowed to access the allocable 

cache memo1y block (in shared L3 cache). 

Page 8 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 9 of 13 PageID #: 254
Claim 1 Identification: Moto Edge1 

cachemem01y DynamlQ cluster 

controller is allowed to LITnEcore(O] LITnE core[1] big core[4] 

access the allocable I L1 1ll 1 D 1 I L1 1ll1 D 1 

I 

L 1 I I L1 D 

I cache mem01y block, L2 

wherein the cache LITnEcore(2] LITnE core[3J big core[5] 

memo1y blocks are I L1 1ll 1 D 1 I L1 1ll 1 D 1 

I 

L 1 I I L1 D 

usable by the cache I L2 

controllers to store data DynamlQ Shared Unit 

and instructions 

fetched from a I Asynchronous bridges I 

random-access Snoop Control Unit and L3 cache 

I 

ACP interface 

I 

memo1y. I 

L3 cache I I Snoop filter 

I 

DebugBlock Debug Block 

interface 

I Memory interface II Peripheral port I 

Figure A1-1 DynamlQ cluster 

About the L3 cache 

- :1 pti011"l :.. ~ ,....,che i 1 I l • '<1 ·1e core., l •1 ·lu 

["he L3 cache suuu.ru1s a clvnam1callv oorumzed allocation nolicv Grano-, ot cache\\ av'> can b~ 

parntionecl;i'i'io :t'>'>1gned to iuctivichial proce<,se'> a11o\\ ing carne allocation to be ra111v ~Ti;i"i"ed l.frtween 

li:)1 ocesse<, I 

Page 9 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 10 of 13 PageID #: 255
Claim 1 Identification: Moto Edge1 

L3 cache partitioning 

The L3 cache supports a partitioning scheme that alters the victim selection policy to avoid one core ( or 

one group of cores) from utilizing the entire cad1e at the expense of another core_ 

Cache partitioning is intended for specialized software where there are distinct classes of processes 

running w-id1 different cache accesses patterns_ 

For example, two processes (A and B) run on separate cores in the same duster and therefore share the 

L3 cache. If process A is more data.-intensive than process B, process A might cause all cache lines 

allocated by process B to be evicted_ In this case, the performance of process B might be reduce-el. 

t lt" C ll'>l l <, e :l',',iQned to vm. v t 1e ei~' c ~1 

... 1 e L .., l- , of '- ,_-, , E ,: 1) l- ._ 1 • r, r._ 1 ._ '-• ,.. , .\. group can be 

as<;.igned as private to 011..e or more scheme IDs. or it can be left unassigned. An unassigned group can be 

shared between all scheme IDs_ Accesses from a given core can allocate into any cache way that is 

assigned as private to that core's partition scheme ID, or to any cache way that is shared. 

An n® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, pp. A.1-20, A.5-64, A.5-66 

Page 10 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 11 of 13 PageID #: 256
Page 11 

CLUSTERPARTCR, Cluster Partition Control Register 

The CLUSTERPARTCR register controls a group of ways to be marked as private to a schem

register is RW. 

This description applies to both the AArch32 (CLUSTERPARTCR) and AArch64 

(CLUSTERPARTCR_ELl) registers. 

Bit field descriptions 

CLUSTERPARTCR is a 32-bit register, and is part of SCU and L3 cache configuration regis

31 30 29 28 27 26 25 24 23 22 212019 18 17 16 1514 1312 11 10 9 8 7 6 5 4 

I I I I I I I I I I I I I I I I I I I I I 

W3_1D7J JJ 

W2_ID7 

W1_ID7 

W0_ID7-

W3_ID6-

W2_ID6-

W1_ID6-

W0_ID6-

W3_ID5-

W2_ID5-

W1_ID5-

W0_ID5-

W3_ID4-

W2_ID4-

W1_ID4-

W0_ID4-

W3_ID3-

W2_ID3-

W1_ID3-

W0_ID3-

W3_ID2-

W2_ID2-

W1_ID2-

W0_ID2-

W3_ID1-

W2_ID1-

W1_ID1-

W0_ID1-

W3_ID

W2

W

Figure B1-8 CLUSTERPARTCR bit a

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 12 of 13 PageID #: 
Claim 1 Identification: Moto Edge1 

..-...-n-.s.-,hr-+-tlcr 1. m :D If more- t! .. 

• '11, 3ic 1i1c11 tuoc,e \\"3\"<, 31e <,i131 • • 

\\"3\, not 3,s1gnel to 311\ c,che1 

• • " p1 i, 3te \\ 3\ ', :li! 

.__ _______ -:,__-_-_--::_----~--~_-_-~~:;:=:::::.=.----~-------------------~-----' 

01 

Ann® DynamIQTM Shared Unit, Revision r3p0, Technical Reference Manual, p. Bl-132 

The Lenovo Tab Pl2 Pro comes with 6/8 GB of RAM 

Specifications 

Proc,essor 

Operating 

system 

Memory 

Display 

Brightness 

Battery 

Camera 

Connection ports 

Qualcom m Snapdragon 870 

Android 11 (Upgradable to Android 12W 

B • P •• , 1281256GB of storage, expandable up to 1TB via MicroSD 

12.6-1nch, 2K {2,560 x 1,600) OLED panel with 120Hz 

600 nits 

10,200mAh, 30W charging 

13MP r,ear camera (auto -focus) with a 5MP wide angle, SMP front (fixed-focus) 

Micro USB-C 2:0, 4-po int Pogo pins, keyboard connector slots, MicroSD card slot, stylus 

port 

Page 12 

Case 2:23-cv-00443-JRG Document 1-17 Filed 09/27/23 Page 13 of 13 PageID #: 258