EXHIBIT 19

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 1 of 8 PageID #: 278
Claim 1 

r1 pre l A computerimplemented method for use in 

a computer system including a 

plurality of resources, the 

method comprising steps of: 

US Patent No. 779307539 

Identification 

To the extent the preamble is limiting, the Google Pixel 6 uses an ARMv8-A based processor that implements a 

method for use in a computer system including a plurality of resources comprising the steps below. 

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The Motorola razi+ includes the Google Tensor mobile platfo1m processor, which uses an ARM Cortex-A55 

CPU. 

Page 1 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 2 of 8 PageID #: 279
Claim 1 

CPU 

GPU 

RAM 

ML 

Media 

Decode 

Google Tensor 

(2021) 

2x Arm Cortex-X1 

(2.80GHz) 

2x Arm Cortex-A76 

(2.25GHz) 

4x Arm Cortex-A55 

(1.80GHz) 

Arm Mali-G78 

MP20 

LPDDR5 

Tensor Processing 

Unit 

H.264, H.265, VP9, 

AV1 

Identification 

https://www.androidauthority.com/google-tensor-3060818/ 

Page2 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 3 of 8 PageID #: 280
Claim 1 Identification 

The Cortex-A55 core is a mid-range, low-power core d1at implements the ARMv8-A architecture with 

support for the v8.2 extension, the RAS extension, the Load acquire (LDAPR) instructions introduced in 

die A . .R.Mv8.3 extension, and the Dot Product instructions introduced in the ARMv8.4 extension. 

ARM® Cortex®-A55 Core, Revision rlp0, Technical Reference Manual 

I Security in an ARMv8-A system 

A secure or lrusled syslem is one thal proleas asselS, for example passwords or credit card 

details from a range of plausible attacks. to prevent them from being cQpied or damaged. or made 

unavailable. 

Security is defined by the principles of: 

Security in an ARMv8-A System (ht!J2s://develoQer.ann.com/documentation/100935/0100/Security-in-ARMv8-

A-svstems-?lan~=en) 

[1] (A) receiving a request from The system receives a request from a software program (such as a software application or OS) to access a 

a software program to access a resource, such as a nonnal world resource or a secure world resource. 

specified one of the plurality of 

resources; 

Page3 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 4 of 8 PageID #: 281
Claim 1 Identification 

Nonnal wotld Secure wotld 

EL0 ( ~~) ( ~bt~) ( Applcation) ( Applcation) : ( Sewre finnware ) 

---------------------------------~--------------- EL 1 ( Guest OS ) ( Guest OS ):( Trusted OS ) ---------------------------------7---------------· 

EL2 ( HypeMSOr ) : No E~re 

-------------- EL3 ( SmRmanlar ) 

Figure I Security model for AArch64 

The ARM Architecture Reference Manual uses the terms Secure and Non-secure to refer to 

system security states. A Non-secure state does not automatically mean security vulnerability, but 

rather normal operation and is therefore the same as the Normal world. Typically, there is a 

master and slave relationship between Non-secure and Secure worlds. Code in the Secure world is 

only executed when the OS permits Secure world execution through a mechanism that is initiated 

by the Secure Monitor Call (SMC) instruction. 

Security in an ARMv8-A System at 5 

r1 l (B) determining whether the A determination is made whether the specified one of the plurality of resources is a protected resource. For 

specified one of the plurality of example, whether the resource is in secure world or nonnal world. 

resources is a protected The ARM Security Extensions model allows system developers to partition device hardware and 

resource; software resources, so that they exist in either the Secure world for the security subsystem, or the 

Normal world for everything else. Correct system design can ensure that no Secure world assets 

can be accessed from the Normal world. A Secure design places all sensitive resources in the 

Secure world, and ideally has robust software running that can protect assets against a wide range 

of possible software attacks. 

Security in an ARMv8-A System at 5 

Page4 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 5 of 8 PageID #: 282
Claim 1 

[1] (C) if the specified one of 

the plurality of resources is a 

protected resource, perfonning 

steps of: 

[l(C)] (1) if the computer 

system is operating in a 

protected mode of operation, 

then denying the request 

regardless of access rights 

associated with the software 

program including software 

programs having a mostprivileged level; and 

Identification 

If the specified one of the plurality of resources is a protected resource ( e.g., in secure world), the steps below are 

perfo1med. 

If the computer system is operating in a protected mode of operation, then the request is denied regardless of 

access rights associated with the software program including software programs having a most-privileged level. 

For example, if the Secure Monitor Disable bit is set to disable, Secure Monitor Call (SMC) instmctions, required 

to access secure world resources, are disabled. 

D19.2.120 SCR_EL3, Secure Configuration Register 

TI1e SCR EL3 characteristics are: 

Purpose 

Defines the configlll·ation of the cun-ent Secmity state. It specifies: 

• The Secmity state ofELO. ELL and EL2. The Security state is Secure. Non-secme. or Reahu. 

• The Execution state at lower Exception levels. 

• Whether IRQ. FIQ. SEirnr intem1pts. and Extemal abo1t exceptions are taken to EL3. 

• Whether ,·a1ious operations are trapped to EL3. 

Alm Ai·chitecture Reference Manual for A-Profile Ai·chitecture at D19.2.29 

(https ://developer.arm.com/ documentation/ ddi048 7 /latest/) 

Page 5 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 6 of 8 PageID #: 283
Claim 1 Identification 

SMD, bit [7] 

Secure Monitor Call disable. Disables SMC instmctions at ELl and above. from any Security state 

and both Execution states. repo11ed using an ESR_ELx.EC Yalue of0x00. 

0b0 SMC instructions are enabled at EL3. EL2 and ELI. 

0bl SMC instrnctions are UNDEFINED. 

~Ott 

SMC instructions ai-e always UNDEFINED at ELO. Any resulting exception is taken from the cm1·ent 

Exception leYel to the Ctlffent Exception level. 

IfHCR_EL2.TSC or HCR.TSC traps attempted ELl execution of SMC instructions to EL2. that trap 

has priority oYer this disable. 

The reset behavior of this field is: 

. On a Wann reset. this field resets to an architecturally UNKNOWN value . 

Alm AI·chitecture Reference Manual for A-Profile AI·chitecture at D19-6959. 

The Secure Monitor Call (SMC) instruction proYides softv.-are with a system call to EL3. When executing at a 

p1frileged Exception le,·el. SMC instrnctions generates exceptions. For more infonnation. see Secure Moniror Call 

(SMC) esception on page Gl-9811 and SMC on page F5-8734. I 

Figure G 1- 1 sho,vs that when EL3 is using AArch32. the Exception levels and modes available in each Secmity 

state are as follows: 

Secure state 

ELO User mode. 

EL3 Ally mode that is available in Secure state. other than User mode. 

Alm AI·chitecture Reference Manual for A-Profile AI·chitecture at Gl-9748-49. 

Page6 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 7 of 8 PageID #: 284
Claim 1 Identification 

[l(C)] (2) processing the If the computer system is not operating in the protected mode of operation (e.g., SMD set to 0), then the request 

request based on the access is processed based on access rights associated with the software program. 

rights associated with the 

software program if the The ARM Architecture Reference Manual uses the terms Secure and Non-secure to refer to 

computer system is not system security states. A Non-secure state does not automatically mean security vulnerability, but 

operating in the protected mode rather normal operation and is therefore the same as the Normal world. Typic:ally, there is a 

master and slave relationship between Non-secure and Secure worlds. Code in the Secure world is 

of operation. only executed when the OS permits Secure world execution through a mechanism that is initiated 

by the Secure Monitor Call (SMC) instruction. 

N ote 

The use of the word world is used to describe not just the Execution state, but also all 

memory and peripherals that are accessible in that state. Non-secure memory and 

functions are also accessible to the Secure world. 

The role of the Secure monitor is to provide a gatekeeper which manages the switches between 

the Secure and Non-secure worlds. In most designs its functionality is similar to a traditional 

operating system context switch, ensuring that state of the world that the core is leaving is safely 

saved, and the state of the world the processor is switching to is correctly restored. 

Security in an ARMv8-A System at 5 

Page? 

Case 2:23-cv-00443-JRG Document 1-20 Filed 09/27/23 Page 8 of 8 PageID #: 285