# Patent

## Title
Photodetector including integration capacitance section and A/D converter circuit

## Abstract

An integration circuit 10 comprises: an amplifier and an integration capacitance section arranged in parallel to each other between an input terminal and an output terminal; and capacitance value switching means for switching the capacitance value of the integration capacitance section into any one of Cf1 through CfK; and inputs electric charge output from a photodiode PD, so as to accumulate the electric charge into the integration capacitance section, so as to output an integration voltage having a value corresponding to the amount of the accumulated electric charge. An A/D converter circuit 20 comprises reference voltage switching means for switching a reference voltage used in A/D conversion, into any one of Vref,1 through Vref,L, and inputs the integration voltage output from the integration circuit 10, so as to A/D-convert the integration voltage on the basis of the reference voltage switched and set to be by the reference voltage switching means, so as to output a digital value corresponding to the integration voltage.

## Background
FIELD OF THE INVENTION
The present invention relates to a photodetector comprising an A/D converter circuit for converting an analog value into a digital value.
BACKGROUND ART
A photodetector comprises a photodetection element or a plurality of photodetection elements. The electric charge output from each photodetection element is integrated by an integration circuit, so that the integration result is output as a voltage. In a certain photodetector, the analog value of this voltage is converted into a digital value (A/D conversion), so that the digital value is output. When the voltage exceeds a predetermined value in this A/D conversion, the digital value output as a result of the A/D conversion of the voltage is saturated at a value corresponding to the predetermined value. This causes a problem where accurate photodetection is not achieved. Thus, in the prior art, the above-mentioned predetermined value is set to be an expected maximum value or larger in order to prevent the saturation.
On the other hand, it is desired to expand the range of the analog value (that is, dynamic range) that can be A/D-converted without saturation. Several techniques for this have been proposed. For example, a technique is known where the dynamic range is expanded using logarithmic compression. In this logarithmic compression technique, a photodiode (photodetection element) and a MOS transistor are connected. Then, when the electric potential of the connection point between these two components is denoted by “V,” and when the electric current flowing from the photodiode to the MOS transistor is denoted by “I,” the relational expression I=A·exp(q(V−Vth)/kT) holds and is used. Here, “A” indicates a proportional constant; “q” indicates the amount of electric charge of the electron; “Vth” indicates the threshold voltage of the MOS transistor; “k” indicates Boltzmann's constant; and “T” indicates the absolute temperature. As seen from this relational expression, for a low incident light intensity (that is, for a small I), a large change is caused in the output voltage V by a change in the incident light intensity. On the contrary, for a high incident light intensity (that is, for a large I), a small change is caused in the output voltage V by a change in the incident light intensity. By virtue of this, the dynamic range is expanded.
DISCLOSURE OF THE INVENTION
However, in this logarithmic compression technique, the I-V characteristic depends on the temperature T as seen from the above-mentioned relational expression. This causes a problem where a change in the temperature T results in a change in the signal level. Furthermore, for a low incident light intensity (that is, for a small I), a large change is caused in the output voltage V by a change in the incident light intensity. Thus, the dark current is amplified notably and affects the output voltage V. This causes the problem of an additional change in the signal level. Furthermore, the MOS transistor has its own threshold voltage Vth, the different transistor has the different value, and causes the problem of another additional change in the signal level.
The invention has been devised in order to resolve the above-mentioned problems. An object of the invention is to provide a photodetector in which the dynamic range is expanded while a change in the signal level caused by the above-mentioned reasons is prevented.
A photodetector according to the invention comprises: (1) a photodetection element for outputting electric charge in an amount corresponding to incident light intensity; (2) an integration circuit which is provided with: an amplifier and an integration capacitance section arranged in parallel to each other between an input terminal and an output terminal; and capacitance value switching means for switching the capacitance value of the integration capacitance section into any one of first through K-th capacitance values (where K indicates an integer greater than or equal to 2); and which inputs electric charge output from the photodetection element through the input terminal, so as to accumulate the electric charge into the integration capacitance section having the capacitance value switched into by the capacitance value switching means, so as to output through the output terminal a voltage corresponding to the amount of accumulated electric charge; and (3) an A/D converter circuit which is provided with reference voltage switching means for switching a reference voltage used in A/D conversion, into any one of first through L-th reference voltages (where L indicates an integer greater than or equal to 2), and which inputs the voltage output through the output terminal of the integration circuit, so as to A/D-convert the voltage on the basis of the reference voltage switched and set to be by the reference voltage switching means, so as to output a digital value corresponding to the voltage.
According to this photodetector, electric charge in an amount corresponding to the light intensity incident on the photodetection element is output from the photodetection element to the integration circuit, and then accumulated in the integration capacitance section of the integration circuit. The integration circuit outputs a voltage corresponding to the amount of electric charge accumulated in the integration capacitance section, so that the voltage is A/D-converted by the A/D converter circuit. The A/D converter circuit outputs a digital value corresponding to the voltage. For a high incident light intensity, the capacitance value of the integration capacitance section of the integration circuit is switched into a large value among the first through K-th capacitance values by the capacitance value switching means, while the reference voltage used in the A/D conversion of the A/D converter circuit is switched into a large value among the first through L-th reference voltages by the reference voltage switching means. This permits the detection of incident light intensity without saturation. In contrast, for a low incident light intensity, the capacitance value of the integration capacitance section of the integration circuit is switched into a small value among the first through K-th capacitance values by the capacitance value switching means, while the reference voltage used in the A/D conversion of the A/D converter circuit is switched into a small value among the first through L-th reference voltages by the reference voltage switching means. This suppresses a change in the signal level caused by dark current, and hence permits high-sensitivity detection of the incident light intensity.
In the photodetector according to the invention, it is preferable that when the k-th capacitance value among the first through K-th capacitance values is denoted by Cfk, the relational expression Cf1>Cf2> . . . >Cfk> . . . >CfK−1>CfK holds, while when the l-th reference voltage among the first through L-th reference voltages is denoted by Vref,1, the relational expression Vref,1>Vref,2> . . . >Vref,l> . . . >Vref,L−1>Vref,L holds. The photodetector according to the invention further comprises: (1) a storage section which is provided with first through K-th storage regions and storage region switching means for switching the region into any one of these regions, and which stores the digital value output from the A/D converter circuit, into any storage region switched into and selected from the first through K-th storage regions by the storage region switching means; and (2) controlling means which controls the capacitance value switching means of the integration circuit, the reference voltage switching means of the A/D converter circuit, and the storage region switching means of the storage section, so as to set the capacitance value of the integration capacitance section of the integration circuit to be the k-th capacitance value Cfk, set the reference voltage of the A/D converter circuit to be the l-th reference voltage Vref,l, and store the digital value output from the A/D converter circuit into the k-th storage region.
In this case, under the control of the controlling means, the capacitance value of the integration capacitance section of the integration circuit is set to be the k-th capacitance value Cfk, while the reference voltage of the A/D converter circuit is set to be the first reference voltage Vref,1. Then, the digital value output from the A/D converter circuit is stored into the k-th storage region of the storage section (k=1 through K). On the basis of the digital values stored, respectively, in the K storage regions of the storage section, the intensity of the light received by the photodetection element is detected with no saturation even for a high intensity and with high sensitivity even for a low intensity.
In the photodetector according to the invention, it is preferable that a plurality of photodetection elements are provided and arranged in two dimensions of M rows by N columns (M≧2, N≧2), while an integration circuit and an A/D converter circuit are arranged for each column of the photodetection elements arranged in two dimensions.
In this case, an optical image is acquired by a plurality of the photodetection elements arranged in two dimensions of M rows by N columns. At that time, the capacitance value of the integration capacitance section of the integration circuit and the reference voltage of the A/D converter circuit are set appropriately for each pixel. As a result, the light intensity in each pixel of the acquired optical image is detected with no saturation even for a high intensity and with high sensitivity even for a low intensity.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic configuration diagram showing a photodetector 1 according to an embodiment.
FIG. 2 is a circuit diagram showing an integration circuit 10 of a photodetector 1 according to an embodiment.
FIG. 3 is a circuit diagram showing an A/D converter circuit 20 of a photodetector 1 according to an embodiment.
FIG. 4A is a block diagram showing a storage section 200.
FIG. 4B is a diagram illustrating a 12-bit digital value output from a storage section 200.
FIG. 5A is a block diagram showing a storage section 200.
FIG. 5B, FIG. 5C, and FIG. 5D are diagrams illustrating an 8-bit digital value output from a storage section 200.



BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the invention are described below in detail with reference to the attached drawings. Herein, like components are designated by like reference numerals, so that duplicated description is omitted.
FIG. 1 is a schematic configuration diagram showing a photodetector 1 according to an embodiment. This photodetector 1 comprises N units 1001–100N (N is an integer greater than or equal to 2), a storage section 200, and a control circuit 300. Each unit 100n (n is an arbitrary integer greater than or equal to 1 and smaller than or equal to N) comprises: M sets (M is an integer greater than or equal to 2) of photodiodes (photodetection elements) PD and switches SW; an integration circuit 10; an A/D converter circuits 20; and a switch SW1. The anode terminal of each photodiode PD is grounded, while the cathode terminal is connected through the switch SW to the integration circuit 10. When a corresponding switch SW is closed, each photodiode PD outputs electric charge in an amount corresponding to the incident light intensity, to the integration circuit 10.
FIG. 2 is a circuit diagram showing the integration circuit 10 of the photodetector 1 according to this embodiment. The integration circuit 10 of each unit 100n, comprises an amplifier A10, capacitors Cf1–Cf3, and switches SW10–SW13. In the amplifier A10, a standard voltage Vinp1 is input through a non-inverting input terminal, while an inverting input terminal is connected through a switch SW to the cathode terminal of the photodiode PD. The switch SW10, a serial connection of the capacitor Cf1 and the switch SW11, a serial connection of the capacitor Cf2 and the switch SW12, and a serial connection of the capacitor Cf3 and the switch SW13 are arranged in parallel to each other between the inverting input terminal and the output terminal of the amplifier A10.
The open and close operation of each of the switches SW10–SW13 is controlled by the control circuit 300. The capacitance values of the capacitors Cf1–Cf3 differ from each other. When the capacitance value of the capacitor Cf1 is denoted by Cf1, and so on, the following relational expression holds.

Cf1>Cf2>Cf3  (1)

The capacitors Cf1–Cf3 serve as components constituting an integration capacitance section the capacitance value of which is variable. The switches SW11–SW13 serve as capacitance value switching means for switching the capacitance value of the integration capacitance section in to any value. That is, when the switch SW11 among the switches SW11–SW13 is solely closed, the capacitance value of the integration capacitance section equals the capacitance value Cf1 of the capacitor Cf1. When the switch SW12 is solely closed, the capacitance value of the integration capacitance section equals the capacitance value of the capacitor Cf2. When the switch SW13 is solely closed, the capacitance value of the integration capacitance section equals the capacitance value of the capacitor Cf3. The integration circuit 10 inputs the electric charge output from the photodiode PD, so as to accumulate the electric charge into the integration capacitance section having any one of the capacitance values Cf1–Cf3, so as to output through the output terminal an integration voltage corresponding to the amount of the accumulated electric charge. When closed, the switch SW10 discharges the electric charge accumulated in the capacitor Cf1–Cf3, so as to reset the output level of the integration circuit 10.
FIG. 3 is a circuit diagram showing the A/D converter circuit 20 of the photodetector 1 according to this embodiment. The A/D converter circuit 20 of each unit 100n comprises a coupling capacitor C201, a feedback capacitor C202, a switch SW202, an amplifier 201, a comparator 202, a capacitance control section 203, and a variable capacitance section 240.
In the amplifier 201, the integration voltage (analog value) output from the integration circuit 10 is input through the inverting input terminal via the coupling capacitor C201, while a standard voltage Vcom is input through the non-inverting input terminal. The feedback capacitor C202 is arranged between the inverting input terminal and the output terminal of the amplifier 201, so as to store electric charge corresponding to the input voltage. The switch SW202 is arranged between the inverting input terminal and the output terminal of the amplifier 201. When being open, the switch SW202 causes the feedback capacitor C202 to accumulate electric charge. When being closed, the switch SW202 resets the electric charge accumulation in the feedback capacitor C202. Then, the amplifier 201 outputs a voltage corresponding to the amount of electric charge accumulated in the feedback capacitor C202, through the output terminal to the comparator 202. In the comparator circuit 202, the voltage output from the amplifier 201 is input through the inverting input terminal, while the standard voltage Vcom is input through the non-inverting input terminal, so that these two input values are compared to each other, so that a signal indicating the comparison result is output to the capacitance control section 203.
The variable capacitance section 240 comprises four capacitors C241–C244 and four switches SW241–SW244 (voltage switching means). One end of the capacitor C241 is connected to the inverting input terminal of the amplifier 201, while the other end is connected through the switch SW241 to any one of reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom. One end of the capacitor C242 is connected to the inverting input terminal of the amplifier 201, while the other end is connected through the switch SW242 to any one of the reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom. One end of the capacitor C243 is connected to the inverting input terminal of the amplifier 201, while the other end is connected through the switch SW243 to any one of the reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom. One end of the capacitor C244 is connected to the inverting input terminal of the amplifier 201, while the other end is connected through the switch SW244 to any one of the reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom.
The capacitance values of the capacitors in the variable capacitance section 240, as well as the coupling capacitor C201 and the feedback capacitor C202, satisfy the following relational expressions.

C201=C202=16C  (2a)

C241=8C  (2b)

C242=4C  (2c)

C243=2C  (2d)

C244=C  (2e)

Here, C indicates a certain constant capacitance value. Furthermore, the reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom supplied to the variable capacitance section 240 satisfy the following relational expressions.

Vref2−Vcom=(Vref1−Vcom)/16  (3a)

Vref3−Vcom=(Vref2−Vcom)/16  (3b)

In general, the standard voltage Vcom is set to be the ground potential. Thus, Vcom=0 is assumed hereinafter. In this case, the above-mentioned Equations (3) are rewritten into the following relational expressions.

Vref1/Vref2=16  (4a)

Vref2/Vref3=16  (4b)

The reference voltages Vref1, Vref2, and Vref3 and the standard voltage Vcom are supplied, for example, from a resistance dividing circuit (not shown).
The capacitance control section 203 and the switches SW241–SW244 serve as reference voltage switching means for switching the reference voltage used in A/D conversion, into any one of Vref1, Vref2, and Vref3, and are controlled by the control circuit 300. The capacitance control section 203 stores the switching status in each of these four switches, so as to output a 4-bit digital value on the basis of the switching status and the signal output from the comparator 202. The A/D converter circuit 20 inputs the integration voltage output from the output terminal of the integration circuit 10, so as to A/D-convert this voltage on the basis of the reference voltage (any one of Vref1, Vref2, and Vref3) switched and set to be by the reference voltage switching means, so as to output a digital value.
As shown in FIG. 1, the storage section 200 comprises a first storage region 211, a second storage region 212, a third storage region 213, and storage region switching means 220. The storage region switching means 220 selects any one of the first storage region 211, the second storage region 212, the third storage region 213, so as to store the digital value output from the A/D converter circuit 20 of each unit 100n via the switch SW1, into the selected storage region.
The control circuit 300 controls the capacitance value switching means of the integration circuit 10, the reference voltage switching means of the A/D converter circuit 20, and the switch SW1 in each unit 100n, and also controls the storage region switching means 220 of the storage section 200. More specifically, the control circuit 300 closes the switch SW1k solely among the switches SW11–SW13 of the integration circuit 10, so as to set the capacitance value of the integration capacitance section to be Cfk. The control circuit 300 further sets the reference voltage in the A/D converter circuit 20 to be Vref,k, and then stores the digital value output from the A/D converter circuit 20 into the k-th storage region 21k.
The operation of the photodetector 1 according to the present embodiment is described below. A series of operations of the photodetector 1 is separated into four stages.
In the first stage under the control of the control circuit 300, in the integration circuit 10 of each unit 100n, the switch SW11 is closed solely among the switches SW11–SW13, so as to set the capacitance value of the integration capacitance section to be Cf1. Then, the switch SW10 is closed temporarily so as to reset the output level of the integration circuit 10. After that, the switch SW10 is opened. Furthermore, under the control of the control circuit 300, in the A/D converter circuit 20 of each unit 100n, the switch SW202 is closed temporarily so as to discharge the feedback capacitor C202. After that, the switch SW202 is opened. In the initial state, each of the switches SW241–SW244 of the A/D converter circuit 20 is switched into the standard voltage Vcom. Furthermore, under the control of the control circuit 300, the reference voltage in the A/D converter circuit 20 is set to be Vref1, while the first storage region 211 is selected by the storage region switching means 220 of the storage section 200.
In each unit 100n, the electric charge output through the switch SW from the photodiode PD on which light is incident is input to the integration circuit 10, so as to be accumulated in the capacitor Cf1, so that a voltage Vin (=Q0/Cf1) corresponding to the amount of the accumulated electric charge Q0 is output from the integration circuit 10. The voltage Vin output from the integration circuit 10 is input to the A/D converter circuit 20. In the A/D converter circuit 20, electric charge in an amount corresponding to the voltage Vin output from the integration circuit 10 is accumulated in the feed back capacitor C202. The amount of electric charge Q accumulated in the feedback capacitor C202 satisfies the following relational expression.

Q=C202·Vin=16C·Vin  (5)

After that, the process of actual A/D conversion begins. In each of the four switches SW241–SW244 in the variable capacitance section 240, switching operation is performed between the reference voltage Vref1 and the standard voltage Vcom. First, the switch SW241 corresponding to the capacitor C241 having the largest capacitance value among the four capacitors C241–C244 is switched into the reference voltage Vref1. As a result, an amount of electric charge Q241 which is expressed by the following equation and which is a part of the amount of electric charge Q (above-mentioned Equation (5)) accumulated in the feed back capacitor C202 is transferred to the capacitor C241.

Q241=C241·Vref1=8C·Vref1  (6)

Furthermore, an amount of electric charge Q202 which is expressed by the following equation and which is a part of the amount of electric charge Q (above-mentioned Equation (5)) accumulated in the feedback capacitor C202 remains in the feedback capacitor C202.




  
    
      
        
          
            
              
                Q
                202
              
              =
              
              ⁢
              
                
                  16
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    ·
                    
                      V
                      in
                    
                  
                
                -
                
                  8
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    ·
                    
                      V
                      ref1
                    
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                16
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      V
                      in
                    
                    -
                    
                      
                        V
                        ref1
                      
                      /
                      2
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Then, the amplifier 201 outputs the voltage Vin−Vref1/2. The comparator 202 compares the voltage Vin−Vref1/2 input from the amplifier 201 to the inverting input terminal with the standard voltage Vcom (=0) input to the non-inverting input terminal, so as to determine the sign of the voltage Vin−Vref1/2. The result is input to the capacitance control section 203, so as to be stored as the value of the highest bit D3 to be output. That is, when the voltage Vin−Vref1/2 is positive, D3=1 is stored. Otherwise, D3=0 is stored.
When the voltage Vin−Vref1/2 is positive, the switch SW242 corresponding to the capacitor C242 having the next largest capacitance value is switched into the reference voltage Vref1. As a result, an amount of electric charge Q242 which is expressed by the following equation and which is a part of the amount of electric charge Q202 (Equation (9)) accumulated at that time in the feedback capacitor C202 is transferred to the capacitor C242.

Q242=C242·Vref1=4C·Vref1  (8)

Furthermore, an amount of electric charge Q202 which is expressed by the following equation and which is a part of the amount of electric charge Q202 (Equation (9)) accumulated at that time in the feedback capacitor C202 remains in the feedback capacitor C202.




  
    
      
        
          
            
              
                Q
                202
              
              =
              
                
                  16
                  ⁢
                  
                    
                  
                  ⁢
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  
                    (
                    
                      
                        V
                        
                          i
                          ⁢
                          
                            
                          
                          ⁢
                          n
                        
                      
                      -
                      
                        
                          V
                          ref1
                        
                        /
                        2
                      
                    
                    )
                  
                
                -
                
                  4
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    ·
                    
                      V
                      ref1
                    
                  
                
              
            
          
        
        
          
            
              =
              
                16
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      V
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                    
                    -
                    
                      3
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          V
                          ref1
                        
                        /
                        4
                      
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




Then, the amplifier 201 outputs the voltage Vin−3Vref1/4. The comparator 202 compares the voltage Vin−3Vref1/4 input from the amplifier 201 to the inverting input terminal with the standard voltage Vcom (=0) input to the non-inverting input terminal, so as to determine the sign of the voltage Vin−3Vref1/4. The result is input to the capacitance control section 203, so as to be stored as the value of the bit D2 to be output. That is, when the voltage Vin−3Vref1/4 is positive, D2=1 is stored. Otherwise, D2=0 is stored.
When the voltage Vin−3Vref1/4 is positive, the switch SW243 corresponding to the capacitor C243 having the next largest capacitance value is switched into the reference voltage Vref1. As a result, an amount of electric charge Q243 which is expressed by the following equation and which is a part of the amount of electric charge Q202 (above-mentioned Equation (7)) accumulated at that time in the feedback capacitor C202 is transferred to the capacitor C243.

Q243=C243·Vref1=2C·Vref1  (10)

Furthermore, an amount of electric charge Q202 which is expressed by the following equation and which is a part of the amount of electric charge Q202 (above-mentioned Equation (7)) accumulated at that time in the feedback capacitor C202 remains in the feedback capacitor C202.




  
    
      
        
          
            
              
                Q
                202
              
              =
              
                
                  16
                  ⁢
                  
                    
                  
                  ⁢
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  
                    (
                    
                      
                        V
                        
                          i
                          ⁢
                          
                            
                          
                          ⁢
                          n
                        
                      
                      -
                      
                        
                          V
                          ref1
                        
                        /
                        4
                      
                    
                    )
                  
                
                -
                
                  2
                  ⁢
                  
                    C
                    ·
                    
                      V
                      ref1
                    
                  
                
              
            
          
        
        
          
            
              =
              
                16
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      V
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                    
                    -
                    
                      7
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          V
                          ref1
                        
                        /
                        8
                      
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




Then, the amplifier 201 outputs the voltage Vin−7Vref1/8. The comparator 202 compares the voltage Vin−7Vref1/8 input from the amplifier 201 to the inverting input terminal with the standard voltage Vcom (=0) input to the non-inverting input terminal, so as to determine the sign of the voltage Vin−7Vref1/8. The result is input to the capacitance control section 203, so as to be stored as the value of the bit D1 to be output. That is, when the voltage Vin−7Vref1/8 is positive, D1=1 is stored. Otherwise, D1=0 is stored.
On the contrary, when the voltage Vin−Vref1/2 is negative in the determination of the value of the highest bit D3, the switch SW241 is returned to the standard voltage Vcom, while the amount of electric charge Q (above-mentioned Equation (5)) is entirely returned to the feedback capacitor C202. After that, the switch SW242 corresponding to the capacitor C242 having the next largest capacitance value is switched into the reference voltage Vref1. As a result, an amount of electric charge Q242 which is expressed by the following equation and which is a part of the amount of electric charge Q (above-mentioned Equation (5)) accumulated in the feedback capacitor C202 is transferred to the capacitor C242.

Q242=C242·Vref1=4C·Vref1  (12)

Furthermore, an amount of electric charge Q202 which is expressed by the following equation and which is a part of the amount of electric charge Q (above-mentioned Equation (5)) accumulated in the feedback capacitor C202 remains in the feedback capacitor C202.




  
    
      
        
          
            
              
                Q
                202
              
              =
              
                
                  16
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    ·
                    
                      V
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                    
                  
                
                -
                
                  4
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    ·
                    
                      V
                      ref1
                    
                  
                
              
            
          
        
        
          
            
              =
              
                16
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      V
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                    
                    -
                    
                      
                        V
                        ref1
                      
                      /
                      4
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




Then, the amplifier 201 outputs the voltage Vin−Vref1/4. The comparator 202 compares the voltage Vin−Vref1/4 input from the amplifier 201 to the inverting input terminal with the standard voltage Vcom (=0) input to the non-inverting input terminal, so as to determine the sign of the voltage Vin−Vref1/4. The result is input to the capacitance control section 203, so as to be stored as the value of the bit D2 to be output. That is, when the voltage Vin−Vref1/4 is positive, D2=1 is stored. Otherwise, D2=0 is stored.
As such, the switching statuses of the four switches SW241–SW244 in the variable capacitance section 240 are determined successively, so that the values of the bits D3–D0 are determined successively.
The above-mentioned operation is performed in parallel in each of the N units 1001–100N. Then, the switch SW1 of each unit 100n is closed successively, so that the digital value (D3–D0) output from the A/D converter circuit 20 of each unit 100n is stored in the first storage region 211 of the storage section 200. Furthermore, the above-mentioned operation is performed in parallel in each of the M photodiodes PD of each unit 100n. As such, in the first stage, the capacitance value of the integration capacitance section of the integration circuit 10 is set to be Cf1, while the reference voltage of the A/D converter circuit 20 is set to be Vref1, so that the digital value corresponding to the incident light intensity of each of the photodiodes PD arranged in M rows by N columns is stored in the first storage region 211 of the storage section 200.
The second stage following the first stage is almost the same as that of the first stage described above. The difference is that the capacitance value of the integration capacitance section of the integration circuit 10 is set to be Cf2, while the reference voltage of the A/D converter circuit 20 is set to be Vref2, so that the digital value corresponding to the incident light intensity of each of the photodiodes PD arranged in M rows by N columns is stored in the second storage region 212 of the storage section 200. Furthermore, the third stage following the second stage is almost the same as that of the first stage described above. The difference is that the capacitance value of the integration capacitance section of the integration circuit 10 is set to be Cf3, while the reference voltage of the A/D converter circuit 20 is set to be Vref3, so that the digital value corresponding to the incident light intensity of each of the photodiodes PD arranged in M rows by N columns is stored in the third storage region 213 of the storage section 200.
At the time of completion of the third stage, the digital values, respectively, stored in the first storage region 211, the second storage region 212, and the third storage region 213 of the storage section 200 are of 4-bit data. However, since the capacitance value of the integration capacitance section of the integration circuit 10 is different in each stage, and since the reference voltage of the A/D converter circuit 20 is different in each stage, the digital values stored in the storage regions are different from each other.
For example, when the reference voltages in the A/D converter circuit 20 satisfy the above-mentioned relational expressions of Equations (4), and when the capacitance values of the capacitors of the integration circuit 10 satisfy the following relational expressions, the digital value stored in the first storage region 211 is positioned higher than the digital value stored in the second storage region 212 by 4 bits.

Cf1/Cf2=16  (14a)

Cf2/Cf3=16  (14b)

Furthermore, the digital value stored in the second storage region 212 is positioned higher than the digital value stored in the third storage region 213 by 4 bits. However, when any bit of the 4-bit digital value (D3–D0) stored in the second storage region 212 has a value of 1, the 4-bit digital value stored in the third storage region 213 is saturated. Furthermore, when any bit of the 4-bit digital value (D3–D0) stored in the first storage region 211 has a value of 1, the 4-bit digital values stored in the second storage region 212 and the third storage region 213 are saturated.
Thus, in the fourth stage following the third stage, the 12-bit digital value (D11–D0) output from the storage section 200 corresponding to each of the photodiodes arranged in M rows by N columns is determined on the basis of the 4-bit digital values (D3–D0), respectively, stored in the first storage region 211, the second storage region 212, and the third storage region 213 of the storage section 200. That is, when any bit of the 4-bit digital value (D3–D0) stored in the second storage region 212 has a value of 1, the values of all bits of the 4-bit digital value stored in the third storage region 213 are set to be 0. Furthermore, when any bit of the 4-bit digital value (D3–D0) stored in the first storage region 211 has a value of 1, the values of all bits of the 4-bit digital value stored in the second storage region 212 are set to be 0.
FIG. 4A is a block diagram showing the storage section 200. FIG. 4B is a diagram illustrating a 12-bit digital value output from the storage section 200.
As shown in FIG. 4A and FIG. 4B, the 4-bit digital value (D3–D0) stored in the first storage region 211 is output as the highest 4 bits (D11–D8) of the 12-bit digital value (D11–D0) output from the storage section 200. The 4-bit digital value (D3–D0) stored in the second storage region 212 is output as the middle 4 bits (D7–D4) of the 12-bit digital value (D11–D0) output from the storage section 200. The 4-bit digital value (D3–D0) stored in the third storage region 213 is output as the lowest 4 bits (D3–D0) of the 12-bit digital value (D11–D0) output from the storage section 200.
As described above, the photodetector 1 according to the present embodiment always uses the charge-voltage conversion operation of the integration circuit 10 in the process of converting the photocurrent into a voltage and further into a digital value. That is, the integration circuit 10 is composed of an amplifier A10 having a high open-loop gain and a feedback capacitor. When the feedback capacitance value is denoted by Cf, and when the amount of electric charge accumulated in the feedback capacitor is denoted by Q, the relation “output voltage Vout=Q/Cf ” always holds for the case where the open-loop gain is sufficiently high in the amplifier A10. This feedback capacitor is fabricated by laminating insulators composed of oxide films or the like, and hence has no substantial temperature dependence. This ensures the relational expression Vout=Q/Cf under any temperature environment. As such, the final digital converted value has only a small temperature dependence by nature. This is an essential difference from the prior art where the logarithmic compression scheme is dominated by temperature characteristics.
Furthermore, in the prior art logarithmic compression scheme, the relation is nonlinear. This causes a problem, for example, where the dark current component is enhanced undesirably in the amplification. In contrast, in the present embodiment, the above-mentioned relation of the charge amplifier is always used. This ensures a linear relation in the final digital output value for the photocurrent. This prevents the problem where the dark current component is enhanced undesirably in the amplification.
The capacitance values of the capacitors of the integration circuit 10 may be those satisfying the following relational expressions in place of the above-mentioned Equations (14).

Cf1/Cf2=4  (15a)

Cf2/Cf3=4  (15b)

In this case, the digital value stored in the first storage region 211 is positioned higher than the digital value stored in the second storage region 212 by 2 bits. Furthermore, the digital value stored in the second storage region 212 is positioned higher than the digital value stored in the third storage region 213 by 2 bits. Thus, in the fourth stage following the third stage, an 8-bit digital value (D7–D0) is output from the storage section 200 corresponding to each of the photodiodes arranged in M rows by N columns on the basis of the 4-bit digital values (D3–D0), respectively, stored in the first storage region 211, the second storage region 212, and the third storage region 213 of the storage section 200.
FIG. 5A is a block diagram showing the storage section 200. FIG. 5B, FIG. 5C, and FIG. 5D are diagrams illustrating the 8-bit digital value output from the storage section 200.
That is, when any one of the highest two bits D3 and D2 of the 4-bit digital value (D3–D0) stored in the first storage region 211 has a value of 1, the 4-bit digital value (D3–D0) stored in the first storage region 211 is output as the highest 4 bits (D7–D4) of the 8-bit digital value (D7–D0) output from the storage section 200, as shown in FIG. 5B. The value 0 is output as the remaining bits of the 8-bit digital value (D7–D0) output from the storage section 200.
When both of the highest two bits D3 and D2 of the 4-bit digital value (D3–D0) stored in the first storage region 211 have a value of 0, and when any one of the highest two bits D3 and D2 of the 4-bit digital value (D3–D0) stored in the second storage region 212 has a value of 1, the 4-bit digital value (D3–D0) stored in the second storage region 212 is output as the middle 4bits (D5–D2) of the 8-bit digital value (D7–D0) output from the storage section 200, as shown in FIG. 5C. The value 0 is output as the remaining bits of the 8-bit digital value (D7–D0) output from the storage section 200.
When both of the highest two bits D3 and D2 of the 4-bit digital value (D3–D0) stored in the first storage region 211 have a value of 0, and when both of the highest two bits D3 and D2 of the 4-bit digital value (D3–D0) stored in the second storage region 212 have a value of 0, the 4-bit digital value (D3–D0) stored in the third storage region 213 is output as the lowest 4 bits (D3–D0) of the 8-bit digital value (D7–D0) output from the storage section 200, as shown in FIG. 5D. The value 0 is output as the remaining bits of the 8-bit digital value (D7–D0) output from the storage section 200.
As such, in comparison with the case where the capacitance values of the capacitors of the integration circuit 10 satisfy the above-mentioned Equations (14), in this case where Equations (15) are satisfied, the total number of bits of the digital value output from the photodetector 1 is smaller. However, advantageously, the number of effective bits is always 3 or more.
The invention is not limited to the above-mentioned embodiments, and maybe implemented in various modifications. In general, the capacitance value of the integration capacitance section of the integration circuit 10 may be switched into any one of Cf1–CfK, while the reference voltage in the A/D converter circuit 20 may be switched into any one of Vref,1–Vref,L. Furthermore, the storage section 200 may comprise K storage regions (each of K and L is an integer greater than or equal to 2). Furthermore, it is preferable that Cf1>Cf2> . . . >Cfk> . . . >CfK−1>CfK and that Vref,1>Vref,2> . . . >Vref,1> . . . >Vref,L−1>Vref,L. Furthermore, it is preferable that when the number of bits of the digital value output from the A/D converter circuit 20 is denoted by B, the following relational expressions hold.

2≦Cfk/Cfk+1≦2B  (16a)

Vref,k/Vref,k+1=2B  (16b)

(wherein, 1≦k<K, K≧2)

In the above-mentioned embodiments, the number B of bits of the digital value output from the A/D converter circuit 20 has been 4. However, the invention is not limited to this.
INDUSTRIAL APPLICABILITY
The invention is applicable to a photodetector comprising an A/D converter circuit for converting an analog value into a digital value.

## Claims

1. A photodetector, comprising:
a photodetection element for outputting electric charge in an amount corresponding to incident light intensity;
an integration circuit having:
an amplifier,
an integration capacitance section arranged in parallel to said amplifier between an input terminal and an output terminal, and
capacitance value switching means for switching the capacitance value of said integration capacitance section into any one of first through K-th capacitance values, where K indicates an integer greater than or equal to 2,
wherein integration circuit inputs electric charge output from said photodetection element through said input terminal, so as to accumulate said electric charge into said integration capacitance section having the capacitance value switched into by said capacitance value switching means, so as to output through said output terminal a voltage corresponding to the amount of the accumulated electric charge; and
an A/D converter circuit having
reference voltage switching means for switching a reference voltage used in A/D conversion, into any one of first through L-th reference voltages, where L indicates an integer greater than or equal to 2, wherein said reference voltage is applied to a plurality of capacitors connected in parallel to a line that is connected to an input terminal of a comparator,
wherein said A/D converter circuit which inputs the voltage output through said output terminal of said integration circuit, so as to A/D-convert said voltage on the basis of the reference voltage switched and set to be by said reference voltage switching means, so as to output a digital value corresponding to said voltage,

wherein when the k-th capacitance value among said first through K-th capacitance values is denoted by Cfk, the relational expression Cf1>Cf2> . . . >Cfk> . . . >CfK−1>CfK holds, while when the l-th reference voltage among said first through L-th reference voltages is denoted by Vref,l, the relational expression Vref,1>Vref,2> . . . >Vref,l> . . . >Vref,L−1>Vref,L holds, and wherein
said photodetector further comprises:
a storage section which is provided with first through K-th storage regions and storage region switching means for switching the region into any one of these regions, and which stores the digital value output from said A/D converter circuit, into any storage region switched into and selected from said first through K-th storage regions by said storage region switching means; and
controlling means which controls said capacitance value switching means of said integration circuit, said reference voltage switching means of said A/D converter circuit, and said storage region switching means of said storage section, so as to set the capacitance value of said integration capacitance section of said integration circuit to be the k-th capacitance value Cfk, set the reference voltage of said A/D converter circuit to be the l-th reference voltage Vref,l, and store the digital value output from said A/D converter circuit into the k-th storage region.

2. A photodetector according to claim 1, wherein a plurality of said photodetection elements are provided and arranged in two dimensions of M rows by N columns, where M≧2 and N≧2, while said integration circuit and said A/D converter circuit are arranged for each column of said photo detection elements arranged in two dimensions.