# Patent

## Title
Circuit for a transceiver output port of a local area networking device

## Abstract

A driving circuit for a transceiver output port of a local area networking device is provided, including first and second current sources coupled to the ground, first and second resistors coupled to the supply voltage with the resistances of the first and second resistors each being equal to half that of the equivalent resistance of the cable for the purpose of impedance matching, and third and fourth current sources coupled to the cable for providing additional currents while the first and second current sources are operating such that the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

## Background
This is a continuation-in-part of application Ser. No. 09/447,709, filed on Nov. 23, 1999, now U.S. Pat. No. 6,795,493, the subject matter of which is incorporated herein by reference.


BACKGROUND OF THE. INVENTION
1. Field of the Invention
The present invention relates to a local area networking device, especially to a driving circuit for a transceiver output port of local area networking device.
2. Description of the Related Art
The IEEE announced an IEEE 802.3 standard for Ethernet communication system. According to the IEEE 802.3 standard, the transceiver output port of each local area networking device is coupled to other local area networking devices via a unshielded twisted pair (UTP) cable. The data outputted from the transceiver output port is in the form of a differential output signal. In a 10 Mbps Ethernet communication system, for example, the peak-to-peak magnitude of the differential output signal VPP is from ±2.2V to ±2.8V as illustrated in FIG. 1. The differential output signal of the transceiver output port 21 is transmitted to a twisted-pair cable 22 via the transformer 23, as illustrated in FIG. 2.
FIG. 3 shows a conventional circuit of a transceiver output port for communicating with the UTP cable. The circuit includes two current sources: I1 and I2, which are serially-connected to the resistors R1 and R2 respectively. The other ends of the resistors R1 and R2 are connected to a common supply voltage VDD. A differential voltage (V+−V−) appears between the nodes x and y, which have voltages V+ and V− respectively. An equivalent load resistance RL appears between the nodes x and y.
The advantage for the circuit as illustrated in FIG. 3 is that the power consumption of the circuit can be decreased when the circuit is in idle state. When there is no signal output from the transceiver output port (i.e., the transceiver output port is idle), the current sources I1, and I2 can be off in order to save the power consumption. However, due to the inductance of the transformer coil, it takes a period of time for the transformer coil to be fully charged every time after the current sources I1, and I2 are on. The time required is determined by the inductance of the transformer coil and the resistance of the resistors R1 and R2. Consequently, in order to reduce the time delay as mentioned in the above, the current sources I1, and I2 cannot be off even in idle state in practical application. That is, the magnitudes of the output currents of the current sources I1 and I2 cannot be zero even the transceiver is in idle state.
Although the power consumption of the conventional circuit as shown in FIG. 3 can be decreased, the power consumption is still considerably large since the magnitudes of the output currents of the current sources I1, and I2 must be large enough to drive the transceiver output port to output the differential output signal. Moreover, the conventional circuit is not applicable under low supply voltage, which is explained as follows. Referring to FIG. 3, RL is the equivalent load resistance of the UTP cable, and R1 and R2 are the impedance match resistors for matching the impedance of the UTP cable. According to IEEE 802.3 standard, RL=100 Ω and R1=R2=50 Ω. In the following explanation, the resistance of the resistors R1 and R2 are both represented by R and the resistance of RL can be represented by 2R. Accordingly, the following equations can be derived:




  
    
      
        
          
            I
            1
          
          +
          
            I
            2
          
        
        =
        I
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          
            
              
                V
                DD
              
              -
              
                V
                -
              
            
            R
          
          +
          
            
              
                V
                +
              
              -
              
                V
                -
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          I
          1
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          
            
              
                V
                DD
              
              -
              
                V
                +
              
            
            R
          
          ⁢
          
            
              
                V
                +
              
              -
              
                V
                -
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          I
          2
        
      
    
    
      
        (
        3
        )
      
    
  




wherein I is a constant.

From the equations (2) and (3), equation (4) can be derived as follows:




  
    
      
        
          ⇒
          
            
              
                2
                ⁢
                
                  V
                  DD
                
              
              -
              
                (
                
                  
                    V
                    +
                  
                  +
                  
                    V
                    -
                  
                
                )
              
            
            R
          
        
        =
        
          
            I
            ⁢
            
              

            
            ⇒
            
              
                V
                +
              
              +
              
                V
                -
              
            
          
          =
          
            
              
                
                  2
                  ⁢
                  
                    V
                    DD
                  
                
                -
                RI
              
              ⁢
              
                

              
              ⇒
              
                V
                -
              
            
            =
            
              
                2
                ⁢
                
                  V
                  DD
                
              
              -
              RI
              -
              
                V
                +
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Based on equation (2) and equation (4), equation (5) is generated as follows:




  
    
      
        
          ⇒
          
            
              
                2
                ⁢
                
                  V
                  DD
                
              
              -
              
                2
                ⁢
                
                  (
                  
                    
                      2
                      ⁢
                      
                        V
                        DD
                      
                    
                    -
                    RI
                    -
                    
                      V
                      +
                    
                  
                  )
                
              
              +
              
                V
                +
              
              -
              
                (
                
                  
                    2
                    ⁢
                    
                      V
                      DD
                    
                  
                  -
                  RI
                  -
                  
                    V
                    +
                  
                
                )
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          
            
              I
              1
            
            ⁢
            
              

            
            ⇒
            
              
                
                  -
                  4
                
                ⁢
                
                  V
                  DD
                
              
              +
              
                4
                ⁢
                
                  V
                  +
                
              
              +
              
                3
                ⁢
                RI
              
            
          
          =
          
            2
            ⁢
            
              RI
              1
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Based on equations (1) and (5), equation (6) is obtained to represent V+as follows:




  
    
      
        
          ⇒
          
            V
            +
          
        
        =
        
          
            V
            DD
          
          -
          
            
              1
              4
            
            ⁢
            
              RI
              1
            
          
          -
          
            
              3
              4
            
            ⁢
            
              RI
              2
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




Furthermore, based on equations (4) and (6), equation (7) is obtained to represent V−as follows:




  
    
      
        
          ⇒
          
            V
            -
          
        
        =
        
          
            V
            DD
          
          -
          
            
              3
              4
            
            ⁢
            
              RI
              1
            
          
          -
          
            
              1
              4
            
            ⁢
            
              RI
              2
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




The differential voltage (V+−V−) can then be represented by equation (8) according to equations (6) and (7) as follows:




  
    
      
        
          ⇒
          
            
              V
              +
            
            -
            
              V
              -
            
          
        
        =
        
          
            R
            2
          
          ⁢
          
            (
            
              
                I
                1
              
              -
              
                I
                2
              
            
            )
          
        
      
    
    
      
        (
        8
        )
      
    
  




In a 10 Mbps Ethernet communication system, for example, the peak-to-peak magnitude of the differential output signal VPP is from ±2.2V to ±2.8V. If the differential output signal VPP is positive (V+>V−), an inequality (9) can be derived from the equation (8):




  
    
      
        
          
            2.2
            ≤
            
              
                V
                +
              
              -
              
                V
                -
              
            
          
          =
          
            
              
                
                  R
                  2
                
                ⁢
                
                  (
                  
                    
                      I
                      1
                    
                    -
                    
                      I
                      2
                    
                  
                  )
                
              
              ≤
              2.8
            
            ⇒
            
              

            
            ⁢
            
              
                
                  4.4
                  R
                
                +
                
                  I
                  2
                
              
              ≤
              
                I
                1
              
              ≤
              
                
                  5.6
                  R
                
                +
                
                  I
                  2
                
              
            
          
        
        ,
      
    
    
      
        (
        9
        )
      
    
  




and another inequality (10) can be derived from equation (7):





  
    
      
        
          V
          -
        
        =
        
          
            
              
                V
                DD
              
              -
              
                
                  3
                  4
                
                ⁢
                
                  RI
                  1
                
              
              -
              
                
                  1
                  4
                
                ⁢
                
                  RI
                  2
                
              
            
            ≥
            0
          
          ⇒
          
            
              V
              DD
            
            ≥
            
              
                R
                4
              
              ⁢
              
                (
                
                  
                    3
                    ⁢
                    
                      I
                      1
                    
                  
                  +
                  
                    I
                    2
                  
                
                )
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




Based on inequalities (9) and (10), the following inequality can be obtained:




  
    
      V
      DD
    
    ≥
    
      
        R
        4
      
      ⁢
      
        (
        
          
            3
            ×
            
              4.4
              R
            
          
          +
          
            3
            ⁢
            
              I
              2
            
          
          +
          
            I
            2
          
        
        )
      
    
  
  =
  
    3.3
    +
    
      RI
      2
    
  




As a result, the supply voltage VDD has a minimum value of 3.3V when I2=0. Therefore, the supply voltage VDD cannot be further reduced if the same amplitude of the differential output signal is to be kept. In other words, the conventional circuit for a transceiver output port at least has the following disadvantages:
1. The power consumption to drive the transceiver output port is still considerably too large.
2. Magnitude of the supply voltage VDD must also be large. For example, in a 10 Mbps Ethernet communication system, the supply voltage VDD must be larger than 3.3V to maintain the magnitude of the differential output signal to be within a predetermined range.
SUMMARY OF THE INVENTION
Therefore, it is one of the objectives of the present invention to provide a circuit for a transceiver output port of a local networking device, wherein the power consumption can be further decreased.
In addition, it is another one of the objectives of the present invention to provide a circuit for a transceiver output port of a local networking device, wherein the circuit can operate particularly at a supply voltage with the magnitude lower than the conventional supply voltage.
According to the objectives of the present invention, a driving circuit of a transceiver output port of a local area networking device is disclosed. The transceiver output port is coupled to a cable, such as an unshielded twisted pair (UTP), shielded twisted pair (STP), or the like, and the driving circuit is for outputting a differential output signal to the cable. The transceiver output port driving circuit comprises a first output node and a second output node for outputting the differential output signal; a first current source coupled to the first output node for providing a first current; a second current source coupled to the second output node for providing a second current; a first resistor coupled to the first output node; a second resistor coupled to the second output node; a third current source coupled between the first output node and a supply voltage source for providing a third current; and a fourth current source coupled between the second output node and the supply voltage source for providing a fourth current.
The resistance of the first resistor and the second resistor each are equal to 1⁄2 of the equivalent resistance of the cable for the purpose of impedance matching to the cable.
The third and fourth current sources are for providing additional currents while the first and second current sources are operating such that the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 (Prior Art) is a diagram showing the range of a differential output signal Vpp of the conventional transceiver output port of a 10BASE-T Ethernet communication system according to the IEEE 802.3 standard.
FIG. 2 (Prior Art) is a schematic diagram showing the transceiver output port of the local area networking device which is coupled to a UTP cable via a transformer.
FIG. 3 (Prior Art) is a diagram showing the conventional driving circuit of the transceiver output port for a local area networking device.
FIG. 4 is a diagram showing the driving circuit of a transceiver output port according to a first embodiment of the present invention.
FIG. 5 is a diagram showing one of the implementations of the driving circuit of the transceiver output port shown in FIG. 4 when the differential output signal is in a first state.
FIG. 6 is a diagram showing one of the implementations of the driving circuit of the transceiver output port shown in FIG. 4 when the differential output signal is in a second state.
FIG. 7 is a diagram showing another one of the implementations of the driving circuit of the transceiver output port shown in FIG. 4 when the differential output signal is in a first state.
FIG. 8 is a diagram showing another one of the implementations of the driving circuit of the transceiver output port shown in FIG. 4 when the differential output signal is in a second state.
FIG. 9 is a diagram showing a local area networking device with the driving circuit of a transceiver output port shown in FIG. 10.
FIG. 10 is a diagram showing the driving circuit of the transceiver output port according to a second embodiment of the present invention.
FIGS. 11–15 are diagrams showing various implementations of the current sources of the driving circuit of the transceiver output port according to the embodiments of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a diagram showing the driving circuit of the transceiver output port according to the first embodiment of the present invention. One of the differences between the circuit illustrated in FIG. 4 and the conventional circuit as illustrated in FIG. 3 is that two additional current sources I3 and I4 are employed in the circuit illustrated in FIG. 4. The circuit illustrated in FIG. 4 includes four current sources I1to I4. The first terminal and second terminal of the current source I1 are connected to ground and one terminal of a resistor R1, respectively. The other terminal of the resistor R1 is connected to a supply voltage source VDD. The first terminal and second terminal of the current source I2 are connected to ground and one terminal of a resistor R2, respectively. The other terminal of the resistor R2 is connected to the supply voltage source VDD. The resistors R1 and R2 are also impedance matching resistors for the purpose of impedance matching. The equivalent load resistance of the cable is represented by RL and is coupled between output nodes x and y, wherein the cable can be an unshielded twisted pair (UTP) cable, shielded twisted pair (STP) cable, or the like. In this embodiment, the cable is a UTP cable for illustration.
In this embodiment, the current sources I3 and I4 are connected to the resistors R1 and R2 in parallel respectively. In other words, the current source I3 is coupled between the current source I1 and the supply voltage source VDD while the current source I4 is coupled between the current source I2 and the supply voltage source VDD. One of the features of the present invention is that the current sources I3 and I4 are employed in order to provide additional current for the driving circuit so that the magnitude of the differential output signal outputted from the transceiver output port is determined not only by the current sources I1, and I2 but also by the current sources I3 and I4. In this way, the circuit can operate particularly with a supply voltage source VDD at a low level, even if the supply voltage VDD is lower than the minimum magnitude of the supply voltage required by the conventional driving circuit.
According to IEEE 802.3 standard, RL=100 Ω and R1=R2=50 Ω. In the following explanation, the resistance of the resistors R1 and R2 are both represented by R and the resistance of RL can be represented by 2R. Therefore, the resistors R1 and R2 can both be represented by R while RL can be represented by 2R. One of the advantages of the driving circuit shown in FIG. 4 can be explained more clearly, based on the following equations:

I1+I2=I12  (11)

I3+I4=I34  (12)

In this embodiment, the sum of the first current I1 and the second current I2, denoted by I12, is a constant while the sum of the third current I3 and the fourth current I4, denoted by I34, is also a constant. Applying Kirchhoff's voltage law at the output nodes y and x respectively, we have:




  
    
      
        
          
            
              
                V
                DD
              
              -
              
                V
                -
              
            
            R
          
          +
          
            I
            3
          
          +
          
            
              
                V
                +
              
              -
              
                V
                -
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          I
          1
        
      
    
    
      
        (
        13
        )
      
    
  
  
    
      
        
          
            
              
                V
                DD
              
              -
              
                V
                +
              
            
            R
          
          +
          
            I
            4
          
          +
          
            
              
                V
                +
              
              -
              
                V
                -
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          I
          2
        
      
    
    
      
        (
        14
        )
      
    
  




Summing up equations (13) and (14), equation (15) is obtained as follows:




  
    
      
        
          
            
              
                ⇒
                
                  
                    
                      2
                      ⁢
                      
                        V
                        DD
                      
                    
                    -
                    
                      (
                      
                        
                          V
                          +
                        
                        +
                        
                          V
                          -
                        
                      
                      )
                    
                  
                  R
                
              
              =
              
                
                  
                    I
                    1
                  
                  +
                  
                    I
                    2
                  
                  -
                  
                    I
                    3
                  
                  -
                  
                    I
                    4
                  
                
                =
                
                  
                    I
                    12
                  
                  -
                  
                    I
                    34
                  
                
              
            
          
        
        
          
            
              
                ⇒
                
                  
                    V
                    +
                  
                  +
                  
                    V
                    -
                  
                
              
              =
              
                
                  2
                  ⁢
                  
                    V
                    DD
                  
                
                -
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        12
                      
                      -
                      
                        I
                        34
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              
                ⇒
                
                  V
                  -
                
              
              =
              
                
                  2
                  ⁢
                  
                    V
                    DD
                  
                
                -
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        12
                      
                      -
                      
                        I
                        34
                      
                    
                    )
                  
                
                -
                
                  V
                  +
                
              
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




Based on equations (15) and (13), equation (16) is obtained as follows:




  
    
      
        
          ⇒
          
            
              
                2
                ⁢
                
                  
                
                ⁢
                
                  V
                  DD
                
              
              -
              
                2
                ⁡
                
                  [
                  
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        DD
                      
                    
                    -
                    
                      R
                      ⁡
                      
                        (
                        
                          
                            I
                            12
                          
                          -
                          
                            I
                            34
                          
                        
                        )
                      
                    
                    -
                    
                      V
                      +
                    
                  
                  ]
                
              
              +
              
                

              
              ⁢
              
                V
                +
              
              -
              
                [
                
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      DD
                    
                  
                  -
                  
                    R
                    ⁡
                    
                      (
                      
                        
                          I
                          12
                        
                        -
                        
                          I
                          34
                        
                      
                      )
                    
                  
                  -
                  
                    V
                    +
                  
                
                ]
              
            
            
              2
              ⁢
              R
            
          
        
        =
        
          
            
              
                I
                1
              
              -
              
                I
                3
              
            
            ⇒
            
              
                
                  -
                  4
                
                ⁢
                
                  V
                  DD
                
              
              +
              
                4
                ⁢
                
                  V
                  +
                
              
              +
              
                3
                ⁢
                
                  RI
                  12
                
              
              -
              
                3
                ⁢
                
                  RI
                  34
                
              
            
          
          =
          
            
              2
              ⁢
              
                RI
                1
              
            
            -
            
              2
              ⁢
              
                RI
                3
              
            
          
        
      
    
    
      
        (
        16
        )
      
    
  




V+ be expressed by equation (17) which is derived from equations (11), (12), and (16), as follows:




  
    
      
        
          ⇒
          
            V
            +
          
        
        =
        
          
            V
            DD
          
          -
          
            
              1
              4
            
            ⁢
            
              RI
              1
            
          
          -
          
            
              3
              4
            
            ⁢
            
              RI
              2
            
          
          +
          
            
              1
              4
            
            ⁢
            
              RI
              3
            
          
          +
          
            
              3
              4
            
            ⁢
            
              RI
              4
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




Moreover, V− can be represented by equation (18) which is derived from equations (17) and (15), as follows:




  
    
      
        
          ⇒
          
            V
            -
          
        
        =
        
          
            V
            DD
          
          -
          
            
              3
              4
            
            ⁢
            
              RI
              1
            
          
          -
          
            
              1
              4
            
            ⁢
            
              RI
              2
            
          
          +
          
            
              3
              4
            
            ⁢
            
              RI
              3
            
          
          +
          
            
              1
              4
            
            ⁢
            
              RI
              4
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




According to equations (17) and (18), equation (19) is obtained to represent V+−V− as follows:




  
    
      
        
          ⇒
          
            
              V
              +
            
            -
            
              V
              -
            
          
        
        =
        
          
            R
            2
          
          ⁡
          
            [
            
              
                (
                
                  
                    I
                    1
                  
                  -
                  
                    I
                    2
                  
                
                )
              
              -
              
                (
                
                  
                    I
                    3
                  
                  -
                  
                    I
                    4
                  
                
                )
              
            
            ]
          
        
      
    
    
      
        (
        19
        )
      
    
  




In a 10 Mbps Ethernet communication system, for example, the peak-to-peak magnitude of the differential output signal VPP is from ±2.2V to ±2.8V. When the differential signal is positive (V+>V−), according to equation (19), inequality (20) is obtained:




  
    
      
        
          2.2
          ≤
          
            
              V
              +
            
            -
            
              V
              -
            
          
        
        =
        
          
            
              
                R
                2
              
              ⁡
              
                [
                
                  
                    (
                    
                      
                        I
                        1
                      
                      -
                      
                        I
                        2
                      
                    
                    )
                  
                  -
                  
                    (
                    
                      
                        I
                        3
                      
                      -
                      
                        I
                        4
                      
                    
                    )
                  
                
                ]
              
            
            ≤
            2.8
          
          ⁢
          
            
          
          ⇒
          
            
          
          ⁢
          
            
              
                4.4
                R
              
              +
              
                I
                2
              
              -
              
                I
                4
              
            
            ≤
            
              
                I
                1
              
              -
              
                I
                3
              
            
            ≤
            
              
                5.6
                R
              
              +
              
                I
                2
              
              -
              
                I
                4
              
            
          
        
      
    
    
      
        (
        20
        )
      
    
  




According to equation (18), inequality (21) is generated:




  
    
      
        
          ⇒
          
            V
            -
          
        
        =
        
          
            
              
                V
                DD
              
              -
              
                
                  3
                  4
                
                ⁢
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        1
                      
                      -
                      
                        I
                        3
                      
                    
                    )
                  
                
              
              -
              
                
                  1
                  4
                
                ⁢
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        2
                      
                      -
                      
                        I
                        4
                      
                    
                    )
                  
                
              
            
            ≥
            0
          
          ⇒
          
            
              V
              DD
            
            ≥
            
              
                
                  3
                  4
                
                ⁢
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        1
                      
                      -
                      
                        I
                        3
                      
                    
                    )
                  
                
              
              +
              
                
                  1
                  4
                
                ⁢
                
                  R
                  ⁡
                  
                    (
                    
                      
                        I
                        2
                      
                      -
                      
                        I
                        4
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        21
        )
      
    
  




Based on inequalities (20) and (21), inequality (22) is obtained as follows:

VDD≧3.3+R(I2−I4)  (22)

According to inequality (22), if I2=0, and




  
    
      I
      4
    
    =
    
      3.3
      R
    
  
  ,




VDD can be an arbitrary positive value. However, in practical applications, the supply voltage VDD is maintained within a range which enables the current sources I1 to I4 to operate properly. According to practical experiments, the driving circuit of the transceiver output port can operate normally when the magnitude of the supply voltage VDD is larger than 1V, which is much lower than the supply voltage (3.3V) required by the conventional driving circuit. Therefore, the magnitude of the differential signal outputted from the driving circuit as illustrated in FIG. 4, which is one of the embodiments of the present invention, can be sustained within a predetermined range under the supply voltage with the magnitude which is lower than that of the conventional supply voltage.

In addition, the currents required to drive the transceiver output port to output the differential output signal are provided not only by the first and second current sources I1, and I2, but also by the third and fourth current sources I3 and I4. In other words, the third and fourth current sources I3 and I4 provide additional currents while the first and second current sources I1 and I2 are operating. In this manner, the power consumption of the driving circuit of the transceiver output port can be further reduced.
In the embodiments of the present invention, the magnitude of the differential output signal is determined not only by the first and second current sources I1 and I2, but also by the third and fourth current sources I3 and I4. In the above-described embodiment, the sum of the first current I1 and the second current I2 (I12) is a constant and the sum of the third current I3 and the fourth current I4 (I34) is also a constant. In addition, the magnitudes of I12 and I34 are substantially the same. Under these conditions, the magnitudes of the first current I1 and the fourth current I4 are substantially the same and the magnitudes of the second current I2 and the third current I3 are substantially the same.
Referring to FIG. 5, when the differential output signal is in a first state, i.e. V+>V−, the magnitudes of the second current I2 and the third current I3 are larger than those of first current I1 and the fourth current I4 respectively while the sum of the first current I1 and the second current I2 and the sum of the third current I3 and the fourth current I4 remain constant. Referring to FIG. 6, when the differential output signal is in a second state, i.e. V+<V−, the magnitudes of the second current I2 and the third current I3 are smaller than those of first current I1 and the fourth current I4 respectively while the sum of the first current I1 and the second current I2 and the sum of the third current I3 and the fourth current I4 remain constant.
There is another implementation to determine the magnitude of the differential output signal, wherein neither the sum of the first current I1 and the second current I2 (I12) nor the sum of the third current I3 and the fourth current I4 (I34) are constant. Referring to FIG. 7, when the differential output signal is in a first state, i.e. V+>V−, the magnitudes of the second current I2 and the third current I3 are larger than those of the first current I1 and the fourth current I4 respectively, and the magnitudes of the first current I1 and the fourth current I4 are preferably zero. Referring to FIG. 8, when the differential output signal is in a second state, i.e. V+<V−, the magnitudes of the second current I2 and the third current I3 are smaller than those of first current I1 and the fourth current I4 respectively and the magnitudes of second current I2 and the third current I3 are preferably zero. In this manner, the power consumption of the driving circuit of the transceiver output port can be further reduced.
It should be noted that the configuration of the impedance matching resistors, i.e. R1 and R2, for matching the impedance of the UTP, for example, the configuration shown in FIG. 4, is not the essential limitation of the present invention and can be implemented in different configurations with various network cabling schemes, for example, UTP or STP cable. Please refer to FIG. 9, which is a diagram showing the local area networking device with the driving circuit of the transceiver output port shown in FIG. 10. In this embodiment, the output nodes x and y of the driving circuit are coupled to first and second nodes of the transformer, n1 and n2, respectively, wherein the impedance matching resistors R1 and R2 are coupled serially between the output nodes x and y. The primary coil of the transformer is coupled to the output nodes of the driving circuit at the first and second nodes n1 and n2 respectively while the secondary coil of the transformer is coupled to the cable, (e.g. UTP cable), as shown in FIG. 9. The driving circuit of the transceiver output port with the implementation shown in FIG. 9 can be illustrated as FIG. 10, which is the second embodiment of the present invention. The difference between this embodiment and the first embodiment shown in FIG. 4 is the configuration of the impedance matching resistors R1 and R2. Besides, this embodiment and the first embodiment both have a common feature that the currents required to drive the transceiver output port to output the differential output signal are provided not only by the first and second current sources I1 and I2, but also by the third and fourth current sources I3 and I4. In other words, the third and fourth current sources I3 and I4 provide additional currents while the first and second current sources I1 and I2 are operating. In this manner, the magnitude of the differential output signal is determined not only by the first and second current sources I1 and I2, but also by the third and fourth current sources I3 and I4.
There are various ways to implement the current sources of the embodiments of the present invention. For example, each of the current sources can be implemented as a current mirror, as shown in FIG. 11, a voltage controlled current source, as shown in FIG. 12, or a current steering digital-to-analog converter (DAC), as shown in FIG. 13. Two of the embodiments of the current steering digital-to-analog converters (DAC) of FIG. 13 are shown in FIG. 14 and FIG. 15.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

## Claims

1. A driving circuit of a transceiver output port of a local area networking device, wherein the transceiver output port is coupled to a cable and the driving circuit is for outputting a differential output signal to the cable, the driving circuit comprising:
a first output node;
a second output node, wherein the first and second output nodes are for outputting the differential output signal;
a first current source coupled to the first output node for providing a first current;
a second current source coupled to the second output node for providing a second current;
a first resistor coupled to the first output node;
a second resistor coupled to the second output node;
a third current source coupled between the first output node and a supply voltage source for providing a third current; and
a fourth current source coupled between the second output node and the supply voltage source for providing a fourth current;
wherein the resistance of the first resistor and the resistance of the second resistor each are equal to 1⁄2 of the equivalent resistance of the cable for the purpose of impedance matching to the cable, and
wherein the third and fourth current sources are used for providing currents while the first and second current sources are operating such that the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

2. The driving circuit of claim 1, wherein the first resistor is coupled between the first output node and the supply voltage source and the second resistor is coupled between the second output node and the supply voltage source.

3. The driving circuit of claim 1, wherein the first and second resistors are coupled serially between the first and second output nodes, the transceiver output port is coupled to the cable via a transformer, and the transformer is coupled to the first and second output nodes.

4. The driving circuit of claim 1, wherein the resistance of each of the first and second resistors is substantially 50 Ohm.

5. The driving circuit of claim 1, wherein the magnitude of the fourth current is substantially the same with the magnitude of the first current, and the magnitude of the third current is substantially the same with the magnitude of the second current.

6. The driving circuit of claim 5, wherein when the differential output signal is in a first state, the magnitudes of the first and fourth currents are larger than the magnitudes of the second and third currents respectively; and when the differential output signal is in a second state, the magnitudes of the first and fourth currents are smaller than the magnitudes of the second and third currents.

7. The driving circuit of claim 6, wherein the sum of the first current and the second current is a constant and the sum of the third current and the fourth current is also the constant.

8. The driving circuit of claim 6, wherein when the differential output signal is in the first state, the magnitudes of the second current and the third current are both zero; and when the differential output signal is in the second state, the magnitudes of the first current and the fourth current are both zero.

9. The driving circuit of claim 1, wherein at least one of the first, the second, the third, and the fourth current sources is a current mirror.

10. The driving circuit of claim 1, wherein at least one of the first, the second, the third, and the fourth current sources is a voltage controlled current source.

11. The driving circuit of claim 1, wherein at least one of the first, the second, the third, and the fourth current sources is a digital-to-analog converter (DAC).

12. The driving circuit of claim 1, wherein the cable is an unshielded twisted pair (UTP) cable.

13. The driving circuit of claim 1, wherein the cable is a shielded twisted pair (STP) cable.

14. A driving circuit for a transceiver output port of a local networking device, the local networking device including first and second output nodes for communicating with a cable coupled between the first and second output nodes, for providing a differential output signal, the driving circuit comprising:
a supply voltage source for providing a supply voltage;
a first current source coupled between the first output node and ground;
a second current source coupled between the second output node and ground; wherein the resistor unit includes a first resistor coupled to the first output node and a second resistor coupled to the second output node;
a third current source coupled between the first output node and the supply voltage source;
a fourth current source coupled between the second output node and the supply voltage source; and
wherein the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

15. The driving circuit of claim 14, wherein the resistance of each of the first resistor and second resistors is one half of the impedance of the UTP.

16. The driving circuit of claim 14, wherein the cable is an unshielded twisted pair (UTP) cable.

17. The driving circuit of claim 14, wherein the cable is a shielded twisted pair (UTP) cable.

18. The driving circuit of claim 14, wherein most current provided by the third current source flows into the output node.

19. The driving circuit of claim 18, wherein most current provided by the fourth current source flows into the second output node.

20. A driving circuit for a transceiver output port of a local area networking device, the driving circuit comprising:
first and second output nodes for outputting a differential output signal to a network cable;
an equivalent output resistor that matches an impedance of the network cable, wherein the equivalent output resistor comprises a first resistor and a second resistor for matching the impedance of the network cable;
a supply voltage source for providing a supply voltage;
a first current source coupled between the first output node and ground;
a second current source coupled between the second output node and ground;
a third current source coupled between the first output node and the supply voltage source; and
a fourth current source coupled between the second output node and the supply voltage source;
wherein the third and fourth current sources are used for providing currents while the first and second current sources are operating.

21. The driving circuit of claim 20, wherein the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

22. The driving circuit of claim 20, wherein the local area networking device is compliant with the Ethernet standard and the network cable is an unshielded twisted pair cable.

23. The driving circuit of claim 20, wherein the local area networking device is compliant with the Ethernet standard and the network cable is a shielded twisted pair cable.

24. The driving circuit of claim 20, wherein most current provided by the third current source flows into the first output node.

25. The driving circuit of claim 24, wherein most current provided by the fourth current source flows into the second output node.