# Patent

## Title
Method and apparatus for reducing DC offsets in a communication system

## Abstract

Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. The stored DC offset is subtracted from the receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. In a third aspect, a feedback loop circuit reduces DC offset in a WLAN receiver channel. The feedback loop circuit includes a storage element that samples and stores receiver channel DC offset. The loop is opened, and the DC offset stored in the storage element is subtracted from the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of application Ser. No. 09/986,764, filed Nov. 9, 2001, and claims the benefit of U.S. Provisional Application No. 60/384,840, filed Jun. 4, 2002, which are both herein incorporated by reference in their entirety.
STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT
Not applicable.
REFERENCE TO MICROFICHE APPENDIX/SEQUENCE LISTING/TABLE/COMPUTER PROGRAM LISTING APPENDIX (SUBMITTED ON A COMPACT DISC AND AN INCORPORATION-BY-REFERENCE OF THE MATERIAL ON THE COMPACT DISC)
Not applicable.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency conversion of electromagnetic (EM) signals. More particularly, the present invention relates to reducing or eliminating DC offset voltages when down-converting a signal in a communication system.
2. Background Art
Electromagnetic (EM) information signals (baseband signals) include, but are not limited to, video baseband signals, voice baseband signals, computer baseband signals, etc. Baseband signals include analog baseband signals and digital baseband signals. It is often beneficial to propagate baseband signals at higher frequencies. Conventional up-conversion processes use modulation techniques to modulate higher frequency carrier signals with the baseband signals, to form modulated carrier signals.
Numerous problems exist in attempting to accurately receive or down-convert modulated carrier signals in communication systems. One such problem is when unwanted DC offset voltages exist in receiver channels. A DC offset voltage may enter a receiver channel by way of receiver channel down-conversion circuitry components, for example. This unwanted DC offset can enter a receiver channel, and cause the receiver channel to become saturated. For example, DC offset may saturate a receiver channel when it is amplified by gain amplifiers in the receiver channel, such that a voltage rail is reached or exceeded. Furthermore, any DC offset in the receiver channel has the effect of competing with the signal of interest, producing a statistical bias much like an interference. Hence, it is desirable to reduce or entirely eliminate unwanted DC offset voltages from receiver channels. Furthermore, the DC offset voltages must be removed without distorting the signal of interest.
BRIEF SUMMARY OF THE INVENTION
Methods and apparatuses for reducing DC offsets in a communication system are described. In a first embodiment, a first receiver channel signal is received from a first receiver channel node. The first receiver channel signal is integrated to generate an integrated signal. The integrated signal is summed with a second receiver channel signal at a second receiver channel node. The first receiver channel node is downstream from the second receiver channel node in the receiver channel.
In an embodiment, a feedback loop circuit is used to reduce DC offsets in the WLAN receiver channel, according to the above stated method. A receiver channel signal is coupled as a first input to a summing node in the receiver channel. An integrator has an input coupled to a second node of the receiver channel. An output of the integrator is coupled as a second input to the summing node.
The frequency response of the feedback loop circuit may be variable. In such an embodiment, the integrator has a frequency response that may be controlled to vary the frequency response of the feedback loop circuit. By varying the frequency response of the feedback loop circuit, the frequency response of the receiver channel may be varied. For example, the integrator frequency response may be varied to vary the frequency response of the receiver channel to a first frequency response, a second frequency response, and a third frequency response. Each of the three frequency responses have a corresponding lower 3 dB frequency. The first frequency response may have a relatively low lower 3 dB frequency. The second frequency response may have a relatively medium lower 3 dB frequency. The third frequency response may have a relatively greater lower 3 dB frequency.
In a second embodiment, a circuit provides gain control in a communication system, such as a WLAN receiver channel. A first automatic gain control (AGC) amplifier is coupled in a first portion of the receiver channel. A second AGC amplifier is coupled in a second portion of the receiver channel. The second AGC amplifier receives a first AGC signal. The first AGC amplifier receives a second AGC signal. The first and second AGC signals are related to each other. In an example embodiment, a multiplier receives the first AGC signal and outputs the second AGC signal.
In a third embodiment, DC offsets in a communication system are reduced. A DC offset voltage is received from a first node of the receiver channel. The voltage is stored. The stored voltage is de-coupled from the first node. At a second node in the receiver channel the stored voltage is subtracted from a receiver channel signal. The first node is downstream from the second node in the receiver channel.
In an embodiment, a circuit is used to reduce DC offsets in a WLAN receiver channel according to the above stated method. A summing node in the receiver channel receives as a first input a receiver channel signal. A storage element has a terminal coupled as a second input to the summing node. A switch is coupled between a second node of the receiver channel and the terminal of the storage element.
Methods and apparatuses for monitoring DC offset, and for providing control signals for varying the frequency response of the DC offset reducing circuits are provided. In an embodiment, a window comparator module determines whether a DC offset in each of an I channel input signal and a Q channel input signal is within an acceptable range. In an embodiment, a state machine generates the control signals that vary circuit frequency responses.
Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
FIG. 1A is a block diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.
FIG. 1B is a more detailed diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.
FIG. 1C illustrates a UFT module used in a universal frequency down-conversion (UFD) module according to an embodiment of the invention.
FIG. 1D illustrates a UFT module used in a universal frequency up-conversion (UFU) module according to an embodiment of the invention.
FIG. 2 is a block diagram of a universal frequency translation (UFT) module according to an alternative embodiment of the invention.
FIGS. 3A and 3G are example aliasing modules according to embodiments of the invention.
FIGS. 3B–3F are example waveforms used to describe the operation of the aliasing modules of FIGS. 3A and 3G.
FIG. 4 illustrates an energy transfer system with an optional energy transfer signal module according to an embodiment of the invention.
FIG. 5 illustrates an example aperture generator.
FIG. 6A illustrates an example aperture generator.
FIG. 6B illustrates an oscillator according to an embodiment of the present invention.
FIGS. 7A–B illustrate example aperture generators.
FIG. 8 illustrates an aliasing module with input and output impedance match according to an embodiment of the invention.
FIG. 9 illustrates an example energy transfer module with a switch module and a reactive storage module according to an embodiment of the invention.
FIG. 10 is a block diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.
FIG. 11 is a more detailed diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.
FIG. 12 is a block diagram of a universal frequency up-conversion (UFU) module according to an alternative embodiment of the invention.
FIGS. 13A–13I illustrate example waveforms used to describe the operation of the UFU module.
FIG. 14 illustrates a unified down-converting and filtering (UDF) module according to an embodiment of the invention.
FIG. 15 illustrates an exemplary I/Q modulation embodiment of a receiver according to the invention.
FIG. 16 shows an exemplary receiver channel in which embodiments of the present invention may be implemented.
FIG. 17 shows an receiver channel with automatic gain control, according to an embodiment of the present invention.
FIG. 18 shows a DC offset voltage present in an example model of an operational amplifier gain stage.
FIG. 19 shows an example feedback loop for reducing DC offset in a receiver channel, according to an embodiment of the present invention.
FIG. 20 shows an exemplary differentiator circuit that may be used to reduce or eliminate DC offset voltages in the receiver channel.
FIG. 21 shows an example embodiment for the integrator of FIG. 19, including an operational amplifier, a resistor, and a capacitor that are configured in an integrating amplifier configuration.
FIG. 22 shows an embodiment of the feedback loop of FIG. 19, where the first amplifier is divided into a first feedback amplifier and a second feedback amplifier, according to the present invention.
FIG. 23 shows an integrator, where the resistor is a variable resistor, according to an embodiment of the present invention.
FIG. 24A shows a frequency response of an ideal integrator similar to the integrator of FIG. 19.
FIG. 24B shows a plot of the frequency response of the feedback loop of FIG. 19.
FIG. 25A shows frequency responses for the integrator of FIG. 19 during three time periods, according to an embodiment of the present invention.
FIG. 25B shows frequency responses for the feedback loop of FIG. 19 that correspond to first, second, and third frequency responses shown in FIG. 25A.
FIG. 26 shows an example embodiment for the multiplier shown in FIG. 17.
FIGS. 27–29 and 33–34 show example flowcharts providing operational steps for performing embodiments of the present invention.
FIG. 30 shows a differential UFD module that may be used as a down-converter, according to an embodiment of the present invention.
FIGS. 31A and 31B show further detail of a receiver channel, according to an exemplary embodiment of the present invention.
FIGS. 32A (comprising FIGS. 32A-1, 32A-2, 32A-3, and 32A-4) and 32B (comprising FIGS. 32B-1, 32B-2, and 32B-3) show further detail of a receiver channel, according to an example differential receiver channel embodiment of the present invention.
FIGS. 35–37 show exemplary frequency responses for a receiver channel configured as shown in FIGS. 31A–B or 32A–B, when the frequency response is varied, according to embodiments of the present invention.
FIG. 38 shows example waveforms related to the operation of receiver channel as shown in FIGS. 32A–B in a WLAN environment, according to an embodiment of the present invention.
FIG. 39 shows an example timeline for receiving a WLAN DSSS frame, according to an embodiment of the present invention.
FIG. 40 shows an example 1/f noise characteristic curve.
FIG. 41 shows a high level view of a window comparator module, according to an embodiment of the present invention.
FIGS. 42 and 43 show more detailed examples of the window comparator module of FIG. 41, according to embodiments of the present invention.
FIG. 44 shows example waveforms related to the operation of a waveform comparator, according to an embodiment of the present invention.
FIG. 45 shows an example state machine module for generating and sequencing control signals of the present invention.
FIGS. 46 and 47 show example state diagrams that may be implemented by the state machine module of FIG. 45, according to embodiments of the present invention.
FIGS. 48, 49, 50A, and 50B show example flowcharts providing operational steps for performing embodiments of the present invention.
FIG. 51 shows an block diagram of an integrator that receives a control signal, according to an embodiment of the present invention.
FIG. 52 shows an open loop circuit for reducing DC offsets in a receiver channel, according to an example embodiment of the present invention.
FIG. 53 shows an alternative embodiment for the open loop circuit of FIG. 52, according to the present invention.
FIG. 54 shows a differential open loop circuit for reducing DC offsets, according to an embodiment of the present invention.
FIG. 55 shows an open loop circuit pair for reducing DC offset voltages that may be implemented in a receiver channel, according to an example embodiment of the present invention.
FIG. 56 shows a differential open loop circuit pair for reducing DC offset voltages that may be implemented in a receiver channel, according to an example embodiment of the present invention.
FIG. 57 illustrates a baseband portion of a receiver channel, according to an embodiment of the present invention.
FIG. 58 illustrates an example variable gain amplifier that may be used in the receiver channel portion shown in FIG. 58, according to an embodiment of the present invention.
FIG. 59 shows an example buffered configuration for the variable gain amplifier shown in FIG. 58, according to an embodiment of the present invention.
FIG. 60 illustrates the receiver channel portion shown in FIG. 57 with example gain values, according to an embodiment of the present invention.
FIG. 61 shows a detailed schematic view of the variable gain amplifier shown in FIG. 58, according to an embodiment of the present invention.
FIG. 62 shows the gain (in dB) of the variable gain amplifier of FIG. 61.
FIG. 63 shows an equation relating the gain of the variable gain amplifier of FIG. 62 to the square of the difference of a control voltage and a threshold voltage.
FIG. 64 illustrates a process for conditioning an applied gain control voltage to generate the control voltage input to the variable gain amplifier of FIG. 58, according to an embodiment of the present invention.
FIG. 65 illustrates an example square root function generator, according to an embodiment of the present invention.
FIG. 66 shows an example portion of the variable gain amplifier of FIG. 58, with one or more dummy switches for cancellation of charge injection, according to an embodiment of the present invention.
FIGS. 67A–67C show example flowcharts providing operational steps for performing embodiments of the present invention.
FIG. 68 shows an alternative embodiment for the open loop circuit of FIG. 52, according to the present invention.



The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number generally identifies the drawing in which the reference number first appears.
DETAILED DESCRIPTION OF THE INVENTION
Table of Contents


    1. Introduction
    2. Universal Frequency Translation
    
        2.1 Frequency Down-Conversion
        2.2 Optional Energy Transfer Signal Module
        2.3 Impedance Matching
        2.4 Frequency Up-Conversion
        2.5 Enhanced Signal Reception
        2.6 Unified Down-Conversion and Filtering
    
    
    3. Example Down-Converter Embodiments of the Invention
    
        3.1 Receiver Embodiments
        
            3.1.1 In-Phase/Quadrature-Phase (I/Q) Modulation Mode Receiver Embodiments
        
        
    
    
    4. DC Offset and Circuit Gain Considerations and Corrections
    
        4.1 Overview of DC Offset
        4.2 Exemplary Communications System Receiver Channel
        4.3 Embodiments for Cancellation of DC Offset by Closed Feedback Loop
        
            4.3.1 Variable Frequency Response Embodiments of the Present Invention
            4.3.2 Operation of the Closed Feedback Loop of the Present Invention
        
        
        4.4 Embodiments for Cancellation of DC Offset by Open Feedback Loop
        
            4.4.1 Nulling the Receiver Channel Input Signal
            
                4.4.1.1 Example Sampled Baseband Channel Embodiment
            
            
            4.4.2 Operation of the Open Feedback Loop of the Present Invention
        
        
        4.5 Embodiments for Automatic Gain Control
        
            4.5.1 Operation of Automatic Gain Control Embodiments of the Present Invention
        
        
        4.6 Exemplary Receiver Channel Embodiments of the Present Invention
        
            4.6.1 Using the Receiver Channel of the Present Invention to Receive a WLAN Signal Packet
            4.6.2 Embodiments for Generating Control Signals for a Receiver Channel According to the Present Invention
            
                4.6.2.1 Window Comparator for Monitoring DC Offset
                4.6.2.2 State Machine for Generating Control Signals
            
            
        
        
        5. Conclusion

1. Introduction

    
    


The present invention is directed to the down-conversion and up-conversion of an electromagnetic signal using a universal frequency translation (UFT) module, transforms for same, and applications thereof. The systems described herein each may include one or more receivers, transmitters, and/or transceivers. According to embodiments of the invention, at least some of these receivers, transmitters, and/or transceivers are implemented using universal frequency translation (UFT) modules. The UFT modules perform frequency translation operations. Embodiments of the present invention are described below.
Systems that transmit and receive EM signals using UFT modules exhibit multiple advantages. These advantages include, but are not limited to, lower power consumption, longer power source life, fewer parts, lower cost, less tuning, and more effective signal transmission and reception. These systems can receive and transmit signals across a broad frequency range. The structure and operation of embodiments of the UFT module, and various applications of the same are described in detail in the following sections, and in the referenced documents.
2. Universal Frequency Translation
The present invention is related to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.
FIG. 1A illustrates a universal frequency translation (UFT) module 102 according to embodiments of the invention. (The UFT module is also sometimes called a universal frequency translator, or a universal translator.)
As indicated by the example of FIG. 1A, some embodiments of the UFT module 102 include three ports (nodes), designated in FIG. 1A as Port 1, Port 2, and Port 3. Other UFT embodiments include other than three ports.
Generally, the UFT module 102 (perhaps in combination with other components) operates to generate an output signal from an input signal, where the frequency of the output signal differs from the frequency of the input signal. In other words, the UFT module 102 (and perhaps other components) operates to generate the output signal from the input signal by translating the frequency (and perhaps other characteristics) of the input signal to the frequency (and perhaps other characteristics) of the output signal.
An example embodiment of the UFT module 103 is generally illustrated in FIG. 1B. Generally, the UFT module 103 includes a switch 106 controlled by a control signal 108. The switch 106 is said to be a controlled switch.
As noted above, some UFT embodiments include other than three ports. For example, and without limitation, FIG. 2 illustrates an example UFT module 202. The example UFT module 202 includes a diode 204 having two ports, designated as Port 1 and Port 2/3. This embodiment does not include a third port, as indicated by the dotted line around the “Port 3” label. Other embodiments, as described herein, have more than three ports.
The UFT module is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.
For example, a UFT module 115 can be used in a universal frequency down-conversion (UFD) module 114, an example of which is shown in FIG. 1C. In this capacity, the UFT module 115 frequency down-converts an input signal to an output signal.
As another example, as shown in FIG. 1D, a UFT module 117 can be used in a universal frequency up-conversion (UFU) module 116. In this capacity, the UFT module 117 frequency up-converts an input signal to an output signal.
These and other applications of the UFT module are described below. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. In some applications, the UFT module is a required component. In other applications, the UFT module is an optional component.
2.1 Frequency Down-Conversion
The present invention is directed to systems and methods of universal frequency down-conversion, and applications of same.
In particular, the following discussion describes down-converting using a Universal Frequency Translation Module. The down-conversion of an EM signal by aliasing the EM signal at an aliasing rate is fully described in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals,” the full disclosure of which is incorporated herein by reference. A relevant portion of the above-mentioned patent is summarized below to describe down-converting an input signal to produce a down-converted signal that exists at a lower frequency or a baseband signal. The frequency translation aspects of the invention are further described in other documents referenced above, such as application Ser. No. 09/550,644, entitled “Method and System for Down-converting an Electromagnetic Signal, and Transforms for Same, and Aperture Relationships.”
FIG. 3A illustrates an aliasing module 300 for down-conversion using a universal frequency translation (UFT) module 302 which down-converts an EM input signal 304. In particular embodiments, aliasing module 300 includes a switch 308 and a capacitor 310 (or integrator). (In embodiments, the UFT module is considered to include the switch and integrator.) The electronic alignment of the circuit components is flexible. That is, in one implementation, the switch 308 is in series with input signal 304 and capacitor 310 is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation (see FIG. 3G), the capacitor 310 is in series with the input signal 304 and the switch 308 is shunted to ground (although it may be other than ground in configurations such as differential mode). Aliasing module 300 with UFT module 302 can be tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of the EM input signal 304.
In one implementation, aliasing module 300 down-converts the input signal 304 to an intermediate frequency (IF) signal. In another implementation, the aliasing module 300 down-converts the input signal 304 to a demodulated baseband signal. In yet another implementation, the input signal 304 is a frequency modulated (FM) signal, and the aliasing module 300 down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below.
In an embodiment, the control signal 306 includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal 304. In this embodiment, the control signal 306 is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal 304. Preferably, the frequency of control signal 306 is much less than the input signal 304.
A train of pulses 318 as shown in FIG. 3D controls the switch 308 to alias the input signal 304 with the control signal 306 to generate a down-converted output signal 312. More specifically, in an embodiment, switch 308 closes on a first edge of each pulse 320 of FIG. 3D and opens on a second edge of each pulse. When the switch 308 is closed, the input signal 304 is coupled to the capacitor 310, and charge is transferred from the input signal to the capacitor 310. The charge stored during successive pulses forms down-converted output signal 312.
Exemplary waveforms are shown in FIGS. 3B–3F.
FIG. 3B illustrates an analog amplitude modulated (AM) carrier signal 314 that is an example of input signal 304. For illustrative purposes, in FIG. 3C, an analog AM carrier signal portion 316 illustrates a portion of the analog AM carrier signal 314 on an expanded time scale. The analog AM carrier signal portion 316 illustrates the analog AM carrier signal 314 from time t0 to time t1.
FIG. 3D illustrates an exemplary aliasing signal 318 that is an example of control signal 306. Aliasing signal 318 is on approximately the same time scale as the analog AM carrier signal portion 316. In the example shown in FIG. 3D, the aliasing signal 318 includes a train of pulses 320 having negligible apertures that tend towards zero (the invention is not limited to this embodiment, as discussed below). The pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s). The pulses 320 repeat at an aliasing rate, or pulse repetition rate of aliasing signal 318. The aliasing rate is determined as described below.
As noted above, the train of pulses 320 (i.e., control signal 306) control the switch 308 to alias the analog AM carrier signal 316 (i.e., input signal 304) at the aliasing rate of the aliasing signal 318. Specifically, in this embodiment, the switch 308 closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch 308 is closed, input signal 304 is coupled to the capacitor 310, and charge is transferred from the input signal 304 to the capacitor 310. The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples 322 form down-converted signal portion 324 (FIG. 3E) that corresponds to the analog AM carrier signal portion 316 (FIG. 3C) and the train of pulses 320 (FIG. 3D). The charge stored during successive under-samples of AM carrier signal 314 form the down-converted signal 324 (FIG. 3E) that is an example of down-converted output signal 312 (FIG. 3A). In FIG. 3F, a demodulated baseband signal 326 represents the demodulated baseband signal 324 after filtering on a compressed time scale. As illustrated, down-converted signal 326 has substantially the same “amplitude envelope” as AM carrier signal 314. Therefore, FIGS. 3B–3F illustrate down-conversion of AM carrier signal 314.
The waveforms shown in FIGS. 3B–3F are discussed herein for illustrative purposes only, and are not limiting.
The aliasing rate of control signal 306 determines whether the input signal 304 is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or an AM signal. Generally, relationships between the input signal 304, the aliasing rate of the control signal 306, and the down-converted output signal 312 are illustrated below:

(Freq. of input signal 304)=n·(Freq. of control signal 306)±(Freq. of down-converted output signal 312)

For the examples contained herein, only the “+” condition will be discussed. Example values of n include, but are not limited to, n={0.5, 1, 2, 3, 4, . . . }.

When the aliasing rate of control signal 306 is off-set from the frequency of input signal 304, or off-set from a harmonic or sub-harmonic thereof, input signal 304 is down-converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of input signal 304. As a result, the under-samples form a lower frequency oscillating pattern. If the input signal 304 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHZ input signal to a 1 MHZ IF signal, the frequency of the control signal 306 would be calculated as follows:

(Freqinput−FreqIF)/n=Freqcontrol

(901 MHZ−1 MHZ)/n=900/n

For n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 would be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

Alternatively, when the aliasing rate of the control signal 306 is substantially equal to the frequency of the input signal 304, or substantially equal to a harmonic or sub-harmonic thereof, input signal 304 is directly down-converted to a demodulated baseband signal. This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of the input signal 304. As a result, the under-samples form a constant output baseband signal. If the input signal 304 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHZ input signal to a demodulated baseband signal (i.e., zero IF), the frequency of the control signal 306 would be calculated as follows:

(Freqinput−FreqIF)/n=Freqcontrol

(900 MHZ−0 MHZ)/n=900 MHZ/n

For n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F1 and an upper frequency F2 (that is, [(F1+F2)÷2]) of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F1 equal to 899 MHZ and F2 equal to 901 MHZ, to a PSK signal, the aliasing rate of the control signal 306 would be calculated as follows:

Frequency of the input=(F1+F2)÷2=(899 MHZ+901 MHZ)÷2 =900 MHZ

Frequency of the down-converted signal=0 (i.e., baseband)

(Freqinput−FreqIF)/n=Freqcontrol

(900 MHZ−0 MHZ)/n=900 MHZ/n

For n={0.5, 1, 2, 3, 4 . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F1 and the upper frequency F2.

As another example, to down-convert a FSK signal to an amplitude shift keying (ASK) signal (a subset of AM), either the lower frequency F1 or the upper frequency F2 of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F1 equal to 900 MHZ and F2 equal to 901 MHZ, to an ASK signal, the aliasing rate of the control signal 306 should be substantially equal to:

(900 MHZ−0 MHZ)/n=900 MHZ/n, or

(901 MHZ−0 MHZ)/n=901 MHZ/n.

For the former case of 900 MHZ/n, and for n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. For the latter case of 901 MHZ/n, and for n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.802 GHz, 901 MHZ, 450.5 MHZ, 300.333 MHZ, 225.25 MHZ, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F1 and the upper frequency F2 (i.e., 1 MHZ).

In an embodiment, the pulses of the control signal 306 have negligible apertures that tend towards zero. This makes the UFT module 302 a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired.
In another embodiment, the pulses of the control signal 306 have non-negligible apertures that tend away from zero. This makes the UFT module 302 a lower input impedance device. This allows the lower input impedance of the UFT module 302 to be substantially matched with a source impedance of the input signal 304. This also improves the energy transfer from the input signal 304 to the down-converted output signal 312, and hence the efficiency and signal to noise (s/n) ratio of UFT module 302.
Exemplary systems and methods for generating and optimizing the control signal 306 and for otherwise improving energy transfer and s/n ratio, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”
When the pulses of the control signal 306 have non-negligible apertures, the aliasing module 300 is referred to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal 306 is referred to as an energy transfer signal. Exemplary systems and methods for generating and optimizing the control signal 306 and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.
2.2 Optional Energy Transfer Signal Module
FIG. 4 illustrates an energy transfer system 401 that includes an optional energy transfer signal module 408, which can perform any of a variety of functions or combinations of functions including, but not limited to, generating the energy transfer signal 406.
In an embodiment, the optional energy transfer signal module 408 includes an aperture generator, an example of which is illustrated in FIG. 5 as an aperture generator 502. The aperture generator 502 generates non-negligible aperture pulses 508 from an input signal 412. The input signal 412 can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating the input signal 412 are described below.
The width or aperture of the pulses 508 is determined by delay through the branch 506 of the aperture generator 502. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator 502 decrease (i.e., the aperture generator is easier to implement). In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components utilized in the example aperture generator 502 do not require reaction times as fast as those that are required in an under-sampling system operating with the same EM input frequency.
The example logic and implementation shown in the aperture generator 502 are provided for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. The example aperture generator 502 includes an optional inverter 510, which is shown for polarity consistency with other examples provided herein.
An example implementation of the aperture generator 502 is illustrated in FIG. 6A. Additional examples of aperture generation logic are provided in FIGS. 7A and 7B. FIG. 7A illustrates a rising edge pulse generator 702, which generates pulses 508 on rising edges of the input signal 412. FIG. 7B illustrates a falling edge pulse generator 704, which generates pulses 508 on falling edges of the input signal 412. These circuits are provided for example only, and do not limit the invention.
In an embodiment, the input signal 412 is generated externally of the energy transfer signal module 408, as illustrated in FIG. 4. Alternatively, the input signal 412 is generated internally by the energy transfer signal module 408. The input signal 412 can be generated by an oscillator, as illustrated in FIG. 6B by an oscillator 602. The oscillator 602 can be internal to the energy transfer signal module 408 or external to the energy transfer signal module 408. The oscillator 602 can be external to the energy transfer system 401. The output of the oscillator 602 may be any periodic waveform.
The type of down-conversion performed by the energy transfer system 401 depends upon the aliasing rate of the energy transfer signal 406, which is determined by the frequency of the pulses 508. The frequency of the pulses 508 is determined by the frequency of the input signal 412.
The optional energy transfer signal module 408 can be implemented in hardware, software, firmware, or any combination thereof.
2.3 Impedance Matching
The example energy transfer module 300 described in reference to FIG. 3A, above, has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., UFT 302), and (2) the impedance of the storage module (e.g., capacitor 310), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies).
Starting with an aperture width of approximately 1⁄2 the period of the EM signal being down-converted as an example embodiment, this aperture width (e.g. the “closed time”) can be decreased (or increased). As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from 1⁄2 the period of the EM signal being down-converted, the impedance of the energy transfer module decreases.
One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module's characteristic input impedance is 300 ohms. An impedance matching circuit can be utilized to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below.
Referring to FIG. 8, a specific example embodiment using an RF signal as an input, assuming that the impedance 812 is a relatively low impedance of approximately 50 Ohms, for example, and the input impedance 816 is approximately 300 Ohms, an initial configuration for the input impedance match module 806 can include an inductor 906 and a capacitor 908, configured as shown in FIG. 9. The configuration of the inductor 906 and the capacitor 908 is a possible configuration when going from a low impedance to a high impedance. Inductor 906 and the capacitor 908 constitute an L match, the calculation of the values which is well known to those skilled in the relevant arts.
The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1 MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.
In an embodiment, the energy transfer module's characteristic output impedance is 2K ohms. An impedance matching circuit can be utilized to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.
When matching from a high impedance to a low impedance, a capacitor 914 and an inductor 916 can be configured as shown in FIG. 9. The capacitor 914 and the inductor 916 constitute an L match, the calculation of the component values being well known to those skilled in the relevant arts.
The configuration of the input impedance match module 806 and the output impedance match module 808 are considered in embodiments to be initial starting points for impedance matching, in accordance with embodiments of the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be enhanced in accordance with other various design criteria and considerations.
As other optional optimizing structures and/or components are utilized, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria.
2.4 Frequency Up-Conversion
The present invention is directed to systems and methods of frequency up-conversion, and applications of same.
An example frequency up-conversion system 1000 is illustrated in FIG. 10. The frequency up-conversion system 1000 is now described.
An input signal 1002 (designated as “Control Signal” in FIG. 10) is accepted by a switch module 1004. For purposes of example only, assume that the input signal 1002 is a FM input signal 1306, an example of which is shown in FIG. 13C. FM input signal 1306 may have been generated by modulating information signal 1302 onto oscillating signal 1304 (FIGS. 13A and 13B). It should be understood that the invention is not limited to this embodiment. The information signal 1302 can be analog, digital, or any combination thereof, and any modulation scheme can be used.
The output of switch module 1004 is a harmonically rich signal 1006, shown for example in FIG. 13D as a harmonically rich signal 1308. The harmonically rich signal 1308 has a continuous and periodic waveform.
FIG. 13E is an expanded view of two sections of harmonically rich signal 1308, section 1310 and section 1312. The harmonically rich signal 1308 may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment). For ease of discussion, the term “rectangular waveform” is used to refer to waveforms that are substantially rectangular. In a similar manner, the term “square wave” refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed.
Harmonically rich signal 1308 is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal 1308. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is referred to as the first harmonic. FIG. 13F and FIG. 13G show separately the sinusoidal components making up the first, third, and fifth harmonics of section 1310 and section 1312. (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal 1308 is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in FIG. 13H.
The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal 1006 and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal 1006. According to an embodiment of the invention, the input signal 1306 may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).
An optional filter 1008 filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal 1010, shown for example as a filtered output signal 1314 in FIG. 13I.
FIG. 11 illustrates an example universal frequency up-conversion (UFU) module 1101. The UFU module 1101 includes an example switch module 1004, which comprises a bias signal 1102, a resistor or impedance 1104, a universal frequency translator (UFT) 1150, and a ground 1108. The UFT 1150 includes a switch 1106. The input signal 1002 (designated as “Control Signal” in FIG. 11) controls the switch 1106 in the UFT 1150, and causes it to close and open. Harmonically rich signal 1006 is generated at a node 1105 located between the resistor or impedance 1104 and the switch 1106.
Also in FIG. 11, it can be seen that an example optional filter 1008 is comprised of a capacitor 1110 and an inductor 1112 shunted to a ground 1114. The filter is designed to filter out the undesired harmonics of harmonically rich signal 1006.
The invention is not limited to the UFU embodiment shown in FIG. 11. For example, in an alternate embodiment shown in FIG. 12, an unshaped input signal 1201 is routed to a pulse shaping module 1202. The pulse shaping module 1202 modifies the unshaped input signal 1201 to generate a (modified) input signal 1002 (designated as the “Control Signal” in FIG. 12). The input signal 1002 is routed to the switch module 1004, which operates in the manner described above. Also, the filter 1008 of FIG. 12 operates in the manner described above.
The purpose of the pulse shaping module 1202 is to define the pulse width of the input signal 1002. Recall that the input signal 1002 controls the opening and closing of the switch 1106 in switch module 1004. During such operation, the pulse width of the input signal 1002 establishes the pulse width of the harmonically rich signal 1006. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal 1006 are a function of at least the pulse width of the harmonically rich signal 1006. As such, the pulse width of the input signal 1002 contributes to setting the relative amplitudes of the harmonics of harmonically rich signal 1006.
Further details of up-conversion as described in this section are presented in U.S. Pat. No. 6,091,940, entitled “Method and System for Frequency Up-Conversion,” incorporated herein by reference in its entirety.
2.5 Enhanced Signal Reception
The present invention is directed to systems and methods of enhanced signal reception (ESR), and applications of same, which are described in the above-referenced U.S. Pat. No. 6,061,555, entitled “Method and System for Ensuring Reception of a Communications Signal,” incorporated herein by reference in its entirety.
2.6 Unified Down-Conversion and Filtering
The present invention is directed to systems and methods of unified down-conversion and filtering (UDF), and applications of same.
In particular, the present invention includes a unified down-converting and filtering (UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.
FIG. 14 is a conceptual block diagram of a UDF module 1402 according to an embodiment of the present invention. The UDF module 1402 performs at least frequency translation and frequency selectivity.
The effect achieved by the UDF module 1402 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, the UDF module 1402 effectively performs input filtering.
According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.
In embodiments of the invention, input signals 1404 received by the UDF module 1402 are at radio frequencies. The UDF module 1402 effectively operates to input filter these RF input signals 1404. Specifically, in these embodiments, the UDF module 1402 effectively performs input, channel select filtering of the RF input signal 1404. Accordingly, the invention achieves high selectivity at high frequencies.
The UDF module 1402 effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
Conceptually, the UDF module 1402 includes a frequency translator 1408. The frequency translator 1408 conceptually represents that portion of the UDF module 1402 that performs frequency translation (down conversion).
The UDF module 1402 also conceptually includes an apparent input filter 1406 (also sometimes called an input filtering emulator). Conceptually, the apparent input filter 1406 represents that portion of the UDF module 1402 that performs input filtering.
In practice, the input filtering operation performed by the UDF module 1402 is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concurrently with the frequency translation operation. This is a reason why the input filter 1406 is herein referred to as an “apparent” input filter 1406.
The UDF module 1402 of the present invention includes a number of advantages. For example, high selectivity at high frequencies is realizable using the UDF module 1402. This feature of the invention is evident by the high Q factors that arc attainable. For example, and without limitation, the UDF module 1402 can be designed with a filter center frequency fc on the order of 900 MHZ, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth).
It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable.
The invention exhibits additional advantages. For example, the filtering center frequency fc of the UDF module 1402 can be electrically adjusted, either statically or dynamically.
Also, the UDF module 1402 can be designed to amplify input signals.
Further, the UDF module 1402 can be implemented without large resistors, capacitors, or inductors. Also, the UDF module 1402 does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module 1402 is friendly to integrated circuit design techniques and processes.
The features and advantages exhibited by the UDF module 1402 are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, the UDF module 1402 performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa.
According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and/or samples/instances of the output signal.
More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.
As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (IF) or baseband.
Next, the input sample is held (that is, delayed).
Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.
Thus, according to a preferred embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, current samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.). By operating in this manner, the UDF module 1402 preferably performs input filtering and frequency down-conversion in a unified manner.
Further details of unified down-conversion and filtering as described in this section are presented in U.S. Pat. No. 6,049,706, entitled “Integrated Frequency Translation And Selectivity,” filed Oct. 21, 1998, and incorporated herein by reference in its entirety.
3. Example Down-Converter Embodiments of the Invention
As noted above, the UFT module of the present invention is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications and combinations in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications and combinations.
Such applications and combinations include, for example and without limitation, applications/combinations comprising and/or involving one or more of: (1) frequency translation; (2) frequency down-conversion; (3) frequency up-conversion; (4) receiving; (5) transmitting; (6) filtering; and/or (7) signal transmission and reception in environments containing potentially jamming signals. Example receiver, transmitter, and transceiver embodiments implemented using the UFT module of the present invention are set forth below.
3.1 Receiver Embodiments
In embodiments, a receiver according to the invention includes an aliasing module for down-conversion that uses a universal frequency translation (UFT) module to down-convert an EM input signal. For example, in embodiments, the receiver includes the aliasing module 300 described above, in reference to FIG. 3A or FIG. 3G. As described in more detail above, the aliasing module 300 may be used to down-convert an EM input signal to an intermediate frequency (IF) signal or a demodulated baseband signal.
In alternate embodiments, the receiver may include the energy transfer system 401, including energy transfer module 404, described above, in reference to FIG. 4. As described in more detail above, the energy transfer system 401 may be used to down-convert an EM signal to an intermediate frequency (IF) signal or a demodulated baseband signal. As also described above, the aliasing module 300 or the energy transfer system 401 may include an optional energy transfer signal module 408, which can perform any of a variety of functions or combinations of functions including, but not limited to, generating the energy transfer signal 406 of various aperture widths.
In further embodiments of the present invention, the receiver may include the impedance matching circuits and/or techniques described herein for enhancing the energy transfer system of the receiver.

    
    
        3.1.1 In-Phase/Quadrature-Phase (I/Q) Modulation Mode Receiver Embodiments
    
    


FIG. 15 illustrates an exemplary I/Q modulation mode embodiment of a receiver 1502, according to an embodiment of the present invention. This I/Q modulation mode embodiment is described herein for purposes of illustration, and not limitation. Alternate I/Q modulation mode embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein), as well as embodiments of other modulation modes, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
Receiver 1502 comprises an I/Q modulation mode receiver 1538, a first optional amplifier 1516, a first optional filter 1518, a second optional amplifier 1520, and a second optional filter 1522.
I/Q modulation mode receiver 1538 comprises an oscillator 1506, a first UFD module 1508, a second UFD module 1510, a first UFT module 1512, a second UFT module 1514, and a phase shifter 1524.
Oscillator 1506 provides an oscillating signal used by both first UFD module 1508 and second UFD module 1510 via the phase shifter 1524. Oscillator 1506 generates an “I” oscillating signal 1526.
“I” oscillating signal 1526 is input to first UFD module 1508. First UFD module 1508 comprises at least one UFT module 1512. First UFD module 1508 frequency down-converts and demodulates received signal 1504 to down-converted “I” signal 1530 according to “I” oscillating signal 1526.
Phase shifter 1524 receives “I” oscillating signal 1526, and outputs “Q” oscillating signal 1528, which is a replica of “I” oscillating signal 1526 shifted preferably by 90 degrees.
Second UFD module 1510 inputs “Q” oscillating signal 1528. Second UFD module 1510 comprises at least one UFT module 1514. Second UFD module 1510 frequency down-converts and demodulates received signal 1504 to down-converted “Q” signal 1532 according to “Q” oscillating signal 1528.
Down-converted “I” signal 1530 is optionally amplified by first optional amplifier 1516 and optionally filtered by first optional filter 1518, and a first information output signal 1534 is output.
Down-converted “Q” signal 1532 is optionally amplified by second optional amplifier 1520 and optionally filtered by second optional filter 1522, and a second information output signal 1536 is output.
In the embodiment depicted in FIG. 15, first information output signal 1534 and second information output signal 1536 comprise a down-converted baseband signal. In embodiments, first information output signal 1534 and second information output signal 1536 are individually received and processed by related system components. Alternatively, first information output signal 1534 and second information output signal 1536 are recombined into a single signal before being received and processed by related system components.
Alternate configurations for I/Q modulation mode receiver 1538 will be apparent to persons skilled in the relevant art(s) from the teachings herein. For instance, an alternate embodiment exists wherein phase shifter 1524 is coupled between received signal 1504 and UFD module 1510, instead of the configuration described above. This and other such I/Q modulation mode receiver embodiments will be apparent to persons skilled in the relevant art(s) based upon the teachings herein, and are within the scope of the present invention.
4. DC Offset and Circuit Gain Considerations and Corrections
Various embodiments related to the method(s) and structure(s) described herein are presented in this section (and its subsections). Exemplary WLAN receiver channel circuits are provided below, and circuits used to reduce or eliminate problems of DC offset in the WLAN receiver channel circuits are described. The embodiments of the present invention are applicable to any WLAN receiver circuit, such as IEEE 802.11 WLAN standard compliant receivers, including the IEEE 802.11a and 802.11b extensions, and to other communication standards.
These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments. Furthermore, the invention is applicable to additional communication system environments. For instance, the invention as disclosed herein is applicable to any type of communication system receiver, such as wireless personal area network (WPAN) receivers (including the Bluetooth standard), wireless metropolitan area network (WMAN) receivers, code division multiple access (CDMA) receivers (including wideband CDMA receivers), Global System for Mobile Communications (GSM) standard compatible receivers, and 3rd Generation (3G) network receivers.
4.1 Overview of DC Offset
Receivers, and other electronic circuits, may suffer from problems of DC offset and re-radiation. Generally, “DC offset” refers to a DC voltage level that is added to a signal of interest by related circuitry. The related circuitry creates the DC offset voltage through a variety of mechanisms that are well known. Some of these mechanisms are discussed in further detail below. “Re-radiation” is an undesired phenomenon where an unwanted signal is generated by circuitry, such as by an oscillator, and is transmitted by an antenna. The unwanted signal may then be received by circuitry, to interfere with the signal of interest. Such re-radiation may also lead to unwanted DC offset voltages.
If a DC offset voltage value is significant, it can degrade the quality of the signal of interest. In a receiver, for example, the signal of interest may be a down-converted signal. Unless reduced or eliminated, the added DC offset voltage level may undesirably change the voltage value of the down-converted signal. As a result, the desired voltage value of the down-converted signal may be difficult to ascertain by downstream processing.
For example, unwanted DC offset voltages created by receiver channel amplifiers may be inserted into the receiver channel signal path. FIG. 18 shows a DC offset voltage 1802 present in an example model of an operational amplifier gain stage. DC offset voltage 1802 is internally generated in operational amplifier 1804 and/or inherited from previous stages, and may be considered to be a voltage inserted between the amplifier inputs. Typically, DC offset voltage 1802 is a differential input voltage resulting from the mismatch of devices within operational amplifier 1804. Due to DC offset voltage 1802 (VIO), an unwanted output voltage offset (VOO) will appear in output voltage 1808. VIO is amplified by the circuit closed loop gain to create VOO. For example, in the configuration shown in FIG. 18, VOO may be calculated according to the following equation:




  
    V
    oo
  
  =
  
    
      (
      
        
          R2
          R1
        
        +
        1
      
      )
    
    ⁢
    
      V
      IO
    
  




This unwanted output DC offset voltage is input to subsequent amplifiers in the receiver channel and is accordingly amplified. If it becomes significant, it may cause outputs of the subsequent amplifiers to reach their voltage rails. In any event, DC offset voltages present in the receiver channel amplifiers may lead to an erroneous output signal.

Frequency down-converters may input DC offset voltages into the receiver channel. Embodiments of the UFT module may be used in many communications applications, including embodiments of the UFD module, to frequency down-convert signals in receivers. For some of these applications, the signal space may include waveforms with near DC content. Hence, it may be advantageous to limit the amount of artificial DC insertion or DC offsets contributed by the UFD module or its complimentary demodulation architecture.
There are at least three significant categories of offsets related to operation of the UFD module, which are listed as follows:

    
    
        1. Clock Excitation or Charge Injected
        2. Re-radiation Offsets
        3. Intermodulation Distortion

Each category possesses its own mechanisms. Further description of these categories of offsets in relation to the UFD module are provided in U.S. Ser. No. 09/526,041, titled “DC Offset, Re-radiation, and I/Q Solutions Using Universal Frequency Translation Technology,” filed Mar. 14, 2000, the disclosure of which is incorporated by reference herein in its entirety. These sources of DC offset may lead to erroneous receiver channel output signals.

    
    


Example methods and systems are provided in the sub-sections below for reducing or eliminating unwanted DC offsets. Such methods and systems may be used separately, or in any combination, to address offset issues.
4.2 Exemplary Communications System Receiver Channel
FIG. 16 shows an exemplary receiver channel 1600 in which embodiments of the present invention may be implemented. Receiver channel 1600 may be used to receive WLAN signals, or other signal types.
Receiver channel 1600 includes an optional low noise amplifier 1602, a second automatic gain control (AGC) amplifier 1604, a down-converter 1606, a first optional amplifier/filter section 1608, a first AGC amplifier 1610, a second optional amplifier/filter section 1612, and an antenna 1614. The present invention is also applicable to further receiver channel embodiments than receiver channel 1600, with fewer or more elements than shown in FIG. 16. Furthermore, the elements of receiver channel 1600 are not necessarily required to be arranged in the order shown in FIG. 16. For example, when first amplifier/filter section 1612 is present, some or all of it may be implemented upstream from down-converter 1606. Further embodiments for receiver channel 1600 will be apparent to persons skilled in the relevant art(s) from the teachings herein.
In an embodiment, more than one receiver channel 1600 may be required to receive a particular input signal. In the case of an I/Q modulated input signal, for example, a first receiver channel 1600 may be used to down-convert the I-channel, and a second receiver channel 1600 may be used to down-convert the Q-channel. Alternatively, for example, receiver channel 1600 may be divided into two channels (an I and Q channel) following LNA 1602 or second AGC amplifier 1604.
Antenna 1614 receives an input RF signal 1616. LNA 1602 (when present) receives and amplifies input RF signal 1616.
Second AGC amplifier 1604 receives input RF signal 1616 and receives a second AGC signal 1620. Second AGC amplifier 1604 amplifies input RF signal 1616 by an amount controlled by second AGC signal 1620, and outputs amplified RF signal 1618. Typically, second AGC signal 1620 is generated by downstream circuitry that detects the level of the receiver channel signal at a given location (not shown), and then determines by what amount the signal level of the receiver channel needs to be amplified, i.e., increased or decreased, to produce an acceptable receiver channel signal level.
Down-converter 1606 receives amplified RF signal 1618. Down-converter 1606 frequency down-converts, and optionally demodulates amplified input RF signal 1618 to a down-converted signal 1622. For example, in an embodiment, down-converter 1606 includes a conventional down-converter, such as a superheterodyne configuration. In another embodiment, down-converter 1606 may include a UFD module (e.g., UFD module 114 shown in FIG. 1C, aliasing module 300 shown in FIG. 3A) for frequency down-conversion/demodulation. Down-converted signal 1622 may be an intermediate frequency signal or baseband signal.
When present, first amplifier-filter section 1608 amplifies and/or filters down-converted signal 1622. First amplifier-filter section 1608 includes one or more amplifiers, such as operational amplifiers, and filter circuits for conditioning down-converted signal 1622. Any filter circuits that are present may have low-pass, high-pass, band-pass, and/or band-stop filter characteristics, for example. The filters may be active or passive filter types.
First AGC amplifier 1610 receives the optionally amplified/filtered down-converted signal 1622 and receives a first AGC signal 1626. First AGC amplifier 1610 amplifies down-converted signal 1622 by an amount controlled by first AGC signal 1626, and outputs amplified down-converted signal 1624. Similarly to second AGC signal 1620, first AGC signal 1626 is generated by circuitry that detects the level of the receiver channel signal at a given location (not shown), and then determines by what amount the signal level of the receiver channel needs to be amplified, i.e., increased or decreased, to produce an acceptable receiver channel signal level.
When present, second amplifier-filter section 1612 amplifies and/or filters amplified down-converted signal 1624. Second amplifier-filter section 1612 includes one or more amplifiers, such as operational amplifiers, and filter circuits for conditioning amplified down-converted signal 1624. Any filter circuits that are present may have low-pass, high-pass, band-pass, and/or band-stop filter characteristics, for example. The filters may be active or passive filter types. Second amplifier-filter section 1612 outputs an output signal 1628. Output signal 1628 may be an intermediate frequency signal that is passed on to further down-converters if needed, or a baseband signal that is passed to subsequent baseband signal processor circuitry.
Each element of receiver channel 1600 may introduce DC offsets, as described above, into the signal passing through receiver channel 1600. The following subsections further describe some of these sources of DC offset, and describe embodiments of the present invention for reducing or eliminating unwanted DC offset in a receiver channel.
4.3 Embodiments for Cancellation of DC Offset by Closed Feedback Loop
As described above, DC offset voltages may be introduced by elements of a receiver channel. DC offset voltages due to a down-converter, such as a UFD module, are briefly described in section 4.1 above, as are DC offset voltages due to an operational amplifier. These DC offset voltages can lead to erroneous receiver channel output signals. Hence, it would be desirable to reduce or eliminate DC offset voltages due to these and other elements of the receiver channel.
FIG. 20 shows an exemplary high-pass filter, or differentiator circuit 2000 that may be used to reduce or eliminate DC offset voltages in a receiver channel. Circuit 2000 is located in series in the receiver channel path. Circuit 2000 includes an amplifier 2002, a first resistor 2004, a capacitor 2006, and a second resistor 2008. Amplifier 2002 receives receiver channel signal 2010. First resistor 2004 and capacitor 2006 are coupled in series between the output of amplifier 2002 and the circuit output, output signal 2012. Second resistor 2008 is coupled between output signal 2012 and a ground or other potential.
A transfer function for circuit 2000 is provided below, wherein amplifier 2002 has a gain of G:




  
    Vo
    Vi
  
  =
  
    
      G
      ·
      
        R2
        
          R1
          +
          R2
        
      
    
    
      1
      +
      
        1
        
          
            (
            
              R1
              +
              R2
            
            )
          
          ⁢
          
            C
            ·
            s
          
        
      
    
  




Circuit 2000 is suitable for correcting an instantaneous DC offset, but may not be efficient in correcting for DC offset voltages over an infinite amount of time. For example, when there are perturbations in the DC offset voltage due to the temperature drift of circuit components, potentials may form across capacitor 2006 that do not easily dissipate. In addition, there is a single fixed time constant which does not simultaneously permit adequate frequency response and rapid DC offset acquisition time. Hence, circuit 2000 is not necessarily a desirable solution in all situations.

According to the present invention, DC offset voltages may be reduced or eliminated from a receiver channel using a closed feedback loop to subtract out the DC offset voltage. Embodiments for the closed feedback loop are provided as follows. These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
In embodiments, a DC offset voltage at a particular receiver channel node is measured. Using a feedback loop, the measured DC offset voltage is subtracted from the receiver channel. FIG. 19 shows an example feedback loop 1900 for reducing DC offset in a receiver channel, according to an embodiment of the present invention. Feedback loop 1900 includes an optional first amplifier 1902, an integrator 1904, a summing node 1906, and a second amplifier 1908. Feedback loop 1900 may be located at any point in a receiver channel, including at RF, IF, and baseband portions of the receiver channel. The direction of signal flow in the receiver channel is shown by arrow 1910.
Feedback loop 1900 provides a more robust approach to removing DC offset than circuit 2000, described above and shown in FIG. 20. Feedback loop 1900 continually measures the DC level of the receiver channel node, and continually corrects for it. Furthermore, feedback loop 1900 allows for rapid acquisition and removal of DC offset voltages, particularly when accompanied by time varying integration time constants as described herein.
The receiver channel DC offset is monitored at an output node 1914. Output node 1914 is located in the receiver channel signal path. Output node 1914 also provides an output signal 1916 of feedback loop 1900. Output signal 1916 is further coupled to subsequent components of the receiver channel.
Integrator 1904 has an input coupled to output node 1914 through first amplifier 1902. First amplifier 1902 is optional, and when first amplifier 1902 is not present, integrator 1904 may be directly coupled to output node 1914. Integrator 1904 integrates the signal received from output node 1914, which includes a DC offset voltage. Integrator 1904 outputs an integrator output signal 1918. Integrator 1904 may include passive and/or active circuit elements to provide the integration function.
Summing node 1906 is located in the receiver channel upstream from output node 1914. A receiver channel signal 1912 is coupled as a first input to summing node 1906. The output of integrator 1904, integrator output signal 1918, is coupled as a second input to summing node 1906.
Summing node 1906 may be merely a signal node in the receiver channel, or may include circuit components (active and/or passive) for combining integrator output signal 1918 and receiver channel signal 1912. Integrator output signal 1918 includes the DC offset to be removed from the receiver channel that is determined by feedback loop 1900. Integrator output signal 1918 may be inverted, such that summing node 1906 adds integrator output signal 1918 and receiver channel signal 1912, or may be non-inverted, so that summing node 1906 subtracts integrator output signal 1918 from receiver channel signal 1912. For example, integrator 1904 may be configured as an inverting integrator, or first amplifier 1902, when present, may be configured as an inverting amplifier, so that integrator output signal 1918 is inverted.
One or more amplifiers and other circuit components may be coupled between summing node 1906 and output node 1914. Feedback loop 1900 operates to eliminate or reduce DC offsets produced by these circuit components from the receiver channel, so that they do not substantially appear in output signal 1916. In the example embodiment shown in FIG. 19, second amplifier 1908 is coupled between summing node 1906 and output node 1914, and may provide a DC offset voltage at output node 1914.
FIG. 21 shows an example embodiment for integrator 1904, including an operational amplifier 2102, a resistor 2104, and a capacitor 2106 that are configured in an integrating amplifier configuration. Integrator input signal 1920 is coupled to a first terminal of resistor 2104. A second terminal of resistor 2104 is coupled to a first input 2112 of amplifier 2102. A second input 2114 of amplifier 2102 is coupled to ground or other reference potential. Capacitor 2106 is coupled between first input 2112 and output 2116 of amplifier 2102. Output 2116 is coupled to integrator output signal 1918.
Integrator 1904 shown in FIG. 21 performs the integration operation of:



  
    
      
        v
        o
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        -
        
          1
          CR
        
      
      ⁢
      
        
          ∫
          0
          t
        
        ⁢
        
          
            
              v
              i
            
            ⁡
            
              (
              t
              )
            
          
          ⁢
          
            d
            t
          
        
      
    
  




  
    
      
        V
        o
      
      
        V
        i
      
    
    =
    
      -
      
        1
        sCR
      
    
  



Hence, as indicated by the minus sign in the integrator transfer function, integrator 1904 is an inverting integrator. Note that a non-inverting integrator may alternatively be used for integrator 1904 provided that integrator output signal 1918 is subtracted at summing node 1906. Hence, an inverting integrator 1904 with positive summing node 1906 weighting or a non-inverting integrator 1904 with negative summing node 1906 weighting of integrator output signal 1918 may be used. The feedback loop averages the output signal and effectively subtracts that result at the loop input. FIG. 24A shows a frequency response 2400 of an ideal integrator similar in an embodiment to integrator 1904. The integrator frequency response 2400 of FIG. 24A has a time constant, CR, determined by the values of capacitor 2106 and resistor 2104.

The transfer function for feedback loop 1900 shown in FIG. 19 may be calculated as follows:

Vo(s)=(−KiGfbVo(s)+Vi(s))G

Vo(1+KiGfbG)=ViG





  
    
      V
      o
    
    
      V
      i
    
  
  =
  
    
      
        
          V
          i
        
        ⁢
        G
      
      
        1
        +
        
          
            K
            i
          
          ⁢
          
            G
            fb
          
          ⁢
          G
        
      
    
    =
    
      
        G
        
          1
          +
          
            
              
                G
                fb
              
              ⁢
              G
            
            RCs
          
        
      
      =
      
        Gs
        
          s
          +
          
            
              
                G
                fb
              
              ⁢
              G
            
            RC
          
        
      
    
  




where:

    
    
        Ki=1/RCs
        G=the gain of amplifier 1908,
        Gfb=the gain of amplifier 1902,
        Vo=output signal 1916, and
        Vi=receiver channel signal 1912.

In the above calculation, a negative sign at the summing node accounts for a non-inverting integrator for integrator 1904 in feedback loop 1900. An inverting integrator for integrator 1904 may also be accommodated by these calculations by adjusting the polarity of the summing node. FIG. 24B shows a plot of the transfer function of feedback loop 1900. Feedback loop 1900 is useful for reducing or eliminating DC offset voltages originating between summing node 1906 and output node 1914 in the receiver channel, in addition to DC offset voltages existing in receiver channel signal 1912. For example, a DC offset voltage of second amplifier 1908, VIOA, appearing at the input of second amplifier 1908, is reduced as follows:

Vo(s)=(−KiGfbVo(s)+Vi(s)+VIOA)G

Vo(1+KiGfbG)=VIOAG where Vi=0

    
    






  
    V
    o
  
  =
  
    
      
        V
        IOA
      
      ⁢
      G
    
    
      1
      +
      
        
          K
          i
        
        ⁢
        
          G
          fb
        
        ⁢
        G
      
    
  




For large loop gain Gfb 




  |
  
    V
    o
  
  |
  
    ≈
    
      
        V
        IOA
      
      
        
          K
          i
        
        ⁢
        
          G
          fb
        
      
    
  




In some situations, DC offset voltages appearing in the feedback path of feedback loop 1900 may not be reduced as effectively. For example, FIG. 22 shows an embodiment of feedback loop 1900, where first amplifier 1902 is divided into a first feedback amplifier 2202 and a second feedback amplifier 2204, according to an embodiment of the present invention. FIG. 22 shows a DC offset voltage of integrator 1904, VIOI, being added to the feedback signal path at the input of integrator 1904. VIOI affects output signal 1916 as follows:

Vo=−(KiGfb1Vo+KiVIOI)Gfb2·G+ViG

Where Gfb=Gfb1Gfb2 




  
    V
    o
  
  =
  
    
      
        
          GK
          i
        
        ⁢
        
          G
          fb2
        
        ⁢
        
          V
          IOI
        
      
      
        1
        +
        
          
            GK
            i
          
          ⁢
          
            G
            fb
          
        
      
    
    +
    
      
        V
        i
      
      ⁢
      
        G
        
          1
          +
          
            
              GK
              i
            
            ⁢
            
              G
              fb
            
          
        
      
    
  




For Vi=0 and large loop gain Gfb,




  |
  
    V
    o
  
  |
  
    ≈
    
      
        V
        IOI
      
      
        G
        fb1
      
    
  




Hence, in the embodiment of FIG. 22, the DC offset contribution of integrator 1904, VIOI, can be reduced by increasing the gain of first feedback amplifier 2202 (with a corresponding decrease in the gain of second feedback amplifier 2204 to keep from affecting the overall loop gain).

It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
As described above, the frequency response of the feedback loop may be varied. The varying of the frequency response of the feedback loop is described more fully in the next sub-section. Examples of the operation of closed feedback loop embodiments of the present invention are then described in the following sub-section.

    
    
        4.3.1 Variable Frequency Response Embodiments of the Present Invention
    
    


In some communication system receivers, it may be advantageous to incorporate a feedback loop 1900 with a variable frequency response. This may allow for DC offset voltages to be acquired according to different degrees of accuracy, while allowing the receiver channel to better pass signals of different signal formats. By varying the frequency response of feedback loop 1900, a frequency response of the receiver channel may be correspondingly varied. Furthermore, the ability to vary the frequency response of feedback loop 1900 allows for more rapid acquisition of DC offset voltages.
For example, a frequency response with a high-pass filter characteristic may be desirable to avoid problems of 1/f noise, also known as “flicker” noise. 1/f noise is produced by amplifiers, and gets its name from the fact that its characteristic curve has a slope close to 1/f. 1/f noise can cause subsequent amplifiers in the receiver channel to saturate, and can otherwise interfere with the receiver channel signal. Hence, it may be advantageous to have a high-pass filter characteristic in the receiver frequency response to reject 1/f noise. FIG. 40 shows an example 1/f noise characteristic curve 4002. The 1/f corner frequency for an amplifier can be around 10 KHz, or even greater, as shown in 1/f noise characteristic curve 4002. The noise level to the left of the 1/f corner frequency can be in the microvolts. Hence, a high-pass corner frequency of 100 KHz or 1 MHz may be desirable, for example.
However, a signal packet being received may have characteristics making a lower high-pass filter corner frequency more desirable. For example, in a 802.11 standard WLAN environment, a CCK modulated data portion of a WLAN signal frame may have this characteristic, as opposed to the WLAN signal frame preamble which may not. Furthermore, it may be advantageous to have a lower high-pass filter corner frequency in order to better capture and follow DC offset voltage changes due to thermal drift, etc. These considerations must be balanced with the problem of 1/f noise, as well as DC acquisition loop settling time.
In a WLAN (or other) communication system receiver, two or more separately located antennas may be used. During signal acquisition, the antennas may be sequentially switched on, so that each antenna is individually coupled to the same receiver channel. This antenna “diversity” switch allows for the antennas to be sequenced through, until it is determined which antenna allows for the strongest received signal. During this period of diversity antenna switching, a first frequency response for feedback loop 1900 may be desired, due to potentially a higher or lower tolerance in the acceptability of DC offset. Once an antenna has been selected, further frequency responses for feedback loop 1900 may be desired, due to changes in the tolerance for DC offset. Different frequency responses for feedback loop 1900 may be desirable when down-converting each of the preamble and data portions of a data frame, for example.
Hence, in an embodiment of the present invention, the frequency response of feedback loop 1900 is variable. The frequency response of feedback loop 1900 may be varied by changing component values in the feedback loop circuit, for example.
In an embodiment, integrator 1904 in feedback loop 1900 may be variable. The frequency response of integrator 1904 may be made variable by varying its respective components. Furthermore, integrator 1904 may receive one or more control signals to control the timing of frequency response changes for integrator 1904. FIG. 51 shows an block diagram of integrator 1904, according to an embodiment of the present invention. As shown in FIG. 51, integrator 1904 may receive a control signal 5102. One or more components of integrator 1904 may be varied in response to control signal 5102. In the embodiment of integrator 1904 shown in FIG. 21, the values of resistor 2104 and/or capacitor 2106 may be made variable in response to a control signal in order to vary the frequency response of integrator 1904. Other components may be made variable in other embodiments for integrator 1904.
FIG. 23 shows an integrator 1904, where resistor 2104 is a variable resistor, according to an embodiment of the present invention. Integrator 1904 as shown in FIG. 23 is configured substantially similarly to integrator 1904 shown in FIG. 21, with resistor 2104 divided into a first resistor 2302, a second resistor 2304, and a third resistor 2306, which are coupled in series. Furthermore, as shown in FIG. 23, integrator 1904 receives two control signals, first and second control signals 2312 and 2314.
A first switch 2308 is coupled across second resistor 2304, and receives a first control signal 2312. A second switch 2310 is coupled across third resistor 2306, and receives a second control signal 2314. By using first control signal 2312 and second control signal 2314 to switch second resistor 2304 and third resistor 2306 in and out of the circuit of integrator 1904, the frequency response of integrator 1904 may be varied. Any number of one or more resistors with corresponding switches in parallel may be used, according to the present invention, each providing for a corresponding change in the frequency response for integrator 1904. Furthermore, one or more continuously variable resistors may be used for resistor 2104 instead fixed resistors.
In an example embodiment, first and second control signals 2312 and 2314 are sequenced between three consecutive time periods according to the following table:










TABLE 1







first control
second control



signal 2312
signal 2314




















first time period
1
1



second time period
0
1



third time period
0
0










Due to the sequencing shown in Table 1, during the first time period, second and third resistors 2304 and 2306 are both shorted out of resistor 2104. First and second controls signals 2312 and 2314 (which are both high) open both of first and second switches 2308 and 2310, respectively. Only first resistor 2302 has an affect on the frequency response of integrator 1904. During the second time period, only third resistor 2306 is shorted out of resistor 2104 by second control signal 2314, which opens second switch 2310. The sum of the resistances of first resistor 2302 and second resistor 2304 affect the frequency response of integrator 1904. During the third time period, none of the three resistors are shorted out of resistor 2104 by the control signals/switches. The sum of the resistances of first resistor 2302, second resistor 2304, and third resistor 2306 affect the frequency response of integrator 1904.

Note that, although not shown in Table 1, in a fourth time period, first control signal 2312 could be equal to a logical high level, and second control signal 2314 could be equal to a logical low level.
Also, note that in an actual implementation, the switching action of first and second switches 2308 and 2310 may cause voltage spikes that appear in integrator output signal 1918. Any such voltage spikes could harm the operation of integrator 1904. Circuit components must be carefully selected and configured to keep the amplitude and duration of any voltage spikes below certain amounts to keep from disturbing the integrator too much.
In an embodiment, the values for first, second, and third resistors 2302,2304, and 2306 may be selected such that the value of first resistor 2302 has a lower resistance value than second resistor 2304, and second resistor 2304 has a lower resistance value than third resistor 2306. Other resistor value combinations are also applicable to the present invention.
FIG. 25A shows frequency responses of integrator 1904 during the three time periods of Table 1, according to an embodiment of the present invention. For the frequency response shown in FIG. 25A, R1 (first resistor 2302)<<R2 (second resistor 2304)<<R3 (third resistor 2306). FIG. 25A shows a first integrator frequency response 2502 corresponding to the first time period, a second integrator frequency response 2504 corresponding to the second time period, and a third integrator frequency response 2506 corresponding to the third time period.
FIG. 25B shows a plot of transfer functions for feedback loop 1900 that correspond to first, second, and third integrator frequency responses 2502,2504, and 2506. FIG. 25B shows a first loop frequency response 2510 that corresponds to third integrator frequency response 2506, a second loop frequency response 2512 that corresponds to second integrator frequency response 2504, and a third loop frequency response 2514 that corresponds to first integrator frequency response 2502. First loop frequency response 2510 has a relatively low high-pass corner frequency of approximately 10 KHz, for example. Second loop frequency response 2512 has a relatively medium high-pass corner frequency of approximately 100 KHz, for example. Third loop frequency response 2514 has a relatively higher high-pass corner frequency of approximately 1 MHz, for example.
First loop frequency response 2510, second loop frequency response 2512, and third loop frequency response 2514 may be respectively referred to as having a long or slow time constant, a medium time constant, and a short or fast time constant, elsewhere herein. These labels correspond to the RC time constants for their respective configurations of integrator 1904: (R1+R2+R3)C for loop frequency response 2510, (R1+R2)C for loop frequency response 2512, and (R1)C for loop frequency response 2514.
In an embodiment, one or more feedback loops similar to feedback loop 1900 are present in a receiver channel used to receive WLAN signals. In such an embodiment, different frequency responses for feedback loop 1900 may be used during different portions of the signal receiving process. For example, during the first time period, an initial pass at acquiring DC offset may be made. Accurately acquiring and following DC offset may not be as important during this time period (i.e., a short time constant may be acceptable). During the second time period, an optimal antenna diversity may be searched for and selected. DC offset concerns may become greater during this time period. Also during the first and second time periods, a signal preamble may be received. For example, the preamble may be coded with a Barker word. Hence, DC offset considerations may become more important during this time period (i.e., a medium time constant may be acceptable). During the third time period, a data portion of the data frame corresponding to the received preamble may be received. For example, the data portion may be modulated according to complementary code keying (CCK). The CCK modulated data signal may require the receiver to have a high-pass corner frequency closer to DC than does the Barker coded preamble (i.e., long time constant). Hence, the actions performed during these three time periods may each require a respective receiver frequency response tailored to their special conditions.
In an embodiment, these three time periods are sequenced through each time a new WLAN signal packet is received. In such an embodiment, for example, the first time period used to initially acquire DC offset may be within the range of 5 to 6 microseconds. The second time period used to complete the reception of the preamble may be within the range of 55 to 128 microseconds. The third time period may last as long as it is required to receive the entire data portion of the signal packet. In alternative embodiments, one or more of such time periods may be of any duration necessary to support portions of the signal receiving process.

    
    
        4.3.2 Operation of the Closed Feedback Loop of the Present Invention
    
    


FIG. 27 shows a flowchart 2700 providing operational steps for performing embodiments of the present invention. FIGS. 28, 29, 33, and 34 provide additional operational steps for flowchart 2700, according to embodiments of the present invention. The steps shown in FIGS. 27–29, 33, and 34 do not necessarily have to occur in the order shown, as will be apparent to persons skilled in the relevant art(s) based on the teachings herein. Other embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. These steps are described in detail below.
As shown in FIG. 27, flowchart 2700 begins with step 2702. In step 2702, a first receiver channel signal is received from a first receiver channel node. For example, the first receiver channel signal is output signal 1916, received from output node 1914, as shown in FIG. 19. In an embodiment, the first receiver channel signal is amplified before being received. For example, output signal 1916 may be amplified by first amplifier 1902, which outputs integrator input signal 1920.
In step 2704, the first receiver channel signal is integrated to generate an integrated signal. For example, integrator input signal 1920 is integrated. For example, integrator input signal 1920 may be integrated by integrator 1904 to generate integrator output signal 1918.
In step 2706, the integrated signal is summed with a second receiver channel signal at a second receiver channel node. For example, integrator output signal 1918 is summed with receiver channel signal 1912 at summing node 1906. The first receiver channel node is downstream from the second receiver channel node in the receiver channel. As shown in FIG. 19, output node 1914 is further downstream in the receiver channel than is summing node 1906.
In an embodiment, step 2704 includes the step where the integrated signal is generated as an integrated and inverted version of the first receiver channel signal. For example, integrator 1904 may be configured as an inverting integrator to produce an inverted integrator output signal 1918. In another example, when present, first amplifier 1902 may be configured in an inverting amplifying configuration to produce an inverted integrator input signal 1904, which is input to integrator 1904.
In an embodiment, step 2704 is performed by an integrator circuit. For example, the integrator circuit is integrator 1904. In an embodiment, the integrator circuit includes an amplifier, a capacitor, and a resistor. For example, integrator 1904 may include amplifier 2102, capacitor 2106, and resistor 2104, as shown in FIG. 21. The present invention is applicable to alternative embodiments for integrator 1904. In an embodiment, flowchart 2700 further includes the step where the amplifier, capacitor, and resistor are arranged in an integrating amplifier configuration. For example, amplifier 2102, capacitor 2106, and resistor 2104, may be arranged in an integrating amplifier configuration as shown in FIG. 21.
FIG. 28 shows flowchart 2700 with additional optional steps, according to an embodiment of the present invention. In FIG. 28, optional steps are indicated by dotted lines. In an embodiment, flowchart 2700 further includes step 2808. In step 2808, the frequency response of the integrator circuit is varied in response to a control signal. For example, as shown in FIG. 23, integrator 1904 is variable according to first control signal 2312 and second control signal 2314.
In an embodiment, flowchart 2700 further includes step 2810 shown in FIG. 28. In this embodiment, the integrator includes an amplifier, a capacitor, and a variable resistor. For example, resistor 2104 may be a variable resistor. In step 2810, the value of the variable resistor is varied to alter the frequency response of the integrator. For example, the value of resistor 2104 may be varied to alter the frequency response of integrator 1904.
In an embodiment, flowchart 2700 further includes step 2812 shown in FIG. 28. In step 2812, the variable resistor is configured. In an embodiment, the variable resistor includes at least one resistor and a switch corresponding to each of the at least one resistor. For example, resistor 2104 includes second resistor 2304 and first switch 2308. In an embodiment, step 2812 includes the step where the corresponding switch is coupled across each of the at least one resistor. For example, first switch 2308 is coupled across second resistor 2304.
In an embodiment, the variable resistor includes a first resistor, a first switch, a second resistor, a second switch, and a third resistor. For example, resistor 2104 includes first resistor 2302, first switch 2308, second resistor 2304, second switch 2310, and third resistor 2306. In an embodiment, step 2812 includes the following steps, which are shown in FIG. 29:
In step 2914, the first switch is coupled across the second resistor. For example, first switch 2308 is coupled across second resistor 2304.
In step 2916, the second resistor is coupled in series with the first resistor. For example, second resistor 2304 is coupled in series with first resistor 2302.
In step 2918, the second switch is coupled across the third resistor. For example, second switch 2308 is coupled across third resistor 2306.
In step 2920, the third resistor is coupled in series with the second resistor. For example, third resistor 2306 is coupled in series with second resistor 2304.
In embodiments, one or more control signals may be supplied to the switches in the variable resistor. The control signals control the opening and closing of the switches, which in turn alters the resistance of the variable resistor. This allows the frequency response of the integrator to be varied. For example, in an embodiment, step 2812 further includes the following steps, which are shown in FIG. 33:
In step 3322, a first control signal is received with the first switch. For example, first switch 2308 is received by first control signal 2312.
In step 3324, a second control signal is received with the second switch. For example, second switch 2310 is received by second control signal 2314.
In step 3326, the first and second control signals are sequenced according to Table 1, as shown above.
In an embodiment, step 3326 includes the step where the first and second control signals are sequenced according to the time periods shown in Table 1, where the first time period is in the range of 4 to 6 microseconds, and where the second time period is in the range of 55 to 128 microseconds.
FIG. 34 shows flowchart 2700 with additional optional steps, according to an embodiment of the present invention. In FIG. 34, optional steps are indicated by dotted lines. In step 3428, a preamble is received during the first and second time periods. For example, a 802.11 WLAN DSSS data frame preamble may be received by a receiver channel incorporating feedback loop 1900, such as receiver channels 1600, 1700, during the first and second time periods. The preamble may be short or long. The receiver may perform diversity switching during these time periods. The present invention is also applicable to receiving additional signal types and formats.
In step 3430, a data portion of a data frame corresponding to the preamble is received during the third time period. For example, a data portion of the 802.11 WLAN DSSS data frame may be received during the third time period.
In an embodiment, step 2706 includes the step where the second receiver channel signal is received, where the second receiver channel signal is a radio frequency signal. In an alternative embodiment, step 2706 includes the step where the second receiver channel signal is received, where the second receiver channel signal is an intermediate frequency signal. For example, receiver channel signal 1912 may be a radio frequency or intermediate frequency signal.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, in variable frequency response embodiments of the present invention, a plurality of frequency responses for feedback loop 1900 may be sequenced between as necessary to acquire DC offset and receive signal packets of any communication standard type. The invention is intended and adapted to include such alternate embodiments.
4.4 Embodiments for Cancellation of DC Offset by Open Feedback Loop
According to embodiments of the present invention, DC offset voltages may be reduced or eliminated (in a receiver channel, for example) using open loop DC offset voltage subtraction. In embodiments, a DC offset voltage at a particular receiver channel node may be captured and stored using a closed feedback loop. Once the DC offset voltage is captured, the feedback loop may be opened, and the captured DC offset voltage may be subtracted from the receiver channel.
The open feedback loop configuration has numerous advantages. These include a reduction in circuit components compared to other techniques, an ease in implementation, and a corresponding reduction in power consumption. Furthermore, the open feedback loop configuration can acquire the DC offset voltage rapidly. In embodiments, the DC offset voltage may be acquired in less than 2 μS.
FIG. 52 shows an open loop circuit 5200 for reducing DC offsets in a receiver channel, according to an embodiment of the present invention. Open loop circuit 5200 includes a summing node 5202, an AGC amplifier 5222, an output node 5204, a switch 5206, and a storage device 5208. Storage device 5208 is shown as a capacitor 5210 in FIG. 52, but may be an alternative type of storage device. The direction of signal flow in the receiver channel is shown by arrow 5218.
Generally, open loop circuit 5200 measures a DC offset voltage at an output node 5204 located in the receiver channel, and stores a charge proportional to this voltage in storage device 5208 when switch 5206 is closed. This charge or voltage is then de-coupled from output node 5204 by opening switch 5206, and subtracted from a receiver channel signal 5218 at summing node 5202. This has the effect of removing the DC offset voltage that would otherwise appear in output signal 5220. The DC offset voltage may be due, for example, to non-ideal circuit components prior to open loop circuit 5200 in the receiver channel and between summing node 5202 and output node 5204. Preferably, the receiver channel input to open loop circuit 5200 is squelched or nulled while the DC offset voltage is being acquired, such that receiver channel signal 5218 contains DC signal content to be subtracted out. The nulling of the receiver channel is described more fully in the following sub-section 4.4.1.
Summing node 5202 is located in the receiver channel. Receiver channel signal 5218 is coupled as an first input to summing node 5202.
The receiver channel DC offset is measured at output node 5204 and stored in storage device 5208 (this is further described in section 4.4.1). Output node 5204 is located in the receiver channel, downstream from summing node 5202.
Switch 5206 is coupled between output node 5204 and storage device 5208. Switch 5206 receives a control signal, DC voltage acquire signal 5216. When DC voltage acquire signal 5216 is high, switch 5206 is closed, and switch 5206 couples output node 5204 to storage device 5208. In this state, a voltage at output node 5204 is stored in storage device 5208. When DC voltage acquire signal 5216 is low, switch 5206 is opened, which isolates output node 5204 from storage device 5208. In this state, storage device 5208 holds the stored voltage.
Storage device 5208 outputs a stored DC voltage output signal 5214. Stored DC voltage output signal 5214 is coupled as a second input to summing node 5202. Summing node 5202 may be merely a signal node, or may include circuit components for combining stored DC voltage output signal 5214 and receiver channel signal 5218. Stored DC voltage output signal 5214 includes the DC offset voltage stored by storage device 5208, that is to be removed from the receiver channel. In an embodiment, summing node 5202 removes the stored DC offset voltage from the receiver channel by subtracting stored DC voltage output signal 5214 from receiver channel signal 5218. Alternatively, stored DC voltage output signal 5214 may be inverted, such that summing node 5202 adds stored DC voltage output signal 5214 to receiver channel signal 5218. Summing node 5202 outputs summed signal 5212.
AGC amplifier 5222 receives summed signal 5212, and amplifies summed signal 5212 according to AGC signal 5224. One or more amplifiers and other circuit components may be coupled between summing node 5202 and output node 5204. As described above, open loop circuit 5200 operates to eliminate or reduce DC offsets produced by these circuit components in the receiver channel. In the example embodiment shown in FIG. 52, AGC amplifier 5222 is coupled between summing node 5202 and output node 5204. Alternatively, non-AGC amplifiers may be coupled between summing node 5202 and output node 5204 in addition to, or instead of AGC amplifier 5222.
Output node 5204 is coupled to the output of AGC amplifier 5222. Output node 5204 provides the output signal, output signal 5220, of open loop circuit 5200. Output signal 5220 is further coupled to subsequent downstream components of the receiver channel.
Open loop circuit 5200 may be used, for example, to reduce DC offsets in receiver channel 1600, shown in FIG. 16. For example, open loop circuit 5200 may be configured around either one of, or both of first and second AGC amplifiers 1610 and 1604, and/or any other amplifiers in the receiver channel.
In an embodiment, the acquisition of the DC offset voltage that occurs according to DC voltage acquire signal 5216 is performed while AGC amplifier 5222 is operating at a maximum gain setting. The input DC offset voltage and DC offset voltage of AGC amplifier 5222 are stored by capacitor 5210. However, this value is reduced by the closed loop gain, Acl, of AGC amplifier 5222, as shown below:




  
    V
    corr
  
  =
  
    
      
        V
        os
      
      ⁢
      
        A
        cl
      
    
    =
    
      
        
          V
          os
        
        ⁢
        
          A
          ol
        
      
      
        (
        
          1
          +
          
            A
            ol
          
        
        )
      
    
  




where:

    
    
        Vcorr=actual DC offset voltage correction
        Vos=total DC voltage offset
        Aol=open loop gain of AGC amplifier 5222

This results in a DC offset correction error, Verr:

Verr=Vos−Vcorr=Vos−VosAcl=Vos(1−Acl)

The output DC offset voltage, Vout, is equal to the correction error multiplied by the open loop, dynamic gain, Aol—d:

    
    






  
    V
    out
  
  =
  
    
      
        A
        ol_d
      
      ⁢
      
        V
        os
      
    
    
      (
      
        1
        +
        
          A
          ol
        
      
      )
    
  




Hence, in a worst case, the output DC offset is about equal to the worst case DC offset of AGC amplifier 5222. The DC offset correction error, Verr, may be reduced by increasing the open loop gain.

The open loop output DC offset voltage, Voutl, for open loop circuit 5200 is shown as follows:




  
    
      V
      out1
    
    ⁢
    
      (
      
        A
        ol_d
      
      )
    
  
  =
  
    
      A
      ol_d
    
    ⁡
    
      [
      
        
          
            V
            osi
          
          ⁢
          
            e
            
              
                -
                tr
              
              τ
            
          
        
        +
        
          
            V
            os1
          
          ⁡
          
            [
            
              
                1
                +
                
                  
                    A
                    ol_s
                  
                  ⁢
                  
                    e
                    
                      
                        -
                        tr
                      
                      τ
                    
                  
                
              
              
                1
                +
                
                  A
                  ol_s
                
              
            
            ]
          
        
      
      ]
    
  




where:

    
    
        Vosi=input DC offset voltage
        Vosl=DC voltage offset contribution of AGC amplifier 5222
        Aol—s=static open loop gain of AGC amplifier 5222
        τ=time constant related to capacitor 5210

This equation provides an illustration of a problem in subtracting a DC offset in the presence of varying gain. Note that further configurations may include a feedback amplifier in open loop circuit 5200, and/or two or more cascaded stages similar to open loop circuit 5200, for example. In such configurations, the problem with subtracting a DC offset is typically exacerbated, and the corresponding open loop DC offset voltage equation is more complicated. Such open loop DC offset voltage configurations and corresponding equations would be know to persons skilled in the relevant art(s) from the teachings herein.

    
    


FIG. 53 shows an alternative embodiment for open loop circuit 5200, according to the present invention. Open loop circuit 5200 in FIG. 53 includes a second amplifier 5302 and a second switch 5304 coupled between output node 5204 and storage device 5208. When DC voltage acquire signal 5216 is high, first switch 5206 and second switch 5304 are closed, and output node 5204 is coupled to storage device 5208 through second amplifier 5302. In this state, a voltage at output node 5204 is amplified by second amplifier 5302, and stored in storage device 5208. When DC voltage acquire signal 5216 is low, first switch 5206 and second switch 5304 are opened, which isolates output node 5204 from storage device 5208, and isolates second amplifier 5302. In this state, storage device 5208 holds the amplified/stored voltage. First switch 5206 is optional in such a configuration.
As stated above, stored DC voltage output signal 5214 may be inverted by an amplifier located prior to or following storage device 5208 in open loop circuit 5200. When amplifier 5302 is present, it may be configured in an inverting amplifier configuration to invert the DC offset voltage stored in storage device 5208, so that stored DC voltage output signal 5214 may be added to receiver channel signal 5218 to remove the DC offset.
FIG. 54 shows a differential open loop circuit 5400, according to an embodiment of the present invention. Differential open loop circuit 5400 is a differential version of open loop circuit 5200, which is shown as single-ended for exemplary purposes. Differential open loop circuit 5400 includes a differential AGC amplifier 5402, a first switch 5404, a second switch 5406, a first capacitor 5408, a second capacitor 5410, a first resistor 5412, and a second resistor 5414.
Generally, differential open loop circuit 5400 operates similarly to open loop circuit 5200 as described above. A DC voltage acquire signal 5418 is received by first and second switches 5404 and 5406. In a first mode, DC voltage acquire signal 5418 is high, closing first and second switches 5404 and 5406. In this mode, differential open loop circuit 5400 receives DC voltages at output nodes 5424 and 5426 located in the receiver channel, and stores these voltage in first and second capacitors 5408 and 5410, respectively.
In a second mode, while switches 5404 and 5406 are open, the voltages stored in first and second capacitors 5408 and 5410 during the first mode are subtracted from differential receiver channel signal 5420 at first and second summing nodes 5428 and 5430. This has the effect of reducing or removing DC offset voltages due to components prior to differential open loop circuit 5400 in the receiver channel, and due to components between first and second summing nodes 5428 and 5430 and output nodes 5424 and 5426, that would otherwise appear in a differential output signal 5422.
Differential AGC amplifier 5402 is shown coupled between first and second summing nodes 5428 and 5430, and output nodes 5424 and 5426. Differential AGC amplifier 5402 receives first and second summed signals 5432 and 5434, and amplifies first and second summed signals 5432 and 5434 according to AGC signal 5416. Output nodes 5424 and 5426 are coupled to the output of differential AGC amplifier 5402. Output nodes 5424 and 5426 provide the output signal, differential output signal 5422, of open loop circuit 5400. Output signal 5220 is further coupled to subsequent downstream components of the receiver channel.
One or more amplifiers and other circuit components may be coupled between first and second summing node 5428 and 5430 and output nodes 5424 and 5426 other than, or in addition to differential AGC amplifier 5402.
Note that AGC amplifiers coupled between the summing and output nodes may undergo changes in gain due to changes in the level of the AGC signals. The level of a DC offset voltage passing through an AGC amplifier will be amplified according to the new gain setting, and thus will be changed. If a gain change in the AGC amplifier occurs after the DC offset voltage has been stored, the stored DC offset voltage may become out-dated and incorrect. Accordingly, the gain function(s) of the loop can be dynamically adjusted to accommodate AGC adjustments.
In some applications, it is desireable to remove DC offset of the baseband signal prior to the first AGC function. Accordingly, FIG. 68 shows a block diagram of an alternative implementation 6800 of the block diagram illustrated in FIG. 52. In FIG. 68, the AGC amplifier 5222 is implemented outside of the DC offset correction loop. Implementation 6800 allows for maximization of fixed gain with DC offset removed, prior to a baseband AGC function. This allows the system to obtain the largest reasonable fixed gain in the process, prior to the AGC function, such that other receiver figures of merit are not sacrificed. Maximization of this pre-AGC gain is subject to radio design criteria, such as, for example, and without limitation, intercept point and noise figure. Note that one or more fixed gain amplifiers may be inserted between summing node 5202 and output node 5204 in the implementation of 6800 to provide additional fixed gain.
Generally, maximization of AGC is desireable, provided that overall dynamic range (e.g., noise figure and intercept point) is preserved in the process. Hence, RF AGC, under certain scenarios dominated by DC offset control, should be adjusted at a greater rate than the corresponding baseband AGC.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
As described above, preferably, the receiver channel is nulled while the DC offset voltage is being acquired or measured, such that receiver channel signal 5218 mainly contains the DC signal content to be subtracted out. The nulling of the receiver channel is described more fully in the next sub-section. Examples of the operation of open feedback loop embodiments of the present invention are then described in the following sub-section.

    
    
        4.4.1 Nulling the Receiver Channel Input Signal
    
    


This subsection describes the nulling of the receiver channel input signal while a DC offset voltage is being stored. Although the nulling of the input signal may be discussed in reference to one or the other of open loop circuits 5200 and 5400, the following description is applicable to both configurations.
As described above, referring to FIG. 52, the control signal for switch 5206, DC voltage acquire signal 5216, controls whether or not open loop circuit 5200 is in a DC offset voltage storing mode. When DC voltage acquire signal 5216 is high, open loop circuit 5200 is in a DC offset storing mode. In this mode, switch 5206 is closed, closing the feedback loop, and a voltage at output node 5204 is stored in storage device 5208. During this period, receiver channel signal 5218 should be nulled so that primarily, a DC offset voltage is received at output node 5204. In this manner, the DC offset voltage can be more accurately stored, without interference from extraneous receiver channel signals.
When DC voltage acquire signal 5216 is low, open loop circuit 5200 is in a non-DC offset storing mode. Switch 5206 is opened, opening the feedback loop of open loop circuit 5200. In this mode, the DC offset voltage that was acquired and stored in storage device 5208 is applied to summing node 5202, and subtracted out from the receiver channel. During this period, receiver channel signal 5218 no longer needs to be nulled, and instead may provide an RF/IF/baseband input signal to open loop circuit 5200. In this manner, the acquired DC offset is removed from the receiver channel.
To “null” receiver channel signal 5218, an input RF/IF/baseband signal in an upstream portion of the receiver channel is cut off. The receiver channel is thus caused to be substantially equal to ground or other reference voltage, with only DC offset voltage(s) due to receiver channel components being present. In other words, any signal of interest is removed, while the DC characteristics of the receiver channel are retained so that the DC offset may be removed (including thermal drift of DC offset). In this manner, open loop circuit 5200 only stores a DC offset voltage.
For example, an antenna (such as antenna 1614) for the receiver channel may be switched off or otherwise disconnected or “nulled” so that no RF signal is received by the receiver channel from the antenna. Alternatively, any receiver channel signal prior to open loop circuit 5200 may be coupled to ground or reference voltage. Note that the further upstream in the receiver channel that nulling takes place, the greater the number of receiver channel circuit components that can have their DC offset voltages nulled.
In another alternative configuration for nulling receiver channel signal 5218, a gain setting of an AGC amplifier that precedes summing node 5202 in the receiver channel may be reduced during the time period that the DC offset voltage is being stored. For example, second AGC signal 1620 may provide a signal that causes second AGC amplifier 1604 to not pass a signal. The gain setting for second AGC amplifier 1604 may be reduced to be substantially equal to zero during the time period. In this manner, second AGC amplifier 1604 does not pass a signal, and only the DC offset voltage of second AGC amplifier 1604 and any intervening components reaches open loop circuit 5200.
Another way of nulling receiver channel signal 5218 is to turn off a frequency down-converter that precedes open loop circuit 5200 in the receiver channel. For example, a control signal coupled to the down-converter module may be set to inactive during the time period.
In an example embodiment of a receiver channel, a universal frequency down-conversion (UFD) module may be located in the receiver channel preceding receiver channel signal 5218 to perform frequency down-conversion. The UFD module may be located in down-converter 1606, for example, shown in FIG. 16. The UFD module may include a switch and a storage element, with the switch receiving a control signal. The control signal may be set to an inactive state, causing the UFD module to output only a DC offset voltage of the UFD module, nulling receiver channel 5218. For example, FIG. 30 shows a differential UFD module 3000 that may precede open loop circuit 5200 in a receiver channel. Differential UFD module 3000 includes a switch 3002, and a first and second capacitor 3004 and 3006. Switch 3002 receives a control signal 3012. Control signal 3012 may be set to an inactive state, causing switch 3002 to close and short out differential down-converted signal 3010. Hence, only a DC offset voltage of UFD module 3000 will be substantially present in differential down-converted signal 3010.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments. For example, for illustrative purposes, an example receiver channel portion that incorporates embodiments of the present invention is described in detail in the following subsection.

    
    
        
        
            4.4.1.1 Example Sampled Baseband Channel Embodiment
        
        
    
    


FIG. 57 illustrates a baseband portion of a receiver channel 5700 that includes embodiments of the present invention. Receiver channel portion 5700 includes first and second variable gain differential amplifiers 5702 and 5704 (although receiver channel portion 5700 is shown in a single-ended form in FIG. 57) coupled in series. An output amplifier 5706 is coupled in receiver channel portion 5700 down-stream from second open loop amplifier 5702.
First and second open loop amplifiers 5702 and 5704 each have a gain range. For example, in an embodiment, first and second open loop amplifiers 5702 and 5704 may each have a gain range of at least 36 dB, that extends from −6 dB to +30 dB. Output amplifier 5706 has a fixed gain. In the current example, the gain for output amplifier 5706 is a fixed gain of 6 dB. Receiver channel portion 5700 may be included in a receiver channel that receives WLAN signals, and/or receives RF signals formatted according to further communication schemes.
Each of first and second open loop amplifiers 5702 and 5704 are configured similarly to differential open loop circuit 5400 shown in FIG. 54, and described above. First and second open loop amplifiers 5702 and 5704 respectively include an open loop circuit 5708 and 5710. Open loop circuits 5708 and 5710 provide an input DC offset removal mechanism that not only reduces the corresponding open loop amplifier's own DC offset voltage, but also a DC offset present at an input to a respective sampling capacitor 5712 and 5714, at each stage. The offset removal by each of open loop circuits 5708 and 5710 is activated by a reset signal 5716. Reset signal 5716 is similar to DC voltage acquire signal 5418, shown in FIG. 54 and described above.
Furthermore, a high pass filter 5722 is located in receiver channel portion 5700 between open loop amplifier 5704 and output amplifier 5706. High pass filter 5722 reduces DC offset due to drift, and reduces low frequency noise. High pass filter 5722 is also initialized by reset signal 5716.
First and second auxiliary amplifiers 5718 and 5720 may be present in open loop circuits 5708 and 5710, respectively. First and second auxiliary amplifiers 5718 and 5720 are optional. When present, first and second auxiliary amplifiers 5718 and 5720 provide additional gain in the respective feedback loop, and can be used to enhance removal of the internal DC offsets of first and second open loop amplifiers 5702 and 5704, respectively. In the present example, first and second auxiliary amplifiers 5718 and 5720 contribute an additional 40 dB to the loop gain of open loop circuits 5708 and 5710, which yields an effective 70+dB for DC offset removal.
In an embodiment, for nominal device parameters and matched components in receiver channel portion 5700, the output DC offset of receiver channel portion 5700 should be equal to that of output amplifier 5706, amplified by the gain of output amplifier 5706. To enhance common mode noise rejection and improve differential signal gain, receiver channel portion 5700 is constructed with fully differential elements. In alternative embodiments, however, some or all components of receiver channel portion 5700 may be single-ended, depending on the particular application.
FIG. 58 illustrates an example variable gain amplifier 5800 that may be used for first and second open loop amplifiers 5702 and 5704 of FIG. 57. Variable gain amplifier 5800 includes a differential pair of NMOS FETs, MOSFETs 5810 and 5812, with an active/passive load. A variable gain function is accomplished by operating MOSFETs 5810 and 5812 in the linear region rather than the traditional saturated region. A second NMOS pair, MOSFETS 5802 and 5804, operate as voltage followers to control the drain voltage of MOSFETs 5810 and 5812, and consequently control the gain of variable gain amplifier 5800. MOSFETS 5802 and 5804 are also referred to as a cascode cell herein. Operation in this manner allows for the gain to be varied using few components, thereby minimizing side effects such as noise, non-linearity, etc.
The resulting voltage gain of variable gain amplifier 5800 is a function of a control voltage 5814, which is also referred to herein as Vgain. In the present example, the resulting gain is proportional to the square of control voltage 5814. Hence, a square-root pre-distortion function may be used on control voltage 5814 so that the resulting gain is more linearly proportional to an input control voltage. The square-root pre-distortion function is described in further detail below.
A load of variable gain amplifier 5800 includes a pair of PMOS devices, MOSFETs 5806 and 5808, which form a common mode load, and first and second resistors 5816 and 5818, which form a differential load. In the present example, these loads are used because they provide the ability to control the output common mode level with minimal components, while allowing a sufficient impedance to achieve the desired gain with low capacitance.
In an embodiment, variable gain amplifier 5800 may be buffered. For example, a class A bipolar output stage may be used to buffer variable gain amplifier 5800 to produce increased drive capability for a subsequent capacitive load, while minimizing a capacitive load detected by variable gain amplifier 5800. An example of variable gain amplifier 5800 with output buffer stages 5902 is shown in FIG. 59, according to an embodiment of the present invention. As shown in the example of FIG. 59, buffer stages 5902 are class A bipolar buffer stages that are coupled to the differential outputs of variable gain amplifier 5800. Each buffer stage 5902 includes a diode-connectedNPN transistor 5910. Each diode-connectedNPN transistor 5910 drives an NPN transistor 5904 configured to operate as a voltage follower. Note that in an alternative embodiment, a PNP transistor follower-to-NPN transistor follower configuration may be used, or further buffer configurations. In the present example, the NPN transistor-to-NPN transistor follower configuration is used due to VBE matching considerations. Furthermore, diode-connected NPN transistor 5910 is configured such that the input resistance seen by variable gain amplifier 5800 is still quite high, relative to the load resistance.
Buffer stages 5902 have an input resistance. In the present example, the input resistance to buffer stages 5902 may be approximately 300KΩ. Current sources 5906 and 5908 bias the bipolar devices of buffer stages 5902. For example, current source 5906 may be configured to provide 20 μA to each of diode-connected NPN transistors 5910, while current source 5908 may be configured to provide twice this amount, 40 μA, to each of output NPN transistors 5904. For example, the area of NPN transistors 5904 may be twice that of a diode-connected NPN transistor 5910, which allows them to have the same current density and thus equal base-emitter voltages (VBE).
Note that these buffer stage component types and parameter values are provided for illustrative purposes, and are not intended to limit the invention. The present invention is applicable to further component types and parameter values, as would be understood to persons skilled in the relevant art(s) from the teachings herein.
FIG. 60 illustrates receiver channel portion 5700 with example gain values, according to an embodiment of the present invention. As shown in FIG. 60, a combined gain range of receiver channel portion 5700 is −6 dB to +66 dB. In the open-loop configuration of receiver channel portion 5700, this gain is distributed among open-loop amplifiers 5702 and 5704, having −6 dB to +30 dB gain each, and closed loop output amplifier 5706, having a fixed gain of +6 dB. In the present example, each of open loop amplifiers 5702 and 5704 may be configured to have a maximum gain of −6 dB at a minimum control voltage of 0V, and a minimum gain of +30 dB at a maximum control voltage of 1.2V.
As described above, each of open-loop amplifiers 5702 and 5704 is avariable gain amplifier, such as variable gain amplifier 5800, shown in FIG. 58. Variable gain amplifier 5800 exhibits a non-linear gain as a function of control voltage 5814 (Vgain). Variable gain amplifier 5800 is biased such that the input pair, MOSFETs 5810 and 5812, operate in the linear, or triode, region. This allows for high achievable gain, with a low supply voltage, such as 3.3V. The gain of variable gain amplifier 5800 is determined by the ratio of the transconductance of the input pair to the conductance of the differential load resistors 5816 and 5818, which is dominated by the resistance value of load resistors 5816 and 5818, shown as RL, in FIG. 58. The gain of variable gain amplifier 5800 may be represented as follows in Equation 1:




  
    
      
        
          A
          v
        
        =
        
          
            g
            m
          
          
            g
            o
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        1
      
    
  




Where:

    
    
        Av=gain of variable gain amplifier 5800
        gm=transconductance of MOSFETs 5810 and 5812
        go=conductance of the differential load resistors 5816 and 5818

By operating the input pair, MOSFETs 5810 and 5812, in the linear region, their transconductance is controlled by their drain-to-source voltage (VDS). Thus, the transconductance of the input pair is given by:

    
    






  
    
      
        
          g
          m
        
        =
        
          
            
              β
              
                5
                ,
                6
              
            
            ⁢
            
              V
              
                DS
                
                  5
                  ,
                  6
                
              
            
          
          =
          
            
              k
              n
              ′
            
            ⁢
            
              
                W
                
                  5
                  ,
                  6
                
              
              
                L
                
                  5
                  ,
                  6
                
              
            
            ⁢
            
              V
              
                DS
                
                  5
                  ,
                  6
                
              
            
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        2
      
    
  




Where:





  
    β
    
      5
      ,
      6
    
  
  =
  
    
      k
      n
      ′
    
    ⁢
    
      
        W
        
          5
          ,
          6
        
      
      
        L
        
          5
          ,
          6
        
      
    
  




    
    
        W5,6 and L5,6=width and length parameters of MOSFETS 5810 and 5812
        k′n=constant related to MOSFETs 5810 and 5812

The transfer function of Equation 2 is dominated by the square-law behavior of MOSFETs 5802 and 5804 that are present in the cascode cell of variable gain amplifier 5800. The drain voltage presented to MOSFETs 5810 and 5812 is regulated by MOSFETs 5802 and 5804, and follows the gain control voltage 5814. The drain voltage is approximately equal to:

    
    






  
    
      
        
          
            V
            d
          
          ⁡
          
            (
            
              V
              gain
            
            )
          
        
        =
        
          
            V
            gain
          
          -
          
            
              (
              
                
                  
                    I
                    ss
                  
                  ⁢
                  
                    L
                    
                      3
                      ,
                      4
                    
                  
                
                
                  
                    k
                    n
                    ′
                  
                  ⁢
                  
                    W
                    
                      3
                      ,
                      4
                    
                  
                
              
              )
            
            
              1
              2
            
          
          -
          
            V
            thn
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        3
      
    
  




Where:

    
    
        Vgain=control voltage 5814
        Iss=current of current source 5820 shown in FIG. 58
        Vthn=threshold voltage
        k′n=constant related to MOSFETs 5802 and 5804
    
    


FIG. 61 shows an example detailed schematic of variable gain amplifier 5800, according to an embodiment of the present invention. FIG. 62 shows a plot 6200 of the gain (in dB) of variable gain amplifier 5800 of FIG. 61, where the gain is plotted as a function of control voltage 5814. A square-law characteristic for the gain is visible in a range 6202 of control voltage 5814, which extends approximately from 1.5V to 2.2V. Range 6202 is a desirable operating region for this particular implementation of variable gain amplifier 5800. However, note that at approximately 2.3V for control voltage 5814, saturation of the MOS devices of variable gain amplifier 5800 begins, and the increase in gain of variable gain amplifier 5800 diminishes.
In the present example, it would be desirable to have a gain control signal that is input to receiver channel portion 5700 be a linear voltage ranging from 0V to 1.2V. However, FIG. 63 illustrates a relationship of the gain of variable gain amplifier 5800 and control voltage 5814. As shown in FIG. 63, the gain of variable gain amplifier 5800 is proportional to the square of the difference in control voltage (and a threshold voltage). To produce a linear gain transfer function in dB in response to a linear input control voltage, the input control voltage must be conditioned.
FIG. 64 illustrates a process for conditioning an applied gain control voltage 6402 to generate control voltage 5814, according to an embodiment of the present invention. As illustrated in FIG. 64, in the present example, an applied gain control voltage 6402 may be scaled, raised to the 1⁄2 power, and offset to render a near linear gain function. Hence, variable gain amplifier 5800 will resultantly respond in a linear fashion to a linear variation in applied gain control voltage 6402.
As shown in FIG. 64, in a first stage 6404, applied gain control voltage 6402 (Vagc) may be scaled down in voltage, to match a high gain response of variable gain amplifier 5800. In a second stage 6406, the scaled control voltage may be pre-distorted with a function inversely related to the square law gain response of variable gain amplifier 5800. To counter the square law gain response, an inverse square law response, or square root function, may be applied. In a third stage 6410, an inherent offset, which is an undesired threshold voltage added to the control voltage during second stage 6406, may be removed. The undesired threshold voltage added during second stage 6404 is represented as being added to the control voltage by an adder 6408 in FIG. 64. In a fourth stage 6412, the control signal may be offset to an appropriate DC common mode level for the cascode portion of variable gain amplifier 5800. As shown in FIG. 64, control signal 5814 is output from fourth stage 6412. In a fifth stage (not shown in FIG. 64), control signal 5814 may be temperature compensated to counter an inherent temperature dependent behavior of the gain function of variable gain amplifier 5800.
In embodiments, any one or more of the stages shown in FIG. 64 may be used to condition 5814 control signal prior to being input to variable gain amplifier 5800, as well as alternative and additional conditioning stages.
To counteract the square-law gain function of variable gain amplifier 5800, a square root function in second stage 6406 is used. Hence, control signal 5814 is preconditioned by second stage 6406 such that a square root characteristic is included. Control signal 5814 is input to the cascode cell of variable gain amplifier 5800, and renders the desired response for amplifier 5800, i.e., a linear gain (in dB) versus a linear applied gain control signal 6402.
FIG. 65 illustrates an example square root function generator 6500, according to an embodiment of the present invention. Square root function generator 6500 has a square law characteristic similar to that of the cascode cell of variable gain amplifier 5800. The structure and operation of square root function generator 6500 is now described. As shown in FIG. 65, applied gain control signal 6402 is input to an amplifier 6502, which together with a MOSFET 6504, converts the input voltage of applied gain control signal 6402 to a current. The current is injected into a diode-connected MOSFET 6506, shown as a NMOS transistor, through a current mirror that includes MOSFETs 6508 and 6510. MOSFETs 6508 and 6510 are shown as PMOS transistors in FIG. 65. An output voltage 6512 of square root function generator 6500 is equal to the drain-to-source voltage of MOSFET 6506. The drain-to-source voltage of MOSFET 6506 is equal to the sum of the threshold voltage of MOSFET 6506 and the saturation voltage thereof, the latter being proportional to the square root of the current injected therein. Hence, output voltage 6512 is representative of the square root of applied gain control signal 6402, plus an offset voltage equal to the threshold voltage of MOSFET 6506. Output voltage 6512, Vout, is shown in Equation 4:




  
    
      
        
          
            
              
                V
                out
              
              =
              
                
                  
                    V
                    dsat4
                  
                  +
                  
                    V
                    thn
                  
                
                =
                
                  
                    
                      
                        2
                        ⁢
                        
                          I
                          4
                        
                      
                      
                        
                          k
                          n
                          ′
                        
                        ⁢
                        
                          
                            W
                            4
                          
                          
                            L
                            4
                          
                        
                      
                    
                  
                  +
                  
                    V
                    thn
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    
                      2
                      ⁢
                      
                        V
                        agc
                      
                    
                    
                      
                        R
                        1
                      
                      ⁢
                      
                        k
                        n
                        ′
                      
                      ⁢
                      
                        
                          W
                          4
                        
                        
                          L
                          4
                        
                      
                    
                  
                
                +
                
                  V
                  thn
                
              
            
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        4
      
    
  




Where:

    
    
        Vdsat4=Saturation voltage of MOSFET 6506
        Vthn=threshold voltage of MOSFET 6506
        I4=Vagc/R1=current though MOSFET 6506
        W4 and L4=width and length parameters of MOSFET 6506
        kn=constant related to MOSFET 6506

Offset subtraction may be used to remove any added DC voltage, which is primarily the threshold voltage of MOSFET 6506. For example, the offset subtraction may be accomplished by third stage 6410, as shown in FIG. 64 and described above.

    
    


Referring back to FIG. 57, note that after completion of a DC offset absorption or reduction period controlled by reset signal 5716, the reset switches in open loop circuits 5708 and 5710 are turned off, and auxiliary amplifiers 5718 and 5720 will be decoupled from open loop amplifiers 5702 and 5704. During this potentially “abrupt” decoupling event, unwanted charge may be injected into storage capacitors 5712 and 5714 by the reset switches. Thus, attention to the charge injection properties of the reset switches in open loop circuits 5708 and 5710 may be important, and is further discussed as follows.
Charge injection primarily emanates from the reset switches at the outputs of auxiliary amplifiers 5718 and 5720, which are used to couple and decouple the outputs of auxiliary amplifiers 5718 and 5720 to and from the inputs to open loop amplifiers 5702 and 5704. When reset signal 5716 transitions to a low logic level, an offset voltage induced due to the resulting charge injection will approximately be shown by Equation 5 below:




  
    
      
        
          V
          os_inj
        
        =
        
          
            1
            2
          
          ⁢
          
            
              C
              S
            
            
              
                C
                S
              
              +
              
                C
                H
              
            
          
          ⁢
          
            Δ
            ⁢
            V
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        5
      
    
  




Where:

    
    
        Vos—inj=resulting charge injection
        CS=stray capacitance appearing between gate of the reset switch to the respective one of capacitors 5712 and 5714
        CH=capacitance value of respective one of capacitors 5712 and 5714
        ΔV=change in voltage on reset signal 5716 due to transition

The “1⁄2” factor of Equation 5 is present because the path for charge injection from the gate to the hold capacitance forms approximately half of a particular switch's total gate to source/drain capacitance.

    
    


Although the offset voltage induced by charge injection is ideally added to both nodes of a differential signal (note that both differential nodes are not shown in the receiver channel path of FIG. 57), and thus would appear as a common mode signal, a reduction of charge injected offset error still may improve performance of the differential receiver channel. In the present example, an acceptable compromise with regard to the reset switches of open loop circuits 5708 and 5710 is to use reset switch size parameters of 3.84 μm/0.6 μm. These size parameters provide for a moderately conductive switch, with a gate-to-drain and gate-to-source capacitance that are acceptable from a cancellation and loading viewpoint. Using these example switch size parameters, the offset voltage created due to charge injection may be calculated as follows:




  
    V
    os_inj
  
  =
  
    
      
        1
        2
      
      ⁢
      
        
          C
          S
        
        
          
            C
            S
          
          +
          
            C
            
              i
              ⁢
              
                
              
              ⁢
              n
            
          
        
      
      ⁢
      Δ
      ⁢
      
        
      
      ⁢
      V
    
    =
    
      
        
          
            1
            2
          
          ·
          
            
              0.0067
              ⁢
              
                
              
              ⁢
              pF
            
            
              4.0067
              ⁢
              
                
              
              ⁢
              pF
            
          
          ·
          3.3
        
        ⁢
        
          
        
        ⁢
        V
      
      =
      
        2.75
        ⁢
        
          
        
        ⁢
        mV
      
    
  




Typically, charge injection reduction techniques include a charge cancellation MOS device (i.e., a “dummy” device) with the switching device. The gate of the charge cancellation device is driven by a complementary logic signal. The MOS dummy device may be sized at half of the area of the switching device, because about half of the charge is actually injected into the hold device, while the other half is injected into the sourcing node. The net charge injection is approximately equal to the integrated time-voltage product during which the charge is transferred. As such, a duration of the switching transient should be of little difference. However, this is true only for an ideally linear system. Some non-linear effects may change the results. Furthermore, bandwidth limitations may limit the temporal response, preventing complete charge accumulation. For these reasons, fast switching times, and overlapping switching signals are desired. Although 50% of the area of the switching device may be used for the area of the dummy switch, second order effects may cause a value of 40% to 60% of the area to be preferable.
FIG. 66 shows an example portion of variable gain amplifier 5800, with one or more dummy switches 6602 for cancellation of charge injection, according to an embodiment of the present invention. In the present example, when one or more dummy switches 6602 are present, as shown in FIG. 66, the calculated error due to charge injection can be reduced into the range of single microvolts, a substantial improvement.

    
    
        4.4.2 Operation of the Open Feedback Loop of the Present Invention
    
    


FIG. 67A shows a flowchart 6700 providing operational steps for performing embodiments of the present invention. FIGS. 67B–C provide additional operational steps for flowchart 6700, according to embodiments of the present invention. The steps of FIGS. 67A–C do not necessarily have to occur in the order shown, as will be apparent to persons skilled in the relevant art(s) based on the teachings herein. Other embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. These steps are described in detail below.
Flowchart 6700 begins with step 6702. In step 6702, a charge is received from a first node of the receiver channel. For example, referring to FIG. 52, the charge corresponds to a voltage that includes a DC offset voltage, and is received from output node 5204. In a differential receiver channel example embodiment of FIG. 54, the charge may be received from first and second output nodes 5424 and 5426.
In step 6704, the charge is stored. For example, the charge is stored in storage device 5208. In a differential receiver channel example embodiment, the charge is stored in capacitors 5408 and 5410.
In step 6706, the stored charge is de-coupled from the first node. For example, in FIG. 52, the first node is output node 5204. Storage device 5208 may be decoupled from output node 5204 by opening switch 5206. In a differential receiver channel example embodiment of FIG. 54, the stored charges may be decoupled from output nodes 5424 and 5426 by opening switches 5404 and 5406.
In step 6708, at a second node in the receiver channel a voltage corresponding to the stored charge is summed with a receiver channel signal. For example, the second node is summing node 5202 in FIG. 52. In a differential receiver channel example embodiment, the second node is one or both of first and second summing nodes 5428 and 5430. Stored DC voltage output signal 5214 is summed with receiver channel signal 5218 at summing node 5202. In a preferred embodiment, the first node is downstream from the second node in the receiver channel. For example, output node 5204 is downstream from summing node 5202.
In an embodiment, step 6704 includes the step where the charge is stored in a capacitor. For example, the charge may be stored in capacitor 5210. In a differential receiver channel example embodiment, the charges are stored in first and second capacitors 5408 and 5410.
FIG. 67B shows flowchart 6700 with additional optional steps, according to an embodiment of the present invention. In FIG. 67B, optional steps are indicated by dotted lines. As shown in step 6704 of FIG. 67B, in an embodiment, the charge received from the first node of the receiver channel is stored in a capacitor. In step 6710, a switch is coupled between the first node and the capacitor. For example, the switch may be switch 5206, which is shown coupled between output node 5204 and capacitor 5210 in FIG. 52. In a differential receiver channel example embodiment, first switch 5404 is coupled between first output node 5424 and first summing node 5428, and second switch 5406 is coupled between second output node 5426 and second summing node 5430.
FIG. 67C shows flowchart 6700 with additional optional steps, according to an embodiment of the present invention. In FIG. 67C, optional steps are indicated by dotted lines. As shown in FIG. 67C, flowchart 6700 may further include step 6712. In step 6712, at least one amplifier in the receiver channel is coupled between the first and second nodes. In an embodiment, an automatic gain control (AGC) amplifier is coupled in the receiver channel between the first and second nodes. For example, the AGC amplifier is AGC amplifier 5222, which is coupled between summing node 5202 and output node 5204. In a differential receiver channel example embodiment, differential AGC amplifier 5402 is coupled between first and second summing nodes 5428 and 5430 and first and second output nodes 5424 and 5426. In an alternative embodiment, any type and combination of amplifiers may be coupled between the summing and output nodes.
In an embodiment, flowchart 6700 further includes step 6714 shown in FIG. 67C. In step 6714, the receiver channel signal is substantially nulled. For example, receiver channel signal 5218 is nulled such that it primarily includes a DC offset voltage signal. In a differential receiver channel example embodiment, differential input signal 5420 is nulled. In an embodiment, the nulling step includes the step where a gain setting of an AGC amplifier that precedes the summing node in the receiver channel is reduced. For example, when second AGC amplifier 1604 (shown in FIG. 16) precedes summing node 5202 anywhere in the receiver channel, it may be nulled by reducing the gain setting supplied by second AGC signal 1620. In an embodiment, the gain setting is reduced to be substantially equal to zero.
In an embodiment, the second node is preceded by a down-converter module. For example, a summing node may be preceded by down-converter 1606, shown in FIG. 16, anywhere in the receiver channel. In an embodiment, the nulling step includes the step where a control signal coupled to a down-converter module is set to inactive. In an embodiment, the down-converter module includes a universal frequency down-conversion (UFD) module. For example, the down-converter is UFD module 114 shown in FIG. 1C, or aliasing module 300 shown in FIG. 3A. In an embodiment, the UFD module includes a switch and a storage element. For example, aliasing module 300 includes a switch 308 and a capacitor 310. In an embodiment, the control signal is coupled to the switch. For example, the control signal is control signal 306, which is coupled to switch 308. In an embodiment, the control signal coupled to the switch is set to inactive. For example, control signal 306 may be set to a logical low, to open switch 308. In a differential receiver channel example embodiment, the UFD module is differential UFD module 3000, shown in FIG. 30. Differential UFD module 3000 includes switch 3002 and first and second capacitors 3004 and 3006. Switch 3002 receives control signal 3012.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
4.5 Embodiments for Automatic Gain Control
Automatic gain control may be used in a communication system receiver channel to maintain the received signal of interest at a useful level. A receiver may use an automatic gain control system to keep the output signal of the receiver at a relatively constant level, despite variations in signal strength at the antenna(s) of the receiver. Automatic gain control makes it possible to range from a weak input signal to a strong input signal without having amplifiers in the receiver channel become saturated. It is important for a receiver to automatically vary the gain of the receiver in such a manner that the receiver will receive a weak signal with high sensitivity but a strong signal with low sensitivity.
Generally in an automatic gain control system, as described briefly above in section 4.2, a level detector monitors a downstream receiver channel signal. When the downstream receiver channel signal increases or decreases in amplitude, the level detector provides an automatic gain control (AGC) signal to an AGC amplifier upstream in the receiver channel. The AGC signal causes the AGC amplifier to attenuate or amplify the upstream receiver channel signal, accordingly. For example, FIG. 16 shows example receiver channel 1600 that includes first AGC amplifier 1610 and second AGC amplifier 1604, as described above in section 4.2. First AGC amplifier 1610 receives a first AGC signal 1626 and second AGC amplifier 1604 receives a second AGC signal 1620. First and second AGC signals 1626 and 1620 are generated by corresponding circuitry located downstream from the respective amplifiers. Typically, first and second AGC signals 1626 and 1620 are the same signal, or are generated separately. First AGC amplifier 1610 and second AGC amplifier 1604 amplify their respective receiver channel signals according to first and second AGC signals 1626 and 1620, respectively.
FIG. 17 shows a receiver channel 1700 with automatic gain control, according to an embodiment of the present invention. Receiver channel 1700 is substantially similar to receiver channel 1600 shown in FIG. 16, except for the configuration of the AGC signals. A first AGC signal 1704 is received by first AGC amplifier 1610. A second AGC signal 1706 is received by second AGC amplifier 1604. Second AGC signal 1706 is equal to first AGC signal 1704, multiplied or amplified by some amount.
In the embodiment of FIG. 17, multiplier 1702 generates second AGC signal 1706 by multiplying first AGC signal 1704 by a particular amount, shown as N in FIG. 17. This amount may be any value greater than zero (or less than zero if the receiver channel becomes inverted between AGC amplifiers). In a preferred embodiment, this amount is greater than one, and furthermore may be any integer value greater than one.
FIG. 26 shows an example embodiment for multiplier 1702. Multiplier 1702 as shown in FIG. 26 includes an operational amplifier 2602, a first resistor 2604, and a second resistor 2606 that are arranged in a single-ended non-inverting amplifier configuration. The ratio of first and second resistors 2604 (R1) and 2606 (R2) is selected to provide the gain for multiplier 1702 (1+R2/R1). As a result, multiplier 1702 amplifies first AGC signal 1704 to generate second AGC signal 1706. The present invention is applicable to other types of signal multipliers, as would be apparent to a person skilled in the relevant art(s) from the teachings herein.
When the magnitude of N is greater than 1, such as an integer value of 2, second AGC amplifier 1604 reacts more strongly to automatic gain control than does first AGC amplifier 1610, because second AGC signal 1706 has a greater amplitude than does first AGC signal 1704. For example, when second AGC amplifier 1604 is located in a radio frequency (RF) portion of the receiver channel, and the first AGC amplifier 1610 is located in an intermediate frequency (IF) or baseband portion of the receiver channel, the configuration of FIG. 17 allows for a greater reaction at the RF AGC amplifier than at the IF or baseband AGC amplifier. Hence, there is less perturbation in the receiver channel signal at the IF or baseband AGC amplifier. This provides for further advantages in DC offset acquisition and settling time in the receiver channel.
Furthermore, greater AGC reaction at RF in the receiver channel allows for a greater amplitude signal being received by down-converter 1606 in the receiver channel. Down-converter 1606 is then able to output a greater amplitude down-converted signal 1622. Thus, any DC offsets added into down-converted signal 1622 by down-converter 1606 have less impact proportionally than if down-converted signal 1622 was of lesser amplitude.
Hence, automatic gain control according to the present invention provides numerous benefits. Additionally, in embodiments, because a single source produces the AGC control signal that is the basis of AGC control for both AGC amplifiers, fewer components are required and less power may be consumed.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, the present invention is applicable to AGC implementations in any communication system type, where there are two or more AGC amplifiers. Additional multipliers may be used to produce further AGC signals from the first AGC control signal. The invention is intended and adapted to include such alternate embodiments.
Examples of the operation of automatic gain control embodiments of the present invention are described in the following sub-section.

    
    
        4.5.1 Operation of Automatic Gain Control Embodiments of the Present Invention
    
    


FIG. 48 shows a flowchart 4800 providing operational steps for performing embodiments of the present invention. FIGS. 49, 50, and 52 provide additional operational steps for flowchart 4800, according to embodiments of the present invention. The steps shown in FIGS. 48–50 and 52 do not necessarily have to occur in the order shown, as will be apparent to persons skilled in the relevant art(s) based on the teachings herein. Other embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. These steps are described in detail below.
As shown in FIG. 48, flowchart 4800 begins with step 4802. In step 4802, a first AGC signal is multiplied by an amount to generate a second AGC signal. For example, the first AGC signal may be first AGC signal 1704, which is multiplied to generate second AGC signal 1706.
In step 4804, the first AGC signal is provided to a first automatic gain control (AGC) amplifier coupled in a first portion of the receiver channel. For example, the first AGC amplifier may be first AGC amplifier 1610, as shown in FIG. 17.
In step 4806, the second AGC signal is provided to a second AGC amplifier coupled in a second portion of the receiver channel. For example, the second AGC amplifier may be second AGC amplifier 1604, which receives second AGC signal 1706.
FIG. 49 shows flowchart 4800 with additional optional steps, according to an embodiment of the present invention. In FIG. 49, optional steps are indicated by dotted lines. As shown in FIG. 49, flowchart 4800 may further include step 4908. In step 4908, the second AGC amplifier is positioned upstream in the receiver channel from the first AGC amplifier. For example, as shown in FIG. 17, second AGC amplifier 1604 is positioned upstream in the receiver channel from first AGC amplifier 1610.
FIG. 50A shows flowchart 4800 with additional optional steps, according to an embodiment of the present invention. In FIG. 50A, optional steps are indicated by dotted lines. In step 5010, a radio frequency receiver channel signal is received with the second AGC amplifier. For example, input RF signal 1616 may be a radio frequency signal that is received by second AGC amplifier 1604.
In step 5012, a baseband receiver channel signal is received with the first AGC amplifier. For example, down-converted signal 1622 may be a baseband signal that is received by first AGC amplifier 1610.
FIG. 50B shows flowchart 4800 with additional optional steps, according to an alternative embodiment of the present invention. In FIG. 50B, optional steps are indicated by dotted lines. In step 5014, a radio frequency receiver channel signal is received with the second AGC amplifier. For example, input RF signal 1616 may be a radio frequency signal that is received by second AGC amplifier 1604.
In step 5016, an intermediate frequency receiver channel signal is received with the first AGC amplifier. For example, down-converted signal 1622 may be an intermediate frequency signal that is received by first AGC amplifier 1610.
In an embodiment, step 4802 includes the step where the first AGC signal is multiplied by an integer amount to generate the second AGC signal. For example, as shown in FIG. 17, multiplier 1702 may multiply first AGC signal 1704 by an integer amount to generate second AGC signal 1706. In an embodiment, the first AGC signal is multiplied by 2 to generate the second AGC signal. For example, factor N may be equal to 2.
In an embodiment, step 4802 includes the step where the first AGC signal is amplified to generate the second AGC signal. For example, first AGC signal 1704 may be amplified by an amplifier such as shown in FIG. 23, to generate second AGC signal 1706.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
4.6 Exemplary Receiver Channel Embodiments of the Present Invention
This section provides further details about various communications system configurations in which embodiments of the present invention may be implemented, and provides further details for implementing these embodiments. These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
For exemplary purposes, this section describes the present invention in the context of WLAN communications system configurations. However, the invention is applicable to additional communication system environments. For instance, the invention as disclosed herein is applicable to any type of communication system receiver. These include wireless personal area network (WPAN) receivers (including the Bluetooth standard), wireless metropolitan area network (WMAN) receivers, code division multiple access (CDMA) receivers including wideband CDMA receivers, Global System for Mobile Communications (GSM) standard compatible receivers, and 3rd Generation (3G) network receivers.
In actual implementations, one or more embodiments of the present invention may be located in a WLAN receiver channel, such as either of receiver channels 1600 and 1700. The receiver channels may be configured to receive packets formatted according to any WLAN 802.11 standard format, such as direct sequence spread spectrum (DSSS) (including high rate DSSS) and frequency hopping spread spectrum (FHSS). The data rates for these formats include 1, 2, 5.5, and 11 Mbps. Another possible format, orthogonal frequency division multiplexing (OFDM), includes data rates ranging from 6 Mbps to 54 Mbps. Received WLAN signals may have carrier frequencies of 2.4 and 5.0 GHz, and others. The modulation techniques used for these various formats include phase shift keying (PSK), differential binary phase shift keying (DBPSK), differential quadrature phase shift keying (DQPSK), Gaussian frequency shift keying (GFSK), 16- and 64-quadrature amplitude modulation (QAM), packet binary convolutional coding (PBCC) modulation, and complementary code keying (CCK) modulation.
Receiver channels according to the present invention may have a variety of configurations. The embodiments of the present invention described above are adaptable to being implemented in either single-ended or differential receiver channels. It is noted that even-order inter-mod products may be more effectively canceled in differential implementations. Hence, in some applications, differential implementations may be desirable.
FIGS. 31A and 31B show further details of receiver channel 1700, according to an exemplary embodiment of the present invention. FIGS. 31A and 31B also incorporate examples of feedback loop 1900 and automatic gain control, according to embodiments of the present invention. FIG. 31A shows a first portion of receiver channel 1700, including an antenna 1614, optional low noise amplifier 1602, second AGC amplifier 1604, down-converter 1606, and first amplifier/filter section 1608. FIG. 31B shows a second portion of receiver channel 1700, including first AGC amplifier 1610, second optional amplifier/filter section 1612, and multiplier 1702.
As shown in FIG. 31A, down-converter 1606 may be a UFD module. The UFD module receives a control signal 3106. Alternative types of down-converters may be used for down-converter 1606, according to embodiments of the present invention.
Amplifier-filter section 1608 is shown including a first amplifier 3110, a filter 3112, and a feedback loop 1900a. First amplifier 3110 provides for gain in amplifier-filter section 1608. Filter 3112 provides for filtering in amplifier-filter section 1608. Feedback loop 1900a provides for gain and for DC offset voltage reduction in amplifier-filter section 1608. Feedback loop 1900a includes a first amplifier 1902a, a second amplifier 1908a, and an integrator 1904a. The elements of feedback loop 1900a operate as described for the similarly designated elements of feedback loop 1900 shown in FIG. 19. Feedback loop 1900a measures a DC offset voltage at output node 1914a, and subtracts the measured DC offset voltage from the receiver channel at summing node 1906a. 
Integrator 1904a provides for a variable frequency response, similarly to that of integrator 1904 shown in FIG. 23. Integrator 1904a receives two control signals, ACQ1 3104 and ACQ2 3102, that control the opening and closing of switches 2308a and 2310a in integrator 1904a, in order to vary the frequency response of feedback loop 1900a. 
Second amplifier 1908a provides for receiver channel gain between summing node 1906a and output node 1914a. First amplifier 1902a provides for gain in the feedback loop.
As stated above, receiver channel 1700 shown in FIGS. 31A and 31B include automatic gain control features of the present invention. The AGC features of the present invention are more fully described in section 4.5. As shown in FIG. 31B, multiplier 1702 receives first AGC signal 1704 and generates second AGC signal 1706. Second AGC signal 1706 is input to second AGC amplifier 1604 in FIG. 31A. First AGC signal 1704 is input to first AGC amplifier 1610 in FIG. 31B. Multiplier 1702 is shown in FIG. 31B as an operational amplifier implemented in a non-inverting configuration, but may be implemented in alternative configurations. The AGC signals for second AGC amplifier 1604 and first AGC amplifier 1610 are based upon a single AGC signal source. Furthermore, multiplier 1702 allows for faster gain control in second AGC amplifier 1604 than in first AGC amplifier 1610, by amplifying first AGC signal 1704 to generate a greater amplitude second AGC signal 1706.
Amplifier-filter section 1612 is shown to include feedback loop 1900b in FIG. 31B. Feedback loop 1900b provides for gain and for DC offset voltage reduction in amplifier-filter section 1612. Feedback loop 1900b includes a first amplifier 1902b, a second amplifier 1908b, and an integrator 1904b. The elements of feedback loop 1900b operate as described for the similarly designated elements of feedback loop 1900 shown in FIG. 19. Feedback loop 1900b measures a DC offset voltage at output node 1914b, and subtracts the measured DC offset voltage from the receiver channel at summing node 1906b. 
Integrator 1904b provides for a variable frequency response, similarly to that of integrator 1904 shown in FIG. 23. Integrator 1904b receives the two control signals ACQ1 3104 and ACQ2 3102, that control the opening and closing of switches 2308b and 2310b (and of switches 2308a and 2310a in integrator 1904a shown in FIG. 31A) in integrator 1904b of FIG. 31B, in order to vary the frequency response of feedback loop 1900b. 
Second amplifier 1908b provides for receiver channel gain between summing node 1906b and output node 1914b. First amplifier 1902b provides for gain in the feedback loop.
The present invention is applicable to any 802.11 WLAN receiver implementations, including differential receiver channel configurations. FIGS. 32A and 32B show further details of receiver channel 1700, according to an example differential receiver channel embodiment of the present invention. FIGS. 32A and 32B incorporate embodiments of feedback loop 1900 and automatic gain control, according to embodiments of the present invention. FIG. 32A comprises FIGS. 32A-1, 32A-2, 32A-3, 32A-4, and FIG. 32B comprises FIGS. 32B-1, 32B-2, and 32B-3. FIGS. 32A-1, 32A-2, 32A-3, and 32A-4 show a first portion of receiver channel 1700, including second AGC amplifier 1604, first amplifier/filter section 1608, and multiplier 1702. FIGS. 32B-1, 32B-2, and 32B-3 show a second portion of receiver channel 1700, including first AGC amplifier 1610 and second optional amplifier/filter section 1612. An antenna and down-converter are not shown in the portions of receiver channel 1700 shown in FIGS. 32A-1, 32A-2, 32A-3, 32A-4, 32B-1, 32B-2, and 32B-3. FIG. 30 shows a differential UFD module that may be used as a differential down-converter in down-converter 1606 shown in FIGS. 16 and 17, according to embodiments of the present invention. The invention is also applicable to other types of differential down-converters.
As shown in FIG. 32A-3, an input differential signal 3210 is received by second AGC amplifier 1604. Input differential signal 3210 is a differential signal, and second AGC amplifier 1604 is a differential AGC amplifier. Input differential signal 3210 may be a differential version of a received RF signal or IF signal, for example.
Amplifier-filter section 1608 is shown as a first amplifier 3202, a second amplifier 3204, a first filter 3206, a second filter 3208, and feedback loop 1900c. First and second amplifiers 3202 and 3204 receive the differential output of second AGC amplifier 1604, and provide gain to the + and − components of this signal. First and second filters 3206 and 3208 provide for filtering of the + and − components of the differential output of second AGC amplifier 1604.
Feedback loop 1900c provides for gain and for DC offset voltage reduction for the differential signal output by first and second filters 3206 and 3208. Feedback loop 1900c includes a first amplifier 1902c, a second amplifier 1908c, and an integrator 1904c. The elements of feedback loop 1900c operate as described for the similarly designated elements of feedback loop 1900 shown in FIG. 19. Feedback loop 1900c receives the amplified and filtered differential signal output of second AGC amplifier 1604 at summing node 1906c. Feedback loop 1900c measures aDC offset voltage at output node 1914c, and subtracts the measured DC offset voltage from the receiver channel at summing node 1906c. 
Second amplifier 1908c provides for receiver channel gain between summing node 1906c and output node 1914c. Second amplifier 1908c includes two amplifiers configured differentially in series.
First amplifier 1902c provides for gain in the feedback loop. First amplifier 1902c receives a receiver channel differential signal 3212 that is output from second amplifier 1908c, and outputs a single-ended output signal 1920.
Integrator 1904c provides for a variable frequency response, similarly to that of integrator 1904 shown in FIG. 23. Integrator 1904c receives single-ended output signal 1920. Integrator 1904c also receives two control signals, ACQ1 3104 and ACQ2 3102, that control the opening and closing of switches 2308c and 2310c in integrator 1904c, in order to vary the frequency response of feedback loop 1900c. 
As stated above, receiver channel 1700 shown in FIGS. 32A and 32B include automatic gain control features of the present invention. These features are more fully described in section 4.5. As shown in FIG. 32A-1, multiplier 1702 receives first AGC signal 1704 and generates second AGC signal 1706. Second AGC signal 1706 is input to second AGC amplifier 1604 in FIG. 32A-3. First AGC signal 1704 is input to first AGC amplifier 1610 in FIG. 32B-1. Multiplier 1702 is shown in FIG. 32A-1 as an operational amplifier implemented in a non-inverting configuration, but may be implemented in alternative configurations. The AGC signals for second AGC amplifier 1604 and first AGC amplifier 1610 are based upon a single AGC signal source that generates first AGC signal 1704. Furthermore, multiplier 1702 allows for faster gain control in second AGC amplifier 1604 than in first AGC amplifier 1610, by amplifying first AGC signal 1704 to generate a greater amplitude second AGC signal 1706.
In FIG. 32B-1, first AGC amplifier 1610 receives receiver channel differential signal 3212, and outputs an amplified differential signal.
Amplifier-filter section 1612 includes feedback loop 1900d. Feedback loop 1900d provides for gain and for DC offset voltage reduction in amplifier-filter section 1612. Feedback loop 1900d includes a first amplifier 1902d, a second amplifier 1908d, and an integrator 1904d. The elements of feedback loop 1900d operate as described for the similarly designated elements of feedback loop 1900 shown in FIG. 19. Feedback loop 1900d receives the amplified differential signal output of first AGC amplifier 1610 at summing node 1906d. Feedback loop 1900d measures a DC offset voltage at output node 1914d, and subtracts the measured DC offset voltage from the receiver channel at summing node 1906d. 
Second amplifier 1908d provides for receiver channel gain between summing node 1906d and output node 1914d. Second amplifier 1908d includes four amplifiers configured differentially in series, with a single-ended output, output signal 1628.
First amplifier 1902d provides for gain/attenuation in the feedback loop. First amplifier 1902d is shown in FIG. 32B-3 as a resistor voltage-divider circuit. First amplifier 1902d receives and attenuates output signal 1628 according to the voltage divider, and outputs an attenuated output signal 1920d. 
Integrator 1904d provides for a variable frequency response, similarly to that of integrator 1904 shown in FIG. 23. Integrator 1904d receives the two control signals ACQ1 3104 and ACQ2 3102, that control the opening and closing of switches 2308d and 2310d (and switches 2308c and 2310c in integrator 1904c shown in FIGS. 32A-2 and 32A-1) in integrator 1904d of FIGS. 32B-1, 32B-2, and 32B-3, in order to vary the frequency response of feedback loop 1900d. 
FIGS. 35–37 show exemplary frequency response waveforms for receiver channel 1700 configured as shown in FIGS. 31A–B and 32A–B, when the frequency response is varied. The frequency responses shown in FIGS. 35–37 for receiver channel 1700 may be varied as needed by the particular application, by selecting the circuit components accordingly. As stated above, a down-converter is not present in the portion of the receiver channel shown in FIGS. 32A–B, so frequency down-conversion does not occur in the portion of receiver channel 1700 shown in FIGS. 32A–B.
FIG. 35 shows a first frequency response waveform 3500 resulting when ACQ1 3104 and ACQ2 3102 are both set to high. This setting indicates a short time constant has been selected for integrators 1904a and 1904b in FIGS. 31A–B, or for integrators 1904c and 1904d in FIGS. 32A-1, 32A-2, 32B-1, 32B-2, and 32B-3. As can be seen in FIG. 35, a high-pass corner frequency for first frequency response waveform 3500 is located near 2.5 MHz.
FIG. 36 shows a second frequency response waveform 3600 resulting when ACQ1 3104 is set to a high level and ACQ2 3102 is set to a low level. This setting indicates a medium time constant has been selected for integrators 1904a and 1904b in FIGS. 31A–B, or for integrators 1904c and 1904d in FIGS. 32A-1, 32A-2, 32B-1, 32B-2, and 32B-3. As can be seen in FIG. 36, a high-pass corner frequency for second frequency response waveform 3600 is located near 269 KHz.
FIG. 37 shows a third frequency response waveform 3700 resulting when ACQ1 3104 and ACQ2 3102 are both set to low levels. This setting indicates a long time constant has been selected for integrators 1904a and 1904b in FIGS. 31A–B, or for integrators 1904c and 1904d in FIGS. 32A-1, 32A-2, 32B-1, 32B-2, and 32B-3. As can be seen in FIG. 37, a high-pass corner frequency for third frequency response waveform 3700 is located near 21.6 KHz.
In alternative embodiments, receiver channel 1700 shown in FIGS. 31A–32B may include one or more implementations of open loop circuit 5200, 5400, shown in FIGS. 52 and 54, respectively, for receiver channel gain and DC offset voltage reduction. For example, one or more of open loop circuit 5200 may be used in addition to, or instead of feedback loops 1900a and 1900b shown in FIGS. 31A and 31B. Furthermore, one or more of open loop circuit 5400 may be used in addition to, or instead of feedback loops 1900c and 1900d shown in FIGS. 32A and 32B.
FIG. 55 shows an example open loop circuit pair 5500 that may be implemented in receiver channel 1700 as shown in FIGS. 31A and 31B. Open loop circuit pair 5500 may replace, or be used in addition to feedback loops 1900a and 1900b. Open loop circuit pair 5500 includes a first open loop circuit 5200a, a second open loop circuit 5200b, and an amplifier 5502 coupled in series. By cascading multiple stages of open loop circuit 5200, greater receiver channel gains may be attained, and DC offset voltages may be better reduced.
First open loop circuit 5200a receives and amplifies receiver channel signal 5504. Second open loop circuit 5200b receives and amplifies the output of first open loop circuit 5200a. Amplifier 5502 receives and amplifies the output of second open loop circuit 5200b, and outputs an output signal 5506. Amplifier 5502 is optional.
First and second open loop circuits 5200a and 5200b also receive DC voltage acquire signal 5418, which controls the storing of a DC offset voltage present in their respective output signals. First open loop circuit 5200a stores a DC offset voltage that is present in receiver channel signal 5504 and amplified by AGC amplifier 5222a, and also stores a DC offset voltage due to AGC amplifier 5222a. The stored DC offset voltage is subtracted from receiver channel signal 5504 at summing node 5202a. Accordingly, a DC offset voltage is reduced by first open loop circuit 5200a as reflected in output signal 5220a. 
Likewise, second open loop circuit 5200b stores a DC offset voltage that is present in first open loop circuit output signal 5220a and amplified by AGC amplifier 5222b, and also stores a DC offset voltage due to AGC amplifier 5222b. This stored DC offset voltage is subtracted from output signal 5220a at summing node 5202b. Accordingly, a DC offset voltage is reduced by second open loop circuit 5200b as reflected in output signal 5220b. The operation of first and second open loop circuits 5200a and 5200b is described in further detail in section 4.4 above.
FIG. 56 shows a differential open loop circuit pair 5600 that may be implemented in receiver channel 1700 as shown in FIGS. 32A and 32B. Differential open loop circuit pair 5600 may replace, or be used in addition to feedback loops 1900c and 1900d. Differential open loop circuit pair 5600 includes a first differential open loop circuit 5400a, a second differential open loop circuit 5400b, and an amplifier 5602 coupled in series. Amplifier 5602 is arranged in a differential amplifier configuration. By cascading multiple stages of differential open loop circuit 5400, greater receiver channel gains may be attained, and DC offset voltages may be better reduced.
First differential open loop circuit 5400a receives and amplifies differential receiver channel signal 5604. Second differential open loop circuit 5400b receives and amplifies the output of first differential open loop circuit 5400a. Amplifier 5602 receives and amplifies the output of second differential open loop circuit 5400b, and outputs a differential output signal 5606. Amplifier 5602 is optional.
First and second differential open loop circuits 5400a and 5400b also receive DC voltage acquire signal 5418, which controls the timing of the storage of the DC offset voltage present in their respective output signals. First differential open loop circuit 5400a stores a DC offset voltage that is present in differential receiver channel signal 5604 and amplified by AGC amplifier 5402a, and also stores a DC offset voltage due to AGC amplifier 5402a. The stored DC offset voltage is subtracted from differential receiver channel signal 5604 at summing nodes 5432a and 5434a. Accordingly, a DC offset voltage is reduced by first differential open loop circuit 5400a as reflected in differential output signal 5422a. 
Likewise, second differential open loop circuit 5400b stores a DC offset voltage that is present in first differential open loop circuit output signal 5422a and amplified by AGC amplifier 5402b, and also stores a DC offset voltage due to AGC amplifier 5402b. This stored DC offset voltage is subtracted from differential output signal 5422a at summing nodes 5432b and 5434b. Accordingly, a DC offset voltage is reduced by second differential open loop circuit 5400b as reflected in differential output signal 5422b. The operation of first and second open loop circuits 5400a and 5400b is described in further detail in section 4.4 above.
Note that in the example embodiments shown in FIGS. 55 and 56, during operation of the receiver channel, a change in the gain of a first open loop circuit may cause the DC offset correction performed by the second open loop circuit to become incorrect. For example, a change in the gain of first differential open loop circuit 5400a may occur due to a change in the level of AGC signal 5416. This may change the level of differential output signal 5422a that is input to second differential open loop circuit 5400b. This change may appear as a DC offset to second differential open loop circuit 5400b. If this gain change occurs without reacquiring the DC offset voltage in the second open loop circuit, the DC offset due to the gain change may not be removed by the second open loop circuit, and may instead be amplified, increasing the level of unwanted DC offset.
The embodiment of open loop circuit 5200 shown in FIG. 53 may be used to better maintain DC offset correction with varying gain in cascaded stages such as shown in FIGS. 55 and 56. To better maintain DC offset correction with varying gain in cascaded stages, the DC offset correction error in each stage must be reduced. This may be accomplished by increasing the open loop gain for each amplifier.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

    
    
        4.6.1 Using the Receiver Channel of the Present Invention to Receive a WLAN Signal Packet
    
    


The section provides examples of how embodiments of the present invention may be used to receive signal frames or packets, and in particular, to receive WLAN signal packets. WLAN signal frames are briefly described. Selection of antenna diversity is described, and the use of variable frequency response according to the present invention is described in relation to receiving a WLAN signal frame. These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
As mentioned above, receiver channels 1600 and 1700 may be used to receive WLAN signals. For example, as described as follows, receiver channel 1700 may receive a transmitted WLAN DSSS frame modulated according to DQPSK, and having a short preamble. The short preamble portion of the frame is received first, and includes a 56 bit SYNC field that a receiver uses to acquire the subsequent portions of the signal. In this example, the preamble data rate is 1 Mbps. After receiving the preamble, a portion of the frame called a SFD follows. The SFD field contains information marking the start of the PSDU frame. The PSDU is the data field for the DSSS frame.
FIG. 39 shows an example timeline 3900 for receiving a DSSS frame. Timeline 3900 includes a first time segment 3902, a second time segment 3904, a third time segment 3906, a fourth time segment 3908, a fifth time segment 3910, a sixth time segment 3912, and a seventh time segment 3914. In the example of FIG. 39, the receiver includes two switchable antennas (i.e., dual diversity). During time segments shown in FIG. 39, the receiver switches between the two antennas, labeled antennas A and B, to determine which antenna is best suited to receive the remainder of the frame. In FIG. 39 each of the time segments, except for first time segment 3902, last for 10 μs. In alternative embodiments, there may be more or fewer time segments, and they may last for longer or shorter segments of time. For example, if the preamble was a long preamble (128 bits), there may be the same number of time segments, but they could each last for 20 μs instead of 10 μs. Alternatively, there could be a larger number of time segments.
As shown in FIG. 39, during first time segment 3902, which lasts 2 μs, the transmitted signal ramps up. During first time segment 3902 and second time segment 3904, which lasts 10 μs, the first antenna, antenna A, is selected to receive the transmitted signal. During third time segment 3906, which lasts 10 μs, the second antenna, antenna B, is selected to receive the transmitted signal. During fourth time segment 3908, which lasts 10 μs, antenna A, is again selected to receive the transmitted signal. During fifth time segment 3910, which lasts 10 μs, antenna B is again selected to receive the transmitted signal. During sixth time segment 3912, which lasts 14 μs, the one of antennas A and B, that was chosen to receive the transmitted signal is selected to receive the transmitted signal frame. During seventh time period 3914, the SFD frame portion and remainder of the DSSS frame are received using the chosen antenna.
FIG. 38 shows example waveforms related to the operation of receiver channel 1700 as shown in FIGS. 32A–B in a WLAN environment, according to an embodiment of the present invention. The waveforms of FIG. 38 relate to receiving the preamble of the above described DSSS frame. The waveforms shown in FIG. 38 are output signal 1628, second AGC signal 1706, integrator output signal 1918c, and AGC2 3102. FIG. 38 shows integrator output signal 1918c, which is related to feedback loop 1900c, but it is understood to persons skilled in the relevant art(s) from the teachings herein that integrator output signal 1918d is similar, even though not shown.
Receiver channel 1700 as shown in FIGS. 32A and 32B provides for gain, filtering, and DC offset voltage reduction for input differential signal 3210. Output signal 1628, shown in FIG. 32B-3, is the output signal for receiver channel 1700. As can be seen in the embodiment of FIG. 38, output signal 1628 is an approximately 1 MHz information signal.
ACQ2 3102 is shown as a logical high from 0 to about 4 μs (FIG. 38 shows ACQ2 3102 transitioning to a logic low at about 4 μs). During this period, ACQ1 3104 is also high (not shown), so feedback loops 1900c and 1900d are causing receiver channel 1700 to operate with a frequency response similar to first frequency response 3500 shown in FIG. 35 (i.e., fast time constant). First frequency response 3500 shows low gain as DC is approached, so DC offset acquisition by feedback loops 1900c and 1900d is not as significant during this time period. For example, integrator output signal 1918c in FIG. 38, shows the amount of DC offset being fed back to be subtracted from the receiver channel signal at summing node 1906c. This time period coincides roughly with first time segment 3902 and a portion of second time segment 3904 shown in FIG. 39.
ACQ2 3102 transitions to a logical low level at around 4μs, as shown in FIG. 38. ACQ1 3104 remains high (not shown), so feedback loops 1900c and 1900d are causing receiver channel 1700 to operate with a frequency response similar to second frequency response 3600 shown in FIG. 36 (i.e., medium time constant). Receiver channel 1700 retains this frequency response for most of the remainder of the timeline 3900. Second frequency response 3600 shows moderate gain as DC is approached, so DC offset acquisition by feedback loops 1900c and 1900d is more significant during this time period. Integrator output signal 1918c shown in FIG. 38, operates with improved DC offset accuracy during this time period, due to the medium time constant selection.
While ACQ2 3102 and ACQ1 3104 remain in this state, receiver channel 1700 begins to switch between antennas A and B to determine which is best suited to receive the incoming DSSS frame. During the time period of approximately 4 μs through 14 μs, corresponding to second time segment 3904 shown in FIG. 39, antenna A is selected. During this time period, second AGC signal 1706 ramps up to increase the gain of first AGC amplifier 1908c. This increase in gain is reflected in output signal 1628, which increases in amplitude. Second AGC signal 1706 is increased because downstream processing determined that the amplitude of output signal 1628 was initially too low, with antenna A as the input antenna.
The amount of DC offset detected also increases during this time period, due to the increase in gain, as reflected in integrator output signal 1918c. During the time period from about 4 μs to about 12 μs, it can be seen that the absolute offset of output signal 1628 from zero volts, which initially is significant (the center of output signal 1628 is at about −0.2 V at 4 μs), is reduced to be essentially equal to zero volts. This decrease is caused by an increase in integrator output signal 1918c during this time period, which feeds back the DC offset to be summed with the receiver channel.
During the time period of approximately 14 μs through 24 μs, corresponding to third time period 3906 shown in FIG. 39, antenna B is selected. During this time period, second AGC signal 1706 is decreased to decrease the gain of first AGC amplifier 1908c. This decrease in gain is reflected in output signal 1628, which initially increases sharply with the switch to antenna B, and then decreases in amplitude. Second AGC signal 1706 is decreased because downstream processing determined that the amplitude of output signal 1628 was initially too high, with antenna B as the input antenna.
The amount of DC offset detected also decreases during this time period, due to the decrease in gain, as reflected in integrator output signal 1918c. During the time period from about 14 μs to about 18 μs, it can be seen that the absolute offset of output signal 1628 initially increases, and then is decreased. The offset of output signal 1628 was initially significant (the center of output signal 1628 is at about 0.5 V at 16 μs), is reduced to be essentially equal to zero volts. This decrease is caused by an decrease in integrator output signal 1918c during this time period, which feeds back the DC offset to be summed with the receiver channel.
The process of switching between antenna A and antenna B continues during the next two time periods of 24 μs to 34 μs, and 34 μs to 44 μs. These correspond to fourth and fifth time segments 3908 and 3910 shown in FIG. 39. Similar results are found during these two time periods as occurred during the previous two.
As shown in the following time period, 44 μs to 54 μs, which corresponds to sixth time segment 3912, antenna B is selected to receive the DSSS frame. At the beginning of the next time period, corresponding to seventh time segment 3914 shown in FIG. 39, ACQ2 3104 will transition to a logical low level while ACQ1 3104 remains low (not shown in FIG. 38). In this state, feedback loops 1900c and 1900d will cause receiver channel 1700 to operate with a frequency response similar to third frequency response 3700 shown in FIG. 37 (i.e., slow time constant). Receiver channel 1700 retains this frequency response for the remainder of the DSSS frame. Third frequency response 3700 shows relatively greater gain as DC is approached, so DC offset acquisition by feedback loops 1900c and 1900d is even more significant during this time period. In other words, feedback loops 1900c and 1900d will track the DC offset with greater accuracy, due to the slow time constant selection.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

    
    
        4.6.2 Embodiments for Generating Control Signals for a Receiver Channel According to the Present Invention
    
    


This section provides embodiments for generating control signals used to vary the frequency response of a receiver channel, according to embodiments of the present invention. For example, this section relates to circuits and modules used to generate first and second control signals 2312 and 2314 shown in FIG. 23 and generating ACQ1 3104 and ACQ2 3102 shown in FIGS. 31A–32B. Varying the frequency response of a receiver channel may be used to enhance DC offset reduction, as described above. A window comparator for monitoring the level of DC offset is described. A state machine for sequencing the control signals is also described. The state machine may receive the output of the window comparator as an input, among other input signals.

    
    
        
        
            4.6.2.1 Window Comparator for Monitoring DC Offset
        
        
    
    


A window comparator according to the present invention may be used to monitor a signal in a receiver channel, and determine whether the level of DC offset in the receiver channel is within an acceptable range. FIG. 41 shows a high level view of a window comparator module 4100, according to an embodiment of the present invention. The implementations for window comparator module 4100 below are described herein for illustrative purposes, and are not limiting. In particular, window comparator module 4100 as described in this section can be achieved using any number of structural implementations, including hardware, firmware, software, or any combination thereof.
Window comparator module 4100 receives an I channel input signal 4102 and a Q channel input signal 4104. For example, I channel input signal 4102 and Q channel input signal 4104 may be output signals of respective receiver channels, such as output signal 1628 shown in FIGS. 16 and 17, or may be upstream signals in the respective receiver channels. Window comparator module 4100 determines whether a DC offset in each of I channel input signal 4102 and Q channel input signal 4104 is within an acceptable range. Window comparator module 4100 outputs window compare (WC) signal 4106, which indicates whether both of I channel input signal 4102 and Q channel input signal 4104 are within acceptable ranges.
Window comparator module 4100 as shown in FIG. 41 accepts as input I and Q channel signals, but in alternative embodiments may accept a single channel signal as input, or may accept additional input channel signals.
FIG. 42 shows further detail of an exemplary window comparator module 4100, according to an embodiment of the present invention. Window comparator module 4100 includes a prefilter 4202, a window comparator 4204, a filter 4208, a magnitude comparator 4212, and an AND gate 4216. FIG. 42 shows the components of a window comparator module 4100 used to provide the window compare function for I channel input signal 4102. AND gate 4216 is optional, and may be present when more than one receiver channel signal is input to window comparator module 4100, as in the embodiment shown in FIG. 41.
Prefilter 4202 receives and filters I channel input signal 4102, and outputs a filtered signal 4220. Prefilter 4202 is optional, and is present when I channel input signal 4102 requires filtering. For example, prefilter 4202 may be used to remove data/symbol variance. Prefilter 4202 may be any suitable filter type.
Window comparator 4204 receives filtered signal 4220 and voltage reference 4206. Window comparator 4204 compares the voltage level of filtered signal 4220 to determine whether it is within a voltage range centered upon the voltage value of voltage reference 4206. For example, voltage reference 4206 may be zero when zero is the reference value for the receiver channel, or may be another value such as 1.5 volts, or any other reference voltage value. In one example, the voltage range may be +/−50 mV around the value of voltage reference 4206. Window comparator 4204, for example, may include two analog comparators. The first analog comparator may determine whether filtered signal 4220 is above a maximum value of the voltage range, and the second analog comparator may determine whether filtered signal 4220 is below a minimum value of the voltage range. Preferably, window comparator outputs a logical output signal, compare value 4222. For example, compare value 4222 may be a logical high value when the voltage level of filtered signal 4220 is within the voltage range, and a logical low level when the voltage level of filtered signal 4220 is outside the voltage range.
Filter 4208 receives compare value 4222 and clock 4210. Filter 4208 outputs a value providing an indication of how well I channel input signal 4102 is remaining within the voltage range. For example, filter 4208 may provide an output that indicates how many clock cycles of clock 4210 that filter signal 4220 was found to be within the voltage range, during some number of the last clock cycles. In embodiments, filter 4208 may be a finite impulse response (FIR) or an infinite impulse response (IIR) filter. Preferably, filter 4208 outputs a logical output value, filter output 4222, that provides the indication.
FIG. 43 shows an example embodiment for window comparator module 4100, where filter 4208 includes a FIR filter. The FIR filter of filter 4208 includes a plurality of registers 4302a through 4302k (12 registers in this example) that store and shift values of compare value 4222 during each cycle of clock 4210. In the embodiment of FIG. 43, clock 4210 is shown to be an 11 MHz clock, but may instead be of alternative clock cycles rates. Registers 4302a through 4302k provide register output signals 4304a through 4304k, which are the shifted and stored values of compare value 4222. In embodiments, register output signals 4304a through 4304k may be weighted (not shown). Register output signals 4304a through 4304k are summed by summer 4306. Summer 4306 outputs a summed signal 4224, which is essentially a sum of the previous k values of compare value 4222.
As shown in FIG. 43, filter 4208 may receive a WC reset signal 4308 that is used to reset registers 4302a through 4302k to a low logical output value. WC reset signal 4308 may be used at power up, and at other times during the operation of a receiver channel, when it is desired to re-start the monitoring of a receiver channel signal for DC offset.
As shown in FIGS. 42 and 43, magnitude comparator 4212 receives summed signal 4224 and a threshold value 4214. Magnitude comparator 4212 compares the value of summed signal 4224 to threshold value 4214. If summed signal 4224 is greater than threshold value 4214, magnitude comparator 4212 outputs a logical high value on a I channel WC signal 4226, indicating that a DC offset voltage level in I channel input signal 4102 has been determined to be within an acceptable voltage range for enough of the designated length of time. If summed signal 4224 is less than or equal to threshold value 4214, I channel WC signal 4226 is a logical low value, indicating that a DC offset voltage level in I channel input signal 4102 has been determined to be outside of an acceptable voltage range for too much of the designated length of time. In the example of FIG. 43, threshold 4214 is shown in be equal to 7 (out of 12 cycles), but may be equal to other values.
When AND 4216 is present, AND 4216 receives I channel WC signal 4226 and comparable signal for every other channel being monitored by window comparator module 4100. AND 4216 outputs WC signal 4106 that indicates whether all receiver channels have acceptable DC offset values. FIG. 42 shows AND 4216 receiving I channel WC signal 4226 for the I channel, and Q channel WC signal 4218 for the Q channel. When both of I and Q channel WC signals 4226 and 4218 are equal to a high logical value, indicating that both channels are within the acceptable DC offset voltage range, AND 4216 outputs a logical high value on WC signal 4106. When either or both of I and Q channel WC signals 4226 and 4218 are not equal to a logical high value, WC signal 4106 is a logical low value.
FIG. 44 shows example waveforms related to the operation of window comparator 4100, according to an embodiment of the present invention. FIG. 44 shows waveforms for I channel input signal 4102, filtered signal 4220, and I channel WC signal 4226 of FIG. 43.
I channel input signal 4102 is an I channel receiver signal to be monitored, which is shown as a data signal that is triangle modulated with DC offset. Filtered signal 4220 is a filtered version of I channel input signal 4102, where the higher frequency oscillating data information is filtered out, and the lower frequency DC offset voltage remains. For the example of FIG. 44, reference voltage 4206 is equal to 1.65 V, and the desired DC offset voltage range is 1.6 V to 1.7 V (+/−0.05V around 1.65V).
As shown in I channel WC signal 4226, as filtered signal 4220 moves above 1.7 V, and moves below 1.6 V, for a long enough period of time, I channel WC signal 4226 is a logical low level, indicating an unacceptable amount of DC offset. As long as I channel WC signal 4226 remains between 1.6 V and 1.7 V, I channel WC signal 4226 is a logical high signal, indicating an acceptable amount of DC offset.
It should be understood that the above examples for window comparator module 4100 are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

    
    
        
        
            4.6.2.2 State Machine for Generating Control Signals
        
        
    
    


FIG. 45 shows an example state machine module 4500 for generating and sequencing control signals of the present invention, such as first and second control signals 2312 and 2314 shown in FIG. 23, and ACQ1 3104 and ACQ2 3102 shown in FIGS. 31A–32B. Implementations for state machine 4500 are described herein for illustrative purposes, and are not limiting. In particular, state machine 4500 as described in this section can be achieved using any number of structural implementations, including hardware, firmware, software, or any combination thereof.
State machine module 4500 according to the present invention may receive one or more of a variety of inputs that are used to generate control signals. FIG. 45 shows an embodiment of state machine module 4500 that receives WC signal 4106, a PCM signal 4502, a diversity signal 4504, and a clock signal 4506. State machine 4500 generates ACQ1 3104 and ACQ2 3102. In alternative embodiments, state machine module 4500 may receive fewer or more inputs, and may generate fewer or more outputs than shown in FIG. 45.
In an embodiment, PCM signal 4502 provides one or more bits of data to state machine module 4500 that indicate the mode or state of the communication system that includes the receiver channel. Hence, PCM signal 4502 provides information that indicates whether state machine module 4500 needs to be operating, for example. For instance, in an embodiment, PCM signal 4502 provides a two bit-wide signal to state machine module 4500, in the form of bits PCM1 and PCM2. The communication system modes provided to state machine module 4500 via PCM1 and PCM2 are shown in the table below:











TABLE 2







Mode
PCM1
PCM2









Off
0
0



Standby
0
1



Transmitting
1
0



Receiving
1
1










“Off” mode is where the communication system that includes the receiver channel is not operating. “Standby” mode is where the communication system is in a standby or wait state. “Transmitting” mode is where the communication system is currently in a transmitting state. “Receiving” mode is where the communication system is in a receiving state. In an embodiment, state machine module 4500 only needs to be active when the communication system is in receiving mode. Hence, in such an embodiment, state machine module 4500 will only be active when PCM1 and PCM2 are both equal to a logical high level, as shown in the above table.

In an embodiment, state machine module 4500 receives WC signal 4106, as further described in section 4.6.2.1 above. As described above, WC signal 4106 provides an indication of whether the level of DC offset in the receiver channel is within an acceptable range. WC signal 4106 is a logical high level when DC offset is within an acceptable range, and is a logical low level when DC offset is outside of the acceptable range. Hence, when state machine module 4500 receives a logical low or high level on WC signal 4106, state machine may manipulate ACQ1 3104 and ACQ2 3102 to cause the receiver channel to change the DC offset acquisition mode, as described above in section 4.3.1 in regards to first and section control signals 2312 and 2314.
For example, DC offset in receiver channel 1600 or 1700 may be drifting out of the acceptable voltage range, when the receiver channel is operating according to a slow time constant. When the receiver channel is operating according to a slow time constant, ACQ1 3104 and ACQ2 3102 are set to logical low levels. Hence, the receiver channel will have a frequency response with a relatively lower 3 dB cutoff frequency, and a relatively larger amount of 1/f noise, as shown in FIG. 40, may be passing through the receiver channel. This larger amount of 1/f noise may contribute to the DC offset drifting out of the acceptable range. Hence, when WC signal 4106 transitions to a low logical level, indicating that DC offset is out of an acceptable range, one or both of ACQ 3104 and ACQ2 3102 may be set to logical high levels in order to select a medium or faster time constant, to select a frequency response for the receiver channel with a relatively higher high-pass corner frequency. These time constants will cause the receiver channel to filter out more of the 1/f noise, and possibly allow the receiver channel to better attain and remove the DC offset, to bring the receiver channel DC offset back into an acceptable DC offset voltage range.
Furthermore, although not shown in FIG. 45, state machine module 4500 may output WC reset signal 4308, shown as an input signal to waveform comparator 4100 in FIG. 43. In FIG. 43, WC reset signal 4308 is used to reset filter 4208, which has been keeping track of how long the DC offset has been out of range. State machine module 4500 may toggle WC reset signal 4308 for various reasons, including at power up and during a transition from transmitting to receiving modes.
Diversity signal 4505 is a one or more bit wide signal that at least provides an indication of antenna diversity transitions. For example, a first bit of diversity signal 4505, b[0], may transition from a logic low to a logic high, and vice versa, when a transition from one diversity antenna to another occurs. Diversity signal 4505 may provide further bits of information that indicate the type of diversity antenna search being performed.
Clock signal 4506 is received to control the timing for state machine module 4500. Clock signal 4506 may be the same as or different from clock 4210.
FIG. 46 shows a state diagram 4600, according to an exemplary embodiment of the present invention. State diagram 4600 may be implemented in state machine module 4500 to generate signals ACQ1 3104, ACQ2 3102, and WC reset signal 4308. State diagram 4600 includes states 4602, 4604, 4606, 4608, 4610, and 4612. State diagram 4600 is particularly applicable to a WLAN environment, and is applicable to both short preamble (e.g., 56 μS) and long preamble (e.g., 128 μS) data frames, for example. Time periods are provided below for the length of time that some of the states are active. In a WLAN environment, the time periods, and corresponding levels of ACQ1 3104 and ACQ2 3102, correspond to the time periods shown in FIG. 39 above.
In the embodiment of state diagram 4600, clock signal 4506 is used to control timing. PCM 4502 is a two bit-wide input signal formed from PCM1, PCM2, as further described above. ACQ1 3104 and ACQ2 3102 form a two-bit wide signal named ACQ in state diagram 4600, in the bit order of ACQ1 3104, ACQ2 3102. A signal TOUT is shown in state diagram 4600. When TOUT is shown equal to zero during a transition from a first state to a second state, this indicates that a time period defined by the first state has expired. In the embodiment of state diagram 4600, WC reset signal 4308 may or may not be generated, although it is shown as generated in state diagram 4600.
Diversity signal 4504 provides an antenna diversity transition indication to state diagram 4600, through b[0], as described above. A logical high or low level of signal b[0] each indicate a respective diversity antenna setting. A signal B[0] is used to represent an updated version of b[0]. The signals b[0] and B[0] are compared to detect a diversity antenna transition. When b[0] is not equal to B[0], a diversity antenna transition has just occurred. When they are equal, a diversity transition has not occurred. When a diversity antenna has finally been selected for the WLAN data frame, b[0] will become dormant.
The states of state diagram 4600 are further described as follows.
State 4602 shown in FIG. 4600 is the active state upon power-up/reset. After system power up, the active state transitions from state 4602 to state 4604 via a transition 4614. PCM is set to 00, which signifies an “off” mode for state machine module 4500. Also, at system power up, B[0] equals b[0].
When active, state 4604 is an off state for state machine module 4500. State 4606 is remained in when the communication system remains in a mode other than a receiving mode, such as “off”, “standby”, or “transmitting.” As long as PCM does not change to 11 (receiving mode), a transition 4616 transitions from state 4604 back to state 4604. When PCM transitions to be equal to 11, (receiving mode), the active state transitions from state 4604 to state 4606 via a transition 4618.
In state 4606, ACQ is equal to 11. In other words, ACQ1 3104 and ACQ2 3102 are selecting a short time constant for DC offset acquisition. Furthermore, WC reset signal 4308 may be set equal to 1 for a clock cycle during the transition to state 4606, to reset the DC offset acquisition registers of window comparator module 4100. In an embodiment, state 4606 is active for a first time period of 6 μS. After the first time period in state 4606 expires, the active state transitions from state 4606 to state 4608 via a transition 4620.
In state 4608, ACQ is equal to 10. In other words, ACQ1 3104 and ACQ2 3102 are selecting a medium time constant for DC offset acquisition. In an embodiment, state 4608 is active for a second time period of 12 μS. If a diversity transition occurs while state 4608 is active, (i.e., B[0] is not equal to b[0]) atransition 4622 transitions from state 4608 back to state 4608. State 4608 is thus again active for a new second time period of 12 μS. However, after second time period in state 4608 expires, the active state transitions from state 4608 to state 4610 via a transition 4624.
In state 4610, ACQ is equal to 10. In other words, ACQ1 3104 and ACQ2 3102 are continuing to select a medium time constant for DC offset acquisition. In an embodiment, state 4610 is active for a third time period of 9 μS. If a diversity transition occurs while state 4610 is active (i.e., B[0] is not equal to b[0]), the active state transitions from state 4610 back to state 4608 via a transition 4626. After third time period in state 4610 expires, the active state transitions from state 4610 to state 4612 via a transition 4628.
In state 4612, ACQ is equal to 00. In other words, ACQ1 3104 and ACQ2 3102 select a long time constant for DC offset acquisition. In an embodiment, WC reset signal 4308 is equal to 0. State 4608 is active as long as a receiving mode is maintained, and a diversity transition does not occur. If a diversity transition occurs while state 4612 is active (i.e., B[0] is not equal to b[0]), the active state transitions from state 4612 back to state 4608 via a transition 4630. When PCM is set to be equal to a setting other than 11, the active state transitions from state 4612 to state 4604, via a transition 4632.
FIG. 47 shows a state diagram 4700, according to an exemplary alternative embodiment of the present invention. State diagram 4700 may be implemented in state machine module 4500 to generate signals ACQ1 3104, ACQ2 3102, and WC reset signal 4308. State diagram 4700 includes states 4702, 4704, 4706, 4708, 4710, 4712, 4734, 4736, and 4746. State diagram 4700 is similar to state diagram 4600 in using PCM and b[0]/B[0] as input signals, while additionally using WC signal 4106 (shown in FIG. 41) as an input signal. In state diagram 4700, when WC signal 4106 is received, changes to states of ACQ may occur, such that changes in the DC offset voltage acquisition time constant are made. For example, a change in WC signal 4106 may cause a change from a medium time constant to a long time constant, and vice versa. State diagram 4700 is particularly applicable to a WLAN environment, and is applicable to both short preamble (e.g., 56 μS) and long preamble (e.g., 128 μS) data frames, for example.
It should be understood that the above state machine and state diagram examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, diversity signal 4505 may provide further bits of information that control the operation of state machine 4500. Diversity signal 4505 may instruct state machine 4500 to cause changes in the DC offset voltage acquisition time constant at each diversity antenna transition. For example, a change to a short time constant may be inserted at a diversity antenna transition, for a duration of 1 μS, 2 μS, or 4 μS, for instance. In another example, a setting for diversity signal 4505 may instruct state machine 4500 to use WC signal 4106 to control the DC offset voltage acquisition time constant, such that changes between short, medium, and long time constants may occur as necessary. These changes may be implemented by the addition/modification of states in state diagrams 4600 and/or 4700. The invention is intended and adapted to include such alternate embodiments.
5. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

## Claims

1. An apparatus for reducing a DC offset voltage in a receiver channel of a communication channel, comprising:
a summer that receives a receiver channel signal;
a storage element coupled to said summer; and
a switch coupled in series between a node of the receiver channel and said storage element;
wherein said switch receives a control signal, wherein said storage element stores an offset voltage during a time period when said control signal causes said switch to close; and
wherein said receiver channel signal is substantially nulled during said time period.

2. The apparatus of claim 1, wherein the communication channel is a wireless local area network (WLAN) receiver channel.

3. The apparatus of claim 1, wherein said storage element includes a capacitor.

4. The apparatus of claim 1, wherein the DC offset voltage is present in said receiver channel signal, wherein said DC offset voltage is stored in said storage element, wherein said stored DC offset voltage is subtracted from said receiver channel signal at said summer.

5. The apparatus of claim 1, further comprising:
at least one amplifier coupled in the receiver channel between said summer and said node.

6. The apparatus of claim 5, wherein a first amplifier of said at least one amplifier comprises an automatic gain control (AGC) amplifier.

7. The apparatus of claim 3, wherein an amplifier is coupled in series with said switch between said node and said storage element, wherein said amplifier is configured in an inverting configuration.

8. The apparatus of claim 1, wherein said receiver channel signal is substantially nulled at least in part by reducing a gain setting of an AGC amplifier that precedes the summer in the receiver channel during said time period.

9. The apparatus of claim 8, wherein said gain setting is reduced to be substantially equal to zero during said time period.

10. The apparatus of claim 1, wherein a second control signal coupled to a down-converter module is set to inactive during said time period.

11. The apparatus of claim 10, wherein said down-converter module includes a frequency down-conversion module, wherein said frequency down-conversion module includes a second switch and a second storage element, wherein said second control signal is coupled to said second switch.

12. The apparatus of claim 1, wherein a path from said summer, to said node, to said switch, to said storage element, and back to said summer, does not include an adjustable baseband amplifier.

13. The apparatus of claim 12, further comprising a baseband amplifier downstream from said path.

14. The apparatus of claim 1, further comprising:
an adjustable RF amplifier coupled to said communication channel; and
an adjustable baseband amplifier coupled to said communication channel;
wherein said adjustable RF amplifier has a rate of adjustment that is greater than a rate of adjustment of said adjustable baseband amplifier.

15. The apparatus of claim 1, wherein said node of the receiver channel is downstream from said summer in the receiver channel.

16. An apparatus for reducing DC offset in a communication channel, comprising:
a differential output amplifier that has an inverting output and a non-inverting output;
a first storage element that has a first terminal coupled to a non-inverting input of said differential output amplifier, wherein said first storage element has a second terminal that receives a first receiver channel signal;
a first switch coupled between said non-inverting input and said inverting output;
a second storage element that has a first terminal coupled to an inverting input of said differential output amplifier, wherein said second storage element has a second terminal that receives a second receiver channel signal; and
a second switch coupled between said inverting input and said non-inverting output.

17. The apparatus of claim 16, wherein the communication channel is a wireless local area network (WLAN) receiver channel.

18. The apparatus of claim 16, wherein said amplifier is an automatic gain control amplifier.

19. The apparatus of claim 16, wherein said first and second storage elements each include a capacitor.

20. The apparatus of claim 16, wherein said first and second switches receive at least one control signal, wherein said first and second storage elements each store an offset voltage during a time period when said at least one control signal causes said first and second switches to close.

21. The apparatus of claim 20, wherein said first and second receiver channel signals form a differential receiver channel signal, wherein said differential receiver channel signal is substantially nulled during said time period.

22. The apparatus of claim 21, wherein a gain setting of an AGC amplifier that precedes said differential output amplifier in a receiver channel is reduced during said time period.

23. The apparatus of claim 22, wherein said gain setting is reduced to be substantially equal to zero during said time period.

24. The apparatus of claim 21, wherein a second control signal coupled to a down-converter module that precedes said differential output amplifier in a receiver channel is set to inactive during said time period.

25. The apparatus of claim 24, wherein said down-converter module includes a differential frequency down-conversion module.

26. The apparatus of claim 25, wherein said differential module includes
a third storage element;
a fourth storage element; and
a third switch coupled between said third and fourth storage elements;
wherein said second control signal is coupled to said third switch.

27. A method for reducing DC offset in a communication channel, comprising the steps of:
(1a) substantially nulling a receiver channel signal;
(1) receiving a charge from a first node of a receiver channel;
(2) storing the charge;
(3) de-coupling the stored charge from the first node; and
(4) summing at a second node in the receiver channel a voltage that corresponds to the stored charge with the receiver channel signal, wherein the first node is downstream from the second node in the receiver channel.

28. The method of claim 27, wherein the communication channel is a wireless local area network (WLAN) receiver channel.

29. The method of claim 27, wherein step (2) comprises the step of:
storing the charge in a capacitor.

30. The method of claim 29, further comprising the step of:
coupling a switch between the first node and the capacitor.

31. The method of claim 27, further comprising the step of:
(5) coupling at least one amplifier in the receiver channel between the first and second nodes.

32. The method of claim 31, wherein step (5) comprises the step of:
coupling an automatic gain control (AGC) amplifier in the receiver channel between the first and second nodes.

33. The method of claim 27, wherein step (1a) comprises the step of:
(a) reducing a gain setting of an AGC amplifier that precedes the second node in the receiver channel.

34. The method of claim 33, wherein step (a) comprises the step of:
reducing the gain setting to be substantially equal to zero.

35. The method of claim 34, wherein step (2) comprises the step of:
storing a charge proportional to a measured DC offset voltage in a storage element.

36. The method of claim 35, wherein step (4) comprises the step of:
subtracting a voltage signal corresponding to the stored charge from the receiver channel signal at the second node.

37. The method of claim 35, wherein step (3) comprises:
decoupling the storage element from the first node after step (1) is substantially complete.

38. The method of claim 27, wherein the second node is preceded by a down-converter module, wherein step (1a) comprises the step of:
(i) setting a control signal coupled to a down-converter module to inactive.

39. The method of claim 38, wherein the down-converter module includes a switch and a storage element, wherein the control signal is coupled to the switch, wherein step (i) comprises the step of:
setting the control signal coupled to the switch to inactive.

40. An apparatus for reducing a DC offset voltage in a communication channel, comprising:
a summing node in a receiver channel that receives as a first input a receiver channel signal;
a storage element coupled as a second input to said summing node;
a switch coupled between an output node of the receiver channel and said storage element;
an adjustable RF amplifier coupled to said communication channel; and
an adjustable baseband amplifier coupled to said communication channel;
wherein said adjustable RF amplifier has a rate of adjustment that is greater than a rate of adjustment of said adjustable baseband amplifier.