# Patent

## Title
Fractional-Bit Systems

## Abstract

The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application relates to a first provisional application Ser. No. 60/559,683, Filed Apr. 4, 2004 and a second provisional application Ser. No. 60/594,141, Filed Mar. 14, 2005.


SYMBOLS USED IN THE SPECIFICATION
N—states-per-cell, i.e. number of possible states per cell, a positive integer;
m—word-width, i.e. number of cells in a word, a positive integer;
n—the maximum number of binary bits that can be represented by m N-ary cells, a positive integer;
b—bits-per-cell, i.e. average number of bits represented by each cell, could be a non-integer;
β—efficiency of N-ary fractional-bit system.
BACKGROUND
1. Technical Field of the Invention
The present invention relates to the field of electronic systems, more particularly to data storage and transmission systems.
2. Prior Arts
Multi-level memory cell can be used to improve the storage density. A multi-level cell (e.g. an N-level flash cell) can store and represent more than two states, e.g. by having N (sates-per-cell, N>2) Vt (threshold voltage) levels. In a conventional multi-level flash, b (bits-per-cell) is an integer. Accordingly, after successfully putting the flash with 2-bit cell into mass production, the industry immediately starts to develop 3-bit cell and 4-bit cell. Although migrating b from 1 to 2 might be easy (N increases from 2 to 4—a difference of 2), from 2 to 3 or even 4 proves quite difficult. This is because, after b=2, each single-step increment of b involves significant increase of N: for example, for b=3, N becomes 23 (=8), which is 4 levels more than b=2; for b=4, N becomes 24 (=16), or 8 levels more than b=3. For a given total Vt window (TVW, e.g. 1.5V–6V), this significant increase of N will dramatically reduce the allowed Vt distribution width (for each Vt level) and their separation gap. For example, for b=2, the Vt distribution width can be 0.5V with a separation gap as large as 1.0V (FIG. 1A); for b=3, the Vt distribution width is more than halved to 0.2V with a separation gap of 0.4V (FIG. 1B); for b=4, the Vt distribution width becomes as small as 0.1V with a separation gap of 0.2V (FIG. 1C). To achieve these numbers, it may incur considerable research and development cost, and lost time-to-market. Accordingly, the present invention discloses a fraction-bit storage system. It abandons the conventional approach of incrementing b by 1, but allows increments of N by as little as 1 between product generations. This concept can be readily extended to other data storage and transmission systems.
OBJECTS AND ADVANTAGES
It is a principle object of the present invention to improve the storage density of a storage system.
It is a further object of the present invention to optimize the storage density of a fractional-bit storage system.
It is a further object of the present invention to improve the transmission bandwidth of a transmission system.
In accordance with these and other objects of the present invention, fractional-bit systems are disclosed.
SUMMARY OF THE INVENTION
In an N-ary system, each cell has N possible states (N—states-per-cell, a positive integer). Physical attributes that may be used to represent the states include threshold voltage, charge, current, voltage, resistance, optical transmission or reflection, thermal conductance, electrical field, magnetic field, etc. N-ary system includes N-ary storage and N-ary transmission. N-ary storage is also referred to as multi-level storage (e.g. multi-level flash) or multi-valued storage. On the other hand, in an N-ary transmission, a cell is the input in a clock cycle.
It has been realized that the conventional approach of incrementing b by 1 between product generations has become impractical. It is a more practical approach to increment b by just a fraction of 1 between product generations. This smaller incremental step enables a more relaxed and more realistic product roadmap. Accordingly, the present invention abandons the conventional approach of incrementing b by 1, but allows increments of N by as little as 1 between product generations. For example, after b=2 (N=4), instead of directly going to b=3 (N=8), the next product generation to develop is N=5, 6, 7 . . . Because N is not an integral power of 2 and b takes a fractional value (i.e. is a non-integer), this N-ary system is referred to as fractional-bit system. From the discussion in the “Prior Arts” section, fractional-bit system is particularly advantageous when b>2.
In a conventional integer-bit system, cell is decoded individually. However, this approach is inefficient for a fractional-bit system (FIG. 4). Thus, in a fractional-bit system, a plurality of cells are decoded collectively—in unit of word. Each word comprises m N-ary cells (m—word-width, m≧2 is a positive integer). In fact, this decoding process simply converts a number from an N-ary representation to a binary representation. Preferably, each cell is first read out to a cell-coding block and converted into j bits. Because these j bits represent more states (2j) than the cell states (N), they are referred to as binary-like code. Examples of binary-like code include thermometer code (FIGS. 6A–6C, Table 3A) and quasi-binary code (FIGS. 7A–7B, Table 3B). After being processed by the cell-coding blocks, binary-like codes from m cells are then collectively fed into an N-ary-to-binary encoder and converted into i binary bit, where

i≦INT[log2(Nm)]

(INT[x] is the largest integer smaller than x); its maximum value n is:

n=imax=INT[log2(Nm)]

(Table 1) and bits-per-cell b, i.e. average number of bits represented by each cell, is then:

b≡n/m=INT[log2(Nm)]/m

(FIG. 3), which takes a fractional value.

Because it occupies chip real estate, an N-ary-to-binary encoder is preferably shared by a plurality of words. An address decoder (or a mux) can be used to select one word from said plurality of words. An N-ary-to-binary encoder can be shared within a memory unit-array, between different unit-arrays, or even between different chips. It may be located on-chip, external to the memory chip or a combination thereof. An N-ary-to-binary encoder can be programmable. A preferred programmable N-ary-to-binary encoder is comprised of a general-purpose processor and a program. The processor may be shared with other system components, e.g. controller in flash memory or disc drives, thus lowering the system cost.
For a given N, b varies with m. For example, for N=6, when m=1, b=2, i.e. each 2 cells represent 4 bits; when m=2, b=2.5, i.e. each 2 cells represent 5 bits (FIG. 3). Thus, the m=2 grouping has a higher storage density than m=1, or a better efficiency. Accordingly, efficiency β of an N-ary system is defined as the ratio between b and its theoretical limit blimit,




  
    
      
        
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For a fractional N-ary system, because N is not an integral power of 2 and not all N-ary states are used during N-ary-to-binary encoding (see, for example, the last 4 rows of Table 3A), β does not reach 100% (FIG. 4). To ensure β≧90%, m needs to satisfy certain conditions, e.g. for N=5, m≧4; for N=6, m≧2; for N=7, m≧3 . . . (FIG. 4 and Table 2); β can be further improved by selecting m values so that β reaches a local maximum, e.g. for N=7, m preferably takes the values of 5, 10, 15, 20, 25, or 31 . . . (FIG. 4 and Table 2).

Fractional-bit storage can be applied to any storage system, e.g. semiconductor memories such as flash, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, variable-resistance memory such as phase-change memory or Ovonyx unified memory (OUM), mask-programmable memory, diode memory, antifuse memory and others, disc storages such as optical disc storage (e.g. CD, VCD, DVD) and magnetic disc storage (e.g. HDD), or other storage systems. The same concept can be readily extended to any transmission system.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A–1C illustrate the Vt distribution of 4-ary (b=2), 8-ary (b=3), 16-ary (b=4) flash cells, respectively (prior arts);
FIG. 2A illustrates a basic N-ary fractional-bit parallel-input system; FIG. 2B illustrates a basic N-ary fractional-bit serial-input system;
Table 1 lists the maximum number of binary bits n that can be represented by m N-ary cells;
FIG. 3 illustrates bits-per-cell b vs. word-width m for various N values;
FIG. 4 illustrates efficiency β vs. word-width m for various N values;
Table 2 lists the m values that ensure: A) β≧90%; or, B) β reaches local maximum, for various N values;
FIG. 5 illustrates a preferred N-ary fractional-bit parallel-input system;
FIG. 6A is a symbol for a thermometer-coding block; FIG. 6B illustrates a first preferred thermometer-coding block; FIG. 6C illustrates a second preferred thermometer-coding block;
FIG. 7A illustrates a preferred quasibinary-coding block; FIG. 7B illustrates a preferred thermometer-quasibinary conversion block;
FIG. 8 illustrates a preferred N-ary fractional-bit serial-input system;
FIG. 9A illustrates a first preferred 6×2-to-2×5 encoder; Table 3A is a preferred truth table for said first encoder; FIG. 9B illustrates a second preferred 6×2-to-2×5 encoder; Table 3B is a preferred truth table for said second encoder; FIG. 9C illustrates a third preferred programmable N-ary-to-binary encoder;
FIG. 10 illustrates a preferred N-ary fractional-bit memory unit-array.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.
FIG. 2A illustrates a basic N-ary fractional-bit parallel-input system. In a parallel-input system, a plurality of cells are accessed in parallel. Typical parallel-input system is semiconductor memory (e.g. flash, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, variable-resistance memory such as phase-change memory or Ovonyx unified memory (OUM), mask-programmable memory, diode memory, antifuse memory, etc.) Semiconductor memory is array-based and easy to provide parallel access. The N-ary fractional-bit parallel-input system in FIG. 2A is comprised of a word 10 and an N-ary-to-binary encoder 100. The word 10 comprises m N-ary cells 10a, 10b . . . 10m, with each cell having N possible states (the expression N×m in FIG. 2A means m N-ary cells or signals). Physical attributes that may be used to represent the states include threshold voltage, charge, current, resistance, voltage, optical transmission or reflection, thermal conductance, electrical field, magnetic field, etc. The read-outs 12a, 12b . . . 12m of these cells are fed into the N-ary-to-binary encoder 100 in parallel and converted into binary outputs 18 with i (i is a positive integer) bits (including 18a, 18b . . . 18i).
FIG. 2B illustrates a basic N-ary fractional-bit serial-input system. In a serial-input system, cells are accessed in series. Typical serial-input systems are disc storage (e.g. optical disc storage such as CD, VCD, DVD, magnetic disc storage such as HDD, etc.) and data transmission system. The N-ary fractional-bit serial-input system in FIG. 2B comprises a serial-to-parallel converter 30 and an N-ary-to-binary encoder 100. The input Vin 31 has N possible states. Inputs Vin 31 from m cells are collected by the serial-to-parallel converter 30 and converted into m parallel signals 32a, 32b . . . 32m. These signals are grouped into a word 32, fed into the N-ary-to-binary encoder 100 and converted into binary outputs 38 with i (i is a positive integer) bits (including 38a, 38b . . . 38i). It should be apparent to those skilled in the art, for a system that is a combination of parallel-input and serial-input systems, it can be implemented by combining designs in FIGS. 2A and 2B.
The essential function of the N-ary-to-binary encoder 100 is to convert a number from an N-ary representation to a binary representation. Based on N-ary logic, the number of binary bits i that can be represented by a word of m N-ary cells should be:

i≦INT[log2(Nm)]

(INT[x] is the largest integer smaller than x), its maximum value n is:

n=imax=INT[log2(Nm)].

In this case, the N-ary-to-binary encoder 100 in FIGS. 2A and 2B is an N×m-to-2×n encoder, which means that m N-ary cells are converted in n binary bits. Table 1 lists the maximum number of binary bits n that can be represented by m N-ary cells. For example, for four 6-ary cells (i.e. N=6, m=4), n=10; in comparison, for the state-of-the-art four 4-ary (b=2) cells (i.e. N=4, m=4), n=8—a gain of 25%.

The present invention abandons the conventional approach of incrementing b by 1, but allows increments of N by as little as 1 between product generations. For example, after b=2 (N=4), instead of directly going to b=3 (N=8), the next product generation to develop is N=5, 6 . . . This approach demands a more relaxed development investment, while still providing steady improvement of storage density. It is particularly advantageous when b>2. Because N is not an integral power of 2, bits-per-cell b, i.e. average number of bits represented by each cell,

b≡n/m=INT[log2(Nm)]/m

takes a fractional value (i.e. a non-integer). FIG. 3 illustrates bits-per-cell b vs. word-width m for various N values.

For a given N, b varies with m. For example, for N=6, when m=1, b=2; when m=2, b=2.5 (FIG. 3). In other words, the m=2 grouping represents more bits for given number of cells than m=1, or a better efficiency. Accordingly, efficiency β is defined as the ratio between b and its theoretical limit blimit,




  
    
      
        
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FIG. 4 illustrates efficiency β vs. word-width m for various N values. From FIG. 4, when m=1, most N-ary fractional-bit systems have a low efficiency and therefore, single-cell decoding (which is used in conventional integer-bit systems) is not suitable for a fractional-bit system. In a fractional N-ary system, because N is not an integral power of 2 and not all N-ary states are used during N-ary-to-binary encoding (see, for example, the last 4 rows of Table 3A), β does not reach 100% (FIG. 4). To ensure β≧90%, m needs to satisfy certain conditions: for N=5, m≧4; for N=6, m≧2; for N=7, m≧3 . . . (Table 2); β can be further improved by selecting m values so that β reaches a local maximum, e.g. for N=7, m preferably takes the values of 5, 10, 15, 20, 25, or 31 . . . (Table 2).

FIG. 5 illustrates a preferred N-ary fractional-bit parallel-input system. Each N-ary cell (e.g. 10a) is connected with a cell-coding block (e.g. 14a). Preferably, each cell (e.g. 10a) is first read out to a cell-coding block (e.g. 14a) and converted into j bits (e.g. 12a). Because these j bits 12a represent more states (2j) than the cell states (N), they are referred to as binary-like code. Examples of binary-like code include thermometer code (FIGS. 6A–6C, Table 3A) and quasi-binary code (FIGS. 7A–7B, Table 3B). Thermometer code uses j=N-1 binary bits to represent N states, while quasi-binary code uses j=k={INT[log2(N)]+1} binary bits to represent N states.
FIG. 6A is a symbol for a thermometer-coding block 21. Its input(s) 11a is a read-out of the cell 10a; its output(s) 12a is a thermometer code (to be explained below). FIG. 6B illustrates a first preferred thermometer-coding block 14a. It is comprised of a sense-amp 13a and N−1 latches 16a1, 16a2 . . . 16a(N-1). In this preferred embodiment, cell 10a is a N-level flash cell with N Vt levels (e.g. Vt,1<Vt,2<Vt,3< . . . <Vt,N). Its state can be read out in N-1 read cycles. During each read cycle, a read voltage VR is applied to the word line 11x: if it is larger than Vt, the bit line 11a is pulled down and the sense-amp 13a outputs an “0”; if it is smaller than Vt, the bit line 11a stays high and the sense-amp 13a outputs an “1”. VR's are applied in the following order: VR,(N-1) . . . VR,2, VR,1 (with Vt,N>VR,(N-1)>Vt,N-1> . . . >Vt,3>VR,2>Vt,2>VR,1>Vt,1). The latches 16a1, 16a2 . . . 16a(N-1) forms a shift register, which is controlled by read-cycle signal 17. After N-1 read cycles, the outputs of these latches 12a (including 12a1, 12a2 . . . 12a(N-1)) form a thermometer code. For example, for N=5, if Vt of the cell is Vt,3, the outputs 12a are: 0 (12a4), 0 (12a3), 1 (12a2), 1 (12a1); if Vt is Vt,5, the outputs 12a are: 1 (12a4), 1 (12a3), 1 (12a2), 1 (12a1) (see Table 3A for more examples). Because these outputs 12a look similar to a thermometer where the mercury column always rises to the appropriate temperature and no mercury is present above that temperature, this coding scheme is named as thermometer code.
FIG. 6C illustrates a second preferred thermometer-coding block 14a. It adopts a flash ADC architecture and is comprised of N-1 comparators 15a1, 15a2 . . . 15a(N-1). In this preferred embodiment, cell 10a is viewed as a resistor during read with N possible resistance values. Hence, its bit-line voltage 19 has N possible voltage values (e.g. Vb,1<Vb,2<Vb,3< . . . <Vb,N). The reference voltages of the comparators Vref,1, Vref,2 . . . Vref,(N-1) are selected in such a way that Vb,1<Vref,1<Vb,2<Vref,2<Vb,3, . . . <Vb,(N-1)<Vref,(N-1)<Vb,N. During read-out, the bit-line voltage 19 is compared with all reference voltages Vref,1, Vref,2 . . . at the same time. The resultant outputs 12a are also a thermometer code.
Besides thermometer code, quasi-binary code may also be used. Quasi-binary code could have the same value as the conventional binary code (see Table 3B for examples). In general, it needs fewer bits to represent the same N states than the thermometer code. FIG. 7A illustrates a preferred quasibinary-coding block 14a. It is comprised of a thermometer-coding block 21 (as in FIGS. 6A–6C) and a thermometer-quasibinary converter 23. The thermometer-quasibinary converter 23 converts thermometer code 25a (with N-1 bits) into quasi-binary code 12a (with k bits). FIG. 7B illustrates a preferred thermometer-quasibinary converter 23. It is a 2k-to-k priority encoder 25, which is commonly used in the flash ADC architecture. Because 2k>N, only a fraction 25a of its inputs (N-1 out of a total number of 2k signal lines) are used.
FIG. 8 illustrates a preferred N-ary fractional-bit serial-input system. Compared with FIG. 2B, it further comprises a cell-coding block 34 between the input 31 and the serial-to-parallel converter 30. The cell-coding block 34 reads out the state of the serial input Vin 31 and generates a binary-like code 33 with j bit: for thermometer code, j=N-1; for quasi-binary code, j=k=INT[log2(N)]+1. Preferably, the serial-to-parallel converter 30 uses a serial-to-parallel shift register. Its operation should be apparent to those skilled in the art.
FIG. 9A illustrates a first preferred 6×2-to-2×5 encoder 102. It converts two 6-ary inputs 12a (A) and 12b (B) into one 5-bit output 18 (C). Its inputs A, B are thermometer codes, i.e. they use 5 (=6-1) signals (12a1, 12a2 . . . 12a5, i.e. A1, A2 . . . A5; or, 12b1, 12b2 . . . 12b5, i.e. B1, B2 . . . B5) to represent one 6-ary state. Table 3A lists a preferred truth table for the first preferred encoder. For example, for A=1, B=4, the thermometer codes are “00001” and “01111”, the output is C=146=10=010102 (the subscript “6” means it is a 6-ary number; no subscript means 10-ary). Note that two 6-ary signals can represent 62(=36) states, while five binary signals can represent 25(=32) states. As a result, there are 4 un-used states for the encoder (see the last four rows of Table 3A).
FIG. 9B illustrates a second preferred 6×2-to-2×5 encoder 102. Its inputs A, B are quasi-binary codes, i.e. they use 3 (=INT[log2(6)]+1) signals (12a1, 12a2, 12a3, i.e. A1, A2, A3; or, 12b1, 12b2, 12b3, i.e. B1, B2, B3) to represent one 6-ary state. Table 3B lists a preferred truth table for the second preferred encoder. For example, for A=1, B=4, the quasi-binary codes are “001” and “100”, the output, based on 6-ary logic, is C=146=10=010102.
The preferred N-ary-to-binary encoders in FIGS. 9A–9B are hard-wired for a specific N. These methods are referred to as hard-encoding. Soft-encoding, i.e. using a software means to convert N-ary to binary, may also be implemented. Accordingly, a programmable N-ary-to-binary encoder 102 is disclosed in the present invention. As is illustrated in FIG. 9C, it is comprised of a general-purpose processor 104 and a program 106. The program 106 (e.g. a software or a firmware) is written in such a way that the preferred truth table in Table 3A (or 3B) can be realized. For different N's, different programs 106 are loaded into the processor 104 to carry out different N-ary-to-binary encodings. The programmable N-ary-to-binary encoder 102 may be located on-chip, or off-chip (i.e. encoding is performed at the system level). It may share the processor with other system components, e.g. controller in flash memory or disc drives, thus lowering the system cost.
FIG. 10 illustrates a preferred N-ary memory unit-array 50. Its bit lines are divided into a plurality of words 52A, 52B . . . 52X (with each word comprising m bit lines). Based on the column address 53, the column address-decoder 51 selects one word 54S from these words. The selected word 54S is fed into the cell-coding blocks 14a, 14b . . . 14m, then to the N×m-to-2×n encoder 100 and converted into binary output 18 (n bits). Because N×m-to-2×n encoder 100 is located after the column address-decoder 51, it can be shared by a plurality of words in this unit-array 50. This can help reduce the chip area. In fact, an N-ary-to-binary encoder can be shared between different unit-arrays, or even between different chips. It may be located on-chip, external to the memory chip or a combination thereof.
While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that may more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.

## Claims

1. An N-ary fractional-bit system, comprising:
a first word and a second word, each comprising m N-ary cells, each N-ary cell having N possible states, where m is an integer representing the number of cells in a word and N is an integer representing the number of possible states for each cell;
means for selecting a word from said first and second words; and
an N-ary-to-binary encoder for converting said selected word into i binary bits, where i is an integer representing the number of binary outputs from said encoder and has a maximum value of n=INT[log2(Nm)], with INT[x] representing the largest integer smaller than x;
whereby the average number of binary bits stored in each cell b is a non-integer and larger than 2.

2. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in a same unit-array.

3. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in different unit-arrays.

4. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in different chips.

5. The N-ary fractional-bit system according to claim 1, further comprising a plurality of cell-coding blocks for converting the read-out from each cell into a binary-like code.

6. The N-ary fractional-bit system according to claim 5, wherein said binary-like code is thermometer-code.

7. The N-ary fractional-bit system according to claim 5, wherein said binary-like code is quasibinary-code.

8. The N-ary fractional-bit system according to claim 1, wherein efficiency β=INT[log2(Nm)]/log2(Nm)≧90%.

9. The N-ary fractional-bit system according to claim 8, wherein:
A) for N=5, m≧4;
B) for N=7, 11 or 15, m≧3;
C) for N=6, 12, 13 or 14, m≧2; or
D) for N=9 or 10, m≧1.

10. The N-ary fractional-bit system according to claim 1, wherein efficiency β=INT[log2(Nm)]/log2(Nm) reaches a local maximum.

11. The N-ary fractional-bit system according to claim 10, wherein:
A) for N=5, m=4, 7, 10, 13, 16, 19, 22, 25, 28 or 32;
B) for N=6, m=2, 4, 7, 9, 12, 14, 16, 19, 21, 24, 26, 28 or 31;
C) for N=7, m=5, 10, 15, 20, 25 or 31;
D) for N=9, m=6, 12, 18, 24 or 30;
E) for N=10, m=4, 7, 10, 13, 16, 19, 22, 25 or 28;
F) for N=11, m=3, 5, 7, 9, 11, 14, 16, 18, 20, 22, 24, 27, 29 or 31;
G) for N=12, m=2, 4, 7, 9, 12, 14, 16, 19, 21, 24, 26, 28 or 31;
H) for N=13, m=3, 6, 10, 13, 16, 20, 23, 26 or 30;
I) for N=14, m=5, 10, 15, 20, 25 or 31; or
J) for N=15, m=10, 21 or 32.

12. The N-ary fractional-bit system according to claim 1, wherein said system is a parallel-input system.

13. The N-ary fractional-bit system according to claim 12, wherein said cells are semiconductor memory cells.

14. The N-ary fractional-bit system according to claim 13, wherein said semiconductor memory is selected from a group of semiconductor memories including flash, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, variable-resistance memory, phase-change memory, Ovonyx unified memory, mask-programmable memory, diode memory, and antifuse memory.

15. The N-ary fractional-bit system according to claim 1, wherein said system is a serial-input system and further comprises a serial-to-parallel converting means.

16. The N-ary fractional-bit system according to claim 15, wherein said serial-input system is a disc drive.

17. The N-ary fractional-bit system according to claim 16, wherein said disc is selected from a group of disc storages including optical disc storage and magnetic disc storage.

18. The N-ary fractional-bit system according to claim 1, wherein said encoder is located in a same chip as said cells or a different chip from said cells.

19. The N-ary fractional-bit system according to claim 1, wherein said encoder is a programmable encoder.

20. The N-ary fractional-bit system according to claim 19, further comprising a processor or a program.