# Patent

## Title
Method to control three-phase inverter voltage

## Abstract

A method is provided to control the output voltage across an unbalanced load connected to a three-phase inverter, The method includes transformation of a set of three-phase voltage signals to a dq-coordinate system. Based on the transformation, a set of d-axis and a set of q-axis positive, negative and a set of zero sequence signals are generated. The method includes phase shifting of each of the zero sequence signals to generate 120 degrees and 240 degrees phase shifted zero sequence signals. Each of the zero sequence signals, the 120 degrees and the 240 degrees phase shifted zero sequence signals are transformed to a set of d-axis and q-axis zero sequence signals. A set of error signals, calculated based on the set of d-axis and q-axis zero, positive and negative sequence signals, are minimized and transformed to abc-coordinate system to obtain a three-phase control voltage signal.

## Background
TECHNICAL FIELD
The present disclosure relates to a three-phase inverter connected to a load. More particularly, the present disclosure relates to a method for controlling an output voltage across the load fed by the three-phase inverter.
BACKGROUND
A three-phase inverter supplying a load, especially in application areas such as, an uninterruptable power supply (UPS) is known in the art. If the load is balanced, a variety of control methods may be utilized to regulate a three-phase output voltage of the three-phase inverter. For example, the three-phase output voltage of the three-phase inverter supplying a balanced load may be regulated by use of one or more stationary frame proportional-integral (PI) controllers.
However, it is difficult to regulate the three-phase output voltage of the three-phase inverter by use of the one or more stationary frame PI controllers, when the three-phase inverter is supplying an unbalanced load. This is because the integral pails in atypical stationary frame PI controller are not able to compensate the effect of the unbalanced load. For example, the three-phase output voltage of the three-phase inverter across the unbalanced load is unbalanced due to undesired negative and zero sequence components of the three-phase output voltage. The negative sequence component is a stable component that can be eliminated by using the stationary frame PI controller. However, the stationary frame PI controller cannot eliminate the zero sequence component since it is a variable component. Thus, eliminating the zero sequence component in the three-phase output voltage of the three-phase inverter is difficult by using the stationary frame PI controller.
U.S. Pat. No. 5,883,796 discloses a method and apparatus for the dynamic series voltage restoration for sensitive loads in unbalanced power systems. is a recovery system for the unbalanced loads generated by faults in an existing balanced load system. This system introduce a compensator inverter that generates an inverter voltage signal in series with the power transmission line, which restores the positive sequence load voltage component to pre-fault conditions, and which cancels the negative and the zero sequence components of the load voltage signal. This system does not provide solution for the scenario where the three-phase inverter is feeding the unbalanced load.
Given description covers one or more problems existing in the art and discloses a method to solve the problem(s).
SUMMARY OF THE DISCLOSURE
In an aspect of the present disclosure, a method to control a three-phase output voltage of a three-phase inverter connected to a three-phase load is provided. The method includes transforming, by use of a controller, a three-phase command voltage signal to a dq-coordinate system in order to generate ad-axis and a q-axis positive sequence command signals, a d-axis and a q-axis negative sequence command signals, and a zero sequence command signal. The method further includes transforming, by use of the controller, a three-phase feedback voltage signal to the dq-coordinate system in order to generate a d-axis and a q-axis positive sequence feedback signals, a d-axis and a q-axis negative sequence feedback signals, and a zero sequence feedback signal. The method further includes phase shifting, by use of the controller, the zero sequence command signal to generate a 120 degrees phase shifted zero sequence command signal and a 240 degrees phase shifted zero sequence command signal. Similarly, the method further includes phase shifting, by use of the controller, the zero sequence feedback signal to generate a 120 degrees phase shifted zero sequence feedback signal and a 240 degrees phase shifted zero sequence feedback signal. The method further includes transforming, by use of the controller, the zero sequence command signal, the 120 degrees phase shifted zero sequence command signal, and the 240 degrees phase shifted zero sequence command signal to the dq-coordinate system in order to generate ad-axis and a q-axis zero sequence command signals. Similarly, the method further includes transforming, by use of the controller, the zero sequence feedback signal, the 120 degrees phase shifted zero sequence feedback signal, and the 240 degrees phase shifted zero sequence feedback signal to the dq-coordinate system in order to generate ad-axis and a q-axis zero sequence feedback signals. The method further includes generating, by use of -the controller, a set of positive sequence control signals based on the d-axis and the q-axis positive sequence command and feedback signals. Similarly, the method further includes generating, by use of the controller, a set of negative sequence control signals based on the d-axis and the q-axis negative sequence command and feedback signals. The method further includes generating, by use of the controller, a set of zero sequence control signals based on the d-axis and the q-axis zero sequence command and feedback signals. The method further includes transforming, by use of the controller, the set of positive sequence control signals, the set of negative sequence control signals, and the set of zero sequence control signals from the dq-coordinate system to an abc-coordinate system. This transformation from the dq-coordinate system to the abc-coordinate system generates a three-phase positive sequence control signal, a three-phase negative sequence control signal, and a three-phase zero sequence control signal. The method further includes combining, by use of the controller, the respective abc-coordinates of the three-phase positive sequence control signals, the three-phase negative sequence control signals, and the three-phase zero sequence control signal to generate a balanced three-phase control voltage signal for controlling the three-phase output voltage of the three-phase inverter.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram that illustrates a system to control an output voltage across a load being fed by a three-phase inverter, in accordance with an embodiment of the present disclosure;
FIG. 2 is a block diagram that illustrates a controller to control a three-phase output voltage across the load being fed by the three-phase inverter, in accordance with an embodiment of the present disclosure; and
FIG. 3 is a flow chart that illustrates a method for controlling the three-phase output voltage across the load being fed by the three-phase inverter, in accordance with an embodiment of the present disclosure.



DETAILED DESCRIPTION
Referring to FIG, 1, a system 10 to control an output voltage across a load being fed by an inverter is illustrated. The system 10 includes a three-phase inverter 12, a load 14, and a controller 16. The three-phase inverter 12 is connected to the load 14 and the controller 16. The controller 16 is configured to control the three-phase inverter 12 such that a balanced three-phase output voltage is maintained across the load 14.
The three-phase inverter 12 is a commonly known three-phase power converter that may facilitate conversion of a. direct current (DC) voltage into an alternating current (AC) voltage, The three-phase inverter 12 may be realized by use of one or more suitable logics, circuitries, interfaces, and/or codes. More specifically, the three-phase inverter 12 includes three single-phase inverter switches (not shown in the figure), Further, each of the three single-phase inverter switches is coordinated to generate a three-phase output voltage.
A person having ordinary skills in the art will understand that the scope of the disclosure is not limited to the realization of the three-phase inverter 12 with the three single-phase inverter switches only, The three-phase inverter 12 may include more than three single-phase inverter switches. For example, the three-phase inverter 12 may include a fourth single-phase inverter switch (not shown in the figure). The fourth single-phase inverter switch may be connected to the three-phase load 14.
Further, each of the three single-phase inverter switches is connected to the load 14. In an embodiment, the load 14 may correspond to at least one of a single-phase load, a two-phase load, a three-phase load, or a combination thereof. Furthermore, the load 14 may correspond to an unbalanced load. The load 14 may include a varying impedance in each of the three phases. In a scenario where a load is connected to the three-phase inverter 12, a line phase of the load 14 draws a line current, from a respective phase of the three-phase inverter 12, which is different (in terms of magnitude and/or phase angle) from remaining line phases of the load 14. When the load 14 is unbalanced, the output voltage of the three-phase inverter 12 may not stay at a fixed value. The controller 16 controls the switching operation of the three-phase inverter 12 to maintain the balanced three-phase output voltage across the load 14.
The controller 16 may include one or more suitable logics, circuitries, interfaces, and/or codes that may be configured to execute a set of instructions to control the switching operation of the three-phase inverter 12. More specifically, the controller 16 includes one or more microprocessors, such as a microprocessor 18, one or more memories, such as a memory 20, one or more transceivers, such as a transceiver 22, one or more abc-to-dq0 transformers, such as an abc-to-dq0 transformer 24, one or more dq0-to-abc transformers, such as a dq0-to-abc transformer 25, one or more Proportional Integral (PI) controller units, such as a PI controller unit 26, and one or more phase shifter units, such as a phase shifter unit 28. Further, each of the microprocessor 18, the memory 20, the transceiver 22, the abc-to-dq0 transformer 24, the dq0-to-abc transformer 25, the PI controller unit 26, and the phase shifter unit 28 may be realized by use of one or more suitable logics, circuitries, interfaces, and/or codes that may he configured to execute a set of instructions to perform one or more associated operations.
FIG. 2 shows a schematic view of the controller 16. The controller 16 is configured to control the three-phase output voltage across the load 14 that is being fed by the three-phase inverter 12. Hereinafter, the load 14 has been referred to as the unbalanced load 14. The unbalanced load 14 may be realized by use of at least one of one or more single-phase loads, one or more two-phase loads, a three-phase load, or a combination thereof.
In a scenario where the three-phase inverter 12 is supplying the unbalanced load 14, the transceiver 22 receives a three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) from one or more sensors (not shown in the figures) connected across the unbalanced load 14. The three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) may be transmitted to the transceiver 22 via a set of capacitors (not shown in figures). The transceiver 22 further receives a three-phase command voltage signal (denoted by Vacmd, Vbcmd and Vccmd) from a signal generator (not shown in the figures). The signal generator may be operable to generate the three-phase command voltage signal (denoted by Vacmd, Vbcmd Vccmd) from one or more reference voltage signals. Further, the transceiver 22 may store the three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) and the three-phase command voltage signal (denoted by Vacmd, Vbcmd Vccmd) in the memory 20.
Further, the abc-to-dq0 transformer 24 is operable to transform the three-phase command voltage signal (denoted by Vacmd, Vbcmd Vccmd) to a dq-coordinate system. More specifically, in the dq-coordinate system, the abc-to-dq0 transformer 24 generates a d-axis and a q-axis positive sequence command signals (denoted by Vdcmd+ and Vqcmd+, respectively), a d-axis and a q-axis negative sequence command signals (denoted by Vdcmd− and Vqcmd−, respectively), and a zero sequence command signal (denoted by V0cmd+). Similarly, the abc-to-dq0 transformer 24 is operable to transform the three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) to the dq-coordinate system in order to generate a d-axis and a q-axis positive sequence feedback signals (denoted by Vdfdk+ and Vqfdk+, respectively), a d-axis and a q-axis negative sequence feedback signals (denoted by Vdfdk− and Vqfdk−, respectively), and a zero sequence feedback signal (denoted by V0fdk+).
Further, the phase shifter unit 28 may include one or more suitable logics, circuitries, interfaces, and/or codes that may be configured to execute a set of instructions to shift a phase of an input signal to generate a phase shifted output signal. More specifically, the phase shifter unit 28 is operable to shift the phase of the zero sequence command signal (denoted by V0cmd+) by 120 degrees to generate a 120 degrees phase shifted zero sequence command signal (denoted by V0/120cmd+). Similarly, the phase shifter unit 28 is operable to shift the phase of the zero sequence command signal (denoted by V0cmd+) by 240 degrees to generate a 240 degrees phase shifted zero sequence command signal (denoted by V0/240cmd+). The phase shifter unit 28 is further operable to shift the phase of the zero sequence feedback signal (denoted by V0fdk+) by 120 degrees to generate a 120 degrees phase shifted zero sequence feedback signal (denoted by V0/120fdk+). Similarly, the phase shifter unit 28 is operable to shift the phase of the zero sequence feedback signal (denoted by V0fdk+) by 240 degrees to generate a 240 degrees phase shifted zero sequence feedback signal (denoted by V0/240fdk+).
Thereafter, the abc-to-dq0 transformer 24 is operable to transform the zero sequence command signal (denoted by V0cmd+) the 120 degrees phase shifted zero sequence command signal (denoted by V0/120fdk+), and the 240 degrees phase shifted zero sequence command signal (denoted by V0/240fdk+) to the dq-coordinate system. More specifically, based on such transformation in the dq-coordinate system, the abc-to-dq0 transformer 24 generates a d-axis and a q-axis zero sequence command signals (denoted by Vd—0cmd+ and Vq—0cmd+, respectively). Similarly, the abc-to-dq0 transformer 24 transforms the zero sequence feedback signal (denoted by V0fdk+), the 120 degrees phase shifted zero sequence feedback signal (denoted by V0/120fdk+), and the 240 degrees phase shifted zero sequence feedback signal (denoted by V0/240fdk+) to the dq-coordinate system in order to generate a d-axis and a q-axis zero sequence feedback signals (denoted by Vd—0fdk+ and Vq—0fdk+, respectively).
The microprocessor 18 is operable to determine a set of error signals based on at least a plurality of signals. The set of error signals may be determined based on the plurality of signals from the d-axis and the q-axis positive sequence command signals (denoted by Vdcmd+ and Vqcmd+, respectively) and the d-axis and the q-axis positive sequence feedback signals (denoted by Vdfdk+ and Vqfdk+, respectively). Similarly, the set of error signals may be determined based on the d-axis and the q-axis negative sequence command signals (denoted by Vdcmd− and Vqcmd−, respectively), the d-axis and the q-axis negative sequence feedback signals (denoted by Vdfdk− and Vqfdk−, respectively). Similarly, the set of error signals may be determined based on the d-axis and the q-axis zero sequence command signals (denoted by Vd—0cmd+ and Vq—0cmd+, respectively), and the d-axis and the q-axis zero sequence feedback signals (denoted by Vd—0fdk+ and Vq—0fdk+, respectively).
More specifically, the set of error signals includes a first d-axis error signal (denoted by d1), a second d-axis error signal (denoted by d2), a third d-axis error signal (denoted by d3), a first q-axis error signal (denoted by q1), a second q-axis error signal (denoted by q2), and a third q-axis error signal (denoted by q3). The microprocessor 18 may be operable to determine the first d-axis error signal (denoted by d1) based on the d-axis positive sequence command signal (denoted by Vdcmd+) and the d-axis positive sequence feedback signal (denoted by Vdfdk+). The microprocessor 18 may further be operable to determine the first q-axis error signal (denoted by q1) based on the q-axis positive sequence command signal (denoted by Vqcmd+) and the q-axis positive sequence feedback signal (denoted by Vqfdk+). The microprocessor 18 may further be operable to determine the second d-axis error signal (denoted by d2) based on the d-axis negative sequence command signal (denoted by and the d-axis negative sequence feedback signal (denoted by Vdcmd−), The microprocessor 18 may further be operable to determine, the second q-axis error signal (denoted by q2) based on the q-axis negative sequence command signal (denoted by Vqcmd−) and the q-axis negative sequence feedback signal (denoted by Vqcmd−). The microprocessor 18 may further be operable to determine the third d-axis error signal (denoted by d3) based on the d-axis zero sequence command signal (denoted by Vd—0cmd+) and the d-axis zero sequence feedback signal (denoted by Vdfdk−). The microprocessor 18 may further be operable to determine the third q-axis error signal (denoted by q3) based on the q-axis zero sequence command signal (denoted by Vq—0cmd+) and the q-axis zero sequence feedback signal (denoted by Vq—0fdk+).
After the determination of the set of error signals (denoted by d1, d2, d3, q1, q2 and q3), the PI controller unit 26 is operable to generate a set of positive sequence control signals (denoted by Cd+ and Cq+, a set of negative sequence control signals (denoted by Cd− and Cq−), and a set of zero sequence control signals (denoted by Cd0 and Cq0). The PI controller unit 26 is operable to generate the set of positive sequence control signals (denoted by Cd+ and Cq+) based on the first d-axis error signal (denoted by d1) and the first q-axis error signal (denoted by q1), respectively. Similarly, the PI controller unit 26 is operable to generate the set of negative sequence control signals (denoted by Cd− and Cq−) based on the second d-axis error signal (denoted by d2) and the second q-axis error signal (denoted by q3), respectively. Similarly, the PI controller unit 26 is operable to generate the set of zero sequence control signals (denoted by Cd0 and Cq0) based on the third d-axis error signal (denoted by d3) and the third q-axis error signal (denoted by q3), respectively. Thereafter, the microprocessor 18 may be operable to transmit each of the set of positive sequence control signals (denoted by Cd+ and Cq+), the set of negative sequence control signals (denoted by Cd− and Cq−)), and the set of zero sequence control signals (denoted by Cd0 and Cq0) to the dq0-to-abc transformer 25.
The dq0-to-abc transformer 25 is operable to transform each of the set of positive sequence control signals (denoted by Cd+ and Cq+), the set of negative sequence control signals (denoted by Cd− and Cq−), and the set of zero sequence control signals (denoted by Cd0 and Cq0) from the dq-coordinate system to the abc-coordinate system. Mote specifically, the dq0-to-abc transformer 25 is operable to transform the set of positive sequence control signals (denoted by Cd+ and Cq+) to generate a three-phase positive sequence control signal (denoted by Vinv_a+, Vinv_b+ and Vinv_c+). Similarly, the dq0-to-abc transformer 25 is operable to transform the set of negative sequence control signals (denoted by Cd− and Cq−) to generate a three-phase negative sequence control signal (denoted by Vinv_a−, Vinv_b− and Vinv_c−). Similarly, the dq0-to-abc transformer 25 is operable to transform the set of zero sequence control signals (denoted by Cd0 and Cq0) in order to generate a three-phase zero sequence control signal (denoted by Vinv0).
Thereafter, the microprocessor 18 is operable to combine the respective abc-coordinates of the three-phase positive sequence control signal (denoted by Vinv_a+, Vinv_b+ and Vinv_c+), the three-phase negative sequence control signal (denoted by Vinv_a−, Vinv_b− and Vinv_c−), and the three-phase zero sequence control signal (denoted by Vinv0). Based on at least the combination, the microprocessor 18 is operable to generate a balanced three-phase control voltage signal (denoted by Vinv_a, Vinv_b and Vinv_c). The microprocessor 18 is further operable to utilize the balanced three-phase control voltage signal (denoted by Vinv_a, Vinv_b and Vinv_c) to control the three-phase output voltage of the three-phase inverter 12 across the unbalanced load 14.
INDUSTRIAL APPLICABILITY
In operation, a disclosed method controls the three-phase output voltage across the load 14 being fed by the three-phase inverter 12. Referring to FIG. 3, there is shown a flow chart 30 for the disclosed method. The flow chart 30 is described in conjunction with FIG. 1 and FIG. 2. The method starts at step 32 and proceeds to step 34.
At step 34, the three-phase command voltage signal (denoted by Vacmd, Vbcmd and Vccmd) is transformed to the dq-coordinate system. In an embodiment, the controller 16 is operable to transform the three-phase command voltage signal (denoted by Vacmd, Vbcmd and Vccmd) to the dq-coordinate system. Based on the transformation, the controller 16 is operable to generate the d-axis and the q-axis positive sequence command signals (denoted by Vdcmd+ and Vqcmd+ respectively), the d-axis and the q-axis negative sequence command signals (denoted by Vdcmd− and Vqcmd−, respectively), and the zero sequence command signal (denoted by V0cmd+).
Similarly, at step 35, the three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) is transformed to the dq-coordinate system. In an embodiment, the controller 16 is operable to transform the three-phase feedback voltage signal (denoted by Vcap_afdk, Vcap_bfdk and Vcap_cfdk) to the dq-coordinate system. Based on the transformation, the controller 16 is operable to generate the d-axis and the q-axis positive sequence feedback signals (denoted by Vdfdk+ and Vqfdk+, respectively), the d-axis and the q-axis negative sequence feedback signals (denoted by Vdfdk− and Vqfdk−, respectively) and the zero sequence feedback signal (denoted by V0fdk+).
At step 36, the zero sequence command signal (denoted by V0cmd+) is phase shifted by each of 120 degrees and 240 degrees. In an embodiment, the controller 16 is operable to shift the phase of the zero sequence command signal (denoted by V0cmd+) by each of the 120 degrees and the 240 degrees. Based on the phase shifting, the controller 16 is operable to generate the 120 degrees phase shifted zero sequence command signal (denoted by V0/120cmd+) and the 240 degrees phase shifted zero sequence command signal (denoted by V0/240cmd+).
Similarly, at step 37, the zero sequence feedback signal (denoted by V0fdk+) is phase shifted by each of 120 degrees and 240 degrees. In an embodiment, the controller 16 is operable to shift the phase of the zero sequence feedback signal (denoted by V0fdk+) by each of the 120 degrees and the 240 degrees. Based on the phase shifting, the controller 16 is operable to generate the 120 degrees phase shifted zero sequence feedback signal (denoted by V0/120cmd+) and the 240 degrees phase shifted zero sequence feedback signal (denoted by V0/240cmd+).
At step 38, the zero sequence command signal (denoted by V0cmd+), the 120 degrees phase shifted zero sequence command signal (denoted by V0/120cmd+) and the 240 degrees phase shifted zero sequence command signal (denoted by V0/240cmd+) are transformed to the dq-coordinate system. In an embodiment, the controller 16 is operable to transform the zero sequence command signal (denoted by V0cmd+), the 120 degrees phase shifted zero sequence command signal (denoted by V0/120cmd+) and the 240 degrees phase shifted zero sequence command signal (denoted by V0/240cmd+) to the dq-coordinate system. Based on the transformation, the controller 16 is operable to generate the d-axis and the q-axis zero sequence command signals (denoted by Vd_0cmd+ and Vq_0cmd+, respectively).
Similarly, at step 39, the zero sequence feedback signal (denoted by V0fdk+ the 120 degrees phase shifted zero sequence feedback signal (denoted by V0/120fdk+) and the 240 degrees phase shifted zero sequence feedback signal (denoted by V0/240fdk+) are transformed to the dq-coordinate system. In an embodiment, the controller 16 is operable to transform the zero sequence feedback signal (denoted by V0fdk+) the 120 degrees phase shifted zero sequence feedback signal (denoted by V0/120fdk+) and the 240 degrees phase shifted zero sequence feedback signal (denoted by V0/240fdk+) to the dq-coordinate system. Based on the transformation, the controller 16 is operable to generate the d-axis and the q-axis zero sequence feedback signals (denoted by Vd_0fdk+ and Vq_0fdk+ respectively).
At step 40, the set of positive sequence control signals (denoted by Cd+ and Cq+) is generated, In an embodiment, the controller 16 is operable to generate the set of positive sequence control signals (denoted by Cd+ and Cq+). The controller 16 may generate the set of positive sequence control signals (denoted by Cd+ and Cq+), based on the d-axis and the q-axis positive sequence command signals (denoted by Vdcmd+ and Vdcmd+, respectively) and the d-axis and the q-axis positive sequence feedback signals (denoted by Vdfdk+ and Vdfdk+, respectively).
Similarly, at step 42, the set of negative sequence control signals (denoted by Cd− and Cq−) is generated. In an embodiment, the controller 16 is operable to generate the set of negative sequence control signals (denoted by Cd− and Cq−). The controller 16 may generate the set of negative sequence control signals (denoted by (Cd− and Cq−) based on the d-axis and the q-axis negative sequence command signals (denoted by Vdcmd− and Vdcmd−, respectively) and the d-axis and the q-axis negative sequence feedback signals (denoted by Vdfdk− and Vdfdk−, respectively).
Similarly, at step 44, the set of zero sequence control signals (denoted by Cd0  and Cq0) is generated. In an embodiment, the controller 16 is operable to generate the set of zero sequence control signals (denoted by Cd0 and Cq0). The controller 16 may generate the set of zero sequence control signals (denoted by Cd0 and Cq0) based on the d-axis and the q-axis zero sequence command signals (denoted by Vd_0cmd+ and Vq_0cmd+, respectively) and the d-axis and the q-axis zero sequence feedback signals (denoted by Vd_0cmd+ and Vq_0cmd+, respectively).
At step 40, step 42 and step 44, the set of positive sequence control signals (denoted by Cd+ and Cq+), the set of negative sequence control signals (denoted by Cd− and Cq−) and the set of zero sequence control signals (denoted by Cd0  and Cq0) are generated based on the set of error signals. The controller 16 is operable to generate the set of positive sequence control signals (denoted by Cd+ and Cq+) based on the first d-axis error signal (denoted by d1) and the first q-axis error signal (denoted by q1), respectively. Similarly, the controller 16 is operable to generate the set of negative sequence control signals (denoted by Cd− and Cq−) based on the second d-axis error signal (denoted by d2) and the second q-axis error signal (denoted by q3). respectively. Similarly, the controller 16 is operable to generate the set of zero sequence control signals (denoted by Cd0 and Cq0) based on the third d-axis error signal (denoted by d3) and the third q-axis error signal (denoted by q3), respectively.
At step 46, the set of positive sequence control signals (denoted by Cd+ and Cq+), the set of negative sequence control signals (denoted by Cd− and Cq−), and the set of zero sequence control signals (denoted by Cd0 and Cq0) are transformed from the dq-coordinate system to the abc-coordinate system. In an embodiment, the controller 16 is operable to transform the set of positive sequence control signals (denoted by Cd+ and Cq+), the set of negative sequence control signals (denoted by Cd− and Cq−), and the set of zero sequence control signals (denoted by Cd0 and Cq0) from the dq-coordinate system to the abc-coordinate system. Based on the transformation, the controller 16 is operable to generate the three-phase positive sequence control signal (denoted by Vinv_a+, Vinv_b+ and Vinv_c+), the three-phase negative sequence control signal (denoted by Vinv_a−, Vinv_b− and Vinv_c−)) and the three-phase zero sequence control signal (denoted by Vinv0).
At step 48, the respective abc-coordinates of the three-phase positive sequence control signal (denoted by Vinva+, Vinvb+ and Vinvc+), the three-phase negative sequence control signal (denoted Vinva−, Vinvb− and Vinvc−), and the three-phase zero sequence control signal (denoted by Vinv0) are combined. In an embodiment, the controller 16 is operable in combine the respective abc-coordinates of the three-phase positive sequence control signal (denoted by Vinva+, Vinvb+ and Vinvc+), the three-phase negative sequence control signal (denoted by Vinva−, Vinvb− and Vinvc−), and the three-phase zero sequence control signal (denoted by Vinv0).
The method 30 facilitates regulated output of the three-phase inverter 12, feeding the unbalanced load 14, using the three-phase balanced voltage signal (denoted by Vinv_a, Vinv_b and Vinv_c) in the system 10. More specifically, the controller 16 of the system 10 is operable to utilize the balanced three-phase control voltage signal (denoted by Vinv_a, Vinv_b and Vinv_c) to regulate the three-phase output voltage of the three-phase inverter 12 across the unbalanced load 14.
While aspects of the present disclosure have been particularly shown and described with reference to the embodiments above, it will be understood by -those skilled in the art that various additional embodiments may be contemplated by the modification of the disclosed machines, systems, and methods without departing from the spirit and scope of the disclosure. Such embodiments should be understood to fall within the scope of the present disclosure as determined based upon the claim(s) and any equivalents thereof.

## Claims

1. A method for controlling a three-phase output voltage of a three-phase inverter connected to aloud, the method comprising:
transforming, using a controller, a three-phase command voltage signal to a dq-coordinate system in order to generate a d-axis and a q-axis positive sequence command signals, a d-axis and a q-axis negative sequence command signals, and a zero sequence command signal;
transforming, using the controller, a three-phase feedback voltage signal to the dq-coordinate system in order to generate ad-axis and a q-axis positive sequence feedback signals, a d-axis and a q-axis negative sequence feedback signals, and a zero sequence feedback signal;
phase shifting, using the controller, the zero sequence command signal to generate a 120 degrees phase shifted zero sequence command signal, and a 240 degrees phase shifted zero sequence command signal;
phase shifting, using the controller, the zero sequence feedback signal to generate a 120 degrees phase shifted zero sequence feedback signal, and a 240 degrees phase shifted zero sequence feedback signal;
transforming, using the controller, the zero sequence command signal, the 120 degrees phase shifted zero sequence command signal and the 240 degrees phase shifted zero sequence command signal to the dq-coordinate system in order to generate a d-axis and a q-axis zero sequence command signals;
transforming, using the controller, the zero sequence feedback signal, the 120 degree phase shifted zero sequence feedback signal and the 240 degree phase shifted zero sequence feedback signal to the dq-coordinate system in order to generate a d-axis and a q-axis zero sequence feedback signals;
generating, using the controller, a set of positive sequence control signals, a set of negative sequence control signals, and a set of zero sequence control signals, wherein the set of positive sequence control signals are generated based on the d-axis and the q-axis positive sequence command signals and the d-axis and the q-axis positive sequence feedback signals, the set of negative sequence control signals are generated based on the d-axis and the q-axis negative sequence command signals and the d-axis and the q-axis negative sequence feedback signals, and the set of zero sequence control signals are generated based on the d-axis and the q-axis zero sequence command signals and the d-axis and the q-axis zero sequence feedback signals;
transforming, using the controller, the set of positive sequence control signals, the set of negative sequence control signals, and the set of zero sequence control signals from the dq-coordinate system to a abc-coordinate system in order to generate a three-phase positive sequence control signal, a three-phase negative sequence control signal, and a three-phase zero sequence control signal; and
combining, using the controller, the respective abc-coordinates of the three-phase positive sequence control signal, the three-phase negative sequence control signal, and the three-phase zero sequence control signal to generate a balanced three-phase control voltage signal for controlling the three-phase output voltage of the three-phase inverter.