# Patent

## Title
Systems and methods for discharging an AC input capacitor with automatic detection

## Abstract

System and method for discharging a capacitor. An example system includes a signal detector and a discharge control component. The signal detector is configured to receive an input signal and generate a detection signal based on at least information associated with the input signal, the input signal being associated with an alternate current signal received by a capacitor including a first capacitor terminal and a second capacitor terminal. The discharge control component configured to receive at least the detection signal and generate an output signal to discharge the capacitor if the detection signal satisfies one or more conditions.

## Background
1. CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 13/367,097, filed Feb. 6, 2012, which claims priority to U.S. Provisional Application No. 61/443,637, filed Feb. 16, 2011, commonly assigned, both of the above-referenced applications being incorporated by reference herein for all purposes.
Additionally, this application is related to U.S. patent application Ser. No. 12/892,580, filed Sep. 28, 2010, which is incorporated by reference herein for all purposes.


2. BACKGROUND OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for discharging a capacitor with automatic detection. Merely by way of example, the invention has been applied to a power converter. But it would be recognized that the invention has a much broader range of applicability.
Power converters have been widely used for consumer electronics such as portable devices. The power converters can convert electric power from one form to another. As an example, the electric power is transformed from alternate current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. Additionally, the power converters can also convert the electric power from one voltage level to another voltage level. Specifically, the power converters include linear converters and switch-mode converters. The switch-mode converters often use pulse-width-modulated (PWM) or pulse-frequency-modulated (PFM) mechanisms. The switch-mode converters usually are more efficient than the linear converters.
FIG. 1 is a simplified conventional diagram showing a switch-mode power conversion system with an AC input resistor and an AC input capacitor. The switch-mode power conversion system 100 includes an alternating current (AC) input resistor 120 (e.g., an X-resistor), an AC input capacitor 110 (e.g., an X-capacitor), input terminals 122 and 124, a switch-mode controller 130, a primary winding 172, a secondary winding 174, an auxiliary winding 176, and a switch 180.
As shown in FIG. 1, the switch-mode power conversion system 100 includes the AC input capacitor 110 that is connected to the input terminals 122 and 124. The AC input capacitor 110 often is used to address the issue of electromagnetic interference (EMI). Additionally, to comply with some safety requirements, the voltage across the AC input capacitor 110 needs to drop below a predetermined threshold (e.g., direct current 60V) in a short time period (e.g., within 1 second) after the input terminals 122 and 124 are disconnected from an AC power supply. To facilitate the discharge of the AC input capacitor 110, the power conversion system 100 also includes the AC input resistor 120 that is connected to the AC input capacitor 110 in parallel.
But the AC input resistor 120 also consumes power when the power supply for AC input voltage is not disconnected and thus causes the standby power consumption of the power conversion system 100 to rise. For example, if the AC input resistor 120 has a resistance of 3 MΩ, then, with a 264-volt AC input voltage, the power consumption of the resistor 120 is about 23 mW.
As shown in FIG. 1, after the input terminals 122 and 124 are disconnected from the AC power supply, the charges accumulated on the AC input capacitor 110 are released through the AC input resistor 120. For example, the voltage across the AC input capacitor 110 decreases with time as follows.




  
    
      
        
          
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where Vxc is the voltage across the AC input capacitor 110, and V0 is the voltage value of Vxc at the time when the input terminals 122 and 124 are disconnected from the AC power supply. Rx and Cx are the resistance value and the capacitance value of the AC input resistor 120 and the AC input capacitor 110 respectively.

As an example, in order for Vxc to drop approximately by a factor of e within one second, the resistance of the AC input resistor 120 satisfies the following equation.




  
    
      
        
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Usually, the magnitude of Cx depends on the power of the switch-mode power conversion system 100 and the solution to electromagnetic interference. If the capacitance of the AC input capacitor 110 is increased, the resistance of the AC input resistor 120 would become smaller according to Equation 2 and the AC input resistor 120 may consume more power.
Hence it is highly desirable to improve the techniques of discharging the AC input capacitor in order to reduce the power loss.
3. BRIEF SUMMARY OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for discharging a capacitor with automatic detection. Merely by way of example, the invention has been applied to a power converter. But it would be recognized that the invention has a much broader range of applicability.
According to one embodiment, a system for discharging a capacitor includes a signal detector and a discharge control component. The signal detector is configured to receive an input signal and generate a detection signal based on at least information associated with the input signal, the input signal being associated with an alternate current signal received by a capacitor including a first capacitor terminal and a second capacitor terminal. A discharge control component is configured to receive at least the detection signal and generate an output signal to discharge the capacitor if the detection signal satisfies one or more conditions.
According to another embodiment, a system for detecting an input signal includes a comparator, a pulse generator, and a detection component. The comparator is configured to receive an input signal and a threshold signal and generate a comparison signal based on at least information associated with the input signal and the threshold signal. The pulse generator is configured to generate a pulse signal based on at least information associated with the comparison signal. The detection component is configured to receive the pulse signal and generate a detection signal based on at least information associated with the pulse signal. The comparator is further configured to change the comparison signal from a first logic level to a second logic level if the input signal changes from a first input value larger than the threshold signal to a second input value smaller than the threshold signal. In addition, the comparator is configured to change the comparison signal from the second logic level to the first logic level if the input signal changes from a third input value smaller than the threshold signal to a fourth input value larger than the threshold signal. The pulse generator is further configured to generate a pulse if the comparison signal is changed from the first logic level to the second logic level or if the comparison signal is changed from the second logic level to the first logic level. Furthermore, the detection component is further configured to change the detection signal from a third logic level to a fourth logic level if no pulse is generated by the pulse generator for a predetermined time period.
According to yet another embodiment, a system for discharging a device includes a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal, a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal, and a fourth transistor including a tenth transistor terminal, an eleventh transistor terminal and a twelfth transistor terminal. The second transistor terminal is connected to the fourth transistor terminal. The fifth transistor terminal is connected to the seventh transistor terminal. The eighth transistor terminal is connected to the eleventh terminal and configured to receive an input signal. Additionally, the system is further configured to, if the input signal satisfies one or more conditions, turn on the first transistor and the fourth transistor, and discharge the device through at least the first transistor and the fourth transistor.
In one embodiment, a system for detecting an input signal includes a signal detector, a comparator, a first pulse generator, and a detection component. The signal detector is configured to sample an input signal and generate one or more sampled signals including a first sampled signal. The comparator is configured to receive the one or more sampled signals and a threshold signal and generate a comparison signal based on at least information associated with the one or more sampled signals and the threshold signal. The first pulse generator is configured to generate a first pulse signal based on at least information associated with the comparison signal. The detection component is configured to receive the first pulse signal and generate a detection signal based on at least information associated with the first pulse signal. The comparator is further configured to, if the first sampled signal is smaller than the threshold signal, generate the comparison signal at a first logic level. Additionally, the comparator is configured to, if the first sampled signal is larger than the threshold signal, generate the comparison signal at a second logic level. Moreover, the first pulse generator is further configured to generate a pulse if the comparison signal is changed from the first logic level to the second logic level or if the comparison signal is changed from the second logic level to the first logic level. The detection component is further configured to change the detection signal from a third logic level to a fourth logic level if no pulse is generated by the first pulse generator for a predetermined time period.
In another embodiment, a system for detecting an input signal and discharging a device includes a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal, and a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal. The system further includes a first resistor including a first resistor terminal and a second resistor terminal, and a second resistor including a third resistor terminal and a fourth resistor terminal. The third transistor terminal is connected, directly or indirectly, to the fourth transistor terminal. The third transistor terminal is connected, directly or indirectly, to the first resistor terminal. The second resistor terminal is connected to the third resistor terminal. The fourth resistor terminal is connected to the seventh transistor terminal. The first transistor terminal is configured to receive an input signal. The second transistor terminal is configured to receive a first drive signal. The fifth transistor terminal is configured to receive a second drive signal. Moreover, the eighth transistor terminal is configured to receive a third drive signal. The system is further configured to, if the first drive signal satisfies one or more first conditions and the second drive signal satisfies one or more second conditions, turn on the first transistor and the second transistor, and discharge the device through at least the first transistor and the second transistor. In addition, the system is further configured to, if the first drive signal satisfies the one or more first conditions and the third drive signal satisfies one or more third conditions, turn on the first transistor and the third transistor, and generate an output signal based on at least information associated with the input signal.
In yet another embodiment, a system for detecting an input signal includes a signal detector, a comparator, a counting component, and a detection component. The signal detector is configured to sample an input signal at a plurality of times during a first predetermined time period and generate a plurality of sampled signals corresponding to the plurality of times respectively, the plurality of times including a first time and a second time immediately after the first time, the plurality of sampled signals including a first sampled signal corresponding to the first time and a second sampled signal corresponding to the second time. The comparator is configured to receive the plurality of sampled signals and generate a comparison signal based on at least information associated with the plurality of sampled signals. The counting component is configured to receive at least the comparison signal and change a value based on at least information associated with the comparison signal. The detection component is configured to generate a detection signal based on at least information associated with the value. The comparator is further configured to, if the first sampled signal is smaller than the second sampled signal, generate the comparison signal at a first logic level. Additionally, the comparator is configured to, if the first sampled signal is larger than the second sampled signal, generate the comparison signal at the second logic level. The counting component is further configured to increase the value by a first predetermined magnitude if the comparison signal is at the first logic level, and decrease the value by a second predetermined magnitude if the comparison signal is at the second logic level. The detection component is further configured to change the detection signal from a third logic level to a fourth logic level if the value is larger than a first threshold or smaller than a second threshold after the first predetermined time period.
Many benefits are achieved by way of the present invention over conventional techniques. Certain embodiments of the present invention provide a system and method for automatically detecting the AC input voltage, and if appropriate, in response, quickly discharging the AC input capacitor. For example, the system and method can reduce the power consumption (e.g., standby power consumption) of the power conversion system. In another example, the system and method does not need to use the AC input resistor.
Depending upon embodiment, one or more of these benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.



4. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified conventional diagram showing a switch-mode power conversion system with an AC input resistor and an AC input capacitor.
FIG. 2 is a simplified diagram showing a switch-mode power conversion system according to an embodiment of the present invention.
FIG. 3 is a simplified diagram showing a controller for the switch-mode power conversion system of FIG. 2 according to an embodiment of the present invention.
FIG. 4 is a simplified diagram showing an AC detection component as part of the controller for the switch-mode power conversion system of FIG. 2 according to an embodiment of the present invention.
FIG. 5 is a simplified timing diagram for generating a detection signal by the AC detection component of FIG. 4 as part of the controller for the switch-mode power conversion system of FIG. 2 according to an embodiment of the present invention.
FIG. 6 is a simplified diagram showing a voltage control component as part of the controller for the switch-mode power conversion system of FIG. 2 according to an embodiment of the present invention.
FIG. 7 is a simplified diagram showing the AC detection component of FIG. 4 and the voltage control component of FIG. 6 as parts of the controller for the switch-mode power conversion system of FIG. 2 according to another embodiment of the present invention.
FIG. 8 is a simplified diagram showing a switch-mode power conversion system according to another embodiment of the present invention.
FIG. 9 is a simplified diagram showing an AC detection component as part of the controller for the switch-mode power conversion system of FIG. 8 according to an embodiment of the present invention.
FIG. 10 is a simplified timing diagram for generating a detection signal by the AC detection component of FIG. 9 as part of the controller for the switch-mode power conversion system of FIG. 8 according to an embodiment of the present invention.
FIG. 11 is a simplified timing diagram for generating the detection signal by the AC detection component of FIG. 9 as part of the controller for the switch-mode power conversion system of FIG. 8 according to another embodiment of the present invention.
FIG. 12 is a simplified diagram showing a combination component for a sampling component and a voltage control component of FIG. 9 as parts of the controller for the switch-mode power conversion system of FIG. 8 according to an embodiment of the present invention.
FIG. 13 is a simplified diagram showing the AC detection component and the voltage control component of FIG. 9 as parts of the controller for the switch-mode power conversion system of FIG. 8 according to an embodiment of the present invention.
FIG. 14 is a simplified diagram showing an AC detection component as part of the controller for the switch-mode power conversion system of FIG. 8 according to another embodiment of the present invention.
FIG. 15 is a simplified timing diagram for generating a detection signal by the AC detection component of FIG. 14 as part of the controller for the switch-mode power conversion system FIG. 8 according to another embodiment of the present invention.



5. DETAILED DESCRIPTION OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for discharging a capacitor with automatic detection. Merely by way of example, the invention has been applied to a power converter. But it would be recognized that the invention has a much broader range of applicability.
FIG. 2 is a simplified diagram showing a switch-mode power conversion system according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The power conversion system 200 includes AC input terminals 270 and 272, an AC input capacitor 210, diodes 220 and 222, resistors 230 and 232, a controller 240, a primary winding 282, a secondary winding 284, an auxiliary winding 286, and a switch 280. The power conversion system 200 further includes diodes 224 and 226. For example, the controller 240 is a chip that includes terminals 250, 252, 254, 256, 258, 260, and 262. In another example, the controller 240 includes an AC detection component 296 and a voltage control component 298. In yet another example, the terminal 256 (e.g., GND) is biased at a chip-ground voltage 292. In yet another example, an anode terminal of the diode 224 is biased at the chip-ground voltage 292. In yet another example, an anode terminal of the diode 226 is biased at the chip-ground voltage 292.
In one embodiment, a voltage divider that includes the resistors 230 and 232 receives a signal 236 from an AC input terminal 272 (or an AC input terminal 270) and outputs a signal 234. For example, the AC detection component 296 receives the signal 234 through the terminal 250 (e.g., terminal BO) and outputs a signal 294 to the voltage control component 298. In another example, if the signal 294 indicates that the AC input terminals 270 and 272 are disconnected from an AC power supply, the voltage control component 298 discharges the AC input capacitor 210 through the diode 220 or the diode 222 in combination with other internal circuit components of the controller 240.
The resistance values of the resistors 230 and 232 can be made large and the power consumption of the resistors 230 and 232 can thus be reduced according to certain embodiments. For example, if the resistance value of the resistor 230 is 40 MΩ and the resistance value of the resistor 232 is 300 KΩ, the power consumption of the resistors 230 and 232, with a 264-volt AC input voltage, is about 1.7 mW, which is much lower than the power consumption of 23 mW for the AC input resistor 120 as discussed above.
FIG. 3 is a simplified diagram showing the controller 240 for the switch-mode power conversion system 200 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 240 includes at least an AC detection component 310, a voltage control component 320, a brownout detection component 330, and an under-voltage-lockout (UVLO) component 340. For example, the AC detection component 310 and the voltage control component 320 are the same as the AC detection component 296 and the voltage control component 298, respectively.
In one embodiment, the AC detection component 310 receives at least a signal 312 through the terminal 250 (e.g., terminal BO) and a threshold signal 316 (e.g., Vth_bo). For example, the AC detection component 310 compares the signal 312 with the threshold signal 316, and outputs a detection signal 314 (e.g., ACoff). In another example, if the magnitude of the signal 312 crosses over the threshold 316 (e.g., Vth_bo) periodically, the AC input terminals 270 and 272 are not disconnected from the AC power supply. In yet another example, if the magnitude of the signal 312 does not cross over the threshold 316 (e.g., Vth_bo) for a predetermined period of time, it is recognized that the AC input terminals 270 and 272 are disconnected from the AC power supply. In yet another example, the detection signal 314 (e.g., ACoff) is at a logic high level if the AC input terminals 270 and 272 are disconnected from the AC power supply, and is at a logic low level if the AC input terminals 270 and 272 are not disconnected from the AC power supply. In yet another example, the signal 312 is associated with an input signal (e.g., an AC input voltage) received at the AC input terminals 270 and 272. In yet another example, the threshold signal 316 is much larger than zero in magnitude. In yet another example, the threshold signal 316 has a low magnitude (e.g., close to zero). In yet another example, the signal 312 is the same as the signal 234. In yet another example, the signal 314 is the same as the signal 294.
In another embodiment, the UVLO component 340 receives a signal 344 through the terminal 260 (e.g., terminal VDD) and outputs at least a signal 342 (e.g., PWD). For example, if the signal 344 is larger than a predetermined threshold in magnitude, the signal 342 (e.g., PWD) is at a logic high level. In another example, if the signal 344 is lower than the predetermined threshold in magnitude, the signal 342 (e.g., PWD) is at a logic low level.
In yet another embodiment, the voltage control component 320 receives the detection signal 314 and the signal 342 (e.g., PWD) and outputs a signal 322. In another example, if the detection signal 314 is at the logic high level and the signal 342 (e.g., PWD) is at the logic low level, the voltage control component 320 discharges the AC input capacitor 210 by reducing the voltage level of the signal 322 through the terminal 262 (e.g., terminal HV). In another example, if the signal 342 (e.g., PWD) is at the logic high level and/or the detection signal 314 (e.g., ACoff) is at the logic low level, the voltage control component 320 does not discharge the AC input capacitor 210 by reducing the voltage level of the signal 322 through the terminal 262 (e.g., terminal HV). In yet another embodiment, the AC detection component 310 shares the same terminal 250 with the brownout detection component 330, without requiring any additional terminal for the controller chip.
FIG. 4 is a simplified diagram showing an AC detection component according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The AC detection component 400 includes a comparator 410, a debounce component 420, a pulse generator 430, and a counter 440. For example, the AC detection component 400 is the same as the AC detection component 310. In another example, the AC detection component 400 is used to replace the AC detection component 296 in FIG. 2.
In one embodiment, the comparator 410 receives and compares a signal 402 (e.g., BO) and a threshold signal 404 (e.g., Vth_bo), and in response, outputs a comparison signal 412 to the debounce component 420. In another example, if the magnitude of the signal 402 crosses over the threshold 404 (e.g., Vth_bo) periodically, the AC input terminals 270 and 272 are not disconnected from the AC power supply. In yet another example, if the magnitude of the signal 402 does not cross over the threshold 404 (e.g., Vth_bo) for a predetermined period of time, the AC input terminals 270 and 272 are disconnected from the AC power supply. In yet another example, the signal 402 is the same as the signal 312. In yet another example, the signal 404 is the same as the signal 316.
In another embodiment, the debounce component 420 generates a signal 422 (e.g., the Cout signal), which is received by the pulse generator 430. For example, the pulse generator 430, in response, outputs a signal 432 (e.g., the reset signal) to the counter 440. In another example, the counter 440 also receives a clock signal 406 and generates a detection signal 408 (e.g., ACoff). In yet another example, the detection signal 408 (e.g., ACoff) is at a logic high level if the AC input terminals 270 and 272 are disconnected from the AC power supply, and is at a logic low level if the AC input terminals 270 and 272 are not disconnected from the AC power supply. In yet another example, the signal 402 is associated with an input signal (e.g., an AC input voltage) received at the AC input terminals 270 and 272. In yet another example, the threshold signal 404 is much larger than zero in magnitude. In yet another example, the threshold signal 404 has a low magnitude (e.g., close to zero). In some embodiments, the debounce component 420 is omitted and thus the signal 412 is the same as the signal 422. In yet another example, the signal 406 is the same as the signal 318. In yet another example, the signal 408 is the same as the signal 314.
FIG. 5 is a simplified timing diagram for generating the detection signal 408 by the AC detection component 400 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The waveform 510 represents an AC voltage across the AC input capacitor 210 as a function of time, the waveform 520 represents the signal 402 as a function of time, and the waveform 530 represents the signal 422 as a function of time. Additionally, the waveform 540 represents the signal 432 as a function of time, and the waveform 550 represents the detection signal 408 as a function of time.
In one embodiment, the signal 422 (e.g., corresponding to the waveform 530) is at a logic high level if the signal 402 (e.g., corresponding to the waveform 520) is higher than the threshold signal 404 (e.g., Vth_bo) in magnitude, and the signal 422 (e.g., corresponding to the waveform 530) is at a logic low level if the signal 402 (e.g., corresponding to the waveform 520) is lower than the threshold signal 404 (e.g., Vth+bo) in magnitude. In another example, the pulse generator 430 detects rising edges and falling edges of the signal 422 (e.g., corresponding to the waveform 530), and in response generates pulses for the signal 432 (e.g., corresponding to the waveform 540). In yet another example, the counter 440 is reset by the pulses of the signal 432 (e.g., corresponding to the waveform 540) and counts the lapse of time since the last reset. According to one embodiment, if the lapse of time since the last reset reaches a predetermined value (e.g., 30 ms), the counter 440 generates the detection signal 408 (e.g., corresponding to the waveform 550 and changing to the logic high level at time t2) to indicate the AC input terminals 270 and 272 are no longer provided with an AC input voltage. According to another embodiment, the AC input terminals 270 and 272 stop being provided with the AC input voltage at time t1 as shown in FIG. 5. For example, the signal 402 has a peak magnitude 564 which is much larger than the threshold signal 404 in magnitude.
FIG. 6 is a simplified diagram showing a voltage control component according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The voltage control component 600 includes transistors 606, 610, 616 and 620 and a resistor 630. The voltage control component 600 further includes resistors 608, 622 and 630, and a current-limit component 624. For example, the voltage control component 600 is the same as the voltage control component 320. In another example, the voltage control component 600 is used to replace the voltage control component 298 in FIG. 2.
In one embodiment, the transistor 610 is a MOS transistor that sustains a high voltage (e.g., 600 volts). For example, the transistor 610 is an N-channel MOS field effect transistor. In another example, the transistor 606 is an N-channel field effect transistor and a source terminal of the transistor 606 is biased at a chip-ground voltage 692. In yet another example, the transistor 616 is an N-channel field effect transistor and a source terminal of the transistor 616 is biased at the chip-ground voltage 692. In yet another example, the transistor 620 is an N-channel field effect transistor and a source terminal of the transistor 620 is biased at the chip-ground voltage 692. In yet another example, a drain terminal of the transistor 606 is connected to a gate terminal of the transistor 616. In yet another example, a drain terminal of the transistor 616 is connected to a gate terminal 610. In yet another example, the resistor 630 is connected between a source terminal of the transistor 610 and a drain terminal of the transistor 620. In yet another example, an anode terminal of the diode 626 is connected to the drain terminal of the transistor 620, and a signal 632 is applied to a cathode terminal of the diode 626. In yet another example, the chip-ground voltage 692 is the same as the chip-ground voltage 292.
As shown in FIG. 6, the voltage control component 600 receives at least a detection signal 604 (e.g., ACoff) and a signal 602 (e.g., PWD) according to one embodiment. For example, the detection signal 604 (e.g., ACoff) is at a logic high level if the AC input terminals 270 and 272 are disconnected from the AC power supply, and is at a logic low level if the AC input terminals 270 and 272 are not disconnected from the AC power supply. In another example, the signal 602 (e.g., PWD) is associated with a signal 632 (e.g., VDD) that is applied to the terminal 260. In yet another example, the signal 602 (e.g., PWD) is at a logic high level if the signal 632 is larger than a predetermined threshold in magnitude, and is at a logic low level if the signal 632 (e.g., VDD) is lower than the predetermined threshold in magnitude. In yet another example, the signal 602 is the same as the signal 342. In yet another example, the signal 604 is the same as the signal 312.
According to another embodiment, if the detection signal 604 (e.g., ACoff) is at the logic low level, the transistors 606 and 620 are turned off. For example, if the signal 602 (e.g., PWD) is at the logic high level, the transistor 616 is turned on. In another example, a gate signal 612 is pulled down and the transistor 610 is turned off. In yet another example, the transistor 618 is used as a large resistor.
According to yet another embodiment, if the detection signal 604 (e.g., ACoff) is at the logic high level and the signal 602 (e.g., PWD) is at the logic low level, the transistor 616 is turned off and the gate signal 612 is raised. For example, the transistors 610 and 620 are turned on by the signals 612 and 604, respectively. In another example, the AC input capacitor 210 is discharged through the transistors 610 and 620 and the resistor 630. In yet another example, when both the transistors 610 and 620 are turned on, the AC input capacitor 210 is discharged by reducing the voltage level of a signal 634 through the terminal 262 (e.g., HV). In yet another example, the current-limit component 624 detects a current flowing through the resistor 630 and operates to reduce the current if it is larger than a threshold in magnitude. In yet another example, the discharging current on the discharging path is at a predetermined level, e.g., 3 mA. In yet another example, the signal 634 is the same as the signal 322.
FIG. 7 is a simplified diagram showing the AC detection component 310 and the voltage control component 320 as parts of the controller 240 for the switch-mode power conversion system 200 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The AC detection component 310 includes the comparator 410, the debounce component 420, the pulse generator 430, and the counter 440. The debounce component 420 is omitted in some embodiments. The voltage control component 320 includes transistors 606, 610, 616 and 620 and a resistor 630.
For example, the debounce component 420 includes two current sources 750 and 752, two transistors 754 and 756, a capacitor 758 and an inverter 760. In another example, the counter 440 includes three D flip-flops 762, 764 and 766.
FIG. 8 is a simplified diagram showing a switch-mode power conversion system according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the power conversion system 800 includes an AC input capacitor 810, diodes 820 and 822, a resistor 830, a controller 840, a primary winding 882, a secondary winding 884, an auxiliary winding 886, and a switch 880. In another example, the controller 840 is a chip that includes terminals 850, 852, 854, 856, 858, 860, and 862. In yet another example, the controller 840 includes at least an AC detection component 1810 and a voltage control component 1820.
According to one embodiment, the AC detection component 1810 receives a signal 1822 through the resistor 830 and the terminal 862, and receives a clock signal 1818 and a gate control signal 1824. For example, in response, the AC detection component 1810 determines whether the AC amplitude of the signal 1822 is nearly zero and, in response, outputs the detection signal 1814 (e.g., the ACoff signal) to indicate whether the AC amplitude of the signal 1822 is nearly zero. In another example, the voltage control component 1820 receives the detection signal 1814, and if the detection signal 1814 indicates the AC amplitude of the signal 1822 is nearly zero (e.g., the signal 1822 being nearly a DC signal), discharges the AC input capacitor 810 by reducing the voltage level of the signal 1822 through the terminal 862.
FIG. 9 is a simplified diagram showing the AC detection component 1810 as part of the controller 840 for the switch-mode power conversion system 800 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The AC detection component 1810 includes a pulse generator 910, a sampling component 920, a comparator 930, a debounce component 940, a flip-flop component 950, a pulse generator 960, and a counter 970.
According to one embodiment, the pulse generator 910 of the AC detection component 1810 receives the clock signal 1818 and outputs a pulse signal 912 to the sampling component 920. For example, the sampling component 920 also receives the gate control signal 1824, samples the signal 1822 (e.g., sampling 10 times within each AC period), and generates a sampled signal 922. In another example, the sampled signal 922 is received by the comparator 930.
According to another embodiment, the comparator 930 compares the sampled signal 922 with a threshold signal 924 (e.g., Vth1) and outputs a comparison signal 932 to the debounce component 940. For example, if the AC input terminals 870 and 872 are provided with an AC input voltage, the comparison signal 932 changes back and forth between the logic high level and the logic low level for several times (e.g., 4 times) within each AC period (e.g., 20 ms). In another example, if the comparison signal 932 does not change within a predetermined period of time (e.g., 30 ms), the AC input terminals 870 and 872 are determined to be no longer provided with the AC input voltage.
According to yet another embodiment, the debounce component 940 in response outputs a signal 942 to the flip-flop component 950. For example, the flip-flop component also receives a pulse signal 914 from the pulse generator 910. In another example, the flip-flop component 950 sends a signal 952 (e.g., the Cout signal) to the pulse generator 960, which in response generates a pulse signal 962 (e.g., the reset signal). In yet another example, the pulse signal 962 is received by the counter 970, which also receives the clock signal 1818 and generates the detection signal 1814. In yet another example, an AND gate 998 receives the detection signal 1814 and the pulse signal 912 and outputs the gate control signal 1824. In yet another example, the AND gate 998 is included in the AC detection component 1810. In yet another example, the AND gate 998 is not included in the AC detection component 1810. In yet another example, the gate control signal 1824 is equal to a logic sum of the detection signal 1814 and the pulse signal 912.
FIG. 10 is a simplified timing diagram for generating the detection signal 1814 by the AC detection component 1810 as part of the controller 840 for the switch-mode power conversion system 800 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The waveform 1010 represents the signal 1822 as a function of time, the waveform 1020 represents the pulse signal 912 as a function of time, the waveform 1030 represents the sampled signal 922 as a function of time, and the waveform 1040 represents the pulse signal 914 as a function of time. Additionally, the waveform 1050 represents the signal 952 as a function of time, the waveform 1060 represents the signal 962 as a function of time, and the waveform 1070 represents the detection signal 1814 as a function of time. Moreover, the waveform 1080 represents the gate control signal 1824 as a function of time.
FIG. 11 is a simplified timing diagram for generating the detection signal 1814 by the AC detection component 1810 as part of the controller 840 for the switch-mode power conversion system 800 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveforms 1110, 1120, 1130, 1140, 1150, and 1180 are expanded views (e.g., from time ta to time tb) for the waveforms 1010, 1020, 1030, 1040, 1050, and 1080 respectively.
As discussed above and further emphasized here, FIGS. 8 and 9 are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the debounce component 940 is removed, and thus the signal 932 is the same as the signal 942. In another example, the sampling component 920 and the voltage control component 1820 are combined by sharing some components. In yet another example, the AC detection component 1810 is not used as part of the controller 840, but used as an independent device or as a component in one or more other devices.
FIG. 12 is a simplified diagram showing a combination component for the sampling component 920 and the voltage control component 1820 as parts of the controller 840 for the switch-mode power conversion system 800 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The combined component 1200 includes transistors 1210, 1220, and 1240, and resistors 1230, 1232, and 1234. For example, the transistors 1210 and 1220 and the resistors 1232, and 1234 are used as part of the sampling component 920. In another example, the transistors 1210 and 1240 and the resistor 1230 are used as part of the voltage control component 1820. In yet another example, the transistor 1210 is a MOS transistor that sustains a high voltage (e.g., 600 volts). In yet another example, the transistor 1210 is an N-channel field effect transistor (FET). In yet another example, the transistor 1240 is an N-channel FET. In yet another example, the transistor 1220 is an N-channel FET.
In one embodiment, a source terminal of the transistor 1210 is connected to the resistor 1230. For example, a drain terminal of the transistor 1240 is connected to both the resistor 1230 and the resistor 1232 and a source terminal of the transistor 1240 is biased at a chip-ground voltage 1292. In another example, a drain terminal of the transistor 1220 is connected to the resistor 1234 and a source terminal of the transistor 1220 is biased at a chip-ground voltage 1292. In yet another example, the resistors 1232 and 1234 are connected.
As discussed above, and further emphasized here, FIG. 12 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the combination component 1200 is not used as part of the controller 840, but used as an independent device or as a component in one or more other devices.
FIG. 13 is a simplified diagram showing the AC detection component 1810 and the voltage control component 1820 as parts of the controller 840 for the switch-mode power conversion system 800 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the debounce component 940 includes two current sources 1350 and 1352, two transistors 1354 and 1356, a capacitor 1358 and an inverter 1360. In another example, the counter 970 includes three D flip-flops 1362, 1364 and 1366.
As shown in FIG. 9, FIG. 10, FIG. 11, FIG. 12, and/or FIG. 13, the pulse generator 910 generates pulses periodically for the pulse signal 912 (e.g., corresponding to the waveform 1020 and/or the waveform 1120), and also generates pulses periodically for the pulse signal 914 (e.g., corresponding to the waveform 1040 and/or the waveform 1140) according to some embodiments. For example, the pulse signal 912 (e.g., Det_pul) has a same frequency as the pulse signal 914 (e.g., Det_pul_s). In another example, the pulse signal 912 (e.g., Det_pul) has a larger duty cycle than the pulse signal 914 (e.g., Det_pul_s). In yet another example, the pulse signal 912 (e.g., Det_pul) has a frequency equal to 500 Hz and a duty cycle equal to 1%. In another example, the pulse signal 914 (e.g., Det_pul_s) has a frequency equal to 500 Hz and a duty cycle equal to 0.5%. In yet another example, a rising edge of the pulse signal 912 and a rising edge of the pulse signal 914 appear at the same time.
In one embodiment, the pulse signal 912 (e.g., corresponding to the waveform 1020 and/or the waveform 1120) is received by the transistor 1220, which is turned on by the pulses. For example, the transistor 1210 is also turned on by the pulses of the gate control signal 1824 (e.g., corresponding to the waveform 1080 and/or the waveform 1180). In another example, when both the transistors 1210 and 1220 are turned on, the signal 1822 is received by a voltage divider that includes the resistors 1230, 1232, and 1234 and outputs the sampled signal 922 (e.g., at time t3 as shown in FIG. 11) as follows (e.g., assuming that the on-resistance of the transistor 1210 and the on-resistance of the transistor 1220 are both small):




  
    
      
        
          V
          ac_div
        
        =
        
          
            V
            ac
          
          ×
          
            
              R
              1
            
            
              
                R
                1
              
              +
              
                R
                2
              
              +
              
                R
                3
              
              +
              
                R
                4
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        )
      
    
  




where Vac_div represents the voltage level of the sampled signal 922, and Vac represents the voltage level of the signal 1822. Additionally, R1, R2, R3, and R4 represent the resistance values of the resistors 1234, 1232, 1230 and 830 respectively.

In another embodiment, the sampled signal 922 (e.g., corresponding to the waveform 1030 and/or the waveform 1130) is received by the comparator 930 (e.g., as shown in FIG. 9 and/or FIG. 13), which compares the sampled signal 922 with the threshold signal 924, and outputs the comparison signal 932. For example, the comparison signal 932 is received by the debounce component 940, which in response generates the signal 942. In another example, the signal 942 is received by the flip-flop component 950, which locks the signal 952 (e.g., corresponding to the waveform 1050 and/or the waveform 1150) as the same as the signal 942 at the falling edge of the pulse signal 914 (e.g., at time t4 as shown in FIG. 11 that corresponds to the falling edge of the waveform 1140). In yet another example, if the voltage level of the sampled signal 922 (e.g., corresponding to the waveform 1030 and/or the waveform 1130) is smaller than the threshold signal 924, the signal 952 (e.g., corresponding to the waveform 1050 and/or the waveform 1150) is at a logic low level. In yet another example, if the voltage level of the sampled signal 922 (e.g., corresponding to the waveform 1030 and/or the waveform 1130) is larger than the threshold signal 924, the signal 952 (e.g., corresponding to the waveform 1050 and/or the waveform 1150) is at a logic high level.
In yet another embodiment, the signal 952 is received by the pulse generator 960, which detects rising edges and falling edges of the signal 952 (e.g., corresponding to the waveform 1050 and/or the waveform 1150), and in response generates pulses for the signal 962 (e.g., corresponding to the waveform 1060). For example, the signal 962 is received by the counter 970, which is reset by the pulses of the signal 962 (e.g., corresponding to the waveform 1060) and counts the lapse of time since the last reset. In another example, if the lapse of time since the last reset reaches a predetermined value (e.g., 30 ms), the counter 970 generates the detection signal 1814 (e.g., changing to the logic high level at time t6 as shown in FIG. 10) to indicate the AC input terminals 870 and 872 are no longer provided with the AC input voltage. In yet another example, the AC input terminals 870 and 872 stop being provided with the AC input voltage at time t5 as shown in FIG. 10.
As shown in FIG. 12 and/or FIG. 13, the detection signal 1814 (e.g., corresponding to the waveform 1070) is received by the transistor 1240 according to certain embodiments. For example, the transistor 1240 is turned on when the detection signal 1814 is at the logic high level. In another example, the transistor 1210 is also turned on when the gate control signal 1824 (e.g., corresponding to the waveform 1080 and/or the waveform 1180) is at the logic high level. In yet another example, when both the transistors 1210 and 1240 are turned on, the transistors 1210 and 1240, together with the diodes 820 and 822 and the resistors 830 and 1230, form a discharging path for the AC input capacitor 810. In yet another example, the discharging current on the discharging path is at a predetermined level, e.g., 3 mA. In yet another example, when both the transistors 1210 and 1240 are turned on, the AC input capacitor 810 is discharged by reducing the voltage magnitude of the signal 1822 through the terminal 862.
FIG. 14 is a simplified diagram showing the AC detection component 1810 as part of the controller 840 for the switch-mode power conversion system 800 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The AC detection component 1810 includes a pulse generator 1410, a sampling component 1420, a buffer 1430, a comparator 1440, capacitors 1450 and 1452, a component 1460 for addition and subtraction, a determination component 1470, switches 1480, 1482, and 1484.
According to one embodiment, the pulse generator 1410 of the AC detection component 1810 receives a clock signal 1918 and generates signals 1412, 1414, and 1416. For example, the signal 1412 is received by the sampling component 1420, and also received by the switch 1480 as a control signal. In another example, the signal 1414 is received by the switches 1482 and 1484 as control signals. In yet another example, the signal 1416 is received by the component 1460. In yet another example, the switch 1480 is closed when the signal 1412 is at the logic high level. In yet another example, the switches 1482 and 1484 are closed when the signal 1414 is at the logic high level.
According to another embodiment, the signal 1412 is the same as the signal 912, and the sampling component 1420 is the same as the sampling component 920. For example, the sampling component 1420 samples a signal 1922 through the terminal 862 (e.g., sampling 10 times within each AC period), and generates a sampled signal 1422. In another example, the sampled signal 1422 is the same as the sampled signal 922.
According to yet another embodiment, when the signal 1414 is at the logic high level, the voltage across the capacitor 1452 is duplicated, by at least the buffer 1430, as the voltage across the capacitor 1450. For example, the sampled signal 1422 previously obtained is preserved as a signal 1444 (e.g., the Vnb signal), and the sampled signal 1422 later obtained is represented by a signal 1442 (e.g., the Vn signal). In another example, the comparator 1440 receives the signal 1442 and a signal 1445 that is equal to the signal 1444 plus a predetermined offset, Vos, and outputs a comparison signal 1446 (e.g., the Ca signal) to the component 1460 for addition and subtraction. In yet another example, if the signal 1442 is equal to the signal 1444 in magnitude, the comparator 1440 outputs the comparison signal 1446 at a logic low level.
As shown in FIG. 14, the component 1460 for addition and subtraction (e.g., an incremental and decremental counter) detects the comparison signal 1446 and generates a count signal 1462 based on at least information associated with the comparison signal 1446 according to one embodiment. For example, if the component 1460 detects at a particular time (e.g., at a falling edge of the signal 1416) the comparison signal 1446 is at the logic high level, the number represented by the count signal 1462 is decreased by 1. In another example, if the component 1460 detects at the particular time (e.g., at the falling edge of the signal 1416) the comparison signal 1446 is at the logic low level, the number represented by the count signal 1462 is increased by 1. In yet another example, after every N additions and subtractions (e.g., N is an integer no less than 1), the number represented by the count signal 1462 is reset to 0.
In another embodiment, the determination component 1470 receives the count signal 1462, and generates the detection signal 1814 For example, the determination component 1470 determines the number represented by the count signal 1462, and if the number represented by the count signal 1462 is larger than a predetermined number or smaller than another predetermined number, generates the detection signal 1914 to indicate the AC input terminals 870 and 872 are no longer provided with the AC input voltage. In another example, if the AC input terminals 870 and 872 are provided with the AC input voltage, the sampled signal 1422 should change up and down in magnitude; hence if during a predetermined time period (e.g., much longer than half a period of the AC input voltage signal), the sampled signal 1422 decreases monotonically, increases monotonically, or remains unchanged, the AC input terminals 870 and 872 are determined to be no longer provided with the AC input voltage.
As discussed above, and further emphasized here, FIG. 14 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, instead of detecting the comparison signal 1446 at the falling edge of the signal 1416, the component 1460 detects the comparison signal 1446 at a rising edge of the signal 1416. In another example, if the signal 1442 is equal to the signal 1444 in magnitude, the comparator 1440 outputs the comparison signal 1446 at a logic high level. In yet another example, if the component 1460 detects that the comparison signal 1446 is at the logic high level, the number represented by the count signal 1462 is increased by 1. In yet another example, if the component 1460 detects the comparison signal 1446 is at the logic low level, the number represented by the count signal 1462 is decreased by 1.
FIG. 15 is a simplified timing diagram for generating the detection signal 1914 by the AC detection component 1810 as part of the controller 840 for the switch-mode power conversion system 800 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The waveform 1510 represents the signal 1412 as a function of time, the waveform 1520 represents the signal 1414 as a function of time, and the waveform 1530 represents the signal 1416 as a function of time. Seven timing reference points t7, t8, t9, t10, t11, t12, and t13 are shown in FIG. 15. For example, t7≦t8≦t9≦t10≦t11≦t12≦t13.
In one embodiment, during the time period between t7 and t9, the signal 1412 (e.g., corresponding to the waveform 1510) is at the logic high level; hence the switch 1480 is closed and the sampled signal 1422 is represented by the voltage across the capacitor 1452 (e.g., as shown by the signal 1442). For example, during the time period between t10 to t11, the signal 1414 (e.g., corresponding to the waveform 1520) is at the logic high level; hence the switches 1482 and 1484 are closed and the voltage across the capacitor 1452 (e.g., as shown by the signal 1442) is represented by the voltage across the capacitor 1450 (e.g., as shown by the signal 1444). In another example, during the time period between t11 to t12, both the signals 1412 and 1414 are at the logic low level; hence the switches 1480, 1482 and 1484 are open and the signal 1444 is preserved to represent the sampled signal 1422 that was obtained during the previous sampling process. In yet another example, during the time period between t12 to t13, the signal 1412 is at the logic high level; hence the sampled signal 1422 is generated during the current sampling process and represented by the signal 1442, which is compared with the signal 1444. In yet another example, at t13, the comparison signal 1446 is received by the component 1460 for addition and subtraction, and the component 1460 generates, at the falling edge of the signal 1416, the count signal 1462 based on at least information associated with the comparison signal 1446.
According to another embodiment, a system for discharging a capacitor includes a signal detector and a discharge control component. The signal detector is configured to receive an input signal and generate a detection signal based on at least information associated with the input signal, the input signal being associated with an alternate current signal received by a capacitor including a first capacitor terminal and a second capacitor terminal. A discharge control component is configured to receive at least the detection signal and generate an output signal to discharge the capacitor if the detection signal satisfies one or more conditions. For example, the system is implemented according to FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14 and/or FIG. 15.
According to another embodiment, a system for detecting an input signal includes a comparator, a pulse generator, and a detection component. The comparator is configured to receive an input signal and a threshold signal and generate a comparison signal based on at least information associated with the input signal and the threshold signal. The pulse generator is configured to generate a pulse signal based on at least information associated with the comparison signal. The detection component is configured to receive the pulse signal and generate a detection signal based on at least information associated with the pulse signal. The comparator is further configured to change the comparison signal from a first logic level to a second logic level if the input signal changes from a first input value larger than the threshold signal to a second input value smaller than the threshold signal. In addition, the comparator is configured to change the comparison signal from the second logic level to the first logic level if the input signal changes from a third input value smaller than the threshold signal to a fourth input value larger than the threshold signal. The pulse generator is further configured to generate a pulse if the comparison signal is changed from the first logic level to the second logic level or if the comparison signal is changed from the second logic level to the first logic level. Furthermore, the detection component is further configured to change the detection signal from a third logic level to a fourth logic level if no pulse is generated by the pulse generator for a predetermined time period. For example, the system is implemented according to at least FIG. 2, FIG. 3, FIG. 4, FIG. 5, and/or FIG. 7.
According to yet another embodiment, a system for discharging a device includes a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal, a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal, and a fourth transistor including a tenth transistor terminal, an eleventh transistor terminal and a twelfth transistor terminal. The second transistor terminal is connected to the fourth transistor terminal. The fifth transistor terminal is connected to the seventh transistor terminal. The eighth transistor terminal is connected to the eleventh terminal and configured to receive an input signal. Additionally, the system is further configured to, if the input signal satisfies one or more conditions, turn on the first transistor and the fourth transistor, and discharge the device through at least the first transistor and the fourth transistor. For example, the system is implemented according to at least FIG. 2, FIG. 3, FIG. 6, and/or FIG. 7.
In one embodiment, a system for detecting an input signal includes a signal detector, a comparator, a first pulse generator, and a detection component. The signal detector is configured to sample an input signal and generate one or more sampled signals including a first sampled signal. The comparator is configured to receive the one or more sampled signals and a threshold signal and generate a comparison signal based on at least information associated with the one or more sampled signals and the threshold signal. The first pulse generator is configured to generate a first pulse signal based on at least information associated with the comparison signal. The detection component is configured to receive the first pulse signal and generate a detection signal based on at least information associated with the first pulse signal. The comparator is further configured to, if the first sampled signal is smaller than the threshold signal, generate the comparison signal at a first logic level. Additionally, the comparator is configured to, if the first sampled signal is larger than the threshold signal, generate the comparison signal at a second logic level. Moreover, the first pulse generator is further configured to generate a pulse if the comparison signal is changed from the first logic level to the second logic level or if the comparison signal is changed from the second logic level to the first logic level. The detection component is further configured to change the detection signal from a third logic level to a fourth logic level if no pulse is generated by the first pulse generator for a predetermined time period. For example, the system is implemented according to at least FIG. 8, FIG. 9, FIG. 10, FIG. 11, and/or FIG. 13.
In another embodiment, a system for detecting an input signal and discharging a device includes a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal, and a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal. The system further includes a first resistor including a first resistor terminal and a second resistor terminal, and a second resistor including a third resistor terminal and a fourth resistor terminal. The third transistor terminal is connected, directly or indirectly, to the fourth transistor terminal. The third transistor terminal is connected, directly or indirectly, to the first resistor terminal. The second resistor terminal is connected to the third resistor terminal. The fourth resistor terminal is connected to the seventh transistor terminal. The first transistor terminal is configured to receive an input signal. The second transistor terminal is configured to receive a first drive signal. The fifth transistor terminal is configured to receive a second drive signal. Moreover, the eighth transistor terminal is configured to receive a third drive signal. The system is further configured to, if the first drive signal satisfies one or more first conditions and the second drive signal satisfies one or more second conditions, turn on the first transistor and the second transistor, and discharge the device through at least the first transistor and the second transistor. In addition, the system is further configured to, if the first drive signal satisfies the one or more first conditions and the third drive signal satisfies one or more third conditions, turn on the first transistor and the third transistor, and generate an output signal based on at least information associated with the input signal. For example, the system is implemented according to at least FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, and/or FIG. 13.
In yet another embodiment, a system for detecting an input signal includes a signal detector, a comparator, a counting component, and a detection component. The signal detector is configured to sample an input signal at a plurality of times during a first predetermined time period and generate a plurality of sampled signals corresponding to the plurality of times respectively, the plurality of times including a first time and a second time immediately after the first time, the plurality of sampled signals including a first sampled signal corresponding to the first time and a second sampled signal corresponding to the second time. The comparator is configured to receive the plurality of sampled signals and generate a comparison signal based on at least information associated with the plurality of sampled signals. The counting component is configured to receive at least the comparison signal and change a value based on at least information associated with the comparison signal. The detection component is configured to generate a detection signal based on at least information associated with the value. The comparator is further configured to, if the first sampled signal is smaller than the second sampled signal, generate the comparison signal at a first logic level. Additionally, the comparator is configured to, if the first sampled signal is larger than the second sampled signal, generate the comparison signal at the second logic level. The counting component is further configured to increase the value by a first predetermined magnitude if the comparison signal is at the first logic level, and decrease the value by a second predetermined magnitude if the comparison signal is at the second logic level. The detection component is further configured to change the detection signal from a third logic level to a fourth logic level if the value is larger than a first threshold or smaller than a second threshold after the first predetermined time period. For example, the system is implemented according to at least FIG. 8, FIG. 14 and/or FIG. 15.
For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined.
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.

## Claims

1. A system for discharging a capacitor, the system comprising:
a signal detector configured to receive an input signal and generate a detection signal based at least in part on the input signal, the input signal being associated with an alternate current signal; and
a discharge controller configured to receive the detection signal and generate an output signal to discharge a capacitor in response to the detection signal satisfying one or more conditions, the capacitor including a first capacitor terminal and a second capacitor terminal;
wherein:
the signal detector is further configured to, during a first time period, sample the input signal a first plurality of times to generate a first plurality of sampled signals respectively and compare each sampled signal of the first plurality of sampled signals with a first threshold; and
the discharge controller is further configured to, in response to the detection signal indicating that each sampled signal of the first plurality of sampled signals is larger than the first threshold, generate the output signal to discharge the capacitor, or is further configured to, in response to the detection signal indicating that each sampled of the first plurality of sampled signals is smaller than the first threshold, generate the output signal to discharge the capacitor.

2. The system of claim 1 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that the capacitor is disconnected from the alternate current signal.

3. The system of claim 1 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that during a second time period, the input signal remains larger than a second threshold.

4. The system of claim 1, wherein the discharge controller is further configured to, in response to the detection signal indicating that each sampled signal of the first plurality of sampled signals is larger than the first threshold, generate the output signal to discharge the capacitor.

5. The system of claim 1 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that during a second time period, the input signal remains smaller than a second threshold.

6. The system of claim 1 wherein the discharge controller is further configured to, in response to the detection signal indicating that each sampled signal of the first plurality of sampled signals is smaller than the first threshold, generate the output signal to discharge the capacitor.

7. The system of claim 1 wherein the discharge controller is further configured to, in response to the detection signal indicating that each sampled signal of the first plurality of sampled signals is larger than the first threshold, generate the output signal to discharge the capacitor, and is further configured to, in response to the detection signal indicating that each sampled of the first plurality of sampled signals is smaller than the first threshold, generate the output signal to discharge the capacitor.

8. The system of claim 1, and further comprising:
a first diode including a first diode terminal and a second diode terminal; and
a second diode including a third diode terminal and a fourth diode terminal;
wherein:
the second diode terminal is connected to the third diode terminal;
the first diode terminal is connected to the first capacitor terminal; and
the fourth diode terminal is connected to the second capacitor terminal.

9. The system of claim 8 wherein:
the second diode terminal and the third diode terminal are cathode terminals; and
the first diode terminal and the fourth diode terminal are anode terminals.

10. The system of claim 8 wherein the discharge controller is further configured to provide the output signal to the second diode terminal and the third diode terminal.

11. The system of claim 1, and further comprising:
a first resistor including a first resistor terminal and a second resistor terminal; and
a second resistor including a third resistor terminal and a fourth resistor terminal;
wherein:
the first resistor terminal is connected to the capacitor;
the second resistor terminal is connected to the third resistor terminal; and
the signal detector is further configured to receive the input signal from the second resistor terminal.

12. The system of claim 11 wherein the fourth resistor terminal is biased at a voltage.

13. A system for detecting an input signal, the system comprising:
a comparator configured to receive an input signal and a threshold signal and generate a comparison signal based at least in part on the input signal and the threshold signal, the comparison signal being associated with a signal level;
a pulse generator configured to generate a pulse signal based on at least information associated with the comparison signal; and
a counter configured to receive the pulse signal and generate a detection signal based at least in part on the pulse signal;
wherein the comparator is either further configured to:
change the signal level associated with the comparison signal in response to the input signal changing from a first input value larger than the threshold signal to a second input value smaller than the threshold signal; or is further configured to:
change the signal level associated with the comparison signal in response to the input signal changing from a third input value smaller than the threshold signal to a fourth input value larger than the threshold signal;

wherein the pulse generator is further configured to generate a pulse in response to the signal level associated with the comparison signal being changed; and
wherein the counter is further configured to change a logic level associated with the detection signal in response to no pulse being generated by the pulse generator for a time period.

14. The system of claim 13, wherein the pulse generator is either further configured to generate the pulse in response to the signal level associated with the comparison signal being changed from a first logic level to a second logic level, or further configured to generate the pulse in response to the signal level associated with the comparison signal being changed from the second logic level to the first logic level.

15. The system of claim 14, wherein the counter is further configured to change the logic level associated with the detection signal from a third logic level to a fourth logic level in response to no pulse being generated by the pulse generator for the time period.

16. The system of claim 15 wherein:
the first logic level and the third logic level are the same; and
the second logic level and the fourth logic level are the same.

17. The system of claim 15 wherein:
the first logic level and the fourth logic level are the same; and
the second logic level and the third logic level are the same.

18. A system for discharging a device, the system comprising:
a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal;
a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal;
a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal; and
a resistor including a first resistor terminal and a second resistor terminal, the first resistor terminal being connected to the third transistor terminal, the second resistor terminal being connected to the fourth transistor terminal;
wherein:
the eighth transistor terminal is connected to the fifth terminal and configured to receive an input signal;

wherein in response to the input signal satisfying one or more conditions:
the first transistor and the second transistor are turned on; and
the device is discharged through the first transistor and the second transistor.

19. The system of claim 18 wherein each terminal of the sixth transistor terminal, the ninth transistor terminal, and the twelfth transistor terminal is biased to a voltage.

20. The system of claim 18, wherein the device being discharged is a capacitor.

21. The system of claim 18, wherein the device is a capacitor configured to be connected to an alternate current signal.

22. A system for detecting an input signal, the system comprising:
a sample signal generator configured to sample an input signal and generate one or more sampled signals including a first sampled signal;
a comparator configured to receive the one or more sampled signals and a threshold signal and generate a comparison signal based at least in part on the one or more sampled signals and the threshold signal, the comparison signal being associated with a signal level;
a first pulse generator configured to generate a first pulse signal based on at least information associated with the comparison signal; and
a counter configured to receive the first pulse signal and generate a detection signal based at least in part on the first pulse signal;
wherein the comparator is either further configured to:
in response to the first sampled signal being smaller than the threshold signal, change the signal level associated with the comparison signal to a first logic level; or

is further configured to:
in response to the first sampled signal being larger than the threshold signal, change the signal level associated with the comparison signal to a second logic level;

wherein the first pulse generator is further configured to generate a pulse in response to the signal level associated with the comparison signal being changed; and
wherein the detection component is further configured to change the detection signal from a third logic level to a fourth logic level if no pulse is generated by the first pulse generator for a predetermined time period.

23. The system of claim 22 wherein the sample signal generator includes:
a second pulse generator configured to generate a second pulse signal including one or more detection pulses, the one or more detection pulses corresponding to one or more detection times; and
a signal sampler configured to receive the second pulse signal and sample the input signal at each detection time of the one or more detection times associated with the one or more detection pulses to generate the one or more sampled signals.

24. The system of claim 22 wherein the first pulse generator includes:
a flip flop configured to generate a signal based on at least information associated with the comparison signal;
wherein the first pulse generator is further configured to receive the signal and generate the first pulse signal based at least in part on the signal; and
wherein the flip flop is further configured to generate the signal at a fifth logic level in response to the comparison signal being at the first logic level, and generate the signal at a sixth logic level in response to the comparison signal being at the second logic level.

25. The system of claim 24 wherein:
the first logic level and the fifth logic level are the same; and
the second logic level and the sixth logic level are the same.

26. The system of claim 24 wherein:
the first logic level and the sixth logic level are the same; and
the second logic level and the fifth logic level are the same.

27. The system of claim 22 wherein:
the first logic level and the third logic level are the same; and
the second logic level and the fourth logic level are the same.

28. The system of claim 22 wherein:
the first logic level and the fourth logic level are the same; and
the second logic level and the third logic level are the same.

29. A system for detecting an input signal and discharging a device, the system comprising:
a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal;
a second transistor including a fourth transistor terminal, a fifth transistor terminal and a sixth transistor terminal;
a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal; and
a first resistor including a first resistor terminal and a second resistor terminal;
wherein:
the third transistor terminal is connected to the fourth transistor terminal;
the third transistor terminal is connected to the first resistor terminal;
the second resistor terminal is connected to the seventh transistor terminal;

wherein:
the first transistor terminal is configured to receive an input signal;
the second transistor terminal is configured to receive a first drive signal;
the fifth transistor terminal is configured to receive a second drive signal; and
the eighth transistor terminal is configured to receive a third drive signal;

wherein in response to the first drive signal satisfying one or more first conditions and the second drive signal satisfying one or more second conditions,
turn on the first transistor and the second transistor; and
discharge the device through the first transistor and the second transistor;

wherein in response to the first drive signal satisfying the one or more first conditions and the third drive signal satisfying one or more third conditions,
turn on the first transistor and the third transistor; and
generate an output signal based on at least information associated with the input signal; and

wherein the first drive signal is equal to a logic AND of the second drive signal and the third drive signal.

30. The system of claim 29 wherein the output signal is generated at the second resistor terminal.

31. The system of claim 29, and further comprising a second resistor including a third resistor terminal and a fourth resistor terminal, the third resistor terminal being connected to the third transistor terminal, the fourth resistor terminal being connected to the fourth transistor terminal.

32. The system of claim 29 wherein each transistor terminal of the sixth transistor terminal and the ninth transistor terminal is biased to a voltage.

33. A system for detecting an input signal, the system comprising:
a sample signal generator configured to sample an input signal at a plurality of times during a time period and generate a plurality of sampled signals corresponding to the plurality of times respectively, the plurality of times including a first time and a second time after the first time, the plurality of sampled signals including a first sampled signal corresponding to the first time and a second sampled signal corresponding to the second time;
a comparator configured to receive the plurality of sampled signals and generate a comparison signal based on at least information associated with the plurality of sampled signals;
a counter configured to receive the comparison signal and change a value based on at least information associated with the comparison signal; and
a detector configured to generate a detection signal based at least in part on the value;
wherein the comparator is further configured to:
in response to the second sampled signal being smaller than a sum of the first sampled signal and an offset, generate the comparison signal at a first logic level; and
in response to the second sampled signal being larger than the sum of the first sampled signal and the offset, generate the comparison signal at a second logic level;

wherein the counter is further configured to:
increase the value by a first magnitude in response to the comparison signal being at the first logic level; and
decrease the value by a second magnitude in response to the comparison signal being at the second logic level; and

wherein the detector is further configured to change the detection signal from a third logic level to a fourth logic level in response to the value being larger than a first threshold after the time period, or is further configured to change the detection signal from the third logic level to the fourth logic level in response to the value being smaller than a second threshold after the time period.

34. The system of claim 33 further comprising:
a pulse generator configured to generate a first signal; and
wherein the sample signal generator is further configured to receive the first signal and the second signal and generate the plurality of sampled signals based at least in part on the first signal and the second control signal.

35. The system of claim 34 wherein the sample signal generator includes:
a first sampler configured to sample the input signal in response to the first signal being at a fifth logic level at the first time and generate a third sampled signal corresponding to the first time; and
a second sampler configured to receive the third sampled signal in response to the second signal being at a sixth logic level and generate the first sampled signal corresponding to the first time.

36. The system of claim 35 wherein the first sampled signal and the third sampled signal are the same.

37. The system of claim 35 wherein the fifth logic level and the sixth logic level are the same.

38. The system of claim 35 wherein the first sampler includes:
a first switch configured to be closed in response to the first signal being at the fifth logic level; and
a first capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being connected to the first switch.

39. The system of claim 35 wherein the second sampler includes:
a second switch configured to be closed in response to the second signal being at the sixth logic level;
a buffer connected to the second switch and configured to generate a buffer signal;
a third switch configured to be closed in response to the second signal being at the sixth logic level; and
a second capacitor including a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal being connected to the third switch.

40. The system of claim 35 wherein:
the first sampler is further configured to sample the input signal in response to the first signal being at the fifth logic level at the second time and generate the second sampled signal corresponding to the second time; and
the comparator is further configured to receive the first sampled signal and the second sampled signal and generate the comparison signal based at least in part on the first sampled signal and the second sampled signal.

41. The system of claim 34 wherein:
the pulse generator is further configured to generate a third signal; and
the counter is further configured to receive the third signal and change the value based on at least in part the third signal and the comparison signal.

42. The system of claim 33 wherein the first magnitude and the second magnitude are the same.

43. The system of claim 33 wherein:
the first logic level and the third logic level are the same; and
the second logic level and the fourth logic level are the same.

44. The system of claim 33 wherein:
the first logic level and the fourth logic level are the same; and
the second logic level and the third logic level are the same.

45. The system of claim 33 wherein the comparator is further configured to, in response to the first sampled signal being equal to the second sampled signal, generate the comparison signal at the first logic level.

46. The system of claim 33 wherein the comparator is further configured to, in response to the first sampled signal being equal to the second sampled signal, generate the comparison signal at the second logic level.

47. The system of claim 33 wherein the first logic level is a logic low level.

48. The system of claim 33 wherein the second logic level is a logic high level.

49. A system for discharging a capacitor, the system comprising:
a signal detector configured to receive an input signal and generate a detection signal based at least in part on the input signal, the input signal being associated with an alternate current signal; and
a discharge controller configured to receive the detection signal and generate an output signal to discharge a capacitor in response to the detection signal satisfying one or more conditions, the capacitor including a first capacitor terminal and a second capacitor terminal;
wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that, during a time period, the input signal changes monotonically over time, the time period being longer than half a period of the alternate current signal.

50. The system of claim 49 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that, during the time period, the input signal decreases monotonically over time.

51. The system of claim 49 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that, during the time period, the input signal increases monotonically over time.

52. The system of claim 49 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that the capacitor is disconnected from the alternate current signal.

53. The system of claim 49 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that during the time period, the input signal remains larger than a threshold.

54. The system of claim 49 wherein the discharge controller is further configured to generate the output signal to discharge the capacitor in response to the detection signal indicating that during the time period, the input signal remains smaller than a threshold.

55. The system of claim 49, and further comprising:
a first diode including a first diode terminal and a second diode terminal; and
a second diode including a third diode terminal and a fourth diode terminal;
wherein:
the second diode terminal is connected to the third diode terminal;
the first diode terminal is connected to the first capacitor terminal; and
the fourth diode terminal is connected to the second capacitor terminal.

56. The system of claim 55 wherein:
the second diode terminal and the third diode terminal are cathode terminals; and
the first diode terminal and the fourth diode terminal are anode terminals.

57. The system of claim 55 wherein the discharge controller is further configured to provide the output signal to the second diode terminal and the third diode terminal.

58. The system of claim 49, and further comprising:
a first resistor including a first resistor terminal and a second resistor terminal; and
a second resistor including a third resistor terminal and a fourth resistor terminal;
wherein:
the first resistor terminal is connected to the capacitor;
the second resistor terminal is connected to the third resistor terminal; and
the signal detector is further configured to receive the input signal from the second resistor terminal.

59. The system of claim 58 wherein the fourth resistor terminal is biased at a voltage.