# Patent

## Title
Circuits and methods of synchronizing differential ring-type oscillators

## Abstract

A circuit includes a first and second oscillator, a first and second phase comparator, and a control unit. The first and second oscillators are configured to respectively generate a first and second oscillating signal. The first and second phase comparators are connected between the first and second oscillators. The first phase comparator is configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal. The second phase comparator is configured to generate a second phase error signal according to the second signal and a delayed version of the first signal. The control unit is connected between the first and second phase comparators and configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.

## Background
PRIORITY CLAIM
The present application is a divisional application of U.S. application Ser. No. 14/621,583, filed Feb. 13, 2015, which is a continuation-in-part of U.S. application Ser. No. 14/319,787, filed Jun. 30, 2014, which is a continuation-in-part of U.S. application Ser. No. 14/075,021, filed Nov. 8, 2013, all of which are incorporated by reference herein in their entirety.


BACKGROUND
In an integrated circuit, a clock tree is generally used for distributing a common clock signal to various components in order to synchronize the operation thereof. Differences in the arrival time of the clock signals at two or more clocked components of the integrated circuit can result in errors in the operation of the integrated circuit. In some applications, the clock tree for the distribution of the common clock signal includes structures such as H-tree meshes or balanced buffer trees. In many cases, mismatch of the arrival of the distributed clock signals is minimized at the cost of sufficient driving current for distributing the common clock signal along the clock tree. With the increase of the frequency of the clock signal, power consumption for driving the clock tree increases. Also, clock buffers at various stages of the clock trees usually draw huge currents from a power supply grid, and thus affect the performance of nearby components by causing voltage drops of the supply voltage. In some applications, clock trees use 20% to 40% of total power consumption of the integrated circuits.



DESCRIPTION OF THE DRAWINGS
One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout.
FIG. 1 is a schematic diagram of two oscillators in accordance with one or more embodiments.
FIG. 2A is a schematic diagram of a capacitor array usable in one or both of the oscillators in FIG. 1 in accordance with one or more embodiments.
FIG. 2B is a schematic diagram of a varactor usable in one or both of the oscillators in FIG. 1 in accordance with one or more embodiments.
FIG. 3 is a schematic diagram of six oscillators in accordance with one or more embodiments.
FIG. 4 is a functional block diagram of a set of master-slave fine-tuning unit in accordance with one or more embodiments.
FIG. 5 is a schematic diagram of a pulse distribution network in accordance with one or more embodiments.
FIG. 6 is a flowchart of a method of synchronizing oscillators in accordance with one or more embodiments.
FIG. 7 is a schematic diagram of a ring oscillator in accordance with one or more embodiments.
FIG. 8 is a schematic diagram of another ring oscillator in accordance with one or more embodiments.
FIG. 9 is a top view of a coupling structure and corresponding inductive devices in accordance with one or more embodiments.
FIG. 10 is a diagram of coupling factor versus frequency between two inductive devices, with or without a coupling structure, in accordance with one or more embodiments.
FIGS. 11A-C are top views of coupling structures and corresponding inductive devices in accordance with one or more embodiments.
FIGS. 12A-E are top views of coupling structures and corresponding inductive devices in accordance with one or more embodiments.
FIGS. 13A-B are top views of coupling structures and corresponding inductive devices in accordance with one or more embodiments.
FIG. 14 is a top view of a coupling structure and corresponding inductive devices in accordance with one or more embodiments.
FIG. 15 is a top view of a coupling structure with shielding structures and corresponding inductive devices in accordance with one or more embodiments.
FIG. 16 is a flowchart of a method of magnetically coupling inductive devices in accordance with one or more embodiments.
FIG. 17 is a schematic diagram of an exemplary circuit in accordance with one or more embodiments.
FIG. 18 is a schematic diagram of an exemplary differential amplifier and an exemplary oscillator tuner in accordance with one or more embodiments.
FIG. 19 is a schematic diagram of another exemplary oscillator tuner in accordance with one or more embodiments.
FIG. 20 is a schematic block diagram of an exemplary master-slave fine-tuning unit in accordance with one or more embodiments.
FIG. 21 is a schematic diagram of an exemplary pulse distribution network in accordance with one or more embodiments.
FIG. 22 is a flowchart of an exemplary method of synchronizing a first differential ring-type oscillator and a second differential ring-type oscillator of a circuit in accordance with one or more embodiments.
FIG. 23 is a schematic diagram of another exemplary circuit in accordance with one or more embodiments.
FIG. 24 is a plot illustrating oscillating signals of oscillators of a circuit in accordance to one or more embodiments.
FIG. 25 is a plot illustrating another oscillating signals of oscillators of a circuit in accordance to one or more embodiments.



DETAILED DESCRIPTION
It is understood that the following disclosure provides one or more different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, examples and are not intended to be limiting. In accordance with the standard practice in the industry, various features in the drawings are not drawn to scale and are used for illustration purposes only.
In some embodiments, two or more oscillators configured to generated output oscillating signals having a predetermined frequency, instead of using a clock tree, is utilized to distribute a clock signals to various clocked components in an integrated circuit. Furthermore, one or more synchronization mechanisms are implemented to minimize frequency or phase differences among the oscillating signals generated by the two or more oscillators. In some embodiments, the one or more synchronization mechanisms include magnetic coupling, master-slave fine-tuning, and pulse injection.
FIG. 1 is a schematic diagram of two oscillators 100A and 100B in accordance with one or more embodiments. In some embodiments, oscillators 100A and 100B are configured to generate oscillating signals having a predetermined frequency. In some embodiments, frequencies of oscillating signals from oscillators 100A and 100B are approximately the same but not exactly equal to the predetermined frequency. Also, in some embodiments, phases of oscillating signals from oscillators 100A and 100B are not exactly synchronized. In some embodiments, synchronizing oscillators 100A and 100B refers to minimizing the frequency or phase differences between the oscillating signals from oscillators 100A and 100B. Although only two oscillators 100A and 100B are illustrated in conjunction with FIG. 1, the synchronization mechanisms illustrated in this disclosure are applicable to two or more similarly configured oscillators of a same integrated circuit.
Oscillator 100A includes an inductive device 110A, a capacitive device 120A, an active feedback device 130A, a switch device 140A, an output node 152A, and a complementary output node 154A. Inductive device 110A, capacitive device 120A, active feedback device 130A, and switch device 140A are coupled between output node 152A and complementary output node 152B.
Active feedback device 130A includes two N-type transistors 132A and 134A. Source terminals of transistors 132A and 134A are coupled with ground reference node 162A. A drain terminal of transistor 132A is coupled with node 152A and a gate terminal of transistor 134A, and a drain terminal of transistor 134A is coupled with node 154A and a gate terminal of transistor 132A. Active feedback device 130A is configured to output a first output oscillating signal at node 152A and a first complementary output oscillating signal at node 154A. The first output oscillating signal and the first complementary output oscillating signal have the predetermined frequency determined according to electrical characteristics of inductive device 110A and electrical characteristics of the capacitive device 120A. In some embodiments, if inductive device 110A has a inductance of LTOTAL and capacitive device 120A has a capacitance of CTOTAL, the predetermined frequency FOSC (in Hz) is determinable according to the following equation:




  
    F
    OSC
  
  =
  
    1
    
      2
      ⁢
      π
      ⁢
      
        
          
            L
            TOTAL
          
          ⁢
          
            C
            TOTAL
          
        
      
    
  




In some applications, oscillators having configurations similar to oscillator 100A are also known as “LC tank oscillators.” In some embodiments, transistors 132A and 134A are P-type transistors. In some embodiments, other types of active feedback devices are also usable as active feedback device 130A.
Inductive device 110A includes inductor 112A and inductor 114A integratedly formed as a conductive coil. Inductor 112A is coupled between node 152A and a supply reference node 164A, and inductor 114A is coupled between node 154A and supply reference node 164A.
Capacitive device 120A includes a coarse-tuning capacitor 122A and a fine-tuning capacitor 124A. In some embodiments, capacitance of coarse-tuning capacitor 122A is set according to a set of digital signals from bus 126A. In some embodiments, a coarse-tuning capacitor 122A is replaced by a set of hard-wired capacitors, and thus capacitance of coarse-tuning capacitor 122A is fixed and bus 126A is thus omitted. In some embodiments, capacitance of fine-tuning capacitor 124A is set according to an analog signal from path 128A. In some embodiments, a resonant frequency of oscillator 100A is adjustable by controlling coarse-tuning capacitor 122A or fine-tuning capacitor 124A.
Switch device 140A is configured to set signals at nodes 152A and 154A at corresponding predetermined voltage levels when switch device 140A is turned on. For example, when switch device 140A is turned on, node 152A and 154A are electrically coupled together. Under this circumstance, transistors 132A and 134A and inductors 112A and 114A function as a voltage divider, and signals at node 152A and 154A are set at a voltage level determinable according to impedance of transistors 132A and 134A and inductors 112A and 114A. In some embodiments, when switch device 140A is turned on, signals at node 152A and 154A are set at about the middle of voltage levels of the supply reference node 164A and ground reference node 162A.
Switches device 140A is controlled by a signal on path 170A. In some embodiments, the control signal on path 170A is a pulse signal used to force the crossing-over of oscillating signals at node 152A and 154A. Therefore, in the present application, switch device 140A is also referred to as a reset device or a pulse-injection device. In some embodiments, switch device 140A is a transistor. In some embodiments, switch device 140A is a P-type transistor, an N-type transistor, or a transmission gate. In some embodiments, switch device 140A is omitted.
Oscillator 100B includes an inductive device 110B, a capacitive device 120B, an active feedback device 130B, a switch device 140B, an output node 152B, and a complementary output node 154B. Oscillator 100B and Oscillator 100A have substantially the same configuration. Components of oscillator 100B similar to those of oscillator 100A are given similar reference numbers, except the corresponding suffixes are changed from ‘A’ to ‘B’. Features and functions of oscillator 100B are substantially similar to those advanced above with regard to oscillator 100A, and detailed description regarding oscillator 100B is thus not repeated.
In some embodiments, oscillator 100A and oscillator 100B are on a same substrate, different substrates on a same package substrate, different substrates of a stack of substrates, or different substrates of a stack of dies. In some embodiments, a power distribution network is implemented to cause supply reference nodes 164A and 164B to have substantially a same supply voltage level, and to cause ground reference nodes 162A and 162B to have substantially a same ground reference level. In some embodiments, digital signals on buses 126A and 126B have the same logic values.
In some embodiments, signals on path 170A and path 170B are provided by a signal distribution network based on a common signal. In some embodiments, signals on path 170A and path 170B are synchronized signals. In some embodiments, signals on path 170A and path 170B are pulse signals. In some embodiments, the predetermined frequency of output oscillating signals of oscillators 100A and 100B is an integer multiple of a frequency of signals on path 170A and path 170B.
Furthermore, inductive device 110A of oscillator 100A and inductive device 110B of oscillator 100B are magnetically coupled (as depicted by dotted arrow 180). Magnetic coupling between inductive device 110A and inductive device 110B refers to that magnetic flux generated by operating inductive device 110A affects operation of inductive device 110B, and vice versa. Similar to the location where oscillators 100A and 100B are disposed, in some embodiments, inductive device 110A and inductive device 110B are on a same substrate, different substrates on a same package substrate, different substrates of a stack of substrates, or different substrates of a stack of dies. Inductive device 110A and inductive device 110B are configured to attenuate out-of-phase components and enhance in-phase component of oscillating signals at node 152A of oscillator 100A and node 152B of oscillator 100B. As a result, after oscillator 100A and oscillator 100B are enabled, output oscillating signals at nodes 152A and 152B are eventually stabilized to be in-phase oscillating signals. In other words, inductive device 110A and inductive device 110B are configured to synchronize oscillating signals generated by oscillator 100A and oscillator 100B.
In some embodiments, inductive device 110A of oscillator 100A and inductive device 110B of oscillator 100B have a distance equal to or less than a predetermined distance in order to cause mutual-inductance sufficient to synchronize oscillator 100A and oscillator 100B within a predetermined period of time. In some embodiments, the predetermined distance is one half of a wavelength of an electromagnetic wave having the predetermined frequency of oscillating signals. In some embodiments, the predetermined frequency of output oscillating signals ranges from 100 MHz to 20 GHz.
FIG. 2A is a schematic diagram of a capacitor array 200 usable as coarse-tuning capacitor 122A or coarse-tuning capacitor 122B in accordance with one or more embodiments. Capacitor array 200 includes a first node 202, a second node 204, K transistors 212-1 to 212-K, and 2K capacitors 222-1 to 222-K and 224-1 to 224-K, where K is a positive integer. First node 202 and second node 204 are usable to be connected with the corresponding node 152A or node 154A, or to be connected with the corresponding node 152B or node 154B. Capacitors 222-1 to 222-K are coupled to first node 202, capacitors 224-1 to 224-K are coupled to second node 204, and transistors 212-1 to 212-K are coupled between corresponding pairs of capacitors 222-1 to 222-K and 224-1 to 224-K. Transistors 212-1 to 212-K function as switches and controlled by control signals B[0], B[1], to B[K−1].
In some embodiments, transistors 212-1 to 212-K are P-type transistors or N-type transistors. In some embodiments, transistors 212-1 to 212-K are replaced by transmission gates or other types of switches. In some embodiments, capacitors 222-1 to 222-K and 224-1 to 224-K are metal-oxide-metal capacitors or metal-insulator-metal capacitors.
In some embodiments, total capacitance of each path, including one of transistors 212-1 to 212-K, a corresponding capacitor of capacitors 222-1 to 222-K, and a corresponding capacitor of capacitors 224-1 to 224-K, has a same value. Under these circumstances, control signals B[0:K−1] are coded in a unary coding format. In some embodiments, total capacitance of each path as defined above corresponds to one of 20, 21, . . . 2K-1 times of a predetermined unit capacitance value. Under these alternative circumstances, control signals B[0:K−1] are coded in a binary coding format.
FIG. 2B is a schematic diagram of a varactor 250 usable as fine-tuning capacitor 124A or fine-tuning capacitor 124B in FIG. 1 in accordance with one or more embodiments. Varactor 250 includes a first node 252, a second node 254, a control node 256, and transistors 262 and 264. First node 252 and second node 254 are usable to be coupled with a corresponding node 152A or node 154A, or to be coupled with a corresponding node 152B or node 154B. Transistor 262 has a drain terminal and a source terminal coupled together with first node 252. Transistor 262 has a gate terminal coupled to the control node 256. Transistor 264 has a drain terminal and a source terminal coupled together with second node 254. Transistor 264 has a gate terminal coupled to the control node 256. Control node 256 is configured to receive an analog control signal VCAP, such as a control signal on path 128A or 128B. A total capacitance between nodes 252 and 254 is adjustable responsive to a voltage level of control signal VCAP. In some embodiments, transistors 262 and 264 are P-type transistors or N-type transistors.
In FIG. 1, only two oscillators 100A and 100B are depicted. However, in some embodiments, there are more than two oscillators for generating clocks in an integrated circuit. Also, the inductive device 110A or 110B of an oscillator 100A or 100B is capable of magnetically coupled with more than two inductive devices of two or more oscillators.
For example, FIG. 3 is a schematic diagram of six oscillators 300A to 300F in accordance with one or more embodiments. Oscillators 300A to 300F have a configuration similar to oscillator 100A described above. Among other things, oscillators 300A to 300F have corresponding inductive devices 310A to 310F. Other details of oscillators 300A to 300F are omitted.
As depicted in FIG. 3, inductive devices 310A and 310B are magnetically coupled (dotted arrow 380A); inductive devices 310B and 310C are magnetically coupled (dotted arrow 380B); inductive devices 310D and 310E are magnetically coupled (dotted arrow 380C); inductive devices 310E and 310F are magnetically coupled (dotted arrow 380D); inductive devices 310A and 310D are magnetically coupled (dotted arrow 380E); inductive devices 310B and 310E are magnetically coupled (dotted arrow 380F); and inductive devices 310C and 310F are magnetically coupled (dotted arrow 380G). In this embodiment, mutual-inductive coupling 380A to 380G are configured to cause oscillators 300A to 300F to generate oscillating signals having approximately a same predetermined frequency and approximately the same phase.
In some embodiments, inductive devices 310A to 310F are formed on a same substrate, different substrates on a same package substrate, different substrates of a stack of substrates, or different substrates of a stack of dies. In some embodiments, distances between two of inductive devices 310A to 310F that corresponds to one of magnetic coupling 380A to 380G is equal to or less than one half of a wavelength of an electromagnetic wave having the predetermined frequency. In some embodiments, the predetermined frequency of output oscillating signals ranges from 100 MHz to 20 GHz.
FIG. 4 is a functional block diagram of a set of master-slave fine-tuning unit 400 in accordance with one or more embodiments. The set of master-slave fine-tuning unit 400 is coupled to a mater oscillator 402 and a slave oscillator 404 and is capable of controlling a resonant frequency of slave oscillator 404 based on comparing output oscillating signals of master oscillator 402 and the slave oscillator 404. In some embodiments, master oscillator 402 corresponds to oscillator 100B in FIG. 1, slave oscillator 404 corresponds to oscillator 100A, and resonant frequency of slave oscillator 404 is adjustable by controlling fine-tuning capacitor 124A.
The set of master-slave fine-tuning unit 400 includes a first phase comparator 412, a second phase comparator 414, a control unit 416, a first conductive path 422, a second conductive path 424, a first frequency divider 432, and a second frequency divider 434.
First frequency divider 432 is disposed adjacent to and electrically coupled to master oscillator 402. First frequency divider 432 is configured to receive an output oscillating signal CLK_M from master oscillator 402 and to generate a reference signal CLK_MR by frequency-dividing the output oscillating signal CLK_M by a predetermined ratio N. In some embodiments, N is a positive integer. In some embodiments, N ranges from 4 to 16. Second frequency divider 434 is disposed adjacent to and electrically coupled to slave oscillator 402. Second frequency divider 434 is configured to receive an output oscillating signal CLK_S from slave oscillator 404 and to generate a reference signal CLK_SR by frequency-dividing the output oscillating signal CLK_S by the predetermined ratio N.
In some embodiments, first frequency divider 432 and second frequency divider 434 are omitted, and oscillating signals CLK_M and CLK_S are used as reference signal CLK_MR and reference signal CLK_SR.
First phase comparator 412 is disposed adjacent to the master oscillator 402. Second phase comparator 414 is disposed adjacent to the slave oscillator 404. First conductive path 422 and second conductive path 424 are disposed between master oscillator 402 and slave oscillator 404. First phase comparator 412 is configured to generate a first phase error signal 442 according to reference signal CLK_MR from master oscillator 402 and a delayed version CLK_SR′ of reference signal CLK_SR from the slave oscillator 404 transmitted through first conductive path 422. Second phase comparator 422 is configured to generate a second phase error signal 444 according to reference signal CLK_SR from slave oscillator 404 and a delayed version CLK_MR′ of reference signal CLK_MR from the master oscillator 402 transmitted through the second conductive path 424.
Control unit 416 is configured to generate a tuning signal VTUNE to slave oscillator 404 according to first phase error signal 442 and second phase error signal 444. In some embodiments, tuning signal VTUNE is usable as analog control signal VCAP of FIG. 2B or as analog control signal for adjusting fine-tuning capacitor 124A carried by path 128A of FIG. 1.
FIG. 5 is a schematic diagram of a pulse distribution network 500 in accordance with one or more embodiments. In some embodiments, pulse distribution network 500 is usable to provide a control signal to switch device 140A of oscillator 100A through path 170A and a control signal to switch device 140B of oscillator 100B through path 170B.
Pulse distribution network 500 includes a pulse generator 510, a driver 520, and one or more conductive paths arranged to have an H-tree configuration. Two or more oscillators 532 and 534 are coupled to two of ends of the H-tree. In some embodiments, oscillator 532 corresponds to oscillator 100A in FIG. 1, and oscillator 532 corresponds to oscillator 100B.
Pulse generator 510 is configured to generate a pulse signal usable as control signals for switch devices or reset devices of corresponding oscillators. In some embodiments, the pulse signal has a pulse frequency, and the predetermined frequency of output oscillating signals of oscillators 532 and 534 is an integer multiple of the pulse frequency. The pulse signal is transmitted to oscillators 532 and 534 in order to set output oscillating signals at predetermined voltage levels by corresponding switch devices of the oscillators responsive to the pulse signal. Thus, a timing of rising edges or falling edges of output oscillating signals of oscillators 532 and 534 are synchronized according to the pulse signal.
The H-tree depicted in FIG. 5 is a five-level H-tree including one (20) first level conductive path 541, two (21) second level conductive paths 543a and 543b coupled to corresponding ends of path 541, four (23) third level conductive paths 545a, 545b, 545c, and 545d coupled to corresponding ends of paths 543a or 543b, eight (23) fourth level conductive paths 547a to 547i coupled to corresponding ends of paths 545a to 545d, and 16 (24) fifth level conductive paths 549a to 549p coupled to corresponding ends of paths 547a to 547i. Fifth level conductive paths 549a to 549p have ends connected to corresponding switch devices of various oscillators. For example, one end of path 549a is coupled to oscillator 532, and one end of path 549b is coupled to oscillator 534. In some embodiments, each ends of fifth level conductive paths 539a to 539p has a same routing distance. Therefore, conductive paths from driver 520 to corresponding ends of fifth level conductive paths 549a to 549p are configured to impose substantially the same delay to the pulse signal during the transmission and distribution thereof.
Driver 520 is configured to provide sufficient current driving capability to transmit the pulse signal generated by pulse generator 510 to various ends of the fifth level conductive paths 549a to 549p. In some embodiments, additional drivers 552, 554, 556, and 558 are at ends of second level conductive paths 543a and 543b. In some embodiments, additional drivers 552, 554, 556, and 558 are omitted. In some embodiments, additional drivers 552, 554, 556, and 558 are disposed at corresponding ends of a different level of conductive paths in the H-tree.
Therefore, at least three different ways to synchronize output oscillating signals of two or more oscillators, such as oscillators 100A and 100B in FIG. 1, are described above: magnetic coupling (illustrated with reference to FIGS. 1 and 3); master-slave fine-tuning (illustrated with reference to FIG. 4); and pulse injection (illustrated with reference to FIG. 5). In some embodiments, two or more oscillators 100A and 100B are synchronized using magnetic coupling and master-slave fine-tuning mechanisms. In some embodiments, two or more oscillators 100A and 100B are synchronized using magnetic coupling and pulse injection mechanisms. In some embodiments, two or more oscillators 100A and 100B are synchronized using magnetic coupling, master-slave fine-tuning, and pulse injection mechanisms.
FIG. 6 is a flowchart of a method 600 of synchronizing oscillators, such as oscillators 100A and 100B depicted in FIG. 1, in accordance with one or more embodiments. It is understood that additional operations may be performed before, during, and/or after the method 600 depicted in FIG. 6, and that some other processes may only be briefly described herein.
In operation 610, oscillators are operated to output oscillating signals. For example, in some embodiments, oscillator 100A is operated to output a first oscillating signal at node 152A, and oscillator 100B is operated to output a second oscillating signal at node 152B.
In operation 620, inductive devices of oscillators are magnetically coupled. For example, in some embodiments, inductive device 110A of oscillator 100A and inductive device 110B of oscillator 100B are magnetically coupled in order to reduce a frequency difference or phase difference between output oscillating signals of oscillator 100A and oscillator 100B.
In operation 630, a pulse injection process is performed on various oscillators. For example, in some embodiments, a pulse injection process is performed on oscillator 100A and oscillator 100B. In some embodiments, operation 630 includes generating a pulse signal (operation 632), transmitting the pulse signal to switch device 140A of oscillator 100A through a first conductive path, and transmitting the pulse signal to switch device 140B of oscillator 100B through a second conductive path. In some embodiments, the first conductive path and the second conductive path are configured to impose substantially a same delay to the pulse signal.
In some embodiments, operation 630 further includes setting the first oscillating signal of oscillator 100A at a first predetermined voltage level by switch device 140A responsive to the pulse signal (operation 634), and setting the second oscillating signal of oscillator 100B at a first predetermined voltage level by switch device 140B responsive to the pulse signal (operation 636).
The method proceeds to operation 640, where a master-slave fine-tuning process is performed on two or more oscillators. For example, in some embodiments, a master-slave fine-tuning process is performed on oscillator 100A and oscillator 100B. As depicted in FIGS. 6 and 4, operation 640 includes generating reference signal CLK_MR by frequency-dividing oscillating signal from oscillator 402 or 100B by a predetermined ratio (operation 642); and generating reference signal CLK_SR by frequency-dividing oscillating signal from oscillator 404 or 100A by the predetermined ratio (operation 643).
Furthermore, in operation 645, a first phase error signal 442 is generated based on reference signal CLK_MR and delayed version CLK_SR′ of reference signal CLK_SR transmitted through conductive path 422. In operation 646, a second phase error signal 444 is generated based on reference signal CLK_SR and a delayed version CLK_MR′ of reference signal CLK_MR transmitted through conductive path 424. In operation 648, a tuning signal VTUNE is generated based on the first phase error signal 422 and the second phase error signal 424.
As depicted in FIGS. 6 and 1, in operation 649, a frequency or a phase of oscillating signal generated by oscillator 404 or 100A is adjusted based on the tuning signal VTUNE.
In some embodiments when synchronizing oscillators 100A and 100B of FIG. 1, either or both of operation 630 or operation 640 is/are omitted.
Moreover, the pulse distribution network 500 in FIG. 5 and pulse-injection process (operation 630) are applicable to other type of oscillators and not limited to LC tank oscillators. In some embodiments, pulse-injection process or pulse-injection mechanism described above is also applicable to a particular type of oscillator known as ring oscillators.
For example, FIG. 7 is a schematic diagram of a ring oscillator 700 in accordance with one or more embodiments. Oscillator 700 has an output node 702 and P inverters 710-1 to 710-P, where P is an odd integer. Inverters 710-1 to 710-P are connected in series. Furthermore, output terminal of the last stage inverter 710-P is coupled with output node 702, and input terminal of the first stage inverter 710-1 is coupled with output terminal of inverter 710-P. Inverters 710-1 to 710-P are configured to be an active feedback device and to generate an oscillating signal at output node 702. Another inverter 720 has an input terminal configured to receive a pulse signal and an output terminal coupled with first node 702. Inverter 720 functions as a reset device configured to set output oscillating signal at node 704 at a predetermined voltage level responsive to the pulse signal. In some embodiments, two or more ring oscillators similar to oscillator 700 (e.g., oscillators 532 and 534 in FIG. 5) are connected to various ends of a pulse distribution network similar to pulse distribution network 500 in order to synchronizing output oscillating signals of the two or more ring oscillators.
FIG. 8 is a schematic diagram of another ring oscillator 800 in accordance with one or more embodiments. Oscillator 800 has a pair of output nodes 802 and 804 and Q differential amplifiers 810-1 to 810-Q, where Q is an odd integer. Amplifiers 810-1 to 810-Q are connected in series. Output terminals of the last stage amplifier 810-Q are coupled with output nodes 802 and 804, and input terminals of the first stage amplifier 810-1 are coupled with output terminals of amplifier 810-Q. Amplifiers 810-1 to 810-Q are configured as an active feedback device and to generate a pair of differential oscillating signals at output nodes 802 and 804. One of the amplifiers, such as amplifier 810-1, further includes a switch device or a reset device configured to set output terminals of that amplifier 810-1 at a predetermined voltage level responsive to a pulse signal. In some embodiments, any differential amplifier among amplifiers 810-1 to 810-Q is usable for pulse signal injection. In some embodiments, two or more ring oscillators similar to oscillator 800 (e.g., oscillators 532 and 534 in FIG. 5) are connected to various ends of a pulse distribution network similar to pulse distribution network 500 in order to synchronizing output oscillating signals of the two or more ring oscillators.
FIG. 9 is a top view of a portion of a circuit 900 including a coupling structure 910 and corresponding first and second inductive devices 922 and 924 in accordance with one or more embodiments. In some embodiments, inductive devices 922 and 924 correspond to inductive devices 110A and 110B in FIG. 1 or inductive devices 310A to 310F in FIG. 3. In some embodiments, coupling structure 910 is configured to facilitate the magnetic coupling 180 in FIG. 1 or magnetic coupling 308A to 380G in FIG. 3.
Coupling structure 910 includes a first conductive loop 912, a second conductive loop 914, and a set of conductive paths 916 electrically connecting first conductive loop 912 and second conductive loop 914. First conductive loop 912 and second conductive loop 914 have a shape of an octagon loop. In some embodiments, first conductive loop 912 and second conductive loop 914 have a shape of a polygon loop or a circular loop. First conductive loop 912, second conductive loop 914, and the set of conductive paths 916 are formed in various interconnection layers of one or more chips. First conductive loop 912 surrounds the first inductive device 922 as observed from a top view perspective. Second conductive loop 914 surrounds the second inductive device 924 as observed from the top view perspective.
First inductive device 922 has a signal port 922a corresponding to an opening of a coil of inductive device 922, a center of the coil 922b, and a port direction 922c. Second inductive device 924 has a signal port 924a corresponding to an opening of a coil of inductive device 924, a center of the coil 924b, and a port direction 924c. In FIG. 10, port directions 922c and 924c point to the same direction. In some embodiments, port directions 922c and 924c point to different directions.
First conductive loop 912 includes a first end 912a and a second end 912b. Second conductive loop 914 includes a first end 914a and a second end 914b. The set of conductive paths 916 includes a first conductive path 916a and a second conductive path 916b. First conductive path 916a electrically connects first end 912a of first conductive loop 912 and first end 914a of second conductive loop 914. Second conductive path 916b electrically connects second end 912b of first conductive loop 912 and second end 914b of second conductive loop 914. A length L is defined as the length of a space between first conductive loop 912 and second conductive loop 914. In some embodiments, length L is equal to or greater than 100 μm.
In some embodiments, an induced current is generated at first conductive loop 912 responsive to a first magnetic field generated by first inductive device 922. The induced current is transmitted to second conductive loop 914 through the set of conductive paths 916 and generates a second magnetic field within the second conductive loop 914. Accordingly, a mutual inductance between the first and second inductive devices 922 and 924 is less dependent from the field distribution of first magnetic field and more dependent from the second magnetic field reproduced by the induced current. As a result, a mutual inductance between the first and second inductive devices 922 and 924 is independent of a distance between inductive devices 922 and 924, such as when the length L is equal to or greater than 100 μm.
FIG. 10 is a diagram of coupling factor K versus frequency Freq between two inductive devices, such as inductive devices 922 and 924, with or without a coupling structure, in accordance with one or more embodiments. Curve 1010 represents a coupling factor K between inductive devices 922 and 924 when there is no coupling structure 910 and a distance therebetween is set to be 1000 μm. Curve 1020a represents a coupling factor K between inductive devices 922 and 924, with coupling structure 910 and a length L set to be 500 μm; curve 1020b represents a coupling factor K if length L is 1000 μm; curve 1020c represents a coupling factor K if length L is 2000 μm; curve 1020d represents a coupling factor K if length L is 3000 μm; and curve 1020e represents a coupling factor K if length L is 5000 μm. Reference line 1030 represents a K value of 0.001 (10−3).
Coupling factor K is defined as:




  K
  =
  
    M
    
      
        
          L
          1
        
        ⁢
        
          L
          2
        
      
    
  




M is the mutual conductance between inductive devices 922 and 924, L1 is the self-inductance of first inductive device 922, and L2 is the self-inductance of first inductive device 924. If the K value is greater than 0.001 (reference line 1030), oscillators corresponding to inductive devices 922 and 924 have meaningful magnetic coupling sufficient to maintain a stable phase difference therebetween.

As shown by curve 1010 in FIG. 10, at a distance of 1000 μm, a configuration without coupling structure 910 no longer ensures sufficient magnetic coupling between inductive devices 922 and 924. In contrast, curves 1020a-1020e demonstrate that an embodiment with coupling structure 910 renders the magnetic coupling between inductive devices 922 and 924 independent of the distance therebetween. As shown in FIG. 10, after 500 MHz, curves 1020a-1020e are all above reference line 1030 for length L set to 500, 1000, 2000, 3000, or 5000 μm.
Some possible variations along the embodiment of FIG. 9 are further illustrated in conjunction with FIGS. 11A-15. In some embodiments, variations as illustrated in FIGS. 11A-15 are combinable to form yet a different variation consistent with the ideas as demonstrated in conjunction with FIG. 9 and FIGS. 11A-15.
FIG. 11A is a top view of a coupling structure 910A and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. The components the same or similar to those in FIG. 9 are given the same reference numbers, and detailed description thereof is omitted.
Compared with coupling structure 910, coupling structure 910A includes a set of conductive paths 916A in place of the set of conductive paths 916. The set of conductive paths 916A includes a first conductive path 916Aa and a second conductive path 916Ab. First conductive path 916Aa and second conductive path 916Ab are routed such that first conductive path 916Aa crosses over second conductive path 916Ab at location 1110 as observed from a top view perspective.
FIG. 11B is a top view of a coupling structure 910B and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. The components the same or similar to those in FIG. 9 are given the same reference numbers, and detailed description thereof is omitted.
Compared with coupling structure 910, coupling structure 910B includes a set of conductive paths 916B in place of the set of conductive paths 916. The set of conductive paths 916B includes a first conductive path 916Ba and a second conductive path 916Bb. First conductive path 916Ba and second conductive path 916Bb are routed such that each one of first conductive path 916Ba and second conductive path 916Bb has an angled corner at location 1120 as observed from a top view perspective.
FIG. 11C is a top view of a coupling structure 910C and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. The components the same or similar to those in FIG. 9 are given the same reference numbers, and detailed description thereof is omitted.
Compared with coupling structure 910, coupling structure 910C includes a set of conductive paths 916C in place of the set of conductive paths 916. The set of conductive paths 916C includes a first conductive path 916Ca and a second conductive path 916Cb. First conductive path 916Ca and second conductive path 916Cb are routed such that each one of first conductive path 916Ca and second conductive path 916Cb has an angled corner at location 1130 as observed from a top view perspective. Also, first conductive path 916Ca crosses over second conductive path 916Cb at location 1130 as observed from the top view perspective.
FIG. 12A is a top view of a coupling structure 1210A and corresponding inductive devices 1222 and 1224 in accordance with one or more embodiments. Coupling structure 1210A includes a first conductive loop 1212A, a second conductive loop 1214A, a first set of conductive paths 1216A electrically connecting conductive loops 1212A and 1214A, a third conductive loop 1212B, a fourth conductive loop 1214B, and a second set of conductive paths 1216B electrically connecting conductive loops 1212B and 1214B. A first inductive device 1222 is magnetically coupled with first conductive loop 1212A. A second inductive device 1224 is magnetically coupled with third conductive loop 1212B. Second conductive loop 1214A is magnetically coupled with fourth conductive loop 1214B. Second conductive loop 1214A surrounds fourth conductive loop 1214B as observed from a top view perspective.
In some embodiments, a first induced current is generated at first conductive loop 1212A responsive to a first magnetic field generated by first inductive device 1222. The first induced current is transmitted to second conductive loop 1214A through the first set of conductive paths 1216A and generates a second magnetic field within second conductive loop 1214A. A second induced current is generated at fourth conductive loop 1214B responsive to the second magnetic field. The second induced current is transmitted to third conductive loop 1214B through the second set of conductive paths 1216B and generates a third magnetic field within third conductive loop 1214B. Accordingly, second inductive device 1224 is magnetically coupled with first inductive device 1222 through the third magnetic field reproduced by the second induced current within third conductive loop 1214B.
FIG. 12B is a top view of a coupling structure 1210B and corresponding inductive devices 1222 and 1224 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 12A are given the same reference numbers, and detailed description thereof is omitted. Compared with coupling structure 1210A, second conductive loop 1214A and fourth conductive loop 1214B overlap as observed from a top view perspective. In other words, second conductive loop 1214A and fourth conductive loop 1214B have the same size and shape but formed on different interconnection layers.
FIG. 12C is a top view of a coupling structure 1210C and corresponding inductive devices 1222, 1224, and 1226 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 12A are given the same reference numbers, and detailed description thereof is omitted. Compared with coupling structure 1210A, second conductive loop 1214A and fourth conductive loop 1214B are arranged to magnetically couple with an additional inductive device 1226. Also, fourth conductive loop 1214B surrounds second conductive loop 1214A as observed from a top view perspective.
FIG. 12D is a top view of a coupling structure 1210D and corresponding inductive devices 1222, 1224, and 1226 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 12B are given the same reference numbers, and detailed description thereof is omitted. Compared with coupling structure 1210B, second conductive loop 1214A and fourth conductive loop 1214B are arranged to magnetically couple with an additional inductive device 1226.
FIG. 12E is a top view of a coupling structure 1210E and corresponding inductive devices 1222, 1224, and 1226 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 12D are given the same reference numbers, and detailed description thereof is omitted. Compared with coupling structure 1210D, a set of conductive paths 1216B′ is used in place of second set of conductive paths 1216B, where one conductive path of the set of conductive paths 1216B′ crosses over another conductive path of the set of conductive paths 1216B′ at location 1230.
FIG. 13A is a top view of a coupling structure 1310A and corresponding inductive devices 1322, 1324, and 1326 in accordance with one or more embodiments. Coupling structure 1310A includes three conductive loops 1312, 1314, and 1316 electrically coupled together through a set of conductive paths 1318. Each one of conductive loops 1312, 1314, and 1316 is magnetically coupled with a corresponding one of inductive devices 1322, 1324, and 1326.
FIG. 13B is a top view of a coupling structure 1310B and corresponding inductive devices 1322, 1324, 1326, and 1327 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 13A are given the same reference numbers, and detailed description thereof is omitted. Coupling structure 1310B includes four conductive loops 1312, 1314, 1316, and 1317 electrically coupled together through a set of conductive paths 1318. Each one of conductive loops 1312, 1314, 1316, and 1317 is magnetically coupled with a corresponding one of inductive devices 1322, 1324, 1326, and 1327.
FIG. 14 is a top view of a coupling structure 1410 and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 9 are given the same reference numbers, and detailed description thereof is omitted. Coupling structure 1410 includes two conductive loops 1412 and 1414 electrically coupled together through a set of conductive paths 1416. Each one of conductive loops 1412 and 1416 is magnetically coupled with a corresponding one of inductive devices 922 and 924. Moreover, inductive device 922 surrounds conductive loop 1412 as observed from a top view perspective; and inductive device 924 surrounds conductive loop 1414 as observed from the top view perspective.
FIG. 15 is a top view of a coupling structure 910 with shielding structures 1512 and 1514 and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Components that are the same or similar to those in FIG. 9 are given the same reference numbers, and detailed description thereof is omitted. Compared with the circuit 900 in FIG. 9, the circuit depicted in FIG. 15 further includes a first shielding structure 1512 and a second shielding structure 1514. At least a portion of the set of conductive paths 916 is between first shielding structure 1512 and second shielding structure 1514 as observed from a top view perspective.
FIG. 16 is a flowchart of a method 1600 of magnetically coupling inductive devices in accordance with one or more embodiments. In some embodiments, method 1600 is usable in conjunction with the circuit in FIG. 9 or FIG. 12A. In some embodiments, method 1600 is also usable in conjunction with the circuit in FIGS. 11A-11C, FIGS. 12B-12E, or FIGS. 13A-15. It is understood that additional operations may be performed before, during, and/or after the method 1600 depicted in FIG. 16, and that some other processes may only be briefly described herein.
The process begins with operation 1610, where an induced current is generated at a first conductive loop 912 or 1212A responsive to a first magnetic field of a first oscillator generated by a first inductive device 922 or 1222.
The process proceeds to operation 1620, where the induced current is transmitted to a second conductive loop 914 or 1214A through a set of conductive paths 916 or 1216A electrically connecting the first and second conductive loops.
The process proceeds to operation 1630, where a second magnetic field is generated responsive to the induced current passing the second conductive loop 914 or 1214A.
For a coupling structure having a configuration the same or similar to FIG. 12A or FIGS. 12B-E, the process proceeds to operation 1640, where another induced current is generated at a third conductive loop 1214B responsive to the second magnetic field.
The process proceeds to operation 1650, where the another induced current is transmitted to a fourth conductive loop 1212B through another set of conductive paths 1216B electrically connecting the third and fourth conductive loops.
As a result, a second inductive device 924 or 1224 of a second oscillator is magnetically coupled with the first inductive device 922 or 1222 of the first oscillator through the coupling structure 910 or 1210.
FIG. 17 is a schematic diagram of an exemplary circuit 1700 in accordance with one or more embodiments. The circuit 1700 includes a pair of oscillators 1710, 1720 and a coupling structure 1750.
Each of the oscillators 1710, 1720 includes a plurality of differential amplifiers 1730 and a pair of differential output nodes 1760, 1770. Each of the differential amplifiers 1730 has differential input terminals (Ip, In) and differential output terminals (Op, On). The differential amplifiers 1730 are connected in series to form a loop. The input terminal (Ip) of the first differential amplifier 1730 in the series and the output terminal (Op) of the last differential amplifier 1730 in the series are connected to each other and to the output node 1760. The input terminal (In) of the first differential amplifier 1730 in the series and the output terminal (On) of the last differential amplifier 1730 in the series are connected to each other and to the output node 1770.
Since each of the oscillators 1710, 1720 includes differential amplifiers 1730 that are connected in series, forming a loop, each of the oscillators 1710, 1720 may be termed a differential ring-type oscillator.
The oscillator 1710 is configured to generate an oscillating signal OS1 at the output node 1760 thereof and a complementary oscillating signal COS1 at the output node 1770 thereof. Similarly, the oscillator 1720 is configured to generate an oscillating signal OS2 at the output node 1760 thereof and a complementary oscillating signal COS2 at the output node 1770 thereof. The frequency (f) of the oscillating signal OS1, OS2, COS1, COS2 is given, e.g., by:

f=1⁄2Ntd 

where N is the number of the differential amplifiers 1730 and td is the delay of the differential amplifier 1730.

The coupling structure 1750 capacitively couples the oscillators 1710, 1720. The construction as such permits reduction of phase difference and frequency difference between the oscillating signals OS1, OS2 and phase difference and frequency difference between the complementary oscillating signals COS1, COS2. In this exemplary embodiment, the coupling structure 1750 includes a pair of metal strips 1780a, 1780b, a pair of capacitors 1790a, another pair of capacitors 1790b, and a metal plate 1780c. Each of the capacitors 1790a has a first capacitor terminal connected to the output node 1770 of a respective one of the oscillators 1710, 1720, and a second capacitor terminal connected to the metal strip 1780a through an interconnect, e.g., a via. Each of the capacitors 1790b has a first capacitor terminal connected to the output node 1760 of the respective one of the oscillators 1710, 1720, and a second capacitor terminal connected to the metal strip 1780b through an interconnect.
In some embodiments, one of the capacitors 1790a is dispensed with and the output node 1770 is connected to the metal strip 1780a through an interconnect. In some embodiments, one of the capacitors 1790b is dispensed with and the output node 1760 is connected to the metal strip 1780b through an interconnect.
The oscillators 1710, 1720 are formed into a substrate. The metal strips 1780a, 1780b are disposed above the substrate and are symmetrical. The metal plate 1780c is disposed under the metal strips 1780a, 1780b, is connected to ground, and is configured to isolate the metal strips 1780a, 1780b from the substrate. In some embodiments, the substrate is a bulk substrate. In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate. Examples of materials for the metal strips 1780a, 1780b and the metal plate 1780c include, but are not limited to, Al, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, another metal material, an alloy of metal material and semiconductor material, and a combination thereof.
The circuit 1700 further includes a master-slave fine-tuning unit. FIG. 20 is a schematic block diagram of an exemplary master-slave fine-tuning unit 2000 in accordance with one or more embodiments. When compared to the master-slave fine-tuning unit 400 of FIG. 4, the control unit 2010 of the master-slave fine-tuning unit 2000 is configured to generate either a tuning signal VTUNE or a pulse signal according to the first and second phase error signals 442, 444 based on the difference between the first and second phase error signals 442, 444. In this exemplary embodiment, the control unit 2010 generates the tuning signal VTUNE according to the first and second phase error signals 442, 444 when the difference between the first and second phase error signals 442, 444 is greater than a threshold value and generates the pulse signal according to the first and second phase error signals 442, 444 when the difference between the first and second phase error signals 442, 444 is less than the threshold value. The use of the tuning signal VTUNE and the pulse signal is described in further detail below in the context of the circuit 1700 of FIG. 17. In this exemplary embodiment, the master oscillator 402 and the slave oscillator 404 correspond to the oscillators 1710, 1720, respectively.
Referring back to FIG. 17, the oscillator 1720 further includes a first oscillator tuner 1740 configured to further reduce the frequency difference between the oscillating signals OS1, OS2 and the frequency difference between the complementary oscillating signals COS1, COS2 using the tuning signal VTUNE. In this exemplary embodiment, the first oscillator tuner 1740 includes a plurality of current generators 1740a and a node 1740b. Each of the current generators 1740a has an input terminal and an output terminal. The input terminals of the current generators 1740a are connected to each other and to the node 1740b. The node 1740b, to which the tuning signal VTUNE is applied, is connected to the control unit 2010 of the master-slave fine-tuning unit 2000 of FIG. 20. The output terminal of each of the current generators 1740a is connected to a respective one of the differential amplifiers 1730 of the oscillator 1720.
FIG. 18 is a schematic diagram of an exemplary differential amplifier, e.g., the differential amplifier 1730, and an exemplary current generator of an oscillator tuner, e.g., the current generator 1740a of the first oscillator tuner 1740, in accordance with one or more embodiments.
As depicted in FIG. 18, the differential amplifier 1730 includes a pair of transistors 1810, 1820, a pair of resistors 1830, 1840, and a node 1850. In this exemplary embodiment, each of the transistors 1810, 1820 is an N-type transistor, and has a gate terminal, a drain terminal, and a source terminal. The gate terminal of each of the transistors 1810, 1820 serves as a respective one of the input terminals (Ip, In) of the differential amplifier 1730. The drain terminal of each of the transistors 1810, 1820 serves as a respective one of the output terminals (On, Op) of the differential amplifier 1730. The source terminals of the transistors 1810, 1820 are connected to each other and to the node 1850. Each of the resistors 1830, 1840 is connected between a supply voltage and the drain terminal of a respective one of the transistors 1810, 1820.
As also depicted in FIG. 18, the current generator 1740a includes a pair of transistors 1860, 1870 and a node 1880. In this exemplary embodiment, each of the transistors 1860, 1870 is an N-type transistor, and has a gate terminal, a drain terminal, and a source terminal. The gate terminal and the drain terminal of the transistor 1860 are connected to each other and to the node 1880. The node 1880 serves as the input terminal of the current generator 1740a. The gate terminal of the transistor 1870 is connected to the gate terminal of the transistor 1860. The drain terminal of the transistor 1870 is connected to the node 1850 and serves as the output terminal of the current generator 1740a. The source terminals of the transistors 1860, 1870 are connected to the ground.
In operation, when the tuning signal VTUNE is applied to the node 1880, the transistor 1860 generates a tuning current according to the tuning signal VTUNE, and the transistor 1870 generates a current that mirrors the tuning current generated by the transistor 1860 and that flows to the node 1850. When the tuning current increases, a parasitic capacitance, e.g., the gate-source parasitic capacitance, of each of the transistors 1810, 1820 decreases. This causes a charging time of the differential amplifier 1730 to decrease. This, in turn, causes the frequencies of the oscillating signals OS2, COS2 to increase. Conversely, when the tuning current decreases, the parasitic capacitance increases. This causes the charging time to increase. This, in turn, causes the frequencies of the oscillating signals OS2, COS2 to decrease, whereby the first oscillator tuner 1740 further reduces the frequency difference between the oscillating signals OS1, OS2 and the frequency difference between the complementary oscillating signals COS1, COS2 using the tuning signal VTUNE.
Referring back to FIG. 17, each of the oscillators 1710, 1720 further includes a second oscillator tuner 1745 configured to set the oscillating signal OS1 and the complementary oscillating signal COS1 to be substantially 180 degrees out of phase and the oscillating signal OS2 and the complementary oscillating signal COS2 to be substantially 180 degrees out of phase using the pulse signal. In this exemplary embodiment, each of the second oscillator tuners 1745 includes an input terminal connected to the control unit 2010 of the master-slave fine-tuning unit 2000 and for receiving the pulse signal, a first output terminal connected to the input terminal (Ip) of the last differential amplifier 1730 of a respective one of the oscillators 1710, 1720, and a second output terminal connected to the input terminal (In) of the last differential amplifier 1730 of the respective one of the oscillators 1710, 1720. In some embodiments, the first and second output terminals of the second oscillator tuner 1745 are respectively connected to the input terminals (Ip, In) of one of the differential amplifiers 1730 other than the last differential amplifier 1730.
FIG. 19 is a schematic diagram of an exemplary second oscillator tuner, e.g., the second oscillator tuner 1745, in accordance with one or more embodiments. The second oscillator tuner 1745 includes a pair of transistors 1910, 1920, a first node 1930, a second node 1940, and a voltage source 1950. In this exemplary embodiment, each of the transistors 1910, 1920 is an N-type transistor, and includes a drain terminal, a source terminal, and a gate terminal. The drain terminal of each of the transistors 1910, 1920 serves as a respective one of the first and second output terminals of the second oscillator tuner 1745. The source terminals of the transistors 1910, 1920 are connected to each other and to the first node 1930. The voltage source 1950 is connected to the first node 1930, and is configured, in this exemplary embodiment, to generate a common mode voltage of the differential amplifier 1730 or half of the supply voltage. The gate terminals of the transistors 1910, 1920 are connected to each other and to the second node 1940. The second node 1940 serves as the input terminal of the second oscillator tuner 1745.
In operation, when the second node 1940 receives the pulse signal, the drain terminal of the transistor 1910 generates a first reset voltage according to the pulse signal and the drain terminal of the transistor 1920 generates a second reset voltage also according to the pulse signal. This resets the oscillating signals OS1, OS2 to start to rise from a level of the first reset voltage and the complementary oscillating signals COS1, COS2 to start to fall from a level of the second reset voltage, thereby synchronizing timing of rising edges of the oscillating signals OS1, OS2 and timing of falling edges of the complementary oscillating signals COS1, COS2, whereby the second oscillator tuner 1745 sets the oscillating signal OS1 and the complementary oscillating signal COS1 to be substantially 180 degrees out of phase and the oscillating signal OS2 and the complementary oscillating signal COS2 to be substantially 180 degrees out of phase using the pulse signal.
In some embodiments, the first oscillator tuner 1740 is dispensed with. In some embodiments, the second oscillator tuner 1745 is dispensed with. In some embodiments, the first and second oscillator tuners 1740, 1745 are dispensed with.
In some embodiments, at least one of the transistors 1810, 1820, 1860, 1870, 1910, 1920 is a P-type transistor, a CMOS transistor, any transistor, or a combination thereof.
The circuit 1700 further includes a pulse distribution network. FIG. 21 is a schematic diagram of an exemplary pulse distribution network 2100 in accordance with one or more embodiments. When compared to the pulse distribution network 500 of FIG. 5, the pulse generator 510 is dispensed with. The driver 520 has an input terminal 2110 connected to the control unit 2010 of the master-slave fine-tuning unit 2000 and is configured to provide sufficient current driving capability to transmit the pulse signal to various ends of the fifth level conductive paths 549a to 549p. In this exemplary embodiment, the oscillators 532, 534, correspond to the oscillators 1710, 1720, respectively.
FIG. 22 is a flowchart of an exemplary method 2200 of synchronizing a first oscillator and a second oscillator of a circuit, e.g., the oscillators 1710, 1720 of the circuit 1700 of FIG. 17, in accordance with one or more embodiments. It is understood that additional operations may be performed before, during, and/or after the method 2200 and that some other processes may only be briefly described herein.
In operation 2205, the oscillator 1710 is enabled to generate a first oscillating signal OS1 at the output node 1760 thereof and a first complementary oscillating signal COS1 at the output node 1770 thereof, and the oscillator 1720 is enabled to generate a second oscillating signal OS2 at the output node 1760 thereof and a second complementary oscillating signal COS2 at the output node 1770 thereof.
In operation 2210, the coupling structure 1750 capacitively couples the oscillators 1710, 1720. This results in the reduction of phase difference and frequency difference between the first and second oscillating signals OS1, OS2 and phase difference and frequency difference between the first and second complementary oscillating signals COS1, COS2.
In operation 2215, the first frequency divider 432 generates a first signal CLK_MR by dividing a frequency of a reference signal CLK_M by a predetermined ratio, and the second frequency divider 434 generates a second signal CLK_SR by dividing a frequency of a reference signal CLK_S by the predetermined ratio. In some embodiments, the reference signal CLK_M is the first oscillating signal OS1 and the reference signal CLK_S is the second oscillating signal OS2. In some embodiments, the reference signal CLK_M is the first complementary oscillating signal COS1 and the reference signal CLK_S is the second complementary oscillating signal COS2. In some embodiments, the first and second frequency dividers 432, 434 are dispensed with and the first and second oscillating signals OS1, OS2 or the first and second complementary oscillating signals COS1, COS2 are used as the first and second signals CLK_MR, CLK_SR, respectively.
In operation 2220, the first phase comparator 412 generates a first phase error signal 442 according to the first signal CLK_MR and a delayed version CLK_SR′ of the second signal CLK_SR, and the second phase comparator 414 generates a second phase error signal 444 according to the second signal CLK_SR and a delayed version CLK_MR′ of the first signal CLK_MR. In this exemplary embodiment, each of the phase comparators 412, 414 is a time-to-digital converter (TDC).
In operation 2225, when it is determined by the control unit 2010 of the master-slave fine-tuning unit 2000 that the difference between the first phase error signal 442 and the second phase error signal 444 is substantially equal to zero, the flow goes back to operation 2220. Otherwise, the flow proceeds to operation 2230.
In operation 2230, when it is determined by the control unit 2010 of the master-slave fine-tuning unit 2000 that the difference between the first phase error signal 442 and the second phase error signal 444 is greater than a threshold value, the flow proceeds to operation 2235. Otherwise, i.e., when it is determined by the control unit 2010 of the master-slave fine-tuning unit 2000 that the difference between the first phase error signal 442 and the second phase error signal 444 is less than the threshold value, the flow proceeds to operation 2245.
In operation 2235, the control unit 2010 of the master-slave fine-tuning unit 2000 generates a tuning signal VTUNE according to the first phase error signal 442 and the second phase error signal 444.
In operation 2240, the first oscillator tuner 1740 of the oscillator 1720 generates a tuning current according to the tuning signal VTUNE and adjusts frequencies of the oscillating signals OS2, COS2 according to the tuning current. This further reduces the frequency difference between the first and second oscillating signals OS1, OS2 and the frequency difference between the first and second complementary oscillating signals COS1, COS2. Thereafter, the flow goes back to operation 2220.
In operation 2245, the control unit 2010 of the master-slave fine-tuning unit 2000 generates a pulse signal according to the first phase error signal 442 and the second phase error signal 444.
In operation 2250, the second oscillator tuner 1745 of each of the oscillators 1710, 1720 generates a first reset voltage and a second reset voltage that are according to the pulse signal, resets a respective one of the first and second oscillating signals OS1, OS2 to start to rise from a level of the first reset voltage, and resets a respective one of the first and second complementary oscillating signals COS1, COS2 to start to fall from a level of the second reset voltage. This sets the oscillating signals OS1, COS1 to be substantially 180 degrees out of phase and the oscillating signals OS2, COS2 to be substantially 180 degrees out of phase. Thereafter, the flow goes back to operation 2220.
In some embodiments, operation 2215 is skipped and the first and second signals CLK_MR, CLK_SR are the reference signals CLK_M, CLK_S, respectively. In some embodiments, operations 2235 and 2240 are skipped. In some embodiments, operations 2245 and 2250 are skipped. In some embodiments, operations 2215-2250 are skipped.
Although the circuit in FIG. 17 is exemplified including only a pair of oscillators 1710, 1720, it should be understood that the number of oscillators may be increased as required. For example, FIG. 23 is a schematic diagram of another exemplary circuit 2300 in accordance with one or more embodiments. The circuit 2300 includes two pairs of oscillators 2310, 2320, 2330, 2340 and a coupling structure 2350. Each of the oscillators 2310, 2320, 2330, 2340 is a differential ring-type oscillator, includes an output node 2360 and an output node 2370, and is configured to generate an oscillating signal at the output node 2360, 2370.
The coupling structure 2350 capacitively couples the oscillators 2310, 2320, 2330, 2340. In this exemplary embodiment, the coupling structure 2350 includes two pairs of series-connected metal strips 2380a, another two pairs of series-connected metal strips 2380b, two pairs of capacitors 2390a, another two pairs of capacitors 2390b, and a metal plate 2380c. Each of the capacitors 2390a has a first capacitor terminal connected to the output node 2370 of a respective one of the oscillators 2310, 2320, 2330, 2340, and a second capacitor terminal connected to a respective one of the metal strips 2380a through an interconnect. Each of the capacitors 2390b has a first capacitor terminal connected to the output node 2360 of a respective one of the oscillators 2310, 2320, 2330, 2340, and a second capacitor terminal connected to a respective one of the metal strips 2380b via an interconnect.
The oscillators 2310, 2320, 2330, 2340 are formed into a substrate. The metal strips 2380a, 2380b are disposed above the substrate and are symmetrical. The metal plate 2380c is disposed under the metal strips 2380a, 2380b, is connected to the ground, and is configured to isolate the metal strips 2380a, 2380b from the substrate. In some embodiments, the substrate is a bulk substrate. In some embodiments, the substrate is an SOI substrate. Examples of materials for the metal strips 2380a, 2380b and the metal plate 2380c include, but are not limited to, Al, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, another metal material, an alloy of metal material and semiconductor material, and a combination thereof.
From experimental results, during operation of the oscillators of the circuits of the present disclosure, the oscillators generate substantially synchronized, i.e., in-phase and same frequency, oscillating signals. For example, FIG. 24 is a plot illustrating oscillating signals OS1, OS2, OS3, OS4 of oscillators of a circuit, e.g., the oscillating signals of the oscillators 2310, 2320, 2330, 2340 of the circuit 2300, in accordance to one or more embodiments and FIG. 25 is a plot illustrating oscillating signals OS1, OS2, OS3, OS4 of oscillators of a circuit, e.g., the oscillating signals of the oscillators 2310, 2320, 2330, 2340 of the circuit 2300, in accordance to one or more embodiments. As depicted in FIG. 24, when the circuit 2300 is initially operated, the oscillating signals OS1, OS2, OS3, OS4 generated by the oscillators 2310, 2320, 2330, 2340 of the circuit 2300 are out of phase. However, as depicted in FIG. 25, the oscillating signals OS1, OS2, OS3, OS4 generated by the oscillators 2310, 2320, 2330, 2340 of the circuit 2300 eventually stabilized to be substantially synchronized a certain period of time, e.g., 20 nanoseconds, after the initial operation of the circuit 2300.
In accordance with one embodiment, a circuit comprises a first differential ring-type oscillator, a second differential ring-type oscillator, and a coupling structure. The coupling structure capacitively couples the first and second differential ring-type oscillators.
In accordance with another embodiment, a circuit comprises a first oscillator, a second oscillator, a first phase comparator, a second phase comparator, and a control unit. The first oscillator is configured to generate a first oscillating signal. The second oscillator is configured to generate a second oscillating signal. The first phase comparator is connected between the first and second oscillators and is configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal. The second phase comparator is connected between the first and second oscillators and is configured to generate a second phase error signal according to the second signal and a delayed version of the first signal. The control unit is connected between the first and second phase comparators and is configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.
In accordance with another embodiment, a method of synchronizing a first differential ring-type oscillator and a second differential ring-type oscillator comprises: enabling the first differential ring-type oscillator to generate a first oscillating signal; enabling the second differential ring-type oscillator to generate a second oscillating signal; and capacitively coupling the first and second differential ring-type oscillators.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

## Claims

1. A circuit comprising:
a first oscillator configured to generate a first oscillating signal;
a second oscillator configured to generate a second oscillating signal;
a first phase comparator connected between the first and second oscillators and configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal;
a second phase comparator connected between the first and second oscillators and configured to generate a second phase error signal according to the second signal and a delayed version of the first signal; and
a control unit connected between the first and second phase comparators and configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals, wherein the first and second oscillators are further configured to generate, respectively, a first reset voltage and a second reset voltage according to the pulse signal to reset a respective one of the first and second oscillators.

2. The circuit of claim 1, wherein:
the control unit generates the tuning signal when the difference between the first and second phase error signals is greater than a threshold value; and
the second oscillator is further configured to generate a tuning current according to the tuning signal and to adjust a frequency of the second oscillating signal according to the tuning current.

3. The circuit of claim 1, wherein:
the first oscillator is further configured to generate a first complementary oscillating signal; and
the second oscillator is further configured to generate a second complementary oscillating signal.

4. The circuit of claim 3, wherein:
the control unit generates the pulse signal when the difference between the first and second phase error signals is less than a threshold value; and
each of the first and second oscillators is further configured to reset the respective one of the first and second oscillating signals to start to rise from a level of the first reset voltage and to reset a respective one of the first and second complementary oscillating signals to start to fall from a level of the second reset voltage.

5. The circuit of claim 1, wherein the first signal is the first oscillating signal and the second signal is the second oscillating signal.

6. The circuit of claim 1, further comprising:
a first frequency divider connected between the first oscillator and the first phase comparator and configured to generate the first signal by dividing a frequency of the first oscillator signal by a predetermined ratio; and
a second frequency divider connected between the second oscillator and the second phase comparator and configured to generate the second signal by dividing a frequency of the second oscillator signal by the predetermined ratio.

7. A method of synchronizing a first differential ring-type oscillator and a second differential ring-type oscillator, each differential ring-type oscillator having differential output nodes, the method comprising:
enabling the first differential ring-type oscillator to generate a first oscillating signal;
enabling the second differential ring-type oscillator to generate a second oscillating signal;
capacitively coupling, by at least one physical capacitor corresponding to each differential output node of each differential ring-type oscillator, the first and second differential ring-type oscillators;
generating a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal;
generating a second phase error signal according to the second signal and a delayed version of the first signal; and
generating one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.

8. The method of claim 7, wherein the generating one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals includes generating the tuning signal when the difference between the first and second phase error signals is greater than a threshold value, the method further comprising:
generating a tuning current according to the tuning signal; and
adjusting a frequency of the second oscillating signal according to the tuning current.

9. The method of claim 7, further comprising:
enabling the first differential ring-type oscillator to generate a first complementary oscillating signal; and
enabling the second differential ring-type oscillator to generate a second complementary oscillating signal.

10. The method of claim 9, wherein the generating one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals includes generating the pulse signal when the difference between the first and second phase error signals is less than a threshold value, the method further comprising:
generating a first reset voltage and a second reset voltage that are according to the pulse signal;
resetting the first and second oscillating signals to start to rise from a level of the first reset voltage; and
resetting the first and second complementary oscillating signals to start to fall from a level of the second reset voltage.

11. The method of claim 7, wherein the first signal is the first oscillating signal and the second signal is the second oscillating signal.

12. The method of claim 7, further comprising:
generating the first signal by dividing a frequency of the first oscillating signal by a predetermined ratio; and
generating the second signal by dividing a frequency of the second oscillating signal by the predetermined ratio.

13. The method of claim 7, further comprising:
generating the first signal by dividing a frequency of the first oscillating signal by a predetermined ratio; and
generating the second signal by dividing a frequency of the second oscillating signal by the predetermined ratio.

14. A circuit comprising:
a first oscillator having differential output nodes and configured to generate a first oscillating signal;
a second oscillator having differential output nodes and configured to generate a second oscillating signal;
a coupling structure capacitively coupling the first and second oscillators by at least one physical capacitor corresponding to each differential output node of each of the first and second oscillators;
a first phase comparator connected between the first and second oscillators and configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal;
a second phase comparator connected between the first and second oscillators and configured to generate a second phase error signal according to the second signal and a delayed version of the first signal; and
a control unit connected between the first and second phase comparators and configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.

15. The circuit of claim 14, wherein:
the control unit generates the tuning signal when the difference between the first and second phase error signals is greater than a threshold value; and
the second oscillator is further configured to generate a tuning current according to the tuning signal and to adjust a frequency of the second oscillating signal according to the tuning current.

16. The circuit of claim 14, wherein:
the first oscillator is further configured to generate a first complementary oscillating signal; and
the second oscillator is further configured to generate a second complementary oscillating signal.

17. The circuit of claim 16, wherein:
the control unit generates the pulse signal when the difference between the first and second phase error signals is less than a threshold value; and
each of the first and second oscillators is further configured to generate a first reset voltage and a second reset voltage that are according to the pulse signal, to reset a respective one of the first and second oscillating signals to start to rise from a level of the first reset voltage, and to reset a respective one of the first and second complementary oscillating signals to start to fall from a level of the second reset voltage.

18. The circuit of claim 14, wherein the first signal is the first oscillating signal and the second signal is the second oscillating signal.

19. The circuit of claim 14, further comprising:
a first frequency divider connected between the first oscillator and the first phase comparator and configured to generate the first signal by dividing a frequency of the first oscillator signal by a predetermined ratio; and
a second frequency divider connected between the second oscillator and the second phase comparator and configured to generate the second signal by dividing a frequency of the second oscillator signal by the predetermined ratio.

20. The circuit of claim 14, wherein a physical capacitor connects between one of the differential output nodes of the first oscillator and at least one metal strip of the coupling structure.