# Patent

## Title
Charge preamplifier

## Abstract

A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including: a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal; a storage capacitor connected between the input and the output of the phase inverting amplifier; a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and a control element including: a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal, a second input subjected to a reference voltage, a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, the proportionality coefficient being lower than one in a high frequency band, an output connected to the reset system to provide thereto the control signal.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to French Patent Application No. 1357291, filed Jul. 24, 2013, the entire content of which is incorporated herein by reference in its entirety.
FIELD
The technical field of the invention is that of charge source sensors. The present invention relates to a charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal.
BACKGROUND
A sensor is generally followed by a conditioner ensuring the conversion of an electrical magnitude at the output of the sensor into an exploitable electrical magnitude, generally a voltage. In the case of physical measurements using a sensor delivering an electric charge under the effect of a signal to be measured, also called “charge source sensor”, such as a piezoelectric sensor, the suitable conditioner is a charge preamplifier.
In reference to FIG. 1, a charge preamplifier includes a phase inverting amplifier AI, herein of the operational type, and a capacitor Cm, called a “storage capacitor”, collecting the charge delivered by the sensor CAP. The sensor CAP is represented by a charge source qc. More precisely, the operational amplifier AI includes an inverting input terminal connected to an output of the sensor CAP, and a non-inverting input terminal connected to a reference voltage. The storage capacitor Cm is placed between the inverting input terminal and the output terminal of the operational amplifier AI. It is noted that the phase inverting amplifier AI could also be of the transconductance type. The measurement of the voltage at the terminals of the storage capacitor Cm is proportional to the charge quantity qc generated by the sensor CAP, and independent of the capacitance of the sensor CAP and the connecting cables.
Discharging, also called “reset”, of the storage capacitor storing the electric charge delivered by the sensor, can be made permanently or in a pulse way, periodic or not, using a reset system placed in a feedback loop of the charge amplifier. It is noted that it is important to avoid the saturation of the operational amplifier and to keep a sufficient dynamic range.
In the case of a permanent reset, it is known to use a reset system including a resistance placed in parallel with the storage capacitor, enabling the storage capacitor to be discharged. The value of the resistance should be selected very high to reduce the noise it supplies. Indeed, the sensor has generally a leakage current Idet depending on parameters such as temperature, electric bias conditions of the sensor, irradiation doses received, etc. This leakage current generates a shot noise of variance 2qIdet, where q is the elementary charge of an electron. If the resistance has a value equal to 2 kT/(q·Idet), that is 52 MOhms for 1 nA, the power of the shot noise is doubled.
But, a resistance of this order of magnitude is not feasible as a pure passive resistance for reasons of a size unsuitable for integrated circuits. In reference to FIG. 2, SRZ active components biased at very low currents are conventionally used, to replace the resistance. The SRZ active component generates a discharging current id controlled by the variations in the output voltage VsPAC of the operational amplifier AI. In the embodiment of FIG. 2, the SRZ active component is a MOS transistor, equivalent to a voltage controlled current generator. The discharging current id is controlled by the deviation between the output voltage VsPAC and a reference value Vref, corresponding to the output voltage at rest of the charge preamplifier. The discharging current id delivered by the SRZ active component supplies the storage capacitor Cm with a charge opposite to the charge generated by the signal and stored in the storage capacitor Cm.
However, the active element adds noises to the measure. Indeed, the noise of an active element directly depends on the current passing through it. In static operation, that is in the absence of a signal, these noises depend on active element bias currents, which are minimized to restrict the noise source. But in dynamic operation, that is after the arrival of a signal, as soon as the electric charge corresponding to the signal has started to be stored in the storage capacitor, the active component is activated and the discharging current it provides at the input of the charge preamplifier increases. This discharging current reaches a maximum value substantially at the same time as the charge stored in the storage capacitor, possibly slightly later if the corresponding electrical path is slower than the charging circuit of the storage capacitor. The current passing through the active element thus changes from a low rest value to a much higher value required for discharging the storage capacitor. This transient current is a noise source the variance of which increases with the amplitude of said current. A low noise reset system can thus be made in the absence of a signal, but it is not possible to hold this property upon measuring a signal.
But, this noise induces a further fluctuation in the signal measurement and this fluctuation is all the more important that the discharging current maximum is close to the time of arrival of the signal at the input of the charge amplifier.
SUMMARY
An aspect of the invention provides a charge preamplifier enabling this noise to be restricted.
According to a first aspect, the invention substantially relates to a charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including:

    
    
        a phase inverting amplifier including an input related to the charge source sensor,
        a storage capacitor connected between the input and an output of the phase inverting amplifier,
        a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal.
    
    


Further, the charge preamplifier includes a control element connected between the reset system and the output of the phase inverting amplifier, and suitable for providing the control signal to the reset system, said control signal being proportional to the deviation between the output voltage of the phase inverting amplifier and a reference voltage, said proportionality coefficient being lower that one for high frequencies.
In other words, the control element includes:

    
    
        a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal
        a second input subjected to a reference voltage
        a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, said proportionality coefficient being lower than one in a high frequency band
        an output connected to the reset system to provide thereto the control signal.
    
    


By “the control signal is proportional to the deviation between the voltage signal and the reference voltage, said proportionality coefficient being lower than one in a high frequency band”, it is meant that the control signal is such that:

Sg=α(VsPAC−Vref)

Where:

    
    
        Sq is the control signal
        VsPAC is the voltage signal
        Vref is the reference voltage
        α is a proportionality coefficient depending on the frequency
        α<1 in a high frequency band.
    
    


In other words, the control element behaves as an attenuator of the difference between the voltage signal and the reference voltage in a high frequency band.
Besides the mains characteristics just mentioned in the preceding paragraph, the device according to an embodiment of the invention can have one or more further characteristics among the following ones, considered singly or according to the technically possible combinations:

    
    
        the proportionality coefficient is higher than one for low frequencies. In other words, the control element behaves as an amplifier of the difference between the voltage signal and the reference voltage at low frequencies.
        the control element includes a modified transconductance amplifier including:
        
            a resistive element
            a first field effect transistor of a first type, the gate and the drain of the first transistor being connected with each other
            a second field effect transistor of the same type as the first transistor, the sources of the first transistor and the second transistor being at a same fixed potential, the gates of the first transistor and the second transistor being connected via the resistive element
            a capacitor connected between the gate and the drain of the second transistor
        
        
        the resistive element includes a second transconductance amplifier, biased by a low current
        the control element includes:
        
            a D.C. current source
            a third field effect transistor of a complementary type t the first transistor, such that:
            
                the drain of the third transistor is connected to the drain of the first transistor
                the source of the third transistor is connected to the current source
                the gate of the third transistor is subjected to the output voltage of the phase inverting amplifier
            
            
            a fourth field effect transistor of a complementary type to the first transistor, such that:
            
                the drain of the fourth transistor is connected to the drain of the second transistor
                the source of the third transistor is connected to the current source
                the gate of the third transistor is subjected to the reference voltage.
            
            
        
        
        the control element includes:
        
            an operational amplifier, including:
            
                a non-inverting terminal subjected to the voltage signal
                an inverting terminal subjected to the reference voltage
                an output connected to a passive network
            
            
            the passive network including:
            
                a first resistance, including a first terminal connected to the output of the operational amplifier, and a second terminal at which the voltage signal is withdrawn
                a second resistance, including a first terminal connected to the second terminal of the first resistance, and a second terminal
                a third resistance including a first terminal connected to the second terminal of the second resistance, and a second terminal subjected to a zero voltage
                a second capacitor, connected in parallel with the second resistance.
            
            
        
        
        the reset system includes a field effect transistor the source of which is subjected to the control signal.
        the reset system includes a bipolar transistor the emitter of which is subjected to the control signal.
        the reset system is biased by a leakage current of the sensor.
    
    


By “type” of transistor, it is meant a N-channel or P-channel transistor. A N-channel transistor and a P-channel transistor are said to be of a complementary type.
The invention and its different applications will be better understood upon reading the following description and examining the accompanying figures.



BRIEF DESCRIPTION OF THE FIGURES
The figures are only presented by way of indicating and in no way limiting purposes for the invention.
The figures show:
in FIG. 1, already described, a charge preamplifier according to prior art,
in FIG. 2, already described, a charge preamplifier with a reset function according to prior art
in FIG. 3, a charge preamplifier with a reset function, according to one embodiment of the invention
in FIG. 4, a control system and a control element ensuring a reset function, according to a first embodiment of the invention
in FIG. 5, a Bode diagram of the control element of FIG. 4
in FIG. 6, a control element according to a second embodiment of the invention
in FIG. 7, a Bode diagram of the control element of FIG. 6.



DETAILED DESCRIPTION
FIG. 3 shows a charge preamplifier PAC according to an embodiment of the invention. The charge preamplifier PAC includes an input E connected to an output of a charge source sensor CAP, and an output S connected to a voltage acquisition device ACQ.
The charge preamplifier PAC includes:

    
    
        a phase inverting amplifier AI including:
        
            an input related to the input E of the charge preamplifier PAC, which is related to the charge source sensor CAP
            an output related to the output S of the charge preamplifier PAC, which is related to the voltage acquisition device ACQ, to provide a voltage signal VsPAC 
        
        
        a storage capacitor Cm including:
        
            a first terminal connected to the input E of the charge preamplifier PAC
            a second terminal connected to the output S of the charge preamplifier PAC
        
        
        a reset system SRZ including:
        
            an output connected to the input E of the charge preamplifier PAC,
            an input connected to a control element CTL
        
        
        the control element CTL including:
        
            an output connected to the input of the reset system SRZ to provide thereto a control signal Sg
            a first input connected to the output S of the charge preamplifier PAC, for withdrawing the voltage signal VsPAC 
            a second input subjected to a reference voltage Vref.
        
        
    
    


As previously described, the phase inverting amplifier AI is of the operational type (see FIG. 1) or of the transconductance type. The storage capacitor Cm, feedback connected between the input E and the output S of the phase inverting amplifier, forms a Miller integrator. The reset system SRZ provides a discharging current id to the storage capacitor Cm. In an embodiment, the reset system SRZ is made using transistors. Finally, the control element CTL regulates the output voltage VsPAC of the phase inverting amplifier AI to the reference voltage Vref.
The control element CTL includes a set of components configured and arranged to generate a control signal Sg which is proportional to the deviation between the voltage signal VsPAC and the reference voltage, the proportionality coefficient being dependent on the frequency and being lower than one in a high frequency band. Beneficially, the proportionality coefficient is further higher than one at low frequencies.
FIG. 4 shows a first embodiment of a reset system SRZ and of a control element CTL according to the invention.
The reset system SRZ is in the present case a P-channel MOSFET transistor, connected as a common gate. In another embodiment, the reset system SRZ is a P-channel or N-channel MOSFET transistor connected as a common source. In another embodiment, the reset system SRZ is a NPN or PNP bipolar transistor, connected as a common emitter. In another embodiment, the reset system SRZ is a NPN or PNP bipolar transistor, connected as a common base.
In a described embodiment, the reset system SRZ is biased by the leakage current of the sensor CAP, present at the input of the charge preamplifier PAC. In another embodiment, the reset system SRZ is biased by a dedicated current source.
The reset system SRZ provides a discharging current id controlled by a control signal Sg provided by the control element CTL.
In the embodiment of FIG. 4, the control element CTL is a modified transconductance amplifier using a resistance-capacitance network. More precisely, the transconductance amplifier includes:

    
    
        a D.C. current source I0 
        a first P-channel field effect transistor MP1
        a second P-channel field effect transistor MP2
        a third N-channel field effect transistor MN3
        a fourth N-channel field effect transistor MN4
        a resistive element R
        a capacitor C.
    
    


It will be appreciated that the operation would not be modified if transistors were differently chosen. Indeed, the first transistor MP1 and the second transistor MP2 could be of the N-channel type; the third transistor MN3 and the fourth transistor MN4 would then be of the P-channel type. Indeed, it is sufficient that both groups of transistors be of a complementary type.
The first transistor MP1 and the second transistor MP2 are connected as a modified current mirror:

    
    
        the gate and the drain of the first transistor MP1 are connected to each other
        the source of the first transistor MP1 and the source of the second transistor MP2 are at a same fixed potential VDD 
        the gate of the first transistor MP1 and the gate of the second transistor MP2 are connected through the resistive element R. It is noted that the resistive element R isolates the first transistor MP1 from the second transistor MP2, whereas they are connected in a conventional current mirror connection
        the drain of the first transistor MP1 is connected to the current source through the third transistor MN3
        the drain of the second transistor MP2 is connected to the current source through the fourth transistor MN4
        the gate and the drain of the second transistor MP2 are connected through the capacitor C.
    
    


More precisely:

    
    
        the drain of the third transistor MN3 is connected to the drain of the first transistor MP1
        the source of the third transistor MN3 is connected to the current source I0 
        the drain of the fourth transistor MN4 is connected to the drain of the second transistor MP2
        the source of the fourth transistor MN4 is connected to the current source I0.
    
    


Further:

    
    
        the gate of the third transistor MN3 is subjected to the output voltage VsPAC of the phase inverting amplifier AI
        the gate of the third transistor MN3 is subjected to the reference voltage Vret.
    
    


Thus, the voltage at the output of the transconductance amplifier is proportional to the deviation between the output voltage VsPAC of the phase inverting amplifier AI, and the reference voltage Vref. The voltage at the output of the transconductance amplifier is the control signal Sg applied to the reset system SRZ. But the proportionality coefficient varies as a function of the frequency, as shown in the Bode gain diagram of the control element CTL, represented in FIG. 5.
At low frequencies, that is in static mode, that is in the absence of detection, the gain gdB of the control element is high. In the present case, it is 36 decibels. Then, from a certain frequency f0, the gain gdB drops before being restored to a value lower than one, in the present case −12 decibels. The control element CTL thus behaves as a low frequency amplifier, and as an attenuator in a higher frequency band.
Indeed, at low frequencies, the capacitor C is equivalent to an open circuit, whereas at high frequencies, the capacitor C is equivalent to a closed circuit. At high frequencies, the gate and the drain of the second transistor MP2 are thus at the same potential. The second transistor MP2 thus behaves as a charge resistance having a known and controllable value by setting the current I0 output from the current source.
It is noted that from a certain frequency, the gain drops again: this is due to the presence of stray capacitances not represented in the figure and to the mobility limits of the charge carriers in the materials of the transistors.
The amplifier and attenuator behaviour as a function of the frequencies is advantageous. Indeed, a high gain gdB allows a better accuracy for regulating the voltage VsPAC at the output of the phase inverting amplifier AI. Further, a low gain gdB enables the current id peak to be restricted at the output of the reset system SRZ.
More precisely, after the arrival of a signal from the sensor CAP, to ensure a discharge of the storage capacitor Cm, which restricts the transient noise, the control element CTL provides the reset system SRZ with a fraction of the deviation between the output voltage VsPAC of the phase inverting amplifier AI and the reference voltage Vref. The control element CTL thus acts as a voltage attenuator, which restricts the maximum value reached by the discharging current id with respect to the situation of prior art wherein the deviation between the output voltage VsPAC of the inverting amplifier and the reference voltage Vref is directly applied with a gain equal to or higher than one. Further, to ensure a sufficient accuracy for statically regulating the voltage at the output VsPAC of the phase inverting amplifier AI, that is to make sure that the output voltage VsPAC of the phase inverting amplifier AI is close to the reference voltage Vref in the absence of detection, the gain of the control element CTL at low frequencies increases when the frequency decreases.
The control element CTL thus allows:

    
    
        the output voltage VsPAC of the phase inverting amplifier AI to be controlled to be close to the reference voltage Vref in static mode
        the current id provided by the reset system SRZ to be controlled in order to restrict it in dynamic mode.
    
    


The control element CTL thus enables the output voltage VsPAC of the phase inverting amplifier AI to be regulated to a reference voltage Vref which, after the arrival of the signal, ensures the return to the reference voltage Vref by reducing the noise inseparable from this operation.
It will be appreciated that there are a vast number of electronic connections enabling a control element CTL to be made including:

    
    
        a first input connected to the output S of the phase inverting amplifier AI, for withdrawing the voltage signal VsPAC 
        a second input subjected to a reference voltage Vref 
        a set of components configured and arranged to generate a control signal Sg proportional to the deviation between the voltage signal VsPAC and the reference voltage Vref, said proportionality coefficient being lower than one in a high frequency band
        an output connected to the reset system SRZ to provide thereto the control signal Sg.
    
    


The control element CTL presented in FIG. 4 is only an exemplary embodiment thereof.
A second exemplary embodiment is given in FIG. 6. In this second embodiment, the control element CTL includes:

    
    
        an operational amplifier APL with a gain G, including:
        
            a non-inverting terminal subjected to the voltage signal VsPAC 
            an inverting terminal subjected to a reference voltage Vref 
            an output connected to a passive network RP
        
        
        the passive network RP, including:
        
            a first resistance R0, including a first terminal connected to the output of the operational amplifier APL, and a second terminal at which the control signal Sg is withdrawn
            a second resistance R1, including a first terminal connected to the second terminal of the first resistance R0, and a second terminal
            a third resistance R2 including a first terminal connected to the second terminal of the second resistance (R1), and a second terminal subjected to a zero voltage
            a second capacitor C2, connected in parallel with the second resistance R2.
        
        
    
    


The transfer function, in the Laplace domain, associated with the control element CTL presented in FIG. 6 is as follows:




  
    H
    ⁡
    
      (
      s
      )
    
  
  =
  
    
      Sg
      
        VsPAC
        -
        Vref
      
    
    =
    
      
        
          G
          ⁡
          
            (
            
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
              +
              
                R
                ⁢
                
                  
                
                ⁢
                2
              
            
            )
          
        
        
          
            R
            ⁢
            
              
            
            ⁢
            0
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            2
          
        
      
      ⁢
      
        
          1
          +
          
            s
            ⁢
            
              
                R
                ⁢
                
                  
                
                ⁢
                1
                ⁢
                
                  
                
                ⁢
                R
                ⁢
                
                  
                
                ⁢
                2
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                2
              
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
                +
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
        
          1
          +
          
            s
            ⁢
            
              
                
                  (
                  
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                    +
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  )
                
                ⁢
                R
                ⁢
                
                  
                
                ⁢
                2
                ⁢
                
                  
                
                ⁢
                C
                ⁢
                
                  
                
                ⁢
                2
              
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
                +
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
                +
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
      
    
  




The transfer function includes a pole Tp and a zero Tz, such that:




  
    Tp
    Tz
  
  =
  
    
      
        (
        
          
            R
            ⁢
            
              
            
            ⁢
            0
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            1
          
        
        )
      
      ⁢
      
        (
        
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            2
          
        
        )
      
    
    
      R
      ⁢
      
        
      
      ⁢
      1
      ⁢
      
        (
        
          
            R
            ⁢
            
              
            
            ⁢
            0
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            2
          
        
        )
      
    
  




This ratio can assume high values as a function of the values of the resistances. For example, if R1=1Ω, R0=R2=200Ω, then:




  
    Tp
    Tz
  
  =
  100.75




At low frequencies, the gain of this transfer function tends to the static gain:




  
    G
    ⁡
    
      (
      
        
          R
          ⁢
          
            
          
          ⁢
          1
        
        +
        
          R
          ⁢
          
            
          
          ⁢
          2
        
      
      )
    
  
  
    
      R
      ⁢
      
        
      
      ⁢
      0
    
    +
    
      R
      ⁢
      
        
      
      ⁢
      1
    
    +
    
      R
      ⁢
      
        
      
      ⁢
      2
    
  




At high frequencies, the gain of this transfer function tends to:




  
    
      
    
    ⁢
    
      G
      ⁢
      
        
      
      ⁢
      R
      ⁢
      
        
      
      ⁢
      1
    
  
  
    
      R
      ⁢
      
        
      
      ⁢
      0
    
    +
    
      R
      ⁢
      
        
      
      ⁢
      1
    
  




The Bode gain diagram of the control element CTL of FIG. 6 is represented in FIG. 7, for the following values: R0=R2=2 GΩ, R1=10 MΩ, C2=10 nF and G=100. At low frequencies, that is in static mode, that is in the absence of detection, the gain gdB of the control element is high. In the present case, it is 34 decibels. Then, from a certain frequency f1, the gain gdB drops before being restored to a value lower than one, in the present case −6 decibels. The control element CTL thus behaves as an amplifier at low frequencies, and as an attenuator in a higher frequency band.

## Claims

1. A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, comprising:
a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal;
a storage capacitor connected between the input and the output of the phase inverting amplifier;
a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and
a control element including:
a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal,
a second input subjected to a reference voltage,
a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, said proportionality coefficient being lower than one in a high frequency band, and
an output connected to the reset system to provide thereto the control signal,

wherein the control element includes a modified transconductance amplifier including
a resistive element,
a first field effect transistor of a first type, the gate and the drain of the first transistor being connected with each other,
a second field effect transistor of the same type as the first transistor the sources of the first transistor and the second transistor being at a same fixed potential, the gates of the first transistor and the second transistor being connected via the resistive element, and
a capacitor connected between the gate and the drain of the second transistor.

2. The charge preamplifier according to claim 1, wherein said proportional coefficient is higher than one for low frequencies.

3. The charge preamplifier according to claim 1, wherein the resistive element includes a second transconductance amplifier, biased by a low current.

4. The charge preamplifier according to claim 1, wherein the control element includes:
a D.C. current source,
a third field effect transistor of a complementary type to the first transistor, such that:
the drain of the third transistor is connected to the drain of the first transistor,
the source of the third transistor is connected to the current source,
the gate of the third transistor is subjected to the output voltage of the phase inverting amplifier,

a fourth field effect transistor of a complementary type to the first transistor, such that:
the drain of the fourth transistor is connected to the drain of the second transistor,
the source of the third transistor is connected to the current source,
the gate of the third transistor is subjected to the reference voltage.

5. A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, comprising:
a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal;
a storage capacitor connected between the input and the output of the phase inverting amplifier;
a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and
a control element including:
a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal,
a second input subjected to a reference voltage,
a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, said proportionality coefficient being lower than one in a high frequency band,
an output connected to the reset system to provide thereto the control signal,

wherein the control element includes:
an operational amplifier, including:
a non-inverting terminal subjected to the voltage signal,
an inverting terminal subjected to the reference voltage,
an output connected to a passive network,

the passive network including:
a first resistance, including a first terminal connected to the output of the operational amplifier, and a second terminal at which the voltage signal is withdrawn
a second resistance, including a fist terminal connected to the second terminal of the first resistance, and a second terminal
a third resistance including a first terminal connected to the second terminal of the second resistance and a second terminal subjected to a zero voltage
a second capacitor, connected in parallel with the second resistance.

6. The charge preamplifier according to claim 1, wherein the reset system includes a field effect transistor the source of which is subjected to the control signal.

7. The charge preamplifier according to claim 1, wherein the reset system includes a bipolar transistor the emitter of which is subjected to the control signal.

8. The charge preamplifier according to claim 1, wherein the reset system is biased by a leakage current of the sensor.