# Patent

## Title
Semiconductor device and manufacturing method thereof

## Abstract

An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor including a silicon region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, a first insulating layer, a second insulating layer, a third insulating layer, and a second transistor, which includes an oxide semiconductor layer over the third insulating layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode, and a fourth insulating layer and a fifth insulating layer. A first electrode passes through the first insulating layer and the second insulating layer to be electrically connected to the silicon region, and a second electrode passes through the third insulating layer, the fourth insulating layer and the fifth insulating layer to be electrically connected to the first electrode.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 13/779,833, filed Feb. 28, 2013, now U.S. Pat. No. 8,779,479 B2, which is a continuation of U.S. application Ser. No. 12/945,516, filed Nov. 12, 2010, now U.S. Pat. No. 8,389,417, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2009-260392 on Nov. 13, 2009, all of which are incorporated by reference.


TECHNICAL FIELD
A technical field of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Note that semiconductor devices herein refer to general elements and devices which function by utilizing semiconductor characteristics.
BACKGROUND ART
There are a wide variety of metal oxides and such material oxides are used for various applications. Indium oxide is a well-known material and is used as a material for transparent electrodes which are needed for liquid crystal display devices or the like.
Some metal oxides have semiconductor characteristics. Examples of such metal oxides having semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like. A thin film transistor in which a channel formation region is formed using such a metal oxide is already known (see, for example, Patent Documents 1 to 4, Non-Patent Document 1, and the like).
Not only single-component oxides but also multi-component oxides are known as metal oxides. For example, InGaO3(ZnO)m (m: natural number) having a homologous phase is known as a multi-component oxide semiconductor including In, Ga, and Zn (see, for example, Non-Patent Documents 2 to 4 and the like).
Furthermore, it is confirmed that an oxide semiconductor including such an In—Ga—Zn-based oxide can also be applied to a channel formation region of a thin film transistor (see, for example, Patent Document 5, Non-Patent Documents 5 and 6, and the like).
REFERENCES
Patent Documents


    [Patent Document 1] Japanese Published Patent Application No. S60-198861
    [Patent Document 2] Japanese Published Patent Application No. H8-264794
    [Patent Document 3] Japanese Translation of PCT International Application No. H11-505377
    [Patent Document 4] Japanese Published Patent Application No. 2000-150900
    [Patent Document 5] Japanese Published Patent Application No. 2004-103957


Non-Patent Documents


    [Non-Patent Document 1]M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 Jun. 1996, Vol. 68, pp. 3650-3652
    [Non-Patent Document 2]M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3—Ga2ZnO4—ZnO System at 1350° C.”, J. Solid State Chem., 1991, Vol. 93, pp. 298-315
    [Non-Patent Document 3]N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3 (ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System”, J. Solid State Chem., 1995, Vol. 116, pp. 170-178
    [Non-Patent Document 4]M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m: natural number) and related compounds”, KOTAI BUTSURI (SOLID) STATE PHYSICS), 1993, Vol. 28, No. 5, pp. 317-327
    [Non-Patent Document 5]K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”, SCIENCE, 2003, Vol. 300, pp. 1269-1272
    [Non-Patent Document 6]K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”, NATURE, 2004, Vol. 432, pp. 488-492


DISCLOSURE OF INVENTION
Field-effect transistors, which are a typical example of semiconductor devices, are generally formed using a material such as silicon. However, it can hardly be said that even a semiconductor device for which silicon or the like is used as a material has sufficient characteristics for some applications.
For example, off-state current (also referred to as leakage current or the like) of a semiconductor device formed using silicon is not as low as substantially zero. Therefore, a slight amount of current flows regardless of the operation state of the semiconductor device, and thus it has been difficult to ensure an adequate period for charge retention in the case of fabrication of a charge-retention semiconductor device such as a memory device or a liquid crystal display device. In addition, there is a problem in that the power consumption of the semiconductor device increases due to the off-state current.
Furthermore, other characteristics of a transistor, such as subthreshold swing (S-value), on/off ratio, and reliability, need to be improved in some cases.
In view of this, it is an object of an embodiment of the disclosed invention to provide a semiconductor device with a novel structure which solves the above problems.
Alternatively, it is an object to provide a manufacturing method of the semiconductor device with a novel structure.
With a structure in which a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor are stacked, a semiconductor device having advantages of both of the transistors can be provided. In particular, with respect to a transistor including an oxide semiconductor, which has a source electrode and a drain electrode with an oxidized side surface, characteristics such as subthreshold swing (S-value), on/off ratio, and reliability are significantly improved. Specifically, the following structure can be employed, for example.
An embodiment of the present invention is a semiconductor device including a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions provided such that the channel formation region is sandwiched therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode electrically connected to the impurity regions, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer, a second gate insulating layer covering the oxide semiconductor layer, the second source electrode, and the second drain electrode, and a second gate electrode over the second gate insulating layer. The second source electrode and the second drain electrode have an oxide region formed by oxidizing a side surface thereof. At least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode. Note that the oxide region is formed while oxygen is supplied to the oxide semiconductor layer.
In the above embodiment, it is preferable that the oxide region of the second source electrode and the second drain electrode be formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon. It is also preferable that a protective insulating layer having substantially the same planar shape as that of the second source electrode and the second drain electrode be provided over the second source electrode and the second drain electrode. Note that the expression “substantially the same” or “substantially same” does not necessarily mean being exactly the same in a strict sense and can mean being considered as the same. For example, a difference made by a single etching process is acceptable.
In the above embodiment, it is also preferable that the hydrogen concentration of the oxide semiconductor layer be 5×1019/cm3 or less. It is also preferable that the off-state current of the second transistor be 1×10−13 A or less.
Moreover, in the above embodiment, it is preferable that the substrate including the semiconductor material be a single crystal semiconductor substrate or an SOI substrate. It is also preferable that the semiconductor material be silicon.
An embodiment of the present invention is a manufacturing method of a semiconductor device, which includes the step of forming a first transistor and the step of forming a second transistor. The step of forming the first transistor includes: forming a gate insulating layer over a substrate including a semiconductor material and a gate electrode over the gate insulating layer, forming a channel formation region and impurity regions so that the channel formation region is sandwiched the impurity regions by adding an impurity element to the substrate including the semiconductor material, and forming a first source electrode and a first drain electrode electrically connected to the impurity regions. The step of forming the second transistor includes: forming an oxide semiconductor layer over the first transistor, forming a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer, forming a second gate insulating layer covering the oxide semiconductor layer, the second source electrode, and the second drain electrode after oxidizing a side surface of the second source electrode and the second drain electrode, and forming a second gate electrode over the second gate insulating layer. Note that oxygen is supplied to the oxide semiconductor layer when the side surface of the second source electrode and the second drain electrode is oxidized.
In the above embodiment, it is preferable that the side surface of the second source electrode and the second drain electrode be oxidized by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon. It is also preferable that at least one of the second gate electrode, the second source electrode, and the second drain electrode be formed so as to be electrically connected to at least one of the first gate electrode, the first source electrode, and the first drain electrode.
In the above embodiment, it is also preferable that a protective insulating layer having substantially the same planar shape as that of the second source electrode and the second drain electrode be formed over the second source electrode and the second drain electrode.
In the above embodiment, it is also preferable that the off-state current of the second transistor be made 1×10−13 A or less by making the hydrogen concentration of the oxide semiconductor layer 5×1019/cm3 or less.
Moreover, in the above embodiment, it is preferable that a single crystal semiconductor substrate or an SOI substrate be used as the substrate including the semiconductor material. It is also preferable that the semiconductor material be silicon.
Note that the term such as “over” or “below” in this specification and the like does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “a first gate electrode over a gate insulating layer” does not exclude the case where a component is placed between the gate insulating layer and the gate electrode. Moreover, the terms such as “over” and “below” are only used for convenience of description and can include the case where the vertical relation of components is reversed, unless otherwise specified.
In addition, the term such as “electrode” or “wiring” in this specification and the like does not limit a function of a component. For example, an “electrode” can be used as part of a “wiring”, and the “wiring” can be used as part of the “electrode”. Furthermore, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner.
Functions of a “source” and a “drain” are sometimes interchanged with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.
Note that the term “electrically connected” in this specification and the like includes the case where components are connected through an “object having any electric function”. There is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object.
Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring.
In general, the term “SOI substrate” means a substrate having a silicon semiconductor layer over an insulating surface. In this specification and the like, the term “SOI substrate” also means a substrate having a semiconductor layer including a material other than silicon over an insulating surface. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer.
In addition, a substrate in an “SOI substrate” is not limited to a semiconductor substrate such as a silicon wafer, and may be a non-semiconductor substrate such as a glass substrate, a quartz substrate, a sapphire substrate, or a metal substrate. In other words, the “SOI substrate” also includes a conductive substrate or an insulating substrate provided with a layer including a semiconductor material in its category.
In addition, in this specification and the like, a “semiconductor substrate” means a substrate including only a semiconductor material and also a general substrate including a semiconductor material. In other words, in this specification and the like, “SOI substrates” are also included in the broad category of “semiconductor substrates”.
An embodiment of the present invention provides a semiconductor device having a structure in which a transistor including a material other than an oxide semiconductor and a transistor including an oxide semiconductor are stacked.
By stacking a transistor including a material other than an oxide semiconductor and a transistor including an oxide semiconductor as described above, a novel semiconductor device having advantages of characteristics of both of the transistors can be realized.
In particular, the off-state current of a transistor including an oxide semiconductor is extremely small and the switching characteristic thereof is excellent; thus, an excellent semiconductor device can be provided utilizing the characteristics. A transistor including a material other than an oxide semiconductor is advantageous over a transistor including an oxide semiconductor in terms of field-effect mobility and the like, and this can be utilized to provide a semiconductor device taking advantage of the characteristics. In other words, according to an embodiment of the present invention, an excellent semiconductor device having characteristics of both an oxide semiconductor and a material other than an oxide semiconductor can be provided.
A semiconductor device with a novel feature can be realized by including both a transistor including a material other than an oxide semiconductor and a transistor including an oxide semiconductor.
In addition, according to an embodiment of the disclosed invention, characteristics of a transistor including an oxide semiconductor are further improved by supplying oxygen to an oxide semiconductor layer. Here, the oxygen supply process brings the result that a side surface of a source or drain electrode is oxidized in a transistor including an oxide semiconductor.
By oxidizing a side surface of a source or drain electrode, it is possible to prevent short circuit between a gate electrode and the source or drain electrode which may be caused by a reduction in thickness of a gate insulating layer or defective coverage therewith.
By supplying oxygen to an oxide semiconductor layer as described above, a semiconductor device with a novel structure and excellent characteristics can be realized.



BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A and 1B are cross-sectional views each illustrating a semiconductor device.
FIGS. 2A to 2H are cross-sectional views illustrating a manufacturing process of a semiconductor device.
FIGS. 3A to 3E are cross-sectional views illustrating a manufacturing process of a semiconductor device.
FIGS. 4A to 4D are cross-sectional views illustrating a manufacturing process of a semiconductor device.
FIG. 5 is a cross-sectional view of a transistor including an oxide semiconductor.
FIG. 6 is an energy band diagram (schematic diagram) along an A-A′ section in FIG. 5.
FIG. 7A is a diagram illustrating a state where a positive potential (+qVG) is applied to a gate (GE1) and FIG. 7B is a diagram illustrating a state where a negative potential (−qVG) is applied to the gate (GE1).
FIG. 8 is a diagram illustrating the relationships between the vacuum level and the work function of a metal (φM) and between the vacuum level and the electron affinity (χ) of an oxide semiconductor.
FIGS. 9A and 9B are diagrams illustrating energy required for hot carrier injection in silicon (Si).
FIGS. 10A and 10B are diagrams illustrating energy required for hot carrier injection in an In—Ga—Zn—O-based oxide semiconductor (IGZO).
FIGS. 11A and 11B are diagrams illustrating energy required for hot carrier injection in silicon carbide (4H—SiC).
FIG. 12 is a diagram showing the results of device simulation as to a short-channel effect.
FIG. 13 is a diagram showing the results of device simulation as to a short-channel effect.
FIG. 14 is a diagram showing C-V characteristics.
FIG. 15 is a diagram illustrating the relationship between VG and (1/C)2.
FIGS. 16A and 16B are cross-sectional views each illustrating a semiconductor device.
FIGS. 17A to 17F are diagrams each illustrating an electronic device including a semiconductor device.
FIG. 18 is a diagram illustrating the relationship between the thickness of an oxide region formed by plasma treatment and the treatment time.



BEST MODE FOR CARRYING OUT THE INVENTION
Examples of embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and the scope thereof. Therefore, the present invention should not be construed as being limited to the description in the following embodiments.
Note that the position, size, range, or the like of each component illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like.
Note that ordinal numbers such as “first”, “second”, and “third” in this specification and the like are used m order to avoid confusion among components, and the terms do not limit the components numerically.
Embodiment 1
In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. 1A and 1B, FIGS. 2A to 2H, FIGS. 3A to 3E, and FIGS. 4A to 4D.
<Structure of Semiconductor Device>
FIGS. 1A and 1B are cross-sectional views each illustrating an example of a structure of a semiconductor device. The semiconductor device illustrated in FIG. 1A includes, in a lower portion, a transistor 160 including a material other than an oxide semiconductor, and in an upper portion, a transistor 162 including an oxide semiconductor. The transistors 160 and 162 are n-channel transistors here; alternatively, a p-channel transistor may be used. In particular, it is easy to use a p-channel transistor as the transistor 160. FIG. 1B illustrates an example where the connection relationship between the transistor 162 and an electrode (or a wiring) in the lower portion differs from that in FIG. 1A. The structure in FIG. 1A is mainly described below. Note that FIG. 1A shows a cross-sectional view of the transistor 160 provided in the lower portion along A1-A2 and a cross-sectional view of the transistor 162 provided in the upper portion along B1-B2, and FIG. 1B shows a cross-sectional view of the transistor 160 provided in the lower portion along A1-A2 and a cross-sectional view of the transistor 162 provided in the upper portion along C1-C2.
The transistor 160 includes a channel formation region 116 provided in a substrate including a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (these regions can be collectively referred to simply as impurity regions) provided such that the channel formation region 116 is sandwiched therebetween, a gate insulating layer 108a provided over the channel formation region 116, a gate electrode 110a provided over the gate insulating layer 108a, and a source or drain electrode 130a and a source or drain electrode 130b electrically connected to the impurity regions 114 (see FIG. 1A).
Here, a sidewall insulating layer 118 is formed on a side surface of the gate electrode 110a. The high-concentration impurity regions 120 are provided in regions of the substrate which do not overlap with the sidewall insulating layer 118 when seen from above. Metal compound regions 124 are provided in contact with the high-concentration impurity regions 120. An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160. The source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the metal compound regions 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. In other words, the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the high-concentration impurity regions 120 and the impurity regions 114 through the metal compound regions 124.
The transistor 162 includes an oxide semiconductor layer 140 provided over an insulating layer 138, a source or drain electrode 142a and a source or drain electrode 142b provided over the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, a gate insulating layer 146 provided so as to cover the oxide semiconductor layer 140, the source or drain electrode 142a, and the source or drain electrode 142b, and a gate electrode 148 provided over the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 140 (see FIG. 1A).
Here, the source or drain electrode 142a and the source or drain electrode 142b each include an oxide region 143 formed by oxidizing a side surface thereof. With the oxide region 143, it is possible to prevent short circuit between the gate electrode and the source or drain electrode which may be caused by a reduction in thickness of the gate insulating layer or defective coverage therewith.
In addition, over the transistor 162, an interlayer insulating layer 150 and an interlayer insulating layer 152 are provided. Openings that reach the source or drain electrode 142a and the source or drain electrode 142b are formed in the gate insulating layer 146, the interlayer insulating layer 150, and the interlayer insulating layer 152. An electrode 154d and an electrode 154e are formed in contact with the source or drain electrode 142a and the source or drain electrode 142b, respectively, through the respective openings. Like the electrodes 154d and 154e, an electrode 154a, an electrode 154b, and an electrode 154c are formed in contact with an electrode 136a, an electrode 136b, and an electrode 136c, respectively, through openings provided in the gate insulating layer 146, the interlayer insulating layer 150, and the interlayer insulating layer 152.
Here, the oxide semiconductor layer 140 is preferably an oxide semiconductor layer which is purified by sufficiently removing an impurity such as hydrogen therefrom and supplying oxygen thereto. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is 5×1019/cm3 or less, preferably 5×1018/cm3 or less, more preferably 5×1017/cm3 or less. Note that the oxide semiconductor layer 140 which is purified by sufficiently reducing hydrogen concentration and supplying oxygen has a carrier concentration (e.g., less than 1×1012/cm3, preferably 1×1011/cm3 or less) which is sufficiently lower than that of a general silicon wafer (a silicon wafer to which an impurity element such as phosphorus or boron is slightly added) (approximately 1×1014/cm3). The transistor 162 with excellent off-state current characteristics can be obtained with the use of such an i-type or substantially i-type oxide semiconductor. For example, when the drain voltage VD is +1 V or +10 V and the gate voltage VG is set in the range of from −20 V to −5 V, the off-state current is 1×10−13 A or less. The oxide semiconductor layer 140 which is purified by a sufficient reduction in hydrogen concentration as described above is used so that the off-state current of the transistor 162 is reduced, whereby a semiconductor device with a novel structure can be realized. Note that the above hydrogen concentration of the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS).
Note that an oxide semiconductor included in the oxide semiconductor layer is not particularly limited as long as it has a non-single-crystal structure. A variety of structures, such as an amorphous structure, a microcrystalline (nano-crystalline or the like) structure, a polycrystalline structure, a structure in which micro-crystals or poly-crystals are included in an amorphous material, or a structure in which micro-crystals or poly-crystals are formed at a surface of an amorphous structure, can be employed.
An insulating layer 156 is provided over the interlayer insulating layer 152. An electrode 158a, an electrode 158b, an electrode 158c, and an electrode 158d are provided so as to be embedded in the insulating layer 156. The electrode 158a is in contact with the electrode 154a. The electrode 158b is in contact with the electrode 154b. The electrode 158c is in contact with the electrode 154c and the electrode 154d. The electrode 158d is in contact with the electrode 154e. 
In other words, the source or drain electrode 142a of the transistor 162 is electrically connected to another element (such as the transistor including a material other than an oxide semiconductor) through an electrode 130c, the electrode 136c, the electrode 154c, the electrode 158c, and the electrode 154d (see FIG. 1A). In addition, the source or drain electrode 142b of the transistor 162 is electrically connected to another element through the electrode 154e and the electrode 158d. Note that the structure of connection electrodes (such as the electrode 130c, the electrode 136c, the electrode 154c, the electrode 158c, and the electrode 154d) is not limited to the above structure, and appropriate addition, omission, or the like is possible.
FIG. 1B illustrates the case where the connection relationship of the source or drain electrode 142a of the transistor 162 differs from that in FIG. 1A. Specifically, the source or drain electrode 142a is electrically connected to an electrode 110b through the electrode 130c, the electrode 136c, the electrode 154c, the electrode 158c, and the electrode 154d. Here, the electrode 110b is formed in a manner similar to that of the gate electrode 110a. The electrode 110b may be a component of a transistor or may be part of a wiring or the like. Note that the structure of connection electrodes (such as the electrode 130c, the electrode 136c, the electrode 154c, the electrode 158c, and the electrode 154d) is not limited to the above structure, and appropriate addition, omission, or the like is possible.
Although two examples of typical connection relationships are given above, an embodiment of the disclosed invention is not limited to these examples. For example, the structure illustrated in FIG. 1A and the structure illustrated in FIG. 1B may be combined. Furthermore, the gate electrode 110a of the transistor 160 and the source or drain electrode 142a of the transistor 162 may be electrically connected to each other.
<Manufacturing Method of Semiconductor Device>
Next, an example of a manufacturing method of the above semiconductor device will be described. First, a manufacturing method of the transistor 160 will be described below with reference to FIGS. 2A to 2H, and then a manufacturing method of the transistor 162 will be described with reference to FIGS. 3A to 3E and FIGS. 4A to 4D. Note that FIGS. 2A to 2H illustrate only a cross section corresponding to A1-A2 in FIG. 1A. In addition, FIGS. 3A to 3E and FIGS. 4A to 4D illustrate a cross section corresponding to A1-A2 and B1-B2 in FIG. 1A.
<Manufacturing Method of Lower Transistor>
First, a substrate 100 including a semiconductor material is prepared (see FIG. 2A). A single crystal semiconductor substrate of silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate of silicon germanium or the like, an SOL substrate, or the like can be used as the substrate 100 including a semiconductor material. Here, an example of the case where a single crystal silicon substrate is used as the substrate 100 including a semiconductor material is described. Note that the term “SOI substrate” generally means a substrate where a silicon semiconductor layer is provided over an insulating surface. In this specification and the like, the term “SOI substrate” also means a substrate where a semiconductor layer including a material other than silicon is provided over an insulating surface. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer. Moreover, the SOI substrate can be a substrate having a structure where a semiconductor layer is provided over an insulating substrate such as a glass substrate.
A protective layer 102 serving as a mask for forming an element isolation insulating layer is formed over the substrate 100 (see FIG. 2A). As the protective layer 102, an insulating layer formed using a material such as silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used, for example. Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100 in order to control the threshold voltage of the transistor. When the semiconductor material included in the substrate 100 is silicon, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Boron, aluminum, gallium, or the like can be used as the impurity imparting p-type conductivity.
Next, part of the substrate 100 in a region not covered with the protective layer 102 (i.e., in an exposed region) is removed by etching using the protective layer 102 as a mask. Thus, an isolated semiconductor region 104 is formed (see FIG. 2B). As the etching, dry etching is preferably performed, but wet etching may be performed. An etching gas or an etchant can be selected as appropriate depending on a material to be etched.
Then, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in a region overlapping with the semiconductor region 104 is selectively removed, so that the element isolation insulating layer 106 is formed (see FIG. 2B). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a method for removing the insulating layer, any of etching treatment and polishing treatment such as CMP can be employed. Note that the protective layer 102 is removed after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106.
Next, an insulating layer is formed over the semiconductor region 104, and a layer including a conductive material is formed over the insulating layer.
Because the insulating layer serves as a gate insulating layer later, the insulating layer preferably has a single-layer structure or a layered structure using a film containing silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like formed by a CVD method, a sputtering method, or the like. Alternatively, the insulating layer may be formed in such a manner that a surface of the semiconductor region 104 is oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment. The high-density plasma treatment can be performed using, for example, a mixed gas of a rare gas such as He, Ar, Kr, or Xe and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. There is no particular limitation on the thickness of the insulating layer; the insulating layer can have a thickness of 1 nm to 100 nm, for example.
The layer including a conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The layer including a conductive material may be formed using a semiconductor material such as polycrystalline silicon which contains an impurity element imparting conductivity. There is no particular limitation on the method for forming the layer including a conductive material, and a variety of film formation methods such as an evaporation method, a CVD method, a sputtering method, or a spin coating method can be employed. Note that this embodiment shows an example of the case where the layer including a conductive material is formed using a metal material.
After that, the insulating layer and the layer including a conductive material are selectively etched; thus, the gate insulating layer 108a and the gate electrode 110a are formed (see FIG. 2C).
Next, an insulating layer 112 that covers the gate electrode 110a is formed (see FIG. 2C). Then, the impurity regions 114 with a shallow junction depth are formed by adding phosphorus (P), arsenic (As), or the like to the semiconductor region 104 (see FIG. 2C). Note that phosphorus or arsenic is added here in order to form an n-channel transistor; an impurity element such as boron (B) or aluminum (Al) may be added in the case of forming a p-channel transistor. By formation of the impurity regions 114, the channel formation region 116 is formed in the semiconductor region 104 below the gate insulating layer 108a (see FIG. 2C). Here, the concentration of the impurity added can be set as appropriate; the concentration is preferably high when a semiconductor element is highly miniaturized. The process in which the impurity regions 114 are formed after the formation of the insulating layer 112 is employed here; alternatively, the insulating layer 112 may be formed after the formation of the impurity regions 114.
Next, the sidewall insulating layer 118 is formed (see FIG. 2D). An insulating layer is formed so as to cover the insulating layer 112 and then subjected to highly anisotropic etching, whereby the sidewall insulating layer 118 can be formed in a self-aligned manner. At this time, it is preferable to partly etch the insulating layer 112 so that a top surface of the gate electrode 110a and top surfaces of the impurity regions 114 are exposed.
Next, an insulating layer is formed so as to cover the gate electrode 110a, the impurity regions 114, the sidewall insulating layer 118, and the like. Then, phosphorus (P), arsenic (As), or the like is added to regions in contact with the impurity regions 114; thus, the high-concentration impurity regions 120 are formed (see FIG. 2E). After that, the insulating layer is removed, and a metal layer 122 is formed so as to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity regions 120, and the like (see FIG. 2E). The metal layer 122 can be formed by a variety of film formation methods such as a vacuum evaporation method, a sputtering method, and a spin coating method. The metal layer 122 is preferably formed using a metal material which reacts with a semiconductor material included in the semiconductor region 104 and forms a low-resistance metal compound. Examples of such a metal material are titanium, tantalum, tungsten, nickel, cobalt, platinum, and the like.
Next, heat treatment is performed so that the metal layer 122 reacts with the semiconductor material. Thus, the metal compound regions 124 that are in contact with the high-concentration impurity regions 120 are formed (see FIG. 2F). Note that when the gate electrode 110a is formed using polycrystalline silicon or the like, a metal compound region is also formed in a portion of the gate electrode 110a in contact with the metal layer 122.
As the heat treatment, irradiation with a flash lamp can be employed, for example. Although it is needless to say that another heat treatment method may be used, a method by which heat treatment can be achieved in an extremely short time is preferably used in order to improve the controllability of chemical reaction for formation of the metal compound. Note that the metal compound regions are formed by reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can properly reduce the electric resistance and improve element characteristics. Note that the metal layer 122 is removed after the metal compound regions 124 are formed.
Then, the interlayer insulating layer 126 and the interlayer insulating layer 128 are formed so as to cover the components formed in the above steps (see FIG. 2G). The interlayer insulating layers 126 and 128 can be formed using a material including an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Moreover, the interlayer insulating layers 126 and 128 can be formed using an organic insulating material such as polyimide or acrylic. Note that a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is employed here, however, the structure of an interlayer insulating layer is not limited to this structure. After the formation of the interlayer insulating layer 128, a surface of the interlayer insulating layer 128 is preferably planarized by CMP, etching, or the like.
Then, openings that reach the metal compound regions 124 are formed in the interlayer insulating layers, and the source or drain electrode 130a and the source or drain electrode 130b are formed in the openings (see FIG. 2H). The source or drain electrode 130a and the source or drain electrode 130b can be formed in such a manner, for example, that a conductive layer is formed in a region including the openings by a PVD method, a CVD method, or the like and then part of the conductive layer is removed by etching, CMP, or the like.
Note that in the case where the source or drain electrodes 130a and 130b are formed by removing part of the conductive layer, the process is preferably performed so that the surfaces are planarized. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the openings and then a tungsten film is formed so as to be embedded in the openings, excess tungsten, titanium, titanium nitride, or the like is removed and the planarity of the surface can be improved by subsequent CMP. The surface including the source or drain electrodes 130a and 130b is planarized in this manner, so that an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.
There is no particular limitation on a material which can be used for the source or drain electrodes 130a and 130b, and a variety of conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used. Only the source or drain electrodes 130a and 130b in contact with the metal compound regions 124 are shown here; however, the electrode 130c in FIG. 1A or 1B and the like can also be formed in this step.
Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the openings. Here, the titanium film formed by a PVD method functions to reduce an oxide film which may be formed at the surface of the metal compound regions and to decrease the contact resistance with the metal compound regions. The titanium nitride film formed after the formation of the titanium film has a barrier function for suppressing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of the barrier film of titanium, titanium nitride, or the like. Note that not only a so-called single damascene method but also a dual damascene method may be employed.
Through the above steps, the transistor 160 is formed with the use of the substrate including a semiconductor material. Note that an electrode, a wiring, an insulating layer, or the like may further be formed after the above steps. When a multilayer wiring structure in which interlayer insulating layers and conductive layers are stacked is employed, a highly integrated semiconductor device can be provided.
<Manufacturing Method of Upper Transistor>
Next, a process for manufacturing the transistor 162 over the interlayer insulating layer 128 will be described with reference to FIGS. 3A to 3E and FIGS. 4A to 4D. Note that FIGS. 3A to 3E and FIGS. 4A to 4D illustrate steps for manufacturing electrodes, the transistor 162, and the like over the interlayer insulating layer 128; therefore, the transistor and the like placed below the transistor 162 are omitted.
First, an insulating layer 134 is formed over the interlayer insulating layer 128, the source or drain electrodes 130a and 130b, and the electrode 130c. Next, openings that reach the source or drain electrodes 130a and 130b and the electrode 130c are formed in the insulating layer 134. Then, a conductive layer is formed so as to be embedded in the openings. After that, part of the conductive layer is removed by a method such as etching or CMP; thus, the insulating layer 134 is exposed and the electrodes 136a, 136b, and 136c are formed (see FIG. 3A).
The insulating layer 134 can be formed by a PVD method, a CVD method, or the like. The insulating layer 134 can be formed using a material including an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.
The openings in the insulating layer 134 can be formed by a method such as etching using a mask. The mask can be formed by a method such as light exposure using a photomask. Either wet etching or dry etching may be used as the etching; dry etching is preferably used in terms of microfabrication.
The conductive layer can be formed by a PVD method, a CVD method, or the like. The conductive layer can be formed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.
Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the openings. Here, the titanium film formed by a PVD method functions to reduce an oxide film which may be formed at the surface of lower electrodes (here, the source or drain electrodes 130a and 130b, the electrode 130c, and the like) and to decrease the contact resistance with the lower electrodes. The titanium nitride film formed after the formation of the titanium film has a barrier function for suppressing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of the barrier film of titanium, titanium nitride, or the like. Note that not only a so-called single damascene method but also a dual damascene method may be employed.
When the electrodes 136a, 136b, and 136c are formed, the process is preferably performed so that the surfaces are planarized by CMP or the like. The surfaces of the insulating layer 134 and the electrodes 136a, 136b, and 136c are planarized in this manner, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.
Next, the insulating layer 138 is formed so as to cover the insulating layer 134 and the electrodes 136a, 136b, and 136c. Then, an oxide semiconductor layer is formed over the insulating layer 138, and the oxide semiconductor layer is processed by a method such as etching using a mask; thus, the oxide semiconductor layer 140 having an island shape is formed (see FIG. 3B).
The insulating layer 138 functions as a base and can be formed by a CVD method, a sputtering method, or the like. The insulating layer 138 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 138 may have a single-layer structure or a layered structure. There is no particular limitation on the thickness of the insulating layer 138; the insulating layer 138 can have a thickness of 10 nm to 500 nm, for example. Here, the insulating layer 138 is not an essential component; therefore, a structure in which the insulating layer 138 is not provided is also possible.
If hydrogen, water, or the like is contained in the insulating layer 138, hydrogen may enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, whereby characteristics of the transistor may be degraded. Therefore, it is desirable to form the insulating layer 138 so as to include as little hydrogen or water as possible.
In the case of using a sputtering method or the like, for example, it is desirable that the insulating layer 138 be formed in a state where moisture remaining in the treatment chamber is removed. In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbo pump provided with a cold trap may be used. From the treatment chamber evacuated with a cryopump or the like, hydrogen, water, or the like is sufficiently removed; thus, the concentration of an impurity in the insulating layer 138 can be reduced.
When the insulating layer 138 is formed, it is desirable to use a high-purity gas in which an impurity such as hydrogen or water is reduced so that the concentration is decreased to approximately a value expressed in the unit “ppm” (preferably, “ppb”).
As the oxide semiconductor layer, an oxide semiconductor layer formed using any of the following materials can be applied: four-component metal oxide such as In—Sn—Ga—Zn—O; three-component metal oxide such as In—Ga—Zn—O, In—Sn—Zn—O, In—Al—Zn—O, Sn—Ga—Zn—O, Al—Ga—Zn—O, and Sn—Al—Zn—O; two-component metal oxide such as In—Zn—O, Sn—Zn—O, Al—Zn—O, Zn—Mg—O, Sn—Mg—O, and In—Mg—O; In—O; Sn—O; and Zn—O. In addition, the above oxide semiconductor material may include SiO2.
As the oxide semiconductor layer, a thin film including a material represented by InMO3(ZnO)m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like. An oxide semiconductor material which is represented by InMO3(ZnO)m (m>0) and includes Ga as M may be referred to as an In—Ga—Zn—O oxide semiconductor, and a thin film of the In—Ga—Zn—O oxide semiconductor may be referred to as an In—Ga—Zn—O oxide semiconductor film (an In—Ga—Zn—O amorphous film) or the like.
In this embodiment, as the oxide semiconductor layer, an amorphous oxide semiconductor layer is formed by a sputtering method using a target for depositing an In—Ga—Zn—O-based oxide semiconductor. Note that since crystallization of an amorphous oxide semiconductor layer can be suppressed by adding silicon to the amorphous oxide semiconductor layer, an oxide semiconductor layer may be formed, for example, using a target including SiO2 of 2 wt % to 10 wt %.
As a target used for forming the oxide semiconductor layer by a sputtering method, a metal oxide target containing zinc oxide as its main component can be used, for example. Moreover, a target for depositing an oxide semiconductor including In, Ga, and Zn (a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] or In:Ga:Zn=1:1:0.5 [atomic ratio]), or the like can be used, for example. Furthermore, a target for depositing an oxide semiconductor including In, Ga, and Zn (having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] or a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio]) may be used. The filling rate of a target for depositing an oxide semiconductor is 90% to 100%, preferably 95% or higher (e.g., 99.9%). A dense oxide semiconductor layer is formed using a target for depositing an oxide semiconductor with a high filling rate.
The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically, argon) and oxygen. Specifically, it is preferable to use a high-purity gas atmosphere, for example, from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed so that the concentration is decreased to approximately a value expressed in the unit “ppm” (preferably, “ppb”).
In forming the oxide semiconductor layer, the substrate is held in a treatment chamber that is maintained under reduced pressure, and the substrate is heated to a temperature of 100° C. to 600° C., preferably 200° C. to 400° C. Then, a sputtering gas from which hydrogen and water are removed is introduced into the treatment chamber from which remaining moisture is removed, and the oxide semiconductor layer is formed using metal oxide as a target. By forming the oxide semiconductor layer while heating the substrate, the concentration of an impurity in the oxide semiconductor layer can be decreased. Moreover, damage due to sputtering is reduced. In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, a titanium sublimation pump, or the like can be used. A turbo pump provided with a cold trap may be used. From the treatment chamber evacuated with a cryopump or the like, hydrogen, water, or the like is sufficiently removed; thus, the concentration of an impurity in the oxide semiconductor layer can be reduced.
For example, the conditions for forming the oxide semiconductor layer can be as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen atmosphere (the proportion of the oxygen flow is 100%). Note that a pulsed direct current (DC) power source is preferably used because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer is set in the range of 2 nm to 200 nm, preferably 5 nm to 30 nm. Note that the appropriate thickness of the oxide semiconductor layer differs depending on the oxide semiconductor material to be used, the intended use, or the like; therefore, the thickness may be determined as appropriate in accordance with the material, the intended use, or the like.
Note that before the oxide semiconductor layer is formed by a sputtering method, reverse sputtering in which plasma is generated with an argon gas introduced is preferably performed so that a material attached to the surface of the insulating layer 138 is removed. Here, the reverse sputtering is a method by which ions collide with a surface to be processed so that the surface is modified, in contrast to normal sputtering by which ions collide with a sputtering target. An example of a method for making ions collide with a surface to be processed is a method in which high-frequency voltage is applied to the surface in an argon atmosphere so that plasma is generated near a substrate. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of an argon atmosphere.
As a method for etching the oxide semiconductor layer, either dry etching or wet etching may be employed. It is needless to say that dry etching and wet etching can be used in combination. The etching conditions (e.g., an etching gas or an etchant, etching time, and temperature) are set as appropriate depending on the material so that the oxide semiconductor layer can be etched into a desired shape.
As the dry etching method, a parallel plate reactive ion etching (RIE) method, an inductively coupled plasma (ICP) etching method, or the like can be used. Also in this case, etching conditions (e.g., the amount of electric power applied to a coiled electrode, the amount of electric power applied to an electrode on the substrate side, and the electrode temperature on the substrate side) need to be set as appropriate.
An example of an etching gas which can be used for dry etching is a gas containing chlorine (a chlorine-based gas such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4)). Moreover, a gas containing fluorine (a fluorine-based gas such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3)), hydrogen bromide (HBr), oxygen (O2), any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, or the like may be used.
An example of an etchant which can be used for wet etching includes a mixed solution of phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide mixture (hydrogen peroxide solution of 31 wt %:ammonia solution of 28 wt %:water=5:2:2), or the like. An etchant such as ITO-07N (produced by KANTO CHEMICAL CO., INC.) may also be used.
Then, first heat treatment is preferably performed on the oxide semiconductor layer. Water (including a hydroxyl group), hydrogen, or the like contained in the oxide semiconductor layer can be removed by the first heat treatment. The temperature of the first heat treatment is set in the range of 300° C. to 800° C., preferably 400° C. to 700° C. For example, the substrate is introduced into an electric furnace including a resistance heating element or the like, and the oxide semiconductor layer 140 is subjected to heat treatment at 450° C. for one hour in a nitrogen atmosphere. The oxide semiconductor layer 140 is not exposed to the air during the heat treatment so that entry of water or hydrogen can be prevented.
The heat treatment apparatus is not limited to the electric furnace and can be an apparatus for heating an object to be processed by thermal radiation or thermal conduction from a medium such as a heated gas. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object by heat treatment, for example, nitrogen or a rare gas such as argon is used.
For example, as the first heat treatment, a GRTA process may be performed as follows. The substrate is put in an inert gas atmosphere that has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and taken out of the inert gas atmosphere. The GRTA process enables high-temperature heat treatment in a short time. Moreover, the GRTA process can be employed even when the temperature exceeds the upper temperature limit of the substrate because the heat treatment can be achieved in a short time. In the case where an SOI substrate including a substrate with relatively low heat resistance, such as a glass substrate, is used, shrinkage of the substrate becomes a problem at a temperature higher than the upper temperature limit (strain point) but does not in the case of performing heat treatment in a short time. Note that the inert gas may be switched to a gas including oxygen during the process. This is because defects caused by oxygen deficiency can be reduced by performing the first heat treatment in an atmosphere including oxygen.
Note that as the inert gas atmosphere, an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).
Depending on the conditions of the first heat treatment or the material included in the oxide semiconductor layer, the oxide semiconductor layer is sometimes crystallized to be microcrystalline or polycrystalline. For example, the oxide semiconductor layer sometimes becomes a microcrystalline oxide semiconductor layer having a degree of crystallization of 90% or more, or 80% or more. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer containing no crystalline component.
Furthermore, in the oxide semiconductor layer, micro-crystals (the grain size is 1 nm to 20 nm, typically 2 nm to 4 nm) are sometimes mixed in an amorphous oxide semiconductor (e.g., at a surface of the oxide semiconductor layer). The electrical characteristics of the oxide semiconductor layer can also be changed by mixing and aligning micro-crystals in an amorphous semiconductor in the above manner.
For example, when the oxide semiconductor layer is formed using a target for depositing an In—Ga—Zn—O-based oxide semiconductor, the electrical characteristics of the oxide semiconductor layer can be changed by formation of a microcrystalline region in which crystal grains of In2Ga2ZnO7 with electrical anisotropy are aligned. The microcrystalline region is preferably a region in which the crystal grains are arranged so that the c-axis of In2Ga2ZnO7 is perpendicular to a surface of the oxide semiconductor layer, for example. By forming a region in which crystal grains are arranged in such a manner, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved and insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Furthermore, such a microcrystalline region functions to suppress entry of an impurity such as water or hydrogen into the oxide semiconductor layer.
Note that the oxide semiconductor layer including the microcrystalline region can be formed by heating the surface of the oxide semiconductor layer by a GRTA process. Further, the oxide semiconductor layer can be formed in a more preferred manner by using a sputtering target in which the amount of Zn is smaller than that of In or Ga.
The first heat treatment of the oxide semiconductor layer 140 can be performed on the oxide semiconductor layer that has not yet been processed into the oxide semiconductor layer 140 having an island shape. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography step is performed.
Note that the first heat treatment can also be referred to as dehydration treatment, dehydrogenation treatment, or the like. The dehydration treatment or dehydrogenation treatment can be performed, for example, after the oxide semiconductor layer is formed, after a source electrode and a drain electrode are stacked over the oxide semiconductor layer 140, or after a gate insulating layer is formed over the source electrode and the drain electrode. Such dehydration treatment or dehydrogenation treatment may be performed once or plural times.
Next, a conductive layer 142 is formed so as to be in contact with the oxide semiconductor layer 140 and then an insulating layer 144 is formed over the conductive layer 142 (see FIG. 3C). Note that the insulating layer 144 is not an essential component but is effective in selectively oxidizing a side surface of a source electrode and a drain electrode to be formed later.
The conductive layer 142 can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 142 can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy including any of these elements as a component, or the like. A material including one or more of manganese, magnesium, zirconium, beryllium, and thorium may be used. A material including aluminum and one or more of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
The conductive layer 142 may also be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an indium oxide-tin oxide alloy (In2O3—SnO2, which is abbreviated to ITO in some cases), an indium oxide-zinc oxide alloy (In2O3—ZnO), or any of these metal oxide materials in which silicon or silicon oxide is included can be used.
The conductive layer 142 may have a single-layer structure or a layered structure including two or more layers. For example, the conductive layer 142 may have a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Here, a three-layer structure of a titanium film, an aluminum film, and a titanium film is employed.
Note that an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the conductive layer 142. The oxide conductive layer and the conductive layer can be formed successively (successive formation). With such an oxide conductive layer, the resistance of a source region or a drain region can be lowered, which makes it possible to achieve high-speed operation of the transistor.
The insulating layer 144 can be formed by a CVD method, a sputtering method, or the like. The insulating layer 144 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 144 may have a single-layer structure or a layered structure. There is no particular limitation on the thickness of the insulating layer 144; the insulating layer 144 can have a thickness of 10 nm to 500 nm, for example.
Next, the conductive layer 142 and the insulating layer 144 are selectively etched; thus, the source or drain electrode 142a, the source or drain electrode 142b, an insulating layer 144a, and an insulating layer 144b are formed. Then, oxidation treatment is performed in order to supply oxygen to the oxide semiconductor layer 140. By the oxidation treatment, the oxide regions 143 are formed in part of the source or drain electrode 142a and the source or drain electrode 142b (see FIG. 3D). In addition, as indicated by a dotted line, a region supplied with oxygen is formed in the oxide semiconductor layer 140. Note that the range of the region supplied with oxygen changes variously depending on the material included in the oxide semiconductor layer 140, the conditions of the oxidation treatment, or the like. For example, oxygen can also be supplied to the lower interface of the oxide semiconductor layer 140.
For light exposure in forming a mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is preferably used. Particularly for light exposure in the case where the channel length (L) is less than 25 nm, light exposure for forming a mask is preferably performed with extreme ultraviolet light whose wavelength is several nanometers to several tens of nanometers, which is extremely short. In light exposure using extreme ultraviolet light, resolution is high and depth of focus is large. Therefore, the channel length (L) of a transistor, which is formed later, can also be 10 nm to 1000 nm. By a decrease in channel length by such a method, operation speed can be improved. In addition, the off-state current of a transistor including the above-described oxide semiconductor is small; thus, an increase in power consumption due to miniaturization of the transistor can be suppressed.
The materials and etching conditions of the conductive layer 142 and the oxide semiconductor layer 140 are adjusted as appropriate so that the oxide semiconductor layer is not removed in etching of the conductive layer 142. Note that in some cases, the oxide semiconductor layer 140 is partly etched in the etching step and thus has a groove portion (a recessed portion) depending on the materials and the etching conditions.
In order to reduce the number of masks to be used and reduce the number of steps, an etching step may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted to have a plurality of intensities. A resist mask formed with the use of a multi-tone mask has a plurality of thicknesses (has a stair-like shape) and further can be changed in shape by ashing; therefore, the resist mask can be used in a plurality of etching steps. That is, a resist mask corresponding to at least two kinds of different patterns can be formed by using one multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced, whereby a process can be simplified.
The oxidation treatment is preferably performed using oxygen plasma excited with a microwave (300 MHz to 300 GHz), which may be referred to as plasma oxidation treatment. The reason is that high-density plasma is realized by plasma excitation with a microwave and damage to the oxide semiconductor layer 140 can be sufficiently reduced.
Specifically, the above treatment can be performed, for example, at a frequency of 300 MHz to 300 GHz (typically, 2.45 GHz) under a pressure of 50 Pa to 5000 Pa (typically, 500 Pa) at a substrate temperature of 200° C. to 400° C. (typically, 300° C.) with the use of a mixed gas of oxygen and argon.
By the above oxidation treatment, oxygen is supplied to the oxide semiconductor layer 140. Therefore, damage to the oxide semiconductor layer 140 can be sufficiently reduced, and in addition, localized states due to oxygen deficiency can be reduced. In other words, characteristics of the oxide semiconductor layer 140 can be further improved.
Note that without limitation to the plasma oxidation treatment with a microwave, any other method that enables a sufficient reduction in damage to the oxide semiconductor layer and a supply of oxygen to the oxide semiconductor layer 140 can be used. For example, a method such as heat treatment in an atmosphere including oxygen can be used.
In combination with the oxidation treatment, treatment for removing water, hydrogen, or the like from the oxide semiconductor layer 140 may be performed. For example, plasma treatment using a gas such as nitrogen or argon can be performed.
Note that by the oxidation treatment, the oxide regions 143 are formed in part of the source or drain electrode 142a and the source or drain electrode 142b (particularly, portions corresponding to side surfaces thereof). The oxide regions 143 are effective particularly when the transistor 162 is miniaturized (for example, when the channel length is shorter than 1000 nm). With the miniaturization of the transistor, the gate insulating layer needs to have a smaller thickness. The reason why the oxide regions 143 are provided is that the oxide regions 143 can prevent short circuit between the gate electrode and the source or drain electrodes, which may be caused by a reduction in thickness of the gate insulating layer or defective coverage therewith. Note that the oxide regions 143 are sufficiently effective when having a thickness of 5 nm or more (preferably, 10 nm or more).
The oxidation treatment is also effective in terms of improvement in film quality of an exposed portion of the insulating layer 138.
Note that the insulating layer 144a and the insulating layer 144b are important in that these insulating layers function to prevent oxidation of upper portions of the source or drain electrode 142a and the source or drain electrode 142b. This is because it is significantly difficult to perform the plasma treatment while the mask used for etching remains.
Although FIG. 3D illustrates the case where the source or drain electrode 142a, the source or drain electrode 142b, the insulating layer 144a, and the insulating layer 144b are formed at a time by selectively etching the conductive layer 142 and the insulating layer 144, an embodiment of the disclosed invention is not limited to this example.
For example, the source or drain electrode 142a, the source or drain electrode 142b, the insulating layer 144a, and the insulating layer 144b may be completed as follows: an opening that reaches the channel formation region of the transistor is formed by selective etching of only a region of the conductive layer 142 and the insulating layer 144 which overlaps the oxide semiconductor layer 140; then, the region is subjected to the plasma treatment so that oxygen is supplied to the oxide semiconductor layer 140 and the exposed portion of the conductive layer 142 is oxidized; then, etching is performed again. In the case of employing such steps, oxidation treatment can be performed on only an intended portion. Therefore, there is an advantage that the other portion can be prevented from being adversely affected by the oxidation treatment.
Next, the gate insulating layer 146 is formed in contact with part of the oxide semiconductor layer 140 without exposure to the air (see FIG. 3E). The gate insulating layer can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 146 may have a single-layer structure or a layered structure. There is no particular limitation on the thickness of the gate insulating layer 146; the gate insulating layer 146 can have a thickness of 10 nm to 500 nm, for example.
Note that an i-type or substantially i-type oxide semiconductor obtained by removing an impurity (a purified oxide semiconductor) is highly susceptible to interface states or interface charges; therefore, the gate insulating layer 146 needs to have high quality.
For example, a high-density plasma CVD method using a microwave (e.g., 2.45 GHz) is favorable in that the gate insulating layer 146 can be dense and have high withstand voltage and high quality. This is because a close contact between a purified oxide semiconductor layer and a high-quality gate insulating layer reduces interface states and produces desirable interface characteristics.
It is needless to say that another method such as a sputtering method or a plasma CVD method can also be employed as long as a high-quality insulating layer can be formed as the gate insulating layer 146. Moreover, it is possible to use an insulating layer whose quality, interface characteristics, or the like is improved with heat treatment performed after the formation of the insulating layer. In any case, an insulating layer that has a reduced interface state density and can form a favorable interface with an oxide semiconductor layer, as well as having favorable film quality as the gate insulating layer 146, is formed.
By thus improving characteristics of the interface with a gate insulating layer and eliminating an impurity, particularly hydrogen, water, or the like, from an oxide semiconductor, it is possible to obtain a stable transistor whose threshold voltage (Vth) does not change with a gate bias-temperature stress test (BT test, e.g., at 85° C. and 2×106 V/cm for 12 hours).
After that, second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is set in the range of 200° C. to 400° C., preferably 250° C. to 350° C. For example, the heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. The second heat treatment can reduce variation in electric characteristics of the transistor. Note that the second heat treatment is performed in this embodiment after the gate insulating layer 146 is formed; there is no particular limitation on the timing of the second heat treatment as long as it is performed after the first heat treatment.
Next, the gate electrode 148 is formed over the gate insulating layer 146 in a region overlapping the oxide semiconductor layer 140 (see FIG. 4A). The gate electrode 148 can be formed by forming a conductive layer over the gate insulating layer 146 and then selectively patterning the conductive layer.
The conductive layer can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy including any of these elements as a component, or the like. A material including one or more of manganese, magnesium, zirconium, beryllium, and thorium may be used. A material including aluminum and one or more of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
The conductive layer may also be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an indium oxide-tin oxide alloy (In2O3—SnO2, which is abbreviated to ITO in some cases), an indium oxide-zinc oxide alloy (In2O3—ZnO), or any of these metal oxide materials in which silicon or silicon oxide is included can be used.
The conductive layer may have a single-layer structure or a layered structure including two or more layers. For example, the conductive layer may have a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Here, the conductive layer is formed using a material including titanium and then processed into the gate electrode 148.
Next, the interlayer insulating layer 150 and the interlayer insulating layer 152 are formed over the gate insulating layer 146 and the gate electrode 148 (see FIG. 4B). The interlayer insulating layers 150 and 152 can be formed by a PVD method, a CVD method, or the like. The interlayer insulating layers 150 and 152 can be formed using a material including an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that a layered structure of the interlayer insulating layers 150 and 152 is used in this embodiment, but an embodiment of the disclosed invention is not limited to this example. A single-layer structure or a layered structure including three or more layers can also be used.
Note that the interlayer insulating layer 152 is desirably formed so as to have a flat surface. This is because an electrode, a wiring, or the like can be favorably formed over the interlayer insulating layer 152 when the interlayer insulating layer 152 is formed so as to have a flat surface.
Next, openings that reach the electrodes 136a, 136b, and 136c and the source or drain electrodes 142a and 142b are formed in the gate insulating layer 146 and the interlayer insulating layers 150 and 152. Then, a conductive layer is formed so as to be embedded in the openings. After that, part of the conductive layer is removed by a method such as etching or CMP. Thus, the interlayer insulating layer 152 is exposed and the electrodes 154a, 154b, 154c, 154d, and 154e are formed (see FIG. 4C).
The openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as light exposure using a photomask. Either wet etching or dry etching may be used as the etching, dry etching is preferably used in terms of microfabrication.
The conductive layer can be formed by a PVD method, a CVD method, or the like. The conductive layer can be formed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.
Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the openings. Here, the titanium film formed by a PVD method functions to reduce an oxide film which may be formed at the surface of lower electrodes (here, the electrodes 136a, 136b, and 136c, the source or drain electrodes 142a and 142b, and the like) and to decrease the contact resistance with the lower electrodes. The titanium nitride film formed after the formation of the titanium film has a barrier function for suppressing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of the barrier film of titanium, titanium nitride, or the like. Note that not only a so-called single damascene method but also a dual damascene method may be employed.
When part of the conductive layer is removed, the process is preferably performed so that the exposed surface of the interlayer insulating layer 152, the surface of the electrodes 154a, 154b, 154c, 154d, and 154e, and the like are planarized. The surfaces are planarized in this manner, whereby an electrode, a wiring, or the like can be favorably formed in a later step.
After that, the insulating layer 156 is formed, and openings that reach the electrodes 154a, 154b, 154c, 154d, and 154e are formed in the insulating layer 156. After a conductive layer is formed so as to be embedded in the openings, part of the conductive layer is removed by a method such as etching or CMP. Thus, the insulating layer 156 is exposed and the electrodes 158a, 158b, 158c, and 158d are formed (see FIG. 4D). This step is similar to the step of forming the electrode 154a and the like; therefore, the detailed description is not repeated.
In the case where the transistor 162 is formed by the above-described method, the hydrogen concentration of the oxide semiconductor layer 140 is 5×1019/cm3 or less and the off-state current of the transistor 162 is 1×10−13 A or less. The transistor 162 with excellent characteristics can be obtained by the application of the oxide semiconductor layer 140 that is purified by a sufficient reduction in hydrogen concentration and by a supply of oxygen as described above. Note that it is preferable that oxygen be supplied shortly after the hydrogen concentration is reduced because there is no possibility that hydrogen, water, or the like enters the oxide semiconductor layer and thus an oxide semiconductor layer with extremely favorable characteristics can be realized. It is needless to say that a treatment for reducing the hydrogen concentration and a treatment for supplying oxygen do not need to be performed successively as long as an oxide semiconductor layer with favorable characteristics can be realized. For example, another treatment may be performed between these treatments. Alternatively, these treatments may be performed at the same time.
In this embodiment, oxygen plasma treatment is performed on the oxide semiconductor layer 140 in order to supply oxygen to the oxide semiconductor layer 140. Accordingly, the transistor 162 has better characteristics. In addition, a region corresponding to a side surface of the source or drain electrode is oxidized thus, short circuit between the gate electrode and the source electrode (or the drain electrode), which may be caused by a reduction in thickness of the gate insulating layer, can be prevented.
Moreover, the transistor 160 including a material other than an oxide semiconductor is provided in the lower portion and the transistor 162 including an oxide semiconductor is provided in the upper portion; thus, it is possible to manufacture an excellent semiconductor device having characteristics of both of the transistors.
Note that considerable research has been done on properties of oxide semiconductors; however, the research does not include the idea of sufficiently reducing localized states themselves. According to an embodiment of the disclosed invention, a purified oxide semiconductor is manufactured by removing water and hydrogen, which might be a cause of localized states, from the oxide semiconductor. This is based on the idea of sufficiently reducing localized states themselves. Thus, excellent industrial products can be manufactured.
Note that oxygen may be removed while hydrogen, water, or the like is being removed. Therefore, it is preferable to realize a purified (i-type) oxide semiconductor in such a manner that oxygen is supplied to metal dangling bonds generated by oxygen deficiency so that the localized states due to oxygen deficiency are reduced. For example, an oxygen-excess oxide film is formed in close contact with a channel formation region and heat treatment is performed at a temperature of 200° C. to 400° C., typically 250° C., whereby oxygen can be supplied from the oxide film and the localized states due to oxygen deficiency can be reduced. An inert gas may be switched to a gas including oxygen during the second heat treatment. Further, after the second heat treatment, oxygen can be supplied to the oxide semiconductor through a temperature decreasing process in an oxygen atmosphere or an atmosphere in which hydrogen, water, or the like is sufficiently reduced.
It can be considered that a factor causing deterioration of characteristics of an oxide semiconductor is a shallow level due to excess hydrogen at 0.1 eV to 0.2 eV below the conduction band, a deep level due to oxygen deficiency, or the like. The technical idea that hydrogen is thoroughly eliminated and oxygen is adequately supplied in order to eliminate such a defect would be right.
An oxide semiconductor is generally considered as an n-type semiconductor; however, according to an embodiment of the disclosed invention, an i-type oxide semiconductor is realized by removing an impurity such as water or hydrogen and supplying oxygen which is a constituent element of the oxide semiconductor. In this respect, it can be said that an embodiment of the disclosed invention includes a novel technical idea because it is different from an i-type semiconductor such as silicon which is obtained by adding an impurity.
<Electrical Conduction Mechanism of Transistor Including Oxide Semiconductor>
An electrical conduction mechanism of a transistor including an oxide semiconductor will be described with reference to FIG. 5, FIG. 6, FIGS. 7A and 7B, and FIG. 8. Note that the following description is based on the assumption of an ideal situation for easy understanding and does not necessarily reflect a real situation. Note also that the following description is just a consideration and does not affect the validity of the invention.
FIG. 5 is a cross-sectional view of a transistor (thin film transistor) including an oxide semiconductor. An oxide semiconductor layer (OS) is provided over a gate electrode (GE1) with a gate insulating layer (GI) interposed therebetween, and a source electrode (S) and a drain electrode (D) are provided thereover. An insulating layer is provided so as to cover the source electrode (S) and the drain electrode (D).
FIG. 6 is an energy band diagram (schematic diagram) of the A-A′ section in FIG. 5. In FIG. 6, a black circle (●) represents an electron, a white circle (◯) represents a hole, and each has electric charges. With a positive voltage (VD>0) applied to the drain electrode, the dashed line shows the case where no voltage is applied to the gate electrode (VG=0) and the solid line shows the case where a positive voltage is applied to the gate electrode (VG>0). In the case where no voltage is applied to the gate electrode, carriers (electrons) are not injected to the oxide semiconductor side from an electrode because of high potential barrier, so that a current does not flow, which means an off state. On the other hand, when a positive voltage is applied to the gate electrode, potential barrier is lowered, and thus a current flows, which means an on state.
FIGS. 7A and 7B are energy band diagrams (schematic diagrams) of the B-B′ section in FIG. 5. FIG. 7A illustrates an on state in which a positive potential (+qVG) is applied to the gate electrode (GE1) and carriers (electrons) flow between the source electrode and the drain electrode. FIG. 7B illustrates an off state in which a negative potential (−qVG) is applied to the gate electrode (GE1) and minority carriers do not flow.
FIG. 8 illustrates the relationships between the vacuum level and the work function of a metal (φM) and between the vacuum level and the electron affinity (χ) of an oxide semiconductor.
At normal temperature, electrons in the metal are degenerated and the Fermi level is located in the conduction band. On the other hand, a conventional oxide semiconductor is an n-type semiconductor, in which the Fermi level (Ef) is away from the intrinsic Fermi level (Ei) located in the middle of a band gap and is located closer to the conduction band. Note that it is known that part of hydrogen is a donor in an oxide semiconductor and is one factor causing an oxide semiconductor to be an n-type semiconductor.
On the other hand, an oxide semiconductor according to one embodiment of the disclosed invention is an intrinsic (i-type) or a substantially intrinsic oxide semiconductor which is obtained by removing hydrogen that is a factor for an n-type semiconductor from an oxide semiconductor and purifying the oxide semiconductor such that an element other than a main component of the oxide semiconductor (i.e., an impurity element) is prevented from being contained therein as much as possible. In other words, a feature is that a purified i-type (intrinsic) semiconductor, or a semiconductor close thereto, is obtained not by adding an impurity element but by removing an impurity such as hydrogen or water as much as possible. Thus, the Fermi level (Ef) can be comparable with the intrinsic Fermi level (Ei).
It is said that the band gap (Eg) of an oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) included in the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In that case, a Schottky barrier for electrons is not formed at an interface between the metal and the oxide semiconductor.
At that time, the electron moves in the vicinity of the interface between the gate insulating layer and the purified oxide semiconductor (the lowest portion of the oxide semiconductor which is stable in terms of energy) as illustrated in FIG. 7A.
In addition, as illustrated in FIG. 7B, when a negative potential is applied to the gate electrode (GE1), the value of current is extremely close to zero because holes that are minority carriers are substantially zero.
In such a manner, an intrinsic (i-type) or substantially intrinsic oxide semiconductor is obtained by being purified such that an element other than its main element (i.e., an impurity element) is contained as little as possible. Thus, characteristics of the interface between the oxide semiconductor and the gate insulating layer become obvious. For that reason, the gate insulating layer needs to be able to form a favorable interface with the oxide semiconductor. Specifically, it is preferable to use, for example, an insulating layer formed by a CVD method using high-density plasma generated with a power supply frequency in the range of the VHF band to the microwave band, an insulating layer formed by a sputtering method, or the like.
When the oxide semiconductor is purified and the interface between the oxide semiconductor and the gate insulating layer is made favorable, in the case where the transistor has a channel width (W) of 1×104 μm and a channel length (L) of 3 μm, for example, it is possible to realize an off-state current of 10−13 A or less and a subthreshold swing (S-value) of 0.1 V/dec (with a 100-nm-thick gate insulating layer).
The oxide semiconductor is purified as described above so as to contain an element other than its main element (i.e., an impurity element) as little as possible, so that the thin film transistor can operate in a favorable manner.
<Resistance of Transistor Including Oxide Semiconductor to Hot Carrier Degradation>
Next, the resistance of a transistor including an oxide semiconductor to hot carrier degradation will be described with reference to FIGS. 9A and 9B, FIGS. 10A and 10B, and FIGS. 11A and 11B. Note that the following description is based on the assumption of an ideal situation for easy understanding and does not necessarily reflect a real situation. Note also that the following description is just a consideration.
Main causes of hot carrier degradation are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). Note that only electrons are considered below for simplicity.
CHE injection refers to a phenomenon in which electrons having gained energy higher than the barrier of a gate insulating layer in a semiconductor layer are injected into the gate insulating layer or the like. Electrons gain energy by being accelerated at a low electric field.
DAHC injection refers to a phenomenon in which electrons generated by collision of electrons accelerated by a high electric field are injected to a gate insulating layer or the like. A difference between DAHC injection and CHE injection is whether or not they involve avalanche breakdown caused by impact ionization. Note that DAHC injection requires electrons having a kinetic energy higher than a band gap of a semiconductor.
FIGS. 9A and 9B illustrate energy required for each hot carrier injection which is estimated from the band structure of silicon (Si), and FIGS. 10A and 10B illustrate energy required for each hot carrier injection which is estimated from the band structure of an In—Ga—Zn—O-based oxide semiconductor (IGZO). FIG. 9A and FIG. 10A show CHE injection and FIG. 9B and FIG. 10B show DAHC injection.
Regarding silicon, degradation caused by DAHC injection is more serious than that caused by CHE injection. This results from the fact that carriers (e.g., electrons) which are accelerated without colliding are very few in silicon whereas silicon has a narrow band gap and avalanche breakdown readily occurs therein. The avalanche breakdown increases the number of electrons capable of travelling over the barrier of the gate insulating layer, and the probability of DAHC injection readily becomes higher than that of CHE injection.
Regarding an In—Ga—Zn—O-based oxide semiconductor, the energy required for CHE injection does not greatly differ from that in the case of silicon, and the probability of CHE injection is still low. In addition, the energy required for DAHC injection is substantially equal to the energy required for CHE injection due to a wide band gap.
In other words, an In—Ga—Zn—O-based oxide semiconductor has low probabilities of both CHE injection and DAHC injection and has higher resistance to hot carrier degradation than silicon.
Meanwhile, the band gap of an In—Ga—Zn—O-based oxide semiconductor is comparable to that of silicon carbide (SiC) which attracts attention as a material having a high withstand voltage. FIGS. 11A and 11B illustrate energy required for each hot carrier injection regarding 4H—SiC. FIG. 11A shows CHE injection and FIG. 11B shows DAHC injection. Regarding CHE injection, an In—Ga—Zn—O-based oxide semiconductor has a slightly higher threshold and can be said to have an advantage.
As described above, it can be seen that an In—Ga—Zn—O-based oxide semiconductor has significantly higher resistance to hot carrier degradation and higher resistance to source-drain breakdown than silicon. It can also be said that a withstand voltage comparable to that of silicon carbide can be obtained.
<Short-Channel Effect in Transistor Including Oxide Semiconductor>
Next, a short-channel effect in a transistor including an oxide semiconductor will be described with reference to FIG. 12 and FIG. 13. Note that the following description is based on the assumption of an ideal situation for easy understanding and does not necessarily reflect a real situation. Note also that the following description is just a consideration.
The short-channel effect refers to degradation of electrical characteristics which becomes obvious with miniaturization of a transistor (a reduction in channel length (L)). The short-channel effect results from the effect of a drain on a source. Specific examples of the short-channel effect are a decrease in threshold voltage, an increase in subthreshold swing (S-value), an increase in leakage current, and the like.
Here, a structure capable of suppressing a short-channel effect is examined by device simulation. Specifically, four kinds of models each having a different carrier concentration and a different thickness of an oxide semiconductor layer were prepared, and the relationship between a channel length (L) and a threshold voltage (Vth) was checked. As the models, bottom-gate transistors were employed, in each of which an oxide semiconductor had a carrier concentration of 1.7×10−8/cm3 or 1.0×1015/cm3 and an oxide semiconductor layer had a thickness of 1 μm or 30 nm. Note that an In—Ga—Zn—O-based oxide semiconductor was used for the oxide semiconductor layer, and a silicon oxynitride film with a thickness of 100 nm was used as a gate insulating layer. It was assumed that, in the oxide semiconductor, the band gap was 3.15 eV, the electron affinity was 4.3 eV, the relative permittivity was 15, and the electron mobility was 10 cm2/Vs. The relative permittivity of the silicon oxynitride film was assumed to be 4.0. The calculation was performed using device simulation software “ATLAS” produced by Silvaco Inc.
Note that there is no significant difference in calculation results between a top-gate transistor and a bottom-gate transistor.
FIG. 12 and FIG. 13 show calculation results. FIG. 12 shows the case where the carrier concentration is 1.7×10−8/cm3 and FIG. 13 shows the case where the carrier concentration is 1.0×1015/cm3. FIG. 12 and FIG. 13 each show the amount of change (ΔVth) in threshold voltage (Vth) when a transistor whose channel length (L) is 10 μm is used as a reference and channel lengths (L) vary from 10 μm to 1 μm. As shown in FIG. 12, in the case where the carrier concentration in the oxide semiconductor was 1.7×10−8/cm3 and the thickness of the oxide semiconductor layer was 1 μm, the amount of change (ΔVth) in threshold voltage was −3.6 V. Moreover, as shown in FIG. 12, in the case where the carrier concentration in the oxide semiconductor was 1.7×10−8/cm3 and the thickness of the oxide semiconductor layer was 30 nm, the amount of change (ΔVth) in threshold voltage was −0.2 V. In addition, as shown in FIG. 13, in the case where the carrier concentration in the oxide semiconductor was 1.0×1015/cm3 and the thickness of the oxide semiconductor layer was 1 μm, the amount of change (ΔVth) in threshold voltage was −3.6 V. Moreover, as shown in FIG. 13, in the case where the carrier concentration in the oxide semiconductor was 1.0×1015/cm3 and the thickness of the oxide semiconductor layer was 30 nm, the amount of change (ΔVth) in threshold voltage was −0.2 V. The results show that a short-channel effect can be suppressed in a transistor including an oxide semiconductor by a reduction in thickness of an oxide semiconductor layer. For example, in the case where the channel length (L) is approximately 1 μm, even with an oxide semiconductor layer having sufficiently low carrier concentration, it can be understood that a short-channel effect can be sufficiently suppressed when the thickness of the oxide semiconductor layer is set to approximately 30 nm.
<Carrier Concentration>
A technical idea according to the disclosed invention is to make an oxide semiconductor layer as close as possible to an intrinsic (i-type) oxide semiconductor layer by sufficiently reducing the carrier concentration thereof. A method for calculating the carrier concentration and an actually measured carrier concentration will be described with reference to FIG. 14 and FIG. 15.
First, a method for calculating the carrier concentration is briefly explained. The carrier concentration can be calculated in such a manner that a MOS capacitor is manufactured and the results of C-V measurement (C-V characteristics) of the MOS capacitor are evaluated.
Specifically, carrier concentration Nd can be calculated in the following manner: C-V characteristics are obtained by plotting the relationship between the gate voltage VG and capacitance C of a MOS capacitor: a graph of the relationship between the gate voltage VG and (1/C)2 is obtained from the C-V characteristics; a differential value of (1/C)2 in a weak inversion region of the graph is found; and the differential value is substituted into Formula 1. Note that e, ε0, and ε in Formula 1 represent elementary electric charge, vacuum permittivity, and relative permittivity of an oxide semiconductor, respectively.




  
    
      
        
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Next, carrier concentration actually measured by the above method is described. A sample (a MOS capacitor) used for the measurement was formed as follows: a titanium film was formed to a thickness of 300 nm over a glass substrate; a titanium nitride film was formed to a thickness of 100 nm over the titanium film; an oxide semiconductor layer including an In—Ga—Zn—O-based oxide semiconductor was formed to a thickness of 2 μm over the titanium nitride film; and a silver film was formed to a thickness of 300 nm over the oxide semiconductor layer. Note that the oxide semiconductor layer was formed using a target for depositing an oxide semiconductor including In, Ga, and Zn (In:Ga:Zn=1:1:0.5 [atomic ratio]) by a sputtering method. Further, an atmosphere in which the oxide semiconductor layer was formed was a mixed atmosphere of argon and oxygen (with a flow ratio of Ar:O2=30 (sccm): 15 (sccm)).
FIG. 14 and FIG. 15 illustrate the C-V characteristics and the relationship between VG and (1/C)2, respectively. The carrier concentration calculated using Formula 1 from the differential value of (1/C)2 in a weak inversion region of the graph of FIG. 15 was 6.0×1010/cm3.
In this manner, by using an i-type or substantially i-type oxide semiconductor (for example, with a carrier concentration of less than 1×1012/cm3, preferably less than or equal to 1×1011/cm3), a transistor with excellent off-state current characteristics can be obtained.
The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in other embodiments.
Embodiment 2
In this embodiment, a modified example of the semiconductor device described in the above embodiment will be described with reference to FIGS. 16A and 16B.
FIGS. 16A and 16B are cross-sectional views each illustrating an example of a structure of a semiconductor device. The semiconductor device illustrated in FIG. 16A includes, in a lower portion, a transistor 160 including a material other than an oxide semiconductor, and in an upper portion, a transistor 162 including an oxide semiconductor. Note that the structure of the transistor 160 is similar to that of the transistor 160 described in the above embodiment. FIG. 16B illustrates an example where the connection relationship between the transistor 162 and an electrode (or a wiring) in the lower portion differs from that in FIG. 16A. The structure in FIG. 16A is mainly described below. Note that FIG. 16A shows a cross-sectional view of the transistor 160 provided in the lower portion along A1-A2 and a cross-sectional view of the transistor 162 provided in the upper portion along B1-B2, and FIG. 16B shows a cross-sectional view of the transistor 160 provided in the lower portion along A1-A2 and a cross-sectional view of the transistor 162 provided in the upper portion along C1-C2.
The transistor 162 includes an oxide semiconductor layer 140 provided over an insulating layer 138, a source or drain electrode 142a and a source or drain electrode 142b provided over the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, a gate insulating layer 146 provided so as to cover the oxide semiconductor layer 140, the source or drain electrode 142a, and the source or drain electrode 142b, and a gate electrode 148 provided over the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 140 (see FIG. 16A).
The source or drain electrodes 142a and 142b each have an oxide region 143, which is similar to the above embodiment. With the oxide region 143, it is possible to prevent short circuit between the gate electrode and the source or drain electrodes which may be caused by a reduction in thickness of the gate insulating layer or defective coverage therewith.
In addition, over the transistor 162, an interlayer insulating layer 150 and an interlayer insulating layer 152 are provided. Note that in this embodiment, the source or drain electrode 142a is directly connected to an electrode 136c. In other words, connection to another component is not achieved through a variety of electrodes (wirings) embedded in the interlayer insulating layer as in the above embodiment, and a conductive layer formed in a manner similar to that of the source or drain electrode 142a and the like is used as an electrode (wiring). For example, in FIG. 16A, an electrode 142c and an electrode 142d are provided in addition to the source or drain electrode 142a and the like. With such a structure, the step of patterning an insulating layer, the step of forming an embedded electrode, and the like can be omitted. Accordingly, the number of steps can be reduced and manufacturing cost can be reduced. The structure is effective particularly when the degree of miniaturization is not considerable.
The oxide semiconductor layer 140 is preferably an oxide semiconductor layer which is purified by sufficiently removing an impurity such as hydrogen therefrom. The aforementioned embodiment may be referred to for the details of the oxide semiconductor layer 140.
In this manner, the source or drain electrode 142a of the transistor 162 is electrically connected to another element (such as the transistor including a material other than an oxide semiconductor) through the electrode 130c and the electrode 136c (see FIG. 16A). Note that the structure of connection electrodes (such as the electrode 130c and the electrode 136c) is not limited to the above structure, and appropriate addition, omission, or the like is possible.
FIG. 16B illustrates the case where the connection relationship of the source or drain electrode 142a of the transistor 162 differs from that in FIG. 16A. Specifically, the source or drain electrode 142a is electrically connected to an electrode 110b through the electrode 130c and the electrode 136c. Here, the electrode 110b is formed in a manner similar to that of the gate electrode 110a. The electrode 110b may be a component of a transistor or may be part of a wiring or the like. Note that the structure of connection electrodes (such as the electrode 130c and the electrode 136c) is not limited to the above structure, and appropriate addition, omission, or the like is possible.
Although two examples of typical connection relationships are given above, an embodiment of the disclosed invention is not limited to these examples. For example, the structure illustrated in FIG. 16A and the structure illustrated in FIG. 16B may be combined. Furthermore, the gate electrode 110a of the transistor 160 and the source or drain electrode 142a of the transistor 162 may be electrically connected to each other.
Embodiment 3
In this embodiment, examples of electronic devices each including the semiconductor device according to any of the above-described embodiments will be described with reference to FIGS. 17A to 17F. The semiconductor device according to any of the above embodiments has unprecedented excellent characteristics. Therefore, an electronic device with a novel structure can be provided by using the semiconductor device. Note that the semiconductor device according to any of the above embodiments is integrated and mounted on a circuit board or the like, and incorporated in an electronic device.
FIG. 17A illustrates a notebook personal computer including the semiconductor device according to any of the above embodiments, and includes a main body 301, a housing 302, a display portion 303, a keyboard 304, and the like. By applying the semiconductor device according to the disclosed invention to a personal computer, a high-performance personal computer can be provided.
FIG. 17B illustrates a personal digital assistant (PDA) including the semiconductor device according to any of the above embodiments. A main body 311 is provided with a display portion 313, an external interface 315, operation buttons 314, and the like. Further, a stylus 312 is provided as an accessory for operation. By applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a high-performance personal digital assistant (PDA) can be provided.
FIG. 17C illustrates an electronic book 320 as an example of electronic paper including the semiconductor device according to any of the above embodiments. The electronic book 320 includes two housings, a housing 321 and a housing 323. The housing is combined with the housing 323 by a hinge 337, so that the electronic book 320 can be opened and closed using the hinge 337 as an axis. With such a structure, the electronic book can be used like a paper book.
The housing 321 includes a display portion 325, and the housing 323 includes a display portion 327. The display portion 325 and the display portion 327 can display a continuous image or different images. A structure for displaying different images enables text to be displayed on the right display portion (the display portion 325 in FIG. 17C) and images to be displayed on the left display portion (the display portion 327 in FIG. 17C).
FIG. 17C illustrates an example in which the housing 321 is provided with an operation portion and the like. For example, the housing 321 is provided with a power switch 331, operation keys 333, a speaker 335, and the like. The operation keys 333 allow pages to be turned. Note that a keyboard, a pointing device, or the like may also be provided on the same side of the housing as the display portion. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to an AC adapter and various cables such as a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. The electronic book 320 can also serve as an electronic dictionary.
In addition, the electronic book 320 can send and receive information wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.
Note that electronic paper can be used for electronic devices in all fields as long as they can display data. For example, to display data, electronic paper can be applied to posters, advertisement in vehicles such as trains, a variety of cards such as credit cards, and the like as well as electronic books. By applying the semiconductor device according to the disclosed invention to electronic paper, high-performance electronic paper can be provided.
FIG. 17D illustrates a cellular phone including the semiconductor device according to any of the above embodiments. The cellular phone includes two housings, a housing 340 and a housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, and the like. The housing 340 includes a solar cell 349 for charging the cellular phone, an external memory slot 350, and the like. An antenna is incorporated in the housing 341.
The display panel 342 has a touch panel function. A plurality of operation keys 345 displayed as images are indicated by dashed lines in FIG. 17D. Note that the cellular phone includes a booster circuit for increasing a voltage output from the solar cell 349 to a voltage needed for each circuit. It is possible for the cellular phone to have, in addition to the above structure, a structure in which a noncontact IC chip, a small recording device, or the like are formed.
The display panel 342 changes the orientation of display as appropriate in accordance with the application mode. Further, the camera lens 347 is provided on the same side as the display panel 342, so that the cellular phone can be used as a video phone. The speaker 343 and the microphone 344 can be used for videophone calls, recording, and playing sound, etc. as well as voice calls. Moreover, the housings 340 and 341 in a state where they are developed as illustrated in FIG. 17D can be slid so that one is lapped over the other. Therefore, the size of the cellular phone can be reduced, which makes the cellular phone suitable for being carried around.
The external connection terminal 348 can be connected to an AC adapter or a variety of cables such as a USB cable, so that the cellular phone can be charged or can perform data communication. Moreover, the cellular phone can store and transfer a larger amount of data by inserting a recording medium into the external memory slot 350. Further, in addition to the above functions, an infrared communication function, a television reception function, or the like may be provided. By applying the semiconductor device according to the disclosed invention to a cellular phone, a high-performance cellular phone can be provided.
FIG. 17E illustrates a digital camera including the semiconductor device according to any of the above embodiments. The digital camera includes a main body 361, a display portion A 367, an eyepiece 363, an operation switch 364, a display portion B 365, a battery 366, and the like. By applying the semiconductor device according to the disclosed invention to a digital camera, a high-performance digital camera can be provided.
FIG. 17F illustrates a television set including the semiconductor device according to any of the above embodiments. In a television set 370, a display portion 373 is incorporated in a housing 371. Images can be displayed on the display portion 373. Here, the housing 371 is supported by a stand 375.
The television set 370 can be operated with an operation switch included in the housing 371 or by a remote controller 380. Channels and volume can be controlled with a control key 379 included in the remote controller 380, and images displayed on the display portion 373 can thus be controlled. Further, the remote controller 380 can be provided with a display portion 377 for displaying data to be output from the remote controller 380.
Note that the television set 370 preferably includes a receiver, a modem, and the like. The receiver allows the television set 370 to receive a general television broadcast. In addition, the television set 370 is capable of one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver, between receivers, or the like) data communication when connected to a communication network by wired or wireless connection via the modem. By applying the semiconductor device according to the disclosed invention to a television set, a high-performance television set can be provided.
The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in other embodiments.
Example
In this example, oxidation of a conductive layer by high-density plasma treatment according to an embodiment of the disclosed invention is confirmed. The detailed description thereof is given below.
In this example, plasma was generated by excitation of a mixed gas of oxygen and argon at a power supply frequency of 2.45 GHz under a pressure of 500 Pa, and a conductive layer was treated using the plasma. The treatment was performed under three conditions where the lengths of treatment time were 1 minute (60 seconds), 3 minutes (180 seconds), and 10 minutes (600 seconds) to examine the relationship between treatment time and thickness of an oxide region.
Titanium films formed over glass substrates and aluminum films formed over glass substrates were separately prepared as conductive layers. Each of these films was subjected to the above plasma treatment at a substrate temperature of 300° C. or 325° C. In other words, the relationship between treatment time and thickness of an oxide region was examined under four conditions: the titanium film at a substrate temperature of 300° C. the titanium film at a substrate temperature of 325° C., the aluminum film at a substrate temperature of 300° C., and the aluminum film at a substrate temperature of 325° C.
Examination results are shown in FIG. 18. It can be seen from FIG. 18 that the oxidation rate of titanium is higher than that of aluminum. In addition, temperature dependence of the oxidation rate of titanium is large, whereas temperature dependence of the oxidation rate of aluminum is small. Furthermore, it can be said that the thickness of an oxide region of aluminum tends to be saturated in a short time.
Either of the materials can be provided with an oxide region with a thickness (5 nm or more) sufficient to suppress short circuit between a gate electrode and a source or drain electrode.
By performing oxidation treatment with high-density plasma as described in this example, damage to an oxide semiconductor layer can be reduced and localized states due to oxygen deficiency can be reduced, as compared to the case of performing oxidation treatment by normal plasma treatment. In other words, characteristics of an oxide semiconductor layer can be further improved.
In addition, by the above oxidation treatment, an oxide region is formed in part of a source or drain electrode (particularly, a portion corresponding to a side surface thereof); therefore, short circuit between the gate electrode and the source or drain electrode can be prevented.
It can be understood from the above description that an embodiment of the disclosed invention is highly effective in improving reliability and other characteristics of a transistor including an oxide semiconductor.
This application is based on Japanese Patent Application serial No. 2009-260392 filed with Japan Patent Office on Nov. 13, 2009, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
a first transistor including a silicon region, a first gate insulating layer over the silicon region, a first gate electrode over the first gate insulating layer;
a first insulating layer over the first gate electrode;
a second insulating layer over the first insulating layer;
a third insulating layer over the second insulating layer;
a second transistor including an oxide semiconductor layer over the third insulating layer, a second gate insulating layer over the oxide semiconductor layer, and a second gate electrode over the second gate insulating layer;
a fourth insulating layer over the second gate electrode;
a fifth insulating layer over the fourth insulating layer;
a first electrode passing through the first insulating layer and the second insulating layer, wherein the first electrode is electrically connected to the silicon region; and
a second electrode passing through the third insulating layer, the fourth insulating layer and the fifth insulating layer, wherein the second electrode is provided over the first electrode and is electrically connected to the first electrode.

2. The semiconductor device according to claim 1, wherein the third insulating layer is a base layer of the second transistor.

3. The semiconductor device according to claim 1, wherein the fourth insulating layer and the fifth insulating layer include silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.

4. The semiconductor device according to claim 1, wherein a channel formation region of the first transistor is not overlapped with the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistant, an electronic book, a phone, a camera, and a television set.

6. A semiconductor device comprising:
a first transistor including a silicon region, a first gate insulating layer over the silicon region, a first gate electrode over the first gate insulating layer;
a first insulating layer over the first gate electrode;
a second insulating layer over the first insulating layer;
a third insulating layer over the second insulating layer;
a second transistor including an oxide semiconductor layer over the third insulating layer, a second gate insulating layer over the oxide semiconductor layer, a second gate electrode over the second gate insulating layer, and a source electrode and a drain electrode overlapping the oxide semiconductor layer;
a fourth insulating layer over the second gate electrode;
a fifth insulating layer over the fourth insulating layer;
a first electrode passing through the first insulating layer and the second insulating layer, wherein the first electrode is electrically connected to the silicon region; and
a second electrode passing through the third insulating layer, the fourth insulating layer and the fifth insulating layer, wherein the second electrode is provided over the first electrode and is electrically connected to the first electrode.

7. The semiconductor device according to claim 6, wherein the third insulating layer is a base layer of the second transistor.

8. The semiconductor device according to claim 6, wherein the fourth insulating layer and the fifth insulating layer include silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.

9. The semiconductor device according to claim 6, wherein a channel formation region of the first transistor is not overlapped with the oxide semiconductor layer.

10. The semiconductor device according to claim 6, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistant, an electronic book, a phone, a camera, and a television set.