# Patent

## Title
Apparatus and methods for generalized state-dependent learning in spiking neuron networks

## Abstract

Generalized state-dependent learning framework in artificial neuron networks may be implemented. A framework may be used to describe plasticity updates of neuron connections based on connection state term and neuron state term. The state connections within the network may be updated based on inputs and outputs to/from neurons. The input connections of a neuron may be updated using connection traces comprising a time-history of inputs provided via the connections. Weights of the connections may be updated and connection state may be time varying. The updated weights may be determined using a rate of change of the trace and a term comprising a product of a per-neuron contribution and a per-connection contribution configured to account for the state time-dependency. Using event-dependent connection change components, connection updates may be executed on per neuron basis, as opposed to per-connection basis.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to a co-owned and co-pending U.S. patent application Ser. No. 13/487,533, entitled “STOCHASTIC SPIKING NETWORK LEARNING APPARATUS AND METHODS” filed Jun. 4, 2012, U.S. patent application Ser. No. 13/489,280 entitled “APPARATUS AND METHODS FOR REINFORCEMENT LEARNING IN ARTIFICIAL NEURAL NETWORKS”, filed Jun. 5, 2012, “U.S. patent application Ser. No. 13/487,499 entitled “STOCHASTIC APPARATUS AND METHODS FOR IMPLEMENTING GENERALIZED LEARNING RULES”, filed Jun. 4, 2012, U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, each of the foregoing incorporated herein by reference in its entirety.
COPYRIGHT
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND
1. Field of the Disclosure
The present disclosure relates to implementing learning in spiking neuron networks.
2. Description of Related Art
Spiking Neural Networks
Artificial spiking neural networks are frequently used to gain an understanding of biological neural networks, and for solving artificial intelligence problems. These networks typically employ a pulse-coded mechanism, which encodes information using timing of the pulses. Such pulses (also referred to as “spikes” or ‘impulses’) are short-lasting (typically on the order of 1-2 ms) discrete temporal events. Several exemplary embodiments of such encoding are described in a commonly owned and co-pending U.S. patent application Ser. No. 13/152,084 entitled APPARATUS AND METHODS FOR PULSE-CODE INVARIANT OBJECT RECOGNITION”, filed Jun. 2, 2011, [client reference BRAIN.001A] and U.S. patent application Ser. No. 13/152,119, Jun. 2, 2011, entitled “SENSORY INPUT PROCESSING APPARATUS AND METHODS”, [client reference BRAIN.003A] each incorporated herein by reference in its entirety.
A typical artificial spiking neural network, such as the network 100 shown for example in FIG. 1, may comprise a plurality of units (or nodes) 102, which correspond to neurons in a biological neural network. Any given unit 102 may receive input via connections 104, also referred to as communications channels, or synaptic connections. Any given unit 102 may be connected to other units via connections 112, also referred to as communications channels, or synaptic connections. The units (e.g., the units 106 in FIG. 1) providing inputs to any given unit via for example connections 104, are commonly referred to as the pre-synaptic units, while the unit receiving the inputs (e.g., the units 102 in FIG. 1) is referred to as the post-synaptic unit. Furthermore, the post-synaptic unit of one unit layer (e.g. the units 102 in FIG. 1) can act as the pre-synaptic unit for the subsequent upper layer of units (not shown).
Individual ones of the connections (104, 112 in FIG. 1) may be assigned, inter alia, a connection efficacy (which in general refers to a magnitude and/or probability of influence of pre-synaptic spike to firing of post-synaptic neuron, and may comprise, for example a parameter: synaptic weight, by which one or more state variables of post synaptic unit are changed). During operation of the pulse-code network (e.g., the network 100), synaptic weights may be typically adjusted using what is referred to as the spike-timing dependent plasticity (STDP) in order to implement, among other things, network learning.
One such adaptation mechanism is illustrated with respect to FIGS. 2-3. Traces 200, 210 in FIG. 2 depict pre-synaptic input spike train (delivered for example via connection 104_1 in FIG. 1) and post synaptic output spike train (generated, for example, by the neuron 102_1 in FIG. 1), respectively.
Properties of the connections 104 (such as weights w) may be adjusted based on relative timing between the pre-synaptic input (e.g., the pulses 202, 204, 206, 208 in FIG. 2) and post-synaptic output pulses (e.g., the pulses 214, 216, 218 in FIG. 2). One typical STDP weight adaptation rule is illustrated in FIG. 3, where rule 300 depicts synaptic weight change Δw as a function of time difference between the time of post-synaptic output generation and arrival of pre-synaptic input Δt=tpost−tpre. In some implementations, synaptic connections (e.g., the connections 104 in FIG. 1) delivering pre-synaptic input prior to the generation of post-synaptic response are potentiated (as indicated by Δw>0 associated with the curve 302), while synaptic connections (e.g., the connections 104 in FIG. 1) delivering pre-synaptic input subsequent to the generation of post-synaptic response are depressed (as indicated by Δw<0 associated with the curve 304 in FIG. 3). By way of illustration, when the post-synaptic pulse 208 in FIG. 2 is generated: (i) connection associated with the pre-synaptic input 214 may precede the output pulse (indicated by the line denoted 224) and it may be potentiated (Δw>0 in FIG. 3 and the weight is increased); and (ii) connections associated with the pre-synaptic input 216, 218 that follow may be depressed (Δw<0 in FIG. 3 and the weights are decreased).
Spiking Neuron Models
Generalized dynamics equations for spiking neurons models may be expressed as a superposition of input, interaction between the input current and the neuronal state variables, and neuron reset after the spike as follows:




  
    
      
        
          
            d
            
              q
              →
            
          
          
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            t
          
        
        =
        
          
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              (
              
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            ⁢
            
              
            
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        (
        
          Eqn
          .
          
            
          
          ⁢
          1
        
        )
      
    
  




where:

    
    
        {right arrow over (q)} is a vector of internal state variables (e.g., comprising membrane voltage);
        Iest is external input into neuron;
        V is the function that defines evolution of the state variables;
        G describes the interaction between the input current and the state variables (for example, to model postsynaptic potentials); and
        R describes resetting the state variables after the output spikes at tout.
    
    


For example, for IF model the state vector and the state model may be expressed as:

{right arrow over (q)}(t)≡u(t);V({right arrow over (q)})=−Cu;R({right arrow over (q)})=ures;G({right arrow over (q)})=1,  (Eqn. 2)

where C is a membrane constant, ures is a value to which voltage is set after output spike (reset value). Accordingly, Eqn. 1 may become:





  
    
      
        
          
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For a simple neuron model, Eqn. 1 may be expressed as:




  
    
      
        
          
            
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and a,b,c,d are parameters of the model.

Some algorithms for spike-time learning (especially, reinforcement learning) in spiking neural networks may be represented using the following general equation described, for example, in co-pending and co-owned U.S. patent application Ser. No. 13/487,499 entitled “STOCHASTIC APPARATUS AND METHODS FOR IMPLEMENTING GENERALIZED LEARNING RULES”, incorporated supra:




  
    
      
        
          
            d
            
              
                θ
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              ⁡
              
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                t
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          6
        
        )
      
    
  




where:

    
    
        θi(t) is an adaptation (learning) parameter of a synaptic connection between the pre-synaptic neuron i and the post-synaptic neuron j;
        η is a parameter referred to as the learning rate, η can be a constant parameter or it can be a function of some other system parameters;
        F(t) is a performance function; and
        ei(t) is eligibility trace, configured to characterize relations between pre-synaptic and post-synaptic activity.
    
    


An exemplary eligibility trace may comprise a temporary record of the occurrence of an event, such as visiting of a state or the taking of an action, or a receipt of pre-synaptic input. The trace marks the parameters associated with the event (e.g., the synaptic connection, pre- and post-synaptic neuron IDs) as eligible for undergoing learning changes. In one approach, when a reward signal occurs, only eligible states or actions may be ‘assigned credit’ or ‘blamed’ for the error. Thus, the eligibility traces aid in bridging the gap between the events and the training information.
Various implementations of eligibility traces exist for different types of learning (e.g., supervised, unsupervised, reinforcement) for deterministic and stochastic neurons. However, existing implementations do not appear to provide a common framework thereby requiring reformulating, learning rules (e.g., for determining the eligibility traces) for each implementation.
Accordingly, there is a salient need for a more efficient method and apparatus for implementing state-dependent learning comprising in spiking neural network comprising a generalized (canonic) form of eligibility traces that may allow common implementation of the updates.
SUMMARY
The present disclosure satisfies the foregoing needs by facilitating, inter alia, implementing generalized probabilistic learning configured to handle simultaneously various learning rule combinations.
One aspect of the disclosure relates to a system, apparatus, method, and/or computer-readable storage medium associated with implementing an update for a computerized spiking neuron capable of producing an outcome consistent with (i) an input spiking signal, and (ii) a learning task. The system may comprise one or more processors configured to execute computer program modules. Executing the computer program modules may cause the one or more processors to determine a present value of an eligibility trace. The eligibility trace may comprise a time history of one or more spikes of the input spiking signal. The time history may include information associated with individual ones of the one or more spikes occurring at a time period prior to the present time. Executing the computer program modules may cause the one or more processors to determine a rate of change of the eligibility trace at the present time based on one or both of (i) the present value of the eligibility trace or (ii) a product of a neuron portion and connection portion. Executing the computer program modules may cause the one or more processors to effectuate the update based on the rate of change of the eligibility trace. The neuron portion may be characterized by a present neuron state. The update may be configured to transition the present neuron state towards a target state. The target state may be associated with producing the outcome.
In some implementations, the input spike signal may be provided to the neuron via a plurality of connections. The connection portion may be configured to characterize a state of individual ones of the plurality of connections independently from one another. The neuron portion may be configured to characterize the neuron state for individual ones of the plurality of connections substantially simultaneously to one another.
In some implementations, individual ones of the plurality of connections may be characterized by individual ones of a plurality of synaptic weights. The update may comprise modifying individual ones of the plurality of synaptic weights based on updated eligibility trace.
In some implementations, the updated eligibility trace may be determined via an integration of the rate of change with respect to time.
In some implementations, the adjustment of individual ones of the weights may be determined based on a product of the rate of change and an additional signal. The additional signal may be time dependent and configured to affect individual ones of the plurality of connections. The rate of change for at least one of the weights may be configured to be determined independently from other of the weights.
In some implementations, the additional signal may comprise a reinforcement signal conveying information associated with at least one reinforcement spike. The reinforcement signal may be configured based on the present neuron state and the target state.
In some implementations, the update may be based on an event being one or more of: (i) generation of the outcome comprising at least on spike; (ii) occurrence of the one or more spikes; (iii) a timer event indicative of an expiration of current update time period; or (iv) the at least one reinforcement spike.
In some implementations, the reinforcement signal may be configured based on a distance measure between the neuron output and a target output. The target output may be associated with the target state.
In some implementations, the distance measure may include one or more of: (i) mean squared error, (ii) weighed error; or (iii) squared error of the convolved signals the reward signal is configured based on a distance measure between the present neuron state and the target state.
In some implementations, the reinforcement signal may be configured to provide one or both of: (1) a positive reward when a distance measure between the current state and the desired state is smaller compared to the distance measure between the prior state and the desired state or (2) a negative reward when the distance measure between the current state and the desired state is greater compared to the distance measure between the prior state and the desired state.
In some implementations, the additional signal may comprise one or both of (1) a performance measure determined based on a present performance associated with the present state, or (2) a target performance associated with the target state. The present performance may be based on a present value of the learning parameter.
In some implementations, the outcome may be characterized by a spike-free time period subsequent occurrence of the least one reinforcement spike.
In some implementations, the reinforcement signal may comprise a negative reward determined based on the present performance being outside a predetermined measure from the target performance.
In some implementations, the state parameter may be configured to characterize time evolution of the neuron state. The realization of the trace may comprise an analytic solution of the time derivative representation. The construct of the time derivative representation may facilitate attaining the integration via symbolic integration operation.
In some implementations, the neuron may be configured to operate in accordance with a dynamic process configured to be updated at time intervals. The time period may comprise a plurality of the time intervals.
In some implementations, the update may comprise a synaptic update of first and second connections capable of providing the spiking input. The connection portion may comprise a first part configured to characterize the first connection and a second part configured to characterize the second connection. The synaptic update may comprise a connection weight update of the first and the second connections. The weight update may be configured based on the eligibility trace.
In some implementations, the weight update may be configured based on a product of the eligibility trace and a reinforcement signal comprising at least one reinforcement spike. The reinforcement signal may be configured based on the present neuron state and the target state.
In some implementations, the spiking input may be provided during a stimulus interval. The synaptic update may comprise a plasticity rule configured to modify a magnitude of the first connection weight and the second connection weight. The modifying of the magnitude may have a time window associated therewith. The plasticity rule may be configured to adjust one or both of: (1) a start point of the window or (2) an end point of the window.
In some implementations, the spiking input may be provided during an stimulus interval. The synaptic update may comprise a plasticity rule configured to modify magnitude of the first and connection weight and the second connection weight. The plasticity rule may be characterized by a portion having a time scale configured substantially comparable to the stimulus interval.
In some implementations, the plasticity rule may be characterized by another portion configured to exceed the stimulus interval by at least 10 times.
In some implementations, the outcome may comprise at least one spike generated by the neuron based on the input spiking signal.
Another aspect of the disclosure relates to a system, apparatus, method, and/or computer-readable storage medium associated with learning in a computerized spiking neuron. The method may include operating the neuron in accordance with a learning process configured to be updated at one or more time intervals. The update may include retrieving prior values of first and second traces associated, respectively, with first and second connections that are capable of providing spiking input into the neuron. The update may include determining a rate of change of: (i) the first trace based on (1) the prior value of the first trace and (2) a product of a neuron portion and a first connection portion; and (ii) the second trace based on (1) the prior value of the second trace and (2) a product of the neuron portion and second connection portion. The update may include determining an updated value of the first and second traces based on the respective rate of change. The prior values of the first and the second traces may be associated with another update preceding the update. The first connection portion and the second connection portion may be based on one or more spikes of the spiking input being provided, respectively, via the first and the second connections. The one or more spikes may occur within a time interval between the other update and the update. The learning process may be configured to cause the neuron to generate an output in accordance with the spiking input. The output may be characterized by a performance measure configured such that the update is capable of reducing the measure.
Yet another aspect of the disclosure relates to a system, apparatus, method, and/or computer-readable storage medium associated with operating a plurality of data interfaces in a computerized network comprising at least a node. The method may include storing a time record of one or more data items capable of being provided to the node via the plurality of data interfaces. The time history may include information associated with individual ones of the one or more spikes occurring at an interval prior to the present time. The method may include determining a value of a plurality of eligibility traces, based on the time record. The method may include determining a rate of change of a respective trace of the plurality of eligibility traces, based on one or both of: (i) the present value of the plurality of eligibility traces or (ii) a product of a node component and a plurality of interface components. The method may include effectuating the update based on the rate of change.
In some implementations, the respective trace of the plurality of eligibility traces may be associated with a respective interface of the plurality of interfaces. Individual ones of the plurality of interface components may be configured to characterize the respective trace. The node component may be configured based on a node state. The node state may be common to the plurality of interfaces. The update may be configured to transition the present state towards a target state. The target state may be associated with the node to generate an output consistent the one more data items.
These and other objects, features, and characteristics of the present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the disclosure. As used in the specification and in the claims, the singular form of “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram depicting artificial spiking neural network according to the prior art.
FIG. 2 is a graphical illustration depicting spike timing in the spiking network of FIG. 1, according to the prior art.
FIG. 3 is a plot depicting spike time dependent plasticity spike timing in the spiking network of FIG. 1, according to the prior art.
FIG. 4 is a block diagram illustrating spiking neural network configured to effectuate multiple learning rules, in accordance with one or more implementations.
FIG. 5 is a logical flow diagram illustrating generalized update method, for use with network connections of FIG. 4, in accordance with one or more implementations.
FIG. 6 is a logical flow diagram illustrating network configuration for implementing efficient update method, for use with network connections of FIG. 4, in accordance with one or more implementations.
FIG. 7 is a logical flow diagram illustrating efficient update method, comprising time-dependent neuron dynamics, for use with neural network of FIG. 4, in accordance with one or more implementations.
FIGS. 8A-8C are a program listing illustrating high level neuromorphic description of spiking neuron dynamics and stochastic properties configured for processing by a neuromorphic processing logic engine in order to implement synaptic updates, in accordance with one or more implementations.
FIG. 9 is a logical flow diagram illustrating reinforcement modulated STDP update, for use with neural network of FIG. 4, in accordance with one or more implementations.
FIG. 10 is a block diagram illustrating sensory processing apparatus configured to implement efficient connection plasticity update mechanism in accordance with one or more implementations.
FIG. 11A is a block diagram illustrating computerized system useful for efficient connection plasticity update mechanism in a spiking network, in accordance with one or more implementations.
FIG. 11B is a block diagram illustrating a neuromorphic computerized system useful with efficient connection plasticity update mechanism in a spiking network, in accordance with one or more implementations.
FIG. 11C is a block diagram illustrating a hierarchical neuromorphic computerized system architecture useful with efficient connection plasticity update mechanism in a spiking network, in accordance with one or more implementations.
FIG. 11D is a block diagram illustrating cell-type neuromorphic computerized system architecture useful with efficient connection plasticity update mechanism in a spiking network, in accordance with one or more implementations.



All Figures disclosed herein are © Copyright 2012 Brain Corporation. All rights reserved.
DETAILED DESCRIPTION
Exemplary implementations of the present disclosure will now be described in detail with reference to the drawings, which are provided as illustrative examples so as to enable those skilled in the art to practice the disclosure. Notably, the figures and examples below are not meant to limit the scope of the present disclosure to a single implementation, but other implementations are possible by way of interchange of or combination with some or all of the described or illustrated elements. Wherever convenient, the same reference numbers will be used throughout the drawings to refer to same or similar parts.
Where certain elements of these implementations can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the disclosure.
In the present specification, an implementation showing a singular component should not be considered limiting; rather, the disclosure is intended to encompass other implementations including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein.
Further, the present disclosure encompasses present and future known equivalents to the components referred to herein by way of illustration.
As used herein, the term “bus” may be meant generally to denote all types of interconnection or communication architecture that may be used to access the synaptic and neuron memory. The “bus” may be optical, wireless, infrared, and/or another type of communication medium. The exact topology of the bus could be for example standard “bus”, hierarchical bus, network-on-chip, address-event-representation (AER) connection, and/or other type of communication topology used for accessing, e.g., different memories in pulse-based system.
As used herein, the terms “computer”, “computing device”, and “computerized device” may include one or more of personal computers (PCs) and/or minicomputers (e.g., desktop, laptop, and/or other PCs), mainframe computers, workstations, servers, personal digital assistants (PDAs), handheld computers, embedded computers, programmable logic devices, personal communicators, tablet computers, portable navigation aids, J2ME equipped devices, cellular telephones, smart phones, personal integrated communication and/or entertainment devices, and/or any other device capable of executing a set of instructions and processing an incoming data signal.
As used herein, the term “computer program” or “software” may include any sequence of human and/or machine cognizable steps which perform a function. Such program may be rendered in a programming language and/or environment including one or more of C/C++, C#, Fortran, COBOL, MATLABTM, PASCAL, Python, assembly language, markup languages (e.g., HTML, SGML, XML, VoXML), object-oriented environments (e.g., Common Object Request Broker Architecture (CORBA)), JavaTM (e.g., J2ME, Java Beans), Binary Runtime Environment (e.g., BREW), and/or other programming languages and/or environments.
As used herein, the terms “connection”, “link”, “transmission channel”, “delay line”, “wireless” may include a causal link between any two or more entities (whether physical or logical/virtual), which may enable information exchange between the entities.
As used herein, the term “memory” may include an integrated circuit and/or other storage device adapted for storing digital data. By way of non-limiting example, memory may include one or more of ROM, PROM, EEPROM, DRAM, Mobile DRAM, SDRAM, DDR/2 SDRAM, EDO/FPMS, RLDRAM, SRAM, “flash” memory (e.g., NAND/NOR), memristor memory, PSRAM, and/or other types of memory.
As used herein, the terms “integrated circuit”, “chip”, and “IC” may be meant to refer to an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. By way of non-limiting example, integrated circuits may include field programmable gate arrays (e.g., FPGAs), a programmable logic device (PLD), reconfigurable computer fabrics (RCFs), application-specific integrated circuits (ASICs), and/or other types of integrated circuits.
As used herein, the terms “microprocessor” and “digital processor” may be meant generally to include digital processing devices. By way of non-limiting example, digital processing devices may include one or more of digital signal processors (DSPs), reduced instruction set computers (RISC), general-purpose (CISC) processors, microprocessors, gate arrays (e.g., field programmable gate arrays (FPGAs)), PLDs, reconfigurable computer fabrics (RCFs), array processors, secure microprocessors, application-specific integrated circuits (ASICs), and/or other digital processing devices. Such digital processors may be contained on a single unitary IC die, or distributed across multiple components.
As used herein, the term “network interface” refers to any signal, data, and/or software interface with a component, network, and/or process. By way of non-limiting example, a network interface may include one or more of FireWire (e.g., FW400, FW800, etc.), USB (e.g., USB2), Ethernet (e.g., 10/100, 10/100/1000 (Gigabit Ethernet), 10-Gig-E, etc.), MoCA, Coaxsys (e.g., TVnetTM), radio frequency tuner (e.g., in-band or OOB, cable modem, etc.), Wi-Fi (802.11), WiMAX (802.16), PAN (e.g., 802.15), cellular (e.g., 3G, LTE/LTE-A/TD-LTE, GSM, etc.), IrDA families, and/or other network interfaces.
As used herein, the terms “node”, “neuron”, and “neuronal node” may be meant to refer, without limitation, to a network unit (e.g., a spiking neuron and a set of synapses configured to provide input signals to the neuron) having parameters that are subject to adaptation in accordance with a model.
As used herein, the terms “state” and “node state” may be meant generally to denote a full (or partial) set of dynamic variables used to describe node state.
As used herein, the term “synaptic channel”, “connection”, “link”, “transmission channel”, “delay line”, and “communications channel” include a link between any two or more entities (whether physical (wired or wireless), or logical/virtual) which enables information exchange between the entities, and may be characterized by a one or more variables affecting the information exchange.
As used herein, the term “Wi-Fi” may include one or more of IEEE-Std. 802.11, variants of IEEE-Std. 802.11, standards related to IEEE-Std. 802.11 (e.g., 802.11a/b/g/n/s/v), and/or other wireless standards.
As used herein, the term “wireless” means any wireless signal, data, communication, and/or other wireless interface. By way of non-limiting example, a wireless interface may include one or more of Wi-Fi, Bluetooth, 3G (3GPP/3GPP2), HSDPA/HSUPA, TDMA, CDMA (e.g., IS-95A, WCDMA, etc.), FHSS, DSSS, GSM, PAN/802.15, WiMAX (802.16), 802.20, narrowband/FDMA, OFDM, PCS/DCS, LTE/LTE-A/TD-LTE, analog cellular, CDPD, satellite systems, millimeter wave or microwave systems, acoustic, infrared (i.e., IrDA), and/or other wireless interfaces.
Overview
The present disclosure provides, among other things, a computerized apparatus and methods for facilitating state-dependent learning in spiking neuron networks by, inter alia, implementing generalized framework for plasticity updates. In one or more implementations, network updates may comprise modification of learning parameter of the network. In some implementations, the learning parameter may comprise synaptic efficacy. In some implementations, the updates may comprise plasticity rules effectuated using eligibility traces. In some implementations, the trace may comprise a temporary record of the occurrence of one or more events, such as visiting of a state, and/or the taking of an action (e.g., post-synaptic response), and/or a receipt of pre-synaptic input. The trace marks the parameters associated with the event (e.g., the synaptic connection, pre- and post-synaptic neuron IDs) as eligible for undergoing learning changes.
In some implementations, plasticity rule eligibility traces may be determined based on a rate of change of the trace at the update time. In one or more implementations plasticity rule eligibility traces may be determined based integrating the rate of change.
In one or more implementations, the plasticity update may comprise learning parameter update of a plurality of connections of a neuron. In one or more implementations, the plurality of connections may provide pre-synaptic input into the neuron.
In some implementations, the learning parameters associated with the plurality of connections may be updated concurrently with one another. In some implementations, modification of the plurality of learning parameters may be effectuated based on a product of a per-connection term and a per-neuron term. The per-connection term may be capable of characterizing dynamic process associated with individual connections and may be specific to that connection. The per-neuron may be capable of characterizing dynamics of the neuron and be common to all connections within the same neuron.
In accordance with the principles of the disclosure, multiple synaptic updates may be configured to be executed on per neuron basis, as opposed to per-synapse basis of prior art. The cumulative synaptic plasticity update in accordance with some implementations may be factored (decomposed) into multiple event-dependent connection change (EDCC) components, as described in detail, for example, in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra. The EDCC components may be configured to describe synapse plasticity change due to neuronal input spike (i.e., the spike transmitted by a synapse from a pre-synaptic neuron into a post-synaptic neuron) occurring at time ti≦tupdate. In order to effectuate factoring of the synaptic updates, at individual ones of the update instances tupdate (e.g., cyclic and/or on-demand), two or more EDCC components may be computed, with individual components corresponding to one prior network state update time interval ti. The number of EDCC components computed may be configured based on (i) the plasticity rule decay time scale used by the network, and (ii) the network update interval t. By way of illustration, if the plasticity decay time-scale T is 20 ms and the network state may be updated at 1 ms intervals, then at individual ones of the synaptic update events at time t, a number nT=T/t of EDCC components (nT=20 in one or more implementations) is computed, with individual components corresponding to the plasticity change due to input (pre-synaptic) spike occurring at time ti=t−(i−1)×t, i={1, . . . nT}. It is noteworthy, that the nT EDCC components may be computed once for all synapses associated with the neuron, and the occurrence times of input spikes within the time interval (t−T) prior to updates may be used to reference appropriate EDCC component.
In some implementations, the generalized plasticity update framework of the disclosure may be used to implement modulated STDP eligibility traces useful, for example in reinforcement learning tasks such as adaptive control of a garbage collecting robot and/or search and rescue robot.
In some implementations, the generalized plasticity update framework of the disclosure may be used to implement state-dependent eligibility traces for a stochastic neuron configured in accordance with a spike-response process (SRP). Such realization may be useful, for example, in: (i) supervised applications such as learning used for spike pattern recognition; (ii) unsupervised learning, such as, maximization of information transmission, and/or other applications; and (iii) reinforcement learning applications, that may include stabilization of a robotic hand and/or other applications.
In some implementations, the generalized plasticity update framework of the disclosure may be used to implement STDP mechanisms (that are inspired by studies cerebellum). Cerebellum-type (CB) plasticity may comprise a long-term depression (LTD) mechanism configured based on the timing of the pre-synaptic input and of an auxiliary signal spike timing. The CB plasticity may comprise a non-associative long-term potentiation (LTP) may only depend on input spike timing. By way of illustration, the CB plasticity may be used in removing delays when controlling multi-joint robotic manipulator arms.
Spiking Neuron Network
Detailed descriptions of the various implementation of apparatus and methods of the disclosure are now provided. Although certain aspects of the disclosure can best be understood in the context of robotic adaptive control system comprising a spiking neural network, the disclosure is not so limited. Implementations of the disclosure may also be used for implementing a variety of learning systems, such as, for example, sensory signal processing (e.g., computer vision), signal prediction (e.g., supervised learning), finance applications, data clustering (e.g., unsupervised learning), inventory control, data mining, and/or other applications that do not require performance function derivative computations.
Implementations of the disclosure may be, for example, deployed in a hardware and/or software implementation of a neuromorphic computer system. In some implementations, a robotic system may include a processor embodied in an application specific integrated circuit, which can be adapted or configured for use in an embedded application (e.g., a prosthetic device).
Referring now to FIG. 4, one implementation of spiking network apparatus for effectuating the generalized learning framework of the disclosure is shown and described in detail. The network 400 may comprise at least one stochastic spiking neuron 430, operable according to, for example, a Spike Response Process (SRP), and configured to receive M-dimensional input spiking stream X(t) 402 via M-input connections 414. In some implementations, the M-dimensional spike stream may correspond to M-input synaptic connections into the neuron 430. As shown in FIG. 4, individual input connections may be characterized by a connection parameter 412 wij that may be configured to be adjusted during learning. In one or more implementation, the connection parameter may comprise connection efficacy (e.g., weight). In some implementations, the parameter 412 may comprise synaptic delay. In some implementations, the parameter 412 may comprise probabilities of synaptic transmission.
The following signal notation may be used in describing operation of the network 400, below:

    
    
        y(t)=Σkδ(t−tkout) denotes the output spike pattern, corresponding to the output signal 408 produced by the control block 410, where tk denotes the times of the output spikes generated by the neuron; and
        yd(t)=Σtkδ(t−tkd) denotes the teaching spike pattern, corresponding to the desired (or reference) signal that is part of external signal 404 of FIG. 4, where tk denotes the times when the spikes of the reference signal may be received by the neuron.
    
    


In some implementations, the neuron 430 may be configured to receive training inputs, comprising the desired output (reference signal) yd(t) via the connection 404. In some implementations, the neuron 430 may be configured to receive positive and negative reinforcement signals via the connection 404. Accordingly, parameters r+, r− in of FIG. 4 denotes the reinforcement signal spike stream, that may be expressed as:

r+(t)=Σiδ(t−ti+),r−(t)=Σiδ(t−ti−),

where ti+,ti− denote the spike times associated, for example, with positive and negative reinforcement, respectively.

The neuron 430 may be configured to implement the control block 410 which may be configured to control, for example, a robotic arm and may be parameterized by the weights of connections between artificial neurons, and a learning block 420, which may implement learning and/or calculating the changes in the connection weights. The control block 410 may receive an input signal x, and may generate an output signal y. The output signal y may include motor control commands configured to move a robotic arm along a desired trajectory. The control block 410 may be characterized by a system model comprising system internal state variables q. The internal state variable q may include a membrane voltage of the neuron, conductance of the membrane, and/or other variables. The control block 410 may be characterized by learning parameters w, which may include synaptic weights of the connections, firing threshold, resting potential of the neuron, and/or other parameters. In one or more implementations, the parameters w may comprise probabilities of signal transmission between the units (e.g., neurons) of the network.
The input signal x(t) may comprise data used for solving a particular control task. In one or more implementations, such as those involving a robotic arm or autonomous robot, the signal x(t) may comprise a stream of raw sensor data (e.g., proximity, inertial, and/or terrain imaging) and/or preprocessed data (e.g., velocity, extracted from accelerometers, distance to obstacle, and/or positions). In some implementations, such as those involving object recognition, the signal x(t) may comprise an array of pixel values (e.g., RGB, CMYK, HSV, HSL, and/or grayscale) in the input image, or preprocessed data (e.g., levels of activations of Gabor filters for face recognition, contours, and/or other preprocessed data). In one or more implementations, the input signal x(t) may comprise desired motion trajectory, for example, in order to predict future state of the robot on the basis of current state and desired motion.
The control block 410 of FIG. 4 may comprise a probabilistic dynamic system, which may be characterized by an analytical input-output (x→y) probabilistic relationship having a conditional probability distribution associated therewith:

P=p(y|x,w)  (Eqn. 7)

In Eqn. 7, parameter w may denote various system parameters including connection efficacy, firing threshold, resting potential of the neuron, and/or other parameters. The analytical relationship of Eqn. 7 may be selected such that the gradient of ln [p(y|x,w)] with respect to the system parameter w exists and can be calculated. The neuronal network shown in FIG. 4 may be configured to estimate rules for changing the system parameters (e.g., learning rules) so that the performance function F(x,y,r) may be minimized (or maximized) for the current set of inputs and outputs and system dynamics.

In some implementations, the control performance function may be configured to reflect the properties of inputs and outputs (x,y). The values F(x,y,r) may be calculated directly by the learning block 420 without relying on external signal r when providing solution of unsupervised learning tasks.
In some implementations, the value of the function F may be calculated based on a difference between the output y of the control block 410 and a reference signal yd characterizing the desired control block output. This configuration may provide solutions for supervised learning tasks, as described in detail below.
In some implementations, the value of the performance function F may be determined based on the external signal r. This configuration may provide solutions for reinforcement learning tasks, where r represents reward and punishment signals from the environment.
The learning block 420 may comprise learning framework according to the implementation described in co-pending and co-owned owned U.S. patent application Ser. No. 13/487,533, entitled “STOCHASTIC SPIKING NETWORK LEARNING APPARATUS AND METHODS” filed Jun. 4, 2012, that enables generalized learning methods without relying on calculations of the performance function F derivative in order to solve unsupervised, supervised and/or reinforcement learning tasks. The block 420 may receive the input x and output y signals (denoted by the arrow 402_1, 408_1, respectively, in FIG. 2), as well as the state information q 405. In some implementations, such as those involving supervised and reinforcement learning, external teaching signal r may be provided to the block 420 as indicated by the arrow 404 in FIG. 4. The teaching signal may comprise, in some implementations, the desired motion trajectory, and/or reward and punishment signals from the external environment.
In one or more implementations the learning block 420 may optimize performance of the control system (e.g., the network 400 of FIG. 4) that may be characterized by minimization of the average value of the performance function F(x,y,r) as described in detail below.
Optimization of performance of the control system (e.g., the network 430 of FIG. 4) may, in some implementations, be achieved via maximization of the average of the performance function, as described in detail for example, in a co-owned and co-pending U.S. patent application Ser. No. 13/487,499 entitled “STOCHASTIC APPARATUS AND METHODS FOR IMPLEMENTING GENERALIZED LEARNING RULES, incorporated supra.
In one or more implementations, instantaneous probability density of the neuron producing a response may be determined using neuron membrane voltage u(t) for continuous time chosen as an exponential stochastic threshold:

λ(t)=λ0eκ(u(t)−θ)  (Eqn. 8)

where:

    
    
        u(t) is the membrane voltage of the neuron,
        θ is the voltage threshold for generating a spike,
        κ is the probabilistic parameter, and
        λ0 is the basic (spontaneous) firing rate of the neuron.
    
    


For discrete time steps, an approximation for the probability Λ(u(t))ε(0,1] of firing in the current time step may be given by:

Λ(u(t))=1−e−λ(u(t))Δt  (Eqn. 9)

where Δt is time step length.

In some implementations, a score function




  
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may be utilized in order to determine changes for individual spiking neuron parameters. If spiking patterns may be viewed on finite interval length T as an input x and output y of the neuron, then the score function may take the following form:





  
    
      
        
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where time moments ti belong to neuron's output pattern yT (neuron generates spike at these time moments). If an output of the neuron at individual time moments is considered (e.g., whether there is an output spike or not), then an instantaneous value of the score function may be calculated using a time derivative of the interval score function:





  
    
      
        
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where t1 is the time of output spike, and δd(t) is the Kronecker delta.

In one or more implementations, the score function values for the stochastic Integrate-and-Fire neuron discrete time may be determined as follows:




  
    
      
        
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where:

    
    
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State variables q (e.g., probability of firing λ(t)) associated with the control model may be provided to the learning block 420 via the pathway 405. The learning block 420 of the neuron 430 may receive the output spike train y(t) via the pathway 408_1.

    
    


In one or more implementations, the input interfaces (i.e., the connections 414 of the network 400 of FIG. 4) may be operated according a linear dynamic process that may be expressed as:




  
    
      
        
          
            
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where Q(t), Si(t) denote neuron-specific and connection specific portions of the plasticity adjustment rule, respectively.

In one or more implementations, connection dynamic process may be described using stable dynamic equations (e.g., Eqn. 13, Eqn. 14) so that their respective solutions Si(t), ei(t) decay exponentially with time. Accordingly, such dynamic process, comprise exponentially decaying effects (‘memory’) of external influences (the right-hand side terms parts of Eqn. 13 and Eqn. 14 describing the input spikes and the term Q(t) Si(t), respectively) that may produce substantially diminished effects of external influences (e.g., spikes) on the synapse dynamics when these events occur sufficiently far in the past. The exponential decay thus allows characterization of synapse dynamics that may be based on inputs occurring within the time interval (t−T), where T is determined based on the dynamics of the system (i.e., the matrix A in Eqn. 13 the time scale τ in Eqn. 14). By way of example, the time interval T may be configured equal to τ in one or more implementations, while in some implementations T may be determined as T=1/λmax, where λmax is maximum real part of the eigenvalues the matrix A in Eqn. 13.
It is noteworthy that as Eqn. 13 and Eqn. 14 comprise linear differential equations, the superposition principle may be applied in order to obtain solutions Si(t) and ei(t), in one or more implementations. Specifically, the right-hand sides of Eqn. 13 may be decomposed into plurality of event-dependent connection change basis vectors bm(t), and the right-hand sides of Eqn. 14 may be decomposed into plurality of event-dependent connection change (EDCC) components Mt), as described, for example in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra. Accordingly, using the superposition, the state response Si(t) of the ith connection to an input spike sin(tm) within the interval (t−T) of the input spike train Σjδ(t−tjin) may be determined as a linear combination of contributions of individual basis vectors associated with individual mth spikes within the input spike train sin(tm). Similarly, the eligibility trace ei(t) of the ith connection may be determined as a linear combination of contributions of individual EDCC components ym(t) associated with individual mth spikes within the input spike train sin(tm). In one implementation, the superposition may be effectuated using weighted linear combination, as described, for example, in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra. In some implementations, the EDCC components may be pre-computed (once per neuron) and linearly combined in order to determine solutions of Eqn. 13, Eqn. 14 (e.g., Si(t) and ei(t)) at the time of the update t for individual ones of the connections 414. In some implementations, the event-dependent connection change (EDCC) may comprise eligibility trace configured for adapting connection weights (e.g., synaptic weights).
Furthermore, in some implementations, the neuronal dynamic process (e.g., Eqn. 13 and Eqn. 14) may comprise non-stationary the matrix A and/or Q. Provided that the process is stable (i.e., the solution of Eqn. 13 and Eqn. 14 decays with time), these solutions at time tup may be obtained by evaluating the process state over the (tup−T) time interval. It is noteworthy that because of stability of equations, solution of homogeneous equations (where right-hand side is zero) decays to zero. A sufficiently large time interval T, compared to the time decay scale of Eqn. 13, Eqn. 14, may correspond, in some implementations, to zero initial conditions of Eqn. 13 and Eqn. 14.
It will be appreciated by those skilled in the arts that neural network dynamics represented by Eqn. 13 and Eqn. 14 may comprise one implementation and the framework of the innovation is not so limited and may be utilized with any network synaptic dynamics that may be described using linear and stable process so that superposition principle may be used.
Modulated STDP
In one or more implementations, the EDCC components may comprise one or more eligibility trace configured for implementing synaptic plasticity, such as, for example, adapting weights of synaptic connections. In one such implementation described in detail in U.S. Pat. No. 8,103,602, entitled “SOLVING THE DISTAL REWARD PROBLEM THROUGH LINKAGE OF STDP AND DOPAMINE SIGNALING” filed Dec. 21, 2007, the plasticity mechanism, useful with the efficient update methodology of the present disclosure, may comprise STDP that is modulated by an additional parameter. In some implementations, the parameter may be configured as specific to individual neurons. In one or more implementations, the parameter may be configured network-wide, such as for example, when simulating reward actions of biological neurotransmitter dopamine.
In some implementations of the modulated STDP process (e.g., Eqn. 13, Eqn. 14) may be expressed using the following framework:

    
    
        a one dimensional synapse state vector {right arrow over (S)}i(t)=Si(t);
        synaptic coefficient vector ki=1;
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        ,
        
          t
          out
        
      
      )
    
  
  =
  
    1
    
      τ
      s
    
  




that does not depend on input and/or output activity and is time invariant, where τs is STDP time constant (typically 30-100 ms);

    
    
        synapse reset condition after post-synaptic spike Rs(t)=−Si(t);
    
    






  
    
      
        
          Q
          ⁡
          
            (
            t
            )
          
        
        =
        
          
            ∑
            
              t
              out
            
            
              
            
          
          ⁢
          
            
          
          ⁢
          
            δ
            ⁡
            
              (
              
                t
                -
                
                  t
                  out
                
              
              )
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          15
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              -
              
                1
                
                  τ
                  s
                
              
            
            ⁢
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          +
          
            
              ∑
              j
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    j
                    in
                  
                
                )
              
            
          
          -
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              
                
                  S
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          16
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                e
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            -
            
              
                
                  e
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              τ
            
          
          +
          
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              
                ∑
                
                  t
                  out
                
                
                  
                
              
              ⁢
              
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          17
        
        )
      
    
  




where:

    
    
        τ is an eligibility traces time constant (typically 50-500 ms),
        Sik (t) is a k-th element in the synaptic state vector {right arrow over (S)}i.
    
    


In some implementations, the basis vectors {right arrow over (b)}m(t) may be expressed using exponents referenced to the time of presynaptic spike t−m×Δt:

{right arrow over (b)}in(t)=H(t−mΔt)e−(t−mΔt)/τs.  (Eqn. 18)

As seen from Eqn. 18, the component vectors {right arrow over (b)}m(t) do not depend on the input and/or output spike time. Accordingly, the vector traces {right arrow over (b)}m(t) may be pre-computed, in one or more implementations, in advance of neuron network operation. In some implementations, the computational load associated with executing updates of a spiking neuron network may be reduced by using these pre-computed during the duration of network operation in lieu of re-computing the components at a time of the update is to be performed
In one or more implementations, synaptic connection weight changes may be based on an additional spiking signal D(t) as follows:




  
    
      
        
          
            
              d
              
                w
                i
              
            
            
              d
              t
            
          
          =
          
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    r
                  
                
                )
              
            
            *
            
              e
              i
            
          
        
        ,
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          19
        
        )
      
    
  




where tr is the arrival time associates with spikes of D(t). In some implementations, the signal D(t) may be used to implement reward-based learning.

State-Dependent Eligibility Traces for Stochastic SRP Neuron

In one or more implementations, EDCC components may comprise one or more eligibility trace configured for implementing connection updates, such as, for example, adapting weights of synaptic connections. In one or more implementations of a stochastic neuron operable according to a spike-response process (SRP), the eligibility trace may be configured as dependent on a state of the connection at the time of the respective event (e.g., the input spike).
In one such implementation, the update process (e.g., Eqn. 13, Eqn. 14) may be expressed using the following framework:

    
    
        two dimensional synapse state vector {right arrow over (S)}i(t)={Si(t),xi(t)};
        {right arrow over (k)}i={0,1}
        time and activity independent two-dimensional matrix, expressed as:
    
    






  
    
      
        
          
            A
            ⁡
            
              (
              
                q
                ,
                t
                ,
                
                  t
                  out
                
              
              )
            
          
          =
          
            [
            
              
                {
                
                  
                    1
                    
                      τ
                      
                        s
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                  
                  ,
                  
                    -
                    1
                  
                
                }
              
              ;
              
                {
                
                  0
                  ,
                  
                    1
                    
                      τ
                      
                        s
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                
                }
              
            
            ]
          
        
        ;
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          20
        
        )
      
    
  




    
    
        reset of synapse state to zero after individual post-synaptic spikes, expressed as Rs(t)={right arrow over (S)}1(t); and
        function of a state of the neuron in discrete time (e.g., Eqn. 12), expressed as:
    
    






  
    
      
        
          Q
          ⁡
          
            (
            t
            )
          
        
        =
        
          κ
          ⁢
          
            
          
          ⁢
          λ
          ⁢
          
            
          
          ⁢
          
            (
            t
            )
          
          ⁢
          
            (
            
              1
              -
              
                
                  ∑
                  
                    t
                    out
                  
                  
                    
                  
                
                ⁢
                
                  
                
                ⁢
                
                  
                    δ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      (
                      
                        t
                        -
                        
                          t
                          out
                        
                      
                      )
                    
                  
                  
                    Λ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      (
                      t
                      )
                    
                  
                
              
            
            )
          
          ⁢
          Δ
          ⁢
          
            
          
          ⁢
          t
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          21
        
        )
      
    
  




Accordingly, the update process may be characterized as follows:




  
    
      
        
          
            d
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              -
              
                1
                
                  τ
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
            
            ⁢
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          +
          
            
              x
              i
            
            ⁡
            
              (
              t
              )
            
          
          -
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              
                
                  S
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          22
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                x
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              -
              
                1
                
                  τ
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            ⁢
            
              
                x
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          +
          
            
              ∑
              j
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    j
                    in
                  
                
                )
              
            
          
          -
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              
                
                  x
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          23
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                e
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            -
            
              
                
                  e
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              τ
            
          
          +
          
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              Q
              ⁡
              
                (
                t
                )
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          24
        
        )
      
    
  




where:

    
    
        τs is a STDP time constant (typically 30-100 ms),
        τ is an eligibility traces time constant (typically 50-500 ms), and
        Sik(T) is a k-th element in the synaptic state vector {right arrow over (S)}i.
    
    


In one or more implementations, weights changes may be configured based on an additional signal F(t) as follows:




  
    
      
        
          
            
              d
              
                w
                i
              
            
            
              d
              t
            
          
          =
          
            
              F
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              e
              i
            
          
        
        ,
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          25
        
        )
      
    
  




where F(t) is the performance function associated with the learning process effectuated by the neuron network updates. In one or more implementations, learning may be effectuated by minimizing the performance function F(t), as described for example in a co-owned and co-pending U.S. patent application Ser. No. 13/487,499, entitled “STOCHASTIC APPARATUS AND METHODS FOR IMPLEMENTING GENERALIZED LEARNING RULES” filed Jun. 4, 2012, incorporated herein by reference in its entirety.

In some implementations, the efficient update methodology described herein may be effectuated using high level neuromorphic language description (HLND) described in detail in co-pending and co-owned U.S. patent application Ser. No. 13/385,938 entitled “TAG-BASED APPARATUS AND METHODS FOR NEURAL NETWORKS” filed on Mar. 15, 2012, incorporated herein by reference in its entirety. FIG. 13 presents one exemplary HLND script configured to effectuate state-dependent eligibility trace for use, for example with methods of FOGS. 9A-9D described supra.
Eligibility Traces with Non-Associative LTP Term
In one or more implementations, EDCC components may comprise one or more eligibility trace configured for implementing non associative connection updates, such as, for example, adapting weights of synaptic connections, comprising long term connection depression (LTD).
In one such implementation, the update process (e.g., Eqn. 13, Eqn. 14) may be expressed using the following framework:

    
    
        one dimensional synapse state vector {right arrow over (S)}i(t)=Si(t);
        ki=1
        time and activity independent one-dimensional matrix, expressed as
    
    






  
    
      A
      ⁡
      
        (
        
          q
          ,
          t
          ,
          
            t
            out
          
        
        )
      
    
    =
    
      1
      
        τ
        s
      
    
  
  ;




    
    
        reset of synapse state to zero after individual post-synaptic spikes Rs(t)=−Si(t); and
        neuron state process, expressed as:
    
    






  
    
      
        
          Q
          ⁡
          
            (
            t
            )
          
        
        =
        
          
            -
            
              
                ∑
                
                  t
                  out
                
                
                  
                
              
              ⁢
              
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
          +
          P
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          26
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              -
              
                1
                
                  τ
                  s
                
              
            
            ⁢
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          +
          
            
              ∑
              j
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    j
                    in
                  
                
                )
              
            
          
          -
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              
                
                  S
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          27
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                e
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            -
            
              
                
                  e
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              τ
            
          
          +
          
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              (
              
                
                  
                    ∑
                    
                      t
                      out
                    
                    
                      
                    
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    δ
                    ⁡
                    
                      (
                      
                        t
                        -
                        
                          t
                          out
                        
                      
                      )
                    
                  
                
                -
                P
              
              )
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          28
        
        )
      
    
  




where:

    
    
        τs is a STDP time constant (typically 30-100 ms),
        τ is an eligibility traces time constant (typically 50-500 ms),
        Sik(T) is a k-th element in the synaptic state vector {right arrow over (S)}i, and
        P is a non-associative LTP (for e.g., non-associative potentiation of weights that received input spikes).
    
    


In some implementations, the basis vectors {right arrow over (b)}m(t) may be expressed using exponents referenced to the time of presynaptic spike t−×Δt:

{right arrow over (b)}m(t)=H(t−mΔt)e−(t−mΔt)τs.  (Eqn. 29)

As seen from Eqn. 29, the component vectors {right arrow over (b)}m(t) do not depend on the input and/or output spike time. Accordingly, the vector traces {right arrow over (b)}m(t) may be pre-computed, in one or more implementations, in advance of neuron network operation. In some implementations, the computational load associated with executing updates of a spiking neuron network may be reduced by using these pre-computed during the duration of network operation in lieu of re-computing the components at a time of the update is to be performed.
In one or more implementations, weight changes may be effectuated by an additional spiking signal:




  
    
      
        
          
            
              d
              
                w
                i
              
            
            
              d
              t
            
          
          =
          
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    r
                  
                
                )
              
            
            ⁢
            
              e
              i
            
          
        
        ,
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          30
        
        )
      
    
  




where tr time of arrival of the additional signal spikes.

Focused Exploration STDP

In one or more implementations, EDCC components may comprise one or more eligibility trace configured for implementing reward-based focused exploration during reinforcement learning. In one or more implementations, the exploration may comprise potentiation of inactive neurons, as described for example a co-owned U.S. patent application Ser. No. 13/489,280 entitled “APPARATUS AND METHODS FOR REINFORCEMENT LEARNING IN ARTIFICIAL NEURAL NETWORKS”, filed Jun. 5, 2012, [client reference BC201204A] incorporated supra.
In one such implementation, the update process (e.g., Eqn. 13, Eqn. 14) may be expressed using the following framework:

    
    
        one dimensional synapse state vector {right arrow over (S)}i(t)=Si(t);
        ki=1
        time and activity independent one-dimensional matrix
    
    






  
    
      A
      ⁡
      
        (
        
          q
          ,
          t
          ,
          
            t
            out
          
        
        )
      
    
    =
    
      1
      
        τ
        s
      
    
  
  ;




    
    
        reset of synapse state to zero after individual post-synaptic spikes, expressed as Rs(t)=−Si(t);
        function of a state of the neuron
    
    






  
    
      
        
          Q
          ⁡
          
            (
            t
            )
          
        
        =
        
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              δ
              ⁢
              
                (
                
                  t
                  -
                  
                    t
                    out
                  
                
                )
              
            
          
          +
          
            P
            *
            
              H
              ⁡
              
                (
                
                  -
                  
                    R
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          31
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              -
              
                1
                
                  τ
                  s
                
              
            
            ⁢
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          +
          
            
              ∑
              j
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              δ
              ⁡
              
                (
                
                  t
                  -
                  
                    t
                    j
                    in
                  
                
                )
              
            
          
          -
          
            
              ∑
              
                t
                out
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              
                
                  S
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                δ
                ⁡
                
                  (
                  
                    t
                    -
                    
                      t
                      out
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          32
        
        )
      
    
  
  
    
      
        
          
            d
            
              
                e
                i
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            -
            
              
                
                  e
                  i
                
                ⁡
                
                  (
                  t
                  )
                
              
              τ
            
          
          +
          
            
              
                S
                i
              
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              Q
              ⁡
              
                (
                t
                )
              
            
          
        
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          33
        
        )
      
    
  




where:

    
    
        τs is a STDP time constant (typically 30-100 ms),
        τ is an eligibility traces time constant (typically 50-500 ms),
        Sik(t) is a k-th element in the synaptic state vector {right arrow over (S)}i,
        P describes non-associative LTD (for e.g., non-associative depression of weights that received input spikes), and
        H(x) is a Heaviside step function that is equals to 1 if argument is positive, 0 otherwise.
    
    


In some implementations, the basis vectors {right arrow over (b)}m(t) may be expressed using exponents referenced to the time of presynaptic spike t−m×Δt:

{right arrow over (b)}m(t)=H(t−mΔt)e−(t−mΔt)/τs.  (Eqn. 34)

As seen from Eqn. 34, the component vectors {right arrow over (b)}m(t) do not depend on the input and/or output spike time. Accordingly, the vector traces {right arrow over (b)}m(t) may be pre-computed, in one or more implementations, in advance of neuron network operation. In some implementations, the computational load associated with executing updates of a spiking neuron network may be reduced by using these pre-computed during the duration of network operation in lieu of re-computing the components at a time of the update is to be performed.
In one or more implementations, weights changes may be configured based on an additional signal R(t) as follows:




  
    
      
        
          
            
              d
              
                w
                i
              
            
            
              d
              t
            
          
          =
          
            
              R
              ⁡
              
                (
                t
                )
              
            
            ⁢
            
              e
              i
            
          
        
        ,
      
    
    
      
        (
        
          Eqn
          .
          
            
          
          ⁢
          35
        
        )
      
    
  




where R(t) is the reinforcement (e.g., reward and/or punishment) signal associated with the learning process effectuated by the neuron network updates. In one or more implementations, learning may be effectuated by selectively potentiating inactive neurons in accordance with the reinforcement signal, as described for example in a co-owned and co-co-owned U.S. patent application Ser. No. 13/489,280 entitled “APPARATUS AND METHODS FOR REINFORCEMENT LEARNING IN ARTIFICIAL NEURAL NETWORKS”, filed Jun. 5, 2012, [client reference BC201204A], incorporated supra.

Exemplary Methods

FIGS. 5-9 illustrate methods of efficient connection updates for a neuron of a neural network in accordance with one or more implementations. The operations of methods FIGS. 5-9 described below are intended to be illustrative. In some embodiments, methods 500, 600, 700, and/or 900 may be accomplished with one or more additional operations not described, and/or without one or more of the operations discussed. Additionally, the order in which the operations of methods are illustrated in FIGS. 5-9 and described below is not intended to be limiting.
In one or more implementations, methods of FIGS. 5-9 may be implemented in one or more processing devices (e.g., a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and/or other mechanisms for electronically processing information). The one or more processing devices may include one or more devices executing some or all of the operations of method 500, 600, 700, and/or 900 in response to instructions stored electronically on an electronic storage medium. The one or more processing devices may include one or more devices configured through hardware, firmware, and/or software to be specifically designed for execution of one or more of the operations of methods 500, 600, 700, and/or 900.
Referring now to FIG. 5 one exemplary implementation of the generalized update method of the disclosure for use with, for example, the neuron 430 of FIG. 4 may be described in detail. The method 500 of FIG. 5 may allow users to implement a broad range of plasticity rules, such as, for example (i) modulated STDP, state dependent plasticity, cerebellum-type plasticity, and/or other update types.
At step 502 of method 500 the synaptic connection process description Si(t) may be provided. In some implementations, the generalized synaptic connection process description Si(t) of Eqn. 16 may be expressed using realizations of, Eqn. 22, Eqn. 27, Eqn. 32, described above.
At step 504 description of neuron state process Q(t) may be provided. In one or more implementations, the neuron process may comprise stochastic spike response process of Eqn. 21. In one or more implementations, the neuron process may comprise deterministic process described, for example by Eqn. 15, Eqn. 26, Eqn. 31, and/or other appropriate process description.
At step 506, rate of change (ROC) of eligibility traces for one or more connections may be determined. In some implementations, the connection eligibility trace ROC may be determined using Eqn. 14. In some implementations, the ROC may be determined using formulations of Eqn. 17, Eqn. 24, Eqn. 28, Eqn. 33 and/or other realizations.
At step 508, present value of the eligibility trace e(t+Δt) at time t+Δt may be determined. In one or more implementations, the present value of the eligibility trace may be determined based on a prior eligibility trace value and an adjustment term. In some implementations the adjustment term may comprise a product of the connection-specific parameter S(t) and neuron-specific parameter Q(t) as follows:




  
    
      
        
          
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In some implementations, the connection eligibility trace may be determined by integrating formulations Eqn. 17, Eqn. 24, Eqn. 28Eqn. 33 and/or other appropriate realizations.
At step 510, learning parameter of multiple connections may be updated. In some implementations, the learning parameter may comprise connection synaptic weight. In one or more implementations, the update may be effectuated using formulations of Eqn. 19, Eqn. 25, Eqn. 30, Eqn. 35 and/or other appropriate realizations.
FIG. 6 illustrates one exemplary implementation of network operation in accordance with generalized update framework of the disclosure for use with, for example, the neuron 430 of FIG. 4. The method 600 of FIG. 9 may allow users to effectuate automatic network configuration in accordance with the desired plasticity update mechanism prior to network operation.
At step 602 of method 600 determination may be made as to whether neuronal state process Q(t) is time invariant.
When Q(t) is independent of time (such as, for example, when neuron portion of the connection weight adjustment rule does not change, e.g., Δw∝ud, d=const), an analytical solution for the eligibility trace may be determined at step 610.
Subsequently, at step 612, computer code may be generated in order to implement determination of eligibility traces on the basis of spike timing using the analytical solution determined at step 610, above. By way of illustration, in one implementation, the analytical solution of step 610 may be expressed as

e(t)=exp(−(t−tin));  (Eqn. 37)

Accordingly, the computer code of step 612 may comprise code capable of implementing the relationship of Eqn. 37.

When Q(t) is time dependent, such as, for example, when neuron portion of the connection weight adjustment rule does may depend on neuron state and/or time, e.g., Δw∝ud, d=d(t); d=d(u(t))), an efficient STDP methodology may be employed.
In some implementations, efficient update methodology described in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra, may be employed. In one or more implementations, the above-references efficient update methodology may comprise look-up table (LUT) configured to store an array of basis vectors bm configured to provide event-dependent connection change components.
Accordingly, at step 604, the LUT may be allocated. In some implementations, the LUT may be allocated in neuron and/or synaptic memory, as described for example in a commonly owned and co-pending U.S. patent application Ser. No. 13/239,255 filed Sep. 21, 2011, entitled “APPARATUS AND METHODS FOR SYNAPTIC UPDATE IN A PULSE-CODED NETWORK”, [client reference BRAIN.008A] incorporated herein by reference in its entirety. In some implementations, the LUT may be allocated in synaptic and/or neuron memory, comprising shared memory, such as, for example memory block 1108 of FIG. 11A. In some implementations, the LUT may be allocated in neuron specific memory (e.g., memory block 1134 of FIG. 11B).
At step 606, code capable of determining synaptic updates using the efficient update framework may be generated. In one or more implementations, the code may comprise one or more programs capable of determining event dependent connection change (EDCC) components bm.
In one or more implementations, at step 608 of method 600 the code configured at step 606 may be employed in order to perform synaptic updates during operation of the network in accordance with the efficient update framework, such as, for example, described with respect to FIG. 7, below.
At step 704 of method 700, a set of event-dependent connection change basis vectors bm(t) may be computed for the time interval (tup−T), as described above with respect to Eqn. 18, Eqn. 29, Eqn. 34.
At step 706 the EDCC components ym(t) may be computed by, for example, using the basis vectors bm(t) and Euler's integration method.
At step 708, the eligibility traces eij(t) may be computed by, for example, using a linear combination of the EDCC components ym(t) as described, for example, in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra.
At step 710, the connection parameter θij adjustment (e.g., plasticity update) may be computed using the eligibility traces and the performance function, as shown, for example, by Eqn. 25, Eqn. 35.
FIGS. 8A-8C provide an exemplary program listing capable of determining synaptic updates using efficient update framework based on event dependent connection change (EDCC) components, such as for example, the program code described with respect to method 600 above. The program listing of FIGS. 8A-8C may comprise, inter alia, one or more instructions configured to implement LUTs per neuron. It is noteworthy, the neuron implementation of FIGS. 8A-8C may comprise one or more synapses operable in accordance with event-based efficient update rules thereby advantageously alleviating the use an UPDATE_RULE that may be executed at individual time steps Δt of network operation.
FIG. 9 illustrates one exemplary implementation of modulated STDP update in accordance with generalized update framework of the disclosure. The method 900 of FIG. 9 may allow users to effectuate reward-based plasticity updates when implementing reinforcement learning.
At step 902 of method 900, neuronal plasticity term Q(t) may be determined. In one or more implementations, the neuronal term Q(t) may be determined based on the tie history of neuron post-synaptic activity.
At step 904, rate of change of the eligibility trace for one or more (M) connections may be determined. In some implementations, the eligibility trace ROC may be determined in accordance with Eqn. 17.
At step 906, connection learning parameter modification may be determined based on the eligibility trace and reinforcement signal timing. In one or more implementations, the learning parameter change may be determined in accordance with Eqn. 19
At step 908 of method 900, learning parameters of M connections may be updated. In one or more implementations, immediate (on demand) and/or synchronized update may be effectuated, as described in detail in U.S. patent application Ser. No. 13/560,891 entitled “APPARATUS AND METHODS FOR EFFICIENT UPDATES IN SPIKING NEURON NETWORKS”, filed Jul. 27, 2012, incorporated supra.
Exemplary Apparatus
Various exemplary spiking network apparatus comprising one or more of the methods set forth herein (e.g., using the efficient connection plasticity update mechanism explained above) are now described with respect to FIGS. 10-11D.
Adaptive Processing Apparatus
One apparatus for processing of sensory information (e.g., visual, audio, somatosensory) using spiking neural network comprising for example the efficient connection plasticity update mechanism is shown in FIG. 10. The illustrated processing apparatus 1000 may comprise an input interface configured to receive an input sensory signal 1020. In some implementations, this sensory input may comprise electromagnetic waves (e.g., visible light, IR, UV, etc.) entering an imaging sensor array (comprising RGCs, a charge coupled device (CCD), or an active-pixel sensor (APS)). The input signal in this case may be a sequence of images (image frames) received from a CCD camera via a receiver apparatus, or downloaded from a file. Alternatively, the image may be a two-dimensional matrix of RGB values refreshed at a 24 Hz frame rate. It will be appreciated by those skilled in the art that the above image parameters are merely exemplary, and many other image representations (e.g., bitmap, CMYK, grayscale, etc.) and/or frame rates are equally useful with the present invention.
The apparatus 1000 may comprise an encoder 1024 configured to transform (encodes) the input signal into an encoded signal 1026. In one variant, the encoded signal may comprise a plurality of pulses (also referred to as a group of pulses) configured to model neuron behavior. The encoded signal 1026 may be communicated from the encoder 1024 via multiple connections (also referred to as transmission channels, communication channels, or synaptic connections) 1004 to one or more neuronal nodes (also referred to as the detectors) 1002.
In the implementation of FIG. 10, different detectors of the same hierarchical layer may be denoted by a “_n” designator, such that e.g., the designator 1002_1 denotes the first detector of the layer 1002. Although only two detectors (1002_1, 1002—n) are shown in the embodiment of FIG. 10 for clarity, it is appreciated that the encoder can be coupled to any number of detector nodes that may be compatible with the detection apparatus hardware and software limitations. Furthermore, a single detector node may be coupled to any practical number of encoders.
In one embodiment, individual ones of the detectors 1002_1, 1002—n contain logic (which may be implemented as a software code, hardware logic, or a combination of thereof) configured to recognize a predetermined pattern of pulses in the encoded signal 1004, using for example any of the mechanisms described in U.S. patent application Ser. No. 12/869,573, filed Aug. 26, 2010 and entitled “SYSTEMS AND METHODS FOR INVARIANT PULSE LATENCY CODING”, U.S. patent application Ser. No. 12/869,583, filed Aug. 26, 2010, entitled “INVARIANT PULSE LATENCY CODING SYSTEMS AND METHODS”, U.S. patent application Ser. No. 13/117,048, filed May 26, 2011 and entitled “APPARATUS AND METHODS FOR POLYCHRONOUS ENCODING AND MULTIPLEXING IN NEURONAL PROSTHETIC DEVICES”, [BRAIN.006A] U.S. patent application Ser. No. 13/152,084, filed Jun. 2, 2011, entitled “APPARATUS AND METHODS FOR PULSE-CODE INVARIANT OBJECT RECOGNITION”, [client reference BRAIN.001A] each incorporated herein by reference in its entirety, to produce post-synaptic detection signals transmitted over communication channels 1008. In FIG. 10, the designators 1008_1, 1008—n denote output of the detectors 1002_1, 1002—n, respectively.
In one implementation, the detection signals may be delivered to a next layer of the detectors 1012 (comprising detectors 1012_1, 1012—m, 1012—k) for recognition of complex object features and objects, similar to the exemplary implementation described in commonly owned and co-pending U.S. patent application Ser. No. 13/152,084, filed Jun. 2, 2011, entitled “APPARATUS AND METHODS FOR PULSE-CODE INVARIANT OBJECT RECOGNITION”, [client reference BRAIN.001A] incorporated herein by reference in its entirety. In this implementation, individual subsequent layers of detectors may be configured to receive signals from the previous detector layer, and to detect more complex features and objects (as compared to the features detected by the preceding detector layer). For example, a bank of edge detectors may be followed by a bank of bar detectors, followed by a bank of corner detectors and so on, thereby enabling alphabet recognition by the apparatus.
Individual ones of the detectors 1002 may output detection (post-synaptic) signals on communication channels 1008_1, 1008—n (with appropriate latency) that may propagate with different conduction delays to the detectors 1012. The detector cascade of the embodiment of FIG. 10 may contain any practical number of detector nodes and detector banks determined, inter alia, by the software/hardware resources of the detection apparatus and complexity of the objects being detected.
The sensory processing apparatus implementation illustrated in FIG. 10 may comprise lateral connections 1006.
In some implementations, the apparatus 1000 may comprise feedback connections 1014, configured to communicate context information from detectors within one hierarchy layer to previous layers, as illustrated by the feedback connections 1014_1 in FIG. 10. In some implementations, the feedback connection 1014_2 may be configured to provide feedback to the encoder 1024 thereby facilitating sensory input encoding, as described in detail in commonly owned and co-pending U.S. patent application Ser. No. 13/152,084, filed Jun. 2, 2011, entitled “APPARATUS AND METHODS FOR PULSE-CODE INVARIANT OBJECT RECOGNITION”, [client reference BRAIN.001A] incorporated supra.
Computerized Neuromorphic System
One particular implementation of the computerized neuromorphic processing system, for operating a computerized spiking network (and implementing the exemplary efficient connection plasticity update methodology described supra), is illustrated in FIG. 11A. The computerized system 1100 of FIG. 11A may comprise an input interface 1110, such as for example an image sensor, a computerized spiking retina, an audio array, a touch-sensitive input device, etc. The input interface 1110 may be coupled to the processing block (e.g., a single or multi-processor block) via the input communication interface 1114. The system 1100 may comprise a random access memory (RAM) 1108, configured to store neuronal states and connection parameters (e.g., weights 526 in FIG. 5), and to facilitate synaptic updates. In some implementations, synaptic updates may be performed according to the description provided in, for example, in U.S. patent application Ser. No. 13/239,255 filed Sep. 21, 2011, entitled “APPARATUS AND METHODS FOR SYNAPTIC UPDATE IN A PULSE-CODED NETWORK”, [client reference BRAIN.008A] incorporated by reference supra.
In some implementations, the memory 1108 may be coupled to the processor 1102 via a direct connection (memory bus) 1116. The memory 1108 may also be coupled to the processor 1102 via a high-speed processor bus 1112).
The system 1100 may comprise a nonvolatile storage device 1106, comprising, inter alia, computer readable instructions configured to implement various aspects of spiking neuronal network operation (e.g., sensory input encoding, connection plasticity, operation model of neurons, etc.). in one or more implementations, the nonvolatile storage 1106 may be used to store state information of the neurons and connections when, for example, saving/loading network state snapshot, or implementing context switching (e.g., saving current network configuration (comprising, inter alia, connection weights and update rules, neuronal states and learning rules, etc.) for later use and loading previously stored network configuration.
In some implementations, the computerized apparatus 1100 may be coupled to one or more external processing/storage/input devices via an I/O interface 1120, such as a computer I/O bus (PCI-E), wired (e.g., Ethernet) or wireless (e.g., Wi-Fi) network connection.
In another variant, the input/output interface may comprise a speech input (e.g., a microphone) and a speech recognition module configured to receive and recognize user commands.
It will be appreciated by those skilled in the arts that various processing devices may be used with computerized system 1100, including but not limited to, a single core/multicore CPU, DSP, FPGA, GPU, ASIC, combinations thereof, and/or other processors. Various user input/output interfaces may be similarly applicable to embodiments of the invention including, for example, an LCD/LED monitor, touch-screen input and display device, speech input device, stylus, light pen, trackball, end the likes.
Referring now to FIG. 11B, one implementation of neuromorphic computerized system configured to implement efficient connection plasticity update mechanism in a spiking network is described in detail. The neuromorphic processing system 1130 of FIG. 11B may comprise a plurality of processing blocks (micro-blocks) 1140 where individual micro cores may comprise a computing logic core 1132 and a memory block 1134. The logic core 1132 may be configured to implement various aspects of neuronal node operation, such as the node model, and synaptic update rules (e.g., the I-STDP) and/or other tasks relevant to network operation. The memory block may be configured to store, inter alia, neuronal state variables and connection parameters (e.g., weights, delays, I/O mapping) of connections 1138.
The micro-blocks 1140 may be interconnected with one another using connections 1138 and routers 1136. As it is appreciated by those skilled in the arts, the connection layout in FIG. 11B is exemplary, and many other connection implementations (e.g., one to all, all to all, etc.) may be compatible with the disclosure.
The neuromorphic apparatus 1130 may be configured to receive input (e.g., visual input) via the interface 1142. In one or more implementations, applicable for example to interfacing with computerized spiking retina, or image array, the apparatus 1130 may provide feedback information via the interface 1142 to facilitate encoding of the input signal.
The neuromorphic apparatus 1130 may be configured to provide output (e.g., an indication of recognized object or a feature, or a motor command, e.g., to zoom/pan the image array) via the interface 1144.
The apparatus 1130, in one or more implementations, may interface to external fast response memory (e.g., RAM) via high bandwidth memory interface 1148, thereby enabling storage of intermediate network operational parameters (e.g., spike timing, etc.). The apparatus 1130 may also interface to external slower memory (e.g., Flash, or magnetic (hard drive)) via lower bandwidth memory interface 1146, in order to facilitate program loading, operational mode changes, and retargeting, where network node and connection information for a current task may be saved for future use and flushed, and previously stored network configuration may be loaded in its place.
FIG. 11C, illustrates one or more implementation of shared bus neuromorphic computerized system comprising micro-blocks, described with respect to FIG. 11B, supra. architecture coupled to a shared) 1140. The apparatus 1145 of FIG. 11C utilized one o (or more) shared bus 1146 in order to interconnect micro-blocks 1140 with one another.
FIG. 11D, illustrates one implementation of cell-based neuromorphic computerized system architecture configured to implement efficient connection plasticity update mechanism in a spiking network is described in detail. The neuromorphic system 1150 of FIG. may comprise a hierarchy of processing blocks (cells block). In some implementations, the lowest level L1 cell 1152 of the apparatus 1150 may comprise logic and memory and may be configured similar to the micro block 1140 of the apparatus shown in FIG. 11B. A number of cell blocks may be arranges in a cluster and communicate with one another a local interconnects 1162, 1164. Individual ones of such clusters may form higher level cell, e.g., cell L2, denoted as 1154 in FIG. 11d. Similarly several L2 clusters may communicate with one another via a second level interconnect 1166 and form a super-cluster L3, denoted as 1156 in FIG. 11D. The super-clusters 1154 may communicate via a third level interconnect 1168 and may form a next level cluster, and so on. It will be appreciated by those skilled in the arts that the hierarchical structure of the apparatus 1150, comprising four cells-per-level, is merely one exemplary implementation, and other implementations may comprise more or fewer cells per level, and/or fewer or more levels.
Different cell levels (e.g., L1, L2, L3) of the apparatus 1150 may be configured to perform functionality various levels of complexity. In one implementation, different L1 cells may process in parallel different portions of the visual input (e.g., encode different frame macro-blocks), with the L2, L3 cells performing progressively higher level functionality (e.g., edge detection, object detection). Different L2, L3, cells may also perform different aspects of operating, for example, a robot, with one or more L2/L3 cells processing visual data from a camera, and other L2/L3 cells operating motor control block for implementing lens motion what tracking an object or performing lens stabilization functions.
The neuromorphic apparatus 1150 may receive input (e.g., visual input) via the interface 1160. In one or more implementations, applicable for example to interfacing with computerized spiking retina, or image array, the apparatus 1150 may provide feedback information via the interface 1160 to facilitate encoding of the input signal.
The neuromorphic apparatus 1150 may provide output (e.g., an indication of recognized object or a feature, or a motor command, e.g., to zoom/pan the image array) via the interface 1170. In some implementations, the apparatus 1150 may perform all of the I/O functionality using single I/O block (not shown).
The apparatus 1150, in one or more implementations, may interface to external fast response memory (e.g., RAM) via high bandwidth memory interface (not shown), thereby enabling storage of intermediate network operational parameters (e.g., spike timing, etc.). In one or more implementations, the apparatus 1150 may also interface to external slower memory (e.g., flash, or magnetic (hard drive)) via lower bandwidth memory interface (not shown), in order to facilitate program loading, operational mode changes, and retargeting, where network node and connection information for a current task may be saved for future use and flushed, and previously stored network configuration may be loaded in its place.
Exemplary Uses and Applications of Certain Aspects of the Invention
Advantageously, the methodology described herein may provide generalized framework for implementing state-dependent learning in spiking neuron networks. In some implementations, learning parameter adjustment for a connection may be configured based on the eligibility trace associated with the connection. The eligibility trace time evolution may be expressed based on neuron-specific term and connection specific term. Accordingly, implementation specific program code may be ‘plugged-in’ into the generalized framework thereby enabling seamless implementation of a wide range of plasticity rules.
Efficient update methodology may advantageously be traded for (i) reduction in cost, complexity, size and power consumption of a neuromorphic apparatus that may be required to operate the network; and/or (ii) increase apparatus throughput thereby allowing for networks of higher synapse density. The use of efficient neuron network update framework, may reduce neuron network development costs by enabling the users to rely on the framework to implement updates efficiently, thereby alleviating additional coding efforts.
In one or more implementations, the generalized state-dependent learning methodology of the disclosure may be implemented as a software library configured to be executed by a computerized neural network apparatus (e.g., containing a digital processor). In some implementations, the generalized learning apparatus may comprise a specialized hardware module (e.g., an embedded processor or controller). In some implementations, the spiking network apparatus may be implemented in a specialized or general purpose integrated circuit (e.g., ASIC, FPGA, and/or PLD). Myriad other implementations may exist that will be recognized by those of ordinary skill given the present disclosure.
Advantageously, the present disclosure can be used to simplify and improve control tasks for a wide assortment of control applications including, without limitation, industrial control, adaptive signal processing, navigation, and robotics. Exemplary implementations of the present disclosure may be useful in a variety of devices including without limitation prosthetic devices (such as artificial limbs), industrial control, autonomous and robotic apparatus, HVAC, and other electromechanical devices requiring accurate stabilization, set-point control, trajectory tracking functionality or other types of control. Examples of such robotic devices may include manufacturing robots (e.g., automotive), military devices, and medical devices (e.g., for surgical robots). Examples of autonomous navigation may include rovers (e.g., for extraterrestrial, underwater, hazardous exploration environment), unmanned air vehicles, underwater vehicles, smart appliances (e.g., ROOMBA®), and/or robotic toys. The present disclosure can advantageously be used in all other applications of adaptive signal processing systems (comprising for example, artificial neural networks), including: machine vision, pattern detection and pattern recognition, object classification, signal filtering, data segmentation, data compression, data mining, optimization and scheduling, and/or complex mapping.
It will be recognized that while certain aspects of the disclosure are described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods of the invention, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed implementations, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the disclosure disclosed and claimed herein.
While the above detailed description has shown, described, and pointed out novel features of the disclosure as applied to various implementations, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the disclosure. The foregoing description is of the best mode presently contemplated of carrying out the invention. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles of the invention. The scope of the disclosure should be determined with reference to the claims.

## Claims

1. A computer-implemented method of implementing learning in a computerized spiking neuron, the method being performed by one or more processors configured to execute computer program modules, the method comprising:
operating the neuron in accordance with a learning process configured to be updated at one or more time intervals, the learning process update comprising:
retrieving prior values of first and second traces associated, respectively, with first and second connections that are capable of providing spiking input into the neuron;
determining a rate of change of:
(i) the first trace based on (1) the prior value of the first trace and (2) a product of a neuron portion and a first connection portion; and
(ii) the second trace based on (1) the prior value of the second trace and (2) a product of the neuron portion and a second connection portion; and

determining an updated value of the first and second traces based on the respective rate of change;

wherein:
the prior values of the first and the second traces are associated with another update preceding the update,
the first connection portion and the second connection portion are based on one or more spikes of a spiking input being provided, respectively, via the first and the second connections, the one or more spikes occurring within a time interval between the another update and the update; and
the learning process is capable of causing the neuron to generate an output in accordance with the spiking input, the output being characterized by a performance measure configured such that the update is capable of reducing the measure.

2. A computer-implemented method of operating a plurality of data interfaces in a computerized network comprising at least a node, the method being performed by one or more processors configured to execute computer program modules, the method comprising:
storing a time record of one or more data items capable of being provided to the node via the plurality of data interfaces, the time record comprising information associated with individual ones of the one or more data items occurring at an interval prior to present time;
determining a value of a plurality of eligibility traces, based on the time record;
determining a rate of change of a respective trace of the plurality of eligibility traces, based on (i) a present value of the plurality of eligibility traces; and (ii) a product of a node component and a plurality of interface components; and
effectuating an update of individual ones of the plurality of interfaces based on the rate of change;
wherein:
the respective trace of the plurality of eligibility traces is associated with a respective interface of the plurality of interfaces;
the individual ones of the plurality of interface components are configured to characterize the respective trace; and
the node component is configured based on a node state, the node state being common to the plurality of interfaces; and
the update is configured to transition a present instance of the node state towards a target state, the target state being associated with the node generating an output consistent with the one more data items.

3. The method of claim 2, wherein:
individual ones of the plurality of interface components are configured to characterize a state of individual ones of the plurality of interfaces independently from one another; and
the node component is configured to characterize the present instance of the node state for individual ones of the plurality of interfaces simultaneously to one another.

4. The method of claim 2, wherein:
individual ones of the plurality of interfaces are characterized by individual ones of a plurality of synaptic weights; and
the update comprises modifying individual ones of the plurality of synaptic weights based on an updated eligibility trace.

5. The method of claim 4, wherein: the updated eligibility trace is determined via an integration of the rate of change with respect to time.

6. The method of claim 4, wherein:
the modifying individual ones of the weights is determined based on a product of the rate of change and an additional signal, the additional signal being time dependent and configured to affect individual ones of the plurality of interfaces; and
the rate of change for at least one of the weights is capable of being determined independently from other of the weights.

7. The method of claim 6, wherein the additional signal comprises a reinforcement signal conveying information associated with at least one reinforcement spike, the reinforcement signal being configured based on the node state and the target state.

8. The method of claim 7, wherein the update is based on an event comprising one or more of:
(i) generation of the output comprising at least one spike;
(ii) occurrence of the one or more spikes;
(iii) a timer event indicative of an expiration of a current update time period; or
(iv) the at least one reinforcement spike.

9. The method of claim 7, wherein the reinforcement signal is configured based on a distance measure between the output and a target output, the target output being associated with the target state.

10. The method of claim 9, wherein the distance measure comprises one or more of: (i) mean squared error, (ii) weighed error; or (iii) squared error.

11. The method of claim 7, wherein the reinforcement signal is capable of providing:
a positive reward when a distance measure between the present instance of the node state and the target state is smaller compared to a distance measure between a prior node state and the target state; and
a negative reward when the distance measure between the present instance of the node state and the target state is greater compared to the distance measure between the prior state and the target state.

12. The method of claim 6, wherein: the additional signal is configured based on a performance measure determined based on a present performance associated with the present instance of the node state, and a target performance associated with the target state.

13. The method of claim 7, wherein the output is characterized by a spike-free time period subsequent to an occurrence of the least one reinforcement spike.

14. The method of claim 12, wherein the additional signal comprises a negative reward determined based on the present performance being outside a predetermined measure from the target performance.

15. The method of claim 2, wherein:
individual ones of the plurality of eligibility traces are configured based on an analytic solution of a time derivative representation, the time derivative representation configured to characterize the time record; and
the determination of the value of the plurality of eligibility traces comprises integration of the time derivative representation via symbolic integration operation.

16. The method of claim 2, wherein:
the node is capable of being operated in accordance with a dynamic process configured to be updated at time intervals; and
the time interval comprises a plurality of the time intervals.

17. The method of claim 1, wherein:
the update further comprises a synaptic update of efficacy of the first connection and efficacy of the second connection;
efficacy of the first connection configured to affect contribution to state of the spiking neuron due to a portion of the spiking input provided to the neuron via the first connection; and
efficacy of the second connection configured to affect contribution to the state of the spiking neuron due to a portion of the spiking input provided to the neuron via the second connection.

18. The method of claim 17, wherein:
the first connection portion is configured to characterize a first connection and the second connection portion is configured to characterize a second connection; and
the update comprises a modification of efficacy of the first connection and efficacy of the second connection, efficacy modification being configured based on the first trace and the second trace, respectively.

19. The method of claim 18, wherein the efficacy modification of the first and second connections is configured based on a product of the first or the second trace, respectively, and a reinforcement signal comprising at least one reinforcement spike, the reinforcement signal being configured based on present state and a target state of the neuron.

20. The method of claim 18, wherein:
the spiking input is provided during a stimulus interval;
the update comprises a plasticity rule configured to modify a magnitude of the efficacy of the first connection and the efficacy of the second connection efficacy, the modifying of the magnitude having a time window associated therewith; and
the plasticity rule is configured to adjust at least one of (1) a start point of the window and (2) an end point of the window.

21. The method of claim 18, wherein:
the first connection efficacy comprises a first connection weight;
the second connection efficacy comprises a second connection weight;
the first connection weight configured to perform a weighted linear combination on a first portion of the spiking input provided to the neuron via the first connection; and
the second connection weight configured to perform a weighted linear combination on a second portion of the spiking input provided to the neuron via the second connection.

22. The method of claim 21, wherein:
the spiking input is provided during a stimulus interval; and
the update comprises a plasticity rule configured to modify a magnitude of the first connection weight and a magnitude of the second connection weight, the plasticity rule being characterized by a portion of the plasticity rule having a time scale configured substantially comparable to the stimulus interval.

23. The method of claim 22, wherein the plasticity rule is characterized by another portion of the plasticity rule configured to exceed the stimulus interval by at least 10 times.

24. The method of claim 22, wherein the output comprises at least one spike generated by the neuron based on the spiking input.

25. A system configured to operate a plurality of data interface means in a computerized network comprising at least a node means, the system comprising:
a means for storing a time record of one or more data items capable of being provided to the node means via the plurality of data interface means, the time record comprising information associated with individual ones of the one or more data items occurring at an interval prior to present time;
a means for determining a value of a plurality of eligibility trace means, based on the time record;
a means for determining a rate of change of a respective trace means of the plurality of eligibility trace means, based on (i) a present value of the plurality of eligibility trace means; and (ii) a product of a node component means and a plurality of interface component means; and
a means for effectuating an update of individual ones of the plurality of interface means based on the rate of change;
wherein:
the respective trace means of the plurality of eligibility trace means is associated with a respective interface means of the plurality of interface means;
the individual ones of the plurality of interface component means are configured to characterize the respective trace means; and
the node component means is configured based on a node state, the node state being common to the plurality of interface means; and
the update is configured to transition a present instance of the node state towards a target state, the target state being associated with the node means generating an output consistent with the one more data items.