# Patent

## Title
Load control device for a light-emitting diode light source

## Abstract

A load control device for controlling the intensity of a light source (e.g., a light-emitting diode light source) reduces visible flickering in the light source when a target intensity of the light source is dynamically changing. The load control device includes a load regulation circuit operable to conduct a load current through the electrical load and to control the amount of power delivered to the electrical load. The load control device also includes a controller for adjusting the average magnitude of the load current to a target current. The controller pulse-width modulates the magnitude of the load current between a first current less than the target current and a second current greater than the target current. When the target current is dynamically changing, the controller is operable to adjust to the average magnitude of the load current towards the sum of the target current and a supplemental signal.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a non-provisional application of commonly-assigned U.S. Provisional Application No. 61/668,759, filed Jul. 6, 2012, entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosure of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a load control device for a light-emitting diode (LED) light source, and more particularly, to an LED driver for controlling the intensity of an LED light source.
2. Description of the Related Art
Light-emitting diode (LED) light sources (i.e., LED light engines) are often used in place of or as replacements for conventional incandescent, fluorescent, or halogen lamps, and the like. LED light sources may comprise a plurality of light-emitting diodes mounted on a single structure and provided in a suitable housing. LED light sources are typically more efficient and provide longer operational lives as compared to incandescent, fluorescent, and halogen lamps. In order to illuminate properly, an LED driver control device (i.e., an LED driver) must be coupled between an alternating-current (AC) source and the LED light source for regulating the power supplied to the LED light source. The LED driver may regulate either the voltage provided to the LED light source to a particular value, the current supplied to the LED light source to a specific peak current value, or may regulate both the current and voltage.
LED light sources are typically rated to be driven via one of two different control techniques: a current load control technique or a voltage load control technique. An LED light source that is rated for the current load control technique is also characterized by a rated current (e.g., approximately 350 milliamps) to which the peak magnitude of the current through the LED light source should be regulated to ensure that the LED light source is illuminated to the appropriate intensity and color. In contrast, an LED light source that is rated for the voltage load control technique is characterized by a rated voltage (e.g., approximately 15 volts) to which the voltage across the LED light source should be regulated to ensure proper operation of the LED light source. Typically, each string of LEDs in an LED light source rated for the voltage load control technique includes a current balance regulation element to ensure that each of the parallel legs has the same impedance so that the same current is drawn in each parallel string.
It is known that the light output of an LED light source can be dimmed. Different methods of dimming LEDs include a pulse-width modulation (PWM) technique and a constant current reduction (CCR) technique. Pulse-width modulation dimming can be used for LED light sources that are controlled in either a current or voltage load control mode. In pulse-width modulation dimming, a pulsed signal with a varying duty cycle is supplied to the LED light source. If an LED light source is being controlled using the current load control technique, the peak current supplied to the LED light source is kept constant during an on time of the duty cycle of the pulsed signal. However, as the duty cycle of the pulsed signal varies, the average current supplied to the LED light source also varies, thereby varying the intensity of the light output of the LED light source. If the LED light source is being controlled using the voltage load control technique, the voltage supplied to the LED light source is kept constant during the on time of the duty cycle of the pulsed signal in order to achieve the desired target voltage level, and the duty cycle of the load voltage is varied in order to adjust the intensity of the light output. Constant current reduction dimming is typically only used when an LED light source is being controlled using the current load control technique. In constant current reduction dimming, current is continuously provided to the LED light source, however, the DC magnitude of the current provided to the LED light source is varied to thus adjust the intensity of the light output. Examples of LED drivers are described in greater detail in commonly-assigned U.S. patent application Ser. No. 12/813,908, filed Jun. 11, 2010, and U.S. patent application Ser. No. 13/416,741, filed Mar. 9, 2012, both entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosures of which are hereby incorporated by reference.
In addition, some LED light sources comprise forward converters for driving the LED light sources to control the load current conducted through the LED light source. Forward converters comprise a transformer having a primary winding coupled to at least one semiconductor switch and a secondary winding operatively coupled to the LED light source. The semiconductor switch is rendered conductive and non-conductive to conduct a primary current through the primary winding and to thus transfer power to the secondary winding of the transformer. Forward converters typically comprise an optocoupler for coupling a feedback signal on the secondary side of the transformer to the primary side of the transformer, such that a controller can control the semiconductor switch is response to the feedback signal. However, there is a need for a forward converter that is able to control the magnitude of the load current through an LED light source without the need for an optocoupler.
SUMMARY OF THE INVENTION
As described herein, a load control device for controlling the intensity of a light source (e.g., a light-emitting diode light source) reduces visible flickering in the light source when a target intensity of the light source is dynamically changing. The load control device includes a load regulation circuit operable to conduct a load current through the electrical load and to control the amount of power delivered to the electrical load. The load control device also includes a controller. When a target current is in a steady state, the controller is operable to pulse-width modulate the magnitude of the load current between a current less than the target current and a current greater than the target current to adjust an average magnitude of the load current to the target current. When the target current is dynamically changing, the controller is operable to pulse-width modulate the magnitude of the load current between a sum of a supplemental signal and a current less than the target current and a sum of the supplemental signal and a current greater than the target current to adjust the average magnitude of the load current towards the sum of the target current and the supplemental signal.
In addition, a method for controlling the amount of power delivered to an electrical load is also described herein. The method comprises: (1) conducting a load current through the electrical load; (2) when a target current is in a steady state, adjusting the average magnitude of the load current to the target current by pulse-width modulating the magnitude of the load current between a current less than the target current and a current greater than the target current; and (3) when the target current is dynamically changing, adjusting the average magnitude of the load current towards a sum of the target current and a supplemental signal by pulse-width modulating the magnitude of the load current between a sum of the supplemental signal and a current less than the target current and a sum of the supplemental signal and a current greater than the target current.
Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of a light-emitting diode (LED) driver for controlling the intensity of an LED light source.
FIG. 2 is a simplified schematic diagram of an isolated forward converter and a current sense circuit of an LED driver.
FIG. 3 is an example diagram illustrating a magnetic core set of an energy-storage inductor of a forward converter.
FIG. 4 shows example waveforms illustrating the operation of a forward converter and a current sense circuit when the intensity of an LED light source is near a high-end intensity.
FIG. 5 shows example waveforms illustrating the operation of a forward converter and a current sense circuit when the intensity of an LED light source is near a low-end intensity.
FIG. 6 is an example plot of a relationship between an offset time and a target intensity of an LED driver.
FIG. 7 is a simplified flowchart of a control procedure executed periodically by a controller of an LED driver.
FIG. 8 is an example plot of a relationship between the offset time and the target intensity of an LED driver.
FIG. 9 shows an example waveform of a load current conducted through an LED light source when a target current of an LED driver is at a steady-state value.
FIG. 10 shows an example waveform of the load current conducted through the LED light source when the target current of the LED driver is being increased with respect to time.
FIG. 11 shows an example waveform of a periodic ramp signal that is added to a target current of an LED driver.
FIG. 12 is a flowchart of a load current adjustment procedure executed periodically by a controller of an LED driver.



DETAILED DESCRIPTION OF THE INVENTION
The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed.
FIG. 1 is a simplified block diagram of a load control device, e.g., a light-emitting diode (LED) driver 100, for controlling the amount of power delivered to an electrical load, such as, an LED light source 102 (e.g., an LED light engine), and thus the intensity of the LED light source. The LED light source 102 is shown as a plurality of LEDs connected in series but may comprise a single LED or a plurality of LEDs connected in parallel or a suitable combination thereof, depending on the particular lighting system. In addition, the LED light source 102 may alternatively comprise one or more organic light-emitting diodes (OLEDs). The LED driver 100 comprises a hot terminal H and a neutral terminal that are adapted to be coupled to an alternating-current (AC) power source (not shown).
The LED driver 100 comprises a radio-frequency (RFI) filter circuit 110 for minimizing the noise provided on the AC mains and a rectifier circuit 120 for generating a rectified voltage VRECT. The LED driver 100 further comprises a boost converter 130, which receives the rectified voltage VRECT and generates a boosted direct-current (DC) bus voltage VBUS across a bus capacitor CBUS. The boost converter 130 may alternatively comprise any suitable power converter circuit for generating an appropriate bus voltage, such as, for example, a flyback converter, a single-ended primary-inductor converter (SEPIC), a Ćuk converter, or other suitable power converter circuit. The boost converter 120 may also operate as a power factor correction (PFC) circuit to adjust the power factor of the LED driver 100 towards a power factor of one. The LED driver 100 also comprises a load regulation circuit, e.g., an isolated, half-bridge forward converter 140, which receives the bus voltage VBUS and controls the amount of power delivered to the LED light source 102 so as to control the intensity of the LED light source between a low-end (i.e., minimum) intensity LLE (e.g., approximately 1-5%) and a high-end (i.e., maximum) intensity LHE (e.g., approximately 100%). Alternatively, the load regulation circuit could comprise any suitable LED drive circuit for adjusting the intensity of the LED light source 102.
The LED driver 100 further comprises a control circuit, e.g., a controller 150, for controlling the operation of the boost converter 130 and the forward converter 140. The controller 150 may comprise, for example, a digital controller or any other suitable processing device, such as, for example, a microcontroller, a programmable logic device (PLD), a microprocessor, an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The controller 150 generates a bus voltage control signal VBUS-CNTL, which is provided to the boost converter 130 for adjusting the magnitude of the bus voltage VBUS. The controller 150 receives from the boost converter 130 a bus voltage feedback control signals VBUS-FB, which is representative of the magnitude of the bus voltage VBUS.
The controller 150 also generates drive control signals VDRIVE1, VDRIVE2, which are provided to the forward converter 140 for adjusting the magnitude of a load voltage VLOAD generated across the LED light source 102 and the magnitude of a load current ILOAD conducted through the LED light source to thus control the intensity of the LED light source to a target intensity LTRGT. The LED driver 100 further comprises a current sense circuit 160, which is responsive to a sense voltage VSENSE that is generated by the forward converter 140 and is representative of the magnitude of the load current ILOAD. The current sense circuit 160 is responsive to a signal-chopper control signal VCHOP (which is received from the controller 150), and generates a load current feedback signal VI-LOAD (which is a DC voltage representative of the magnitude of the load current ILOAD). The controller 150 receives the load current feedback signal VI-LOAD from the current sense circuit 160 and controls the drive control signals VDRIVE1, VDRIVE2 to adjust the magnitude of the load current ILOAD to a target load current ITRGT to thus control the intensity of the LED light source 102 to the target intensity LTRGT. The target load current ITRGT may be adjusted between a minimum load current IMIN and a maximum load current IMAX.
The controller 150 is coupled to a memory 170 for storing the operational characteristics of the LED driver 100 (e.g., the target intensity LTRGT, the low-end intensity LLE, the high-end intensity LHE, etc.). The LED driver 100 may also comprise a communication circuit 180, which may be coupled to, for example, a wired communication link or a wireless communication link, such as a radio-frequency (RF) communication link or an infrared (IR) communication link. The controller 150 may be operable to update the target intensity LTRGT of the LED light source 102 or the operational characteristics stored in the memory 170 in response to digital messages received via the communication circuit 180. Alternatively, the LED driver 100 could be operable to receive a phase-control signal from a dimmer switch for determining the target intensity LTRGT for the LED light source 102. The LED driver 100 further comprises a power supply 190, which receives the rectified voltage VRECT and generates a direct-current (DC) supply voltage VCC for powering the circuitry of the LED driver.
FIG. 2 is a simplified schematic diagram of a forward converter 240 and a current sense circuit 260, e.g., the forward converter 140 and the current sense circuit 160 of the LED driver 100 shown in FIG. 1. The forward converter 240 comprises a half-bridge inverter circuit having two field effect transistors (FETs) Q210, Q212 for generating a high-frequency inverter voltage VINV from the bus voltage VBUS. The FETs Q210, Q212 are rendered conductive and non-conductive in response to the drive control signals VDRIVE1, VDRIVE2, which are received from a controller (e.g., the controller 150). The drive control signals VDRIVE1, VDRIVE2 are coupled to the gates of the respective FETs Q210, Q212 via a gate drive circuit 214 (e.g., part number L6382DTR, manufactured by ST Microelectronics). The controller generates the inverter voltage VINV at a constant operating frequency fOP (e.g., approximately 60-65 kHz) and thus a constant operating period TOP. However, the operating frequency fOP may be adjusted under certain operating conditions. The controller adjusts the duty cycle DC of the inverter voltage VINV to adjust the magnitude of the load current ILOAD and thus the intensity of an LED light source 202. The forward converter 240 may be characterized by a turn-on time TTURN-ON from when the drive control signals VDRIVE1, VDRIVE2 are driven high until the respective FET Q210, Q212 is rendered conductive, and a turn-off time TTURN-OFF from when the drive control signals VDRIVE1, VDRIVE2 are driven low until the respective FET Q210, Q212 is rendered non-conductive.
The inverter voltage VINV is coupled to the primary winding of a transformer 220 through a DC-blocking capacitor C216 (e.g., having a capacitance of approximately 0.047 μF), such that a primary voltage VPRI is generated across the primary winding. The transformer 220 is characterized by a turns ratio nTURNS (i.e., N1/N2) of approximately 115:29. The sense voltage VSENSE is generated across a sense resistor R222, which is coupled series with the primary winding of the transformer 220. The FETs Q210, Q212 and the primary winding of the transformer 220 are characterized by parasitic capacitances CP1, CP2, CP3.
The secondary winding of the transformer 220 generates a secondary voltage, which is coupled to the AC terminals of a full-wave diode rectifier bridge 224 for rectifying the secondary voltage generated across the secondary winding. The positive DC terminal of the rectifier bridge 224 is coupled to the LED light source 202 through an output energy-storage inductor L226 (e.g., having an inductance of approximately 10 mH), such that the load voltage VLOAD is generated across an output capacitor C228 (e.g., having a capacitance of approximately 3 μF).
FIG. 3 is an example diagram illustrating a magnetic core set 290 of an energy-storage inductor (e.g., the output energy-storage inductor L226 of the forward converter 240 shown in FIG. 2). The magnetic core set 290 comprises two E-cores 292A, 292B, and may comprise part number PC40EE16-Z, manufactured by TDK Corporation. The E-cores 292A have respective outer legs 294A, 294B and inner legs 296A, 296B. Each inner leg 296A, 296B may have a width wLEG (e.g., approximately 4 mm). The inner leg 296A of the first E-core 292A has a partial gap 298A (i.e., the magnetic core set 290 is partially-gapped), such that the inner legs 296A, 296B are spaced apart by a gap distance dGAP (e.g., approximately 0.5 mm). The partial gap 298A may extend for a gap width wGAP, e.g., approximately 2.8 mm, such that the gap extends for approximately 70% of the leg width wLEG of the inner leg 296A. Alternatively, both of the inner legs 296A, 296B could comprise partial gaps. The partially-gapped magnetic core set 290 shown in FIG. 3 allows the output energy-storage inductor L226 of the forward converter 240 shown in FIG. 2 to maintain continuous current at low load conditions (e.g., near the low-end intensity LLE).
FIG. 4 shows example waveforms illustrating the operation of a forward converter and a current sense circuit, e.g., the forward converter 240 and the current sense circuit 260 shown in FIG. 2. The controller drives the respective drive control signals VDRIVE1, VDRIVE2 high to approximately the supply voltage VCC to render the respective FETs Q210, Q212 conductive for an on time TON at different times (i.e., the FETs Q210, Q212 are not conductive at the same time). When the high-side FET Q210 is conductive, the primary winding of the transformer 220 conducts a primary current IPRI to circuit common through the capacitor C216 and sense resistor R222. Immediately after the high-side FET Q210 is rendered conductive (at time t1 in FIG. 4), the primary current IPRI conducts a short high-magnitude pulse of current due to the parasitic capacitance CP3 of the transformer 220 as shown in FIG. 4. While the high-side FET Q210 is conductive, the capacitor C216 charges, such that a voltage having a magnitude of approximately half of the magnitude of the bus voltage VBUS is developed across the capacitor. Accordingly, the magnitude of the primary voltage VPRI across the primary winding of the transformer 220 is approximately equal to approximately half of the magnitude of the bus voltage VBUS. When the low-side FET Q212 is conductive, the primary winding of the transformer 220 conducts the primary current IPRI in an opposite direction and the capacitor C216 is coupled across the primary winding, such that the primary voltage VPRI has a negative polarity with a magnitude equal to approximately half of the magnitude of the bus voltage VBUS.
When either of the high-side and low-side FETs Q210, Q212 are conductive, the magnitude of an output inductor current IL conducted by the output inductor L226 and the magnitude of the load voltage VLOAD across the LED light source 202 both increase with respect to time. The magnitude of the primary current IPRI also increases with respect to time while the FETs Q210, Q212 are conductive (after the initial current spike). When the FETs Q210, Q212 are non-conductive, the output inductor current IL and the load voltage VLOAD both decrease in magnitude with respective to time. The output inductor current IL is characterized by a peak magnitude IL-PK and an average magnitude IL-AVG as shown in FIG. 4. The controller increases and decreases the on times TON of the drive control signals VDRIVE1, VDRIVE2 (and the duty cycle DC of the inverter voltage VINV) to respectively increase and decrease the average magnitude IL-AVG of the output inductor current IL and thus respectively increase and decrease the intensity of the LED light source 102.
When the FETs Q210, Q212 are rendered non-conductive, the magnitude of the primary current IPRI drops toward zero amps (e.g., as shown at time t2 in FIG. 4 when the high-side FET Q210 is rendered non-conductive). However, current may continue to flow through the primary winding of the transformer 220 due to the magnetizing inductance LMAG of the transformer (which conducts a magnetizing current IMAG). In addition, when the target intensity LTRGT of the LED light source 102 is near the low-end intensity LLE, the magnitude of the primary current IPRI oscillates after either of the FETs Q210, Q212 is rendered non-conductive due to the parasitic capacitances CP1, CP2 of the FETs, the parasitic capacitance CP3 of the primary winding of the transformer 220, and any other parasitic capacitances of the circuit, such as, parasitic capacitances of the printed circuit board on which the forward converter 240 is mounted.
The real component of the primary current IPRI is representative of the magnitude of the secondary current ISEC and thus the intensity of the LED light source 202. However, the magnetizing current IMAG (i.e., the reactive component of the primary current IPRI) also flows through the sense resistor R222. The magnetizing current IMAG changes from negative to positive polarity when the high-side FET Q210 is conductive, changes from positive to negative polarity when the low-side FET Q212 is conductive, and remains constant when the magnitude of the primary voltage VPRI is zero volts as shown in FIG. 4. The magnetizing current IMAG has a maximum magnitude defined by the following equation:




  
    
      
        
          I
          
            MAG
            ⁢
            
              -
            
            ⁢
            MAX
          
        
        =
        
          
            
              
                V
                BUS
              
              ·
              
                T
                HC
              
            
            
              4
              ·
              
                L
                MAG
              
            
          
          .
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        )
      
    
  




where THC is the half-cycle period of the inverter voltage VINV, i.e., THC=TOP/2. As shown in FIG. 4, the areas 250, 252 are approximately equal, such that the average value of the magnitude of the magnetizing current IMAG when the magnitude of the primary voltage VPRI is greater than approximately zero volts.

The current sense circuit 260 averages the primary current IPRI during the positive cycles of the inverter voltage VINV, i.e., when the high-side FET Q210 is conductive. The load current feedback signal VI-LOAD generated by the current sense circuit 260 has a DC magnitude that is the average value of the primary current IPRI when the high-side FET Q210 is conductive. Because the average value of the magnitude of the magnetizing current IMAG is approximately zero when the high-side FET Q210 is conductive, the load current feedback signal VI-LOAD generated by the current sense circuit is representative of only the real component of the primary current IPRI.
The current sense circuit 260 comprises an averaging circuit for producing the load current feedback signal VI-LOAD. The averaging circuit may comprise a low-pass filter having a capacitor C230 (e.g., having a capacitance of approximately 0.066 uF) and a resistor R232 (e.g., having a resistance of approximately 3.32 kΩ). The low-pass filter receives the sense voltage VSENSE via a resistor R234 (e.g., having resistances of approximately 1 kΩ). The current sense circuit 160 further comprises a transistor Q236 (e.g., a FET as shown in FIG. 2) coupled between the junction of the resistors R232, R234 and circuit common. The gate of the transistor Q236 is coupled to circuit common through a resistor R238 (e.g., having a resistance of approximately 22 kΩ) and receives the signal-chopper control signal VCHOP from the controller.
When the high-side FET Q210 is rendered conductive, the controller drives the signal-chopper control signal VCHOP low towards circuit common to render the transistor Q236 non-conductive for a signal-chopper time TCHOP, which is approximately equal to the on time TON of the high-side FET Q210 as shown in FIG. 4. The capacitor C230 is able to charge from the sense voltage VSENSE through the resistors R232, R234 while the signal-chopper control signal VCHOP is low, such that the magnitude of the load current feedback signal VI-LOAD is the average value of the primary current IPRI and is thus representative of the real component of the primary current during the time when the high-side FET Q210 is conductive. When the high-side FET Q210 is not conductive, the controller 150 drives the signal-chopper control signal VCHOP high to render the transistor Q236 non-conductive. Accordingly, the controller is able to accurately determine the average magnitude of the load current ILOAD from the magnitude of the load current feedback signal VI-LOAD since the effects of the magnetizing current IMAG and the oscillations of the primary current IPRI on the magnitude of the load current feedback signal VI-LOAD are reduced or eliminated completely.
As the target intensity LTRGT of the LED light source 202 is decreased towards the low-end intensity LLE (and the on times TON of the drive control signals VDRIVE1, VDRIVE2 get smaller), the parasitic of the forward converter 140 (i.e., the parasitic capacitances CP1, CP2 of the FETs, the parasitic capacitance CP3 of the primary winding of the transformer 220, and other parasitic capacitances of the circuit) can cause the magnitude of the primary voltage VPRI to slowly decrease towards zero volts after the FETs Q210, Q212 are rendered non-conductive.
FIG. 5 shows example waveforms illustrating the operation of a forward converter and a current sense circuit (e.g., the forward converter 240 and the current sense circuit 260) when the target intensity LTRGT is near the low-end intensity LLE. The gradual drop off in the magnitude of the primary voltage VPRI allows the primary winding to continue to conduct the primary current IPRI, such that the transformer 220 continues to delivered power to the secondary winding after the FETs Q210, Q212 are rendered non-conductive as shown in FIG. 5. In addition, the magnetizing current IMAG continues to increase in magnitude. Accordingly, the controller 150 increases the signal-chopper time TCHOP (during which the signal-chopper control signal VCHOP is low) by an offset time TOS when the target intensity LTRGT of the LED light source 202 is near the low-end intensity LLE. The controller may adjust the value of the offset time TOS as a function of the target intensity LTRGT of the LED light source 202 as shown in FIG. 6. For example, the controller may adjust the value of the offset time TOS linearly with respect to the target intensity LTRGT when the target intensity LTRGT is below a threshold intensity LTH (e.g., approximately 10%) as shown in FIG. 6.
FIG. 7 is a simplified flowchart of a control procedure 300 executed periodically by a controller (e.g., the controller 150 of the LED driver 100 shown in FIG. 1 and/or the controller controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 2). The controller may execute the control procedure 300, for example, at the operating period TOP of the inverter voltage VINV of the forward converter 240. First, the controller determines the appropriate on time TON for the drive control signals VDRIVE1, VDRIVE2 in response to the target intensity LTRGT and the load current feedback signal VI-LOAD at step 310. If the controller should presently control the high-side FET Q210 at step 312, the controller drives the first drive control signal VDRIVE1 high to approximately the supply voltage VCC for the on time TON at step 314. If the target intensity LTRGT is greater than or equal to the threshold intensity LTH at step 316, the controller 150 sets the signal-chopper time TCHOP equal to the on time TON at step 318. If the target intensity LTRGT is less than the threshold intensity LTH at step 316, the controller determines the offset time TOS in response to the target intensity LTRGT at step 320 (e.g., using the relationship shown in FIG. 6), and sets the signal-chopper time TCHOP equal to the sum of the on time TON and the offset time TOS at step 322.
Next, the controller drives the signal-chopper control signal VCHOP low towards circuit common for the signal-chopper time TCHOP at step 324. The controller then samples the averaged load current feedback signal VI-LOAD at step 326 and calculates the magnitude of the load current ILOAD using the sampled value at step 328, for example, using the following equation:




  
    
      
        
          
            I
            LOAD
          
          =
          
            
              
                n
                TURNS
              
              ·
              
                V
                
                  I
                  ⁢
                  
                    -
                  
                  ⁢
                  LOAD
                
              
              ·
              
                T
                HC
              
            
            
              
                R
                SENSE
              
              ·
              
                (
                
                  
                    T
                    CHOP
                  
                  -
                  
                    T
                    DELAY
                  
                
                )
              
            
          
        
        ,
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        )
      
    
  




where TDELAY is the total delay time due to the turn-on time and the turn-off time of the FETs Q210, Q212, e.g., TDELAY=TTURN-ON−TTURN-OFF, which may be equal to approximately 200 μsec. Finally, the control procedure 300 exits after the magnitude of the load current ILOAD has been calculated. If the controller should presently control the low-side FET Q210 at step 312, the controller drives the second drive control signal VDRIVE2 high to approximately the supply voltage VCC for the on time TON at step 330, and the control procedure 300 exits without the controller driving the signal-chopper control signal VCHOP low.

Alternatively, the controller can use a different relationship to determine the offset time TOS throughout the entire dimming range of the LED light source (i.e., from the low-end intensity LLE to the high-end intensity LHE) as shown in FIG. 8. For example, the controller could use the following equation:




  
    
      
        
          
            T
            OS
          
          =
          
            
              
                
                  V
                  BUS
                
                4
              
              ·
              
                C
                PARASITIC
              
            
            
              
                
                  
                    
                      T
                      ON
                    
                    +
                    
                      T
                      
                        OS
                        ⁢
                        
                          -
                        
                        ⁢
                        PREV
                      
                    
                  
                  
                    T
                    HC
                  
                
                ·
                
                  I
                  
                    MAG
                    ⁢
                    
                      -
                    
                    ⁢
                    MAX
                  
                
              
              +
              
                
                  
                    K
                    RIPPLE
                  
                  
                    n
                    TURNS
                  
                
                ·
                
                  I
                  LOAD
                
              
            
          
        
        ,
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        )
      
    
  




where TOS-PREV is the previous value of the offset time, KRIPPLE is the dynamic ripple ratio of the output inductor current IL (which is a function of the load current ILOAD) i.e.,

KRIPPLE=IL-PK/IL-AVG,  (Equation 4)

and CPARASITIC is the total parasitic capacitance between the junction of the FETs Q210, Q212 and circuit common.

As previously mentioned, the controller increases and decreases the on times TON of the drive control signals VDRIVE1, VDRIVE2 for controlling the FETs Q210, Q212 of the forward converter 140 to respectively increase and decrease the intensity of the LED light source. Due to hardware limitations, the controller may be operable to adjust the on times TON of the drive control signals VDRIVE1, VDRIVE2 by a minimum time step TSTEP, which results in a corresponding step ISTEP in the load current ILOAD. Near the high-end intensity LHE, this step ISTEP in the load current ILOAD may be rather large (e.g., approximately 70 mA). Since it is desirable to adjust the load current ILOAD by smaller amounts, the controller is operable to “dither” the on times TON of the drive control signals VDRIVE1, VDRIVE2, e.g., change the on times between two values that result in the magnitude of the load current being controlled to DC currents on either side of the target current ITRGT.
FIG. 9 shows an example waveform of a load current conducted through an LED light source (e.g., the load current ILOAD conducted through the LED light source 102). For example, the load current ILOAD shown in FIG. 9 may be conducted through the LED light source when the target current ITRGT is at a steady-state value of approximately 390 mA. A controller (e.g., the controller 150 of the LED driver 100 shown in FIG. 1 and/or the controller controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 2) may control a forward converter (e.g., the forward converter 140, 240) to conduct the load current ILOAD shown in FIG. 9 through the LED light source. The controller adjusts the on times TON of the drive control signals VDRIVE1, VDRIVE2 to control the magnitude of the load current ILOAD between two DC currents IL-1, IL-2 (e.g., approximately 350 mA and 420 mA, respectively) that are separated by a step ISTEP (which is dependent upon the digital resolution of the LED driver 100 and the impedance of the LED light source 102). In other words, the controller is operable to pulse-width modulate the magnitude of the load current ILOAD between two DC currents IL-1, IL-2. The load current ILOAD is characterized by a dithering frequency fDITHER (e.g., approximately 2 kHz) and a dithering period TDITHER as shown in FIG. 9. For example, a duty cycle DCDITHER of the load current ILOAD may be approximately 57%, such that the average magnitude of the load current ILOAD is approximately equal to the target current ITRGT (e.g., approximately 390 mA for the example of FIG. 9). The dithering frequency fDITHER is high enough that the human eye does not detect the change in the magnitude of the load current ILOAD between the two DC currents IL-1, IL-2 when the target current ITRGT is at a steady-state value.
FIG. 10 shows an example waveform of the load current ILOAD when the target current ITRGT is dynamically changing (i.e., not at a steady-state value). For example, the target current ITRGT is being increased with respect to time as shown in FIG. 10. The controller is able to adjust the on times TON of the drive control signals VDRIVE1, VDRIVE2 to control the magnitude of the load current ILOAD between two DC currents IL-1, IL-2 that are separated by the step ISTEP. The duty cycle DCDITHER of the load current ILOAD increases as the target current ITRGT increases. At some point, the controller is able to control the on times TON of the drive control signals VDRIVE1, VDRIVE2 to achieve the desired target current ITRGT without dithering the on times, thus resulting in a constant section 400 of the load current ILOAD. As the target current ITRGT continues to increase after the constant section 400, the controller is able to control the on times TON of the drive control signals VDRIVE1, VDRIVE2 to dither the magnitude of the load current ILOAD between the DC current IL-2 and a larger DC current IL-3.
However, the constant section 400 of the load current ILOAD as shown in FIG. 10 may cause the human eye to detect a visible step in the adjustment of the intensity of the LED light source. Therefore, when the controller is actively adjusting the intensity of the LED light source, the controller is operable to control the magnitude of the load current ILOAD in response to the sum of the target current ITRGT and a supplemental signal (e.g., a disturbance function). For example, the controller may be operable to control the average magnitude of the lamp current to the sum of the target current ITRGT and the supplemental signal. The supplemental signal may comprise, for example, a periodic signal, such as a periodic ramp signal IRAMP or sawtooth waveform as shown in FIG. 11. Note that the waveform of the ramp signal IRAMP shown in FIG. 11 is a digital waveform, is not to scale, and is provided as an example. The ramp signal IRAMP may be characterized by a ramp frequency fRAMP (e.g., approximately 238 Hz) and a ramp period TRAMP. When the controller is actively adjusting the intensity of the LED light source, a peak magnitude IRAMP-PK of the ramp signal IRAMP is set equal to a maximum ramp signal magnitude IRAMP-MAX (e.g., approximately 150 mA). The ramp signal IRAMP may increase with respect to time in, for example, approximately 35 steps across the length of the ramp period TRAMP. When the controller adds the ramp signal IRAMP to the target current ITRGT to control the on times TON of the drive control signals VDRIVE1, VDRIVE2, the resulting load current ILOAD has a varying magnitude. As a result, the constant section 400 of the load current ILOAD is avoided and the perception to the human eye of the visible steps in the intensity of the LED light source as the controller is actively adjusting the intensity of the LED light source is reduced.
When the target current ITRGT returns to a steady-state value, the controller may stop adding the ramp signal IRAMP to the target current ITRGT. For example, the controller may decrease (e.g., fade) the peak magnitude IRAMP-PK of the ramp signal IRAMP from the maximum ramp signal magnitude IRAMP-MAX to zero amps across a period of time after the target current ITRGT has reached a steady-state value. Alternatively, the controller may decrease the ramp period TRAMP to zero seconds across a period of time after the target current ITRGT has reached a steady-state value.
While FIG. 11 shows the ramp signal IRAMP (i.e., a sawtooth waveform) that is added to the target current ITRGT, other periodic waveforms could be used. For example, a ramp signal or sawtooth waveform having a decreasing amplitude could be used.
FIG. 12 is a flowchart of a load current adjustment procedure 500 executed periodically by a controller (e.g., the controller 150 of the LED driver 100 shown in FIG. 1 and/or the controller controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 2). During the load current adjustment procedure 500, the controller is configured to control the magnitude of the load current ILOAD towards the sum of the target current ITRGT and a supplemental signal (e.g., the ramp signal IRAMP shown in FIG. 11). When the target current ITRGT is not at a steady-state value (i.e., the intensity of the LED light source is presently being adjusted) at step 510, the controller sets the peak magnitude IRAMP-PK of the ramp signal IRAMP equal to the maximum ramp signal magnitude IRAMP-MAX (e.g., approximately 150 mA) at step 512. The controller then controls the magnitude of the load current ILOAD towards the target current ITRGT plus the ramp signal IRAMP at step 514, and the load current adjustment procedure 500 exits.
If the target current ITRGT is at a steady-state value at step 510, but the peak magnitude IRAMP-PK of the ramp signal IRAMP is not equal to zero amps at step 516, the controller fades (e.g., decreases) the peak magnitude IRAMP-PK from the maximum ramp signal magnitude IRAMP-MAX to zero amps across a period of time at step 518, and controls the magnitude of the load current ILOAD to be equal to the target current ITRGT plus the ramp signal IRAMP at step 514, before the load current adjustment procedure 500 exits. Alternatively, the controller may decrease the ramp period TRAMP to zero seconds across a period of time at step 518. When the target current ITRGT is at a steady-state value at step 510 and the peak magnitude IRAMP-PK of the ramp signal IRAMP is equal to zero amps at step 516, the controller controls the magnitude of the load current ILOAD towards the target current ITRGT at step 520, and the load current adjustment procedure 500 exits.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

## Claims

1. A load control device for controlling the amount of power delivered to an electrical load, the load control device comprising:
a load regulation circuit operable to conduct a load current through the electrical load and to control the amount of power delivered to the electrical load; and
a controller coupled to the load regulation circuit;
wherein, when a target current of the load current is in a steady state, the controller is operable to pulse-width modulate the magnitude of the load current between a current less than the target current and a current greater than the target current to adjust an average magnitude of the load current to the target current; and
wherein, when the target current is dynamically changing, the controller is operable to pulse-width modulate the magnitude of the load current between a sum of a supplemental signal and a current less than the target current and a sum of the supplemental signal and a current greater than the target current to adjust the average magnitude of the load current to the sum of the target current and the supplemental signal.

2. The load control device of claim 1, wherein the supplemental signal comprises a periodic ramp signal.

3. The load control device of claim 2, wherein the controller sets a peak magnitude of the periodic ramp signal to a maximum ramp signal magnitude when the target current is dynamically changing.

4. The load control device of claim 3, wherein the controller is operable to decrease the peak magnitude of the periodic ramp signal from the maximum ramp signal to zero amps across a period of time after the target current reaches a steady-state value.

5. The load control device of claim 3, wherein the controller is operable to decrease a ramp period of the periodic ramp signal to zero seconds across a period of time after the target current reaches a steady-state value.

6. The load control device of claim 2, wherein the controller comprises a microprocessor and the periodic ramp signal is a digital signal.

7. The load control device of claim 1, wherein the load regulation circuit comprises an LED drive circuit for an LED light source.

8. The load control device of claim 7, wherein the LED drive circuit comprises a forward converter.

9. The load control device of claim 1, wherein the supplemental signal comprises a sawtooth waveform.

10. The load control device of claim 1, wherein, when the target current is in a steady state, the controller is operable to adjust a duty cycle of the pulse-width modulated load current to adjust the average magnitude of the load current between the current less than the target current and the current greater than the target current; and
wherein, when the target current is dynamically changing, the controller is operable to adjust the duty cycle of the pulse-width modulated load current to adjust the average magnitude of the load current between the sum of the supplemental signal and the current less than the target current and the sum of the supplemental signal and the current greater than the target current.

11. A method for controlling the amount of power delivered to an electrical load, the method comprising:
conducting a load current through the electrical load;
adjusting, when a target current of the load current is in a steady state, an average magnitude of the load current to the target current by pulse-width modulating the magnitude of the load current between a current less than the target current and a current greater than the target current; and
adjusting, when the target current is dynamically changing, the average magnitude of the load current to a sum of the target current and a supplemental signal by pulse-width modulating the magnitude of the load current between a sum of the supplemental signal and a current less than the target current and a sum of the supplemental signal and a current greater than the target current.

12. The method of claim 11, wherein the supplemental signal comprises a periodic ramp signal.

13. The method of claim 12, further comprising:
setting a peak magnitude of the periodic ramp signal to a maximum ramp signal magnitude when the target current is dynamically changing.

14. The method of claim 13, further comprising:
decreasing the peak magnitude of the periodic ramp signal from the maximum ramp signal to zero amps across a period of time after the target current reaches a steady-state value.

15. The method of claim 13, further comprising:
decreasing a ramp period of the periodic ramp signal to zero seconds across a period of time after the target current reaches a steady-state value.

16. The method of claim 11, wherein the supplemental signal comprises a sawtooth waveform.

17. The method of claim 11, wherein the electrical load comprises an LED light source.

18. The method of claim 11, further comprising:
adjusting, when a target current is in a steady state, a duty cycle of the pulse-width modulated load current to adjust the average magnitude of the load current between the current less than the target current and the current greater than the target current; and
adjusting, when the target current is dynamically changing, the duty cycle of the pulse-width modulated load current to adjust the average magnitude of the load current between the sum of the supplemental signal and the current less than the target current and the sum of the supplemental signal and the current greater than the target current.