# Patent

## Title
Level-crossing based circuit and method with offset voltage cancellation

## Abstract

A level-crossing based circuit with offset voltage cancellation includes a first level-crossing detector section having a first output capacitor, wherein the first level-crossing section is configured to charge the first output capacitor to a first voltage corresponding to an input signal. The first voltage includes a first offset voltage. The level-crossing based circuit also includes a second level-crossing detector section having a second output capacitor, wherein the second level-crossing detector section is configured to discharge the second output capacitor to a second voltage corresponding to the input signal such that the second voltage includes a second offset voltage that is substantially equal in magnitude to the first offset voltage and opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.

## Background
RELATED APPLICATIONS
This application claims the benefit of U.S. provisional patent application No. 61/547,243, filed Oct. 14, 2011, the disclosure of which is incorporated herein by reference in its entirety.


GOVERNMENT SUPPORT
This invention was made with government funds under Contract No. HR0011-07-3-0002 awarded by DARPA. The U.S. Government has certain rights in this invention.


FIELD OF THE DISCLOSURE
The present disclosure relates generally to switched capacitor type data sampling circuits and in particular to an offset cancellation technique for level-crossing based circuits used in switched capacitor type data sampling circuits.
BACKGROUND
Conventionally, an operational amplifier (op-amp) is used for accurate charge transfer in switched capacitor circuits. The op-amp has differential inputs and an output. In operation, the op-amp senses the voltage difference at the differential inputs, and drives an output node continuously with its output to achieve a virtual ground condition at the differential inputs. As long as high-gain and wide-bandwidth op-amps are available this method is accurate and robust. However, it is relatively difficult to make power efficient, high-gain, and wide-bandwidth op-amps in nano-scale complementary metal oxide semiconductor (CMOS) technology.
A related art zero-crossing based circuit technique replaces the op-amp with a zero-crossing detector and a current source. FIG. 1A is a schematic of an exemplary related art zero-crossing detector based circuit 10. The circuit 10 includes a zero-crossing detector ZCD1 and a current source 12 that supplies a current I1. The circuit 10 also includes switches S1, S2, S3, S4, S5, S6, and S7 along with capacitors C1, C2, and C3. A switch controller (not shown) controls the opening and closing of switches S1 through S6. The switch S7 is opened and closed in response to the output state of the zero-crossing detector ZCD1.
FIG. 1B is a series of graphs depicting switching phases φ1, φ2, φp, and φ2e, along with an output voltage Vout, and a virtual ground node voltage VX for the circuit 10 (FIG. 1A). In operation, the circuit 10 samples an input signal (Vin) that is applied to the capacitor C1 by closing switches S1 and S3. Switches S2 and S4 are open during this sampling period. This sampling step is similar to a sampling step used in the operation of traditional op-amp based switched capacitor circuits. Optionally, the switch S6 may be closed during the sampling period to ensure that the output voltage Vout is at ground potential (GND). After the sampling period, the capacitor C1 and the second capacitor C2 are selectably coupled to a virtual ground node 14 that includes an input of the zero-crossing detector ZCD1 by closing the switches S2 and S4. As a result, a charge accumulated by the capacitor C1 from Vin is transferred to the second capacitor C2. The charge transfer starts in response to the preset phase φp, which initializes the output voltage Vout to GND via the switch S6. After the preset phase φp concludes, the current source 12 begins charging the output capacitor C3 with the current I1. The zero-crossing detector ZCD1 monitors the virtual ground node 14, while the current I1 is charging the output capacitor C3. The zero-crossing detector ZCD1 detects the instant of the zero-crossing of the virtual ground node voltage Vx, and opens the switch S7 coupled to a terminal node 16. As such, the voltage Vout and the virtual ground node voltage Vx increase linearly in time and stop once a virtual ground condition Vcm (common mode voltage) is met. The circuit 10 is power efficient because the zero-crossing detector ZCD1 is significantly more power efficient than a high-gain wide-bandwidth op-amp typically used in circuits having the same function as circuit 10. Moreover, the circuit 10 eliminates stability issues, due to semi-open loop operation.
FIG. 2A is a schematic of a modified version of the related art zero-crossing detector circuit 10 of FIG. 1A having a reversed direction current source. For example, charge transfer operations of zero-crossing based circuits can be done in an opposite direction of the current source 10 shown in FIG. 1A. A configuration for an opposite output charging direction is depicted in FIG. 2A. In this case, the output voltage Vout is initialized to a supply voltage VDD instead of GND during the preset phase (φp) by the preset switch S6. In this configuration the preset switch S6 is coupled between a source of the supply voltage VDD and a node between the switch S5 and a first terminal of the capacitor C3. In operation, the zero-crossing detector ZCD1 monitors the zero crossing at the input of the zero-crossing detector ZCD1 while the current source 12 discharges the output voltage Vout via the current I1. FIG. 2B shows a similar operation to FIG. 1B except that the direction of change for the output voltage Vout and the virtual ground node voltage Vx are reversed with those shown in FIG. 1B. It may be necessary to switch the two inputs of the zero-crossing detector ZCD1 in cases where a same version of zero-crossing detector ZCD1 is reused in circuit 10 of FIG. 2A.
For the following discussion FIG. 3A is a schematic reproduction of the related art zero-crossing detector circuit of FIG. 1. The operation aspects of the circuit 10 of FIG. 1A and FIG. 2A are described as ideal operations. In practical terms, the response time between a zero-crossing detection and an output change of the zero-crossing detector 10 and a corresponding switch transition for the switch S7 is not instantaneous. Instead, there is a finite delay (td) in turning off the switch S7 after a zero-crossing at the input of the zero-crossing detector ZCD1.
FIG. 3B is a series of graphs depicting switching phases φ1, φ2, φp, and φ2e, along with an output voltage Vout, a virtual ground node voltage VX and an offset caused by the delay td of the circuit 10 of FIG. 3A. Due to the delay td, the virtual ground node voltage Vx overshoots an ideal voltage by a voltage overshoot Vxover given by




  
    
      
        
          
            V
            xover
          
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              d
            
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                  V
                  x
                
              
              
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                t
              
            
          
        
        ,
      
    
    
      
        (
        1
        )
      
    
  




which leads to an offset voltage Voffset in the output voltage Vout. The voltage offset Voffset is given by





  
    
      
        
          V
          offset
        
        =
        
          
            t
            d
          
          ·
          
            
              
                d
                Vout
              
              
                d
                t
              
            
            .
          
        
      
    
    
      
        (
        2
        )
      
    
  




Therefore, a final output voltage Vfinal is given by

Vfinal=Vsignal+Voffset,  (3)

wherein the signal voltage Vsignal equals an ideal output voltage.

Related art techniques address the inaccuracy due to the virtual ground node voltage Vx overshoot and the resulting offset voltage Voffset by implementing a coarse charge transfer phase followed by a fine charge transfer phase. The goal of this dual phase charge transfer is to reduce the ramp rate right before the zero-crossing detector ZCD1 detects a zero-crossing. In this regard and as shown in FIG. 4A, one related art modification adds a current control 18.
As shown in FIG. 4B, a charge transfer begins with a coarse charging phase (φc), wherein the current source 12 in response to the current control 18 charges the capacitor C3 relatively quickly via a relatively high current ramp of the current I1. While the current source 12 charges the capacitor C3, the zero-crossing detector ZCD1 detects when the virtual ground node voltage Vx reaches a predetermined voltage level Vclose that is relatively close to the virtual ground condition Vcm. Once the virtual ground node voltage Vx reaches the predetermined voltage level Vclose, the current control 18 significantly reduces the relatively high current ramp of the current I1, thereby replacing the coarse charging phase φc with a fine charging phase φf. The resulting offset voltage Voffset is relatively lower, which results in a relatively greater accuracy of charge transfer to the capacitor C2 and higher accuracy of the output voltage on the capacitor C3. The fine charging phase ends when the virtual ground node voltage Vx crosses the virtual ground condition Vcm. The charge accumulated by the capacitor C3 is sampled by a following sampling stage (not shown). While the modified circuit 10 of FIG. 4 provides improved accuracy, a small but significant error in the output voltage Vout remains due to the smaller but still significant offset voltage Voffset.
Additional related art techniques to compensate for the offset voltage Voffset include employing a programmable offset in the zero-crossing detector ZCD1 and/or coupling a small capacitor array (not shown) to the virtual ground node 14 to cancel the offset voltage Voffset. However, after considering temperature and process variations, these related art techniques are relatively impractical. What is needed is a level-crossing based circuit and method that provides cancellation of offset voltage and tracking of the offset variation with efficiencies in power consumption and die area.
SUMMARY
The present disclosure provides a level-crossing based circuit with offset voltage cancellation and includes a first level-crossing detector section having a first output capacitor, wherein the first level-crossing detector section is configured to charge the first output capacitor to a first voltage corresponding to an input signal. The first voltage includes a first offset voltage. The level-crossing based circuit also includes a second level-crossing detector section having a second output capacitor, wherein the second level-crossing detector section is configured to discharge the second output capacitor to a second voltage corresponding to the input signal, wherein the second voltage includes a second offset voltage that is substantially equal in magnitude to the first offset voltage, but is opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.
Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
FIG. 1A is a schematic of a related art zero-crossing detector circuit.
FIG. 1B is a series of graphs depicting switching phases, an output voltage, and a virtual ground node voltage for the related art zero-crossing detector circuit of FIG. 1A.
FIG. 2A is a schematic of a modified version of the related art zero-crossing detector circuit of FIG. 1A having a reversed direction current source.
FIG. 2B is a series of graphs depicting switching phases, an output voltage, and a virtual ground node voltage for the related art zero-crossing detector circuit of FIG. 2A.
FIG. 3A is a schematic reproduction of the related art zero-crossing detector circuit of FIG. 1.
FIG. 3B is a series of graphs depicting switching phases, an output voltage, a virtual ground node voltage, and an offset caused by a delay of the related art zero-crossing detector circuit of FIG. 3A.
FIG. 4A is a schematic of a related art zero-crossing based circuit for demonstrating a dual phase charge transfer scheme for accurate operation of zero-crossing based circuits.
FIG. 4B is a series of graphs depicting switching phases including a phase controlling charge transfer, an output voltage, a virtual ground node voltage, and an offset caused by a delay of the related art zero-crossing detector circuit of FIG. 4A.
FIG. 5A is a schematic of an embodiment of a level-crossing based circuit that employs a dual phase charge transfer in accordance with the present disclosure.
FIG. 5B is a series of graphs depicting switching phases, output voltages, and virtual ground node voltages for the embodiment of the zero-crossing detector circuit of FIG. 5A.
FIG. 6A is a schematic of the embodiment of the level-crossing based circuit of FIG. 5A depicting a current flow through a voltage reference during a fine phase for offset correction.
FIG. 6B is a series of graphs depicting switching phases, output voltages, and virtual ground node voltages for the embodiment of the level-crossing based circuit of FIG. 6A during offset cancellation.



DETAILED DESCRIPTION
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
The present disclosure provides a level-crossing based circuit and method that provides cancellation of offset voltage and tracking of the offset variation with efficiencies in power consumption and die area. FIG. 5A is a schematic of an embodiment of a level-crossing based circuit 20 that employs a dual phase charge transfer in accordance with the present disclosure. The level-crossing based circuit 20 has a first level-crossing detector section 22 and a second level-crossing detector section 24.
The first level-crossing detector section 22 includes switches S1a, S2a, S3a, S4a, S5a, S6a, and S7a, along with capacitors C1a, C2a, and C3a. Also included in the first level-crossing detector section 22 are a first zero-crossing detector ZCD1 and a current source 26. The switches S1a-S4a together with the capacitor C1a make up a first switched capacitor network having a first sampling input terminal 28 and a first sampling output terminal 30. The first sampling input terminal 28 is coupled to a signal input terminal 32 that receives an input signal Vin. The switch S1a acts as a sampling switch during a sampling phase φ1 as shown in FIG. 5B. During a sampling phase φ1, the switch S3a is closed so that the capacitor C1a can be charged with a sample voltage corresponding to the input signal Vin.
The capacitor C2a acts as a charge transfer capacitor when capacitor C1a is selectively coupled to capacitor C2a via switch S4a. The first zero-crossing detector ZCD1 has a first virtual ground node input 34 that is coupled to the first sampling output terminal 30. A first common mode input 36 of the first zero-crossing detector ZCD1 is coupled to a common node 38 that is at a common mode voltage Vcm, wherein Vcm is typically at ground potential. The first zero-crossing detector ZCD1 further includes a first detector output 40 that is controllably coupled to the switch S7a, which is coupled between a first terminal node 42 and the common node 38. The capacitor C3a is coupled between the first terminal node 42 and a first output node 44.
As shown in FIG. 5B, a control signal φ2ea selectively closes and opens the switch S7a to first allow charging of the capacitor C3a with the current I1a that is sourced by the first current source 26. The switch phases φ1, φ2, and φp apply to switches S1a-S6a and S1b-S6b. Therefore, FIG. 5 refers to these switches generically as switches S1-S6. A control signal φp momentarily closes switch S6a at the beginning of the control signal φ2ea to preset the charge stored by the capacitor C3a to zero. Note that a switch phase φ2 closes the switches S2a, S4a and S5a during the charging phase φ2ea. As a result, the capacitor C3a provides a first output voltage Vouta at the first output node 44 after the zero-crossing detector ZCD1 detects that a first voltage sample Vxa of the input signal on the first virtual ground node input 34 exceeds the common mode voltage Vcm. The first output voltage Vouta at the first output node 44 includes a first offset voltage Voffseta due to an overshoot of the voltage Vxa caused by a delay td in turning off the switch S7a.
The second level-crossing detector section 24 includes switches S1b, S2b, S3b, S4b, S5b, S6b, and S7b, along with capacitors C1b, C2b, and C3b. Also included in the second level-crossing detector section 24 are a second zero-crossing detector ZCD2 and a second current source 46. As disclosed below, the second level-crossing detector section 24 is configured to discharge the capacitor C3b to a second output voltage Voutb such that the second output voltage Voutb includes a second offset voltage Voffsetb that is substantially equal in magnitude and opposite in polarity to the first offset voltage Voffseta relative to an average of the first output voltage Vouta and the second output voltage Voutb, which as shown in FIG. 5b is Vout(n).
The switches S1b-S4b together with the capacitor C1b make up a second switched capacitor network having a second sampling input terminal 48 and a second sampling output terminal 50. The second sampling input terminal 48 is coupled to the signal input terminal 32 that receives the input signal Vin. The switch S1b acts as a sampling switch during a sampling phase φ1 as shown in FIG. 5B. During the sampling phase φ1, the switch S3b is closed so that the capacitor C1b can be charged with a sample voltage corresponding to the input signal Vin.
The capacitor C2b acts as a charge transfer capacitor when C1b is selectively coupled to C2b via switch S4b. The second zero-crossing detector ZCD2 has a second virtual ground node input 52 that is coupled to the second sampling output terminal 50. A second common mode input 54 of the second zero-crossing detector ZCD2 is coupled to the common node 38 that is at a common mode voltage Vcm, wherein Vcm is typically at ground potential. The second zero-crossing detector ZCD2 further includes a first detector output 46 that is controllably coupled to the switch S7b, which is coupled between a second terminal node 58 and the common node 38. The capacitor C3b is coupled between the second terminal node 58 and a second output node 60.
As shown in FIG. 5B, a control signal φ2eb selectively closes and opens the switch S7b to allow discharging of the capacitor C3b with the current I1b that is sourced by the second current source 46. The control signal φp momentarily closes switch S6b at the beginning of the control signal φ2eb to preset the charge stored by the capacitor C3b to a supply voltage VDD. Note that the switch phase φ2 closes the switches S2b, S4b, and S5b during the discharging phase φ2eb. As a result, the capacitor C3b provides an output voltage Voutb at the second output node 60 after the second zero-crossing detector ZCD2 detects that a second voltage sample Vxb of the input signal on the second virtual ground node input 52 falls below the common mode voltage Vcm.
FIG. 6A is a schematic of a modified embodiment of the level-crossing based circuit 20 of FIG. 5A depicting a current flow through a voltage reference 62 during a fine phase for offset correction. The voltage reference 62 provides a low impedance sink for the first current I1a and an additional low impedance source for the second current I1b. As a result, the voltage reference 62 improves the accuracy of the first output voltage Vouta and the second output voltage Voutb by balancing any mismatches between the first current I1a and the second current I1b. Interestingly, the currents I1a and I1b sourced by the first current source 26 and the second current source 46 substantially cancel while passing inside the voltage reference 62. As such, the current rating specification for the voltage reference 62 can be relaxed.
FIG. 6B is a series of graphs depicting switching phases, output voltages, and virtual ground node voltages for the embodiment of the level-crossing based circuit 20 of FIG. 6A during offset cancellation. In operation, the capacitor C3a functioning as a first output capacitor is initiated to zero volts by the preset phase φp via the switch S6a, and is then charged linearly during a coarse phase φca at a relatively high rate with the current I1a sourced by the first current source 26. The capacitor C3b functioning as a second output capacitor is initialized to a voltage VDD during the preset φp via the switch S6b, and is then discharged linearly during a coarse phase φcb at a relatively high rate by the current I1b sourced by the second current source 46. Since the coarse phase φca and the coarse phase φcb start with different voltages for the capacitors C3a and C3b, but arrive at about the same voltage level, either the coarse phase φca or the coarse phase φcb will finish first depending on the voltage level of the input signal Vin. As a result, either the coarse phase φca will wait for the coarse phase φcb to finish or the coarse phase φcb will wait for the coarse phase φca to finish before starting a fine phase that significantly reduces the charging current I1a and that simultaneously reduces the discharging current I1b. Completion of the fine phase results in a relatively smaller offset voltage Voffseta and a relatively smaller offset voltage Voffsetb in comparison to the operation of the level-crossing based circuit 20 of FIG. 5A. As a result, the modified operation of the modified version of the level-crossing based circuit 20 of FIG. 6A is comparatively more accurate. An average of the first output voltage Vouta and the second output voltage Voutb, results in the desired output voltage Vout(n). It is to be understood that a variety of traditional averaging circuits (not shown) can be employed as a following stage to average the first output voltage Vouta and the second output voltage Voutb together.
Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

## Claims

1. A level-crossing based circuit with offset voltage cancellation comprising:
a first level-crossing detector section having a first output capacitor, and being configured to charge the first output capacitor to a first voltage corresponding to a single input signal, wherein the first voltage includes a first offset voltage; and
a second level-crossing detector section having a second output capacitor, and being configured to discharge the second output capacitor to a second voltage corresponding to the input signal such that the second voltage includes a second offset voltage that is substantially equal in magnitude to the first offset voltage and opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.

2. The level-crossing based circuit of claim 1 wherein the first level-crossing detector section comprises:
a first zero-crossing detector having a first virtual ground node input, a first common mode input, and a first zero-crossing detector output; and
a first output switch coupled to the first output capacitor to selectively interrupt the charging of the first output capacitor once a first voltage sample of the input signal on the first virtual ground node input exceeds a common mode voltage on the first common mode input and wherein the first output switch is controllably coupled to the first zero-crossing detector output.

3. The level-crossing based circuit of claim 2 wherein the second level-crossing detector section comprises:
a second zero-crossing detector having a second virtual ground node input, a second common mode input, and a second zero-crossing detector output; and
a second output switch coupled to the second output capacitor to selectively interrupt the charging of the second output capacitor once a second voltage sample of the input signal on the second virtual ground node input falls below a common mode voltage on the second common mode input and wherein the second output switch is controllably coupled to the second zero-crossing detector output.

4. The level-crossing based circuit of claim 1 further including a first current source configured to linearly charge the first output capacitor, and a second current source to linearly discharge the second output capacitor.

5. The level-crossing based circuit of claim 4 wherein the first current source and the second current source are configured to source current at a first relatively high rate and a second relatively low rate.

6. The level-crossing based circuit of claim 5 further including a voltage reference communicably coupled between the first level-crossing detector section and the second level-crossing detector section to control portions of currents sourced by the first current source and the second current source while the first current source and the second current source are sourcing current at the second relatively low rate.

7. The level-crossing based circuit of claim 6 wherein the currents sourced by the first current source and the second current source substantially cancel while passing inside the voltage reference.

8. A method of offset cancellation for a level-crossing based circuit having a first output capacitor and a second output capacitor, the method comprising:
charging the first output capacitor to a first voltage corresponding to a single input signal, wherein the first voltage includes a first offset voltage; and
discharging the second output capacitor to a second voltage corresponding to the input signal such that the second voltage includes a second offset voltage that is substantially equal to the first offset voltage and opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.

9. The method of claim 8 wherein the charging of the first output capacitor and the discharging of the second output capacitor are performed linearly.

10. The method of claim 9 wherein the charging of the first output capacitor occurs at a first relatively high rate and then at a second relatively low rate as the first voltage approaches a first sample voltage corresponding to the input signal.

11. The method of claim 9 wherein the discharging of the second output capacitor occurs at a first relatively high rate and then at a second relatively low rate as the first voltage approaches a second sample voltage corresponding to the input signal.

12. A level-crossing based circuit comprising:
a signal input terminal;
a first switched capacitor sampling network having a first sampling input terminal coupled to the signal input terminal and a first sampling output terminal;
a first level-crossing detector having a first virtual ground node input coupled to the first sampling output terminal, a first common mode input, and a first level-crossing detector output;
a first output capacitor for providing a first output voltage;
a first current source configured to charge the first output capacitor;
a first output switch coupled to the first output capacitor to selectively interrupt the charging of the first output capacitor once a first voltage sample of a single input signal on the first virtual ground node input exceeds a common mode voltage on the first common mode input and wherein the first output switch is controllably coupled to the first level-crossing detector output;
a second switched capacitor sampling network having a second sampling input terminal coupled to the signal input terminal and a second sampling output terminal;
a second level-crossing detector having a second virtual ground node input coupled to the second sampling output terminal, a second common mode input and a second level-crossing detector output;
a second output capacitor for providing a second output voltage;
a second current source configured to discharge the second output capacitor; and
a second output switch coupled to the second output capacitor to selectively interrupt the discharging of the second output capacitor once a second voltage sample of the input signal on the first virtual ground node input drops below a common mode voltage on the second common mode input and wherein the second output switch is controllably coupled to the second level-crossing detector output.

13. The level-crossing based circuit of claim 12 wherein the second level-crossing detector is configured to discharge the second output capacitor to the second output voltage such that the second output voltage includes a second offset voltage that is substantially equal in magnitude to a first offset voltage of the first output voltage and opposite in polarity to the first offset voltage relative to an average of the first output voltage and the second output voltage.

14. The level-crossing based circuit of claim 12 wherein the first level-crossing detector and the second level-crossing detector are zero-crossing detectors.

15. The level-crossing based circuit of claim 12 wherein the first current source and the second current source are configured to source current at a first relatively high rate and a second relatively low rate.

16. The level-crossing based circuit of claim 15 further including a voltage reference communicably coupled between the first sampling input terminal and the second sampling input terminal to control portions of currents sourced by the first current source and the second current source while the first current source and the second current source are sourcing current at the second relatively low rate.

17. The level-crossing based circuit of claim 16 wherein the currents sourced by the first current source and the second current source substantially cancel while passing inside the voltage reference.

18. The level-crossing based circuit of claim 15 wherein the first level-crossing detector controls the first current source to transition from the first relatively high rate of sourcing current to the second relatively low rate of sourcing current as the first voltage sample of the input signal on the first virtual ground node input approaches near below the common mode voltage.

19. The level-crossing based circuit of claim 15 wherein the second level-crossing detector controls the second current source to transition from the first relatively high rate of sourcing current to the second relatively low rate of sourcing current as the second voltage sample of the input signal on the first virtual ground node input approaches near above the common mode voltage.

20. The level-crossing based circuit of claim 12 wherein the first level-crossing detector and the second level-crossing detector are implemented as nano-scale complementary metal oxide semiconductor (CMOS) technology.