# Patent

## Title
Generating a root of an open-loop freqency response that tracks an opposite root of the frequency response

## Abstract

In an embodiment, an electronic includes a feedback-coupled circuit stage and a compensation circuit stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that a combination of the compensation and feedback-coupled stages has a frequency response including a first root and an opposite second root that depend on the load. For example, an embodiment of such an electronic circuit may be a low-dropout (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator. The regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that is designed such that the frequency response of the regulator includes a zero that tracks a non-dominant output pole of the regulator so that the output pole does not adversely affect the stability of the regulator.

## Background
SUMMARY
In an embodiment, an electronic circuit includes a feedback-coupled stage and a compensation stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that the circuit, which is a combination of the compensation and feedback-coupled stages, has a transfer function, i.e., a frequency response, including a first root and an opposite second root that depend on the load.
An embodiment of such an electronic circuit may be a low-drop-out (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator; for example, such an LDO voltage regulator may be an on-chip circuit that generates a voltage for one of multiple separate voltage islands inside a system on a chip (SOC), where including such a large output capacitance may be impractical. The LDO regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that imparts to the frequency response of the regulator a zero that tracks a non-dominant output pole of the regulator's frequency response so that the output pole does not degrade the stability of the regulator, particularly at lighter loads that draw lower load currents. Furthermore, the compensation stage may also impart to the frequency response of the regulator a dominant pole that stays within a relatively small frequency range over a relatively large range of load levels.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a LDO voltage regulator.
FIG. 2 is a diagram of a system that includes circuit islands each having a respective LDO voltage regulator, according to an embodiment.
FIG. 3 is a diagram of a load, and of a circuit that includes a feedback-coupled stage configured to drive the load and a compensation stage configured to stabilize the circuit, according to an embodiment.
FIG. 4 is a schematic diagram of a load, and of a LDO voltage regulator that is an implementation of the circuit of FIG. 3 and that is configured to provide a regulated supply voltage to the load, according to an embodiment.
FIG. 5 is a circuit model of the load and of the LDO voltage regulator of FIG. 4, according to an embodiment.
FIG. 6 is a plot of the output pole and the tracking zero of the LDO voltage regulator of FIG. 4 versus frequency, according to an embodiment.
FIG. 7 is a Bode plot of the open-loop magnitude and phase of the LDO voltage regulator of FIG. 4 at two different load currents, according to an embodiment.
FIG. 8 is a diagram of a system that may incorporate the circuit of FIG. 3, for example, in the form of the LDO voltage regulator of FIG. 4, according to an embodiment.



DETAILED DESCRIPTION
FIG. 1 is a schematic diagram of a LDO voltage regulator 10, which is configured to provide a regulated output voltage Vout to a load, which is modeled as a resistor RLoad. Although the load may be described as being a resistive load RLoad, the load may also have a reactive component such as a capacitive component Cout as shown in FIG. 1. Cout may represent only the capacitance of the load, or it may represent the combination of the load capacitance and a separate output capacitance that is in parallel with the load.
The LDO regulator 10 includes a high-gain amplifier 12, a PMOS pass transistor 14, a voltage divider 16 including resistors R1 and R2, and an output capacitor Cout—if the load has a capacitive component, then the capacitance of this component may be accounted for in the value of Cout as described above. The amplifier 12 includes an inverting node “−” coupled to receive a stable (e.g., a band-gap) reference voltage Vref, and includes a non-inverting node “+” coupled to receive a feedback voltage VFB from the junction of the resistors R1 and R2. The PMOS transistor 14 has a source coupled to receive an input voltage VDD—LDO, a drain coupled to provide Vout, and a gate coupled to the output node of the amplifier 12.
In operation, the amplifier 12 controls the conductance of the PMOS pass transistor 14 so as to regulate Vout to a particular voltage (e.g., 1.3 Volts (V)) by maintaining VFB equal to Vref, at least within a tolerance dictated, at least in part, by the input offset error and gain of the amplifier. Because the PMOS transistor 14 can conduct a current even while its source-drain voltage is relatively low, the regulator 10 can generate Vout to have a magnitude that is almost equal to the magnitude of VDD—LDO. For example, depending on the value of the effective load resistance RLoad, and, therefore, depending on the level of the load current ILOAD, the regulator 10 may be able to generate Vout=1.3 V from a value of VDD—LDO as low as 1.4 V. That is, the regulator 10 can operate properly even when the “head room” between VDD—LDO and Vout is relatively low; hence, the term “low-drop-out regulator.” Consequently, the LDO regulator 10 may be best suited for applications in which the difference between VDD—LDO and Vout is 1.0 V or less.
Still referring to FIG. 1, the output capacitor Cout typically serves at least two functions.
A first function of Cout is to act as a bypass capacitor that can filter step changes in the load current ILoad. For example, Cout may provide an “injection” of current in response to a step, or otherwise sudden, increase in the load current ILoad until the regulation feedback loop, which includes of the voltage divider 16, the amplifier 12, and the PMOS transistor 14, responds to this increase by increasing the current through the PMOS transistor. For example, where the load is a microprocessor, such a step increase in ILoad may be caused by the microprocessor transitioning from a “sleep” mode to an “awake” mode. Similarly, Cout may absorb an injection of current in response to a step, or otherwise sudden, decrease in ILoad until the regulation feedback loop responds to this decrease by decreasing the current through the PMOS transistor. For example, where the load is a microprocessor, such a step decrease in ILoad may be caused by the microprocessor transitioning from an “awake” mode to a “sleep” mode.
And a second function of Cout is to form a lowest, i.e., dominant, pole of the regulator's frequency response such that the LDO regulator 10 is stable (i.e., does not oscillate or generate excessive “ringing” on the output voltage Vout). That is, in general, Cout, along with RLoad, R1, R2, and the output resistance and output conductance of the PMOS transistor 14, form a pole that is low enough in frequency such that the open-loop gain of the LDO regulator 10 is less than unity at frequencies at which the open-loop phase of the LDO regulator is greater than or equal to 180°, and such that the open-loop phase of the LDO regulator is less than 180° at frequencies at which the open-loop gain of the LDO regulator is greater than or equal to unity. Although the frequency of this dominant pole may shift with changes in RLOAD, and, therefore, with changes in ILOAD, a circuit designer typically makes COUT large enough, and, therefore, makes the dominant pole small enough, so that the LDO regulator 10 remains stable even when such load-induced shifts in the dominant pole's frequency occur.
A value of capacitance that allows Cout to serve both of the above-described first and second functions, at least in some applications, is a value that lies within an approximate range of 100 nanofarads (nF)-10 microfarads (μF).
But unfortunately, as described below in conjunction with FIG. 2, having a capacitance value within this range may render Cout unsuitable for at least some other applications.
FIG. 2 is a block diagram of a system on a chip (SOC) 20, according to an embodiment.
The SOC 20 includes a main power supply 22, circuit islands (also called “power islands” or “voltage islands”) 24, and LDO voltage regulators 26. The main power supply 22 may include a conventional power supply, such as a multiphase switching power supply.
In operation, the main power supply 22 receives an external supply voltage Vsupply, and generates therefrom a regulated internal supply voltage VDD—LDO. For example, Vsupply may equal 5.0 V, and VDD—LDO may equal 1.80 V.
Each LDO voltage regulator 26 converts VDD—LDO into a respective supply voltage for the respective circuit island 24 on which the LDO regulator is located. For example, VDD—LDO may equal 1.80 V, and one or more of the LDO voltage regulators 26 may each convert VDD—LDO into a respective island supply voltage equal to 1.30 V.
Because there are multiple LDO voltage regulators 26 on the SOC 20, it typically would be impractical or impossible to include, on the SOC, a respective output capacitor having the size (e.g., 100 nF-10 μF) of the output capacitor Cout of FIG. 1 for each LDO regulator. Reasons for this include that it may be difficult to integrate on an integrated circuit capacitors having such a large capacitance, and, that even if one could integrate such capacitors, the SOC 20 may be too small to include such an integrated capacitor for each circuit island 24.
Furthermore, it may be impractical to include such output capacitors on a printed circuit board to which the SOC 20 is mounted, because the board may not have enough room to accommodate a respective output capacitor for each LDO voltage regulator 26.
Therefore, there is a need for a circuit topology that allows stabilizing a feedback-coupled circuit (or circuit stage), such as an LDO voltage regulator, over a relatively large range of load levels without a relatively large output capacitor.
FIG. 3 is a diagram of a load 30 and a circuit 32 for providing a signal Sout to the load, where the circuit stable over a relatively large range of load levels without the presence of a relatively large output capacitor.
The circuit 32 includes a feedback-coupled stage 34 and a compensation stage 36 coupled to the feedback-coupled stage; that is, the circuit 32 may be considered to be a combination of the feedback-coupled and compensation stages.
The feedback-coupled stage 34 includes an input stage 38 and an output stage 40. The input stage 38 is configured to receive an input signal SIN and a feedback signal SFB, and to generate an intermediate signal SINT in response to SIN and SFB. For example, the input stage 38 may include a high-gain differential amplifier (not shown in FIG. 3) that generates SINT so as to cause SFB to approximately equal SIN. The output stage 40 is configured to receive SINT from the input stage 38, and to generate SFB and an output signal SOUT, which has a voltage component VOUT and a current component IOUT—although not shown in FIG. 3, the other signals SIN, SINT, and SFB also have respective voltage and current components. Although IOUT is shown as being equal to ILOAD, in another embodiment IOUT may not be equal to ILOAD.
Because the feedback-coupled stage 34 includes a negative-feedback topology in which the output stage 40 feeds back the signal SFB to the input stage 38, the feedback-coupled stage may be unstable if the input and output stages are not frequency compensated properly. Such instability may manifest itself, for example, in “ringing” (i.e., damped oscillations) superimposed on VOUT, or in oscillation of VOUT.
Because a pole or a zero of the feedback-coupled stage 34 may change as the load 30 changes, proper frequency compensation should encompass at least the entire anticipated range of the load for a particular application.
For example, as described above in conjunction with FIG. 2, when it is an output pole that may change as the load 30 changes, one way to provide such proper frequency compensation is to include a large output capacitor at an output node 42 of the output stage 40.
But as also described above, a large output capacitor may be unsuitable for some applications of the feedback-coupled stage 34, such as an application in which multiple feedback-coupled stages are integrated on a single integrated-circuit die.
Therefore, the compensation stage 36 is added to the circuit 32, and is configured to impart proper frequency compensation to the circuit throughout the entire anticipated range of the load 30 without a large output capacitor.
For purposes of explanation, assume that the circuit 32 has a transfer function, i.e., a frequency response, that includes a dominant, lower-frequency pole that, by itself, would cause the circuit to operate stably, and that includes an output pole that is at a higher frequency than the dominant pole but that is dependent on, i.e., shifts with changes in, the load 30; for example, the output pole may increase as the load current ILOAD increases, and may decrease as ILOAD decreases. Therefore, at one or more levels of the load 30, the output pole may be close enough to the dominant pole to cause the circuit 32 to be unstable. For example, at relatively low levels of the load current ILOAD, the load-current-dependent output pole may be close enough to the dominant pole to cause the open-loop phase shift of the circuit 32 to equal or exceed 180° while the open-loop gain of the circuit is greater than or equal to unity, thus causing the circuit to oscillate. But even if the output pole does not cause the open-loop phase shift to equal or exceed 180° while the open-loop gain is greater than or equal to unity, the output pole may still be close enough to the dominant pole to cause ringing on VOUT. And even if the output pole does not cause VOUT to ring, it may reduce the phase margin or gain margin of the circuit 32 to a level that puts the circuit in danger of becoming unstable if one or more other parameters (e.g., temperature, process, voltage) differ from their nominal values.
But the compensation stage 36 stabilizes the circuit 32 by introducing a zero to the circuit's frequency response, where the zero tracks and fully cancels the output pole, or tracks and at least mitigates the negative affect that the output pole would otherwise have on the dominant pole as described in the preceding paragraph. It is known that if a circuit has a frequency response with a pole and a zero at the same frequency, then the pole and zero fully cancel each other such that it is as if the frequency response has neither a pole nor a zero at the frequency. But even if the pole and zero are not at exactly the same frequency, then the pole and zero may partially cancel each other if their frequencies are relatively close to each other. Therefore, the zero that the compensation stage 36 introduces into the frequency response of the circuit 32 may track the output pole exactly so as to fully cancel the output pole, or may track the output pole inexactly, but closely enough such that the output pole does not cause the circuit to be unstable for at least any level of the load 30 that falls within an anticipated range load levels.
Still referring to FIG. 3, in more general terms, because a pole and a zero are roots of the denominator and numerator, respectively, of a characteristic equation that represents the frequency response of the circuit 32, it can be said that the compensation stage 36 is configured to introduce into the circuit's frequency response a first numerator or denominator root that tracks, and partially or fully cancels, a second denominator or numerator root so as to stabilize the circuit over a range of at least one variable parameter (e.g., a load) on which the second root depends. That is, the compensation stage 36 may introduce into the frequency response of the circuit 32 a zero that tracks, and that partially or fully cancels, a pole that depends on a varying parameter, or may introduce into the frequency response a pole that tracks, and that partially or fully cancels, a zero that depends on a varying parameter. At least for purposes of this disclosure, a numerator root (i.e., a zero) may be referred to as being an “opposite” (or another form or a synonym of “opposite”) root to a denominator root (i.e., a pole), and a denominator root (i.e., a pole) may be referred to as being an “opposite” (or another form or a synonym of “opposite”) root to a numerator root (i.e., a zero). That is, for example, “a first root and an opposite second root” may refer to a first root that is a pole and a second root that is a zero, or to a first root that is a zero and a second root that is a pole. And, for example, “a first root and a second root” may refer to a first root that is a zero and a second root that is a zero, to a first root that is a zero and a second root that is a pole, to a first root that is a pole and a second root that is a zero, and to a first root that is a pole and a second root that is a pole.
Consequently, the compensation stage 36 may be added to any feedback-coupled stage, such as the feedback-coupled stage 34, to form a feedback-coupled circuit in which a root of the circuit's frequency response is tracked, and partially or fully cancelled, by an opposite root of the circuit's frequency response so as to stabilize the circuit or to impart another characteristic to the circuit.
Still referring to FIG. 3, other embodiments of the feedback-coupled circuit 32 are contemplated. For example, the feedback-coupled stage 34 may include stages in addition to, or in place of, one or both of the input and output stages 38 and 40. Furthermore, the compensation stage 36 may be coupled to the feedback-coupled stage 34 in a manner other than the manner described.
FIG. 4 is a schematic diagram of an embodiment of the load 30 and of the feedback-coupled circuit 32 of FIG. 3; in the described embodiment, the feedback-coupled circuit is a LDO voltage regulator 50 that includes no large output capacitor but that is stable over a range of anticipated levels of the load. The regulator 50 may be formed from discrete components, integrated by itself on an integrated-circuit die, or integrated with other LDO voltage regulators or other circuits on an integrated-circuit die.
In addition to the load 30, which is modeled as a parallel combination of a load resistance RL and a load capacitance CL, the LDO voltage regulator 50 includes an input stage 52, an output stage 54, and a compensation stage 56.
The input stage 52 includes a high-gain differential amplifier 58, such as an operational amplifier, that includes an output resistance Ro, that is configured to receive a reference voltage VREF and a feedback voltage VFB, and that is configured to generate an intermediate voltage VINT.
The output stage 54 includes a drive transistor M6 that is configured to generate a current IOUT in response to the voltage VINT, a mirror transistor M5 that is configured to generate a feedback current IFB, a compensation capacitor C1, and a voltage divider 60 that includes series-coupled resistors R1, R2, and R3, which are configured to generate the feedback voltage VFB and another feedback voltage VFB—TRACK.
The compensation stage 56 includes a first node 62 configured to receive the voltage VINT, a second node 64 configured to receive the feedback current IFB, a third node 66 configured to receive the feedback voltage VFB—TRACK, a compensation capacitor CM coupled between the first and second nodes, and a network 68 that is configured to provide a variable resistance that tracks the load resistance RL. As further described below, the capacitor CM and the variable resistance form a zero that tracks, and at least partially cancels, an output pole of the LDO voltage regulator 50. Furthermore, as described below, the capacitor CM is also a factor in the dominant pole of the LDO voltage regulator 50.
The network 68 of the compensation stage 56 includes PMOS bias transistors M3 and M4, variable-transconductance PMOS transistors M1 and M2, which have their sources respectively coupled to the drains of the transistors M3 and M4 and their gates coupled to the third node 66, and a resistor R4 coupled between the sources of the transistors M3 and M4.
FIG. 5 is a diagram of a simplified circuit model of the load 30 and of the LDO voltage regulator 50 of FIG. 4.
The steady-state and output-root-tracking operations of the LDO voltage regulator 50 are now described in conjunction with FIGS. 4 and 5, where the root that is tracked is an output pole of the LDO regulator, and the opposite root that tracks the output pole is a zero of the LDO regulator.
During steady-state operation, the amplifier 58 generates the voltage VINT, which causes the transistor M6 to source the current IOUT.
A first portion of the current IOUT is the current ILOAD, which powers the load 30, and a second portion of the current IOUT flows through the voltage divider 60, which generates the feedback voltage VFB according to the following equation:




  
    
      
        
          V
          FB
        
        =
        
          
            V
            OUT
          
          ·
          
            
              
                R
                2
              
              +
              
                R
                3
              
            
            
              
                R
                1
              
              +
              
                R
                2
              
              +
              
                R
                3
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




The amplifier 58 receives VFB at its non-inverting input node, and generates VINT such that VFB equals (within the error tolerance of the amplifier) VREF, which the amplifier receives at its inverting input node and which is a stable reference voltage such as generated by a band gap voltage generator (not shown in FIGS. 4 and 5).
But as described above in conjunction with FIG. 3, as the load resistance RL changes (e.g., due to the load 30 “waking up” or “falling asleep”), an output pole POUT of the frequency response of the LDO voltage regulator 50 may change, and thus may cause the LDO regulator to become unstable such that, for example, VOUT exhibits ringing in response to transient changes in RL, or, in an extreme case, exhibits oscillation.
To prevent the LDO voltage regulator 50 from becoming unstable, the compensation stage 56 causes the regulator's frequency response to include a zero ZTRACK that tracks, and partially or fully cancels, the output pole POUT.
The output pole POUT increases as the load resistance RL decreases and, therefore, as the load current ILOAD increases, and POUT decreases as RL increases and, therefore, as ILOAD decreases; therefore, the output pole POUT is proportional to ILOAD and is inversely proportional to RL.
The network 68 of the compensation circuit 56 receives, via the node 64, the feedback current IFB, which is given by the following equation:

IFB=K1·IOUT  (2)

K1 of equation (2) is a constant that is, in an embodiment, less than one, and that is given by the following equation:




  
    
      
        
          K
          1
        
        =
        
          
            
              W
              5
            
            
              L
              5
            
          
          
            
              W
              6
            
            
              L
              6
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




where





  
    W
    5
  
  
    L
    5
  




is the width-to-length ratio of the transistor M5, and





  
    W
    6
  
  
    L
    6
  




is the width-to-length ratio of the transistor M6. Because IFB is proportional to IOUT per equation (2), and because IOUT is proportional to ILOAD and is inversely proportional to RL, then IFB is also proportional to ILOAD and inversely proportional to RL.

In response to a bias voltage VBIAS, the bias transistor M3 of the network 68 generates a bias current IB3 that flows through, and biases, the transistor M1; likewise, in response to VBIAS, the bias transistor M4 generates a bias current IB4 that flows through, and biases, the transistor M2. In an embodiment, the width-to-length ratio of M4 is less than the width-to-length ratio of M3 such that IB3>IB4.
And, as further described below, the transconductance gm1 of the transistor M1 is proportional to the source-to-drain current ISD1 that flows through the transistor M1; likewise, the transconductance gm2 of the transistor M2 is proportional to the source-to-drain current ISD2 that flows through the transistor M2. In an embodiment, the width-to-length ratio of the transistor M1 is greater than the width-to-length ratio of the transistor M2 such that ISD1>ISD2.
Because a first portion of the feedback current IFB flows through the transistor M1 such that this first portion of IFB is a component of the current ISD1, and because gm1 is proportional to ISD1, the transconductance gm1 of M1 is proportional to IFB, and is, therefore, proportional to ILOAD and inversely proportional to RL.
Furthermore, because 1/gm1 has units of ohms (Ω), the transistor M1 effectively functions as a variable resistance Rm1 that is proportional to the effective load resistance RL. That is, as RL increases, Rm1 increases, and as RL decreases, Rm1 decreases.
Similarly, because a second portion of the feedback current IFB flows through the resistor R4 and the transistor M2 such that this second portion of IFB is a component of the current ISD2, and because gm2 is proportional to ISD2, the transconductance gm2 of the transistor M2 is proportional to IFB, and is, therefore, proportional to ILOAD and inversely proportional to RL.
Furthermore, because 1/gm2 has units of Ω, the transistor M2 also effectively functions as a variable resistance Rm2 that is proportional to RL.
Moreover, because the width-to-length ratio of the transistor M2 is less than the width-to-length ratio of the transistor M1, the first portion of IFB that flows through the transistor M1 is greater than the second portion of IFB that flows through the resistor R4 and the transistor M2; therefore, for IFB>0, gm1 of M1 is greater than gm2 of M2, and, therefore, Rm1 of M1 is less than Rm2 of M2.
Consequently, the network 68 can be modeled as a variable resistance that is coupled between the node 64 and ground such that this variable resistance and the capacitor CM form the zero ZTRACK that tracks, and partially or fully cancels, the output pole POUT of the LDO regulator's frequency response. As described above, the frequency of the output pole POUT increases as the load current ILOAD increases and the effective load resistance RL decreases, and POUT decreases as ILOAD decreases and RL increases. Also as described above, the effective resistance Rm1 of the transistor M1 and the effective resistance Rm2 of the transistor M2 also decrease as ILOAD increases and RL decreases. Consequently, the frequency of the zero ZTRACK formed by the capacitor CM and the network 68 also increases as the frequency of the output pole POUT increases, and decreases as POUT decreases, such that ZTRACK tracks POUT. By selecting appropriate values for the width-to-length ratios




  
    
      W
      1
    
    
      L
      1
    
  
  ,
  
    
      W
      2
    
    
      L
      2
    
  
  ,
  
    
      W
      3
    
    
      L
      3
    
  
  ,
  
    
      W
      4
    
    
      L
      4
    
  
  ,
  
    
      W
      5
    
    
      L
      5
    
  
  ,
  
    and
    ⁢
    
      
    
    ⁢
    
      
        W
        6
      
      
        L
        6
      
    
  
  ,




and the resistors R1, R2, R3, and R4, a designer of the LDO voltage regulator 50 can design the zero ZTRACK to fully cancel the output pole POUT, or to partially cancel POUT to a desired degree.

Furthermore, the network 68 may be designed such that at lower values of ILOAD (and, therefore, at higher values of RL), the effective resistances Rm1 and Rm2 of the transistors M1 and M2 are relatively high such that R4 is the dominating resistance factor in the tracking zero ZTRACK. If the LDO voltage regulator 50 is integrated on a die and resistors R1, R2, R3, and R4 are polysilicon resistors, then this design strategy allows R4 to track R1, R2, and R3 over process, temperature, and voltage variations that may affect the values of these resistors when ILOAD is relatively low.
And the network 68 may also be designed such that at higher values of ILOAD (and, therefore, at lower values of RL), the effective resistance Rm1 of the transistor M1 is the dominant factor in the tracking zero ZTRACK such that ZTRACK increases as the output pole POUT increases, and decreases as POUT decreases, as described above.
FIG. 6 is a plot of the frequencies of output pole POUT and of the tracking zero ZTRACK of the LDO voltage regulator 50 of FIGS. 4 and 5, according to an embodiment. The plot shows that the zero ZTRACK tracks the output pole POUT over a relatively wide range of load current, from about ILOAD=0 milliamperes (mA) to at least about ILOAD=10 mA.
Referring again to FIGS. 4 and 5, the compensation stage 56 may also cause the frequency response of the LDO voltage regulator 50 to have a dominant pole PDOMINANT having a frequency that is lower than the frequency of POUT and that is relatively constant over a relatively wide range of ILOAD; PDOMINANT having a relatively constant frequency over the anticipated range of ILOAD allows the frequency response of the LDO regulator also to be relatively constant over this same range of ILOAD. In more detail, the capacitor CM is the predominant capacitance in the pole PDOMINANT, and forms PDOMINANT in conjunction with a combination of the following resistances: the output resistance Ro of the amplifier 58, the resistors R1, R2, and R3, the inverse of the transconductance gm6 of the transistor M6, the drain-to-source resistance rds6 (not shown in FIGS. 4 and 5) of the transistor M6, and the load resistance RL; the capacitor CM is effectively coupled to the resistors R1, R2, and R3, the transistor M6, and the load resistance RL through the source-gate junction of the transistor M1 because M1 is configured as a source follower.
A reason that PDOMINANT is relatively constant over a relatively wide range of ILOAD is as follows. At relatively low and moderate levels of ILOAD, gm6, Ro, and CM increase as ILOAD increases. The increase in gm6 is due to the increase in IOUT as described above, the increase in Ro is because the PMOS output pull-up transistor (not shown in FIGS. 4 and 5) of the amplifier 58 starts operating in its saturation region, and the increase in CM, which is a poly-N-well capacitor in an embodiment, is due to CM operating deeper within its accumulation region. But the load resistance RL decreases with increasing ILOAD at about the same combined rate as gm6, Ro, and CM increase so that the net change in the frequency of the dominant pole PDOMINANT is approximately zero. As ILOAD continues to increase from a relatively moderate level to a relatively high level, however, the dominant pole PDOMINANT begins to increase relatively slightly, because as the PMOS output pull-up transistor of the amplifier 58 enters into its deep saturation region, the value of Ro levels off such that the rate at which RL decreases outpaces the combined rate at which gm6 and CM increase.
FIG. 7 is a plot of the open-loop frequency response (magnitude and phase) of the LDO voltage regulator 50 of FIGS. 4 and 5 for ILOAD=1.0 μA and ILOAD=10.0 mA, according to an embodiment. At frequencies above about 100 KHz, the magnitude of the open-loop frequency response is slightly greater at ILOAD=10.0 mA than at ILOAD=1.0 μA because, as described above in conjunction with FIGS. 4 and 5, the frequency of the dominant pole PDOMINANT increases at higher values of ILOAD.
Referring again to FIGS. 4 and 5, the LDO voltage regulator 50 may also have a power-supply-rejection ratio (PSRR) and a load-transient step response that are suitable for many applications, and that are as good, or better, than the PSSRs and load-transient step responses of conventional LDO voltage regulators.
Still referring to FIGS. 4 and 5, now provided is a more rigorous mathematical explanation of the frequency response of the LDO voltage regulator 50, and of components of the frequency response such as the dominant pole PDOMINANT, the output pole POUT, and the zero ZTRACK that tracks, and that partially or fully cancels the effects of, POUT.
The open-loop transfer function (in the Laplace Transform, i.e., “s”, domain) of the LDO voltage regulator 50 is given by the following equation:




  
    
      
        
          
            VOUT
            ⁡
            
              (
              S
              )
            
          
          
            VIN
            ⁡
            
              (
              S
              )
            
          
        
        =
        
          
            
              A
              V
            
            ⁢
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                6
              
            
            ⁢
            
              
                R
                L
              
              [
              
                
                  
                    SC
                    M
                  
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ⁢
                    
                      1
                      
                        
                          R
                          4
                        
                        +
                        
                          1
                          /
                          
                            g
                            
                              m
                              ⁢
                              
                                
                              
                              ⁢
                              2
                            
                          
                        
                      
                    
                  
                
                +
                1
              
              ]
            
          
          
            
              
                
                  
                    
                      S
                      2
                    
                    ⁡
                    
                      [
                      
                        
                          
                            
                              
                                
                                  R
                                  3
                                  ′
                                
                                ⁢
                                
                                  R
                                  0
                                
                                ⁢
                                
                                  R
                                  EQ
                                
                                ⁢
                                
                                  g
                                  
                                    m
                                    ⁢
                                    
                                      
                                    
                                    ⁢
                                    6
                                  
                                
                                ⁢
                                
                                  C
                                  M
                                
                                ⁢
                                
                                  C
                                  1
                                
                              
                              +
                              
                                
                                  R
                                  EQ
                                
                                ⁢
                                
                                  
                                    R
                                    0
                                  
                                  ⁡
                                  
                                    (
                                    
                                      
                                        C
                                        L
                                      
                                      +
                                      
                                        C
                                        1
                                      
                                    
                                    )
                                  
                                
                                ⁢
                                
                                  C
                                  M
                                
                              
                              +
                            
                          
                        
                        
                          
                            
                              
                                
                                  
                                    R
                                    EQ
                                  
                                  ⁡
                                  
                                    (
                                    
                                      1
                                      +
                                      
                                        
                                          g
                                          
                                            m
                                            ⁢
                                            
                                              
                                            
                                            ⁢
                                            2
                                          
                                        
                                        ⁢
                                        
                                          R
                                          4
                                        
                                      
                                    
                                    )
                                  
                                
                                ⁢
                                
                                  (
                                  
                                    
                                      C
                                      L
                                    
                                    +
                                    
                                      C
                                      1
                                    
                                  
                                  )
                                
                                ⁢
                                
                                  C
                                  M
                                
                              
                              
                                G
                                1
                              
                            
                          
                        
                      
                      ]
                    
                  
                  +
                
              
            
            
              
                
                  
                    S
                    ⁡
                    
                      [
                      
                        
                          
                            
                              
                                
                                  
                                    (
                                    
                                      1
                                      +
                                      
                                        
                                          R
                                          4
                                        
                                        ⁢
                                        
                                          g
                                          
                                            m
                                            ⁢
                                            
                                              
                                            
                                            ⁢
                                            2
                                          
                                        
                                      
                                    
                                    )
                                  
                                  ⁢
                                  
                                    C
                                    M
                                  
                                
                                
                                  G
                                  1
                                
                              
                              +
                              
                                
                                  R
                                  EQ
                                
                                ⁡
                                
                                  (
                                  
                                    
                                      C
                                      L
                                    
                                    +
                                    
                                      C
                                      1
                                    
                                  
                                  )
                                
                              
                              +
                              
                                
                                  R
                                  0
                                
                                ⁢
                                
                                  C
                                  M
                                
                              
                              +
                            
                          
                        
                        
                          
                            
                              
                                
                                  R
                                  3
                                
                                
                                  
                                    R
                                    1
                                  
                                  +
                                  
                                    R
                                    2
                                  
                                  +
                                  
                                    R
                                    3
                                  
                                
                              
                              ⁢
                              
                                g
                                
                                  m
                                  ⁢
                                  
                                    
                                  
                                  ⁢
                                  6
                                
                              
                              ⁢
                              
                                R
                                EQ
                              
                              ⁢
                              
                                R
                                0
                              
                              ⁢
                              
                                C
                                M
                              
                            
                          
                        
                      
                      ]
                    
                  
                  +
                  1
                
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




where each variable (e.g., CM, C1, Ro, R1-R4, gm1, gm2, gm6, and rds6) represents the value of the corresponding component previously described above, and REQ, R′3, and G1 are given by the following equations:

REQ=(R1+R2+R3)∥RL∥rds6  (5)

R3′=R3∥(R1+R2)  (6)

G1=gm1(1+gm2R4)+gm2  (7)

Furthermore, gm1, gm2, and gm6 are given by the following equations:




  
    
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          -
          
            
              
                2
                ⁢
                
                  μ
                  p
                
                ⁢
                
                  C
                  ox
                
                ⁢
                
                  I
                  
                    SD
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  W
                  1
                
              
              
                L
                1
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  
  
    
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          -
          
            
              
                2
                ⁢
                
                  μ
                  p
                
                ⁢
                
                  C
                  ox
                
                ⁢
                
                  I
                  
                    SD
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                ⁢
                
                  W
                  2
                
              
              
                L
                2
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  
  
    
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            6
          
        
        =
        
          -
          
            
              
                2
                ⁢
                
                  μ
                  p
                
                ⁢
                
                  C
                  ox
                
                ⁢
                
                  I
                  OUT
                
                ⁢
                
                  W
                  6
                
              
              
                L
                6
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




where the “−” sign is due to the transistors M1, M2, and M6 being PMOS transistors, μp represents the respective hole mobilities in the channels of the PMOS transistors M1, M2, and M6, and Cox represents the respective unit-area capacitances of the gate oxides of these transistors.

And from equation (4), one can derive the following equations for the dominant pole PDOMINANT, the output pole POUT, and the tracking zero ZTRACK of the LDO voltage regulator 50:




  
    
      
        
          P
          DOMINANT
        
        ≈
        
          1
          
            
              
                β
                1
              
              ⁡
              
                (
                
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      6
                    
                  
                  ⁢
                  
                    R
                    EQ
                  
                  ⁢
                  
                    C
                    M
                  
                
                )
              
            
            ⁢
            
              R
              o
            
          
        
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        
          P
          OUT
        
        ≈
        
          -
          
            
              β
              1
            
            
              
                (
                
                  
                    C
                    L
                  
                  +
                  
                    C
                    1
                  
                
                )
              
              ⁢
              
                (
                
                  
                    1
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        6
                      
                    
                  
                  ⁢
                  
                    
                    
                  
                  ⁢
                  
                    β
                    1
                  
                  ⁢
                  
                    R
                    EQ
                  
                
                )
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  
  
    
      
        
          Z
          TRACK
        
        ≈
        
          -
          
            
              (
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  1
                  
                    
                      R
                      4
                    
                    +
                    
                      1
                      /
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                  
                
              
              )
            
            
              C
              M
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




where β1 is given by the following equation:





  
    
      
        
          β
          1
        
        =
        
          
            R
            3
          
          
            
              R
              1
            
            +
            
              R
              2
            
            +
            
              R
              3
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




At higher levels of the load current ILOAD, 1/gm6<<β1·REQ; therefore, assuming that CL>>C1 (this is a valid assumption in many applications, including an embodiment of the LDO voltage regulator 50), equation (12) reduces to:




  
    
      
        
          
            P
            OUT
          
          ≈
          
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  6
                
              
              
                C
                L
              
            
          
        
        =
        
          
            1
            
              C
              L
            
          
          ⁢
          
            
              
                I
                OUT
              
              *
              2
              ⁢
              μ
              ⁢
              
                
              
              ⁢
              
                
                  C
                  ox
                
                ⁡
                
                  [
                  
                    
                      W
                      6
                    
                    
                      L
                      6
                    
                  
                  ]
                
              
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




Similarly at higher levels of the load current ILOAD,




  
    g
    
      m
      ⁢
      
        
      
      ⁢
      1
    
  
  >>
  
    1
    
      
        R
        4
      
      +
      
        1
        /
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            2
          
        
      
    
  




such that equation (13) reduces to:





  
    
      
        
          
            Z
            TRACK
          
          ≈
          
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              
                C
                M
              
            
          
        
        =
        
          
            
              1
              
                C
                M
              
            
            ⁢
            
              
                
                  I
                  
                    SD
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                *
                2
                ⁢
                μ
                ⁢
                
                  
                
                ⁢
                
                  
                    C
                    ox
                  
                  ⁡
                  
                    [
                    
                      
                        W
                        1
                      
                      
                        L
                        1
                      
                    
                    ]
                  
                
              
            
          
          =
          
            
              1
              
                C
                M
              
            
            ⁢
            
              
                
                  K
                  1
                
                ⁢
                
                  I
                  OUT
                
                *
                2
                ⁢
                μ
                ⁢
                
                  
                
                ⁢
                
                  C
                  ox
                
                ⁢
                
                  
                    K
                    2
                  
                  ⁡
                  
                    [
                    
                      
                        W
                        6
                      
                      
                        L
                        6
                      
                    
                    ]
                  
                
              
            
          
        
      
    
    
      
        (
        16
        )
      
    
  




where




  
    
      
        
          K
          1
        
        ·
        
          I
          OUT
        
      
      =
      
        I
        
          SD
          ⁢
          
            
          
          ⁢
          1
        
      
    
    ,
    
      

    
    ⁢
    
      
        
          K
          2
        
        ⁡
        
          [
          
            
              W
              6
            
            
              L
              6
            
          
          ]
        
      
      =
      
        [
        
          
            W
            1
          
          
            L
            1
          
        
        ]
      
    
    ,
    
      

    
    ⁢
    
      
        K
        1
      
      <
      1
    
    ,
    
      

    
    ⁢
    and
  




  
    
      K
      2
    
    <
    1
  



Assuming that CM and CL are related by the following equation:

CM=αCL  (17)

where α<1 (this is a valid assumption in many applications, including an embodiment of the LDO voltage regulator 50), ZTRACK and POUT are related by the following equation:





  
    
      
        
          Z
          TRACK
        
        ≈
        
          
            P
            OUT
          
          ⁡
          
            [
            
              
                1
                α
              
              ⁢
              
                
                  
                    K
                    1
                  
                  ⁢
                  
                    K
                    2
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        18
        )
      
    
  




Consequently, by selecting appropriate values for α, K1, and K2, a circuit designer can determine to what degree ZTRACK cancels POUT. For example, if the designer sets




  
    
      
        1
        α
      
      ⁢
      
        
          
            K
            1
          
          ⁢
          
            K
            2
          
        
      
    
    =
    1
  
  ,




then ZTRACK fully (or at least almost fully, taking into account the approximations made in the above equations, component error tolerances, etc.) cancels POUT. But in some applications, the designer may impart a better stability margin to the frequency response of the LDO voltage regulator 50 by setting





  
    
      1
      α
    
    ⁢
    
      
        
          K
          1
        
        ⁢
        
          K
          2
        
      
    
  
  ≠
  1.




Furthermore, VFB—TRACK and VOUT are related by the following equation:




  
    
      
        
          
            VFB_TRACK
            ⁢
            
              (
              S
              )
            
          
          
            VOUT
            ⁡
            
              (
              S
              )
            
          
        
        =
        
          
            
              R
              3
            
            ⁡
            
              [
              
                
                  
                    S
                    ⁡
                    
                      (
                      
                        
                          R
                          1
                        
                        +
                        
                          R
                          2
                        
                      
                      )
                    
                  
                  ⁢
                  
                    C
                    1
                  
                
                +
                1
              
              ]
            
          
          
            
              (
              
                
                  R
                  1
                
                +
                
                  R
                  2
                
                +
                
                  R
                  3
                
              
              )
            
            ⁡
            
              [
              
                
                  
                    SC
                    1
                  
                  ⁡
                  
                    (
                    
                      
                        R
                        3
                      
                      ⁢
                      
                        
                        
                      
                      ⁢
                      
                        (
                        
                          
                            R
                            1
                          
                          +
                          
                            R
                            2
                          
                        
                        )
                      
                    
                    )
                  
                
                +
                1
              
              ]
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




And VFB and VOUT are related by the following equation:




  
    
      
        
          
            VFB
            ⁡
            
              (
              S
              )
            
          
          
            VOUT
            ⁡
            
              (
              S
              )
            
          
        
        =
        
          
            
              (
              
                
                  R
                  2
                
                +
                
                  R
                  3
                
              
              )
            
            
              (
              
                
                  R
                  1
                
                +
                
                  R
                  2
                
                +
                
                  R
                  3
                
              
              )
            
          
          ⁢
          
            
              
                
                  
                    SC
                    1
                  
                  
                    (
                    
                      1
                      +
                      
                        K
                        3
                      
                    
                    )
                  
                
                ⁡
                
                  [
                  
                    
                      
                        
                          (
                          
                            
                              
                                R
                                3
                              
                              ⁢
                              
                                
                                
                              
                              ⁢
                              
                                (
                                
                                  
                                    R
                                    1
                                  
                                  +
                                  
                                    R
                                    2
                                  
                                
                                )
                              
                            
                            +
                          
                        
                      
                    
                    
                      
                        
                          
                            (
                            
                              
                                R
                                1
                              
                              +
                              
                                R
                                2
                              
                            
                            )
                          
                          ⁢
                          
                            K
                            3
                          
                        
                      
                    
                  
                  ]
                
              
              +
              1
            
            
              [
              
                
                  
                    SC
                    1
                  
                  ⁢
                  
                    (
                    
                      
                        R
                        3
                      
                      ⁢
                      
                        
                        
                      
                      ⁢
                      
                        (
                        
                          
                            R
                            1
                          
                          +
                          
                            R
                            2
                          
                        
                        )
                      
                    
                    )
                  
                
                +
                1
              
              ]
            
          
        
      
    
    
      
        (
        20
        )
      
    
  




where





  
    K
    3
  
  =
  
    
      
        
          R
          1
        
        ⁢
        
          R
          3
        
      
      
        
          (
          
            
              R
              1
            
            +
            
              R
              2
            
            +
            
              R
              3
            
          
          )
        
        ⁢
        
          R
          2
        
      
    
    .
  




From equation (20), one can see that the capacitor C1 generates a pole-zero pair, where the zero has a frequency that is lower than the frequency of the pole. If this pole-zero pair is located just outside of the open-loop unity-gain frequency of the LDO voltage regulator 50, then, at higher and full load currents ILOAD, the LDO regulator may have a better margin of stability than if this pole-zero pair is located further away from the unity-gain frequency, or if the capacitor C1 is omitted altogether from the LDO regulator.

Still referring to FIGS. 4 and 5, examples of values for at least some of the components of an embodiment of the LDO voltage regulator 50 are as follows for a range of ILOAD from about 0-10 mA (gm1, gm2, gm6, K1, and K2 can be calculated from the below values and from the above equations):



  
    
      R
      1
    
    =
    
      2.0
      ⁢
      
        
      
      ⁢
      K
      ⁢
      
        
      
      ⁢
      Ω
    
  




  
    
      R
      2
    
    =
    
      10.0
      ⁢
      
        
      
      ⁢
      K
      ⁢
      
        
      
      ⁢
      Ω
    
  




  
    
      R
      3
    
    =
    
      8.0
      ⁢
      
        
      
      ⁢
      K
      ⁢
      
        
      
      ⁢
      Ω
    
  




  
    
      R
      4
    
    =
    
      1.0
      ⁢
      
        
      
      ⁢
      K
      ⁢
      
        
      
      ⁢
      Ω
    
  




  
    
      C
      M
    
    =
    
      8.0
      ⁢
      
        
      
      ⁢
      pF
    
  




  
    
      C
      1
    
    =
    
      2.7
      ⁢
      
        
      
      ⁢
      pF
    
  




  
    
      C
      L
    
    =
    
      
        0.0
        -
        
          100.0
          ⁢
          
            
          
          ⁢
          
            pF
            ⁢
            
              

            
            [
            
              
                W
                1
              
              
                L
                1
              
            
            ]
          
        
      
      =
      
        
          16
          ·
          
            
              
                5.00
                ⁢
                
                  
                
                ⁢
                
                  micrometers
                  ⁡
                  
                    (
                    μm
                    )
                  
                
              
              
                0.15
                ⁢
                
                  
                
                ⁢
                μm
              
            
            ⁢
            
              

            
            [
            
              
                W
                2
              
              
                L
                2
              
            
            ]
          
        
        =
        
          
            5
            ·
            
              
                
                  5.00
                  ⁢
                  
                    
                  
                  ⁢
                  μm
                
                
                  0.15
                  ⁢
                  
                    
                  
                  ⁢
                  μm
                
              
              ⁢
              
                

              
              [
              
                
                  W
                  3
                
                
                  L
                  3
                
              
              ]
            
          
          =
          
            
              5
              ·
              
                
                  
                    10.00
                    ⁢
                    
                      
                    
                    ⁢
                    μm
                  
                  
                    1.00
                    ⁢
                    
                      
                    
                    ⁢
                    μm
                  
                
                ⁢
                
                  

                
                [
                
                  
                    W
                    4
                  
                  
                    L
                    4
                  
                
                ]
              
            
            =
            
              
                3
                ·
                
                  
                    
                      10.00
                      ⁢
                      
                        
                      
                      ⁢
                      μm
                    
                    
                      1.00
                      ⁢
                      
                        
                      
                      ⁢
                      μm
                    
                  
                  ⁢
                  
                    

                  
                  [
                  
                    
                      W
                      5
                    
                    
                      L
                      5
                    
                  
                  ]
                
              
              =
              
                
                  26
                  ·
                  
                    
                      
                        1.35
                        ⁢
                        
                          
                        
                        ⁢
                        μm
                      
                      
                        0.15
                        ⁢
                        
                          
                        
                        ⁢
                        μm
                      
                    
                    ⁢
                    
                      

                    
                    [
                    
                      
                        W
                        6
                      
                      
                        L
                        6
                      
                    
                    ]
                  
                
                =
                
                  45
                  ·
                  
                    
                      60.00
                      ⁢
                      
                        
                      
                      ⁢
                      μm
                    
                    
                      0.15
                      ⁢
                      
                        
                      
                      ⁢
                      μm
                    
                  
                
              
            
          
        
      
    
  



Furthermore, alternate embodiments of the LDO voltage regulator 50 are contemplated. For example, the transistor M2 may be omitted from the compensation circuit 56, and the resistor R4 may be coupled directly to the node 66 or to ground; but the transistor M2, when present, serves as a buffer that effectively causes R4 to have little or no influence on the frequency of the output pole POUT. Furthermore, a dual of the LDO voltage regulator 50, where the PMOS transistors are replaced with NMOS transistors, may be designed according to the above-described techniques to generate a negative voltage level for VOUT. Moreover, the resistor R2 may be omitted from the voltage divider 60 such that VFB=VFB—TRACK.
FIG. 8 is a functional block diagram of an electronic system 70, which includes processing circuitry 72 containing one or more of the LDO voltage regulator 50 of FIGS. 4 and 5; for example, the processing circuitry may include the SOC 20 of FIG. 2 where the LDO voltage regulators 26 are each replaced by a respective LDO voltage regulator 50. The processing circuitry 72 includes circuitry for performing various functions, such as executing specific software to perform specific calculations, or controlling the system 70 to provide desired functionality. In addition, the electronic system 70 includes one or more input devices 74, such as a keyboard, mouse, touch screen, audible or voice-recognition component, and so on, coupled to the processing circuitry 72 to allow an operator to interface with the electronic system. Typically, the electronic system 70 also includes one or more output devices 76 coupled to the processing circuitry 72, where the output devices can include a printer, video display, audio output components, and so on. One or more data-storage devices 78 are also typically coupled to the processing circuitry 72 to store data or retrieve data from storage media (not shown). Examples of typical data storage devices 78 include magnetic disks, FLASH memory, other types of solid state memory, tape drives, optical disks like compact disks and digital versatile disks (DVDs), and so on.
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. Moreover, the components described above may be disposed on a single or multiple IC dies to form one or more ICs, these one or more ICs may be coupled to one or more other ICs. In addition, any described component or operation may be implemented/performed in hardware, software, firmware, or a combination of any two or more of hardware, software, and firmware. Furthermore, one or more components of a described apparatus or system may have been omitted from the description for clarity or another reason. Moreover, one or more components of a described apparatus or system that have been included in the description may be omitted from the apparatus or system.

## Claims

1. An electronic circuit, comprising:
a feedback-coupled circuit stage including a drive circuit configured to drive a load, said drive circuit having a control input; and
a compensation circuit stage coupled to the feedback-coupled stage;
wherein the compensation circuit stage comprises a capacitor coupled in series with a compensation transistor at the control input, said compensation transistor configured to exhibit a variable transconductance that is dependent on a voltage signal replicating voltage across the load and a current signal replicating current in the load.

2. The electronic circuit of claim 1 wherein the feedback-coupled circuit stage includes an amplifier.

3. The electronic circuit of claim 1 wherein the feedback-coupled circuit stage includes a voltage regulator.

4. The electronic circuit of claim 1 wherein the load includes an integrated circuit.

5. The electronic circuit of claim 1 wherein the load includes a computing circuit.

6. The electronic circuit of claim 1 wherein the load and the electronic circuit are disposed on a same integrated circuit die.

7. The electronic circuit of claim 1 wherein the load and the electronic circuit are disposed on respective integrated circuit dies.

8. The electronic circuit of claim 1 wherein the electronic circuit includes a low-drop-out voltage regulator.

9. The electronic circuit of claim 1 wherein the feedback-coupled circuit stage includes:
an input circuit stage configured to receive an input signal and a feedback signal and to generate an intermediate signal; and
an output circuit stage including said drive circuit and configured to receive the intermediate signal, to generate the feedback signal, and to drive the load.

10. The electronic circuit of claim 1 wherein the feedback-coupled circuit stage includes:
an amplifier circuit stage configured to receive an input signal and a feedback signal and to generate an intermediate signal; and
an output circuit stage including said drive circuit and configured to receive the intermediate signal, to generate the feedback signal, and to drive the load.

11. An electronic circuit, comprising:
a feedback-coupled circuit stage configured to drive a load; and
a compensation circuit stage coupled to the feedback-coupled stage;
wherein a frequency response of a combination of the compensation circuit stage and feedback-coupled circuit stage includes a first root and an opposite second root that depend on the load;
wherein the feedback-coupled circuit includes an intermediate node, and wherein the compensation circuit stage comprises:
a first input configured to receive an intermediate signal from the intermediate node of the feedback-coupled circuit stage;
a second input configured to receive a current signal replicating current in the load;
a third input configured to receive a voltage signal replicating voltage across the load;
a variable resistance biased by the intermediate signal and the current signal, said variable resistance controlled by said voltage signal.

12. The electronic circuit of claim 11 wherein:
the first root includes a first pole;
the second root includes a zero; and
the frequency response includes a third root that includes a dominant second pole.

13. The electronic circuit of claim 11 wherein the first root includes a pole.

14. The electronic circuit of claim 11 wherein the second root includes a zero.

15. The electronic circuit of claim 11 wherein the second root is approximately equal to a product of the first root and a constant.

16. The electronic circuit of claim 11 wherein the frequency response includes a third root that is lower than the first and second roots.

17. The electronic circuit of claim 11, further comprising a capacitor coupled between the first and second inputs and in series with the variable resistance.

18. The electronic circuit of claim 11 wherein the variable resistance comprises a transistor having a control terminal coupled to receive the voltage signal and a conduction terminal coupled to receive the intermediate and current signals.

19. The electronic circuit of claim 18 wherein the transistor has a transconductance that varies in response to the current and voltage signals.

20. An electronic circuit comprising:
a feedback-coupled circuit stage configured to drive a load; and
a compensation circuit stage coupled to the feedback-coupled stage;
wherein the compensation circuit stage comprises:
a current sensing circuit coupled to sense current in the load and generate a current signal applied to a first node;
a capacitor coupled between an intermediate node of the feedback-coupled circuit and the first node;
a voltage sensing circuit coupled to sense voltage in the load and generate a voltage signal;
a first transistor having a source-drain path coupled between the first node and a reference node;
a resistor coupled between the first node and a second node; and
a second transistor having a source-drain path coupled between the second node and the reference node;
wherein gate terminals of the first and second transistors are coupled to receive the voltage signal.