# Patent

## Title
Oscillator circuit with output slope proportional to supply voltage

## Abstract

A voltage-controlled oscillator (VCO) comprises a supply voltage node, configured to receive a supply voltage, a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor, a discharge switch configured to discharge the capacitor according to an oscillation frequency of the oscillating output voltage, and a comparator circuit configured to provide, to a control terminal of the discharge switch, a control signal that is determined based on a comparison of the output voltage and a specified threshold voltage. The oscillating output voltage includes a pulse having a ramp slope that is determined as a function of a magnitude of the supply voltage, and is capable of being adjusted independently of the oscillation frequency.

## Background
TECHNICAL FIELD
This document pertains generally, but not by way of limitation, to oscillator circuits.
BACKGROUND
An electronic oscillation circuit provides an oscillating electric output signal, often in response to a control signal that adjusts one or more characteristics of the oscillating electric output signal. An electronic oscillation circuit can include, for example, a voltage-controlled oscillator (VCO) circuit, or a current-controlled oscillator circuit. Oscillating electric output signal characteristics can include, among others, signal amplitude, frequency, or waveform morphology.
In an example, a voltage-controlled oscillator provides an oscillating electric output signal determined, at least in part, by a voltage control input signal. For instance, an amplitude of a voltage control input signal can correspond to a frequency of the oscillating electric output signal, and a change in the amplitude of the voltage control input signal can correspond to a change in the frequency of the oscillating electric output signal. In other examples, an electronic oscillation circuit can be controlled by a current control input signal, such that a change in the current control input signal corresponds to a change in the frequency of the oscillating electric output signal.
Some examples of signals that can be generated by electronic oscillation circuits include processor clock signals, signals configured for wired and wireless communications, system synchronization signals, and audio signals, among others. VCOs are used in control systems, such as in phase-locked loop (PLL) circuits. In an example, a PLL circuit includes a PLL output that is fed back to a PLL input, and a reference input. The PLL output signal has a phase that is generated using a VCO and is based on a comparison of a reference signal phase and the PLL output signal phase.
OVERVIEW
The present inventors have recognized, among other things, that a problem to be solved can include providing a voltage-controlled oscillator (VCO) circuit with a pulse ramp output having a ramp slope that is proportional to the VCO supply voltage. The present subject matter can help provide a solution to this problem, such as using: a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor; a discharge switch, coupled in parallel with the capacitor, the discharge switch configured to discharge the capacitor according to an oscillation frequency of the oscillating output voltage; and a first comparator circuit, configured to provide, to a control terminal of the discharge switch, a control signal that is determined based on a comparison of the output voltage and a specified threshold voltage. In an example, the specified threshold voltage and the output voltage are proportional to the supply voltage, the ramp slope is proportional to the supply voltage, and the oscillation period is independent of the supply voltage.
In an example, a system comprising the VCO circuit includes a supply voltage node, configured to receive a supply voltage, and a power converter forward path, including first and second switches, an inductor, and a first capacitor, wherein each of the first and second switches is controllably coupled to a respective driver circuit, wherein the first switch is coupled to the supply voltage node, and wherein a system output voltage is provided using the first capacitor. The system can include a feedback path comprising a pulse signal generator, and first and second comparator circuits. The pulse signal generator can include a phase detector and the VCO, wherein the VCO is configured to generate an oscillating output voltage comprising a pulse train, and the pulse train comprises pulses having ramp slopes that are determined as a function of a magnitude of the supply voltage, and the output oscillates at a frequency determined by a signal from a phase detector. The first comparator circuit is operable to provide an error voltage signal based on a comparison of a reference voltage and the system output voltage, and the second comparator circuit is operable to provide a control signal to the respective driver circuits based on a comparison of the error voltage signal and the output of the pulse signal generator. In an example, the system is a buck converter.
Operating the VCO circuit can include, among other things, some or all of the steps including providing a first current to or from a supply through first and second circuit legs, generating a ramped pulse signal across a capacitor in the second circuit leg using a portion of the first current, providing a threshold voltage across a resistor in the first circuit leg using a portion of the first current, and controllably discharging the ramped pulse signal from the capacitor in response to a comparison of the capacitor voltage and the threshold voltage, wherein the ramped pulse signal is generated as a pulse having a slope that is a function of a value of the capacitor, of a value of the resistor, and of a voltage of the supply.
This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.



BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
FIG. 1 illustrates generally an example of a switching voltage converter system.
FIG. 2 illustrates generally an example of a voltage-controlled oscillator circuit.
FIG. 3 illustrates generally an example of an oscillator output voltage ramp signal.
FIG. 4 illustrates generally an example of a voltage-controlled oscillator circuit.
FIG. 5 illustrates generally an example of a threshold voltage change.
FIG. 6 illustrates generally an example of a voltage-controlled oscillator circuit with comparator circuits configured to adjust a slew rate.
FIG. 7 illustrates generally an example that can include generating, using a VCO, a ramped pulse signal having a pulse slope that is proportional to a supply voltage.



DETAILED DESCRIPTION
FIG. 1 illustrates generally an example of a switching voltage converter system 100. The converter system 100 is configured as a buck converter, however, the circuits and methods described herein are similarly applicable to other switching converter topologies. The converter system 100 includes a feedback circuit 105 that includes a phase-locked loop (PLL) circuit 150, and the PLL circuit 150 includes a voltage-controlled oscillator (VCO) circuit. The VCO circuit provides a pulse ramp output signal having a ramp slope that is proportional to the supply voltage of the VCO circuit and, optionally, is proportional to the supply voltage of the converter system 100.
The converter system 100 includes first and second switches S1 and S2 coupled at a switching node 101. An energy-storing inductor 110 is coupled between the switching node 101 and a converter output node. In the example of FIG. 1, the converter output node provides a converter output signal VOUT, such as to an output load 130 (e.g., a resistive load). The inductor 110 receives, via the first and second switches S1 and S2, respectively, first and second currents according to respective duty cycles D and D′. The first and second currents charge an energy storage element, such as a capacitor 120 that is coupled to the converter output node.
The first and second switches S1 and S2 are switched to control the converter output signal VOUT in response to respective switching signals received from a controller circuit 102. The controller circuit 102 generates the switching signals using information about the converter output signal from the feedback circuit 105. The controller circuit 102 can be configured to operate the switches in various modes, such as a pulse-width modulation (PWM) mode and a pulse-skip (or pulse-frequency) mode. In a PWM mode, the frequency at which the first and second switches S1 and S2 are switched is constant and the pulse width, or on-time, of the switches is adjusted to vary the voltage at the converter output node. In the PWM mode, the average power delivered from the converter system 100 is proportional to the duty cycle, D, of the switches. In a pulse-skip mode, the first and second switches S1 and S2 are both open to disable, or skip, switching. In the pulse-skip mode, the voltage and current available at the converter output node are functions of the energy stored by the capacitor 120.
In the example of FIG. 1, the second switch S2 is coupled between the switching node 101 and ground, and the first switch S1 is coupled between the switching node 101 and a supply input node. In operation of the converter system 100, during a first clock period, the second switch S2 is switched off and the first switch S1 is switched on to raise the switching node 101 to approximately a supply voltage VDD at the supply input node (e.g., when VDD is greater than a threshold voltage of the first switch S1, such as a VGS threshold voltage when the switch is a MOS device), and a rising current flows through the inductor 110. During a subsequent second clock period, the first switch S1 is switched off and the second switch S2 is switched on to pull the switching node 101 to approximately a ground voltage level. A falling current then flows from the inductor 110. Throughout both clock periods, the capacitor 120 provides an output current IOUT to the load 130. These rising and falling currents provide the converter output signal VOUT. The duration of the first and second clock periods is adjusted by the controller circuit 102 to establish duty cycles D and D′ for the first and second switches S1 and S2, respectively, to provide or maintain a particular converter output voltage at the converter output node.
The converter output signal VOUT is processed by the feedback circuit 105, and information about VOUT is provided to the controller circuit 102 to update the converter duty cycle. In the example of FIG. 1, the feedback circuit 105 includes a resistive divider 140, a first amplifier 161, and a second amplifier 162. The resistive divider 140 is configured to provide a feedback voltage, VFB, that is proportional to the converter output voltage at VOUT. The first amplifier 161 is a differential amplifier that provides an error voltage signal VERR based on a comparison of the feedback voltage VFB and a reference voltage, VREF1. In an example, the error voltage signal VERR can be processed or filtered to enhance stability of the feedback loop.
The second amplifier 162 is a differential amplifier that provides a control signal to the controller circuit 102. The error voltage signal VERR is applied to the non-inverting input of the second amplifier 162, and a voltage ramp signal, VRMP, is applied to the inverting input of the second amplifier 162. In an example, VRMP is a fixed voltage ramp that provides a PWM signal to the controller circuit 102. In response to the PWM signal, the controller circuit 102 provides signals to the first and second switches S1 and S2 according to the duty cycle determined in part by the error voltage VERR. In this manner, the first and second switches S1 and S2 pass respective currents in different portions of each period of the PWM signal and maintain the feedback voltage VFB at a level that is similar to the reference voltage VREF1. The converter output voltage VOUT is thereby maintained substantially constant regardless of the output current. In some examples, the converter system 100 includes further circuitry, such as a current feedback loop, to supplement the feedback circuit 105 and to address changes in VDD.
The converter system 100 optionally includes a phase-locked loop (PLL) circuit 150. The PLL circuit 150 includes a phase detector circuit 151, a voltage-controlled oscillator (VCO) circuit 200, and a filter 152. The PLL circuit 150 is configured to receive a reference signal from a clock source 170 and provide the voltage ramp signal VRMP from the VCO circuit 200. A first input node of the phase detector circuit 151 is configured to receive the reference signal from the clock source 170, and a second input node of the phase detector circuit 151 is coupled to the VCO circuit 200 using a feedback loop. The phase detector circuit 151 compares the phase of VRMP with the phase of the reference signal and generates a phase error signal according to the phase difference between the two signals.
An output node of the phase detector circuit 151 is coupled to an input node of the filter 152, and an output node of the filter 152 is coupled to an input node of the VCO circuit 200 to provide a VCO control signal to the VCO circuit 200. In an example, the filter 152 filters the phase error signal from the phase detector circuit 151 to remove extraneous components of the phase detector output signal and to convert the signal into a voltage that can be used as the VCO control signal. The VCO control signal can be used to adjust one or more characteristics of the VCO circuit 200, such as an oscillating frequency of the VCO output signal. Because of the PLL feedback loop, the phase detector circuit 151 and the filter 152 will continuously update based on the VCO output signal until the phase error is minimized, such as when the VCO output signal frequency is synchronized with the reference signal frequency.
FIG. 2 illustrates generally an example of the VCO circuit 200. The VCO circuit 200 is configured to provide a voltage ramp signal VRMP, such as can be provided to the phase detector circuit 151 of the converter system 100. In some examples, the VCO circuit 200 provides the voltage ramp signal VRMP as an oscillating signal comprising multiple pulses. One or more of the multiple pulses can include a ramp portion having a slope that is proportional to the supply voltage VDD. In some examples, the VCO circuit 200 provides the oscillating signal at a frequency that is independent of the supply voltage VDD.
The slope of a ramp portion of a VRMP pulse can be increased or decreased according to fluctuations in VDD. In some examples, the VCO circuit 200 provides the oscillating output voltage in a voltage feed forward configuration. That is, the VCO circuit 200 provides the oscillating output voltage without using a feedback loop to tune or update the pulse slopes. In some examples, the supply voltage for the VCO circuit 200 is received from a node that is coupled to the same supply input node as the converter system 100 (e.g., to receive the supply voltage VDD). Accordingly, the VCO circuit 200 provides the output signal VRMP as a signal comprising pulses with ramp slopes that are proportional to VDD.
The example VCO circuit 200 in FIG. 2 includes a circuit network configured to generate the VCO output voltage across an output capacitor 205, and a comparator circuit 230 configured to switchably discharge the output capacitor 205 to provide the oscillating output voltage VRMP. The VCO circuit 200 includes a differential pair of p-type transistors comprising a first p-type transistor 211 and a second p-type transistor 212, configured to receive the VCO control signal and update the oscillating frequency of the VCO. The VCO circuit 200 further includes a first current mirror comprising a diode-connected third p-type transistor 213 and a fourth p-type transistor 214 in the mirror's respective current legs. In an example, the differential pair of transistors is configured to meter the current in the first current mirror, and thereby adjust the charging current applied to the output capacitor 205.
The first current mirror is coupled to the supply input node, and the leg of the first current mirror that includes the fourth p-type transistor 214 supplies current to source nodes of the differential pair. The gate of the first p-type transistor 211 is coupled to a reference voltage biasing node (e.g., to receive a second reference voltage VREF2), and the gate of the second p-type transistor is coupled to a voltage control node (e.g., to receive the VCO control signal VC). The reference voltage biasing node is used to center the operating range of the voltage control node over a specified operating range.
In the first current mirror, the third p-type transistor 213 mirrors the current from the fourth p-type transistor 214, and the drain of the third p-type transistor 213 is coupled to a first resistor 201. The biasing current through the third p-type transistor 213 is expressed as:




  
    
      
        
          I
          
            d
            ,
            213
          
        
        =
        
          
            
              V
              DD
            
            -
            
              V
              
                GS
                ,
                213
              
            
          
          
            R
            201
          
        
      
    
    
      
        (
        1
        )
      
    
  




In an example, the biasing current Id,213 indirectly provides a reference voltage based on the voltage across the first resistor 201, and the reference voltage is used by the comparator circuit 230 to update the duty cycle at which the output capacitor 205 is discharged.

In the example of FIG. 2, the current in the third p-type transistor 213 is mirrored to a sixth p-type transistor 216 by way of a network of current mirrors. For example, the current in the third p-type transistor 213 is mirrored by the fourth p-type transistor 214 and provided, at least partially, to a diode-connected first n-type transistor 221 via the differential pair of transistors. The current in the first n-type transistor 221 can be mirrored to a second n-type transistor 222. The current in the second n-type transistor 222 can bias a fifth p-type transistor 215, whose current can be mirrored to the sixth p-type transistor 216. A drain of the sixth p-type transistor 216 can be coupled to the output capacitor 205. In an example where the mirroring ratios for the n-type and p-type mirrors are 1:1, the drain current in the third p-type transistor 213 can be substantially equal to the drain current in the sixth p-type transistor 216. In an example, the mirroring ratios are not 1:1, and the drain current in the sixth p-type transistor 216 differs from the drain current in the third p-type transistor 213 by a scaling factor γ:




  
    
      
        
          
            
              
                I
                
                  d
                  ,
                  216
                
              
              =
              
              ⁢
              
                γ
                ·
                
                  I
                  
                    d
                    ,
                    213
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                γ
                ·
                
                  
                    
                      V
                      DD
                    
                    -
                    
                      V
                      
                        GS
                        ,
                        213
                      
                    
                  
                  
                    R
                    201
                  
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




The constant γ indicates the overall mirroring ratio from the current through the third p-type transistor 213 to the drain current in the sixth p-type transistor 216 that flows into the output capacitor 205. In the example of FIG. 2, Id,216 is proportional to the difference between the supply voltage VDD and the gate-to-source voltage of the third p-type transistor VGS,213, as shown by Equation (2).

In an example, the VCO output signal VRMP develops across the output capacitor 205 according to the current through the sixth p-type transistor 216. A discharge switch 220 can be coupled across the output capacitor 205 to controllably shunt the output capacitor 205 voltage to circuit ground, such as according to a control signal from the comparator circuit 230. In an example, the discharge switch 220 is a transistor with a gate configured to receive the control signal from the comparator circuit 230.
The comparator circuit 230 is configured to provide the discharge control signal based on a comparison of the output capacitor 205 voltage and a threshold voltage. In an example, the comparator circuit 230 identifies the threshold voltage based on a measured voltage in the VCO circuit 200, receives the threshold voltage from an external source, or uses a specified or predetermined threshold voltage, such as one stored in the comparator circuit 230. In the example of FIG. 2, the threshold voltage can be a measured voltage across the first resistor 201. The voltage across the first resistor 201 depends on the supply voltage VDD and the gate-to-source voltage of the third p-type transistor 213, VGS,213.
In an example where the VCO output signal VRMP oscillates at a fixed frequency, the gate of the first p-type transistor 211 can be tied high (e.g., the input reference signal VREF2 is greater than VGS,211) and the gate of the second p-type transistor 212 can be tied low (e.g., the VCO control signal Vc is less than VGS,212). Biased in this manner, substantially all of the current flowing through the fourth p-type transistor 214 also flows through the second p-type transistor 212. At an initial time t0, the initial voltage across the output capacitor 205 is about 0 V. The discharge switch 220 is in an open state such that the voltage across the output capacitor 205 is not shunted to the circuit ground and the output capacitor 205 charges. In this example, the drain current in the sixth p-type transistor 216 flows into the output capacitor 205 and the voltage ramp signal VRMP increases, or ramps up. The slope of the pulse ramp is the rate of change of the voltage across the output capacitor 205, which is determined in part by the drain current of the third p-type transistor according to:




  
    
      
        SLOPE
        =
        
          
            
              d
              
                V
                RMP
              
            
            
              d
              t
            
          
          =
          
            
              
                I
                
                  d
                  ,
                  213
                
              
              
                C
                220
              
            
            =
            
              γ
              ⁢
              
                
                  
                    V
                    DD
                  
                  -
                  
                    V
                    
                      GS
                      ,
                      213
                    
                  
                
                
                  
                    C
                    220
                  
                  ⁢
                  
                    R
                    201
                  
                
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




The slope of the ramp portion is thus proportional to VDD-VGS,213. The constant γ from Equation (2) indicates the overall mirroring ratio from the current through the third p-type transistor 213 to the drain current in the sixth p-type transistor 216 that flows into the output capacitor 205. Combining Equations (2) and (3), when the supply voltage VDD is large relative to the threshold voltage of the transistors, the slope is approximated as:





  
    
      
        SLOPE
        ≈
        
          γ
          ⁢
          
            
              V
              DD
            
            
              
                C
                220
              
              ⁢
              
                R
                201
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




When the voltage magnitude of VRMP is, for example, substantially the same voltage magnitude as the threshold voltage (e.g., the measured voltage across the first resistor 201), the comparator circuit 230 can provide a signal to the discharge switch 220 to shunt the output capacitor 205 voltage to ground. That is, as the voltage of the output capacitor 205 approaches or exceeds the threshold voltage, the output capacitor 205 is discharged. Once the voltage of the output capacitor 205 is diminished, the comparator circuit 230 can update the signal to the discharge switch 220 to remove the shunt path such that the output capacitor 205 can be charged again.
In an example, the threshold voltage used by the comparator circuit 230 is the voltage across the first resistor 201. This threshold voltage is the difference between the supply voltage VDD and the gate-to-source voltage VGS,213 of the third p-type transistor 213. The threshold voltage is proportional to VDD-VGS,213. When the threshold voltage and the output capacitor 205 charging current are each proportional to VDD-VGS,213, the oscillation frequency or ramp period of VRMP is independent of the supply voltage. The voltage across the output capacitor 205 is the oscillating output voltage VRMP and has a pulse period given by:




  
    
      
        T
        =
        
          
            
              
                C
                205
              
              ⁢
              
                V
                
                  R
                  201
                
              
            
            
              I
              
                d
                ,
                216
              
            
          
          =
          
            
              
                C
                205
              
              ⁡
              
                (
                
                  
                    V
                    DD
                  
                  -
                  
                    V
                    
                      GS
                      ,
                      213
                    
                  
                
                )
              
            
            
              I
              
                d
                ,
                216
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




In an example where the mirroring ratios for the n-type and p-type mirrors are 1:1, the drain current in the third p-type transistor 213 is substantially equal to the drain current in the sixth p-type transistor 216. Substituting the expression for Id,216 from Equation (2) into Equation (5), the oscillation period is:

T=C205R201  (6)

That is, the oscillation period is proportional to the capacitance of the output capacitor 205 and the resistance of the resistor 201, and the oscillation period is independent of the supply voltage VDD and the threshold voltages of the transistors in the VCO circuit 200.

The oscillating output voltage VRMP from the VCO circuit 200 thus comprises pulses having slopes that depend on the supply voltage VDD, the passive resistor, and the passive capacitor of the VCO circuit 200. The slope of the VCO output signal is therefore independent of any circuit that may receive the VCO output signal (e.g., the converter system 100 of FIG. 1). In FIG. 1, the converter system 100 operates in a feed forward manner because a change in VDD can be addressed by the VCO, such as without using information from the converter system 100 output. The output signal from the VCO circuit 200 is influenced by VDD, and, in an example, the oscillating output voltage VRMP from the VCO circuit 200 is used in the feedback circuit 105 of the converter system 100 to provide a control signal to the controller circuit 102.
FIG. 3 illustrates generally an example 300 of the oscillating output voltage VRMP from the VCO circuit 200. In the example of FIG. 3, at an initial time t0, VRMP is 0 V. VTH indicates the threshold voltage and, in the example of FIG. 2, VTH is the voltage across the first resistor 201 (e.g., VDD-VGS,213), and is supply-dependent. Accordingly, as the supply voltage VDD fluctuates, so too does the threshold voltage.
The current charging the output capacitor 205 changes as a function of time, and the current can be expressed as:




  
    
      
        
          I
          
            d
            ,
            216
          
        
        =
        
          
            C
            205
          
          ⁢
          
            
              d
              V
            
            
              d
              t
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Equation (7) is an alternative to the expression in Equation (2) of the current at the output capacitor 205. The slope of the voltage across the output capacitor 205 is represented by the change in the voltage with time, or dV/dt. Substituting the expression for the output capacitor 205 charging current Id,216 from Equation (2) into Equation (7), the expression for the change in time, dt, is:





  
    
      
        dt
        =
        
          
            
              d
              ⁢
              V
            
            ⁢
            
              
                C
                205
              
              
                I
                
                  d
                  ,
                  216
                
              
            
          
          =
          
            
              
                (
                
                  
                    V
                    DD
                  
                  -
                  
                    V
                    
                      GS
                      ,
                      213
                    
                  
                
                )
              
              ⁢
              
                
                  
                    C
                    205
                  
                  ⁢
                  
                    R
                    201
                  
                
                
                  (
                  
                    
                      V
                      DD
                    
                    -
                    
                      V
                      
                        GS
                        ,
                        213
                      
                    
                  
                  )
                
              
            
            =
            
              
                C
                205
              
              ⁢
              
                R
                201
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




Thus, as similarly provided in Equation (6), the oscillating output period dt is independent of the supply voltage VDD. In the example of FIG. 3, the discharge switch 220 is activated by the comparator circuit 230 at the expiration of each period dt, as indicated by the vertical arrows below the time axis. Activating the discharge switch 220 shunts the output capacitor 205 to ground and resets the oscillation cycle.

In the example of FIG. 3, the supply voltage VDD changes at t1 and t2. VTH tracks the changes in VDD. Because the oscillation period is independent of changes in VDD, the slope of VRMP changes to accommodate a change in VDD. For example, at t1, VDD is increased, VTH is increased, and the slope of VRMP is increased. Similarly, at t2, VDD is decreased, VTH is decreased, and the slope of VRMP is decreased. Thus, the slope of VRMP is proportional to VDD even as the oscillating frequency is unchanged.
Referring again to FIG. 2, the frequency of the VCO output signal VRMP can be varied in response to a VCO control signal. For example, the frequency of the output signal of the VCO circuit 200 is adjustable based on an input voltage signal at node VC in FIG. 2. In an example, the frequency adjustment is based on a variable resistance, such as a voltage-controlled resistor. In the example of FIG. 2, the differential pair of first and second p-type transistors 211 and 212 provides such a controlled resistance. Assuming the voltages at the gates of the first and second p-type transistors 211 and 212 are equal and of sufficient magnitude for both transistors to be forward biased, the first and second p-type transistors 211 and 212 will have the same VGS voltage, and each of the first and second p-type transistors 211 and 212 will conduct half of the drain current Id,214 from the fourth p-type transistor 214. In this example, the current in the sixth p-type transistor 216 is reduced, and the output capacitor 205 takes about twice as long to charge up to the threshold voltage set by the resistor 201. The output frequency is reduced as well since it takes more time to charge the output capacitor 205 when less current is provided to it.
When the first and second p-type transistors 211 and 212 are unequally biased, the drain current of the sixth p-type transistor is given by:




  
    
      
        
          I
          
            d
            ,
            216
          
        
        =
        
          
            
              I
              
                d
                ,
                213
              
            
            α
          
          =
          
            
              
                V
                DD
              
              -
              
                V
                
                  GS
                  ,
                  213
                
              
            
            
              α
              ·
              
                R
                201
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




where α is the ratio of the drain currents in the fourth p-type transistor 214 and the second p-type transistor 212:





  
    
      
        α
        =
        
          
            I
            
              d
              ,
              214
            
          
          
            I
            
              d
              ,
              212
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




The quantity α is a function of the voltage difference between VREF2 and VC. For example, when VC is less than VREF2, more current from the fourth p-type transistor 214 is steered toward the second p-type transistor 212, and α decreases. Conversely, when VC is greater than VREF2, more current is steered toward the first p-type transistor 211, and a increases. The quantity α has a minimum value of 1, which indicates substantially all of the drain current from the fourth p-type transistor 214 flows into the second p-type transistor 212.

The VCO oscillation frequency depends on a. For example, substituting the expression for Id,216 from Equation (9) into Equation (5) provides:




  
    
      
        T
        =
        
          
            
              
                
                  C
                  205
                
                ⁡
                
                  (
                  
                    
                      V
                      DD
                    
                    -
                    
                      V
                      
                        GS
                        ,
                        213
                      
                    
                  
                  )
                
              
              ⁢
              
                (
                
                  α
                  ·
                  
                    R
                    201
                  
                
                )
              
            
            
              (
              
                
                  V
                  DD
                
                -
                
                  V
                  
                    GS
                    ,
                    213
                  
                
              
              )
            
          
          =
          
            
              α
              ·
              
                C
                205
              
            
            ⁢
            
              R
              201
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




Thus, the ratio of the drain currents affects the oscillation frequency of the VCO circuit 200, while the oscillation frequency remains supply-independent.

However, α can be somewhat supply dependent when the first and second p-type transistors 211 and 212 are MOS transistors. To reduce the supply dependency and improve the accuracy of α, the first and second p-type transistors can be replaced with first and second bipolar transistors. The first and second bipolar transistors provide a translinear circuit that exploits the linear relationship between collector current and transconductance in the bipolar transistors, and makes a substantially supply independent. In another example to reduce the supply dependency and improve the accuracy of α, the first and second p-type transistors 211 and 212 can be operated in a sub-threshold (weak inversion) region by increasing the physical width of the transistors. When the transistors operate in the sub-threshold region, they behave similarly to bipolar transistors. In another example, if the accuracy of α is not critical and a more linear relationship is desired between the VCO control signal VC and the VCO oscillating frequency, the first and second p-type transistors 211 and 212 can be long channel devices.
Equations (3) and (4) indicate the slope of the VCO output voltage signal VRMP is substantially proportional to the supply voltage VDD when VGS,213 is small relative to the supply voltage VDD. However, when the supply voltage magnitude approaches VGS,213, the VCO circuit 200 can operate improperly or unpredictably. In this case, the operation of the VCO circuit 200 can be adjusted using a voltage-controlled current circuit, such as shown in the example of FIG. 4.
FIG. 4 illustrates generally an example of a second VCO circuit 400. The VCO circuit 400 includes several of the same circuit elements as described above in the discussion of the VCO circuit 200, and these elements are designated with the same numerals as used above in the discussion of FIG. 2. The VCO circuit 400 includes a voltage-controlled current circuit 410 configured to increase the current Id,213 drawn through the third p-type transistor 213 to maintain Id,213 proportional to the voltage supply VDD, such as when the magnitude of the supply voltage drops to a low level.
Referring again to Equation (1), the drain current Id,213 of the third p-type transistor 213 is a function of the supply voltage VDD, the gate-to-source voltage of the transistor VGS,213, and the resistance of the resistor 201. The drain current Id,213 can be made more closely proportional to the supply voltage VDD using the voltage-controlled current circuit 410 to increase the current through the third p-type transistor 213 by an amount that is approximately equal to the gate-to-source voltage divided by the resistance of the resistor 201.
In the example of FIG. 4, the voltage-controlled current circuit 410 includes third and fourth n-type transistors 223 and 224 arranged in a current mirror configuration, and fifth and sixth n-type transistors 225 and 226 arranged in a current mirror configuration. The voltage-controlled current circuit 410 further includes seventh, eighth, and ninth p-type transistors 217, 218, and 219. The ninth p-type transistor 219 is arranged to mirror the current through the third p-type transistor 213. The drain current in the third p-type transistor 213, Id,213, is mirrored to the fourth n-type transistor 224 by way of transistors 223 and 219. The fifth p-type transistor 225 is configured to drive the gate of the seventh p-type transistor and a second resistor 202, to balance the drain current Id,217 in the seventh n-type transistor 217. The resulting current through the eighth p-type transistor 218 is mirrored using the current mirror comprising the fifth and sixth n-type transistors 225 and 226 to increase the total current drawn from the supply node through the third p-type transistor 213.
In an example, the gate-to-source voltages of the third and fourth p-type transistors 213 and 214 are the same, and the first and second resistors 201 and 202 provide the same resistance. Accordingly, the drain current in the eighth p-type transistor 218 is given by:




  
    
      
        
          I
          
            d
            ,
            218
          
        
        =
        
          
            
              V
              
                GS
                ,
                217
              
            
            
              R
              202
            
          
          =
          
            
              V
              
                GS
                ,
                213
              
            
            
              R
              201
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




The drain current Id,218 is mirrored through the current mirror comprising the fifth and sixth n-type transistors 225 and 226, and thereby increases the total current drawn from the supply node through the third p-type transistor 213. In this manner, the magnitude of the drain current Id,213 in the VCO circuit 400 of FIG. 4 exceeds the drain current Id,213 in the VCO circuit 200 of FIG. 2.

Due to the voltage-controlled current circuit 410, the current that charges the capacitor 205 (i.e., Id,216) increases as the drain current Id,213 increases. Although the drain current Id,213 remains proportional to the supply voltage VDD, for example due to the voltage-controlled current circuit 410, the current through the first resistor 201 may not always be proportional to the supply voltage VDD. Accordingly, when the voltage-controlled current circuit 410 is used, the voltage across the first resistor 201 is not reliably proportional to the supply voltage VDD, and the voltage across the first resistor 201 should not be used as the threshold voltage by the comparator circuit 230 if the oscillating frequency is to be supply-independent.
However, the operating frequency of the VCO circuit 400 can be made supply independent when the threshold voltage used by comparator circuit 230 to control the discharge switch 220 is proportional to the supply voltage VDD. As described above in the discussion of FIG. 2, the operating frequency of the VCO circuit 200 can be supply independent because both the threshold voltage VTH and the output capacitor 205 charging current are proportional to the same VDD-VGS,213 voltage. In the example of FIG. 4, however, while the voltage across the first resistor 201 remains proportional to VDD-VGS,213, the elevated drain current Id,216 makes the output capacitor charging current proportional to VDD.
Instead of using the voltage across the first resistor 201 as the threshold voltage (i.e., VDD-VGS,213), the threshold voltage can be determined using a resistive divider comprising third and fourth resistors 203 and 204. The resistive divider can be coupled to the supply node of the VCO circuit 400 to receive the supply voltage VDD. The threshold voltage used by the comparator circuit 230 can be received from a tap node between the third and fourth resistors 203 and 204. Because the resistances of the third and fourth resistors 203 and 204 are fixed, the tap node remains substantially proportional to the supply voltage VDD over an expected operating range of VDD.
The oscillation period is affected by the resistance ratio in the resistive divider because the threshold voltage is determined by the resistance ratio. In an example that includes a changing supply voltage VDD level, the threshold voltage VTH can change almost instantaneously with the supply voltage VDD level change. However, the slope of the output capacitor charging ramp also changes. This change in output frequency is apparent as a phase error (e.g., in the PLL circuit 150), which can be corrected over subsequent oscillation cycles. When the supply voltage level change is brief, the phase error can be compensated in part using a filtering capacitor 206 coupled across a portion of the resistive divider.
For example, suppose the supply voltage VDD doubles during a particular cycle. The threshold voltage VTH can rapidly track the supply voltage VDD change using the resistive divider. Additionally, the slope of the output capacitor 205 charging ramp changes from the time of the supply voltage VDD change to the end of the cycle. The cycle length can be increased due to the increased threshold voltage VTH. In the cycle(s) where the voltage supply VDD transient occurs, the output frequency 1/T can be different than a steady state frequency, for example, because the output capacitor 205 may charge at a slower rate before the supply voltage VDD increase than after the increase.
In another example, the supply voltage VDD is halved in the middle of a cycle. The threshold voltage VTH can again rapidly track the supply voltage VDD change, and the slope of the output capacitor 205 charging ramp will change. In an example, the change in the threshold voltage VTH, in either case of the supply voltage VDD increase or decrease, can be slowed to compensate for the timing error and suppress the phase error. The filtering capacitor 206 can be provided across the fourth resistor 204 in the resistive divider to slow changes at the tap node by acting as a low pass filter.
FIG. 5 illustrates generally an example 500 that includes a threshold voltage change in response to a supply voltage change. The example 500 includes an initial threshold voltage, VTH,0, corresponding to an initial supply voltage, and a subsequent threshold voltage, VTH,NEW, corresponding to a different supply voltage. Further included in the example 500 are theoretical voltage ramp signals, including an initial voltage ramp signal 510 corresponding to an initial ramp rate ρ0, and a subsequent voltage ramp signal 520 corresponding to a subsequent ramp rate ρNEW. The example 500 shows the ramp signals 510 and 520 having a cycle period T.
Referring again to the VCO circuit 200 shown in FIG. 2, a change in an initial supply voltage, such as to twice the initial supply voltage (e.g., a change from VDD to 2VDD), can occur at some time δt prior to the end of a cycle (i.e., before the period duration T elapses). The supply voltage change affects the threshold voltage used by the comparator circuit 230 to initiate discharge of the output capacitor 205, as discussed above in the discussion of FIG. 2.
In an example, the subsequent threshold voltage, VTH,NEW, can increase to twice the initial threshold voltage, or 2VTH,0. The ramp rate ρ will similarly increase by a factor of two when the supply voltage doubles. However, without further compensation, the remaining interval at of the period T will increase to another interval Δt, and can produce an error in the cycle duration. In the following cycle, however, this error can be disregarded because the ratio of the new threshold voltage and new ramp rate remains fixed. When a supply voltage change occurs in-phase with the period T, the VCO circuit 200 maintains the same period without the need for additional compensation circuitry.
In an example, a supply voltage for the VCO circuit 200 can double at time T/2. In this example, δt is T/2. A voltage δV, considered a residual voltage, represents a voltage difference between the voltage ramp signal magnitude and the threshold voltage. As described above, when the supply voltage doubles, the threshold voltage also doubles. For example, VTH,NEW=2VTH,0. In this example, after time T/2, δV increases in response to the supply voltage increase to yield δVNEW:




  
    
      
        
          δ
          ⁢
          
            
          
          ⁢
          
            V
            NEW
          
        
        =
        
          
            
              
                V
                
                  TH
                  ,
                  0
                
              
              2
            
            +
            
              (
              
                
                  V
                  
                    TH
                    ,
                    NEW
                  
                
                -
                
                  V
                  
                    TH
                    ,
                    0
                  
                
              
              )
            
          
          =
          
            
              3
              2
            
            ⁢
            
              V
              
                TH
                ,
                0
              
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




The ramp rate similarly increases by a factor of two when the supply voltage doubles. The new residual interval is thus given by:





  
    
      
        
          δ
          ⁢
          
            
          
          ⁢
          
            t
            NEW
          
        
        =
        
          
            
              
                3
                2
              
              ⁢
              
                V
                
                  TH
                  ,
                  0
                
              
            
            
              2
              ⁢
              
                ρ
                0
              
            
          
          =
          
            
              3
              2
            
            ⁢
            
              T
              2
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




To correct this interval, the slew rate of VTH can be restricted. For example, the VCO circuit 400 from the example of FIG. 4 includes the filter capacitor 206 to help restrict the slew rate of VTH.

The slew rate after the supply voltage change should be (VTH,NEW-VTH,0)/T to maintain a cycle period T. The filter capacitor 206 can be provided, as in the example of the VCO circuit 400, at the node where the threshold voltage is obtained. In some examples, the value of the filter capacitor 206 can be selected as a function of the period T, and the resistances of the resistors 203 and 204 of the resistive divider in the VCO circuit 400. For example, the value of the filter capacitor 206 can be selected to satisfy the relationship:




  
    
      
        
          C
          206
        
        =
        
          T
          ⁢
          
            
              R
              204
            
            
              R
              203
            
          
          ⁢
          
            (
            
              
                R
                203
              
              +
              
                R
                204
              
            
            )
          
        
      
    
    
      
        (
        15
        )
      
    
  




Referring again to FIG. 5, in an example, the supply voltage can change by a factor α at time φT. That is, VDD can be the initial supply voltage, and αVDD can be the subsequent supply voltage. In response to the supply voltage change, the ramp rate can be updated from an initial ramp rate ρ0 to αρ0, and the threshold voltage can be updated from an initial threshold voltage VTH,0 to αVTH,0. As shown in the example of FIG. 5, the remaining period at the time of the supply voltage transition can be (1−φ)T. In an example, to maintain the same period T even after the supply voltage transition, the new ramp rate αρo can be applied from the time φT for the remaining period (1−φ)T. The position of the slewed voltage, VTH,φ, at the end of the period is given by (1−φ)Tαρ+φVTH,0, which, in some examples, may not coincide with VTH,NEW until a subsequent cycle. When φ is 0, VTH,NEW=αVTH,0, and when φ is 1, VTH,NEW=VTH,0. The slew rate, σ, can thus be independent of φ, as given by:




  
    
      
        σ
        =
        
          
            
              
                
                  (
                  
                    1
                    -
                    φ
                  
                  )
                
                ⁢
                
                  T
                  ⁡
                  
                    (
                    
                      αρ
                      0
                    
                    )
                  
                
              
              +
              
                φ
                ⁢
                
                  
                
                ⁢
                
                  V
                  
                    TH
                    ,
                    0
                  
                
              
              -
              
                V
                
                  TH
                  ,
                  0
                
              
            
            
              
                (
                
                  1
                  -
                  φ
                
                )
              
              ⁢
              T
            
          
          =
          
            
              (
              
                α
                -
                1
              
              )
            
            ⁢
            
              ρ
              0
            
          
        
      
    
    
      
        (
        16
        )
      
    
  




In the example VCO circuit 400, when the resistive divider is stabilized, the current available at the filter capacitor 206 is (VDD−VTH,0)/R203. After a supply voltage change, an excess current at the time of the supply voltage change is (αVDD−VDD)/R203, and the resulting slew rate σ is:




  
    
      
        σ
        =
        
          
            
              
                α
                ⁢
                
                  
                
                ⁢
                
                  V
                  DD
                
              
              -
              
                V
                DD
              
            
            
              
                R
                203
              
              ⁢
              
                C
                206
              
            
          
          =
          
            
              
                V
                DD
              
              ⁡
              
                (
                
                  α
                  -
                  1
                
                )
              
            
            
              
                R
                203
              
              ⁢
              
                C
                206
              
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




Equating Equations (16) and (17), and recalling the relationships ρ0=VTH,0/T, and VTH,0=VDD,0(R203/(R203+R204)), the expression in Equation (15) for C206 can be provided by solving the following for C206:





  
    
      
        
          
            
              V
              
                DD
                ,
                0
              
            
            ⁡
            
              (
              
                α
                -
                1
              
              )
            
          
          
            
              R
              203
            
            ⁢
            
              C
              206
            
          
        
        =
        
          
            
              ρ
              0
            
            ⁡
            
              (
              
                α
                -
                1
              
              )
            
          
          =
          
            
              
                
                  (
                  
                    α
                    -
                    1
                  
                  )
                
                ⁢
                
                  V
                  
                    DD
                    ,
                    0
                  
                
              
              T
            
            ⁢
            
              
                R
                203
              
              
                
                  R
                  203
                
                +
                
                  R
                  204
                
              
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




Thus, a value for the filter capacitor 206 can be obtained as a function of the period and of the resistances of the resistive divider in the VCO circuit 400. The value for the filter capacitor 206, such as given by Equation (15), can provide a capacitance correction that can be used in the VCO circuit 400 to compensate for changes in the supply voltage VDD by modifying a voltage ramp slew rate.

The effective time constant for the slew between VTH,0 and VTH,NEW can be expressed as R∥C206, where R∥ is the parallel combination of R203 and R204. Referring again to Equation (16), an initial slew rate, σ0, can thus be expressed as VTH,0(α−1)/R∥C206. In some examples, therefore, a change in the supply voltage VDD that is applied at the onset of a new cycle produces a change in the final threshold voltage by a factor of (1/e)(αVTH,0), which accordingly decreases the threshold voltage-dependent period. However, this threshold error can be compensated, such as using comparator circuits and a second resistive divider to adjust the slew rate
FIG. 6 illustrates generally an example of a third VCO circuit 600 with comparator circuits configured to adjust a slew rate. The third VCO circuit 600 includes several of the same circuit elements as described above in the discussion of the VCO circuit 200 and the VCO circuit 400, and these elements are designated with the same numerals as used above. The third VCO circuit 600 can compensate for the above-mentioned threshold error by providing a more linear slew rate using the filter capacitor 206.
The third VCO circuit 600 includes a second resistive divider comprising fifth and sixth resistors 605 and 606. The resistive divider can be coupled to the supply node of the third VCO circuit 600 to receive the supply voltage VDD. The fifth resistor 605 can be proportional to the third resistor 203 by a factor Γ, and the sixth resistor 606 can be proportional to the fourth resistor 204 by the same factor Γ such that the divider ratio of the respective resistive divider networks is the same. In an example, the factor Γ is large and the divider current through the second resistive divider is small.
The third VCO circuit 600 includes a first tap node P1 between the third and fourth resistors 203 and 204, and a second tap node P2 between the fifth and sixth resistors 605 and 606. In an example, the threshold voltage used by the comparator circuit 230 can be received from the second tap node P2. Because the resistances of the fifth and sixth resistors 605 and 606 are fixed, the tap node remains substantially proportional to the supply voltage VDD over an expected operating range of VDD.
The third VCO circuit 600 can include a current source module 610, such as a constant DC current source, configured to source current to the filter capacitor 206. In an example, a current source IH is switchably coupled to the second tap node P2 using a first switch S1. The first switch S1 is driven by a comparator circuit ΔH, and the comparator circuit ΔH is coupled to the first and second tap nodes P1 and P2 and respective non-inverting and inverting inputs. In an example, IH is configured to provide a constant current equal to the supply voltage VDD divided by the series combination of the third and fourth resistors 203 and 204. That is, IH=VDD/(R203+R204). In an example, when the supply voltage VDD increases (e.g., α>1), the comparator circuit ΔH provides a control signal to the first switch S1 that couples the current source IH to the second tap node P2 to charge the filter capacitor 206.
The third VCO circuit 600 can include a current sink module 620, such as a constant DC current sink, configured to sink current from the filter capacitor 206. In an example, a current sink IL is switchably coupled to the second tap node P2 using a second switch S2. The second switch S2 is driven by a comparator circuit ΔL, and the comparator circuit ΔL is coupled to the first and second tap nodes P1 and P2 and respective inverting and non-inverting inputs. In an example, IL is configured to sink a constant current equal to the supply voltage VDD divided by the series combination of the third and fourth resistors 203 and 204. That is, IL=IH. In an example, when the supply voltage VDD decreases (e.g., α<1), the comparator circuit ΔL provides a control signal to the second switch S2 that couples the current sink IL to the second tap node P2 to sink current from, or discharge, the filter capacitor 206.
The current source module 610 and the current sink module 620 can be used to configure the third VCO circuit 600 to generate an approximately linear slew rate in the filter capacitor 206. For example, a slew error in the example of the third VCO circuit 600 can be based on the divider current through the second resistive divider (e.g., determined at least in part by the factor Γ), such as can be a smaller current than provided through the resistive divider comprising the third and fourth resistors 203 and 204. In an example, when the voltage at the filter capacitor 206 is approximately equal to the voltage at the second tap point P2, the current provided or sunk using the modules 610 and 620 can be switched off. In an example, the comparators ΔH and ΔL can be tunable hysteretic comparators configured to avoid actuation for an insignificant change in the supply voltage VDD (e.g., a change in VDD by less than a specified threshold amount).
Referring now to FIG. 7, an example of a method 700 includes generating, using a VCO circuit, a ramped pulse signal having a pulse slope that is proportional to a supply voltage. At 710, the method 700 includes providing a first current using a first circuit leg. The first current can be provided from or to a supply node that is coupled to multiple circuit legs (e.g., circuit paths between the supply node and a circuit reference or ground). The first current can be provided using a fixed or variable current or voltage source. In some examples, the first current is provided from a supply node that supplies current or voltage to one or more other circuits or circuit elements. For instance, the supply node can be configured to supply a current to an output stage of a power converter, such as shown in the example of FIG. 1.
At 720, the first current can be mirrored from the first circuit leg to a second circuit leg. The current can be mirrored directly (e.g., using a single pair of transistors configured as a current mirror), or indirectly, using one or more intervening current mirrors or other circuit elements. For example, referring to the VCO circuit 200 of FIG. 2, a current Id,213 can be mirrored to the circuit leg comprising the sixth p-type transistor 216 to generate an output voltage across the output capacitor 205. The mirroring is accomplished via several current mirrors, including the current mirror comprising the third and fourth p-type transistors 213 and 214, the current mirror comprising the first and second n-type transistors 221 and 222, and the current mirror comprising the fifth and sixth p-type transistors 215 and 216.
In an example, the current mirrored from the first circuit leg to the second circuit leg can be proportional to a voltage at the supply node. At 730, a portion of the first current from the first circuit leg can be sunk to maintain the second current at a level that is proportional to the supply voltage. For example, the voltage-controlled current circuit 410 can be provided, as in the example of FIG. 4, to increase the current through the third p-type transistor 213 (by an amount that is approximately equal to the gate-to-source voltage of the third p-type transistor 213 divided by the resistance of the resistor 201) such that the current in the second circuit leg is proportional to the voltage at the supply node, even at low voltage supply levels.
At 740, a portion of the first current in the first circuit leg can be mirrored in a third circuit leg. The portion of the first current mirrored in the third circuit leg can be used to adjust an operating frequency of the VCO. In some examples without the third circuit leg, the circuit is a fixed-frequency oscillator. The current in the third circuit leg can flow through a variable resistance, such as a voltage-controlled variable resistance provided by, for example, a differential pair of transistors.
At 750, a bias voltage in one of the transistors in the differential pair can be adjusted to update a frequency of the VCO. Adjusting the bias voltage can include maintaining one transistor gate voltage at a constant voltage while adjusting the transistor gate voltage of the other transistor. For example, the gate maintained at the constant voltage level can set an operating level of the differential pair, while the other gate voltage can control an oscillating frequency of the VCO.
At 760, an output capacitor can be charged (e.g., the output capacitor 205 of FIGS. 2 and 4). The output capacitor can be charged using the current in the second circuit leg, which can be adjusted using one or more current mirrors (e.g., by adjusting physical characteristics of the mirroring devices, or transistors, such as channel width or doping density, to adjust a current mirror ratio) or using the differential pair of transistors described above at 750. The output capacitor voltage can be generated as a ramped pulse signal having a pulse slope that is proportional to the supply voltage when the current in the second circuit leg is proportional to the supply voltage. The output capacitor can be controllably discharged, such as using a shunting switch controlled by a comparator circuit (e.g., the comparator circuit 230).
At 770, a threshold voltage can be provided to the comparator circuit. In some examples, the threshold voltage is a fixed or variable portion of the supply voltage. For example, the threshold voltage can be provided from a tap node in a resistive divider that is coupled to the supply node. In some examples, the threshold voltage is specified, or the threshold voltage is provided based on a voltage in one of the circuit legs, such as a voltage developed across a passive resistance in one of the circuit legs.
At 770, the voltage across the output capacitor can be monitored using the comparator circuit. The output capacitor voltage and the threshold voltage can be compared. At 780, when the output capacitor voltage is equal to all or a specified portion of the threshold voltage, the comparator circuit can provide a control signal to the discharge switch to discharge the output capacitor. When the output capacitor is discharged (e.g., fully or partially), the comparator circuit can update the discharge switch (e.g., open the switch) such that the output capacitor can charge over a new cycle. As the output capacitor is repeatedly charged and discharged, an oscillating output voltage comprising multiple pulses can be provided, and the pulses can have ramp portions with slopes that are proportional to the supply voltage.
VARIOUS NOTES & EXAMPLES
Example 1 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable medium including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use an output capacitor to provide an oscillating output voltage ramp pulse having a slope that is determined as a function of a magnitude of a supply voltage. Example 1 can include, among other things, a voltage-controlled oscillator (VCO), comprising a supply voltage node, configured to receive a supply voltage, and a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor. The VCO can include a discharge switch, coupled in parallel with the capacitor, and configured to discharge the capacitor according to an oscillation frequency of the oscillating output voltage. The VCO can include a first comparator circuit that is configured to provide, to a control terminal of the discharge switch, a control signal that is determined based on a comparison of the output voltage and a specified threshold voltage. In Example 1, the oscillating output voltage includes a ramp pulse having a ramp slope that is determined as a function of a magnitude of the supply voltage and that is capable of being adjusted independently of the oscillation frequency.
Example 2 can include, or can optionally be combined with the subject matter of Example 1, to optionally include the VCO, comprising a resistor providing the specified threshold voltage across the resistor, wherein the first comparator circuit is configured to compare the specified threshold voltage to the output voltage to operate the discharge switch to determine the output voltage slope as a function of the magnitude of the supply voltage, of a resistance of the resistor, and of a capacitance of the capacitor.
Example 3 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 or 2 to optionally include a voltage level shift circuit configured to receive the supply voltage and provide the specified threshold voltage referenced to and level-shifted from the supply voltage.
Example 4 can include, or can optionally be combined with the subject matter of Example 3, to optionally include, in the voltage level shift circuit, a diode-connected transistor.
Example 5 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 4 to optionally include a differential pair of transistors configured with respective inputs arranged to compare an oscillation frequency control input voltage to a reference voltage, wherein the differential pair is configured to directly or indirectly provide a current to the capacitor to affect the oscillation frequency.
Example 6 can include, or can optionally be combined with the subject matter of Example 5, to optionally include a current source/sink, configured to source or sink current to commonly connected source terminals of the differential pair of transistors, wherein a ratio of current provided in the current source/sink to a current provided to the capacitor determines the oscillation frequency.
Example 7 can include, or can optionally be combined with the subject matter of one or any combination of Examples 5 or 6 to optionally include a feedback circuit that includes the VCO, the feedback circuit including an input node coupled to receive and detect a frequency of the oscillating output voltage of the VCO, a frequency-to-voltage converter circuit, configured to provide the oscillation frequency control input voltage determined based on the detected frequency of the oscillating output voltage and a reference frequency, and an output node coupled to provide the oscillation frequency control input voltage to one of the transistors of the differential pair of transistors to adjust the oscillation frequency.
Example 8 can include, or can optionally be combined with the subject matter of one or any combination of Examples 5 through 7, to optionally include a pair of bipolar junction transistors as the differential pair of transistors.
Example 9 can include, or can optionally be combined with the subject matter of one or any combination of Examples 5 through 7, to optionally include, as the differential pair of transistors, a pair of field-effect transistors configured to operate in a weak inversion region.
Example 10 can include, or can optionally be combined with the subject matter of one or any combination of Examples 2 through 9, to optionally include a voltage-controlled resistance circuit, configured to directly or indirectly provide respective currents to the resistor and the capacitor to establish the oscillation frequency.
Example 11 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 10, to optionally include a voltage-controlled current circuit, including a diode-connected transistor configured to sink, from the supply voltage node, a current that is proportional to a magnitude of the supply voltage, and wherein the VCO output capacitor is charged using the current that is proportional to the magnitude of the supply voltage.
Example 12 can include, or can optionally be combined with the subject matter of Example 11 to optionally include the voltage-controlled current circuit, comprising a parallel circuit coupled to the resistor at a summing node, the parallel circuit configured to sink a current from the summing node in an amount substantially equal to a voltage between a source and a gate of the diode-connected transistor divided by a resistance of the resistor.
Example 13 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 12, to optionally include, in the VCO, a voltage divider coupled to the supply voltage node, wherein the specified threshold voltage is determined using a voltage received at a tap node in the voltage divider.
Example 14 can include, or can optionally be combined with the subject matter of Example 13 to optionally include a low pass filter configured to suppress a transient change in the voltage at the tap node due to a change in the supply voltage at the supply voltage node.
Example 15 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 14, to optionally include the discharge switch is configured to intermittently discharge the capacitor to provide a pulse-width modulated output voltage signal.
Example 16 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 15, to optionally include a switching power converter forward path including first and second switches, an inductor, and a converter output capacitor, wherein each of the first and second switches is controllably coupled to a respective driver circuit, and a converter output voltage is provided using the converter output capacitor, wherein the first switch is coupled to the supply voltage node of the VCO.
Example 17 can include, or can optionally be combined with the subject matter of Example 16 to optionally include the respective driver circuits are configured to operate in response to the oscillating output voltage from the VCO.
Example 18 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 17 to include, subject matter (such as an apparatus, a method, a means for performing acts, or a machine readable medium including instructions that, when performed by the machine, that can cause the machine to perform acts), such as can include a system, comprising a supply voltage node, configured to receive a supply voltage, a power converter forward path, including first and second switches, an inductor, and a first capacitor, wherein each of the first and second switches is controllably coupled to a respective driver circuit, wherein the first switch is coupled to the supply voltage node, and wherein a system output voltage is provided using the first capacitor, and a feedback path. In Example 18, the feedback path can include a pulse signal generator, including a phase detector and a voltage-controlled oscillator, wherein the voltage-controlled oscillator is configured to generate an oscillating output voltage comprising a pulse train, the pulse train comprising pulses having ramp slopes that are determined as a function of a magnitude of the supply voltage, and the oscillating output oscillating at a frequency determined by a signal from a phase detector. In Example 18, the feedback path can include a first comparator circuit, operable to provide an error voltage signal based on a comparison of a reference voltage and the system output voltage, and a second comparator circuit, operable to provide a control signal to the respective driver circuits based on a comparison of the error voltage signal and the oscillating output of the pulse signal generator.
Example 19 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 18 to include, subject matter (such as an apparatus, a method, a means for performing acts, or a machine readable medium including instructions that, when performed by the machine, that can cause the machine to perform acts), such as can include providing a ramped pulse signal using a voltage-controlled oscillator. Example 19 can include providing a first current to or from a supply through first and second circuit legs, generating a ramped pulse signal across a capacitor in the second circuit leg using a portion of the first current, providing a threshold voltage across a resistor in the first circuit leg using a portion of the first current, and controllably discharging the ramped pulse signal from the capacitor in response to a comparison of the capacitor voltage and the threshold voltage. In Example 19, the ramped pulse signal can be generated as a pulse having a slope that is a function of a value of the capacitor, of a value of the resistor, and of a voltage of the supply.
Example 20 can include, or can optionally be combined with the subject matter of Example 19 to optionally include mirroring a portion of the first current from the first circuit leg using a third circuit leg, the third circuit leg including a differential pair of transistors, adjusting a generating frequency of the ramped pulse signal across the capacitor using the differential pair of transistors to directly or indirectly provide a current to the capacitor to establish the oscillation frequency.
Example 21 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1 through 20 to include, subject matter (such as an apparatus, a method, a means for performing acts, or a machine readable medium including instructions that, when performed by the machine, that can cause the machine to perform acts), such as can include first and second resistive divider networks with respective first and second tap nodes. The first and second resistive divider networks can have substantially similar divider ratios. Example 21 can optionally include a filter capacitor configured to influence the specified threshold voltage. Example 21 can optionally include a current source switchably coupled to the filter capacitor. Example 21 can optionally include a comparator circuit configured to provide a control signal to a switch that couples the current source to the filter capacitor.
Each of these non-limiting examples can stand on its own, or can be combined in various permutations or combinations with one or more of the other examples.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

## Claims

1. An apparatus, comprising:
a voltage-controlled oscillator (VCO), comprising:
a supply voltage node, configured to receive a supply voltage;
a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor;
a discharge switch, coupled in parallel with the capacitor, the discharge switch configured to discharge the capacitor according to a control signal;

a first comparator circuit configured to provide the control signal to a control terminal of the discharge switch, the control signal determined based on a comparison of the oscillating output voltage and a specified threshold voltage; and
a current steering circuit configured to directly or indirectly provide a first current to the capacitor to influence an oscillation frequency of the oscillating output voltage, and the first current is a function of a VCO control signal and a reference signal received by the current steering circuit;
wherein the oscillating output voltage includes a ramp pulse having a ramp slope that is determined as a function of a magnitude of the supply voltage and that is capable of being adjusted independently of the oscillation frequency of the oscillating output voltage.

2. The apparatus of claim 1, wherein the VCO comprises a resistor providing the specified threshold voltage across the resistor, and wherein the first comparator circuit is configured to compare the specified threshold voltage to the output voltage to operate the discharge switch to determine the output voltage slope as a function of the magnitude of the supply voltage, of a resistance of the resistor, and of a capacitance of the capacitor.

3. The apparatus of claim 2, comprising a voltage level shift circuit configured to receive the supply voltage and provide the specified threshold voltage referenced to and level-shifted from the supply voltage.

4. The apparatus of claim 3, wherein the voltage level shift circuit includes a diode-connected transistor.

5. The apparatus of claim 2, wherein the current steering circuit includes a differential pair of transistors configured with respective inputs arranged to compare the VCO control signal and the reference signal.

6. The apparatus of claim 5, comprising:
a current source/sink, configured to source or sink current to commonly connected source terminals of the differential pair of transistors; and
wherein a ratio of current provided in the current source/sink to a current provided to the capacitor determines the oscillation frequency.

7. The apparatus of claim 5, comprising a feedback circuit that includes the VCO, the feedback circuit including:
an input node coupled to receive and detect a frequency of the oscillating output voltage of the VCO;
a frequency-to-voltage converter circuit, configured to provide the VCO control signal determined based on the detected frequency of the oscillating output voltage and a reference frequency; and
an output node coupled to provide the VCO control signal to one of the transistors of the differential pair of transistors to adjust the oscillation frequency.

8. The apparatus of claim 5, wherein the differential pair of transistors includes a pair of bipolar junction transistors.

9. The apparatus of claim 5, wherein the differential pair of transistors includes a pair of field-effect transistors configured to operate in a weak inversion region.

10. The apparatus of claim 2, wherein the current steering circuit is configured to directly or indirectly provide respective currents to the resistor and the capacitor to establish the oscillation frequency.

11. The apparatus of claim 1, comprising a voltage-controlled current circuit, including a diode-connected transistor configured to sink, from the supply voltage node, a current that is proportional to a magnitude of the supply voltage, and wherein the VCO output capacitor is charged using the current that is proportional to the magnitude of the supply voltage.

12. The apparatus of claim 11, wherein the VCO comprises a resistor providing the specified threshold voltage across the resistor, and wherein the voltage-controlled current circuit comprises a parallel circuit coupled to the resistor at a summing node, the parallel circuit configured to sink a current from the summing node in an amount substantially equal to a voltage between a source and a gate of the diode-connected transistor divided by a resistance of the resistor.

13. The apparatus of claim 1, wherein the VCO comprises a voltage divider coupled to the supply voltage node, and wherein the specified threshold voltage is determined using a voltage received at a tap node in the voltage divider.

14. The apparatus of claim 13, comprising a low pass filter configured to suppress a transient change in the voltage at the tap node due to a change in the supply voltage at the supply voltage node.

15. The apparatus of claim 1, wherein the discharge switch is configured to intermittently discharge the capacitor to provide a pulse-width modulated output voltage signal.

16. The apparatus of claim 1, comprising a switching power converter forward path including first and second switches, an inductor, and a converter output capacitor, wherein each of the first and second switches is controllably coupled to a respective driver circuit, and a converter output voltage is provided using the converter output capacitor, wherein the first switch is coupled to the supply voltage node of the VCO.

17. The apparatus of claim 16, wherein the respective driver circuits are configured to operate in response to the oscillating output voltage from the VCO.

18. A system, comprising:
a supply voltage node, configured to receive a supply voltage;
a power converter forward path, including first and second switches, an inductor, and a first capacitor, wherein each of the first and second switches is controllably coupled to a respective driver circuit, wherein the first switch is coupled to the supply voltage node, and wherein a system output voltage is provided using the first capacitor; and
a feedback path, comprising:
a pulse signal generator, including a phase detector and a voltage-controlled oscillator, wherein the voltage-controlled oscillator is configured to generate an oscillating output voltage comprising a pulse train, the pulse train comprising pulses having ramp slopes that are determined as a function of a magnitude of the supply voltage, and the oscillating output oscillating at a frequency determined by a signal from a phase detector;
a first comparator circuit, operable to provide an error voltage signal based on a comparison of a reference voltage and the system output voltage; and
a second comparator circuit, operable to provide a control signal to the respective driver circuits based on a comparison of the error voltage signal and the oscillating output of the pulse signal generator.

19. A method to provide a ramped pulse signal using a voltage-controlled oscillator, comprising:
providing a first current to or from a supply through first and second circuit legs;
generating a ramped pulse signal across a capacitor in the second circuit leg using a portion of the first current;
providing a threshold voltage across a resistor in the first circuit leg using a portion of the first current; controllably discharging the ramped pulse signal from the capacitor in response to a comparison of the capacitor voltage and the threshold voltage;
mirroring a portion of the first current from the first circuit leg using a third circuit leg, the third circuit leg including a current steering circuit; and
adjusting a generating frequency of the ramped pulse signal across the capacitor using the current steering circuit to provide a current to the capacitor to establish the oscillation frequency;
wherein the ramped pulse signal is generated as a pulse having a slope that is a function of a value of the capacitor, of a value of the resistor, and of a voltage of the supply.

20. The method of claim 19, comprising: wherein the mirroring the portion of the first current from the first circuit leg using the third circuit leg includes using a differential pair of transistors to provide the current to the capacitor, the current magnitude based on a difference between a VCO control signal and a reference signal provided to respective ones of the transistors.