# Patent

## Title
Thin form factor computational array cameras and modular array cameras

## Abstract

Systems and methods in accordance with embodiments of the invention implement modular array cameras using sub-array modules. In one embodiment, an X×Y sub-array module includes: an X×Y arrangement of focal planes, where X and Y are each greater than or equal to 1; and an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and image data output circuitry that is configured to output image data from the X×Y sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The current application claims priority to U.S. Provisional Application No. 61/768,523, filed Feb. 24, 2013, the disclosure of which is incorporated herein by reference.


FIELD OF THE INVENTION
The present invention generally relates to one-dimensional array cameras and also relates to the construction of modular array cameras using one-dimensional sub-array modules.
BACKGROUND
In response to the constraints placed upon a traditional digital camera based upon the camera obscura, a new class of cameras that can be referred to as array cameras has been proposed. Array cameras are characterized in that they include an imager array that has multiple arrays of pixels, where each pixel array is intended to define a focal plane, and each focal plane has a separate lens stack. Typically, each focal plane includes a plurality of rows of pixels that also forms a plurality of columns of pixels, and each focal plane is contained within a region of the imager that does not contain pixels from another focal plane. An image is typically formed on each focal plane by its respective lens stack. In many instances, the array camera is constructed using an imager array that incorporates multiple focal planes and an optic array of lens stacks.
SUMMARY OF THE INVENTION
Systems and methods in accordance with embodiments of the invention implement one-dimensional array cameras, as well as modular array cameras using sub-array modules. In one embodiment, a 1×N array camera module includes: a 1×N arrangement of focal planes, where N is greater than or equal to 2, each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×N arrangement of lens stacks, the 1×N arrangement of lens stacks being disposed relative to the 1×N arrangement of focal planes so as to form a 1×N arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene.
In another embodiment, N is greater than or equal to 3.
In yet another embodiment, N is 5.
In still another embodiment, the 1×N arrangement of cameras includes a green camera that is configured to image light corresponding with the green band of the visible spectrum.
In still yet another embodiment, the green camera is centrally disposed relative to the 1×N arrangement of cameras.
In a further embodiment, the lens stack of the green camera is adapted to image light corresponding with the green band of the visible spectrum.
In a still further embodiment, a red camera that is configured to image light corresponding with the red band of the visible spectrum and a blue camera that is configured to image light corresponding with the blue band of the visible spectrum are each disposed on either side of the centrally disposed green camera.
In a yet further embodiment, N is 7.
In a still yet further embodiment, the 1×N arrangement of cameras includes a green camera that is configured to image light corresponding with the green band of the visible spectrum, and that is centrally disposed relative to the 1×N arrangement of cameras.
In another embodiment, a red camera that is configured to image light corresponding with the red band of the visible spectrum and a blue camera that is configured to image light corresponding with the blue band of the visible spectrum are each disposed on either side of the centrally disposed green camera.
In yet another embodiment, N is 9.
In still another embodiment, the 1×N arrangement of cameras includes a green camera that is configured to image light corresponding with the green band of the visible spectrum, and that is centrally disposed relative to the 1×N arrangement of cameras.
In still yet another embodiment, a red camera that is configured to image light corresponding with the red band of the visible spectrum and a blue camera that is configured to image light corresponding with the blue band of the visible spectrum are each disposed on either side of the centrally disposed green camera.
In a further embodiment, the 1×N arrangement of focal planes is embodied within a monolithic structure.
In a still further embodiment, the 1×N arrangement of lens stacks is embodied within a monolithic structure.
In a yet further embodiment, the 1×N arrangement of focal planes and the 1×N arrangement of lens stacks are each embodied within the same monolithic structure.
In a still yet further embodiment, at least one camera is embodied within a single sub-array module, the sub-array module including: a 1×X arrangement of focal planes, where X is greater than or equal to 1, each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×X arrangement of lens stacks, the 1×X arrangement of lens stacks being disposed relative to the 1×X arrangement of focal planes so as to form a 1×X arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene.
In another embodiment, the sub-array module further includes interface circuitry that can allow the sub-array module to interface with another sub-array module so that it can at least transmit image data to another sub-array module or receive image data from another sub-array module.
In yet another embodiment, the 1×X arrangement of cameras is embodied within a single monolithic structure.
In still another embodiment N is 9 and X is 3.
In still yet another embodiment, the 1×9 arrangement of cameras are embodied within three 1×3 sub-array modules, each 1×3 sub-array module including: a 1×3 arrangement of focal planes, where each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×3 arrangement of lens stacks, the 1×3 arrangement of lens stacks being disposed relative to the 1×3 arrangement of focal planes so as to form a 1×3 arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene.
In a further embodiment, each sub-array module further includes interface circuitry that can allow the sub-array module to interface with another sub-array module so that it can at least transmit image data to another sub-array module or receive image data from another sub-array module.
In a still further embodiment, an array camera module further includes at least two sub-array modules, where each sub-array module includes: a 1×X arrangement of focal planes, where X is greater than or equal to 1, each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×X arrangement of lens stacks, the 1×X arrangement of lens stacks being disposed relative to the 1×X arrangement of focal planes so as to form a 1×X arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; where each of the at least two sub-array modules are adjoined to the interconnects of a single substrate, and can thereby interface with at least one other sub-array module.
In a yet further embodiment, each of the at least two sub-array modules further includes interface circuitry that can allow the respective sub-array module to interface with another sub-array module so that it can at least transmit image data to another sub-array module or receive image data from another sub-array module.
In a still yet further embodiment, the substrate is optically transparent.
In another embodiment, the substrate is glass.
In yet another embodiment, the substrate is ceramic.
In a further embodiment, a 1×X sub-array module includes: a 1×X arrangement of focal planes, where X is greater than or equal to 1, each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×X arrangement of lens stacks, the 1×X arrangement of lens stacks being disposed relative to the 1×X arrangement of focal planes so as to form a 1×X arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene.
In a yet further embodiment, the 1×X sub-array module further includes interface circuitry that can allow the sub-array module to interface with another sub-array module so that it can at least transmit image data to another sub-array module or receive image data from another sub-array module.
In a still further embodiment, the interface circuitry implements a MIPI CSI 2 interface.
In another embodiment, a 1×N array camera includes: a 1×N arrangement of focal planes, where N is greater than or equal to 2, each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and a 1×N arrangement of lens stacks, the 1×N arrangement of lens stacks being disposed relative to the 1×N arrangement of focal planes so as to form a 1×N arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and a processor that is configured to construct an image of the scene using image data generated by the 1×N array camera module.
In a further embodiment, an X×Y sub-array module includes: an X×Y arrangement of focal planes, where X and Y are each greater than or equal to 1, each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and image data output circuitry that is configured to output image data from the X×Y sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed.
In a yet further embodiment, X is 1.
In a still further embodiment, X and Y are each greater than 1.
In a still yet further embodiment, the arrangement of cameras are embodied within a single monolithic structure
In another embodiment, an M×N array camera includes: a plurality of X×Y sub-array modules, each including: an X×Y arrangement of focal planes, where X and Y are each greater than or equal to 1, each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and each focal plane does not include pixels from another focal plane; and an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and image data output circuitry that is configured to output image data from the sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed; where the plurality of X×Y sub-array modules define at least some of the cameras in an M×N arrangement of cameras; and a processor; where the processor is configured to construct an image of the scene using image data generated by each of the sub-array modules.
In yet another embodiment, X is 1 and M is 1.
In still another embodiment, the plurality of X×Y sub-array modules define an M×N arrangement of cameras.
In still yet another embodiment, an M×N array camera further includes circuitry that aggregates the image data generated by each of the sub-array modules into a single MIPI output, and provides the MIPI output to the processor so that the processor can construct an image of the scene.
In a further embodiment, an M×N array camera further includes a parallax disparity resolution module, where the parallax disparity resolution module is configured to receive image data captured by each sub-array module, implement a parallax detection and correction process on the received image data, and output the result for further processing.
In a still further embodiment, an M×N array camera further includes circuitry that converts the output of the parallax disparity resolution module into a single MIPI output, and provides the MIPI output to the processor so that the processor can construct an image of the scene.
In a still yet further embodiment, the parallax disparity resolution module includes a processor and memory, where the memory contains software to configure the processor to act as a parallax disparity resolution module.
In another embodiment, the parallax disparity resolution module is a hardware parallax disparity resolution module.
In still another embodiment, M and N are each greater than or equal to 2.
In yet another embodiment, at least two of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and can thereby output image data through the interconnects.
In still yet another embodiment, each of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and can thereby output image data through the interconnects.
In a further embodiment, the substrate is optically transparent.
In a still further embodiment, the substrate is glass.
In a still yet further embodiment, the substrate is ceramic.
In another embodiment, at least one sub-array module is embodied within a single monolithic structure.
In yet another embodiment, each sub-array module is embodied within a single respective monolithic structure.
In still another embodiment, an array camera further includes: a plurality of I/O devices, where each of the plurality of I/O devices interfaces with at least one camera: and a separate I/O block that includes circuitry configured to receive image data, aggregate the received image data, and output the aggregated image data to the processor so that the processor can construct an image of the scene; and where each of the plurality of I/O devices interfaces with the I/O block.
In still yet another embodiment, the number of I/O devices equals the number of sub-array modules, and each I/O device interfaces with a corresponding sub-array module.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 conceptually illustrates an array camera architecture in accordance with an embodiment of the invention.
FIG. 2 conceptually illustrates an imager array architecture in accordance with an embodiment of the invention.
FIG. 3 conceptually illustrates the construction of an array camera module in accordance with an embodiment of the invention.
FIGS. 4A and 4B illustrate 1×5 array camera modules in accordance with embodiments of the invention.
FIGS. 5A-5C illustrate 1×7 array camera modules in accordance with embodiments of the invention.
FIGS. 6A-6F illustrate 1×9 array camera modules in accordance with embodiments of the invention.
FIG. 7A illustrates a 1×3 sub-array module in accordance with an embodiment of the invention.
FIG. 7B illustrates another 1×3 sub-array module in accordance with another embodiment of the invention
FIGS. 8A-8K illustrate 1×3 sub-array modules in accordance with embodiments of the invention.
FIG. 9 illustrates how sub-array modules may be reconfigured in accordance with an embodiment of the invention.
FIGS. 10A-10C illustrate how 1×3 sub-array modules may be coupled to form array camera modules in accordance with embodiments of the invention.
FIGS. 11A-11B illustrates how 1×3 sub-array modules may interface with a receiving device and thereby implement an array camera in accordance with embodiments of the invention
FIG. 12 illustrate how sub-array modules may be coupled via a glass substrate with interconnects to form an array camera module in accordance with embodiments of the invention.
FIGS. 13A-13B illustrate how array camera modules formed from sub-array modules may utilize a parallax disparity resolution module in accordance with embodiments of the invention.
FIGS. 14A-14B illustrate how sub-array modules may be coupled to form an M×N array camera in accordance with embodiments of the invention.
FIG. 15 illustrates how sub-array modules may be coupled via a glass substrate with interconnects to form a two-dimensional array camera in accordance with embodiments of the invention
FIG. 16 illustrates a Pi filter group that may be utilized in accordance with embodiments of the invention.
FIGS. 17A-17B illustrates how sub-array modules may be coupled to form an array camera that employs Pi filter groups.
FIGS. 18A-18B illustrate 1×4 sub-array modules in accordance with embodiments of the invention.
FIGS. 19A-19B illustrate how 1×4 sub-array modules may be coupled to form an M×N array camera in accordance with embodiments of the invention
FIGS. 20A-20D illustrate 1×5 sub-array modules in accordance with embodiments of the invention.
FIGS. 21A-21B illustrate how 1×5 sub-array modules may be coupled to form an M×N array camera in accordance with embodiments of the invention.
FIG. 22 illustrates a two-dimensional array camera fabricated from multiple two-dimensional sub-array modules.



DETAILED DESCRIPTION
Turning now to the drawings, systems and methods for implementing one-dimensional array cameras and modular array cameras are disclosed. Processes for constructing array cameras using lens stack arrays are described in U.S. patent application Ser. No. 12/935,504, entitled “Capturing and Processing of Images Using Monolithic Camera Array with Heterogeneous Imagers”, Venkataraman et al., which is incorporated herein by reference in its entirety. The monolithic array camera modules illustrated in U.S. patent application Ser. No. 12/935,504 can be constructed from an optic array of lens stacks—each lens stack in the array defining an optical channel—and an imager array including a plurality of focal planes corresponding to the optical channels in the optic array. The combination of a lens stack and its corresponding focal plane can be understood to be a ‘camera’ (as opposed to an ‘array camera’). Typically, array cameras capture image data that can be used to form multiple images of a single scene using their constituent cameras, and process the image data to yield a single image of the scene with improved image properties.
U.S. patent application Ser. No. 12/935,504 discloses many two-dimensional array camera schemes. However, such two-dimensional embodiments may be inapplicable in a number of desirable applications. For example, a consumer electronics device, such as a tablet or smartphone, may benefit from the use of an array camera with a distinctly thin form factor such that it would be able to fit within the device's bezel.
Many embodiments of the invention utilize one-dimensional array camera modules. One-dimensional array camera modules are advantageous insofar as they may accommodate distinct form factor requirements, and are further advantageous in that they may ease processing requirements as compared with two-dimensional array cameras (e.g. they simplify parallax disparity resolution calculations). In many embodiments, 1×5 array camera modules are utilized in the construction of an array camera. In several embodiments, a 1×5 array camera module is utilized that includes a central narrow spectral band green camera (i.e. a camera configured to image light that falls within the ‘green’ band of the visible spectrum, which can be achieved, for example, where the corresponding lens stack is configured to focus light that falls within the ‘green’ band of the visible spectrum onto the corresponding focal plane), and adjacent narrow spectral band blue and red cameras on either side of the central narrow spectral band green camera. In a number of embodiments, 1×7 array camera modules are utilized in the construction of array cameras. In several embodiments, a 1×7 array camera module includes a central narrow spectral band green camera, adjacent narrow spectral band blue and red cameras on either side of the central narrow spectral band green camera, and two periphery narrow spectral band green cameras.
In many embodiments, 1×9 array camera modules are utilized in the construction of an array camera. A 1×9 array camera module can be preferable to either a 1×7 or a 1×5 array camera module since a 1×9 array camera module can capture more image data. 1×9 array camera modules may include narrow spectral band green, blue, and red cameras, full visual spectrum cameras, and/or near-infrared (near-IR) cameras, which are useful for imaging in low lighting conditions. In many embodiments, a 1×9 array camera module includes more narrow spectral band green cameras than either narrow spectral band blue, narrow spectral band red, or near-IR cameras.
In many embodiments, one-dimensional array camera modules are constructed that do not use narrow spectral band cameras; in many embodiments one-dimensional array camera modules are constructed that employ Bayer filters to facilitate the imaging of a scene.
Although one-dimensional array cameras may be beneficial in numerous applications, their manufacture can be challenging. Specifically, components for one-dimensional array cameras (e.g. the lenses and the corresponding sensor) are typically manufactured on wafers, but the elongated nature of the components may not be conducive to optimizing wafer space. For example, in the manufacture of a one-dimensional lens array, the periphery of the wafer used in the manufacture may contain significant unused space that, because of the elongated shape of lens array, cannot accommodate further lens arrays. In other words, wafers may be more efficient in the manufacture of components that are more ‘square’ in shape than ‘elongated.’
In many embodiments of the invention, array cameras are constructed using sub-array modules. Each of the sub-array modules are configured to interface with other sub-array modules so that data can pass between the sub-array modules, enabling a processor to communicate with multiple sub-array modules via an interface with one of the sub-array modules. The dies used in the construction of sub-array modules may be less elongated as compared with the dies utilized in the construction of the aforementioned one-dimensional array camera modules, and can therefore better utilize wafer space. In several embodiments, a 1×3 sub-array module is utilized that includes input and output interface circuitry, which allow the sub-array module to couple with other sub-array modules. In many embodiments, a sub-array module including a single camera is utilized. The interface circuitry can further allow coupled sub-array modules to transmit and receive data including image data and/or instructions from a processor with one another. The image data from one of the sub-array modules may be read out by a processor. The interface circuitry may employ any interface protocol including Mobile Industry Processor Interface Alliance (MIPI) Camera Serial Interface 2(c) interface format (the “MIPI interface format”) or a Standard Mobile Imaging Architecture (“SMIA”) format. The 1×3 modular array cameras may include constituent narrow spectral band green, blue, or red cameras and may also include near-IR cameras.
Using sub-array modules to construct array cameras can provide numerous advantages. First, the manufacture of sub-array modules can result in a greater yield as compared with the manufacturing yield of longer one-dimensional array camera modules since sub-array module components may more efficiently utilize wafer space. Additionally, their manufacture can also result in comparatively greater homogeneity between sub-array modules since sub-array modules are less intricate as compared with longer one-dimensional array camera modules or two-dimensional array camera modules. Moreover, sub-array modules are versatile insofar as they can be used to construct array cameras of any specified dimension.
One-dimensional array camera modules and sub-array modules in accordance with embodiments of the invention are discussed further below.
Array Camera Architecture
Array cameras in accordance with many embodiments of the invention can include an array camera module and a processor. The array camera module can include an array of cameras. An array camera module can include an imager array, which is a sensor that includes an array of focal planes. Each focal plane includes an array of pixels used to capture an image formed on the focal plane by a lens stack. The focal plane can be formed of, but is not limited to, traditional CIS (CMOS Image Sensor), CCD (charge-coupled device), quantum film image sensors, high dynamic range sensor elements, multispectral sensor elements and various alternatives thereof. In many embodiments, the pixels of each focal plane have similar physical properties and receive light through the same lens stack. Furthermore, the pixels in each focal plane may be associated with the same color filter. In a number of embodiments, at least one of the focal planes includes a Bayer-pattern filter. In several embodiments, the focal planes are independently controlled. In other embodiments, the operation of the focal planes in the imager array is controlled via a single set of controls. Array cameras are discussed in U.S. patent application Ser. No. 13/106,797 entitled “Architectures for imager arrays and array cameras” and U.S. patent application Ser. No. 12/952,106 entitled “Capturing and processing of images using monolithic camera array with heterogenous imagers” the disclosure of both applications is hereby incorporated by reference in its entirety.
An array camera architecture that can be used in a variety of array camera configurations in accordance with embodiments of the invention is illustrated in FIG. 1. The array camera 100 includes an array camera module 102 that is configured to transmit 106 image data to a receiving device 108 via an interface format involving the transmission of additional data describing the transmitted image data. The array camera module 102 includes an array of cameras 104. The cameras 104 in the array camera module 102 are formed from the combination of a lens stack and a focal plane. The array camera module 102 can include an optic array of lens stacks and an imager array of focal planes. These multiple cameras 104 may be active or inactive at any given time. The image data captured by these multiple cameras may be transmitted from the focal planes of each camera to a processor. The focal planes may have different imaging characteristics, such as varying exposure times, start times, and end times. Therefore, the timing of the transmission of the image data captured by each focal plane can vary. Accordingly, the imager array can transmit additional data describing the image data to enable a device receiving the image data to appropriately reconstruct images from the received image data. The transmission of array camera image data is disclosed in U.S. patent application Ser. No. 13/470,252, entitled “Systems and Methods for Transmitting and Receiving Array Camera Image Data,” the disclosure of which is hereby incorporated by reference.
In many embodiments, the array camera 100 captures images using a plurality of cameras 104, which can have different imaging characteristics. The array camera 100 can separately control each of the cameras to obtain enhanced image capture and/or to enhance processes such as (but not limited to) super-resolution processes that may be applied to the captured images. For example, each pixel of
a focal plane may capture different wavelengths of light, or may capture the intensity of light, varying exposure times, start times, or end times. Once the array camera 100 has commenced capturing image data using the pixels on the imager array, the focal planes can commence transmitting the image data captured using the pixels to a receiving device 108. The image data captured by different cameras can be interleaved for transmission to a receiving device 108 that includes interface circuitry configured to receive image data. In many embodiments, the interface circuitry is implemented in hardware and/or using a processor. The receiving device 108 can then organize the captured image data from the received packet and appropriately combine the image data to process and/or reconstruct the image(s) captured by one or more of the focal planes in the imager array.
In the illustrated embodiment, image data from multiple images of a scene can be captured by the array camera module 102. As the image data is captured, the array camera module 102 transmits 106 the image data to a receiving device 108. The array camera module 102 transmits the image data using a small number of local data storage cells on the array camera module 102 that store the captured image data following capture by the cameras. In the illustrated embodiment, the array camera module 102 manages the capture and transmission of image data so that the captured image data stored in the storage cells is transmitted by the imager array of the array camera module 102 in the time taken to capture and load the next set of image data into the storage cells. In this way, the array camera module can continuously buffer and transmit image data using a number of local data storage cells that is less than the total number of pixels in the array camera module.
In many embodiments, a line of image data transmitted by an imager array can be considered to equal the number of pixels in a row of a focal plane multiplied by the number of focal planes. In several embodiments, the clock frequency of transmitter circuitry on the imager array is set to a desired output data rate and the internal focal plane pixel rate is set to 1/N the desired output data rate (where N is the total number of focal planes). In many image transmission protocols, once a start of line condition is sent, all of image data is transmitted without interrupt until the end of line. Accordingly, a sufficient number of data storage cells and a buffering mechanism can be developed that starts transmission of pixels once there are sufficient pixels stored such that all of the pixels will have been captured and transmitted by the time the end of the line of image data is reached. If, for example, an imager array including 4 focal planes (as in a 1×4 array) transmits image data from all focal planes, then there is very little data storage utilized prior to the start of focal plane readout, because the data is transmitted at approximately the rate that at which it is being read. If, however, the same imager array only has one active imager, then almost all of the pixels from a row of the focal plane are stored since the buffer is being read 4 times as fast as it is being written. Therefore, the data storage requirement would be one row of pixels (i.e. 1⁄4th of a line of image data). When three focal planes are active, 1/the data from the three focal planes is buffered before transmission commences to avoid underflow. Therefore, the total number of data storage cells utilized is equal to the number of pixels in three quarters of a row of one of the focal planes in this example. The above examples illustrate how the data storage requirements of an imager array can vary based upon the number of active focal planes. In many embodiments, the total number of storage cells within an imager array is less than a quarter of a line of image data. In several embodiments, the total number of storage cells within an imager array is equal to a line of image data. In several embodiments, the total number of data storage cells is between a quarter of a line of image data and a full line of image data. In a number of embodiments, the total number of storage cells is equal to or greater than a line of image data. When the array camera module transmits the captured image data, the incorporation of additional data describing the image data enables a peripheral device receiving the image data to reconstruct the images captured by each active camera in the imager array 102.
Imager arrays in accordance with many embodiments of the invention are configured to output image data via an interface format that accommodates the transfer of image data captured via multiple focal planes. In several embodiments, the imager array is configured to transmit captured image data in accordance with an interface format that is compatible with standard interface formats, such as (but not limited to) the MIPI CSI-2 interface format (MIPI interface format), the Camera Link interface format, and any of the Universal Serial Bus (USB) interface formats or FireWire interface formats. When image data captured from multiple focal planes is output by the imager array, the device receiving the image data is faced with the task of assembling the image data into a plurality of images of a scene.
Although specific array camera system architectures are discussed above for constructing array cameras including 1×N arrays of cameras, any of a variety of system architectures for array cameras including 1×N arrays of cameras can be utilized as appropriate to the requirements of a specific application in accordance with embodiments of the invention. Imager array architectures are discussed below in greater detail.
Imager Array Architectures
An imager array in accordance with an embodiment of the invention is illustrated in FIG. 2. The imager array 200 includes a focal plane array core 202 that includes a 1×N array of focal planes 204 and all analog signal processing, pixel level control logic, signaling, and analog-to-digital conversion circuitry. The imager array also includes focal plane timing and control circuitry 206 that is responsible for controlling the capture of image information using the pixels. For example, in some embodiments, the focal plane timing and control circuitry 206 can synchronize the capture of image data by the focal planes such that active focal planes capture image data from a scene simultaneously. In many embodiments, the focal plane timing and control circuitry 206 causes the active focal planes to capture image data from a scene in a particular controlled sequence. In a number of embodiments, the focal plane timing and control circuitry 206 utilizes reset and read-out signals to control the integration time of the pixels. In several embodiments, any of a variety of techniques can be utilized to control integration time of pixels and/or to capture image information using pixels. In many embodiments, the focal plane timing and control circuitry 206 provides flexibility of image information capture control, which enables features including (but not limited to) high dynamic range imaging, high speed video, and electronic image stabilization. In various embodiments, the imager array 200 includes power management and bias generation circuitry 208. The power management and bias generation circuitry 208 provides current and voltage references to analog circuitry such as the reference voltages against which an ADC would measure the signal to be converted against. In many embodiments, the power management and bias circuitry also includes logic that turns off the current/voltage references to certain circuits when they are not in use for power saving reasons. In several embodiments, the imager array includes dark current and fixed pattern (FPN) correction circuitry 210 that increases the consistency of the black level of the image data captured by the imager array and can reduce the appearance of row temporal noise and column fixed pattern noise. In several embodiments, each focal plane includes reference pixels for the purpose of calibrating the dark current and FPN of the focal plane and the control circuitry can keep the reference pixels active when the rest of the pixels of the focal plane are powered down in order to increase the speed with which the imager array can be powered up by reducing the need for calibration of dark current and FPN. In many embodiments, the SOC imager includes focal plane framing circuitry 212 that packages the data captured from the focal planes into a container file and can prepare the captured image data for transmission. In several embodiments, the focal plane framing circuitry 212 includes information identifying the focal plane and/or group of pixels from which the captured image data originated. In a number of embodiments, the imager array 200 also includes an interface for transmission of captured image data to external devices. In the illustrated embodiment, the interface is a MIPI CSI 2 output interface supporting four lanes that can support read-out of video at 30 fps from the imager array and incorporating data output interface circuitry 214, interface control circuitry 216 and interface input circuitry 218. Typically, the bandwidth of each lane is optimized for the total number of pixels in the imager array and the desired frame rate. The use of various interfaces including the MIPI CSI 2 interface to transmit image data captured by an array of imagers within an imager array to an external device in accordance with embodiments of the invention is described in U.S. patent application Ser. No. 13/470,252, cited to and incorporated by reference above.
An imager array in accordance with embodiments of the invention can include a single controller that can separately sequence and control each focal plane. Having a common controller and I/O circuitry can provide important system advantages including lowering the cost of the system due to the use of less silicon area, decreasing power consumption due to resource sharing and reduced system interconnects, simpler system integration due to the host system only communicating with a single controller rather than M×N controllers and read-out I/O paths, simpler array synchronization due to the use of a common controller, and improved system reliability due to the reduction in the number of interconnects.
Additionally, an imager array in accordance with embodiments of the invention may include a parallax disparity resolution module 220 that can determine disparity between pixels in different images captured by the camera array using parallax detection processes similar to those described in U.S. Provisional Patent Application Ser. No. 61/691,666 entitled “Systems and Methods for Parallax Detection and Correction in Images Captured Using Array Cameras” to Venkataraman et al., the disclosure of which is incorporated by reference herein in its entirety. In particular, as will be elaborated on below in the section on “One-Dimensional Array Camera Modules”, in some embodiments, the processing requirements for a parallax disparity resolution calculation may be sufficiently low that the process may be computed by the imager array circuitry.
Although specific components of an imager array architecture are discussed above with respect to FIG. 2, any of a variety of imager arrays can be constructed in accordance with embodiments of the invention that enable the capture of images of a scene at a plurality of focal planes in accordance with embodiments of the invention. Array camera modules that utilize imager arrays are discussed below.
Array Camera Modules
Array camera modules in accordance with many embodiments of the invention include the combination of an optic array including a 1×N array of lens stacks and an imager array that includes a 1×N array of focal planes. Each lens stack in the optic array defines a separate optical channel. The optic array may be mounted to an imager array that includes a focal plane for each of the optical channels, where each focal plane includes an array of pixels or sensor elements configured to capture an image. When the optic array and the imager array are combined with sufficient precision, the array camera module can be utilized to capture image data from multiple images of a scene that can be read out to a processor for further processing, e.g. to synthesize a high resolution image using super-resolution processing. For example, each of the cameras in an array camera module can capture image data of a scene reflecting a sub-pixel shifted view of the scene—i.e. relative to the corresponding image formed by at least one other camera (e.g. the lens stack of each camera can have a field-of-view that is shifted with respect to the field-of-view of each other camera so that each shift includes a sub-pixel shifted view of the scene); hence, the aggregated image data can embody sufficient sampling diversity to enable the implementation of super-resolution processes that can be used construct an enhanced image of the scene using the aggregated image data. In other words, each lens stack can form an image of a scene onto a corresponding focal plane, and thereby generate image data, from a slightly different viewpoint relative to an image formed by each of the other lens stacks, such that the images formed of the scene by each of the lens stacks contain non-redundant information of about the scene. Hence, the non-redundant information can be used in the construction of a super-resolved image.
In many embodiments, the optics in an array camera module are designed to be able to resolve images to a sufficient extent such that the super-resolution processes can be implemented. For example, in many instances, the MTF of the optics is able to resolve variation in intensity at the spatial resolution of the image that is to result from implemented super-resolution processes (e.g. as opposed to the spatial resolution of the image that can be formed by a single respective camera within an array camera module).
It should be noted that although ‘arrays of lens stacks’ and ‘arrays of focal planes’ are referenced, it is not meant to be suggested that such arrays are necessarily monolithic structures. In many instances a plurality of distinct lens stacks are disposed relative to one-another to form a 1×N array of lens stacks; similarly, in many instances a plurality of distinct focal planes are disposed relative to one-another to form a 1×N array of focal planes. In general, a plurality of lens stacks, and a plurality of focal planes can be adjoined in any suitable way to construct a 1×N array camera module in accordance with embodiments of the invention. In some instances, the focal planes and/or lens stacks are embodied within monolithic structures.
An exploded view of an array camera module formed by combining a lens stack array with a monolithic sensor including an array of focal planes in accordance with an embodiment of the invention is illustrated in FIG. 3. The array camera module 300 includes an optic array 310 including 1×N distinct lens stacks forming N separate apertures and an imager array 330 that includes a 1×N array of focal planes 340. Each lens stack 320 in the optic array 310 creates an optical channel that resolves an image on one of the focal planes 340 on the imager array 330. Each of the lens stacks 320 may be of a different type. In several embodiments, the optical channels are used to capture images of different portions of the wavelength of light spectrum (e.g. using color filters, located either within the lens stack or on the sensor) and the lens stack in each optical channel is specifically optimized for the portion of the spectrum imaged by the focal plane associated with the optical channel.
In many embodiments, the array camera module 300 includes lens stacks 320 having one or multiple separate optical lens elements axially arranged with respect to each other. Optic arrays of lens stacks 310 in accordance with several embodiments of the invention include one or more adaptive optical elements that can enable the independent adjustment of the focal length of each lens stack and/or later shifting of the centration of the refractive power distribution of the adaptive optical element. The use of adaptive optical elements is described in U.S. patent application Ser. No. 13/650,039, entitled “Lens Stack Arrays Including Adaptive Optical Elements”, filed Oct. 11, 2012, the disclosure of which is incorporated by reference herein in its entirety.
In several embodiments, the array camera module employs wafer level optics (WLO) technology. WLO is a technology that encompasses a number of processes, including, for example, molding of lens arrays on glass wafers, stacking of those wafers (including wafers having lenses replicated on either side of the substrate) with appropriate spacers, followed by packaging of the optics directly with the imager into a monolithic integrated module. The WLO procedure may involve, among other procedures, using a diamond-turned mold to create each plastic lens element on a glass substrate. More specifically, the process chain in WLO generally includes producing a diamond turned lens master (both on an individual and array level), then producing a negative mold for replication of that master (also called a stamp or tool), and then finally forming a polymer replica on a glass substrate, which has been structured with appropriate supporting optical elements, such as, for example, apertures (transparent openings in light blocking material layers), and filters. Although the construction of lens stack arrays using WLO is discussed above, any of a variety of techniques can be used to construct lens stack arrays, for instance those involving precision glass molding, polymer injection molding or wafer level polymer monolithic lens processes.
Although certain array camera module configurations have been discussed above, any of a variety of array camera modules that utilize lens stacks and focal planes may be implemented in accordance with embodiments of the invention. One-dimensional array camera modules are discussed below.
One-Dimensional Array Camera Modules
In many embodiments, one-dimensional (or 1×N) array camera modules are utilized in the construction of array cameras. One-dimensional array camera modules can provide a number of benefits. For instance, one-dimensional array camera modules can enable the construction of array cameras having distinctly thin form factors. Such array cameras may be useful in a host of applications. For example, array cameras having a thin form factor may be incorporated within the bezel of a consumer electronics device such as a laptop, a tablet, or a smart phone, and may further be incorporated within a pair of eye glasses.
Additionally, array cameras that incorporate one-dimensional array camera modules are advantageous insofar as they may require less processing and/or memory requirements as compared to two-dimensional (or M×N) array cameras. For example, array cameras typically employ a parallax detection and correction process in order to facilitate the imaging of a scene. Generally, the process is meant to address the fact that the relative positioning of objects in a scene may appear to vary from the respective viewpoints of different cameras within an array camera module. In two-dimensional array cameras, this technique can be processor intensive and involve significant data storage requirements related to searches for corresponding pixels along epipolar lines (other than just horizontal or vertical) between cameras located in different rows and/or columns within the array camera module. Array camera modules typically pass image data to a processor by starting with image data captured by pixels in a first row of a focal plane and then advancing to the next row of pixels and reading out image data from pixels within the next row of pixels. The read out of image data from pixels within a focal plane can also be interspersed with the readout of image data from pixels within other focal planes. Note that with this technique, because image data is being passed to the processor along the rows of the focal planes, searches for corresponding pixels along vertical or diagonal epipolar lines, for example during a parallax detection and correction process of a two-dimensional array camera, involve the processor storing substantial amounts of image data across multiple rows of image data captured by a focal plane. In other words, whereas a parallax detection and correction process may be employed along the ‘row’ direction as soon as the image data from a respective row of focal planes has been read out to a processor, the parallax detection and correction process along the column direction cannot be employed until multiple rows of image data has been read out to the processor. Consequently, image data across multiple rows of pixels must be stored in order to complete parallax detection and correction processes. This may result in larger storage requirements that may be prohibitive of a system-on-a-chip (SOC) type solution, e.g. where the parallax disparity resolution is built into the imager array. However, because one-dimensional array cameras do not necessarily employ parallax correction and detection processes in two directions, the processing and/or memory requirements can be substantially reduced. Thus, with lesser processing and/or memory requirements, system-on-a-chip (SOC) type solutions may be enabled.
Additionally, one-dimensional array camera modules may provide greater manufacturing yield as compared with two dimensional array camera modules, because one-dimensional array camera modules may have less cameras. Generally, the more cameras an array camera module has, the more difficult it is to directly manufacture because it is more likely to have faulty sensors and/or faulty lens stacks.
A 1×5 array camera module in accordance with embodiments of the invention is illustrated in FIG. 4A. In particular, the array camera module includes a central narrow spectral band green camera (G), adjacent narrow spectral band blue cameras (B), and periphery narrow spectral band red cameras (R). Color filters may be employed to achieve the respective narrow spectral band cameras. The color filters may be located either within the lens stack or on the sensor. A narrow spectral band green camera may be centrally placed to accommodate the fact that humans are most sensitive to green light. Narrow spectral band red and blue cameras may be placed on either side of the central narrow spectral band green camera—this configuration may counteract any occlusion that may occur as a result of any obstructing foreground objects. For example, in the case of an obstructing foreground object, areas of the scene immediately surrounding the foreground object as seen by the central camera may not be seen by the cameras on one of the two sides of the central green camera. However, if both narrow spectral band red and blue cameras are placed on either side of the central green camera, color imaging data can be obtained from the scene irrespective of such obstruction caused by the foreground object, and uniform spectral coverage is thereby provided. FIG. 4B is similar to FIG. 4A except that the narrow spectral band red cameras are adjacent to a central narrow spectral band green camera, and narrow spectral band blue cameras enclose the configuration. Note that although two particular configurations of 1×5 array camera modules are illustrated, any number of configurations may be employed all in accordance with embodiments of the invention. For example, in some embodiments near-IR cameras (N), which facilitate the imaging of scenes with low-lighting, may be employed, and in a number of embodiments, full visual spectrum cameras (P) are employed. Note that where full visual spectrum cameras are employed, Bayer filters, which are typically implemented on the sensor, may be utilized to obtain color information.
By increasing the number of a particular type of narrow spectral band camera (e.g. Green), super-resolution processes can be employed to greater effect. A 1×7 array camera module in accordance with embodiments of the invention is illustrated in FIGS. 5A-5C. As illustrated, a 1×7 array camera module may employ more narrow spectral band green cameras than narrow spectral band blue or narrow spectral band red cameras. This may be to accommodate the fact that humans are most sensitive to green light. In the illustrated embodiments, the array camera module includes a central narrow spectral band green camera and periphery narrow spectral band green cameras, and narrow spectral band red and blue cameras. The cameras may be symmetrically distributed or they may be asymmetrically distributed. In the embodiments illustrated in FIGS. 5A and 5B, the narrow spectral band cameras are symmetrically distributed. In the embodiment illustrated in FIG. 5C, the narrow spectral band cameras are asymmetrically distributed. The inclusion of multiple red and blue cameras uniformly distributed around the central green camera reduces the likelihood of color artifacts related to occlusions by foreground objects. The presence of multiple green cameras in an array having sub-pixel shifted views of the scene to provide sampling diversity enables the application of super-resolution processes to the captured image data to recover a higher resolution image of the scene. As before, although three particular configurations of 1×7 array camera modules are illustrated, any number of configurations may be employed all in accordance with embodiments of the invention. For example, in some embodiments near-IR cameras may be employed, and in a number of embodiments, full visual spectrum cameras are employed. As before, where full visual spectrum cameras are employed, Bayer filters may be utilized to obtain color information.
A 1×9 array camera module in accordance with embodiments of the invention is illustrated in FIGS. 6A-6F. A 1×9 array camera module may be more preferable than either a 1×7 array camera module or a 1×5 array camera module since it provides more image data. As before, a 1×9 array camera module may employ more narrow spectral band green cameras than narrow spectral band blue or narrow spectral band red cameras. The inclusion of multiple red and blue cameras distributed around the central green camera reduces the likelihood of color artifacts related to occlusions by foreground objects. The presence of multiple green cameras in an array having sub-pixel shifted views of the scene to provide sampling diversity enables the application of super-resolution processes to the captured image data to recover a higher resolution image of the scene. Also as before, although six particular configurations of 1×9 array camera modules are illustrated, any number of configurations may be employed all in accordance with embodiments of the invention. For example, in some embodiments, narrow spectral band green cameras are not disposed along the periphery of the array camera module.
Although particular one-dimensional array camera modules have been discussed, an array camera module with any number of cameras may be implemented in accordance with embodiments of the invention. For instance, 1×4 array camera modules and 1×5 array camera modules may be implemented. Sub-array modules that may be used to construct one-dimensional array camera modules are discussed below.
Sub-Array Modules
Much of the discussion above describes the construction of array cameras using a single monolithic array camera module. In many embodiments, sub-array modules are used in the construction of array cameras. Sub-array modules may be configured to interface with other sub-array modules so that data can pass between the sub-array modules, thereby enabling a processor to interact with multiple coupled sub-array modules via an interface with one of the sub-array modules. In this way, sub-array modules can couple with other sub-array modules to enable the fabrication of array cameras of any number of specified dimensions and characteristics. In many embodiments, sub-array modules do not couple with one-another, but instead interact directly or indirectly (e.g. via a bus) with a receiving device (e.g. a processor). Accordingly, sub-array modules of this variety can also enable the modular construction of an array camera of any number of specified dimensions and characteristics.
The use of sub-array modules in the construction of array cameras can provide a number of benefits. For example, the use of sub-array modules to construct array cameras can improve manufacturing yield relative to the direct fabrication of an array camera module. In particular, although one-dimensional array camera modules may be beneficial in numerous applications, their manufacture can be challenging. Specifically, components for one-dimensional array cameras (e.g. the lenses and the corresponding sensor) are typically manufactured on wafers, but the elongated nature of the components may not be conducive to optimizing wafer space. In many instances, in the manufacture of a one-dimensional lens array, the periphery of the wafer used in the manufacture may contain significant unused space that, because of the elongated shape of a lens array, cannot accommodate further lens arrays. In other words, wafers are may be more efficient in the manufacture of components that are more ‘square’ in shape than ‘elongated.’ However, sub-array modules that are used in the construction of an array camera module may be less elongated than the array camera module. Hence, sub-array modules can better optimize wafer space during manufacture.
Moreover, the manufacture of sub-array modules is also beneficial since they comprise a relatively fewer number of cameras compared to an array camera module: the more cameras an array camera module has, the more difficult it is to directly manufacture since it is more likely to have a critical number of faulty cameras. Furthermore, the manufacturing processes disclosed in prior U.S. patent application Ser. No. 13/050,429 disclosure entitled “Fabrication process for mastering imaging lens arrays” can be more beneficially applied if the array to be generated is smaller like those discussed in this application. The 1×N master structure, for the sub-array, can be more optimally fine-tuned for homogeneity either by multiple attempts to directly diamond-turn the 1×N arrays of the template or by multiple attempts to step-and-repeat the 1×N array of the template from single lens pins before using the final small-variation 1×N template to fully populate, for example, a 8′′ wafer scale master. As a result, the array-internal performance variation and in particular BFL-variation can be reduced. Resulting variations from array to array on the full wafer scale master can be compensated by the approach presented under the method described above.
Moreover, array camera modules constructed from sub-array modules may be further advantageous in that each individual sub-array module may incorporate custom spacers to counteract back focal length variation. U.S. Patent Application Ser. No. 61/666,852 entitled “Systems and Methods for Manufacturing Camera Modules Using Active Alignment of Lens Stack Arrays and Sensors” discusses the issues related to back focal length (BFL) misalignment in the construction of array camera modules, and is hereby incorporated by reference. In many embodiments, the distribution of the average BFL for a 1×N sub-array module fabricated in a wafer stack is determined over a sufficient number of stacks to establish the repeatable array-average BFL variation. A spacer wafer may then be machined with steps in thickness that correspond to the pattern of the average-BFL over the wafer stack, and the spacers may thereafter be incorporated into the sub array module. The standard deviation of the BFL of sub-array modules within a wafer stack is expected to be small given the relatively small number of cameras in a sub-array module; accordingly, the incorporation of the customized spacers into the sub-array modules is expected to result in sufficient focusing.
A sub-array module architecture in accordance with embodiments of the invention is illustrated in FIG. 7A. The sub-array module 700 includes a focal plane array core 702 that includes a 1×3 array of focal planes 704 and all analog signal processing, pixel level control logic, signaling, and analog-to-digital conversion circuitry. Although a 1×3 array of focal planes is illustrated, any number of focal planes can be used in accordance with embodiments of the invention. The sub-array module includes lens stacks 706, and the combination of a lens stack 706 and its corresponding focal plane 704 can be configured to implement any type of camera including but not limited to narrow spectral band red cameras, narrow spectral band blue cameras, narrow spectral band green cameras, near-IR cameras, and full visual spectrum cameras. Bayer-filters may be employed to facilitate imaging. The sub-array module may utilize focal plane timing and control circuitry 708 that is responsible for controlling the capture of image information using the focal plane's constituent pixels. In a number of embodiments, the focal plane timing and control circuitry 708 provides flexibility of image information capture control which enables features including, but not limited to, high dynamic range imaging, high speed video, and electronic imaging stabilization. The focal plane timing and control circuitry can have inputs 720 and outputs 722 related to the timing of image capture, so that the sub-array module timing can be controlled by an external device (e.g. a processor, or alternatively another sub-array module). In various embodiments, the sub-array module 700 includes power management and bias generation circuitry 710. The power management and bias generation circuitry 710 provides current and voltage references to analog circuitry such as the reference voltages against which an ADC would measure the signal to be converted against. In many embodiments, the power management and bias circuitry 710 also includes logic that turns off the current/voltage references to certain circuits when they are not in use for power saving reasons. In several embodiments, the imager array includes dark current and fixed pattern (FPN) correction circuitry 712 that increases the consistency of the black level of the image data captured by the imager array and can reduce the appearance of row temporal noise and column fixed pattern noise. In several embodiments, each focal plane includes reference pixels for the purpose of calibrating the dark current and FPN of the focal plane and the control circuitry can keep the reference pixels active when the rest of the pixels of the focal plane are powered down in order to increase the speed with which the imager array can be powered up by reducing the need for calibration of dark current and FPN. In many embodiments, the sub-array module includes focal plane framing circuitry 714 that packages the data captured from the focal planes into a container file and can prepare the captured image data for transmission. In several embodiments, the focal plane framing circuitry 714 includes information identifying the focal plane and/or group of pixels from which the captured image data originated. In a number of embodiments, the sub-array module 700 also includes an interface for transmission and reception of data to and from external device(s). For example, the interface can allow for the transmission and reception of image data. In the illustrated embodiment, the interface is a MIPI CSI 2 output interface supporting four lanes that can support read-out of video at 30 fps from the imager array and incorporating interface control circuitry 716, and two sets of data input/output interface circuitry 718. In the illustrated embodiment, each set of interface circuitry is capable of both sending and receiving data. The interface circuitry, the interface control circuitry, and the focal plane timing and control inputs/outputs can allow the sub-array module to be controlled by a processor (either directly or indirectly), and/or can also allow the sub-array module to receive/transmit captured image data. Typically, the bandwidth of each input/output lane is optimized for the total number of pixels in the imager array and the desired frame rate. The input/output interface circuitry is configured to interface with any receiving device such as another sub-array module or a processor. Note that although the illustrated embodiment depicts a MIPI CSI 2 protocol, any interface protocol may be used including a Standard Mobile Imaging Architecture (“SMIA”) format. The use of various interfaces including the MIPI CSI 2 interface to transmit image data captured by an array of imagers within an imager array to an external device in accordance with embodiments of the invention is described in U.S. patent application Ser. No. 13/470,252, cited to and incorporated by reference above. The sub-array module may also include pins that can be used to establish a unique slave address for the sub-array module in the case where the sub-array module interfaces with a master device (e.g. a processor, or a master sub-array module) via a bus as discussed below. In this way, each slave device can be independently controlled by the master device.
A sub-array module in accordance with several embodiments of the invention is illustrated in FIG. 7B. The sub-array module 750 is similar to that seen in FIG. 7A, except that it does not include two sets of interface circuitry that allow both the transmission and reception of data; instead the illustrated embodiment depicts a sub-array module that includes receive interface circuitry 752 configured to receive image data from another sub-array module for forwarding, and transmit interface circuitry 754 configured to transmit forwarded image data and image data captured by the sub-array module. Such a design may be more efficiently manufactured.
As alluded to above, in many embodiments, sub-array modules are implemented that are not required to couple with other sub-array modules; instead they each interface—either directly or indirectly—with a receiving device, such as a processor, and thereby provide image data. As can be appreciated, any suitable way for transmitting the data can be implemented. For example, image data can be transmitted in parallel, or it can be transmitted in a serial fashion. In many embodiments, sub-array modules are configured to output image data to a bus; subsequently, the image data carried by the bus (e.g. from each of many sub-array modules) can be processed into a single MIPI output that can be more easily handled by a receiving device. The image data can be transmitted to the bus in a parallel fashion, or as serial data, e.g. via low voltage differential signaling. Additionally, any suitable I/O device may be used to relay image data to a receiving device, not just a conventional bus. In this way, sub-array modules can be implemented that do not have to have, for example, distinct MIPI processing circuitry; instead, the processing of image data from many sub-array modules into a single MIPI output can be accomplished separately and more efficiently. Accordingly, the manufacture of sub-array modules can become less intricate, and their manufacturing yield may increase as a result. Further, with this modular construction, I/O devices can be easily swapped if desired. Although a particular architecture is described above, any suitable architecture can be implemented in accordance with embodiments of the invention.
Although particular sub-array modules have been illustrated and discussed, any of a variety of sub-array modules that can allow for transmission and reception of data may be implemented in accordance with embodiments of the invention. For example, 1×4, 1×2, and even 1×1 sub-array modules may be implemented. Furthermore, 2-dimensional sub-array modules may also be implemented in accordance with embodiments of the invention; for example 2×3, 2×2, and 3×3 sub-array modules may be implemented. Two-dimensional sub-array modules may be used to construct two-dimensional array camera modules. Sub-array module lens configurations and the construction of one-dimensional array camera modules using sub-array modules are discussed below.
Sub-Array Module Configurations and the Construction of One-Dimensional Array Modules
Sub-array modules may include cameras arranged in a variety of configurations in accordance with embodiments of the invention. The exact configurations employed in sub-array modules depend on the particular design of the array camera to be formed. For example, in the case where a GNRBGBRNG 1×9 array camera is desired (like the one illustrated in FIG. 6E), three 1×3 sub-array modules may be used to form the corresponding array camera module having the following respective camera arrangement configurations: GNR, BGB, and RNG. FIGS. 8A-8K depict ten examples of sub-array module configurations that are similar to those shown in FIG. 7B in accordance with embodiments of the invention. Although ten examples are provided in FIGS. 8A-8K, any number of configurations of sub-array modules using any of a variety of color filter patterns may be implemented in accordance with embodiments of the invention. The sub-array modules 800 are illustrated as having corresponding interface circuitry 802, represented by arrows. The direction of the arrows is meant to indicate the direction in which image data is passed when the interface circuitry is operational.
The direction in which image data is passed in a sub-array module is configurable in accordance with many embodiments of the invention. For instance, a BGR sub-array module may be reconfigured so that it acts as a RGB sub-array module. FIG. 9 illustrates how a BGR sub-array module may be reconfigured to act as a RGB sub-array module. In particular, the BGR sub-array module 900 may be rotated 180° 902, and its corresponding interface circuitry may be reconfigured 904 such that the transmission/reception protocols in the interface circuitry are reversed. Where sub-array modules are rotated 180° the data read from the sub-array module can include a flag and/or additional data indicating the orientation of the sub-array module to enable a processor to map the relative position of pixel addresses to corresponding locations in other cameras in an array camera. Alternatively, in the case where a BGR sub-array module is mounted on a printed circuit board (PCB), the BGR sub-array module may be rotated 180° and positioned on a PCB (or laminated chip carrier or other similar such interconnector), and the configuration of the PCB (or laminated chip carrier or other similar such interconnector) may invert the routing of the data transmitted to/from the sub-array module, such that the sub-array module acts as a RGB sub-array module. Of course, the above description does not apply only to 1×3 BGR sub-array modules; the direction in which data is passed in any sub-array module may be reconfigured in accordance with embodiments of the invention.
Sub-array modules may be coupled to form an array camera module in accordance with embodiments of the invention. In particular, sub-array modules may be coupled via their respective interface circuitry such that data may be passed from one sub-array module to the coupled sub-array module. FIGS. 10A-10C illustrate the construction of three respective 1×9 array camera modules using three 1×3 sub-array modules. For example, FIG. 10A illustrates a GNRBGBRNG array camera module 1000 made from a GNR sub-array module 1002, a BGB sub-array module 1004, and a RNG sub-array module 1006. Note that data received by one sub-array module can of course be transmitted to another sub-array module. As data is transmitted, a respective sub-array module can include within the transmission information regarding the type of data and its origination and/or the orientation of the sub-array module within the array (i.e. standard or inverted/rotated). For example, where the BGB sub-array module 1004 transmits data to the RNG sub-array module 1006, the BGB can also transmit information regarding what type of data is being transmitted—e.g. image data—and where it originated from—e.g. which pixel of which focal plane of which sub-array module (e.g., the GNR sub-array module or the BGB sub-array module itself). Generally, any type of information can be transmitted between sub-array modules that facilitates their coupling. The RNG sub-array module 1006 can read out the data to an external device. For example, the GNR sub-array module 1002 can transmit image data to the BGB sub-array module 1004, which can then transmit image data (including the image data received from the GNR sub-array module) to the RNG sub-array module 1006; the RNG sub-array module 1006 may then read out image data (including the image data received from the BGB sub-array module, which itself includes image data received from the GNR sub-array module) to an external device. Additionally, the manner in which the sub-array modules interface with each other and with a receiving device may be different. For example, the manner in which the RNG sub-array module 1006 interfaces with a receiving device may be in accordance with the MIPI interface format, whereas the manner in which the GNR sub-array module 1002, the BGB sub-array module 1004, and the RNG sub-array module 1006 interface with one another in a different manner, e.g., via simple analog voltages or serial interfaces.
The array camera module 1000 can couple with a receiving device, e.g. a processor, such that the receiving device can synchronize the capture of images from each of the sub-array modules. In some embodiments, each of the sub-array modules has inputs and outputs that can be used to control the respective sub-array module's internal timing engine, and that can allow a processor to synchronize the capture of images. A processor can thus provide a driving signal to each of the sub-array modules that synchronizes the capture of images of the focal planes in the sub-array modules. For example, the processor can provide the signal via a bus-type architecture, where the processor is set as a master, and each of the sub-arrays is set as a slave. The processor can also provide the driving signal to a directly coupled sub-array module, and the sub-array module can then relay the driving signal to an adjacent sub-array module, and this relaying process can continue until each sub-array module is provided with a driving signal. Thus, as each of the sub-array modules is provided with the driving signal, the capture of images by the focal planes in the sub-array module can be synchronized. In many embodiments, the processor does not provide a driving signal to each sub-array module; instead, the processor provides a driving signal to a master sub-array module. The master sub-array module can then controls the slave sub-array modules so that the capture of images from the cameras of the sub-array modules is synchronized.
The driving signal can constitute a ‘horizontal sync pulse’ and a ‘vertical sync pulse’ to help facilitate the precise capture of image data. For example, when the focal planes capture image data, the image data may be captured by the pixels of the focal plane by advancing along the rows of pixels of the focal plane—i.e. image data is captured by a first row of pixels in a particular direction (e.g. left-to-right), then image data is captured by a next row of pixels, etc. Thus, a constituent horizontal sync pulse within a driving signal can synchronize the sampling and readout of a particular row of pixels within a focal plane (whichever row the vertical timing controller is pointing to at that time). The vertical sync pulse indicates to a vertical timing controller associated with a focal plane that the vertical timing controller should start at the beginning of the frame (i.e. row zero). In the case where the sub-array modules are being used to capture video, the vertical sync pulse can synchronize the capture of individual frames from each sub-array module within the video. In many embodiments, one of the sub-arrays is configured as a master that outputs the horizontal and vertical sync pulses to the other sub-arrays in the array cameras, which are designated as slaves synchronized to the control signals issued by the master sub-array. Although, a particular form of driving signal has been described, any driving signal can be used to synchronize the capture of image data in accordance with embodiments of the invention. In addition to providing inputs for receiving a ‘horizontal sync pulse’ and a ‘vertical sync pulse’ the sub-array modules can also include outputs that provide information concerning the state of the internal timing engine of the sub-array camera module. In many embodiments, the timing information is also provided using a ‘horizontal sync pulse’ and a ‘vertical sync pulse’. Similarly, although the construction of particular array camera modules is illustrated in FIGS. 10A-10C, any number of array camera modules can be constructed using sub-array modules in accordance with embodiments of the invention. For example, array camera modules of any length may be constructed using sub-array modules in accordance with embodiments of the invention.
Furthermore, as mentioned above, in many embodiments, sub-array modules do not couple with one another, and instead interface—either directly or indirectly—with a receiving device. For example, FIG. 11A illustrates a 1×9 array camera fabricated from three 1×3 sub-array modules that do not couple with one another in accordance with embodiments of the invention. In particular, the array camera 1100 corresponds with that seen in FIG. 10A, except that each sub-array module, 1102, 1104, and 1106, outputs image data to a bus 1108, and thereby transmits image data to a processor 1108. In a number of embodiments, intermediary circuitry is used to convert received image data to a single MIPI output, which is then transmitted to a processor 1110. Thus, array cameras can be implemented whereby sub-array modules do not couple with one another.
In many embodiments, multiple I/O devices are used in adjoining multiple sub-array modules. For example, FIG. 11B illustrates a 1×9 array camera similar to that seen in FIG. 11A, except that each sub-array module is associated with a respective I/O device, that itself interfaces with an I/O block which processes the received image data and provides an output to a processor. In particular, a 1×9 array camera 1150 includes three sub-array modules 1152, 1154, and 1156, that are each affiliated with a respective I/O device, 1158, 1160, and 1162. Accordingly, the respective I/O devices interface with a separate I/O block 1164 that can aggregate the image data and thereby provide a single MIPI output. The I/O block 1164 can provide the output in a MIPI container to a processor 1166 for further processing. As this architecture includes multiple I/O devices, each affiliated with certain cameras, image data may be processed more effectively and efficiently. For example, using this architecture, the length of circuit traces can be reduced, and correspondingly, the signal to noise ratio can be enhanced. Consequently, the increased efficiency can help mitigate a host of issues that may otherwise be present including those relating to: image data synchronization; power consumption; and cross-talk. Additionally, as multiple I/O devices are used, they each may be adapted to have a smaller footprint, and can thereby facilitate the implementation of an advantageous physical layout of the sub-array modules. As can be appreciated, each of multiple I/O devices can be affiliated with any number of cameras in accordance with embodiments of the invention. For example, in many embodiments, 2 I/O devices are incorporated whereby one I/O device is affiliated with 6 cameras, and the other I/O device is affiliated with 3 cameras. The I/O devices may then interface with a separate I/O block that receives image data, aggregates it, and outputs it to a processor for further processing. Additionally, as will be elaborated on below, two-dimensional sub-array modules may also be implemented in accordance with embodiments of the invention; accordingly, I/O devices may also be affiliated with any number of cameras in an arrangement of two-dimensional sub-array modules in accordance with embodiments of the invention. Generally, I/O blocks may be affiliated with cameras within sub-array modules of any dimensions in accordance with embodiments of the invention.
Note that sub-array modules of different types may be coupled to form array camera modules. For example, 1×3 sub-array modules may be combined with 1×2 sub-array modules, 1×4 sub-array modules, or even 1×1 sub-array modules. This flexibility is advantageous insofar as it can alleviate unwieldy manufacturing processes. For instance, the manufacture of sub-array modules that include near-IR cameras (e.g. a GRN sub-array module as shown in FIG. 8D) may require the imposition of an IR cut-off filter (that can be a structured dielectric coating), which may then be selectively removed in the areas of the sub-array module where a near-IR camera is desired (e.g. the N camera of a GRN sub-array module). Subsequently, an organic near-IR pass filter or another multilayer dielectric coating can then be applied at the position of the near-IR channels. This manufacturing process may be cumbersome. Thus, in accordance with embodiments of the invention, a 1×1 near-IR sub-array module may be coupled with another sub-array module of any type, thereby resulting in an array camera module that includes a near-IR camera. This technique may be advantageous in that cumbersome manufacturing processes may be avoided. For example, instead of forming sub-array modules that include near-IR cameras and color cameras, 1×1 sub-array modules that include near-IR cameras can be produced separately on a single wafer that does not include any other color channels and later coupled with a sub-array module that includes color cameras constituting different color channels. Consequently, the step of selectively removing an IR cut-off filter and then applying an organic near-IR pass filter or other dielectric coating may be avoided. Thus, for example a 1×2 GR sub-array module may be coupled to a 1×1 near-IR camera to form a 1×3 GRN array camera module in accordance with embodiments of the invention.
Similarly, the particular lens fabrication technique employed in the fabrication of a sub-array module (e.g. WLO manufacturing, precision glass molding, or polymer injection molding) may be selected to accommodate the particular sub-array module's functionality and/or its manufacturing process. Of course, any number of sub-array modules, which can each be of different types, can be coupled to form an array camera module in accordance with embodiments of the invention. More generally, as an array camera module can be formed from different types of sub-array modules that can be coupled using a variety of techniques in accordance with embodiments of the invention, the constituent sub-array modules may be designed to accommodate any number of different manufacturing processes.
Moreover, sub-array modules may be combined using a single substrate that includes interconnects. For example, sub-array modules may be coupled to a substrate that has interconnects, such that when the sub-array modules are coupled to the substrate, the sub-array modules can thereby interface with each other and/or with a receiving device (e.g. a processor) via the substrate's interconnects. The interconnection of three sub-array modules coupled to a glass substrate in accordance with an embodiment of the invention is illustrated in FIG. 12. In the illustrated embodiment, three sub-array modules are coupled to a glass substrate that includes interconnects, thereby allowing the sub-array modules to interface with one another and with a receiving device. Specifically, the array camera module 1200 is constructed from a glass substrate 1202 that includes interconnects 1204, upon which sub-array modules 1206 can couple. The sub-array modules can include electrical pads to couple with the glass substrate's interconnects. The electrical pads can include the same interface functionality discussed above with respect to FIGS. 7A and 7B (e.g. interface circuitry 718, 752, 754, inputs/outputs, 720, 722). The interconnects 1204 can allow the sub-array modules to interface with one another and with a receiving device such as, but not limited to, an appropriately configured microprocessor and/or an application specific device that is configured to read in the serial data from the independent sub-array modules and synthesize a cohesive output data stream (e.g. a MIPI serial output data stream). As can be appreciated, the interconnects can be configured so as to allow each sub-array module to interface—either directly or indirectly—with a receiving device such that each sub-array module can provide image data to a receiving device without having to couple with another sub-array module. Thus, for example, the array camera seen in FIG. 11 can be constructed using a single substrate. Additionally, where a glass substrate is used, the lenses of a sub-array module may also be bonded to the glass substrate. For example, the sensors that include the sub-arrays of focal planes may be coupled with the glass substrate on one side of it that includes interconnects, and the corresponding lenses that combine with the sensors to form an imager array may be bonded to the other side of the glass substrate such that the complete functionality of the sub-array module is achieved. Because the glass substrate is optically transparent, the sub-array module can still function even though the glass substrate lies between the sensor dies and the corresponding lenses. In many embodiments, the lens for each sensor in a sub-array module can be independently mounted to the glass substrate. In a number of embodiments, arrays of lens stacks can be mounted to the glass substrate and the number of lens stacks in the array need not correspond with the number of focal planes on the sensors mounted to the glass substrate.
Using a substrate to facilitate the coupling of sub-array modules can be advantageous in that the specific configuration of the substrate can govern the spacing between the sub-array modules, and the spacing between sub-array modules can control the array camera module's imaging ability. Specifically, the manner in which the interconnects are situated can govern the sub-array module spacing. Hence, sub-array modules that are coupled need not be within immediate proximity of one another when a substrate is used to enable their coupling. Although much of the discussion above refers to the use of glass substrates, any of a variety of optically transparent substrate materials can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention. Furthermore, substrates in which openings are formed to permit transmission of light through the substrate can also be utilized including (but not limited to) ceramic substrates in which through holes are formed. Thus, for example, a single sensor or multiple sensors can be fixed to one side of the ceramic carrier to form the focal planes of the array camera module and lens barrels containing lens stacks can be affixed to the other side of the ceramic carrier so that the lens stacks direct light onto the focal planes of the one or more sensors through the openings in the ceramic carrier. In many instances, the ceramic carrier is rigid and has a coefficient of thermal expansion that matches that of the sensor. Thus, the likelihood that mismatches in thermal expansion will result in changes in the alignment between the lens stacks and corresponding focal planes that deteriorate the quality of the images that can be synthesized using the image data captured by the focal planes. U.S. Provisional Patent Application No. 61/904,947 to Mark Rodda et al. discloses the incorporation of ceramic substrates in the context of array cameras, and is hereby incorporated by reference in its entirety.
One-dimensional array camera modules constructed from sub-array modules may also be coupled to a parallax disparity resolution module in accordance with embodiments of the invention. The parallax disparity resolution module may either a hardware parallax disparity resolution module or may be a software parallax disparity resolution module. FIG. 13A illustrates a 1×9 array camera module constructed from three constituent 1×3 sub array modules, where the array camera module 1300 outputs the data to a hardware parallax disparity resolution module 1302. Similarly, FIG. 13B illustrates a 1×9 array camera module constructed from three constituent 1×3 sub-array modules, where the array camera module 1350 outputs the data to a software parallax disparity resolution module 1352. Either parallax disparity resolution module 1302, 1352 can receive the data and implement processes to detect parallax within image data (using processes similar to, but not limited to, those described in U.S. Provisional Patent Application Ser. No. 61/691,666) and implement processes to account for the detected parallax in the further processing of the image data.
Although particular one-dimensional array camera modules constructed from sub-array modules have been described, many other such configurations exist in accordance with embodiments of the invention. Hence, the descriptions and corresponding figures should not be construed as limiting the scope of the invention, and are instead merely illustrative. Two-dimensional array camera modules may also be constructed from sub-array modules in accordance with embodiments of the invention, and this is discussed below.
The Construction of Two-Dimensional Array Cameras Using Sub-Array Modules
Sub-array modules may be coupled to form two-dimensional array cameras in accordance with embodiments of the invention. A 3×9 two-dimensional array camera constructed from sub-array modules in accordance with embodiments of the invention is illustrated in FIG. 14A. In particular nine 1×3 sub-array modules are coupled so as to form three array camera module sub-assemblies 1402. Each array camera module sub-assembly 1402 is then coupled to a parallax disparity resolution module 1404 (either hardware or software). In the illustrated embodiment, an interconnection module interfaces with a processor 1406 and one of the sub-arrays in each of the rows of the camera array to enable communication between the processor and each of the sub-arrays. In other embodiments, the processor is configured to directly interface with multiple sub-arrays, e.g. similar to the arrangement seen in FIG. 11. In several embodiments, each sub-array module is configured to interface with circuitry that receives image data from each sub-array module and converts the image data to a single MIPI output, which is thereby provided to a processor. Note that in the illustrated embodiment, the three 1×9 array camera module sub-assemblies are adjacent to each other such that a 3×9 array camera module can be achieved. However, any arrangement may be implemented in order to achieve a two-dimensional array camera module in accordance with embodiments of the invention. In many embodiments, the processor 1406 is made aware of the relative location of the cameras, and uses this information in processing received data.
In many embodiments, a two-dimensional array camera is formed from sub-array modules where a single sub-array module reads out data to a processor. FIG. 14B illustrates a two-dimensional 3×9 array camera where a single constituent sub-array module reads out data to a processor. In the illustrated embodiment, the array camera 1450 is formed from nine 1×3 sub-array modules that are coupled, where data from the sub-array modules is read out by a single sub-array module 1452 to a processor 1454, which can then process the image data. Again, in the illustrated embodiment, the sub array modules are arranged such that a 3×9 array camera module is achieved. However, as before, any arrangement may be implemented in order to achieve a two-dimensional array camera module in accordance with embodiments of the invention. In many embodiments, the processor 1454 is made aware of the relative location of the cameras, and uses this information in processing received data. As before, the manner in which the sub-array modules interface with one another and with a receiving device may all be different.
Additionally, similar to before with respect to FIG. 12, sub-array modules may be coupled via a substrate to form an array camera. FIG. 15 illustrates a two-dimensional array camera formed from sub-array modules coupled to a substrate. Specifically, the array camera 1500 includes a glass substrate 1502 with interconnects 1504, sub-array modules 1506, and a processor 1508. As before, the sub-array modules 1506 can connect to the glass substrate 1502 via electrical pads, and as before the imager arrays of a sub-array module 1506 may be coupled to one-side of the glass substrate that includes interconnects 1504, and corresponding lenses may be bonded to the other side of the glass substrate 1502. Again, using substrates to facilitate the coupling of sub-array modules—either to one another or to independent circuitry—can be advantageous in that the substrate can control the spacing between sub-array modules, and this affects the array camera's imaging ability.
In constructing an array camera, an array camera module may be patterned with “π filter groups”, or alternatively “Pi filter groups.” The term Pi filter groups refers to a pattern of narrow spectral band cameras within the array camera module. Processes for patterning array cameras with Pi filter groups are described in U.S. Provisional Patent Application Ser. No. 61/641,164, entitled “Camera Modules Patterned with π Filter Groups”, Venkataraman et al. The disclosure of U.S. Provisional Patent Application Ser. No. 61/641,164 is incorporated by reference herein in its entirety. A single Pi filter group is illustrated in FIG. 16, wherein 5 cameras are configured to receive green light, 2 cameras are configured to receive red light, and 2 cameras are configured to receive blue light. The Pi filter patterns may facilitate the efficient capturing of color image data.
In many embodiments of the invention, two-dimensional array cameras are constructed using sub-array modules wherein the sub-array modules are arranged such that Pi filter groups are implemented within the array camera. FIGS. 17A and 17B are similar to FIGS. 14A and 14B except that the sub-array modules are configured to implement Pi filter groups.
Although the above discussion has largely focused on 1×3 sub-array modules and their implementation in the construction of array camera modules and array cameras, in many embodiments, sub-array modules have other dimensions. FIGS. 18A-18B illustrate 1×4 sub-array modules in accordance with some embodiments. It should be repeated that although only narrow spectral band blue, green and red cameras are illustrated in FIGS. 18A-18B, any type of camera may of course be implemented in sub-array modules in accordance with embodiments of the invention.
Sub-array modules of any dimension can be used in the construction of array cameras in accordance with embodiments of the invention. FIGS. 19A and 19B illustrate the construction of a 4×4 array camera using 1×4 sub-array modules in accordance with many embodiments. FIGS. 19A and 19B are similar to FIGS. 14A and 14B except that 1×4 sub-array modules are used to form the array camera. The illustrated embodiment includes an array camera, sub-array module sub-assemblies 1902, an interconnection module 1904, and a processor 1906, 1908. In the illustrated embodiment, Pi filter groups are patterned on the array camera. Similarly, FIGS. 20A-20D illustrate 1×5 sub-array modules, and FIGS. 21A-21B illustrate the construction of 5×5 array cameras using 1×5 sub-array modules. The illustrated embodiment includes an array camera 2100, sub-array modules sub-assemblies 2102, an interconnection module 2104, and a processor 2106, 2108. Again, in the illustrated embodiments, Pi filter groups are implemented on the two dimensional array cameras. A particular benefit of utilizing 1×5 sub-array modules to build a 5×5 array camera module is that the 5×5 array camera can be constructed using two different types of 1×5 sub-array modules (i.e. GRGRG and BGBGB or GBGBG and RGRGR). Similarly, any square array patterned with Pi filter groups including an odd number of rows and columns can be constructed using only two different types of sub-arrays.
Furthermore, as alluded to above, two-dimensional sub-array modules may also be implemented to construct two-dimensional array cameras in accordance with embodiments of the invention. For example, FIG. 22 illustrates the construction of a 4×4 array camera using 2×2 sub-array modules. In particular, the 4×4 array camera 2200 is similar to that seen in FIG. 19, except that it includes four 2×2 sub-array modules 2202. In the illustrated embodiment, each sub-array module 2202 interfaces with circuitry 2204 that receives image data from each of the sub-array modules and outputs the aggregated image data to a processor 2206. As can be appreciated from the above discussion, it should be understood that the sub-array modules can provide image data to a processor in any suitable fashion in accordance with embodiments of the invention. For example, in some embodiments, the two-dimensional sub-arrays include interface circuitry that allow them to interface with other sub-array modules, and thereby transmit image data to (and otherwise interact with) a processor. In many instances, modular array cameras include both two-dimensional and one-dimensional sub-array modules. In general, modular array cameras of any dimension can be constructed from one-dimensional and/or two-dimensional sub-array modules in accordance with embodiments of the invention.
As mentioned previously, 1×1 sub-array modules may also be used to construct array cameras, and this is discussed below.
1×1 Sub-Array Modules
In accordance with many embodiments of the invention, 1×1 sub-array modules may be used to construct array cameras. Thus, for example, 1×1 sub-array modules may be used to construct either one dimensional array cameras or two-dimensional array cameras. 1×1 sub-array modules are similar to the sub-array modules discussed above except that they do not include multiple lens stacks and multiple focal planes. Instead, a 1×1 sub-array module includes a single lens stack and a sensor including single focal plane. Accordingly, the above-mentioned techniques regarding constructing array cameras from sub-array modules may also be used to construct array cameras from 1×1 sub-array modules. Using 1×1 sub-array modules to construct array cameras may confer a host of benefits. For example, Array cameras of any dimension may be constructed using 1×1 sub-array modules, and many different types of 1×1 sub-array modules may be used in the construction. For example, 1×1 sub-array modules that have different F numbers, focal lengths, image sensor formats and/or fields of view, may be used, particularly because slightly different heights of different types of 1×1 sub-array modules can be accommodated. Similarly, the different substrates and spacer thicknesses within a lens stack may be accommodated. In many embodiments, these sub-array modules are used to construct array cameras that can provide optical zoom with no moving parts. Array cameras may also incorporate 1×1 sub-array modules that are configured for near-IR sensitivity and far-IR sensitivity. Additionally, sub-array modules that implement a time-of-flight camera to provide additional depth information, may also be used in accordance with embodiments of the invention. As already discussed above, 1×1 sub-array modules are also beneficial insofar as 1×1 sub-array modules of the same type (e.g., near-IR cameras) may be constructed on the same wafer, thereby increasing manufacturing efficiencies.
In several embodiments, 1×1 sub-array modules may be assembled to form an array camera module using a variety of technique appropriate to the specific 1×1 sub-array module constructions, including any of the above discussed techniques, in accordance with embodiments of the invention. In some embodiments, the sensor of a 1×1 sub-array module is adjoined to a printed circuit board using reflow soldering. Subsequently, the respective lenses of the sub-array module may be adjoined to the sensor. Note that the lenses may be affixed to the sensor using the active alignment processes U.S. Patent Application Ser. No. 61/666,852. In a number of embodiments, the sensors of a 1×1 sub-array module are bonded to a glass substrate that includes interconnects that allow the sub-array modules and other components to interface. The corresponding lenses may also be bonded to the glass substrate. This technique is similar to that already described above.
In numerous embodiments, each sub-array module is first independently formed such that it is inclusive of the sensor and the lens stack array, and is then reflow soldered to a printed circuit board. In these embodiments, both the lens and the sensor are adapted to be capable of undergoing a reflow soldering process. This method of manufacture may be advantageous insofar as the individual sub-array modules can be evaluated prior to construction of the array camera. It may be further advantageous, as the formed sub-array modules may be easily rearranged to provide different types of array cameras.
As already alluded to above, one-dimensional array camera modules and two-dimensional array camera modules may be formed from 1×1 sub-array modules in accordance with embodiments of the invention. Of course, the particular arrangement of the 1×1 sub-array modules will govern whether a one-dimensional or a two-dimensional array camera module is achieved.
Note that when the individual sub-array modules are assembled to form an array camera, the sub-array modules may be oriented in slightly different directions with respect to one another, for example due to manufacturing tolerances and corrections for alignment. As a result, the epipolar lines of the resulting array camera may deviate with respect to the scanlines of the individual cameras. Consequently, in many embodiments, the array camera includes a processor that can perform an affine transformation in conjunction with parallax disparity resolution, in processing the images provided by the sub-array modules, to resolve the discrepancies in camera orientation.
In many embodiments, an array camera that is constructed from 1×1 sub-array modules also utilizes an external hardware block that can read in serial data from the independent 1×1 sub-array modules, and synthesize a cohesive output data stream (e.g. a MIPI serial output data stream) that can be transmitted to a receiving device, e.g. a processor. In a number of embodiments, the external hardware block can interact with the sub-array modules through a custom 12C interface to, for example, command and control the individual sub-array modules. Moreover, in several embodiments, the external hardware block includes sufficient buffer space so that it can read out all the data from the sub-array modules to the receiving device simultaneously. This may improve array camera performance, since it can mitigate any delay that results from the transmission of data to the receiving device. For example, the rolling shutter performance of the array camera may be improved, since it would be governed by the size of a single sub-array module as opposed to the size of the entire array camera. In several embodiments, the external hardware block includes circuitry to encrypt the data being read out from the camera array to enable digital rights management control. In a plethora of embodiments, the external hardware block includes circuitry to compress the data being read out from the camera array to reduce the data bandwidth requirements in the resulting output stream. Although the external hardware blocks described above is discussed in the context of constructing array cameras using 1×1 sub-array modules, similar external hardware blocks can be utilized in the construction of array cameras using a variety of sub-array modules including sub-array modules having different dimensions. Furthermore, array camera modules can be constructed using any of a variety of techniques involving fixing sub-array modules of any dimension to a substrate appropriate to the requirements of a specific application in accordance with embodiments of the invention.
Although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. For example, sub-array modules of different types (e.g. 1×3 and 1×4) may be coupled to form an array camera module. It is therefore to be understood that the present invention may be practiced otherwise than specifically described. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.

## Claims

1. An X×Y sub-array module comprising:
an X×Y arrangement of focal planes, wherein:
X and Y are each greater than or equal to 1;
each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels;
each focal plane does not include pixels from another focal plane; and
the X×Y arrangement of focal planes are embodied within an integrated circuit that does not include any focal planes of another X×Y sub-array module; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene;
image data output circuitry that is configured to output image data from the X×Y sub-array module that is capable of being aggregated with image data from other sub-array modules to construct so that an image of the scene; and
interface circuitry configured to couple, either directly or indirectly, with one of:
another X×Y sub-array module or a processor that is in electrical communication with at least one other X×Y sub-array module;
wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module or a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module.

2. The X×Y sub-array module of claim 1, wherein X is 1.

3. The X×Y sub-array module of claim 1, wherein X and Y are each greater than 1.

4. The X×Y sub-array module of claim 1, wherein the arrangement of cameras are embodied within a single monolithic structure.

5. An M×N array camera comprising:
a plurality of X×Y sub-array modules, each comprising:
an X×Y arrangement of focal planes, wherein:
X and Y are each greater than or equal to 1;
each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels; and
each focal plane does not include pixels from another focal plane;
the X×Y arrangement of focal planes are embodied within an integrated circuit that does not include any focal planes of another X×Y sub-array module; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene;
image data output circuitry that is configured to output image data from the sub-array module that is capable of being aggregated with image data from other sub-array modules to construct an image of the scene; and
interface circuitry configured to couple, either directly or indirectly, with one of: another X×Y sub-array module or a processor that is in electrical communication with at least one other X×Y sub-array module;
wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module or a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module;


wherein the plurality of X×Y sub-array modules define at least some of the cameras in an M×N arrangement of cameras; and
a processor;
wherein each sub-array module is configured to transmit respective output image data to the processor via its respective distinct interface circuitry;
wherein the processor is configured to construct an image of the scene using image data generated by each of the sub-array modules.

6. The array camera of claim 5, wherein X is 1 and M is 1.

7. The array camera of claim 5, wherein the plurality of X×Y sub-array modules define an M×N arrangement of cameras.

8. The array camera of claim 5, further comprising circuitry that aggregates the image data generated by each of the sub-array modules into a single MIPI output, and provides the MIPI output to the processor.

9. The array camera of claim 5, further comprising a parallax disparity resolution module, wherein the parallax disparity resolution module is configured to receive image data captured by each sub-array module, implement a parallax detection and correction process on the received image data, and output the result for further processing.

10. The array camera of claim 9, further comprising circuitry that converts the output of the parallax disparity resolution module into a single MIPI output, and provides the MIPI output to the processor.

11. The array camera of claim 10, wherein the parallax disparity resolution module comprises a processor and memory, wherein the memory contains software to configure the processor to act as a parallax disparity resolution module.

12. The array camera of claim 10, wherein the parallax disparity resolution module is a hardware parallax disparity resolution module.

13. The array camera of claim 5, wherein M and N are each greater than or equal to 2.

14. The array camera of claim 5, wherein at least two of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and are each capable of outputting image data through the interconnects.

15. The array camera of claim 14, wherein each of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and are each capable of outputting image data through the interconnects.

16. The array camera of claim 15, wherein the substrate is optically transparent.

17. The array camera of claim 16, wherein the substrate is glass.

18. The array camera of claim 15, wherein the substrate is ceramic with through-holes that clear the optical path.

19. The array camera of claim 5, wherein at least one sub-array module is embodied within a single monolithic structure.

20. The array camera of claim 5, wherein each sub-array module is embodied within a single respective monolithic structure.

21. The array camera of claim 5, further comprising:
a plurality of I/O devices, wherein each of the plurality of I/O devices interfaces with at least one camera: and
a separate I/O block that includes circuitry configured to receive image data, aggregate the received image data, and output the aggregated image data to the processor; and
wherein each of the plurality of I/O devices interfaces with the I/O block.

22. The array camera of claim 21, wherein the number of I/O devices equals the number of sub-array modules, and wherein each I/O device interfaces with a corresponding sub-array module.

23. The X×Y sub-array module of claim 1, wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module.

24. The X×Y sub-array module of claim 1, wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module.

25. The M×N array camera of claim 5, wherein at least one X×Y sub-array module comprises interface circuitry configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module.

26. The M×N array camera of claim 5, wherein at least one X×Y sub-array module comprises interface circuitry configured to transmit output image data to a directly or indirectly coupled X×Y processor that is in electrical communication with at least one sub-array module.