# Patent

## Title
Staged startup after failover or reboot

## Abstract

A “high availability” system comprises multiple switches under the control of one more control processors (“CPs”). Each CP performs a staged startup process when failing-over from another CP or otherwise booting up. The staged startup process involves multiple stages of processing of various executable components of the image. Some stages may depend on the prior execution of other stages. The preferred staged startup process includes the use of a staging table which permits the standby image's FSS facility to efficiently schedule the various stages of the fail-over process taking into account the inter-stage dependencies.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to high availability computer networks. More particularly, the invention relates to failing over from an active control processor to a standby control processor upon a fault occurring with the active processor. Still more particularly, the invention relates to a staged startup process which occurs during a fail-over or also a boot-up.
2. Background Information
Initially, computers were most typically used in a standalone manner. It is now commonplace for computers and other types of computer-related and electronic devices to communicate with each other over a network. The ability for computers to communicate with one another has lead to the creation of networks ranging from small networks comprising two or three computers to vast networks comprising hundreds or even thousands of computers. Networks can be set up to provide a wide assortment of capabilities. For example, networks of computers may permit each computer to share a centralized mass storage device or printer. Further, networks enable electronic mail and numerous other types of services. Generally, a network's infrastructure comprises switches, routers, hubs and the like to coordinate the effective and efficient transfer of data and commands from one point on the network to another.
Networks often comprise a “fabric” of interconnected switches which are devices that route data packets from source ports to destination ports. The switches in a network typically are relatively complex devices that include microprocessors, memory, and related components and execute firmware stored in non-volatile memory such as read only memory (“ROM”). The switches typically have multiple ports which may be physically connected to other switches or other devices such as servers, storage devices, user consoles, and other types of I/O devices.
Switches may be fabricated in “blade” form comprising a circuit board mated to a tray. The blade assembly then can be slid into a chassis so that blind mating connectors on the blade engage corresponding sockets in the chassis. In one type of switch chassis embodiment, the chassis is able to accommodate multiple, generally identical, blades (e.g., eight). The number of blades used in the system can be scaled up or down as needed. One or more control processors (“CPs”) may also be included in the chassis in blade form. Each CP preferably includes one or more microprocessors, memory (both volatile and non-volatile), and connects to the various switches in the chassis, firmware stored in non-volatile memory which is executed by the CP's microprocessor, etc.
In those systems in which two CPs are provided in a single chassis, typically, one CP is deemed the “active” CP and the other CP is in a “standby” mode of operation. The active CP is fully operational and interactive with the various switches in the chassis, and switches and CPs in other chassis. The standby CP is generally identical to the active CP (i.e., same hardware and same software loaded thereon), but is non-operational. If the active CP fails or otherwise ceases to be fully operational for whatever reason, control may pass from the failed active CP to the standby CP. This fail-over process involves the coordination of a great deal of software state and hardware configuration information and, accordingly, consumes a significant amount of time. As such, it would be highly desirable to reduce the time required as much as possible to fail over from the active CP to the standby CP. It is also desirable to minimize the disruption of service that may occur during the fail-over process.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS OF THE INVENTION
The preferred embodiments of the present invention solve the problems noted above by a “high availability” system which comprises one or more switches (or other electronic devices) under the control of one or more control processors (“CPs”). One of the CPs is deemed to be the “active” CP, while the other CP is kept in a “standby” mode. Each CP generally has the same software load including a fabric state synchronization (“FSS”) facility. The FSSs of each CP communicate with each other.
In accordance with a preferred embodiment of the invention, the state information pertaining to the active “image” (i.e., the software service running on the active CP) is continuously provided to a standby copy of the image (the “standby image”). The FSSs perform the function of synchronizing the standby image to the active image. The state information generally includes configuration and operational dynamically changing parameters and other information regarding the active image. By keeping the standby image synchronized to the active image, the standby image can rapidly be transitioned to the active mode if the active image experiences a fault. Armed with the state of the previous active image, the standby image will continue operating where the previous active image left off. Some state updates may not be provided to the standby image before the active image fails. The software on the standby CP accounts for this situation, and performs a consistency check when it takes over to determine whether some updates may have been missed.
The fail-over process involves multiple stages of processing of various executable components of the image. Some stages may depend on the prior execution of other stages. In accordance with another aspect of the invention, once it is determined that a fail-over to the standby image is needed, the standby image pulls control away from the failed active image. The preferred fail-over process includes the use of a staging table which permits the standby image's FSS facility to efficiently schedule the various stages of the fail-over process taking into account the inter-stage dependencies noted above.
In accordance with another preferred embodiment of the invention, a standby CP which becomes the active CP, re-issues all messages that the previously active CP had issued and which have not yet completed. Each transaction of messages through the network is assigned a transaction identifier (“XID”) that uniquely distinguishes that transaction from other transactions. In accordance with a preferred embodiment, the newly active CP uses a different range of XIDs than its predecessor CP. By using a different range of XID values, the newly active CP can determine whether an incoming response message is responsive to a message that originated from the previously active CP or the newly activated CP. The currently active CP preferably ignores all response messages that do not have an XID in the CP's XID range. This ensures proper and reliable messaging in the network during a fail-over event.
In accordance with yet another embodiment of the invention, changing a CP's firmware may be desired to provide, for example, additional functionality. It further may be desired to change firmware in a single CP system. Consistent with the high availability nature of the present system (i.e., minimal down time), a single CP system implements a firmware change by loading a reboot manager utility and registering the utility as a standby image with the FSS. Then, the currently active image is prompted to save its state to a file stored in non-volatile memory. Upon an optional reboot of the CP, the new firmware is brought up as a standby image; the reboot manager is launched as an active image. A state restore then occurs in which the previously saved state is provided to the standby image. Then, a fail-over is forced to transition the standby image (which contains the new firmware) to the active mode. During the state save operation, the firmware preferably does not distinguish between communicating with its standby counterpart and communicating with the reboot manager. Likewise, during the state restore phase, the firmware generally has no knowledge that it is receiving the updates from the reboot manager, instead of receiving from the active counterpart.
These and other aspects and benefits of the preferred embodiments of the present invention will become apparent upon analyzing the drawings, detailed description and claims, which follow.



BRIEF DESCRIPTION OF THE DRAWINGS
For a detailed description of the preferred embodiments of the invention, reference will now be made to the accompanying drawings in which:
FIG. 1 shows an exemplary switch fabric comprising a plurality of switches and end node devices;
FIG. 2 shows a chassis in which a plurality of switches and control processors are mounted;
FIG. 3 shows a block diagram of the switches and control processors of FIG. 2 in accordance with a preferred embodiment of the invention;
FIG. 4 shows a preferred embodiment illustrating the synchronization interaction between a pair of control processors;
FIG. 5 illustrates a recovery process in which various software components are recovered in stages and some stages of which may depend on other stages;
FIG. 6 illustrates a preferred embodiment of a staging table which implements the staged recovery process of FIG. 5;
FIG. 7 shows a flow chart depicting how a fail-over image responds to outstanding messages that originated from the previous controlling image using a unique range of exchange identifiers; and
FIG. 8 shows a flow chart showing how firmware can be changed in a single control processor system.



NOTATION AND NOMENCLATURE
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component and sub-components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either a direct or indirect physical connection. Thus, if a first device couples to a second device, that connection may be through a direct physical connection, or through an indirect physical connection via other devices and connections. The term “state” or “state information” refers to values, variables, and other entities that are used for software and/or hardware to run. State information typically dynamically varies during run time and usually is more than just configuration information.
To the extent that any term is not specially defined in this specification, the intent is that the term is to be given its plain and ordinary meaning.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, a network 50 is shown in accordance with a preferred embodiment of the invention. As shown, the network 50 comprises a plurality of inter-connected switches 52. One or more end nodes are also attached to various of the switches 52 and can communicate with each other via the fabric of switches. The end nodes may include one or more storage devices 56, one or more server computers 58, input/output (“I/O”) devices 60 (e.g., a console), and other desired devices. Messages from one end node to another are routed through the fabric of switches 52 in a manner determined by routing tables that are loaded into each switch. The network 50 may be implemented in accordance with the Fibre Channel standard, or other suitable type of well-known or custom-designed network.
FIG. 2 shows one exemplary embodiment of a chassis 70 containing a plurality of switches 52. The chassis 70 shown in FIG. 2 includes the capacity to accommodate eight switches 52 which are labeled SW0–SW7. The chassis 70 preferably also accommodates one or more control processors (“CPs”) 72. Two CPs 72 are shown in FIG. 2 and are labeled as CP0 and CP1. In general, the CPs 72 control the operation of the switches 52. Although the system can operate with only one CP, two are preferred for redundancy. Although the preferred embodiment is described herein in the context of network switches, it should be understood that CPs can be used in conjunction with many other types of electronic devices.
As shown in FIG. 3 the CPs 72 couple to each of the switches 52 via one or more busses 59. Each switch 52 can connect to other switches in the chassis 70, to switches in other chassis, and to end nodes via a plurality of ports 81. Each node on the switch can be configured to send and/or receive messages. The connection 59 between the switches 52 and the CPs 72 may be a bus separate from the ports 81 or one of the ports 81 on each switch may be used to connect the switch to the CPs. Alternatively, each CP can connect to a group of switches SW0–SW3 via one bus and another group of switches SW4–SW7 via a different bus. The CPs 72 perform numerous management functions with regard to the switches 52. An example of such a management function is to load a routing table into the memory 80 of each switch. The routing table specifies how a switch is to route incoming messages received on an input port 81 to an output port 81. Thus, the routing table takes into account the fabric topology the system architect has established for the network. FIG. 1 represents one exemplary topology of how end nodes and switches can be connected together and thus the routing tables would reflect that topology. The CPs 72 generally configure each of the switches 52. Once configured, the switches generally run autonomously meaning CPs 72 are not needed simply for a switch to route messages between input and output ports. The CPs 72, however, may perform other management functions as keeping statistics, static or dynamic route changes, naming or addressing configuration changes and processing network control messages.
Referring again to FIG. 3, each CP 72 preferably includes a central processing unit (“CPU”) 84, volatile memory 86 and non-volatile memory 92. Volatile memory 86 may comprise random access memory (“RAM”). Non-volatile memory 86 may comprise flash memory, a hard disk drive, or other types of non-volatile memory. The non-volatile memory 92 includes various routines and files that are executed and used by CPU 84. Those routines may include a fabric state synchronization (“FSS”) facility 112, operating system kernel 96, application software 98, a reboot manager 99, and a component description file 100. The volatile memory 86 is used to temporarily store data in accordance with known techniques. The volatile memory 86 may contain an exchange identifier (“XID”) table 88 and a staging table 90 as will be described below.
In accordance with a preferred embodiment of the invention, the system of switches 52 and CPs 72 is implemented with “high availability” features. High availability generally refers to the system's capability to quickly recover from a fault with little, or no, down-time. Various aspects of the high availability nature of the system will be described below.
Fabric State Synchronization (“FSS”)
Referring still to FIG. 3, in accordance with a preferred embodiment of the invention, two CPs 72 are provided to control the associated switches 52. Preferably, only one CP 72 is needed to control the switches, the other CP being used for redundancy purposes. Thus, if the currently active CP fails, control can pass to the backup CP (referred to herein as being in a “standby” mode). More than one standby CP can be provided if desired. If a fail-over to the standby CP is required (for example, due to a failure of the active CP), the fail-over preferably occurs as quickly as possible so as to minimize the amount of down time. To that end, state information associated with the active CP is provided periodically to the standby CP thereby synchronizing the standby CP to the active CP. By keeping the standby CP synchronized to the active CP during run-time, the standby CP's transition to the active state is expedited.
Various terminology relevant to the synchronization and failover processes will now be introduced. This terminology should not be used to limit the scope of this disclosure, but is merely being provided for sake of ease in understanding the principles discussed herein. Reference is now made to FIG. 4 which shows two images—an active image 110A and a standby 110S. The “A” designation refers to “active” and the “S” designation refers to “standby.” Each image includes an FSS facility 112A, 112S and executable routines in both user space and operating system kernel space. For example, two components 114A/S and 116A/S are shown in the user space along with an administrator component 118A, 118S. Other components may be included as well. The kernel space includes one or more drivers 120A, 120S and a high availability manager (“HAM”) 122A, 122S. A transport 126 comprises a communication link between the active FSS 112A and the standby FSS 112S.
A focus of the high availability nature of the present system is to provide fault resilient instances of “services.” A service generally refers to a collection of related software that performs a predetermined function. In this context, for example, the software supporting a switch 52 could be considered a service, as would a storage virtualization facility running on a virtualization co-processor blade. A service may comprise one or more service “components.” The components are generally executable routines. A switch service, for example, may contain various individual components, including application level components and one or more kernel level components such as switch and network drivers.
Each component typically has “state” information associated with it. The state information may include configuration and operational values of the software and hardware associated with the component. The state of the service generally comprises the aggregate of the states of the various components comprising the service.
A service “instance” generally refers to a single, fully-specified, configuration of a service. An instance comprises the state of the set of user-level applications and associated kernel state that represent a unique instance of the service. There may be multiple instances of a specific service type running on a given CP 72. For example, two switch service instances may run on a single CP. Multiple types of services may also run on a single computing platform. An example of this is a Fibre Channel-to-iSCSI bridge service instance supporting an iSCSI-Fibre Channel Bridge blade in the same chassis with four switch services supporting other Fibre Channel switches in the same chassis.
In accordance with a preferred embodiment of the invention, multiple “copies” (also called “images”) of a single service instance may also be included. Each of these images is placed into one of two modes: Active or Standby. At any single point in time, only one image of a service instance is active. The active image is fully operational and is what the external logic sees as “the service.” Zero or more images of the service instance may be in the standby mode. A standby image preferably runs on a different CP than the CP on which the active image runs. If desired, however, a standby image may run on the same CP as its active image counterpart. Further, more than one standby image can be included as desired.
A service instance is identified by a service instance identifier, which may be an alphanumeric name or other type of identifier. All images (active and standby) of a specific service instance preferably have the same name. Different instances instantiated on a given computing platform have unique names. Active and standby images preferably occupy separate namespaces, thereby allowing an active image and a standby image of a service instance to exist on the same CP at the same time. Service instance names are the basis for connections between images. That is, a standby image of service instance XYZ will connect to the active image of service instance XYZ. Service instance names can take whatever form is desired by the system architect. For example, the names may comprise two parts: a service name (an ASCII string) and the instance name (another ASCII string) separated by a period (‘.’).
As noted above, a service “component” is an entity that performs some subset of the actions of a service and maintains some set of state relating to its function. A component may be a user-level process (i.e., an application), a set of state in a multi-threaded application, a kernel thread, or a related set of state information maintained by a kernel component (e.g., by device drivers). In accordance with the preferred embodiment of the invention, a service component is the basic element involved in state synchronization. The FSS 112 facilities route state synchronization messages from a component in an active image to its peer component (i.e., the component with the same name) in the corresponding standby image(s).
A service component preferably is identified by the name of the service instance of which it is a member and by a service component identifier, which also may be an alphanumeric name or other identifier. A service component name preferably comprises an arbitrary ASCII string. The only constraint on the contents of a component name is that it be unique within the service—that is, no two components should have the same component name within a given service.
Referring still to FIG. 4, HAM 122 preferably is responsible for deciding where (i.e., on which CP) active and standby service instance images are to be launched. Before launching the service instance images, the HAM 122 preferably initializes the FSS facilities 112 on the CP 72 with the specifics of the service instances to be run on the CP. The HAM 122 performs this action by creating a service which identifies the service name and the names of all of the components comprising the service. The HAM 122 then calls FSS 112 to create a service instance image identity for each service instance image (active or standby) to be run on the CP. This request preferably includes the name of the service instance, the initial mode of the image (either active or standby) and, if the mode is standby, the network address identifier for the FSS service where the active image is to be run. Creating the service instance image is a configuration operation—it preferably does not cause processes to be launched or kernel state to be created (other than within the FSS driver itself).
In accordance with the preferred embodiment of the invention, all images initialize to the standby mode. Then, one of the images is selected to transition to the active mode. The other image(s) remain(s) in the standby mode.
Once the service is created, it is the responsibility of the FSS supporting a standby image (such as FSS 112S in FIG. 4) to connect to the FSS supporting the active image. The active image listens for a connection request from the standby image. When the HAM 122 creates a standby service instance image that references a separate CP, the FSS 112S preferably establishes a connection to the image on the remote CP. If the remote CP does not answer, the FSS periodically will retry to establish a connection to the image on the remote active CP. The establishment of this inter-FSS connection occurs when the FSS is configured and is independent of whether the actual service instance image has been launched.
A service instance image is considered to be initiated when its various constituent components and relevant kernel context are active. Referring still to FIG. 4, when a service instance is initiated, each component within the service “registers” with FSS 112. As part of the registration process, the components identify themselves by service instance name and component name. This registration establishes a messaging channel with FSS that allows control messages to be sent from FSS to the component and for state synchronization messages to flow from the active components and to the standby components. When all components of a service instance image have registered with FSS, the image is considered “complete,” as noted above. The HAM 122 on each image is notified when both the active and standby images are complete. The HAM 122 for the standby image 110S image preferably then initiates a synchronization process by which the active image's component state information is provided to the standby image. In accordance with the preferred embodiment, synchronization is performed between pairs of active/standby components. The dashed lines between components in FIG. 4 indicate this synchronization process. By obtaining the active image's state, the standby image can quickly become the active image and pick up where the previous active image left off in the event a fail-over is needed.
The HAM 122 on the standby image initiates state synchronization by sending a SYNC_START message to FSS 112S specifying the instance name. This message is forwarded to the FSS 112A of the active image and all components of the active image consequently are sent a SYNC_START message. Upon receiving a SYNC13 START message, an active component (e.g., 114A, 116A) preferably provides (“updates or “sends”) its current state in one or more state update messages it sends to its standby component counterpart. The first of such messages is marked SYNC13 BEGIN indicating to the receiving standby component that this and subsequent messages comprise a “sync dump.” The standby component (e.g., 114S, 116S) generally responds to reception of a sync dump by replacing its current view of the state of its active counterpart with the new state being provided to it by its counterpart component. The last message in the sync dump sequence is marked with SYNC_END. All intermediate messages in the sequence represent changes in state and are applied incrementally to the standby component image state. These intermediate messages may be to add state information to the standby component, delete state information or modify state information, although typically the update messages within a sync dump will simply add new information. Preferably, the active component will dump its state “atomically” by sending the entire dump sequence without allowing any changes to its state to occur between the sending of the SYNC_BEGIN and the SYNC_END messages. Preferably, the FSS service on the standby CP will store in its own buffer all messages in a dump sequence until the final SYNC_END message is received, at which time all of the messages will be delivered to the standby peer component. When the message marked SYNC_END is successfully delivered to the standby component, that component is marked as “synchronized.” As noted above, when all components within an image are synchronized, the state of the image is considered to be “synchronized” as well. It should be noted that the synchronized state is generally meaningful only to the standby image because it is to that image that a fail-over would occur. However, the state may be reported to the HAM 122A on the active side as well.
Once the images are brought up and the active and standby images are synchronized, the system operates in accordance with its normal, run-time functionality. During the course of operation, the state associated with each component may change. Another function performed by the FSS facilities 112 during normal run-time is to provide updated state from the components in the active image to the corresponding components in the standby image. As such, when an active component experiences a change in state, a state update message is sent to the corresponding standby component. As noted above, the change in state may include new information, a change to existing information, or the deletion of old information. The new information may include processing status information, for example noting of the reception of an external request for name server information followed by notice that the request had been fulfilled. In some cases, it will be advantageous for the active component to know that an update has been reliably sent to the standby CP before taking further action related to the information in that update. Such an update is termed a “synchronous” update. Preferably the active component may either “block” (stop further processing) until an acknowledgment for a particular synchronous update has been received, or delay further processing related to individual synchronous updates, in which case the active component will be sent an acknowledgment notification message for each such synchronous update. As explained previously, by keeping the standby components fully apprised of the continuing changes in the state of the active component, the standby image will be ready to fail-over at a moment's notice with little, if any, disruption in services.
Some state updates may not be provided to the standby image before the active image fails. The software on the standby CP accounts for this situation, and performs a consistency check when it takes over to determine whether some updates may have been missed.
Efficient Staged Failover
An active image may fail, thereby ceasing to be fully operational. When an active image has failed, control transitions to the standby image. This process is called a “fail-over.” In general, the system may be designed to cause a fail-over as a result of numerous types of failures. However, fail-overs preferably occur upon the occurrence of a non-recoverable active CP/image failure. Because of the nature of the fault experienced by the active image, the active image may be unable to initiate the passing of control to the standby image. Instead, and in accordance with the preferred embodiment, the standby image takes control from the active image. Accordingly, the HAM 122 on the standby image includes a mechanism to detect a failure in the active image. In a preferred embodiment of the invention, a multiplicity of failure detection mechanisms will be used to ensure timely failover. One mechanism unique to the FSS facilities is a TAKE_OVER message sent by the active CP to the standby CP when the FSS facility itself is aware of a failure requiring failover. Other such mechanisms may include support in the hardware of the CPs to indicate one or more failure conditions on the active CP, and a “heartbeat” protocol using messages sent between the CPs at a regular interval to detect whether the other CP is still functioning normally. One skilled in the art may easily adapt any of a multiplicity of well-known detection mechanisms to the purpose of initiating the fail-over function.
Referring to FIGS. 3 and 4, when the HAM 122S on the standby image 110S detects, or is notified of, a failure of the active image, the HAM 122S sends a TAKE_CONTROL message to the standby image. In response, the FSS 112S also sends a GIVE_UP_CONTROL message to the active image in case the active image is sufficiently functional to receive and correctly interpret such a message. The standby FSS 112S also changes its image's mode to “active” and sends all of the standby components a TAKE_CONTROL message. Each standby component then takes whatever action is required for it to be come the active component using the state of its previous active counterpart component as its starting point. This permits the standby component to become the active component and resume where the previous active component left off.
When a fail-over has occurred, the service instance that is now active runs without a standby image (unless the system included more than one standby image). Without a standby image, the now active image is vulnerable to a service outage in the event of another failure. However, a new standby image can be created, if desired, on the CP 72 that ran the previously active image that failed. Also, the CP 72 with the failed image can be replaced and a standby image created on the newly installed CP.
The following describes more detail regarding the fail-over process. All components originally are brought up to a standby mode as explained above. When a component is requested to become active, the component transitions through a “recovery” process which may include several stages of processing. Referring now to FIG. 5, four exemplary components are shown with their associated stages. Component 1 includes three stages. Components 2 and 3 include two stages each and component 4 includes four stages. The stages associated with each component are performed in order (stage 1, then stage 2, then stage 3, etc.). Some of the stages, however, depend on stages associated with other components. For example, stage 2 of component 1 depends on component 2's stage 2. This means that stage 2 of component 1 should not run until stage 2 of component 2 completes. Similarly, stage 1 of component 3 depends on both stage 2 of component 2 and stage 3 of component 1 meaning that both component 2's stage 2 and component 1's stage 3 should complete before component 3's stage 1 is permitted to start. Also, stage 3 of component 4 depends on stage 2 of component 3.
The preferred embodiment of the invention includes an efficient mechanism to ensure the dependencies between stages in the recovery process. To that end, a staging table is used. The staging table preferably is created and stored in each CP's volatile memory 86 as shown in FIG. 3 (staging table 90). The following describes how the staging table 90 is created and used.
The staging table 90 is generated by the CP 72 during compile-time of the software that runs on the CP. The information used to generate the staging table includes component identifiers, stage identifiers and dependency information. The dependency information may include the identifier (e.g., name) of the stages on which the stage depends. Such information may be stored in a text file on the CP's non-volatile memory 92. Such a file is shown in FIG. 3 as component description file 100.
An exemplary embodiment of the staging table 90 is shown in FIG. 6. As shown, the staging table includes a plurality of columns 150 (150a–150h) and a plurality of rows 160. Each row 160 corresponds to a component and includes that component's stages. Each column 150 generally corresponds to a time slice in which any stage listed in that column can be run. Each cell 152 in the table 90 includes a value. The value may comprise a stage identifier or a value (e.g., a null value). FSS 112 accesses the staging table 90 to schedule the stages of the various components. The number of columns provided in the table and the placement of the null values are such that the inter-stage dependency information is inherently built into the table and preferably computed at compile time.
Referring still to FIG. 6, FSS schedules the various stages of the recovery process by accessing the first column in the staging table (column 150a). FSS finds three stages in column 150a—stages 1 of components 1, 2 and 4. Component 3 shows a null value in column 150a indicating that no stage of component 3 can be scheduled at this time. FSS then requests that stages 1 of components 1, 2 and 4 begin execution. Each stage preferably reports back to FSS upon completion of that stage so that FSS will know that the stage has completed. Once the stages in column 150a have completed, FSS then examines the next column (column 150b) to determine which stage(s) can be scheduled next. As shown in column 150b, stages 2 of components 2 and 4 are listed. Accordingly, FSS requests those stages to be executed. This process repeats itself for the remaining columns 150c–150h until all stages in the table have been executed.
FSS preferably includes an internal component called “SCM0” that has some reserved stages (stages whose name FSS recognizes). These stages are used to block further recovery operation of a service until all services are blocked. When all recovering services have reached the BLOCKING stage, FSS instructs the services to proceed to completion. This arrangement allows the critical stages of recovery to happen faster in the Standby CP, thereby improving the recovery time of the switch.
By listing the stage identifiers in the appropriate cells 152 in the staging table 90, the inter-stage dependency links are implemented. For example, as noted above, stage 1 of component 3 is dependent on component 2, stage 2 and component 1, stage 3. As shown in table 90, stage 1 of component 3 is listed in column 150e. Stage 2 of component 2 is shown in column 150b and stage 3 of component 1 is shown in column 150d, both columns of which precede column 150e in which stage stage 1 of component 3 is listed. Thus, component 3, stage 1 will not be scheduled for execution by FSS until the stages on which it depends have completed. Moreover, column 150e is the earliest column in which stage 1 of component 3 could be listed. Although alternatively it could be included in subsequent columns, stage 1 of component 3 preferably is listed in column 150e to minimize the amount of time needed to perform the recovery process. A similar analysis applies to all other dependencies enforced in the staging table 90. The staged recovery process described herein permits FSS 112 to efficiently schedule the various component stages of the recovery process.
Unique XIDs for each CP
According to their normal operation, CPs 72 send requests of various type to switches 52, other CPs, and other entities in the network. The requests may originate from the CP or from another device in the system (e.g., another CP). In the latter case, the CP receives the request and sends it as required. Some of these requests may result in data or other information being returned to the CP that originated the requests. Thus, when an image, that was previously a standby image, becomes active one or more requests may still be working their way through the system in various degrees of completeness. Moreover, the fail-over may have occurred after a request was sent out, but before a response was returned.
In accordance with another aspect of the preferred embodiment, once a standby image becomes active, the now active image re-issues all pending requests originated by the previous active image. For each request that might possibly require a restart, the standby image was preferably sent a “request start” notification message by the (formerly) active CP, using a synchronous update, and the standby CP would have added the request to a list of outstanding requests. For each such request that was completed, the (formerly) active CP, would have sent a second “request complete” message, at which time the standby image would have deleted its outstanding request state. When a standby image becomes active, it simply restarts all outstanding requests for which no completion message has been received. With all previously pending requests re-issued, multiple responses may be received by the newly active CP for the same request. That is, the remote entity that receives the original and re-issued requests will respond accordingly and provide two responses—one resulting from the original request and the other resulting from the re-issued request. Preferably, however, the newly active image uses only the response resulting from the re-issued request; the response associated with the original request is not used and may be ignored or otherwise trashed by the image.
FIG. 7 depicts this process. In block 170, the newly active image preferably retries all requests that are still pending when the previous active image failed-over to the standby image. In block 172, the newly active image receives response data associated with one or more of the original or re-issued requests and in decision block 174 determines whether the response data is “old” (i.e., pertains to an original request) or “new” (i.e., pertains to a re-issued request). If the response data is old, the data is ignored in block 176. Otherwise, new data is accepted and used, as is described in block 178.
In accordance with a preferred embodiment of the invention, each CP 72 includes a mechanism to be able to determine whether response data pertains to a request that originated from an image on that CP or on another CP. Referring briefly to FIG. 3, that mechanism includes an exchange identifier (“XID”) set 88. XIDs are used in accordance with conventional Fibre Channel usage to uniquely identify a “transaction” between entities in the network. Each transaction refers to a data conversation in which requests and responses are passed back and forth. A CP 72 may have multiple transactions on-going at any one point in time and each transaction is assigned a different XID value to permit the CP to distinguish one transaction from another. The XID range 88 includes at least one XID value, and typically will include a plurality of XID values.
The XID values preferably are unique to each CP meaning that each CP 72 has a unique, non-overlapping range of XID values. The XID values preferably are assigned by the CP's FSS facility 112. Through the CPs' FSS facilities' ability to communicate with one another, the range of XID values used by one CP can be conveyed to the other CP to avoid re-use of the same XID range. Alternatively, on initialization, each CP, via HAMs 122, can coordinate with each other to use a different range of XID value. At any rate, upon a fail-over, the newly active image will use a different range of XID values than was used by the previous active image.
An XID value associated with the CP is included in each request message that the CP sends to another entity in the network, and the same XID value is included in the response message that is returned to the CP. Thus, in block 174 a CP's image can determine whether response data is associated with a request that originated from that CP or from another CP by examining the XID value in the response itself.
This technique permits a CP, which issues requests containing XIDs, to be transitioned from a first state to a second state. The XID(s) used in the first state are different from the XID(s) used in the second state. The CP may receive a response to an issued request and determine whether the response contains an XID pertaining to the first state or the second state. If the XID in the response pertains to the first state, the CP ignores any data contained in the response. If, however, the response contains an XID pertaining to the second state, the CP processes data contained in the response.
Single CP Firmware Change
Although the system may include multiple CPs 72 for redundancy, the system can still operate with only a single CP. A user may desire to change the firmware executing on the CP for a variety of reasons. For example, the current version of firmware may have a defect (i.e., a “bug”). Further, a new and improved version of firmware may be available that implements additional and/or improved functionality. For whatever reason, a user may desire to replace the CP's firmware which is stored in non-volatile memory 92. The following description explains a preferred embodiment for firmware replacement in a way that maintains the single CP available for operation as much as possible (i.e., “high availability”).
In a multiple CP system, the new firmware can be brought up as a standby image. Then, using the process described above, the active image's state information can be dumped to the active in a synchronization process. Once synchronized, the standby image (which comprises the new firmware) can force a fail-over to then become the new active image. If desire, the previous active image can repeat the above process to replace itself with the new firmware. The following description explains a preferred embodiment for replacing firmware in a single CP system using much of the functionality described above for replacing firmware in multi-CP system.
Referring now to FIG. 8, in conjunction with FIG. 3, a method is shown by which firmware can be changed on a CP in a system for which no standby image exists. The method shown utilizes much of the logic explained above and minimizes the amount of down time experienced by the CP during the firmware change over. In block 200, the new firmware (which may comprise one or more of the service components) is stored in non-volatile memory 92 (FIG. 3) which may comprise flash memory, a hard drive or ROM as explained previously. In block 202 a reboot manager utility 99 is launched and is designated as a standby image to the currently active image running on the CP. The reboot manager 99 opens a management channel to FSS 112 and creates a standby image, pointing at the active image. A “loopback” transport is created by which state updates from the active image are looped back internally to the standby image in the same CP.
In block 204, the reboot manager 99 registers itself with FSS 112 as all the components of the standby image. Then, in block 206, the new standby image (an instance of the reboot manager) is synchronized to the current active image as was described above. This process thus uses the same basic logic and code as would be used if the standby image was a true copy of the active image running on another CP. Thus, the standby reboot manager image sends a SYNCH_START message to the active image, thereby causing all components of the active image to begin a synchronization dump. As the state updates begin flowing to the reboot manager 99, the messages are saved in the CP's non-volatile memory (e.g., in a file), rather than being applied to component state as would be done if a true standby image was running.
When all components of the active image have finished the synchronization dump, a HALT message is sent to the active image (block 208) by FSS upon request from the reboot manager to cause the active image to cease all operations. When the halt state has been reached, a reboot operation can be performed. A reboot may be necessary to ensure proper operation of the operating system, as would be understood by one of ordinary skill in the art. As such, in block 210, the CP 72 is rebooted with the newly loaded firmware. Based on information passed to the new system image on reboot, the new firmware service image comes up as a standby image, pointing to an active image. In block 212, the reboot manager is launched again as an active image with loopback enabled and registers itself with FSS as all the components of the instance. Then, in block 214 the standby image (which comprises the newly loaded firmware) synchronizes to the active image during which all previously saved state information is loaded into the components of the standby image. Finally, in block 216, a fail-over is forced from the active image to the standby image. This can occur by issuing a TAKE_CONTROL message to the standby image which causes the standby image to take control of the physical resources, using the saved state as its initial state.
In this manner, new firmware can be loaded onto the CP using as much of the existing mechanisms designed for multiple CP systems as possible. Further, the firmware change can occur with little down time. In some situations, a reboot of the CP may not be necessary as would be understood by one of ordinary skill in the art. In those situations, the reboot block 210 can be skipped.
As explained herein, a CP's software comes up as a standby image. This reduces the complexity of the code.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

## Claims

1. A method of bringing up a control processor to an active state, said control processor executing multiple software components, each component being brought up to an active state via one or more consecutive stages, and some of said stages being dependent on the prior execution of stages of different components, said method comprising:
(a) creating a staging table which includes identifiers of the component stages arranged in the order in which the components should be executed, said staging table also including values separating at least some of the stage identifiers so as to implement the inter-stage dependencies;
(b) accessing said staging table and retrieving the identifiers of one or more stages;
(c) executing the stages identified by the identifiers retrieved in (b);
(d) receiving acknowledgements after the stages in (c) have completed their execution; and
(e) repeating (b)–(d) for additional stages.

2. The method of claim 1 wherein (a) includes forming rows and columns in said staging table, each row corresponding to a component and the columns including the stage identifiers and values.

3. The method of claim 2 wherein said a first stage of a first component depends on the prior execution of a second stage of a second component, and the first stage's identifier is included in a column that is after the column in which the second stage's identifier is included, so that the first stage will not be executed until after the second stage executes and acknowledges its completion.

4. The method of claim 2 wherein said a first stage of a first component depends both on the prior execution of a second stage of a second component and on the prior execution of a third stage of a third component, and the first stage's identifier is included in a column that is after the column in which the second stage's identifier is included and the column in which the third stage's identifier is included, so that the first stage will not be executed until after both the first and second stages execute and acknowledge their completion.

5. The method of claim 1 wherein the valves comprise null values.

6. The method of claim 1 wherein the identifiers comprise names.

7. The method of claim 1 wherein (a) is performed during compile time.

8. A system, comprising:
a plurality of electronic devices; and
a control processor having memory in which a staging table is stored, said control processor being coupled to and controlling the electronic devices, and a plurality of software components execute on said control processor;
wherein said control processor transitions to an active state of operation by executing one or more stages associated with each software component wherein some stages are dependent on the prior execution of stages of different components, said transition to the active state also includes accessing the staging table to retrieve identifiers of stages to execute, said identifiers are arranged in said table so as to implement the inter-stage dependencies.

9. The system of claim 8 wherein said staging table comprises rows and columns, each row corresponding to a component and the columns including the stage identifiers.

10. The system of claim 9 wherein some of the columns include values usable to implement the inter-stage dependencies.

11. The system of claim 10 wherein the values comprise null values.

12. The system of claim 8 wherein a first stage of a first component depends on the prior execution of a second stage of a second component, and the first stage's identifier is included in a column of the staging table that is after the column in which the second stage's identifier is included, so that the first stage will not be executed by said control processor until after the second stage executes and acknowledges its completion.

13. The system of claim 8 wherein a first stage of a first component depends both on the prior execution of a second stage of a second component and on the prior execution of a third stage of a third component, and the first stage's identifier is included in a column of the staging table that is after the column in which the second stage's identifier is included and the column in which the third stage's identifier is included, so that the first stage will not be executed by said control processor until after both the first and second stages execute and acknowledge their completion.

14. The system of claim 8 further including more than one control processor with one control processor being active and the other control processor being a standby processor, and the standby processor takes control away from the active processor upon the occurrence of a fault with the active processor, and the standby processor accesses its staging table in order to become active.

15. The system of claim 8 wherein said electronic devices comprise network switches.

16. The system of claim 8 wherein said control processor includes a fabric state synchronization (“FSS”) facility running thereon which permits said control processor to be synchronized to another control processor, and said FSS access the staging table.

17. The system of claim 8 wherein the identifiers comprise names.

18. The system of claim 8, wherein the staging table is generated during compile time.

19. A control processor adapted to perform a staged startup of a plurality of software components, each component being brought up to an active state in one or more stages, some of the stages being dependent on other stages associated with different components, the control processor comprising:
a CPU;
memory coupled to said CPU, said memory containing a staging table which includes names of the stages arranged in the order in which the components should be executed, said staging table also including null values separating at least some of the stage names so as to implement the inter-stage dependencies; and
firmware stored in said memory and executed by said CPU, said firmware causing said control processor to:
(a) access said staging table and retrieve the names of one or more stages;
(b) execute the stages identified by the names retrieved in (a);
(c) receive acknowledgements after the stages have completed their execution; and
(d) repeat (a)–(c) for additional stages.

20. The control processor of claim 19 wherein said staging table comprises rows and columns, each row corresponding to a component and the columns including the stage names.

21. The control processor of claim 19 wherein some of the columns include the null values usable to implement the inter-stage dependencies.

22. The control processor of claim 19 wherein a first stage of a first component depends on the prior execution of a second stage of a second component, and the first stage's name is included in a column of the staging table that is after the column in which the second stage's name is included, so that the first stage will not be executed by said control processor until after the second stage executes and acknowledges its completion.

23. The control processor of claim 19 wherein a first stage of a first component depends both on the prior execution of a second stage of a second component and on the prior execution of a third stage of a third component, and the first stage's name is included in a column of the staging table that is after the column in which the second stage's name is included and the column in which the third stage's name is included, so that the first stage will not be executed by said control processor until after both the first and second stages execute and acknowledge their completion.

24. The control processor of claim 19 further including a fabric state synchronization (“FSS”) facility running thereon which permits said control processor to be synchronized to another control processor, and said FSS performing (a)–(d).

25. The control processor of claim 19 wherein the firmware causes said control processor to perform (a)–(d) when said control processor takes control away from another control processor that has failed.

26. A computer readable storage medium for storing an executable set of software instructions that are executable by a CPU, said software instructions being operable to perform a staged startup up of a control processor which executes a plurality of software components, each component starting up via one or more stages and some of said stages being depend on stages of different components, said software instructions comprising:
(a) a means for accessing a staging table, which includes names of the stages arranged in the order in which the components should be executed, said staging table also including null values separating at least some of the stage names so as to implement the inter-stage dependencies, and retrieving the names of one or more stages;
(b) A means for executing the stages identified by the retrieved names;
(c) a means for receiving acknowledgements after the stages have completed their execution; and
a means for repeating (a)–(c) for additional stages.

27. The storage medium of claim 26 wherein said staging table comprises rows and columns, each row corresponding to a component and the columns including the stage names.

28. The storage medium of claim 27 wherein some of the columns include the null values usable to implement the inter-stage dependencies.

29. The storage medium of claim 26 wherein a first stage of a first component depends on the prior execution of a second stage of a second component, and the first stage's name is included in a column of the staging table that is after the column in which the second stage's name is included, so that the first stage will not be executed by said (b) means until after the second stage executes and acknowledges its completion.

30. The storage medium of claim 26 wherein a first stage of a first component depends both on the prior execution of a second stage of a second component and on the prior execution of a third stage of a third component, and the first stage's name is included in a column of the staging table that is after the column in which the second stage's name is included and the column in which the third stage's name is included, so that the first stage will not be executed by said (b) means until after both the first and second stages execute and acknowledge their completion.

31. The storage medium of claim 26 further including a means for performing (a)–(d) when control is taken away from another control processor that has failed.