# Patent

## Title
Digital/analog converter, display driver and display

## Abstract

An n-bit digital/analog converter is provided for converting an n-bit digital word to a corresponding voltage. The converter comprises an (n−1) bit bufferless switched capacitor digital/analog converter (10) having an output (Vout) for direct connection to a capacitive load (CLOAD). The (n−1) bit converter (10) also has first and second reference voltage inputs (V1, V2) and an (n−1) bit digital input. An (n−1) bit selective inverter (131, . . . , 13n−1, 141, . . . , 14n−1) supplies the (n−1) least significant bits to the digital input and inverts them if the most significant bit has a certain value. A switching arrangement (11, 12) connects the first and second reference voltage inputs (V1, V2) to receive first and second or second and first reference voltages depending on the value of the most significant bit.

## Background
FIELD OF THE INVENTION
The present invention relates to a digital/analog converter, to a display driver including such a converter, and to a display including such a driver. Such a converter may be used, for example, for driving matrix columns of a liquid crystal display. A particular application of such a converter is in small display panels for portable applications where power consumption is at a premium.
BACKGROUND OF THE INVENTION
FIG. 1 of the accompanying drawings illustrates a known type of switched capacitor digital/analog converter (DAC) for converting an n-bit digital word to a corresponding analog output. The DAC comprises n-capacitors C1, . . . , Cn with the capacitance Ci of each ith capacitor being equal to 2(i−1) C1. The DAC further comprises a terminating capacitor CTERM connected between the input of a unity gain buffer 1 and ground. The first electrodes of the capacitors C1, . . . , Cn are connected together and to the first terminal of the terminating capacitor CTERM. The second terminal of each of the capacitors C1, . . . , Cn is connected to a respective switch, such as 2, which selectively connects the second electrode to a first or second reference voltage input V1 or V2 in accordance with the state or value of a corresponding bit of the digital word. The output of the buffer 1 drives a capacitive load CLOAD, for example in the form of a data line or column electrode of an active matrix of a liquid crystal device.
The DAC has two phases of operation, namely a resetting or “zeroing” phase and a converting or “decoding” phase, controlled by internally generated timing signals which are not illustrated in FIG. 1. During the zeroing phase, the first and second electrodes of the capacitors C1, . . . , Cn and the first electrode of the terminating capacitor CTERM are connected together by an electronic switch 3 and to the first reference voltage input V1. The capacitors C1, . . . , Cn are therefore discharged so that the total charge stored in the DAC is equal to V1CTERM.
During the decoding phase, the second electrode of each capacitor Ci is connected to the first reference voltage input V1 or to the second reference voltage input V2 according to the value of the ith bit of the digital input word. The charge stored in the DAC is given by:




  Q
  =
  
    
      
        ∑
        i
      
      ⁢
      
        
          b
          i
        
        ⁢
        
          
            C
            i
          
          ⁡
          
            (
            
              
                V
                DAC
              
              -
              
                V
                2
              
            
            )
          
        
      
    
    +
    
      
        ∑
        i
      
      ⁢
      
        
          (
          
            1
            -
            
              b
              i
            
          
          )
        
        ⁢
        
          
            C
            i
          
          ⁡
          
            (
            
              
                V
                DAC
              
              -
              
                V
                1
              
            
            )
          
        
      
    
    +
    
      
        V
        DAC
      
      ⁢
      
        C
        TERM
      
    
  




where bi is the ith bit of the input digital word and VDAC is the voltage at the first electrodes of the capacitors C1, . . . , Cn and CTERM. The output voltage is therefore given by:





  
    V
    DAC
  
  =
  
    
      V
      OUT
    
    =
    
      
        
          
            
              ∑
              i
            
            ⁢
            
              
                b
                i
              
              ⁢
              
                C
                i
              
            
          
          
            
              
                ∑
                i
              
              ⁢
              
                C
                i
              
            
            +
            
              C
              TERM
            
          
        
        ⁢
        
          (
          
            
              V
              2
            
            -
            
              V
              1
            
          
          )
        
      
      +
      
        V
        1
      
    
  




In general, Ci=2(i−1) C1 and C1 =CTERM. This results in a set of output voltages which are linearly related to the input digital word.
In order to isolate the load capacitance from the DAC and to prevent it from affecting the conversion process, the unity gain buffer 1 is provided. However, such buffers are a substantial source of power consumption. If the buffer 1 were to be omitted, the terminating capacitance would be increased by the addition of the load capacitance so that the maximum output voltage from the DAC would be given by:




  
    V
    
      OUT
      ⁡
      
        (
        MAX
        )
      
    
  
  =
  
    
      
        
          
            ∑
            i
          
          ⁢
          
            C
            i
          
        
        
          
            
              ∑
              i
            
            ⁢
            
              C
              i
            
          
          +
          
            C
            TERM
          
          +
          
            C
            LOAD
          
        
      
      ⁢
      
        (
        
          
            V
            2
          
          -
          
            V
            1
          
        
        )
      
    
    +
    
      V
      1
    
  




The effect of this may be reduced by increasing the value of the switched capacitors. However, this increases the power consumption of and the area of an integrated circuit occupied by the DAC. In order to achieve voltages near to the higher reference voltage, such as that supplied to the reference voltage input V2, the capacitances must be increased substantially.
Another technique for compensating for this effect is to increase the higher reference voltage supplied to the input V2. However, this also increases the power consumption of the DAC and may also require more complex or powerful circuitry to generate the higher reference voltage.
In some applications, DACs are required to generate an output voltage as a non-linear function of the input digital word. For example, FIG. 2 illustrates the required transfer function when a DAC is used as part of a driving arrangement for a liquid crystal display and FIG. 3 of the accompanying drawing illustrates how such a transfer function is modified in order to provide gamma correction. GB2388725 discloses a non-linear DAC in which non-linearity is achieved by providing switched capacitors which are not binary-weighted. By using such an arrangement with a relatively large terminating capacitor, it is possible to connect the DAC directly to the load and without an intermediate buffer as illustrated in FIG. 4 of the accompanying drawings. However, the same limit on the maximum output voltage as described hereinbefore applies to such an arrangement. Further, such a DAC is restricted to providing transfer characteristics with rotational symmetry. For example, in the case of a 6-bit converter within input words or codes in the range of 0 to 63, Vb−V0=V63−Vb′, where b is a 6-bit digital code and b′ is the ones complement thereof as illustrated in FIG. 5 of the accompanying drawings. Thus, although a DAC of this type can approximate the curve illustrated in FIG. 2, in general it cannot adequately approximate non-symmetrical curves such as that illustrated in FIG. 3.
ACKNOWLEDGEMENT OF THE PRIOR ART
FIG. 6 of the accompanying drawings illustrates a non-linear DAC of the type disclosed in U.S. Pat. No. 6,380,917 and in Matsueda et al, “A 6-bit-colour low temperature poly-SiTFT-LCD with integrated digital data drivers”, SID '98 digest, pp. 879–882. Such a non-linear DAC may be used to approximate the transfer characteristics of liquid crystal devices. The 6-bit example illustrated in FIG. 6 does not require a buffer or terminating capacitor and comprises five binary-weighted capacitors whose connections are controlled by signals derived from the five least significant bits of the input word.
The most significant bit D5 controls the selection of reference voltage sources VO1, VO2, VC1 and VC2.
During a zeroing phase, the first electrode of the load capacitance (illustrated as a data line capacitance in FIG. 6) is charged to the reference voltage VC1 or VC2 depending on the value of the most significant bit and the first electrodes of the switched capacitors are discharged to the reference voltage VO1 or VO2 similarly depending on the value of the most significant bit. If the value of the most significant bit D5 is zero, the five least significant bits are supplied without inversion whereas, if the value of the most significant bit is 1, the five least significant bits are inverted. During the decoding phase, the first electrode of the load capacitance is connected to the first electrodes of a selection of the switched capacitors controlled by the inverted or non-inverted values of the five least significant bits. The resulting output voltage of the DAC is given by:




  
    V
    OUT
  
  =
  
    
      
        
          V
          
            C
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          C
          LOAD
        
      
      +
      
        
          V
          01
        
        ⁢
        
          
            ∑
            i
          
          ⁢
          
            
              b
              i
            
            ⁢
            
              C
              i
            
          
        
      
    
    
      
        
          ∑
          i
        
        ⁢
        
          
            b
            i
          
          ⁢
          
            C
            i
          
        
      
      +
      
        C
        LOAD
      
    
  




The transfer function is inherently non-linear and is of the form illustrated in FIG. 7 of the accompanying drawings. Using the most significant bit to control the reference voltages and inversion of the least significant bits effectively provides two output curves, which may be combined as illustrated in FIG. 8 of the accompanying drawings, with rotational symmetry.
The range of transfer characteristics or curves which can be provided by such a DAC is limited to curves of the same general shape although the gradient may be selected by the appropriate selection of capacitance values within the DAC. Also, four reference voltages, some of which are beyond the range of required output voltages, are required. Such an arrangement therefore has the same disadvantages as mentioned hereinbefore.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided an n-bit digital/analog converter for converting an n-bit digital word, were n is an integer greater than 1, comprising: an (n−1) bit bufferless switched capacitor digital/analog converter having an output for direct connection to a capacitive load, first and second reference voltage inputs, and an (n−1) bit digital input; an (n−1) bit selective inverter for supplying to the (n−1) bit digital input the (n−1) least significant bits of the n-bit digital word without inversion when the most significant bit of the n-bit digital word has a first value and with inversion when the most significant bit has a second value different from the first value; and a switching arrangement for connecting the first and second reference voltage inputs to receive first and second reference voltages, respectively, when the most significant bit has the first value and to receive the second and first reference voltages, respectively, when the most significant bit has the second value.
The (n−1) bit converter may comprise (n−1) capacitors whose first electrodes are connected together for connection to the capacitive load. The second electrode of each ith capacitor may be arranged to be connected to the first or second reference voltage input when the ith bit of the (n−1) least significant bits has the first or second value, respectively. The (n−1) bit converter may have a resetting mode in which the first and second electrodes of the capacitors are connected to the first reference voltage input. Each ith capacitor may have a value Ci given by Ci=a(i−1)C1 for 1<i≦(n−1), where a is a positive real number. For example, a may be equal to 2.
The first value may be 0.
The second reference voltage may be greater than the first reference voltage.
The selective inverter may comprise a multiplexing arrangement. As an alternative, the selective inverter may comprise a first memory containing a first look-up table representing a first function addressed by the n-bit digital word. As a further alternative, the selective inverter may comprise (n−1) Exclusive-OR gates, each of which has a first input for receiving the most significant bit and a second input for receiving a respective one of the (n−1) least significant bits.
The converter may comprise a second memory containing a second look-up table representing a second non-linear function addressed by the n-bit digital word.
According to a second aspect of the invention, there is provided a display driver comprising at least one converter according to the first aspect of the invention.
According a third aspect of the invention, there is provided a display comprising a driver according to the second aspect of the invention.
The display may comprise a liquid crystal device.
It is thus possible to provide a converter which does not require a buffer and hence is of lower power consumption. The transfer function of the converter may be linear or non-linear and only two reference voltages are required. These reference voltages may be at the limits of the required output range and are simple to generate with relatively low power consumption. The converter does not have to “dominate” the size of a capacitive load so that integration area can be reduced, power consumption can be reduced and speed of conversion can be increased.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be further described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a simplified circuit diagram of a known DAC;
FIG. 2 is a graph of DAC output voltage against input digital code illustrating a required transfer characteristic for driving a typical liquid crystal display;
FIG. 3 is similar to FIG. 2 but illustrates the use of gamma correction with a gamma value of 2.2;
FIG. 4 is a simplified circuit diagram of another known DAC;
FIG. 5 is a graph similar to FIG. 2 but illustrating the rotational symmetry of the transfer function of the DAC of FIG. 4;
FIG. 6 is a circuit diagram of a further known DAC;
FIGS. 7 and 8 are graphs similar to FIG. 2 illustrating typical transfer functions of the DAC of FIG. 6;
FIG. 9 is a block circuit diagram of a DAC constituting an embodiment of the invention;
FIG. 10 is a simplified circuit diagram of part of the DAC of FIG. 9;
FIG. 11 is a graph illustrating the output range of the DAC of FIG. 9;
FIG. 12 illustrates the use of a look-up table with the DAC of FIG. 9 to provide a non-linear transfer characteristic;
FIG. 13 is a block circuit diagram of a converter constituting another embodiment of the invention; and
FIG. 14 is a block circuit diagram of a converter constituting a further embodiment of the invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The DAC shown in FIG. 9 converts n-bit input words or codes to an output voltage range between and including a lower reference voltage VL and a higher reference voltage VH. The DAC comprises an (n−1) bit switched capacitor DAC 10 of the bufferless type with an output VOUT connected directly to a capacitive load CLOAD, for example comprising a data line of an active matrix liquid crystal device. The DAC 10 has reference voltage inputs V1 and V2 connected to the outputs of 2-input multiplexers 11 and 12 acting as electronic changeover switches controlled by the most significant bit (MSB) bn. First inputs of the multiplexers 11 and 12 are connected to receive the reference voltages VL and VH, respectively, whereas second inputs thereof are connected to receive the reference voltages VH and VL, respectively. When the value of the most significant bit bn is 0, the inputs V1 and V2 are connected by the multiplexers to receive the reference voltages VL and VH. Conversely, when the most significant bit bn is 1, the multiplexers supply the reference voltages VH and VL to the inputs V1 and V2, respectively.
The most significant bit also controls an (n−1) bit selective inverter comprising two-input multiplexers 131, . . . , 13n−1 and inverters 141, . . . , 14n−1. Each of the multiplexers has a first input, which receives the value of the corresponding bit of the (n−1) least significant bits of the input word, and a second input which receives the inverted bit via the corresponding inverter. The multiplexers 131, . . . , 13n−1 act as electronic changeover switches controlled by the value of the most significant bit. Thus, when the value of the most significant bit bn is 0, the (n−1) least significant bits are not inverted whereas, when the value of the most significant bit bn is 1, the (n−1) least significant bits are inverted before being supplied to the DAC 10.
The DAC 10 is shown in more detail in FIG. 10 and is of the bufferless type as illustrated in FIG. 4. Also, no internal terminating capacitor is provided. Instead, as in FIG. 4, the capacitive load CLOAD acts as the terminating capacitor. The capacitance Ci of each capacitor other than the first is equal to the product of the value of the first capacitor C1 and 2(i−1). Also, the sum of the capacitances of the switched capacitors in the DAC 10 is made equal to the load capacitance CLOAD.
The maximum output voltage of the converter shown in FIG. 9 is given by:




  
    
      
        
          V
          
            OUT
            ⁡
            
              (
              MAX
              )
            
          
        
        =
        
          
            
              
                
                  ∑
                  i
                
                ⁢
                
                  C
                  i
                
              
              
                
                  
                    ∑
                    i
                  
                  ⁢
                  
                    C
                    i
                  
                
                +
                
                  C
                  LOAD
                
              
            
            ⁢
            
              (
              
                
                  V
                  2
                
                -
                
                  V
                  1
                
              
              )
            
          
          +
          
            V
            1
          
        
      
    
  
  
    
      
        =
        
          
            1
            2
          
          ⁢
          
            (
            
              
                V
                2
              
              +
              
                V
                1
              
            
            )
          
        
      
    
  




so that the output of the converter is in the range from the voltage at the first reference voltage input V1 to half sum of the reference voltage inputs V1 and V2. Thus, when the most significant bit bn of the input word is 0, the output ranges up from VL to





  
    1
    2
  
  ⁢
  
    
      (
      
        
          V
          H
        
        +
        
          V
          L
        
      
      )
    
    .
  




When the most significant bit is 1, the output ranges from VH down to





  
    1
    2
  
  ⁢
  
    
      (
      
        
          V
          H
        
        +
        
          V
          L
        
      
      )
    
    .
  




Thus, the output voltage of the converter shown in FIG. 9 ranges from VL to VH as illustrated in FIG. 11 so that the reference voltages are at the ends of the range. Generation of the reference voltages is therefore relatively simple and the power required to generate these voltages is substantially minimised. Arranging the converter to suit different output requirements is relatively easy and may involve simply changing the reference voltages to match the required output range.

It is not necessary to provide an output buffer so that what is generally the largest power consumer in a converter, for example, of the type shown in FIG. 1 can be omitted.
The transfer function of the converter may be linear or non-linear depending on the choice of values of the switched capacitors. For example, the binary-weighted capacitance values described hereinbefore may be replaced by other values, such as Ci=a(i−1) C1, where a is a positive real number, by values which are not linearly scaled, by equal values, or by any suitable values for a desired application. Non-linear transfer functions can be provided, for example, by suitable capacitance values and/or by means of look-up tables as described hereinafter.
Only two reference voltages are required and the converter does not have to “dominate” the capacitance of the load. Thus, it is possible to reduce the integration area required for such a converter. Also, power consumption can be substantially reduced and speed of conversion can be increased.
FIG. 12 illustrates a technique for providing a non-linear transfer function with an n-bit DAC 20 of the type shown in FIGS. 9 and 10. A look-up table 21, for example stored in a non-volatile memory, is provided between an m-bit input for receiving m-bit digital words for conversion and the n-bit input of the converter 20. The look-up table 21 acts as non-linear transfer function so that this combined with the linear transfer function of the converter 20 provides a non-linear overall transfer function.
If m is less than n, then the transfer function effectively makes a selection from the range of possible output voltages. If m is equal to n, then the look-up table may reorder and/or combine some codes to provide the non-linear transfer function. If m is greater than n, the look-up table permits the use of a lower resolution converter in a higher resolution system but with a loss of resolution.
The transfer function of the converter 20 does not have to be linear and may therefore be non-linear.
The converter shown in FIG. 13 differs from that shown in FIGS. 9 and 10 in that the arrangement for selectively inverting the (n−1) least significant bits of the input word comprises another look-up table 22, for example stored in a non-volatile memory. The look-up table 22 is addressed by the n-bit input word and represents a function which inverts the (n−1) least significant bits if the most significant bit is 1.
As an alternative, the selective inversion of the (n−1) least significant bits may be combined with other logical functions in the converter. For example, this may be combined with clock signals for controlling the operation of the switches within the converter 10.
The converter shown in FIG. 14 differs from those shown in FIGS. 9, 10 and 13 in that the arrangement for selectively inverting the (n−1) least significant bits of the input word comprises (n−1) Exclusive-OR gates 251, . . . , 25n−1. Each of the gates has a first input which receives the most significant bit and a second input which receives a respective one of the (n−1) least significant bits. When the most significant bit is 1, the gates 251, . . . , 25n−1 invert the n (n−1) least significant bits whereas, when the most significant bit is 0, the gates pass the (n−1) least significant bits without inversion in accordance with the following truth table:












MSM bn
LSB bi
Ex-OR output







0
0
0


0
1
1


1
0
1


1
1
0

## Claims

1. An n-bit digital/analog converter for converting an n-bit digital word, where n is an integer greater than one, comprising: an (n−1) bit bufferless switched capacitor digital/analog converter having an output for direct connection to a capacitive load, first and second reference voltage inputs, and an (n−1) bit digital input; an (n−1) bit selective inverter for supplying to the (n−1) bit digital input the (n−1) least significant bits of the n-bit digital word without inversion when the most significant bit of the n-bit digital word has a first value and with inversion when the most significant bit has a second value different from the first value; and a switching arrangement for connecting the first and second reference voltage inputs to receive first and second reference voltages, respectively, when the most significant bit has the first value and to receive the second and first reference voltages, respectively, when the most significant bit has the second value.

2. A converter as claimed in claim 1, in which the (n−1) bit converter comprises (n−1) capacitors whose first electrodes are connected together for connection to the capacitive load.

3. A converter as claimed in claim 2, in which the second electrode of each ith capacitor is arranged to be connected to the first or second reference voltage input when the ith bit of the (n−1) least significant bits has the first or second value, respectively.

4. A converter as claimed in claim 2, in which the (n−1) bit converter has a resetting mode in which the first and second electrodes of the capacitors are connected to the first reference voltage input.

5. A converter as claimed in claim 2, in which each ith capacitor has a value Ci given by Ci=a(i−1) C1 for 1<i≦(n−1), where a is a positive real number.

6. A converter as claimed in claim 5, in which a=2.

7. A converter as claimed in claim 1, in which the first value is 0.

8. A converter as claimed claim 1, in which the second reference voltage is greater than the first reference voltage.

9. A converter as claimed in claim 1, in which the selective inverter comprises a multiplexing arrangement.

10. A converter as claimed in claim 1, in which the selective inverter comprises a first memory containing a first look-up table representing a first function addressed by the n-bit digital word.

11. A converter as claimed in claim 1, in which the selective inverter comprises (n−1) Exclusive-OR gates, each of which has a first input for receiving the most significant bit and a second input for receiving a respective one of the (n−1) least significant bits.

12. A converter as claimed in claim 1, comprising a second memory containing a second look-up table representing a second non-linear function addressed by the n-bit digital word.

13. A display driver comprising at least one converter as defined in claim 1.

14. A display comprising a driver as defined in claim 13.

15. A display as claimed in claim 14, comprising a liquid crystal device.