# Patent

## Title
Passive integrator and method

## Abstract

In accordance with an embodiment, a passive integrator includes a charge storage element coupled between first and second transistors, wherein the first transistor has a current carrying electrode coupled for receiving a signal and a current carrying electrode coupled to the charge storage element. The second transistor has a current carrying electrode coupled to the charge storage element and a second current carrying electrode coupled to another charge storage element.

## Background
BACKGROUND
The present invention relates, in general, to electronics and, more particularly, to integrators and methods to integrate signals.
In the past, the electronics industry used active circuits to perform signal integration. The active circuits consumed significant power and introduced noise components into the integrated signal. Typically the active circuit included an operational amplifier in a closed loop negative feedback configuration. FIG. 1 is a circuit schematic of a prior art integrator 10. What is shown in FIG. 1 is an operational amplifier 12 in a negative feedback configuration. Operational amplifier 12 has a noninverting input terminal coupled for receiving a reference voltage VREF1 and an inverting input terminal connected to a capacitor 14, which is coupled for receiving an input signal VIN through a switch 16. In addition, the inverting input terminal is connected to an output terminal 26 of operational amplifier 12 through a switch 18 and through a switch 20 and a capacitor 22. Switches 16 and 18 have control terminals that are coupled for receiving a control signal VSW1 and switch 20 has a control terminal coupled for receiving a control signal VSW2. Switch 16 and capacitor 14 have terminals that are commonly connected together and to a terminal of a switch 24. In addition, switch 24 has a terminal coupled for receiving a reference voltage VREF2 and a control terminal coupled for receiving a control signal VSW3.
A load capacitor 28 is coupled between output terminal 26 and a source of operating potential VSS.
The operation of integrator 10 is explained with reference to timing diagram 40 illustrated in FIG. 2. At time t0, control voltages VSW1, VSW2, and VSW3 are at logic low voltage levels and output voltage VOUT is at voltage level VREF1. A reset and sampling phase is initiated by applying a voltage VSW2 at the control terminal of switch 20 at time t1 and a voltage VSW1 at the control terminals of switches 16 and 18 at time t2. More particularly, voltages VSW2 and VSW1 transition from a logic low voltage level to a logic high voltage level at times t1 and t2, respectively. In response to the logic high voltage, switches 16, 18, and 20 close, operational amplifier 12 enters a unity gain operating mode, and the voltages at the inverting and noninverting input terminals equal reference voltage VREF1. Capacitor 14 samples input voltage VIN and is charged to a level Q14S. Because integrator 10 is in a unity gain configuration, capacitor 22 is shorted and as a consequence no charge is accumulated. At time t3, control signal VSW1 transitions to a logic low voltage level ending the sampling period for capacitor 14.
In response to control signal VSW3 transitioning to a logic high voltage level at time t4, switch 24 closes coupling reference voltage VREF2 to capacitor 14 and beginning the integration phase. Output voltage VOUT increases from voltage level VREF1 to a voltage level VINT1. The output voltage VOUT1 after one integration step may be given by Equation 1 (EQT 1):

VOUT1−(VREF1)−(C14/C22)*(VIN−VREF2)   EQT 1

where:
C14 is the capacitance value of capacitor 14; and
C22 is the capacitance value of capacitor 22.
At time t5, control voltages VSW2 and VSW3 transition to a logic low voltage level, opening switches 20 and 24, respectively, and maintaining the charge on capacitor 22.
Another sampling step begins at time t6, at which time control signal VSW1 transitions to a logic high voltage level and ends at time t7 at which time control signal VSW1 transitions to a logic low voltage level. At time t8 control signal VSW2 transitions to a logic high voltage level beginning another integration phase. At time t9 control signal VSW3 transitions to a logic high voltage level and output voltage VOUT transitions from voltage level VREF1 reaching voltage level V INT2 at time t10. In addition, control signal VSW3 transitions to a logic low voltage level at time t10 and control signal VSW2 transitions to a logic low voltage level at time t11. Thus, FIG. 2 illustrates two integration steps. For N integration steps, where N is an integer, the output voltage VOUTN can be given by Equation 2 (EQT 2):

VOUTN−(VREF1)−N*(C14/C22)*(VIN−VREF2)   EQT 2

A drawback with the integrator architecture of FIG. 1 is that it needs an operational amplifier consisting of multiple active elements that are in continuous operation which increases power consumption and introduces noise components.
Accordingly, it would be advantageous to have an integrator and a method for performing integration with reduced power consumption and improved noise performance. It is desirable for the integrator and method to be cost and time efficient to implement.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
FIG. 1 is a circuit schematic of a prior art integrator;
FIG. 2 is a timing diagram for the prior art integrator of FIG. 1;
FIG. 3 is a circuit schematic of a passive integrator in accordance with an embodiment of the present invention;
FIG. 4 is a circuit schematic of a passive integrator in accordance with another embodiment of the present invention;
FIG. 5 is a timing diagram for the integrators of FIGS. 3 and 4 in accordance with an embodiment of the present invention;
FIG. 6 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 7 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 8 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 9 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 10 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 11 is an energy band diagram of the passive integrators of FIGS. 3 and 4 during operation in accordance with an embodiment of the present invention;
FIG. 12 is a circuit schematic of a passive integrator in accordance with another embodiment of the present invention;
FIG. 13 is a circuit schematic of a passive integrator in accordance with another embodiment of the present invention;
FIG. 14 is a timing diagram for the passive integrators of FIGS. 12 and 13 in accordance with an embodiment of the present invention;
FIG. 15 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 16 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 17 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 18 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 19 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 20 is an energy band diagram of the passive integrators of FIGS. 12 and 13 during operation in accordance with an embodiment of the present invention;
FIG. 21 is a circuit schematic of a passive integrator in accordance with another embodiment of the present invention; and
FIG. 22 is a timing diagram for the passive integrator of FIG. 21 in accordance with another embodiment of the present invention.



For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.
It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage or logic low voltage level and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Transistor-Transistor Logic (TTL) system a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level, a logic high voltage, or a logic one voltage and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.
DETAILED DESCRIPTION
FIG. 3 is a circuit schematic of a passive integrator 100 in accordance with an embodiment of the present invention. Passive integrator 100 can also be referred to as a passive integrator circuit. Passive integrator 100 includes an n-type diode 102, switches 104, 106, and 108, switches 110 and 112, and a charge storage element 114. Switch 104 has a terminal connected to a terminal of n-type diode 102 forming a node 105, a terminal commonly connected to switches 106 and 108 forming a node 107, and a control terminal coupled for receiving a control signal VTGL. Diode 102 has another terminal that is coupled for receiving a source of potential VBIAS. Diode 102 may be referred to as a charge storage element or a storage node element. By way of example, diode 102 is engineered to be fully depleted at a voltage VDEP. Switch 106 further includes a terminal coupled for receiving an input signal VIN and a control terminal coupled for receiving a control signal VSAM and switch 108 further includes a control terminal coupled for receiving a control signal VRST and a terminal coupled for receiving a reset potential VRP.
It should be noted that although diode 102 is shown in schematic form as having two terminals, in a monolithically integrated form the terminals may be comprised of a semiconductor material or a conductor coupled to the semiconductor material. Thus, diode 102 may be monolithically integrated with semiconductor devices such as, for example, transistors that form switches.
Switches 110 and 112 have terminals commonly connected together and to a terminal of charge storage element 114 to form a node 113 at which output signal VOUT appears. In addition, switch 110 has a terminal connected to terminals of switch 104 and diode 102 to form a node 105 and a control terminal coupled for receiving control signal VTGI and switch 112 has a terminal coupled for receiving source of operating potential VDD and a control terminal coupled for receiving control signal VRSC. Charge storage element 114 has a terminal coupled for receiving a source of operating potential VSS. By way of example, source of operating potential VSS is ground potential. Although charge storage element 114 is shown as a capacitor, this is not a limitation of the present invention. For example, charge storage element 114 can be a diode.
FIG. 4 is a circuit schematic of a passive integrator 150 in accordance with another embodiment of the present invention. Passive integrator 150 is similar to passive integrator 100 except that switches 104, 106, 108, 110, and 112 have been replaced by transistors 154, 156, 158, 160, and 162, respectively. Transistors 154-162 may be re-channel field effect transistors, p-channel field effect transistors, junction field effect transistors, bipolar transistors, or the like. Transistors 154, 156, and 158 have current carrying electrodes that are commonly connected together to form a node 152 and gate electrodes coupled for receiving control signals VTGL, VSAM, and VRST, respectively. Transistor 156 has a current carrying electrode 157 coupled for receiving input voltage VIN and transistor 158 has a current carrying electrode coupled for receiving reset potential VRP. Transistors 154 and 160 each have current carrying electrodes commonly connected together and to a terminal of diode 102 to form a node 105A. The other terminal of diode 102 is coupled for receiving source of operating potential VBIAS, which may be equal to voltage VSS. Transistor 160 has a gate or control electrode coupled for receiving a control signal VTGI and another current carrying electrode that is commonly connected to a current carrying electrode of transistor 162 and to a terminal of charge storage element 114 to form an output node 163. Transistor 162 has another current carrying electrode coupled for receiving source of operating potential VDD and a gate or control electrode coupled for receiving control signal VRSC. Like passive integrator 100, the other terminal of charge storage element 114 is coupled for receiving source of operating potential VSS.
FIG. 5 is a timing diagram 170 suitable for describing the operation of passive integrator 100 or passive integrator 150. For the sake of clarity, FIG. 5 will be described with reference to passive integrator 150 shown in FIG. 4, however as stated above it is suitable for use in describing the operation of passive integrator 100. In operation, before the integration phase commences, a reset phase occurs, i.e., diode 102 is reset to a voltage that is lower than the lowest voltage level of input voltage VIN. At time t0 control signals VRSC, VRST, VSAM, VTGL, and VTGI are at logic low voltage levels. By way of example, the reset phase begins in response to control signals VTGL, VRST, and VRSC transitioning from a logic low voltage level (VL) to a logic high voltage level (VH) at time t1, turning on transistors 154, 158, and 162, respectively. Turning on transistors 154 and 158 resets diode 102, i.e., charges it with electrons until its voltage is substantially equal to voltage VRP, which may be referred to as a diode reset voltage level. Turning on transistor 162 resets integration capacitor 114 to a voltage substantially equal to source of operating potential VDD or a voltage that is sufficiently high enough to inhibit charge sharing between integration capacitor 114 and a diode capacitance CDIODE associated with diode 102 after N integration steps, where N is an integer representing the number of expected integration cycles. Briefly referring to FIG. 6, an energy band diagram illustrating the charge stored in diode capacitance CDIODE and the charge stored in integration capacitor 114 between times t1 and t3 is shown. More particularly, the voltage on diode capacitance CDIODE decreases from a voltage substantially equal to voltage VDEP to a voltage substantially equal to voltage VRP. The charge (QRESET) accumulated in diode capacitance CDIODE may be given as (VDEP−VRP)*CDIODE. The voltage on capacitor 114 is substantially equal to voltage VDD.
At time t2, control signals VRST and VRSC transition from logic high voltage levels VH to logic low voltage levels VL whereas control signal VTGL remains at logic high voltage level VH. Thus, transistors 158 and 162 are turned off but transistor 154 remains on. It should be noted that resetting integration capacitor 114 introduces a reset noise signal, Vnreset, commonly referred to as kTC noise, which is given by equation 3 (EQT 3) as:

Vnreset=(k*T/C114)1/2   EQT 3

where
k is Boltzmann's constant;
T is temperature in degrees Kelvin; and
C114 is the capacitance value of integration capacitor 114.
At time t3, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 156, thereby discharging diode 102 until its voltage substantially equals input voltage VIN. Briefly referring to FIG. 7, the voltage across diode 102 is equal to voltage VIN and the charge (QSIGNAL) in the diode capacitance is substantially equal to CDIODE times the difference between voltages VDEP and VIN, where CDIODE is the value of the capacitance of diode 102. Integration capacitor 114 remains charged at a voltage level substantially equal to voltage VDD because transistors 160 and 162 are off. It should be noted that FIG. 7 illustrates the charge on diode 102 and integration capacitor 114 substantially between times t3 and t4.
The charge stored by diode 102 is given by equation (EQT) 4 as:

QSIGNAL=CDIODE*(VDEP−VIN)   EQT 4

At time t4, control signal VTGL transitions to logic low voltage level VL turning off transistor 154 and storing the sampled input voltage signal VIN on capacitance CDIODE of diode 102, i.e., turning off transistor 154 samples an amount of charge corresponding to QSIGNAL from EQT. 4. This introduces a sampling noise, Vnsample, commonly referred to as kTC noise, which is given by equation (EQT 5) as:

Vnsample=(k*T/CDIODE)1/2   EQT 5

where:
k is Boltzmann's constant;
T is temperature in degrees Kelvin; and
CDIODE is the capacitance value of diode 102.
At time t5, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 152.
At time t6, control signal VTGI transitions to logic high voltage level VH beginning the integration phase. The charge stored in diode capacitance CDIODE in response to control signal VTGI transitioning to logic high voltage level VH is transferred via transistor 160 to integration capacitor 114. Thus, output voltage VOUT transitions from a voltage level VDD to a voltage level VINT1. The difference (VΔ) between the voltage levels of voltages VDD and VINT1 is given by equation (EQT) 6 as:

VΔ=(CDIODE/C114)*(VDEP−VIN)   EQT 6

Because the charge in diode capacitance CDIODE is substantially completely transferred, diode 102 is fully depleted and therefore a noise signal is not introduced into the charge stored in integration capacitor 114. At time t7, control signal VTGI transitions to a logic low voltage level substantially concluding the integration phase. The voltage change on capacitor 114 serves as an integrated signal. Briefly referring to FIG. 8, the voltage across capacitor 114 decreases from a voltage level substantially equal to voltage VDD to a voltage level VINT1. It should be noted that FIG. 8 illustrates the charge on diode 102 and integration capacitor 114 substantially between times t6 and t8. It should be further noted that the charge stored in diode capacitance CDIODE is transferred to integration capacitor 114 and that the charge (QINT1) stored in integration capacitor 114 is substantially equal to C114 times the difference between voltages VDD and VINT1.
Control voltages VTGL and VRST transition from logic low voltage level VL to logic high voltage level VH turning on transistors 154 and 158, respectively, at time t8. Turning on transistors 154 and 158 resets diode capacitance CDIODE. Briefly referring to FIG. 9, an energy band diagram illustrating the charge stored in diode capacitance CDIODE and the charge stored in integration capacitor 114 is shown. As discussed with reference to FIG. 6, the voltage on diode capacitance CDIODE decreases from a voltage substantially equal to voltage VDEP to a voltage substantially equal to voltage VRP. The charge (QRESET) accumulated in diode capacitance CDIODE may be given as (VDEP−VRP)*CDIODE. The voltage stored on integration capacitor 114 remains substantially equal to voltage VINT1 because transistors 160 and 162 are off. It should be noted that FIG. 9 illustrates the charge on diode 102 and integration capacitor 114 substantially between times t8 and t10.
At time t9, control signal VRST transitions from logic high voltage level VH to logic low voltage level VL whereas control signal VTGL remains at a logic high voltage level VH. Thus, transistor 158 is turned off but transistor 154 remains on.
At time t10, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 156 to discharge diode 102 until its voltage substantially equals input voltage VIN. Briefly referring to FIG. 10, capacitor 114 remains charged at a voltage level substantially equal to voltage VINT1 because transistors 160 and 162 are off. As discussed with reference to FIG. 7, the voltage across diode 102 is equal to voltage VIN and the charge (QSIGNAL) in the diode capacitance is substantially equal to CDIODE times the difference between voltages VDEP and VIN, where CDIODE is the value of the capacitance of diode 102. It should be noted that FIG. 10 illustrates the charge on diode 102 and integration capacitor 114 substantially between times t10 and t13.
At time t11, control signal VTGL transitions to logic low voltage level VL turning off transistor 154 and storing the sampled input voltage signal VIN across diode capacitance CDIODE, introducing a noise component described by EQT 5.
At time t12, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 152.
At time t13, control signal VTGI transitions to a logic high voltage level VH beginning another integration phase. Thus, output voltage VOUT transitions from voltage level VINT1 to a voltage level VINT2. The difference (VΔ) between the voltage levels of voltages VINT1 and VINT2 is given by EQT 5. As discussed above, the charge in diode 102 is substantially completely transferred, thus diode 102 is fully depleted and therefore a noise signal is not introduced into the charge stored in integration capacitor 114. At time t14, control signal VTGI transitions to logic low voltage level VL substantially concluding the integration phase. The voltage change on capacitor 114 serves as an integrated signal. It should be noted that in this portion of the integration process FIG. 11 illustrates the charge on diode 102 and integration capacitor 114 substantially between times t13 and t14. Briefly referring to FIG. 11, which illustrates the charge on diode 102 and integration capacitor 114 substantially between times t13 and t14, the voltage across capacitor 114 decreases from a voltage level substantially equal to voltage VINT1 to a voltage level VINT2. It should be noted that the charge stored in diode capacitance CDIODE is transferred to integration capacitor 114 and that the charge (QINT2) stored in integration capacitor 114 is substantially equal to C114 times the difference between voltages VDD and VINT2.
Although two integration steps have been shown and described, this is not a limitation of the present invention. There can be more than two integration steps or fewer than two integration steps.
It should be noted that the description of the operation of passive integrator 100 is similar to that of passive integrator 150, wherein control signals VRSC, VRST, VSAM, VTGL, and VTGI open and close switches 112, 108, 106, 104, 110, respectively. Turning on a transistor is operationally similar to closing a switch and turning off a transistor is operationally similar to opening a switch.
FIG. 12 is a circuit schematic of a passive integrator 200 in accordance with another embodiment of the present invention. Passive integrator 200 can also be referred to as a passive integrator circuit. Passive integrator 200 includes a p-type diode 202, switches 204, 206, and 208, switches 210 and 212, and a charge storage element 214. Switch 204 has a terminal connected to a terminal of diode 202 forming a node 205, a terminal commonly connected to switches 206 and 208 forming a node 207, and a control terminal coupled for receiving a control signal VTGL. Diode 202 has another terminal that is coupled for receiving a source of potential VBIAS. By way of example, diode 202 may be engineered to be fully depleted at a voltage (VBIAS−VDEP). Switch 206 further includes a terminal coupled for receiving an input signal VIN and a control terminal coupled for receiving a control signal VSAM and switch 208 further includes a control terminal coupled for receiving a control signal VRST and a terminal coupled for receiving an operating potential VDD. It should be noted that voltage VBIAS can be the bulk potential VDD.
It should be noted that although diode 202 is shown in schematic form as having two terminals, in a monolithically integrated form, the terminals may be comprised of a semiconductor material or a conductor coupled to the semiconductor material. Thus, diode 202 may be monolithically integrated with semiconductor devices such as, for example, transistors that form switches. In addition, diode 202 may be referred to as a charge storage element or a storage node element.
Switches 210 and 212 have terminals commonly connected together and to a terminal of charge storage element 214. In addition, switch 210 has a terminal connected to node 205 and a control terminal coupled for receiving control signal VTGI and switch 212 has a terminal coupled for receiving source of operating potential VSS and a control terminal coupled for receiving control signal VRSC. Charge storage element 214 has a terminal coupled for receiving source of operating potential VSS. Although charge storage element 214 is shown as being a capacitor, this is not a limitation of the present invention. For example, charge storage element 214 can be a diode.
FIG. 13 is a circuit schematic of a passive integrator 250 in accordance with another embodiment of the present invention. Passive integrator 250 is similar to passive integrator 200 except that switches 204, 206, 208, 210, and 212 have been replaced by transistors 254, 256, 258, 260, and 262, respectively. By way of example, transistors 254, 256, 258, 260, and 262 are p-channel transistors. However, it should be understood that transistors 254-262 may be other types of semiconductor devices. Transistors 254, 256, and 258 each have a current carrying electrode commonly connected together to form a node 252 and gate electrodes coupled for receiving control signals VTGL, VSAM, and VRST, respectively. Transistor 256 has a current carrying electrode coupled for receiving input voltage VIN and transistor 258 has a current carrying electrode coupled for receiving source of operating potential VDD. Transistors 254 and 260 each have current carrying electrodes commonly connected together and to a terminal of diode 202 to form a node 205A. Diode 202 has another terminal coupled for receiving a source of potential VBIAS, which can be equal to voltage VDD. Transistor 260 has another current carrying electrode that is commonly connected to a current carrying electrode of transistor 262 and to a terminal of charge storage element 214 to form an output node 263. Transistor 262 has another current carrying electrode coupled for receiving source of operating potential VSS and a gate electrode coupled for receiving control signal VRSC. Like passive integrator 200, the other terminal of charge storage element 214 is coupled for receiving source of operating potential VSS.
FIG. 14 is a timing diagram 270 suitable for describing the operation of passive integrator 250 and passive integrator 200. For the sake of clarity, FIG. 14 will be described with reference to passive integrator 250 shown in FIG. 13. In operation, before the integration phase commences, a reset phase occurs, i.e., diode 202 is reset to a voltage that is higher than the highest voltage level of input voltage VINT, and has a default value substantially equal to voltage VDD. At time t0 control signals VRSC, VRST, VSAM, VTGL, and VTGI are at logic low voltage levels. By way of example, the reset phase begins in response to control signals VTGL, VRST, and VRSC transitioning from a logic low voltage level VL to a logic high voltage level VH at time t1, turning on transistors 254, 258, and 262, respectively. Turning on transistors 254 and 258 resets diode 202, i.e., charges it with holes until its voltage substantially equals VDD. Turning on transistor 262 resets integration capacitor 214 to a voltage substantially equal to source of operating potential VSS. Briefly referring to FIG. 15, an energy band diagram illustrating the charge stored in diode capacitance CDIODE and the charge stored in integration capacitor 214 between times t1 and t3 is shown. More particularly, the voltage on diode capacitance CDIODE increased from a voltage substantially equal to voltage VDD−VDEP to a voltage substantially equal to voltage VDD. The voltage on capacitor 214 is substantially equal to voltage VSS. The charge in capacitor C214 may be given as VSS*C214, where C214 is the capacitance associated with capacitor 214.
At time t2, control signals VRST and VRSC transition from logic high voltage levels VH to logic low voltage levels VL whereas control signal VTGL remains at logic high voltage level VH. Thus, transistors 258 and 262 are turned off but transistor 254 remains on. It should be noted that resetting integration capacitor 214 introduces a reset noise signal, Vnreset, commonly referred to as kTC noise, which is given by EQT 3.
At time t3, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 256, thereby discharging holes from diode 202 until its voltage substantially equals input voltage VIN. Briefly referring to FIG. 16, the voltage across diode 202 will be forced on current carrying electrode 257 leaving a positive charge residue in diode capacitance CDIODE substantially equal to CDIODE times the difference given by VIN−(VDD−VDEP), where CDIODE is the value of the capacitance of diode 202. Integration capacitor 214 remains charged at a voltage level substantially equal to voltage VSS because transistors 260 and 262 are off. The charge stored by diode 202 is given by equation 4. Briefly referring to FIG. 16, the voltage on diode 202 is equal to voltage VIN and the charge (QSIGNAL) in the diode capacitance is substantially equal to CDIODE times the difference between voltages VDD and VIN, where CDIODE is the value of the capacitance of diode 202. Integration capacitor 114 remains charged at a voltage level substantially equal to voltage VSS because transistors 260 and 262 are off. It should be noted that FIG. 16 illustrates the charge on diode 202 and integration capacitor 214 substantially between times t3 and t4.
At time t4, control signal VTGL transitions to logic low voltage level VL turning off transistor 254, storing charge resulting from the sampling input voltage signal VIN on capacitance CDIODE of diode 202 and introducing a kTC noise given by EQT 5.
At time t5, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 252.
At time t6, control signal VTGI transitions to logic high voltage level VH beginning the integration phase. The charge stored in diode capacitance CDIODE in response to control signal VTGI transitioning to logic high voltage level VH is transferred via transistor 260 to integration capacitor 214. Thus, output voltage VOUT transitions from a voltage level VSS to a voltage level VINT1. The difference (VΔ) between the voltage levels of voltages VSS and VINT1 is given by equation (EQT) 6 as:

VΔ=(CDIODE/C214)*(VIN−(VDD−VDEP))   EQT 6

Because the charge in diode capacitance CDIODE is substantially completely transferred, diode 202 is fully depleted and therefore a noise signal is not introduced during the integration phase. The voltage as a result of the charge stored in capacitor 214 serves as an integrated signal. At time t7, control signal VTGI transitions to a logic low voltage level substantially concluding the integration phase. Briefly referring to FIG. 17, the charge stored in capacitor 214 increases from a voltage level substantially equal to voltage VSS to a voltage level VINT1 and the charge in the diode capacitance CDIODE is substantially completely transferred leaving diode capacitance CDIODE fully depleted. It should be noted in this portion of the integration process FIG. 17 illustrates the charge on diode 202 and integration capacitor 214 substantially between times t6 and t8.
Control voltages VTGL and VRST transition from logic low voltage level VL to logic high voltage level VH turning on transistors 254 and 258, respectively, at time t8. Turning on transistors 254 and 258 resets diode capacitance CDIODE to voltage VDD. Briefly referring to FIG. 18, an energy band diagram illustrating the charge stored in diode capacitance CDIODE and the charge stored in integration capacitor 214 is shown between times t8 and t10. The voltage stored across integration capacitor 214 remains substantially equal to voltage VINT1 because transistors 260 and 262 are off. As described with reference to FIG. 15, the voltage on diode capacitance CDIODE increases from a voltage substantially equal to voltage VDD−VDEP to a voltage substantially equal to voltage VDD.
At time t9, control signal VRST transitions from logic high voltage level VH to logic low voltage level VL whereas control signal VTGL remains at a logic high voltage level VH. Thus, transistor 258 is turned off but transistor 254 remains on.
At time t10, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 256 to sample input voltage signal VIN. Briefly referring to FIG. 19, integration capacitor 214 remains charged at a voltage level substantially equal to voltage VINT1 because transistors 260 and 262 are off. As discussed with reference to FIG. 16, the voltage on diode 202 is equal to voltage VIN and the charge (QSIGNAL) in the diode capacitance is substantially equal to CDIODE times the difference between voltages VIN, VDD , and VDEP, where CDIODE is the value of the capacitance of diode 202, i.e., QSIGNAL=(VIN−(VDD−VDEP))*CDIODE. It should be noted that in this portion of the integration process FIG. 19 illustrates the charge on diode 202 and integration capacitor 214 substantially between times t10 and t13.
At time t11, control signal VTGL transitions to logic low voltage level VL turning off transistor 254, storing the sampled input voltage signal VIN across diode capacitance CDIODE, and introducing a kTC noise given by EQT 5.
At time t12, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 252.
At time t13, control signal VTGI transitions to a logic high voltage level VH beginning another integration phase. Thus, output voltage VOUT transitions from voltage level VINT1 to a voltage level VINT2. The difference (VΔ) between the voltage levels of voltages VINT1 and VINT2 is given by EQT 6. As discussed above, the charge in diode 202 is substantially completely transferred, thus diode 202 is fully depleted and therefore a noise signal is not introduced into the charge stored in integration capacitor 214. At time t14, control signal VTGI transitions to logic low voltage level VL substantially concluding the integration phase. The charge stored in capacitor 214 serves as an integrated signal.
Briefly referring to FIG. 20, the charge stored in integration capacitor 214 increases from a voltage level substantially equal to voltage VINT1 to a voltage level VINT2 and the charge in diode capacitance CDIODE is substantially completely transferred leaving diode capacitance CDIODE fully depleted. It should be noted that in this portion of the integration process FIG. 20 illustrates the charge on diode 202 and integration capacitor 214 substantially between times t13 and t15.
Although two integration steps have been shown and described, this is not a limitation of the present invention. There can be more than two integration steps or fewer than two integration steps.
It should be noted that the description of the operation of passive integrator 200 is similar to that of passive integrator 250, wherein control signals VRSC, VRST, VSAM, VTGL, and VTGI open and close switches 212, 208, 206, 204, 210, respectively. As discussed above, turning on a transistor is operationally similar to closing a switch and turning off a transistor is operationally similar to opening a switch.
FIG. 21 is a circuit schematic of a passive integrator 300 coupled to a voltage source such as, for example, a portion of a pixel 316 in accordance with an embodiment of the present invention. Passive integrator 300 can also be referred to as a passive integrator circuit. Passive integrator 300 includes a diode 302, transistors 304, 306, 308, 310, and 312. Transistor 304 has a terminal connected to a terminal of diode 302 to form a node 305, a terminal commonly connected to transistors 306 and 308 to form a node 314, and a control terminal coupled for receiving a control signal VTGL. Diode 302 has a terminal coupled for receiving a source of potential VBIAS. By way of example, diode 302 may be engineered to be fully depleted at a voltage VDEP. Transistor 306 further includes a terminal coupled for receiving a signal from a pixel 316 and a control terminal coupled for receiving a control signal VSAM and transistor 308 further includes a control terminal coupled for receiving a control signal VPC and a terminal coupled for receiving a reset potential VRP.
It should be noted that although diode 302 is shown in schematic form as having two terminals, in a monolithically integrated form the terminals may be comprised of a semiconductor material or a conductor coupled to the semiconductor material. Thus, diode 302 may be monolithically integrated with semiconductor devices such as, for example, transistors that form switches. In addition, diode 302 may be referred to as a charge storage element or a storage node element.
Transistors 304 and 310 each have current carrying electrodes commonly connected together and to a terminal of diode 302 at node 305. Transistor 310 has another current carrying electrode that is commonly connected to a current carrying electrode of transistor 312 and to terminals of switches 320 and 322. Transistor 312 has another current carrying electrode coupled for receiving source of operating potential VDD and a gate electrode coupled for receiving control signal VRSC. An integration capacitor 324 is coupled between switch 320 and source of operating potential VSS and another integration capacitor 326 is coupled between switch 322 and source of operating potential VSS. Switch 320 has a control terminal coupled for receiving a control signal VSHR and switch 322 has a control terminal coupled for receiving a control signal VSHS.
Transistors 304-312 may be n-channel field effect transistors, p-channel field effect transistors, junction field effect transistors, bipolar transistors, or the like.
It should be noted that a portion of pixel 316 is illustrated in FIG. 21. As those skilled in the art are aware, pixels can have many architectures. For example, the pixel may be a 3T pixel, a 4T pixel, a 5T pixel, etc. Typically, a pixel includes a transistor 330 configured as a source follower, wherein a source of transistor 330 is coupled to a column line 332 through a select switch 334, which may be a transistor.
FIG. 22 is a timing diagram 370 suitable for describing the operation of passive integrator 300. In operation, before a first integration step commences, passive integrator 300 is reset. At time t0 control signals VRSC, VSAM, VPC, VTGL, VTGI, VSHS, and VSHR are at logic low voltage levels. Control signals VRSC and VSHR transition from logic low voltage level VL to logic high voltage level VH turning on transistor 312 and closing switch 320, respectively, at time t1, which charges integration capacitor 324 to a voltage substantially equal to source of operating potential VDD. It should be noted that resetting integration capacitor 324 introduces a reset noise signal, Vnreset, commonly referred to as kTC noise, which is given by EQT. 3, with the modification that the capacitance value of capacitor 114 is replaced with the capacitance value of capacitor 324.
At time t2, control signal VRSC transitions from logic high voltage level VH to logic low voltage level VL while control signal VSHR remains at logic high voltage level VH. Thus, transistor 312 is turned off and switch 320 remains closed.
At time t3, control signals VPC and VTGL transition from logic low voltage level VL to logic high voltage level VH turning on transistors 304 and 308 to reset diode 302 to voltage VRP. Integration capacitor 324 remains charged at a voltage level substantially equal to voltage VDD because transistor 312 is off and switch 320 is closed.
At time t4, control signal VPC transitions to logic low voltage level VL turning off transistor 308.
At time t5, control signal VSAM transitions to logic high voltage level VH, connecting the column line output of pixel 316 via node 314 to discharge diode 302 until its voltage substantially equals voltage VIN.
At time t6, control signal VTGL transitions to logic low voltage level VL disconnecting node 314 from diode 302 and sampling the input value on diode 302. This introduces a sampling noise signal which is given by EQT 5.
At time t7, control signal VSAM transitions to logic low voltage level VL disconnecting pixel 316 from node 314.
At time t8, control signal VTGI transitions to logic high voltage level VH beginning the integration phase. Thus, output voltage VOUT transitions from a voltage level VDD to a voltage level VR_INT1. At time t9, control signal VTGI transitions to logic low voltage level VL substantially concluding the integration phase. The voltage across integration capacitor 324 decreases to a voltage level VINT1 and the charge from diode 302 is substantially completely transferred to integration capacitor 324. This integration phase is substantially noiseless as described with reference to the integration phases illustrated in FIG. 14, i.e., the description at times t6 to t7 and times t13 to t14.
Control voltages VTGL and VPC transition from logic low voltage level VL to logic high voltage level VH turning on transistors 304 and 308, respectively, at time t10. Turning on transistors 304 and 308 resets diode 302. The voltage stored across capacitor 324 remains substantially equal to voltage VINT1 because transistors 310 and 312 are off.
At time t11, control signal VPC transitions from logic high voltage level VH to logic low voltage level VL while control signal VTGL remains at logic high voltage level VH. Thus, transistor 308 is turned off whereas transistor 304 remains on.
At time t12, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 306 to sample the signal from pixel 316, i.e., input voltage signal VIN is transferred to diode 302, which discharges diode capacitance CDIODE to a voltage substantially equal to voltage VIN. Integration capacitor 324 remains charged at a voltage level substantially equal to voltage VINT1 because transistors 310 and 312 are off.
At time t13, control signal VTGL transitions to logic low voltage level VL turning off transistor 304 and storing the sampled input voltage signal VIN on diode capacitance CDIODE.
At time t14, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 314.
At time t15, control signal VTGI transitions to logic high voltage level VH beginning another integration phase. Thus, output voltage VOUT transitions from voltage level VR_INT1 to a voltage level VR_INT2. At time t16, control signal VTGI transitions to logic low voltage level VL substantially concluding the integration phase.
At time t17, control signal VSHR transitions of logic low voltage level VL causing switch 320 to open and sample the integrated pixel reset value on capacitor 324. The pixel reset value is sampled first because the pixel noise may be cancelled by applying a correlated double sampling which consists of sampling the reset value, sampling the signal value and afterwards performing a subtraction, which can be performed externally or by on-chip logic circuitry. It should be noted that the kTC noise and other offsets may be cancelled by this subtraction because the reset and signal from the pixel have substantially the same offset. At time t18 the pixel signal voltage at column 332 transitions from voltage level VR to voltage level VS. This is the pixel signal voltage.
Control signal VSHS transitions from logic low voltage level VL to logic high voltage level VH closing switch 322 at time t19 and at time t20, control signal VRSC transitions from logic low voltage level VL to logic high voltage level VH while control signal VSHS remains at logic high voltage level VH. Thus, transistor 312 is turned on whereas switch 320 remains closed. This resets integration capacitor 326 to voltage VDD. It should be noted that resetting integration capacitor 326 introduces a reset noise signal Vnreset, commonly referred to as kTC noise, which is given by EQT. 3, with the modification that the capacitance value of capacitor 114 is replaced with the capacitance value of capacitor 324.
At time t21, control signal VRSC transitions from logic high voltage level VH to logic low voltage level VL while control signal VSHS remains at logic high voltage level VH. Thus, transistor 312 is turned off whereas switch 320 remains closed.
At time t22, control signals VPC and VTGL transition from logic low voltage level VL to logic high voltage level VH turning on transistor 306 to precharge column 332 and reset diode 302 to substantially voltage VSS. Integration capacitor 326 remains charged at a voltage level substantially equal to voltage VDD because transistor 312 is off and switch 322 is closed.
At time t23, control signal VPC transitions to logic low voltage level VL turning off transistor 308.
At time t24, control signal VSAM transitions to logic high voltage level VH connecting pixel 316, i.e., input voltage VIN, via node 324 to discharge diode 302 until its voltage substantially equals voltage VIN.
At time t25, control signal VTGL transitions to logic low voltage level VL sampling voltage VIN on diode 302. At time t26, control signal VSAM transitions to logic low voltage level VL disconnecting pixel output 332 from node 314.
At time t27, control signal VTGI transitions to logic high voltage level VH beginning the signal integration phase. The voltage on integration capacitor 326 decreases to a voltage level VS_INT1.
At time t28, control signal VTGI transitions to logic low voltage level VL completing the signal integration phase.
At time t29, control voltages VTGL and VPC transition from logic low voltage level VL to logic high voltage level VH turning on transistors 304 and 308, respectively. Turning on transistors 304 and 308 resets diode 302. The voltage stored across integration capacitor 326 remains substantially equal to voltage VSINT1 because transistors 310 and 312 are off.
At time t30, control signal VPC transitions from logic high voltage level VH to logic low voltage level VL while control signal VTGL remains at logic high voltage level VH. Thus, transistor 308 is turned off whereas transistor 304 remains on.
At time t31, control signal VSAM transitions from logic low voltage level VL to logic high voltage level VH turning on transistor 306 to discharge diode 302 until its voltage is substantially equal to voltage VIN. Integration capacitor 326 remains charged at a voltage level substantially equal to voltage VSINT1 because transistors 310 and 312 are off.
At time t32, control signal VTGL transitions to logic low voltage level VL turning off transistor 304 and effectively sampling input voltage VIN on diode 302.
At time t33, control signal VSAM transitions to logic low voltage level VL, disconnecting input voltage signal VIN from node 314.
At time t34, control signal VTGI transitions to logic high voltage level VH beginning another integration phase. Thus, output voltage VOUT transitions from voltage level VSINT1 to a voltage level VSINT2. The charge stored in diode 302 is substantially completely transferred making the transfer substantially noiseless and leaving diode 302 in a fully depleted state. At time t35, control signal VTGI transitions to logic low voltage level VL substantially concluding the integration phase.
At time t36, control signal VSHS transitions to logic low voltage level VL causing switch 322 to open effectively sampling the integrated pixel signal value on capacitor 326.
It should be noted that passive integrators in accordance with embodiments of the present invention are not limited to passive integrators used in image sensor circuits. For example, it can be a building block for analog-to-digital converters, gain stages, etc.
Although two integration steps have been shown and described, this is not a limitation of the present invention. There can be more than two integration steps or fewer than two integration steps.
By now it should be appreciated that a passive integrator and method have been provided. In accordance with embodiments, the passive integrator includes two charge storage elements connected to each other via a transistor. In accordance with embodiments in which one charge storage element is a diode and the other charge storage element is a capacitor, the diode and capacitor are reset to predetermined voltage levels, i.e., a predetermined amount of charge is stored in the diode and a predetermined amount of opposite charge is stored in the capacitor. An input signal is sampled on the diode capacitance resulting in a charge residue stored in the diode. The charge residue stored in the diode is transferred to the capacitor to generate an integrated signal in the voltage domain. Resetting the diode, sampling the input voltage, and transferring the charge residue can be repeated N times, where N is the number of integration steps.
Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, the present invention is not limited to embodiments including pixels. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.

## Claims

1. A passive integrator comprising:
a first switch having a control terminal and first and second terminals, the first terminal coupled for receiving a first source of potential;
a first diode that fully depletes of charge at an operating voltage, the first diode having a first terminal directly coupled to the second terminal of the first switch;
a second switch having a control terminal and first and second terminals, the first terminal of the second switch directly coupled to the first terminal of the first diode and to the second terminal of the first switch; and
a second charge storage element having first and second terminals, the first terminal of the second charge storage element coupled to the second terminal of the second switch; and
a third switch having a control terminal and first and second terminals, the first terminal coupled for receiving a first source of operating potential and the second terminal commonly coupled to the first terminal of the second charge storage element and to the second terminal of the second switch.

2. The passive integrator of claim 1, wherein the first diode is an n-type diode.

3. The passive integrator of claim 1, wherein the first diode is a p-type diode.

4. The passive integrator of claim 1, wherein the second charge storage element is a capacitor.

5. The passive integrator of claim 1, further comprising a fourth switch having a control terminal and first and second terminals, the first terminal coupled to the second terminal of the third switch.

6. The passive integrator of claim 5, further comprising a fifth switch having a control terminal and first and second terminals, the first terminal of the fifth switch coupled to the first terminal of the second charge storage element.

7. A method for integrating a signal, comprising:
resetting first and second charge storage elements, wherein resetting the first charge storage element comprises applying a first potential to the first charge storage element and resetting the second charge storage element comprises applying a second potential to the second charge storage element; and wherein applying the second potential to the second charge storage element includes turning on a transistor, wherein the transistor has a control electrode and first and second current carrying electrodes, the first current carrying electrode coupled to the second charge storage element and the second current carrying electrode coupled for receiving a first source of operating potential; and
one of turning off another transistor or leaving the another transistor off, wherein the another transistor has a control electrode, a first current carrying electrode coupled to the first charge storage element, and a second current carrying electrode coupled to the second charge storage element;
storing charge in the first charge storage element in response to a sampled input signal; and
generating an integrated signal in the second charge storage element.

8. The method of claim 7, wherein applying the first potential to the first charge storage element includes turning on first and second transistors, wherein:
the first transistor has a control electrode and first and second current carrying electrodes, the first current carrying electrode coupled to the first charge storage element; and
the second transistor has a control electrode and first and second current carrying electrodes, the first current carrying electrode of the second transistor coupled to the second current carrying electrode of the first transistor and the second current carrying electrode of the second transistor coupled for receiving a first source of potential.

9. The method of claim 8, wherein resetting the second charge storage element comprises applying a second potential to the second charge storage element.

10. The method of claim 8, wherein storing charge in the first charge storage element in response to a sampled input signal includes turning off the second transistor and turning on a fifth transistor, wherein the fifth transistor has a control terminal, a first current carrying terminal coupled for receiving an input signal, and the second current carrying electrode is coupled to the second current carrying electrode of the first transistor.

11. The method of claim 10, wherein generating the integrated signal in the second charge storage element includes turning off the first and fifth transistors and turning on the fourth transistor.

12. The method of claim 7, wherein resetting first and second charge storage elements comprises resetting a diode and a capacitor, respectively.

13. A method for integrating a signal, comprising:
resetting a first charge storage element in response to applying a first potential to the first charge storage element, wherein applying the first potential to the first charge storage element includes turning on first and second transistors, and wherein:
the first transistor has a control electrode and first and second current carrying electrodes, the first current carrying electrode coupled to the first charge storage element; and
the second transistor has a control electrode and first and second current carrying electrodes, the first current carrying electrode of the second transistor coupled to the second current carrying electrode of the first transistor and the second current carrying electrode of the second transistor coupled for receiving a first source of potential;

generating an integrated signal in the second charge storage element includes turning off the first and third transistors and turning on a fourth transistor, wherein the fourth transistor has a control electrode, a first current carrying electrode coupled to the first charge storage element, and a second current carrying electrode coupled to the second charge storage element.

14. The passive integrator of claim 6, wherein
the first switch comprises a first transistor having a control electrode and first and second current carrying electrodes;
the second switch comprises a second transistor having a control electrode and first and second current carrying electrodes;
the third switch comprises a third transistor having a control electrode and first and second current carrying electrodes;
the fourth switch comprises a fourth transistor having a control electrode and first and second current carrying electrodes; and
the fifth switch comprises a fifth transistor having a control electrode and first and second current carrying electrodes.

15. The method of claim 13, wherein storing charge in the first charge storage element in response to the sampled input signal includes turning off the second transistor and turning on a third transistor, wherein the third transistor has a control electrode, a first current carrying electrode coupled for receiving the input signal, and a second current carrying electrode coupled to the second current carrying electrode of the first transistor.

16. The method of claim 13, wherein resetting the first charge storage element comprises resetting a diode.

17. The method of claim 16, wherein generating an integrated signal in the second charge storage element includes generating the integrated signal in a capacitor.