# Patent

## Title
Circuitry for generating non-overlapping pulse trains

## Abstract

A gate circuit for gate turn-off thyristors is disclosed which includes a turn-on circuit formed of a series combination of a turn-on power source and an NPN transistor and a turn-off circuit formed of a series combination of a turn-off power source and a thyristor, and in which a PNP transistor is provided between the anode and gate of the thyristor in such a manner that the base of the NPN transistor and the base of the PNP transistor are connected to each other and a junction of these bases receives a control signal for turning on or off a gate turn-off thyristor.

## Background
The present invention relates to a gate circuit for a gate turn-off thyristor (hereinafter referred to as a "GTO"), and more particularly to a gate circuit in which power loss is extremely low.

Various gate circuits for GTO's have been published. A typical one of these gate circuits includes a turn-on circuit and a turn-off circuit each connected between the gate and cathode of a GTO. The turn-on circuit is formed of a series combination of a turn-on power source (namely, a power source for turning on the GTO) and a transistor, and the turn-off circuit is formed of a series combination of a turn-off power source (namely, a power source for turning off the GTO) and another transistor. When the GTO is turned on, the transistor in the turn-on circuit is made conductive, and the transistor in the turn-off circuit is made nonconductive. On the other hand, when the GTO is turned off, the transistor in the turn-on circuit is made nonconductive and the transistor in the turn-off circuit is made conductive.

Such a gate circuit causes no trouble when the anode current of the GTO is small. However, when the anode current of the GTO becomes large, it is required to cause a fairly large current to flow in order to turn off the GTO, since the turn-off gain of the GTO is small, that is, has a value of 3 to 5. Accordingly, the transistor in the turn-off current is required to have a large current capacity. A transistor having a large current capacity is expensive, and a gate circuit including such a transistor is uneconomical.

In order to solve this problem, for example, the following circuit arrangement is disclosed in U.S. Pat. No. 4,117,350, issued on Sept. 26, 1978. That is, the transistor in the turn-off circuit and a thyristor are connected in parallel, so that a major portion of an initial peak gate current flows through this thyristor and a predetermined limited portion of the gate current flows through the transistor in the turn-off circuit. By using such a circuit arrangement, the turn-off circuit can be formed of a transistor and a thyristor which are relatively inexpensive, and therefore an economical gate circuit can be formed.

Methods of supplying a turn-on signal and a turn-off signal to such a gate circuit have been provided. For example, one of the methods is disclosed in U.S. Pat. No. 4,115,707, issued Sept. 19, 1978. In this method, a turn-on signal is outputted from a control signal source, and a turn-off signal is formed by a one-shot circuit which is operated in response to the stoppage of the turn-on signal. However, in order to reduce power loss in the gate circuit, it is required to make a further appropriate improvement in the gate circuit.

An object of the present invention is to provide a gate circuit in which power loss is low. In order to attain the object, a gate circuit according to the present invention includes two concrete means, one of which is to use a thyristor as a main switching element in a turn-off circuit, to connect anode and gate terminals of the thyristor to emitter and collector terminals of a PNP transistor, respectively, and to connect a base terminal of the PNP transistor to a base terminal of an NPN transistor in a turn-on circuit. By using such a circuit arrangement, it is not required that a circuit for firing the above-mentioned thyristor includes a conventional differentiating circuit made up of a resistor and a capacitor, and further it is not required to use the one-shot circuit disclosed in the previously-referred U.S. patent. In other words, according to the present invention, power loss in the differentiating circuit and one-shot circuit can be avoided.

The other concrete means is to connect a diode between the base terminal of the NPN transistor in the turn-on circuit and an anode terminal of a GTO in such a manner that the forward direction of the diode is toward the anode terminal of the GTO. According to such a circuit arrangement, after the GTO has been turned on, a turn-on current flows into the anode side of the GTO through the diode, and the NPN transistor becomes nonconductive. Accordingly, a gate-on current for the GTO is stopped after a minimum period required, and thus a turn-on circuit which is low in power loss as compared with conventional turn-on circuits, can be obtained.

Further, the present invention including the above-mentioned concrete means has an advantage that a gate circuit can be made small in size and low in cost, and other advantages.

FIG. 1a is a circuit diagram showing an embodiment of the present invention.

FIG. 1b is a waveform chart showing the states of operation in various parts of the embodiment shown in FIG. 1a.

FIG. 2a is a circuit diagram showing another embodiment of the present invention.

FIG. 2b is a waveform chart showing voltage waveforms and current waveforms in various parts of the embodiment shown in FIG. 2a.

Referring to FIG. 1a, a GTO has an anode terminal A, a cathode terminal K and a gate terminal G, and a turn-on circuit and a turn-off circuit are connected between the gate terminal G and cathode terminal K of the GTO. The turn-on circuit is formed of a series combination of a turn-on power source C.sub.1, a resistor R.sub.10 and an NPN transistor Q.sub.3 (which can be formed as two transistors in a Darlington connection as shown in FIG. 1a), and the turn-off circuit is formed in such a manner that a series combination of an inductor L.sub.1 and a thyristor Th.sub.1 is connected in parallel with a series combination of a PNP transistor Q.sub.4 and resistors R.sub.5 and R.sub.12, and the parallel combination thus obtained is connected in series with a turn-off power source C.sub.2. Each of the power sources C.sub.1 and C.sub.2 has an earth electrode to be grounded, and the power sources C.sub.1 and C.sub.2 charge up to voltage levels +E and -E, respectively. Needless to say, the negative electrode of the power source C.sub.1 and the positive electrode of the power source C.sub.2 may be connected directly to the cathode terminal of the GTO without being grounded. Further, between the positive electrode of the power source C.sub.1 and the negative electrode of the power source C.sub.2 are connected a series combination of a resistor R.sub.2, a phototransistor of a photo-coupler PC.sub.1 and a resistor R.sub.3, a series combination of a resistor R.sub.4 and a transistor Q.sub.1, and a series combination of a resistor R.sub.8 and a transistor Q.sub.2. A control signal i.sub.F is supplied to a photodiode of the photo-coupler PC.sub.1 through a resistor R.sub.1. Further, the resistor R.sub.3 and a capacitor C.sub.3 are connected in parallel, and a junction of the phototransistor of the photo-coupler PC.sub.1 and the resistor R.sub.3 is connected to a base terminal of the transistor Q.sub.1. A series combination of resistors R.sub.6 and R.sub.7 is connected between the collector and emitter of the transistor Q.sub.1, and a junction of the resistors R.sub.6 and R.sub.7 is connected to a base terminal of the transistor Q.sub.2. A junction S of the resistor 8 and a collector terminal of the transistor Q.sub.2 is connected to path of a base terminal of the NPN transistor Q.sub.3 (namely, the Darlington connection) and a base terminal of the PNP transistor Q.sub.4 through a resistor R.sub.9 and a zener diode ZD.sub.2. In principle, the junction S may be considered a control signal input terminal. Further, a diode D.sub.4 is connected between the anode terminal A of the GTO and a junction of the resistor R.sub.9 and the zener diode ZD.sub.2 in such a manner that the forward direction of the diode D.sub.4 is toward the anode terminal A. The gate terminal G of the GTO is grounded (as indicated by reference symbol G.sub.nd) through a resistor R.sub.13.

The operation of the circuit shown in FIG. 1a is as follows. In the case where the GTO is turned on, the control signal i.sub.F taking a high level is supplied to the photodiode of the photo-coupler PC.sub.1 at a time t.sub.1 shown in FIG. 1b. Then, the photo-transistor of the photo-coupler PC.sub.1 becomes conductive, and a current flows into the base of the transistor Q.sub.1 through a path C.sub.1 -R.sub.2 -PC.sub.1 -Q.sub.1. Thus, the transistor Q.sub.1 becomes conductive, and the transistor Q.sub.2 is made nonconductive. Accordingly, a current flows into the base of the transistor Q.sub.3 through a path C.sub.1 -R.sub.8 -R.sub.9 -ZD.sub.2 -Q.sub.3, and thus the transistor Q.sub.3 becomes conductive. As a result, a gate-on current i.sub.G flows through a path C.sub.1 -R.sub.10 -Q.sub.3 -G-K-G.sub.nd to turn on the GTO. After the GTO has been turned on, the anode voltage thereof becomes less than a predetermined value at a time t.sub.2. Then, the current having flowed into the base of the transistor Q.sub.3 is caused to flow through a path C.sub.1 -R.sub.8 -R.sub.9 -D.sub.4 -A, and is not supplied to the transistor Q.sub.3. As a result, the transistor Q.sub.3 becomes nonconductive and the gate-on current does not flow. However, the GTO is kept in the ON-state. Briefly speaking, in the present invention, the gate-on current i.sub.G for turning on the GTO flows only for a period between times t.sub.1 and t.sub.2 which is a minimum period required for turning it on, and therefore power dissipation in the gate circuit can be reduced. A zener voltage of the zener diode ZD.sub.2 is so selected as to be greater than the sum of a voltage drop across the diode D.sub.4 and a voltage drop between the anode and cathode terminals of the GTO. Thus, the current having flowed into the base of the transistor Q.sub.3 can be rapidly forced to flow into the anode terminal A of the GTO through the diode D.sub.4 when the GTO has been turned on. Further, when the GTO is turned off, a reverse base current to the transistor Q.sub.3 can flow smoothly. It is a matter of course that the zener diode ZD.sub.2 may be replaced by a combination of ordinary diodes, but it is preferred to use a single zener diode in order to simplify the gate circuit.

Next, explanation will be made on the case where the GTO is turned off. The control signal i.sub.F taking a low level is supplied to the photodiode of the photo-coupler PC.sub.1 at a time t.sub.3 shown in FIG. 1b. Then, the phototransistor of the photo-coupler PC.sub.1 becomes nonconductive. Accordingly, no current flows into the base of the transistor Q.sub.1, and therefore the transistor Q.sub.1 becomes non-conductive. In this case, however, a current flows into the base of the transistor Q.sub.2 through a path C.sub.1 -R.sub.4 -R.sub.6 -Q.sub.2, and the transistor Q.sub.2 is thereby made conductive. Then, the gate-off current i.sub.G flows through a path G.sub.nd -K-G-Q.sub.3 -ZD.sub.2 -R.sub.9 -Q.sub.2 -C.sub.2 and through a path G.sub.nd -K-G-Q.sub.4 -ZD.sub.2 -R.sub.9 -Q.sub.2 -C.sub.2. Thus, at a time t.sub.4, the transistor Q.sub.4 is made conductive but the transistor Q.sub.3 is kept nonconductive. When the transistor Q.sub.4 becomes conductive, the gate-off current i.sub.G flows into the gate of the thyristor Th.sub.1 through a path G.sub.nd -K-G-Q.sub.4 -R.sub.5 -Th.sub.1 -C.sub.2, and the thyristor Th.sub.1 is thereby made conductive. Accordingly, in the present invention, it is not required to include such a special circuit as the one-shot circuit disclosed in the previously-referred U.S. patent. Thereafter, the gate-off current i.sub.G flows through a path G.sub.nd -K-G-L.sub.1 -Th.sub.1 -C.sub.2, and the GTO is turned off at a time t.sub. 5. Then, the gate-off current i.sub.G becomes zero, and the thyristor Th.sub.1 is turned off naturally. However, throughout a period when the transistor Q.sub.2 is kept conductive, the transistor Q.sub.4 takes the conductive state and a reverse bias voltage is applied between the gate terminal G and cathode terminal K of the GTO through a path K-G.sub.nd -C.sub.2 -R.sub.12 -R.sub.5 -Q.sub.4 -G. As mentioned above, the transistor Q.sub.4 has a function of making the thyristor Th.sub.1 conductive and a function of improving the dv/dt capability of the GTO.

Incidentally, in FIG. 1b, reference symbol v.sub.Q1 designates a collector potential of the transistor Q.sub.1, v.sub.Q2 a collector potential of the transistor Q.sub.2, v.sub.Q3 a voltage between the collector and base of the transistor Q.sub.3, v.sub.Q4 a voltage between the collector and base of the transistor Q.sub.4, v.sub.Th1 a voltage between the anode and cathode of the thyristor Th.sub.1, and v.sub.GK a voltage between the gate and cathode of the GTO.

FIG. 2a shows another embodiment of a gate circuit according to the present invention, which is a modified version of the embodiment shown in FIG. 1a. In FIG. 2b which shows voltage and current waveforms in various parts of the embodiment shown in FIG. 2a, reference symbol V.sub.A designates an anode voltage of a GTO, I.sub.A an anode current of the GTO, v.sub.GK a voltage between the gate and cathode of the GTO, and i.sub.G a gate current. In this embodiment, a gate-on current flows through the same path as the embodiment shown in FIG. 1a, while a base current of the transistor Q.sub.4 flows through a path G.sub.nd -K-G-Q.sub.4 -ZD.sub.4 -R.sub.9 -Q.sub.2 -C.sub.2. In the case where the current increase rate in turning on a GTO is very high as in a PWM (pulse width modulation) inverter, if a very small inductance l.sub.K of the order of tens of nanohenries such as indicated by a dotted line in FIG. 2a is present between the cathode of the GTO and an earth terminal G.sub.nd, a transient voltage .DELTA.v.sub.GK is generated between the gate terminal G and cathode terminal K of the GTO, as shown in FIG. 2b. In some cases, this transient voltage .DELTA.v.sub.GK causes a false extingushing operation for the GTO if the circuit arrangement shown in FIG. 1a is employed as it is. That is, when the voltage .DELTA.v.sub.GK caused by the inductance l.sub.K at a turn-on time of the GTO becomes higher than the voltage E of the turn-on power source C.sub.1, the transistor Q.sub.3 having supplied a turn-on pulse is turned off, and further the transistor Q.sub.4 is driven to trigger the turn-off thyristor Th.sub.1. Thus, immediately after having been turned on, the GTO is erroneously turned off. FIG. 2b shows voltage and current waveforms before and after the GTO is turned on. In FIG. 2b, solid lines indicate a normal operation, and dotted lines an erroneous operation. When the erroneous operation as described above is generated, an abnormal operation is performed in a main circuit such as an inverter, and additionally a power-source shorting current flows through a path C.sub.1 -R.sub.10 -Q.sub.3 -L.sub.1 -Th.sub.1 -C.sub.2 in the gate circuit, thereby burning out the gate circuit. The circuit shown in FIG. 2a includes additional circuit elements for preventing such an erroneous operation. That is, a diode D.sub.5 shown in FIG. 2a is a fundamental means for solving the above problem, and the transient voltage .DELTA.v.sub.GK is clamped by the diode D.sub.5 so as not to exceed the supply voltage E. In some cases, however, the addition of only the diode D.sub.5 is not sufficient to clamp the transient voltage .DELTA.v.sub.GK, i.e. to bypass a transient reverse current due to the transient voltage. This is due to the fact that a transient recovery time is present with respect to the transient voltage in the forward characteristic of the diode D.sub.4. Namely, it takes a short time for the diode to sufficiently bypass the transient reverse current to the forward direction thereof. Therefore, the voltage .DELTA.v.sub.GK becomes higher than the supply voltage E by a small amount only for a very short period before the transient recovery time has lapsed. A zener diode ZD.sub.4 provides an operational margin for eliminating the above-mentioned difficulty caused by the recovery time. Namely, a resistor R.sub.0 is further provided to make a current path C.sub.1 -R.sub.0 -ZD.sub.4 -ZD.sub.2 -Q.sub.3 -G-K-G.sub.nd for charging the injection capacity of the zener diode ZD.sub.4 previously before the turn-on of the GTO, to thereby block the transient recovery voltage during the transient recovery time of the diode D.sub.5 and prevent the turn-off of the transistor Q.sub.3.

Further, a capacitor C.sub.5 forms a bypass for the transient reverse current appearing only for the above-mentioned very short period, and prevents the transient reverse current from flowing through the base of the transistor Q.sub.4. According to the circuit shown in FIG. 2a, even when the inductance l.sub.K is present at a cathode portion of the GTO, a stable, reliable operation of the GTO is obtained. However, all of the additional elements shown in FIG. 2a such as the diode D.sub.5, capacitor C.sub.5, zener diode ZD.sub.4 and register R.sub.0 are not required, but these additional elements may be adopted or rejected as required.

## Claims

1. A gate circuit provided with a turn-on circuit and a turn-off circuit each connected between gate and cathode terminals of a gate turn-off thyristor, said turn-on circuit including a series combination of a turn-on power source and a first NPN transistor, said turn-off circuit including a series combination of a turn-off power source and a thyristor, said gate circuit comprising: transistor for supplying a control signal to said base terminal of said first NPN transistor; and thyristor, emitter and collector terminals of said PNP transistor being connected to said anode and gate terminals of said thyristor, respectively, a base terminal of said PNP transistor being connected to said base terminal of said first NPN transistor.

2. A gate circuit according to claim 1, wherein said base terminal of said first NPN transistor is connected to said signal input terminal through a first zener diode whose forward direction is toward said signal input terminal.

3. A gate circuit according to claim 2, wherein a first diode is connected between a cathode terminal of said first zener diode and an anode terminal of said gate turn-off thyristor in such a manner that the forward direction of said first diode is toward said anode terminal of said gate turn-off thyristor.

4. A gate circuit according to claim 1, 2 or 3, wherein said gate turn-on circuit further comprises a second NPN transistor coupled to an emitter of said first NPN transistor to form a Darlington connection.

5. A gate circuit provided with a turn-on circuit and a turn-off circuit each connected between gate and cathode terminals of a gate turn-off thyristor, said turn-on circuit including a series combination of a turn-on power source and a first NPN transistor, said turn-off circuit including a series combination of a turn-off power source and a thyristor, said gate circuit comprising: of said first NPN transistor; transistor and said signal input terminal, the forward direction of said first zener diode being toward said signal input terminal; and thyristor, emitter and collector terminals of said PNP transistor being connected to said anode and gate terminals of said thyristor, respectively, a base terminal of said PNP transistor being connected to a anode terminal of said first zener diode.

6. A gate circuit according to claim 5, wherein a first diode is connected between said cathode terminal of said first zener diode and said anode terminal of said gate turn-off thyristor in such a manner that the forward direction of said first diode is toward said anode terminal of said gate turn-off thyristor.

7. A gate circuit according to claim 5 or 6, wherein a second diode is connected between said gate terminal of said gate turn-off thyristor and a positive electrode terminal of said turn-on power source in such a manner that the forward direction of said second diode is toward said positive electrode terminal.

8. A gate circuit according to claim 5 or 6, wherein a second zener diode is connected between said cathode terminal of said first zener diode and said base terminal of said PNP transistor in such a manner that the forward direction of said second zener diode is toward said base terminal of said PNP transistor.

9. A gate circuit according to claim 8, wherein a resistor is connected between said base terminal of said PNP transistor and a positive electrode terminal of said turn-on power source.

10. A gate circuit according to claim 5 or 6, wherein a capacitor is connected between said base and emitter terminals of said PNP transistor.

11. A gate circuit according to claim 8, wherein a capacitor is connected between said emitter terminal of said PNP transistor and an anode terminal of said second zener diode.

12. A gate circuit according to claim 5 or 6, wherein said gate turn-on circuit further comprises a second NPN transistor coupled to an emitter of said first NPN transistor to form a Darlington connection.

13. A gate circuit according to claim 1, 2, 3, 5 or 6, wherein a resistor is connected between a positive electrode terminal of said turn-on power source and said signal input terminal, a switching element is connected between said signal input terminal and a negative electrode terminal of said turn-off power source, and said control signal is generated on the basis of an on-off action of said switching element.

14. A turn-on circuit connected between gate and cathode terminals of a gate turn-off thyristor and including a series combination of a turn-on power source and a first NPN transistor, said turn-on circuit comprising: of said first NPN transistor; transistor and said signal input terminal, the forward direction of said first zener diode being toward said signal input terminal; and diode and an anode terminal of said gate turn-off thyristor, the forward direction of said first diode being toward said anode terminal of said gate turn-off thyristor.

15. A turn-on circuit according to claim 14, further comprising a second NPN transistor coupled to an emitter of said first NPN transistor to form a Darlington connection.