# Patent

## Title
Self-timed semiconductor integrated circuit device

## Abstract

The semiconductor types of first and second semiconductor type transistors are different from one another and the two transistors are connected in series. An input signal is supplied to each of the bases of the first and second transistors. Each of the collector electric currents of the first and second transistors are thus controlled. An output is provided from the inter-connection point of the first and second transistors. A third transistor supplies the collector electric current which is 1/K.sub.1 times the collector electric current of the second transistor, where K.sub.1 is the current-mirror ratio between the second and third transistors. A fourth transistor has the collector and base connected with one another. The fourth transistor supplies an electric current according to the collector electric current of the third transistor. A fifth transistor has the base electric current controlled by the base electric current of the fourth transistor. The fifth transistor supplies its collector electric current, which is K.sub.2 times the collector electric current of the fourth transistor, to the base of the first transistor, where K.sub.2 is the current-mirror ratio between the fourth and fifth transistors.

## Background
1. Field of the Invention

The present invention relates to an amplifying electronic circuit, and, in particular, to an amplifying electronic circuit having a single-end push-pull formation output.

2. Description of the Related Art

FIG.1 shows an amplifying electronic circuit in an example of the related art. This amplifying electronic circuit 1 includes a bias circuit portion 2 which applies a bias to an input signal, a differential amplifying circuit portion 3 which amplifies the input signal, an output circuit portion 4 which outputs the amplified input signal, a constant-electric-current circuit portion 5 which supplies driving constant electric currents to the differential amplifying circuit portion 3 and the output circuit portion 4, and feedback circuit portion 6 which controls the amount of feedback.

The bias circuit portion 2 includes resistors R.sub.1, R.sub.2, R.sub.3, and a ripple removing capacitor C.sub.1. A signal source 7 supplies a signal, to be amplified, to the bias circuit portion 2 via a direct-electric-current removing capacitor C.sub.2. The bias circuit portion 2 applies a bias to the thus-supplied signal, and supplies the signal to the differential amplifying circuit portion 3.

The differential amplifying circuit portion 3 includes PNP transistors Q.sub.1 and Q.sub.2 which act as input transistors, and NPN transistors Q.sub.3 and Q.sub.4 which act as a driving electric current source. The input signal, which has a bias applied thereto by the bias circuit portion 2, is supplied to the base of the input PNP transistor Q.sub.1. An output signal, which is controlled by the feedback circuit portion 6 is supplied to the base of the other input PNP transistor Q.sub.2. The differential amplifying circuit portion 3 noninverting-amplifies the input signal and then supplies it to the output circuit portion 4.

The output circuit portion 4 includes NPN transistors Q.sub.5, Q.sub.6, Q.sub.7, PNP transistors Q.sub.8, Q.sub.9, resistors R.sub.6, R.sub.5, and a capacitor C.sub.3. The output circuit portion 4 is a push-pull output circuit, power-amplifies the signal supplied by the differential amplifying circuit portion 3, and outputs the amplified signal to a load capacitor C.sub.L and a load resistor R.sub.L. During this operation, an electric current for generating an idling electric current is always supplied to the output circuit portion 4 from the constant-electric-current circuit portion 5 in order to prevent a crossover distortion from occurring around the cut-off levels of the NPN transistor Q.sub.7 and the PNP transistor Q.sub.9.

The feedback circuit portion 6 includes resistors R.sub.f and R.sub.i. The resistor R.sub.f is connected between the output node of the output circuit portion 4 and the base of the PNP transistor Q.sub.2 which acts as the input transistor of the differential amplifying circuit portion 3. The other resistor R.sub.i is connected between the resistor R.sub.f and the inter-connection point of the resistors R.sub.1, R.sub.2 and R.sub.3 of the bias circuit portion 2. Thereby, the differential amplifying circuit portion 3 is configured as being a noninverting amplifying circuit.

The constant-electric-current circuit portion 5 includes a constant-current source 8, PNP transistors Q.sub.10, Q.sub.11, Q.sub.12, and resistors R.sub.7, R.sub.8. The constant-electric-current circuit portion 5 includes a current-mirror circuit. A power-supply voltage Vcc is supplied by a power supply 9 to the constant-electric-current circuit portion 5. The constant-electric-current circuit portion 5 generates a driving electric current from the supplied power-supply voltage Vcc, and supplies the driving electric current to the differential amplifying circuit portion 3 and the output circuit portion 4.

Setting of the idling electric current in the output circuit portion 4 will now be described. In the output circuit portion 4, each of an emitter area ratio between the transistors Q.sub.5 and Q.sub.7 and an emitter area ratio between the transistors Q.sub.8 and Q.sub.9 is assumed as being `n`. Further, symbols will be used for various factors as follows:

It is assumed that the amplification factor h.sub.FE Of each transistor is h.sub.FE >>1. Thereby, a base electric current can be considered to be zero with respect to a collector electric current and a base electric current can be considered to be zero with respect to an emitter electric current. A feedback current i.sub.f is assumed such that i.sub.f <<I.sub.E7. .multidot.I.sub.E9 +V.sub.BE9 =V.sub.BE7 +V.sub.BE9 +(R.sub.5 +R.sub.6).multidot.I.sub.E9                               ( 1)

The NPN transistors Q.sub.5, Q.sub.7 and the PNP transistor Q.sub.8, Q.sub.9 are assumed as being configured such that the NPN transistors Q.sub.5, Q.sub.7 are symmetrical with the PNP transistor Q.sub.8, Q.sub.9. Further, it is also assumed that R.sub.5 =R.sub.6. Thereby, it is possible that the emitter electric current I.sub.E7 of the transistor Q.sub.7 is equal to the emitter electric current I.sub.E9 of the transistor Q.sub.9. Further, it is enough to consider a relationship between the transistor Q.sub.5 and the transistor Q.sub.7 when the above-mentioned equation (1) is considered.

Therefore, when the equation (1) is considered, it is enough to consider only the following equation (2):

Generally speaking, the base-emitter voltage V.sub.BE of a transistor is expressed by the following equation (3): /V.sub.A).multidot.I.sub.S }!                             (3);

where: V.sub.T .apprxeq.26 mV, where the temperature thereof is 25.degree. C.); proportion to the emitter area);

When the equation (2) is rewritten using the equation (3), ##EQU1## (Because it is considered that the base electric current is substantially zero with respect to the collector electric current and with respect to the emitter electric current as mentioned above, it is possible that I.sub.C7 can be considered to be equal to I.sub.E7.) ##EQU2## The equation (5) can become the following equation (6): /V.sub.A7)/(1+V.sub.CE5 /V.sub.A5).multidot.I.sub.S7 /I.sub.S5 }=R.sub.5 .multidot.I.sub.C7                                        ( 6).

In the equation (6), I.sub.S7 /I.sub.S5 corresponds to the above-mentioned area ratio `n`. Further, the collector current I.sub.C5 of the transistor Q.sub.5 is approximately equal to the collector current I.sub.C12 of the transistor Q.sub.12 which supplies an electric current to the transistor Q.sub.5. Thereby, the equation (6) becomes the following equation (7): /V.sub.A7)/(1+V.sub.CE5 /V.sub.A5)}.multidot.n!=R.sub.5 .multidot.I.sub.C7( 7).

Generally speaking, in a power amplifier or the like, setting is performed such that an output electric current flows in an amount 100 times to 1000 times the idling electric current. The value of R.sub.5 .multidot.I.sub.C7 in the equation (7) is as small as tens of millivolts according to a design of such a semiconductor device.

It is assumed that V.sub.T .multidot.ln{I.sub.C7 /I.sub.C12 .multidot.(1+V.sub.CE5 /V.sub.A5)/(1+V.sub.CE7 /V.sub.A7)}in the equation (7) is sufficiently larger than R.sub.5 .multidot.I.sub.C7. That is, /V.sub.A5)/(1+V.sub.CE7 /V.sub.A7)}>>R.sub.5 .multidot.I.sub.C7( 8).

It is possible that the following equation (9) is obtained; /V.sub.A7)}                                               (9).

A diode connection is performed for the transistor Q.sub.5. Therefore, V.sub.CE5 is equal to V.sub.BE5. V.sub.BE5 .apprxeq. 0.7 (V), and is constant. Therefore, V.sub.BE5 does not substantially depend on the power-supply voltage.

This is because, generally, in a single-end push-pull electronic circuit, an output center voltage V.sub.OUT is set to (1/2)Vcc.

In the above-mentioned equation (9), the collector electric current I.sub.C7 of the transistor Q.sub.7, which current corresponds to the idling electric current, is obtained from the following equations (11) (corresponding to the above equation (9) ):

where

K=1/(1+V.sub.CE5 /V.sub.A5).

Thus, in the related art, the idling electric current I.sub.C7 is determined from the collector current of the transistor Q.sub.12 which supplies the driving electric current, the emitter area ratio between the transistor Q.sub.5 and transistor Q.sub.7, and resistance values of the resistors R.sub.5 and R.sub.6.

FIG.2 shows characteristics of the idling electric current with respect to the temperature of the device in the related art.

As shown in FIG.2, the idling electric current tends to increase as the temperature of the device increases.

FIG.3 shows characteristics of the idling electric current with respect to the power-supply voltage in the related art.

As shown in FIG.3, the idling electric current increases as the power-supply voltage Vcc increases. As shown in the equation (10), V.sub.CE7 depends on the power-supply voltage Vcc. As shown in the equation (11), the idling electric current depends on V.sub.CE7. Therefore, the idling electric current depends on the power-supply voltage.

In the related art, the idling electric current being supplied to the output transistors in the output circuit portion varies depending on the temperature of the device and power-supply voltage as discussed above. Thereby, it is not possible to provide a stable output signal.

An object of the present invention is to provide an amplifying electronic circuit in which a stable operation is provided without regard to ambient conditions.

An amplifying electronic circuit according to the present invention comprises:

first and second transistors which have semiconductor types different from one another and are connected in series, an input signal being supplied to each of the bases of the first and second transistors, each of the collector electric currents of the first and second transistors being controlled, an output being provided from the inter-connection point of the first and second transistor; and

a current-mirror circuit for controlling the base electric current of the first transistor according to the base electric current supplied to the second transistor.

The current-mirror circuit controls the base electric current of the first transistor according to the base electric current supplied to the second transistor, as mentioned above. Thereby, an idling electric current flowing through the first and second transistors is appropriately controlled. As a result, the idling electric current value is determined from a set constant current and a current mirror ratio. Accordingly, it is possible to improve stability of the idling electric current.

The current-mirror circuit comprises: 1/K.sub.1 times the collector electric current of the second transistor where K.sub.1 is the current-mirror ratio between the second and third transistors; another, the fourth transistor supplying an electric current according to the collector electric current of the third transistor; and base electric current of the fourth transistor, the fifth transistor supplying the collector electric current which is K.sub.2 times the collector electric current of the fourth transistor to the base of the first transistor.

In such a configuration, the idling electric current I.sub.C2 flowing through the second transistor and the collector electric current I.sub.C3 of the third transistor have the following relationship:

where K.sub.2 is the current-mirror ratio between the fourth and fifth transistors.

The collector electric current I.sub.C4 of the fourth transistor and the collector electric current I.sub.C5 of the fifth transistor have the following relationship:

Because I.sub.C3 .apprxeq.I.sub.C4,

I.sub.C5 is set by driving electric currents which drive the amplifying electronic circuit. Therefore, when the driving electric currents are stable, the idling current is determined by K.sub.1, K.sub.2. The current mirror ratios K.sub.1 and K.sub.2 are emitter area ratios between the second and third transistors and between the fourth and fifth transistors, respectively. Therefore, the idling electric current is not likely to be affected by the temperature of the device and is not likely to be affected by the power-supply voltage. Accordingly, it is possible to allow the amplifying electronic circuit to stably operate.

Other objects and further features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

FIG.1 shows a circuit diagram of an example of the related art;

FIG.2 shows characteristics of an idling electric current with respect to the temperature of the device in the related art;

FIG.3 shows characteristics of the idling electric current with respect to a power-supply voltage in the related art;

FIG.4 shows a circuit diagram of a first embodiment of the present invention;

FIG.5 shows characteristics of an idling electric current with respect to the temperature of the device in the first embodiment;

FIG.6 shows characteristics of the idling electric current with respect to a power-supply voltage in the first embodiment;

FIG.7 shows a circuit diagram of a second embodiment of the present invention; and

FIG.8 shows a circuit diagram of a third embodiment of the present invention.

FIG.4 shows a circuit diagram of a first embodiment of the present invention. The amplifying electronic circuit 11 in the first embodiment includes a bias circuit portion 12 for applying a bias to an input signal, a differential amplifying circuit portion 13 which amplifies the input signal, an output circuit portion 14 which performs power amplification on a received signal, a constant-electric-current circuit portion 15 which supplies driving constant electric currents to the differential amplifying circuit portion 13 and to the output circuit portion 14, a feedback circuit portion 16 for controlling feedback, and a current-mirror circuit 17 for setting an idling electric current of the output circuit portion 14.

The bias circuit portion 12 includes resistors R.sub.11, R.sub.12, R.sub.13, and a ripple removing capacitor C.sub.11. A signal source 18 supplies a signal to be amplified to the bias circuit portion 12 via a direct-current removing capacitor C.sub.12. The bias circuit portion 12 applies a bias to the supplied signal, and provides the signal to the differential amplifying circuit portion 13.

The differential amplifying circuit portion 13 includes PNP transistors Q.sub.21 and Q.sub.22 which act as input transistors, NPN transistors Q.sub.23 and Q.sub.24 which act as a driving electric current source, and resistors R.sub.14 and R.sub.15. The input signal, which has the bias applied thereto by the bias circuit portion 12 as mentioned above, is supplied to the base of the input PNP transistor Q.sub.21. An output signal, which has undergone control by the feedback circuit portion 16 is supplied to the base of the other input PNP transistor Q.sub.22. The differential amplifying circuit portion 13 performs noninverting-amplification on the input signal and then supplies the signal to the output circuit portion 14.

The output circuit portion 14 includes NPN transistors Q.sub.25, Q.sub.26, Q.sub.27, a PNP transistor Q.sub.28, and resistors R.sub.16, R.sub.17. The output circuit portion 14 is configured as being a push-pull output electronic circuit. The output circuit portion 14 performs power amplification on the received signal, and provides the signal to a load capacitor C.sub.L and a load resistor R.sub.L. During the amplification operation, the current-mirror circuit 17 always supplies an electric current for generating the idling electric current to the output circuit portion 14 in order to prevent crossover distortion from occurring around the cut-off levels of the NPN transistor Q.sub.27 and PNP transistor Q.sub.28.

The feedback circuit portion 16 includes resistors R.sub.f and R.sub.i. The resistor R.sub.f is connected between the output node of the output circuit portion 14 and the base of the PNP transistor Q.sub.22 which acts as the input transistor of the differential amplifying circuit portion 13. The other resistor R.sub.i is connected between the resistor R.sub.f and the inter-connection point of the resistors R.sub.11, R.sub.12 and R.sub.13 of the bias circuit portion 2. Thereby, the differential amplifying circuit portion 13 is configured as being a noninverting amplifying electronic circuit.

The constant-electric-current circuit portion 15 includes a constant-current source 19, PNP transistors Q.sub.29, Q.sub.30, Q.sub.31, Q.sub.32, and resistors R.sub.18, R.sub.19, R.sub.20. The constant-electric-current circuit portion 15 is configured as being a current-mirror electronic circuit. A power-supply voltage Vcc is supplied by a power supply 20 to the constant-electric-current circuit portion 15. The constant-electric-current circuit portion 15 generates a driving electric current from the supplied power-supply voltage Vcc, and supplies the driving electric current to the differential amplifying circuit portion 13, the output circuit portion 14, and the current-mirror circuit 17.

The current-mirror circuit 17 includes an NPN transistor Q.sub.33, and PNP transistors Q.sub.34, Q.sub.35. The current-mirror circuit 17 controls the base electric current of the output transistor Q.sub.28 according to the base electric current of the other output transistor Q.sub.27. Thus, the current-mirror circuit 17 stabilizes the idling electric current flowing through the output transistors Q.sub.27, Q.sub.28.

Setting of the idling electric current in the output circuit portion 14 of the amplifying electronic circuit 11 will now be described. Hereinafter, the collector electric current of a transistor Q.sub.n will be referred to as I.sub.Cn.

Electric currents I.sub.C30, I.sub.C31 and I.sub.C32 supplied from the constant-electric-current circuit portion 15 are set as follows:

Electric currents I.sub.C25, I.sub.C26 supplied to the transistors in the output circuit portion 14 are set as follows:

where K.sub.1 is the current mirror ratio between the transistor Q.sub.27 and transistor Q.sub.33 ; and

where K.sub.2 is the current mirror ratio between the transistor Q.sub.34 and transistor Q.sub.35.

With regard to the idling electric currents I.sub.C27, I.sub.C28, because it is possible to assume that I.sub.C33 is approximately equal to I.sub.35, the above equation (14) can be rewritten as:

Further, the above-equation (15) can be rewritten as:

Thereby, the above equation (14) can be rewritten as:

Because

the idling electric current I.sub.C27, I.sub.C28 can be expressed as follows:

Here, it is assumed that the current amplification h.sub.FE of the transistors is sufficiently larger than 1. That is, it is assumed that h.sub.FE >>1. Thereby, a base electric current can be considered to be zero with respect to a collector electric current and a base electric current can be considered to be zero with respect to an emitter electric current.

The above equation (16) can be rewritten, using the above equations (12) and (13), into the following equation (17): =(K.sub.1 I.sub.C30)/(4K.sub.2)                           (17).

The setting shown in the equations (12) and (13) may be changed into the setting shown in the following equations (18) and (19), for example:

and

If the setting of equations (18) and (19) is used, the idling electric current I.sub.C27, I.sub.C28 are expressed as follows: ##EQU3##

In the first embodiment, by changing the setting of the equations (12) to (15), the setting of the idling electric current can be changed. Thus, substantial flexibility of the setting of the idling electric current can be provided.

FIG.5 shows characteristics of the idling electric current with respect to the temperature of the device in the first embodiment. FIG.6 shows characteristics of the idling electric current with respect to the power-supply voltage Vcc in the first embodiment. According to the first embodiment, as shown in the equation (17), (20), the idling electric current I.sub.C27, I.sub.C28 is determined from the current mirror ratios K.sub.1, K.sub.2, and the set electric current I.sub.C30. Because the current mirror ratios K.sub.1, K.sub.2 are approximately fixed without regard to the temperature of the device, power-supply voltage Vcc, the idling electric current I.sub.C27, I.sub.C28 can be provided, which current is stable without regard to the temperature of the device and power-supply voltage Vcc, as shown in FIGS.5 and 6, as long as the set electric current I.sub.C30 is stable.

FIG.7 shows a circuit diagram of a second embodiment of the present invention. In FIG.7, for parts/components identical to those shown in FIG.4, the same reference numerals are given and duplicated descriptions thereof will be omitted.

In an amplifying electronic circuit 21 in the second embodiment, different from the first embodiment, the collector of the transistor Q.sub.34 of the current-mirror circuit 17 is connected to the inter-connection point of the emitter of the transistor Q.sub.32 and the resistor R.sub.20 in the constant-electric-current circuit portion 15, and the transistor Q.sub.32 supplies an electric current to the output circuit portion 14. According to the second embodiment, an effect similar to that of the first embodiment can be provided. Further, it is possible to have a smaller current mirror ratio K.sub.2 in the current-mirror circuit 17.

FIG.8 shows a circuit diagram of a third embodiment of the present invention. In FIG.8, for parts/components identical to those shown in FIG.4, the same reference numerals are given and duplicated descriptions thereof will be omitted.

In an amplifying electronic circuit 31 in the third embodiment, the electronic circuit of the first embodiment has a phase control circuit 32 added for adjusting the phase of the output signal, and resistors R.sub.23, R.sub.24 are added in the output circuit portion 14 and the current-mirror circuit 17 respectively. Thus, the amplifying electronic circuit 31 is approximately configured as being an electronic circuit actually provided in a semiconductor integrated circuit. The phase control circuit 32 includes a PNP transistor Q.sub.36, a NPN transistor Q.sub.37, a phase adjusting capacitors C.sub.21, C.sub.22, and resistors R.sub.21, R.sub.22.

In the third embodiment, by setting the phase adjusting capacitors C.sub.21, C.sub.22 to values appropriate for a particular input signal frequency, it is possible to provide a phase of the output signal such that undesired oscillation or the like can be avoided.

The present invention is not limited to the above-described embodiments, and variations and modifications may be made without departing from the claimed scope of the present invention.

## Claims

1. An amplifying electronic circuit comprising: semiconductor types being different from one another, are connected in series, an input signal being supplied to the base of each of said first and second transistors, a collector electric current of each of said first and second transistors being controlled, an output being provided from a connection point of said first and second transistors; second transistor, said third transistor supplying a collector electric current equal to 1/K.sub.1 times said collector electric current of said second transistor, where K.sub.1 is the current mirror ratio between said second and third transistors; current which is K.sub.2 times a collector electric current of said fourth transistor, where K.sub.2 is the current mirror ratio between said fourth and fifth transistors, said third, fourth and fifth transistors thereby controlling a base electric current of said first transistor according to a base electric current supplied to said second transistor.

2. The amplifying electronic circuit according to claim 1, wherein another, said fourth transistor supplying an electric current according to the collector electric current of said third transistor; and electric current of said fourth transistor, said fifth transistor supplying the collector electric current to the base of said first transistor.

3. An amplifying electronic circuit comprising: semiconductor types being different from one another, are connected in series, an input signal being supplied to a base of each of said first and second transistors, a collector electric current of each of said first and second transistors being controlled, an output being provided from a connection point of said first and second transistors; second transistor and which supplies a collector electric current which is 1/K.sub.1 times the collector electric current of said second transistor, where K.sub.1 is the current mirror ratio between said second and third transistors; said fourth transistor supplying an electric current according to the collector electric current of said third transistor; and base electric current of said fourth transistor, said fifth transistor supplying a collector electric current, which is K.sub.2 times the collector electric current of said fourth transistor, to the base of said first transistor, where K.sub.2 is the current-mirror ratio between said fourth and fifth transistors.

4. An amplifying electronic circuit comprising: one another and are connected in series, an input signal being supplied to a control electrode of each of said first and second active devices, an output electric current of each of said first and second active devices being controlled, an output of said amplifying electronic circuit being provided from an inter-connection point of said first and second active devices; relationship with said second semiconductor type active device, said third device supplying an output electric current equal to 1/K.sub.1 times said output electric current of said second device, where K.sub.1 is the current-mirror ratio between said second and third devices; current which is K.sub.2 times an output electric current of said fourth device, where K.sub.2 is the current mirror ratio between said fourth and fifth devices, said third, fourth and fifth devices thereby controlling a control electrode electric current of said first active device according to a control electrode electric current supplied to said second active device.

5. The amplifying electronic circuit according to claim 4, wherein connected with one another, said fourth active device supplying an electric current according to said output electric current of said third active device; and controlled by a control electrode electric current of said fourth active device, said fifth active device supplying said output electric current to said control electrode of said first active device.

6. An amplifying electronic circuit comprising: one another and are connected in series, an input signal being supplied to a control electrode of each of said first and second active devices, an output electric current of each of said first and second active devices being controlled, an output of said amplifying electronic circuit being provided from an inter-connection point of said first and second active devices; second active device and which supplies an output electric current which is 1/K.sub.1 times said output electric current of said second active device, where K.sub.1 is the current-mirror ratio between said second and third active devices; connected with one another, said fourth active device supplying an electric current according to said output electric current of said third active device; and controlled by a control electrode electric current of said fourth active device, said fifth active device supplying an output electric current, which is K.sub.2 times said output electric current of said fourth active device, to said control electrode of said first active device, where K.sub.2 is the current-mirror ratio between said fourth and fifth active devices.