# Patent

## Title
Finfet transistor circuit

## Abstract

A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.

## Background
CLAIM OF PRIORITY
This application is also a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/740,191, filed Jan. 12, 2013, which:
1. claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/586,387, filed Jan. 13, 2012, and
2. claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/589,224, filed Jan. 20, 2012, and
3. is a continuation-in-part application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/775,429, filed May 6, 2010, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/176,058, filed May 6, 2009.
Each of the above-identified applications is incorporated herein by reference in its entirety.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. application Ser. No. 12/572,225, filed Oct. 1, 2009, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/212,562, filed Sep. 17, 2008, issued as U.S. Pat. No. 7,842,975, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 11/683,402, filed Mar. 7, 2007, issued as U.S. Pat. No. 7,446,352, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/781,288, filed Mar. 9, 2006. Each of the above-identified applications is incorporated herein by reference in its entirety.
This application is also related to U.S. application Ser. No. 13/073,994, filed Mar. 28, 2011, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/013,342, filed Jan. 11, 2008, issued as U.S. Pat. No. 7,917,879, which claims priority under 35 U.S.C. 119(e) to each of 1) U.S. Provisional Patent Application No. 60/963,364, filed Aug. 2, 2007, and 2) U.S. Provisional Patent Application No. 60/972,394, filed Sep. 14, 2007. Each of the above-identified applications is incorporated herein by reference in its entirety.
This application is also related to U.S. application Ser. No. 12/753,793, filed Apr. 2, 2010, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/402,465, filed Mar. 11, 2009, issued as U.S. Pat. No. 7,956,421, which claims priority under 35 U.S.C. 119(e) to each of 1) U.S. Provisional Patent Application No. 61/036,460, filed Mar. 13, 2008, and 2) U.S. Provisional Patent Application No. 61/042,709, filed Apr. 4, 2008, and 3) U.S. Provisional Patent Application No. 61/045,953, filed Apr. 17, 2008, and 4) U.S. Provisional Patent Application No. 61/050,136, filed May 2, 2008. Each of the above-identified applications is incorporated herein by reference in its entirety.
This application is also related to U.S. application Ser. No. 13/189,433, filed Jul. 22, 2011, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/814,411, filed Jun. 11, 2010, issued as U.S. Pat. No. 7,994,545, which is a divisional application under 35 U.S.C. 121 of prior U.S. application Ser. No. 11/969,854, filed Jan. 4, 2008, issued as U.S. Pat. No. 7,763,534, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/983,091, filed Oct. 26, 2007. Each of the above-identified applications is incorporated herein by reference in its entirety.
This application is also related to U.S. application Ser. No. 11/956,305, filed Dec. 13, 2007, the disclosure of which is incorporated herein by reference in its entirety.
This application is also related to U.S. application Ser. No. 13/540,529, filed Jul. 2, 2012, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/497,052, filed Jul. 2, 2009, issued as U.S. Pat. No. 8,214,778, which claims priority: 1) under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/081,370, filed Jul. 16, 2008, and 2) as a continuation-in-part application under 35 U.S.C. 120 to U.S. application Ser. No. 12/013,342, filed Jan. 11, 2008, issued as U.S. Pat. No. 7,917,879, which claims priority under 35 U.S.C. 119(e) both U.S. Provisional Patent Application No. 60/963,364, filed Aug. 2, 2007, and U.S. Provisional Patent Application No. 60/972,394, filed Sep. 14, 2007. Each of the above-identified applications is incorporated herein by reference in its entirety.


BACKGROUND
It is known that optical lithography has reached the end of its capability at the 193 nm light wavelength and 1.35 numerical aperture (NA) immersion system. The minimum straight line resolution capability of this equipment is approximately 40 nm with an approximate 80 nm feature-to-feature pitch. A feature-to-feature pitch requirement lower than about 80 nm would require multiple patterning steps for a given structure type within a given chip level. Also, line end resolution becomes more challenging as lithography is pushed toward its resolution limits. In semiconductor device layout, a typical metal line pitch at the 32 nm critical dimension is approximately 100 nm. In order to achieve the cost benefit of feature scaling, a scaling factor of 0.7 to 0.75 is desirable. The scaling factor of about 0.75 to reach the 22 nm critical dimension would require a metal line pitch of about 75 nm, which is below the capability of current single exposure lithography systems and technology. It is within this context that the present invention arises.
SUMMARY
In one embodiment, an integrated circuit is disclosed. The circuit includes a first finfet transistor of a first transistor type. The circuit includes a first finfet transistor of a second transistor type. The circuit includes a second finfet transistor of the first transistor type. The circuit includes a second finfet transistor of the second transistor type. Each of the first and second finfet transistors of the first transistor type and each of the first and second finfet transistors of the second transistor type has a respective gate electrode extending lengthwise in a parallel direction. The gate electrodes of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type have their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction. The gate electrodes of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type are positioned on opposite sides of the common gate electrode track. Each of the first and second finfet transistors of the first transistor type is formed in part by a respective diffusion fin of a first diffusion type electrically connected to a common node. Each of the first and second finfet transistors of the second transistor type is formed in part by a respective diffusion fin of a second diffusion type electrically connected to the common node. The diffusion fins of the first diffusion type are collectively separated from the diffusion fins of the second diffusion type in the parallel direction by an inner non-diffusion region. The gate electrodes of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type are formed by a first conductive structure so as to be electrically connected to each other through the first conductive structure. The gate electrode of the second finfet transistor of the first transistor type is formed by a second conductive structure. The gate electrode of the second finfet transistor of the second transistor type is formed by a third conductive structure. Each of the first, second, and third conductive structures includes portions extending over the inner non-diffusion region. A first conductive contacting structure is connected to the portion of the second conductive structure that extends over the inner non-diffusion region. A second conductive contacting structure is connected to the portion of the third conductive structure that extends over the inner non-diffusion region. Each of the first and second conductive contacting structures is respectively defined as either a gate contact or a local interconnect structure.
In one embodiment, a method is disclosed for creating a layout of an integrated circuit. The method includes operating a computer to define a layout of a first finfet transistor of a first transistor type. The method includes operating the computer to define a layout of a first finfet transistor of a second transistor type. The method includes operating the computer to define a layout of a second finfet transistor of the first transistor type. The method includes operating the computer to define a layout of a second finfet transistor of the second transistor type. Each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type has a respective gate electrode layout feature extending lengthwise in a parallel direction. The gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type have their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction. The gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type are positioned on opposite sides of the common gate electrode track. Each layout of the first and second finfet transistors of the first transistor type includes a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node. Each layout of the first and second finfet transistors of the second transistor type includes a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node. The diffusion fin layouts of the first diffusion type are collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region. The gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type are formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature. The gate electrode layout feature of the second finfet transistor of the first transistor type is formed as part of a second conductive structure layout feature. The gate electrode layout feature of the second finfet transistor of the second transistor type is formed as part of a third conductive structure layout feature. Each of the first, second, and third conductive structure layout features includes portions extending over the inner non-diffusion layout region. The method includes operating the computer to define a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region. The method includes operating the computer to define a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region. Each of the first and second conductive contacting structures is respectively defined as either a gate contact or a local interconnect structure.
In one embodiment, a data storage device having program instructions stored thereon for generating a layout of an integrated circuit is disclosed. The data storage device includes program instructions for defining a layout of a first finfet transistor of a first transistor type. The data storage device includes program instructions for defining a layout of a first finfet transistor of a second transistor type. The data storage device includes program instructions for defining a layout of a second finfet transistor of the first transistor type. The data storage device includes program instructions for defining a layout of a second finfet transistor of the second transistor type. Each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type has a respective gate electrode layout feature extending lengthwise in a parallel direction. The gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type have their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction. The gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type are positioned on opposite sides of the common gate electrode track. Each layout of the first and second finfet transistors of the first transistor type include a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node. Each layout of the first and second finfet transistors of the second transistor type include a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node. The diffusion fin layouts of the first diffusion type are collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region. The gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type are formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature. The gate electrode layout feature of the second finfet transistor of the first transistor type is formed as part of a second conductive structure layout feature. The gate electrode layout feature of the second finfet transistor of the second transistor type is formed as part of a third conductive structure layout feature. Each of the first, second, and third conductive structure layout features includes portions extending over the inner non-diffusion layout region. The data storage device includes program instructions for defining a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region. The data storage device includes program instructions for defining a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region. Each of the first and second conductive contacting structures is respectively defined as either a gate contact or a local interconnect structure.
In one embodiment, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is structured to project from a surface of the substrate. The first diffusion fin is structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is structured to project from the surface of the substrate. The second diffusion fin is structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Also, either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.
In one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate, such that the first transistor has a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is formed to project from a surface of the substrate, and such that the first diffusion fin is formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The method also includes forming a second transistor on the substrate, such that the second transistor has a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is formed to project from the surface of the substrate, and such that the second diffusion fin is formed to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is formed at a position next to and spaced apart from the first diffusion fin. Also, the first and second transistors are formed such that either the first end or the second end of the second diffusion fin is formed at a position in the first direction between the first end and the second end of the first diffusion fin.
In one embodiment, a data storage device has computer executable program instructions stored thereon for rendering a layout of a semiconductor device. The data storage device includes computer program instructions for defining a first transistor to be formed on a substrate, such that the first transistor is defined to have a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is defined to project from a surface of the substrate, and such that the first diffusion fin is defined to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The data storage device also includes computer program instructions for defining a second transistor to be formed on the substrate, such that the second transistor is defined to have a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is defined to project from the surface of the substrate, and such that the second diffusion fin is defined to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is defined to be positioned next to and spaced apart from the first diffusion fin, and such that the second diffusion fin is defined to have either its first end or its second end positioned in the first direction between the first end and the second end of the first diffusion fin.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B show an example layout view of a finfet transistor, in accordance with some embodiments of the present invention.
FIG. 1C shows a variation of the finfet transistor of FIGS. 1A/1B in which the diffusion fin 102 is more pyramid-shaped in the vertical cross-section view A-A, in accordance with some embodiments of the present invention.
FIG. 1D shows a simplified vertical cross-section view of the substrate having a number of finfet transistors formed thereon, in accordance with some embodiments of the present invention.
FIG. 1E shows a diagram of fin pitch relationship in which the internal fin pitch Ps1 is substantially equal to the external fin pitch Ps2, in accordance with some embodiments of the present invention.
FIG. 1F shows a variation of the fin pitch relationship diagram of FIG. 1E in which the denominator (y) of the rational number is two, in accordance with some embodiments of the present invention.
FIG. 1G shows a variation of the fin pitch relationship diagram of FIG. 1E in which the denominator (y) of the rational number is three, in accordance with some embodiments of the present invention.
FIG. 1H shows a more generalized version of the fin pitch relationship diagram of FIG. 1E in which the internal fin pitch Ps1 and external fin pitch Ps2 are different, in accordance with some embodiments of the present invention.
FIG. 2A shows an exemplary cell layout incorporating finfet transistors, in accordance with some embodiments of the present invention.
FIG. 2B shows a circuit diagram corresponding to the 2-input NAND configuration of FIG. 2D, in accordance with some embodiments of the present invention.
FIG. 2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E, in accordance with some embodiments of the present invention.
FIG. 2D shows the layout of FIG. 2A in which the diffusion fins 201A are formed of an n-type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material, in accordance with some embodiments of the present invention.
FIG. 2E shows the layout of FIG. 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material, in accordance with some embodiments of the present invention.
FIG. 2F shows a variation of the layout of FIG. 2A in which the gate electrode structures have their ends substantially aligned on the top of the cell and on the bottom of the cell, in accordance with some embodiments of the present invention.
FIG. 2G shows a variation of the layout of FIG. 2A in which contacts are formed to extend from the met1 interconnect structure to the horizontal local interconnect structure under the power rail at the top of the cell and at the bottom of the cell, in accordance with some embodiments of the present invention.
FIG. 2H shows a variation of the cell of FIG. 2A in which two different diffusion fin pitches are used, in accordance with some embodiments of the present invention.
FIG. 2I shows a variation of the layout of FIG. 2A in which the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cell are extended to the full width of the met1 interconnect structures that serve as the power rails, in accordance with some embodiments of the present invention.
FIG. 3 shows a variation of the layout of FIG. 2A in which the met1 power rails are connected to vertical local interconnect, such that the met1 power rails serve as local power supplies, in accordance with some embodiments of the present invention.
FIG. 4 shows a variation of the layout of FIG. 2A in which a two-dimensionally varying met1 interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention.
FIG. 5 shows a variation of the layout of FIG. 2A in which the met1 power rails are connected to vertical local interconnect and in which a two-dimensionally varying men interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention.
FIG. 6 shows a variation of the layout of FIG. 2A in which fixed, minimum width, shared local met1 power supplies are used, along with a two-dimensionally varying men interconnect structure within the cell for intra-cell routing, in accordance with some embodiments of the present invention.
FIG. 7 shows a variation of the layout of FIG. 2A having shared local and global power supplies with hard connections in the cell, and a two-dimensionally varying met1 interconnect structure within the cell for intra-cell routing, in accordance with some embodiments of the present invention.
FIG. 8A shows a layout of an example standard cell in which input pins are placed between diffusion fins of the same type to ease routing congestion, and in which some diffusion fins are used as interconnect conductors, in accordance with some embodiments of the present invention.
FIG. 8B shows a variation of FIG. 8A in which two different gate electrode pitches are used, in accordance with some embodiments of the present invention.
FIG. 8C shows a circuit schematic of the layout of FIG. 8A, in accordance with some embodiments of the present invention.
FIG. 9A shows an example standard cell layout in which diffusion fins are utilized as interconnect conductors, in accordance with some embodiments of the present invention.
FIG. 9B shows the layout of FIG. 9A with three sets of cross-coupled transistors identified, in accordance with some embodiments of the present invention.
FIG. 9B-1 is an annotated version of FIG. 9A.
FIG. 9C shows a circuit schematic of the layout of FIG. 9A, in accordance with some embodiments of the present invention.
FIG. 9C-1 is an annotated version of FIG. 9A.
FIG. 10 shows an example standard cell layout with gate electrode contacts positioned substantially over the diffusion fins, in accordance with some embodiments of the present invention.
FIG. 11 shows an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 12A/B show a variation of the layout of FIG. 11 having minimum width met1 power rails, in accordance with some embodiments of the present invention.
FIGS. 13A/B show a variation of the layout of FIGS. 12A/B that does not have contacts from each of local interconnect and gate electrode structures to met1, in accordance with some embodiments of the present invention.
FIGS. 14A/B show a variation of the layout of FIG. 11 having minimum width men1 power rails, with all met1 structures of the same width and on the same pitch, including the power rails, in accordance with some embodiments of the present invention.
FIGS. 15A/B show a variation of the layout of FIGS. 14A/B having met1 routing structures populated so each (y) location has a met1 structure, in accordance with some embodiments of the present invention.
FIG. 15C-1 is an annotated version of FIG. 15A.
FIG. 15D-1 is an annotated version of FIG. 15A.
FIGS. 16A/B show a variation of the layout of FIG. 11 having gate electrode structure contacts placed between p-type diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 17A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 18A/B show a variation of the layout of FIGS. 17A/B in which the contacts connect to the horizontal local interconnect, and in which the horizontal local interconnect connects directly to the vertical local interconnect, in accordance with some embodiments of the present invention.
FIGS. 19A/B show a variation of the layout of FIGS. 17A/B in which the power rail contact to local interconnect are not shared, and in which there is no shared local interconnect under the power rails, in accordance with some embodiments of the present invention.
FIGS. 20A/B show a variation of the layout of FIGS. 19A/B in which the diffusion fins are offset by a diffusion fin half-pitch with respect to the cell boundary, in accordance with some embodiments of the present invention.
FIGS. 21A/B show a variation of the layout of FIGS. 20A/B having minimum width power rails and negative vertical local interconnect overlap of the diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 22A/B show a variation of the layout of FIGS. 17A/B having minimum width power rails, no shared local interconnect or diffusion fins under the power rails, and a larger space between p-find and n-fins, in accordance with some embodiments of the present invention.
FIGS. 23A/B show a variation of the layout of FIGS. 17A/B, in accordance with some embodiments of the present invention.
FIGS. 24A/B show a variation of the layout of FIGS. 23A/B, in accordance with some embodiments of the present invention.
FIGS. 25A/B show a variation of the layout of FIGS. 23A/B, in which the cell is doubled in height, in accordance with some embodiments of the present invention.
FIGS. 26A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 27A/B show a variation of the layout of FIGS. 26A/B, in accordance with some embodiments of the present invention.
FIGS. 28A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention.
FIG. 28C-1 is an annotated version of FIG. 28A.
FIGS. 29A/B show a variation of the layout of FIGS. 28A/B in which there are no local interconnect structures present between two gate electrode structures of n-type transistors, in accordance with some embodiments of the present invention.
FIGS. 30A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention.
FIG. 30C-1 is an annotated version of FIG. 30A.
FIG. 31A shows an example sdff cell layout with gate electrode and local interconnect line end gaps centered substantially between diffusion fins, in accordance with some embodiments of the present invention.
FIG. 31B shows the example sdff cell layout of FIG. 31A, with the local interconnect line end gaps centered substantially between the diffusion fins circled, in accordance with some embodiments of the present invention.
FIG. 31C shows the example sdff cell layout of FIGS. 31A and 31B with annotation of the region between two adjacent gate electrode structures in which the diffusion fin ends overlap each other in the x direction, in accordance with some embodiments of the present invention.
FIG. 32 shows an example layout in which all contact layer structures are placed between the diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 33 and 34 shows example layouts in which all contact layer structures are placed on the diffusion fins, in accordance with some embodiments of the present invention.
FIGS. 35A/B through 47A/B show cross-couple transistor configurations having transmission gate in both logic paths, requiring all the internal nodes to have a connection between p-type and n-type, in accordance with some embodiments of the present invention.
FIG. 35C shows a circuit schematic of the layouts of FIGS. 35A/B through 47A/B and 63A/B through 67A/B, in accordance with some embodiments of the present invention.
FIG. 43C-1 is an annotated version of FIG. 43A.
FIG. 43D-1 is an annotated version of FIG. 43A.
FIG. 43E-1 is an annotated version of FIG. 43A.
FIG. 45C-1 is an annotated version of FIG. 45A.
FIG. 46C-1 is an annotated version of FIG. 46A.
FIG. 46D-1 is an annotated version of FIG. 46A.
FIG. 46E-1 is an annotated version of FIG. 46A.
FIG. 46F-1 is an annotated version of FIG. 46A.
FIG. 46F-2 is an annotated version of FIG. 46A.
FIGS. 48A/B through 57A/B show cross-couple transistor configurations having transmission gate in the logic path with larger transistors, and tristate gate in other paths, in accordance with some embodiments of the present invention.
FIG. 48C shows a circuit schematic of the layouts of FIGS. 48A/B through 58A/B, in accordance with some embodiments of the present invention.
FIGS. 58A/B through 59A/B show cross-couple transistor configurations having transmission gate in the logic path with smaller transistors, and tristate gate in other paths, in accordance with some embodiments of the present invention.
FIG. 59C shows a circuit schematic of the layout of FIGS. 59A/B, in accordance with some embodiments of the present invention.
FIGS. 60A/B through 62A/B show cross-couple transistor configurations having tristate gate in both logic paths, in accordance with some embodiments of the present invention.
FIG. 60C shows a circuit schematic of the layouts of FIGS. 60A/B through 62A/B and FIGS. 68A/B through 69A/B, in accordance with some embodiments of the present invention.
FIGS. 63A/B through 67A/B show cross-couple transistor configurations having transmission gate in both logic paths, requiring all the internal nodes to have a connection between p-type and n-type, in accordance with some embodiments of the present invention.
FIGS. 68A/B through 69A/B show cross-couple transistor configurations having tristate gate in both logic paths, in accordance with some embodiments of the present invention.
FIG. 70A shows an example of gate electrode tracks 70-1A through 70-1E defined within the restricted gate level layout architecture, in accordance with some embodiments of the present invention.
FIG. 70B shows the exemplary restricted gate level layout architecture of FIG. 70A with a number of exemplary gate level features 7001-7008 defined therein, in accordance with some embodiments of the present invention.
FIGS. 71A/B through 77A/B show a number of example SDFF circuit layouts that utilize both tri-state and transmission gate based cross-coupled circuit structures, in accordance with some embodiments of the present invention.
FIG. 71C shows a circuit schematic of the layouts of FIGS. 71A/B and 77A/B, in accordance with some embodiments of the present invention.
FIG. 72C shows a circuit schematic of the layouts of FIGS. 72A/B through 76A/B, in accordance with some embodiments of the present invention.



DETAILED DESCRIPTION
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. Additionally, it should be understood that the various circuit and/or layout features depicted in a given figure presented herein can be utilized in combination with other circuit and/or layout features depicted in other figures presented herein.
A “finfet” is a transistor constructed from a vertical silicon island, i.e., fin. The finfet transistor can also be referred to as a tri-gate transistor. The term “finfet” transistor as used herein refers to any transistor configuration that includes a diffusion structure that projects upward from an underlying substrate. FIGS. 1A and 1B show an example layout view of a finfet transistor 100, in accordance with some embodiments of the present invention. The finfet transistor 100 is constructed from a diffusion fin 102 and a gate electrode layer 104. The diffusion fin 102 projects vertically upward from a substrate 105, as shown in FIG. 1B. A gate oxide layer 106 is disposed between the diffusion fin 102 and the gate electrode layer 104. The diffusion fin 102 can be doped to form either a p-type transistor or an n-type transistor. The portion of the gate electrode layer 104 that covers the diffusion fin 102 forms the gate electrode of the finfet transistor 100. Therefore, the gate electrode of the finfet transistor 100 can exist on three or more sides of the diffusion fin 102, thereby providing for control of the finfet transistor channel from three or more sides, as opposed to from one side as in a non-finfet transistor. Also, in some embodiments, the finfet transistor is formed as a “wrap-around” transistor in which the gate oxide layer 106 and the gate electrode layer 104 also extend beneath the diffusion fin 102.
It should be understood that the example finfet transistor 100 depicted in FIGS. 1A and 1B is provided by way of example and does not represent any limitation on the manner in which a finfet transistor, as referenced herein, may be designed and/or fabricated. Specifically, in some embodiments, the diffusion fin (e.g., 102) can be formed as a layering of different materials, including but not limited to Si (silicon), SiGe (silicon germanium), Ge (germanium), InP (indium phosphide), CNT (carbon nanotube), SiNT (silicon nanotube), or any combination thereof, among others. The gate oxide layer 106 can be formed from many different types of dielectric materials. For example, in some embodiments, the gate oxide layer 106 may be formed as a layer of hafnium oxide on a layer of silicon dioxide. In other embodiments, the gate oxide layer 106 can be formed by one or more other dielectric materials. In some embodiments, the gate electrode layer 104 can be formed by any number of electrically conductive materials. For example, in some embodiments, the gate electrode layer 104 can be formed as a film of TiN (titanium nitride) or TaN (tantalum nitride) covered by polysilicon. It should be understood, however, that in other embodiments the gate electrode layer 104 can be formed by other materials.
Also, while the example diffusion fin 102 of FIG. 1B is shown as having a substantially vertically projecting rectangular structure relative to the substrate 105 in the vertical cross-section view A-A, it should be understood that diffusion fins 102 in as “as-fabricated” state on a semiconductor chip may or may not have the substantially vertically projecting rectangular structure relative to the substrate 105. For example, in some embodiments, the diffusion fins 102 in their “as-fabricated” state may have a more triangular or pyramid-like shape in the vertical cross-section view A-A. FIG. 1C shows a variation of the finfet transistor 100 in which the diffusion fin 102 is more pyramid-shaped in the vertical cross-section view A-A. As depicted in FIG. 1C, in some embodiments, the sides of the diffusion fins 102 that extend upward from the substrate 105 may extend upward from the substrate at an angle to the substrate 105, so as to be non-perpendicular to the substrate 105. Also, it should be understood that such a non-perpendicular relationship between the substrate 105 and the sides of the diffusion fins 102 that extend upward from the substrate 105 may be by design or may be a result of fabrication.
Additionally, in some embodiments, a vertical projection distance of the diffusion fins 102 above the substrate 105 will be substantially equal across a region of the semiconductor chip. However, in other embodiments, some diffusion fins 102 may be designed and fabricated to have multiple different vertical projection distances above the substrate 105 across one or more regions of the semiconductor chip. Because the channel area of the finfet transistor 100 is a function of the diffusion fin 102 vertical projection distance above the substrate 105, such a variation in diffusion fin 102 vertical projection distance above the substrate 105 can be used to adjust a drive strength of selected finfet transistors 100 relative to others on the semiconductor chip. In one example, selective variation in diffusion fin 102 height can be provided through selective etching/overetching of the diffusion fin 102 structures during fabrication.
FIG. 1D shows a simplified vertical cross-section view of the substrate 105 having a number of finfet transistors 100 formed thereon, in accordance with some embodiments of the present invention. During fabrication of the finfet transistors 100, a series of cores 107 are formed to facilitate formation of side spacers 109 for each of the cores 107. The side spacers 109 are utilized as masking features to facilitate formation of the underlying finfet transistors 100. It should be understood that the cores 107, the side spacers 109, and the finfet transistors 100 extend lengthwise in a parallel manner, i.e., into the page as shown in FIG. 1D. It should be understood that the cores 107 and side spacers 109 are ultimately removed so as not to be present in the final as-fabricated semiconductor chip/device. The relative spacing of the finfet transistors 100 to each other is a function of the sizes and spacings of the cores 107 and side spacers 109.
FIG. 1D shows the cores 107 as having a width Wb and a pitch Pb. Also, FIG. 1D shows the side spacers 109 as having a width Ws. The finfet transistors 100 can then be characterized as having an alternating pair of fin pitches Ps1, Ps2, where Ps1 is an average centerline-to-centerline pitch between side spacers 109 of a given core 107 (Ps1 is referred to as an internal fin pitch), and where Ps2 is an average centerline-to-centerline pitch between neighboring side spacers 109 of a adjacently positioned cores 107 (Ps2 is referred to as an external fin pitch). Assuming uniformity in each of the core 107 width Wb, the core 107 pitch Pb, and the side spacer 109 width Ws, the internal fin pitch Ps1 is equal to the sum of the core 107 width Wb and side spacer 109 width Ws. And, the external fin pitch Ps2 is equal to the core 107 pitch Pb minus the sum of the core 107 width Wb and side spacer 109 width Ws. Therefore, both the internal fin pitch Ps1 and the external fin pitch Ps2 will vary as each of the core 107 pitch Pb, core 107 width Wb, and/or side spacer 109 width Ws varies. Thus, it should be understood that reference to a given “fin pitch” refers to an average of a given fin pitch, i.e., fin pitch Ps_ave is equal to an average of the internal fin pitch Ps1 and the external fin pitch Ps2, where each of the internal fin pitch Ps1 and the external fin pitch Ps2 are themselves averages.
FIG. 1E shows a diagram of fin pitch relationship in which the internal fin pitch Ps1 is substantially equal to the external fin pitch Ps2, in accordance with some embodiments of the present invention. A cell height Hc is equal to the average fin pitch multiplied by a rational number, i.e., multiplied by a ratio of integers x and y, where x is the numerator of the rational number and y is the denominator of the rational number. In the case of FIG. 1E where the internal fin pitch Ps1 and external fin pitch Ps2 are equal, the average fin pitch is equal to each of Ps1 and Ps2. Therefore, the cell height Hc is equal to either the internal fin pitch Ps1 or the external fin pitch Ps2 multiplied by the rational number. It should be understood that the denominator (y) of the rational number indicates a number of cells required to obtain a repetition of a fin-to-cell boundary spacing when the number of cells are positioned in an abutting manner in the direction of the cell height Hc, i.e., in the direction perpendicular to the lengthwise direction of the fins. Also, when the numerator (x) of the rational number is evenly divisible by the denominator (y) of the rational number, the top and bottom cell boundaries can have the same fin-to-cell boundary spacing when the internal fin pitch Ps1 and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary.
FIG. 1F shows a variation of the fin pitch relationship diagram of FIG. 1E in which the denominator (y) of the rational number is two, in accordance with some embodiments of the present invention. Therefore, in FIG. 1F the fin-to-cell boundary spacing will repeat every two cell heights Hc. Also, in the example of FIG. 1F, the numerator (x) of the rational number is not evenly divisible by the denominator (y) of the rational number. Therefore, the top and bottom fin-to-cell boundary spacings will be different when the internal fin pitch Ps1 and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary.
FIG. 1G shows a variation of the fin pitch relationship diagram of FIG. 1E in which the denominator (y) of the rational number is three, in accordance with some embodiments of the present invention. Therefore, in FIG. 1G the fin-to-cell boundary spacing will repeat every three cell heights Hc. Also, in the example of FIG. 1G, the numerator (x) of the rational number is not evenly divisible by the denominator (y) of the rational number. Therefore, the top and bottom fin-to-cell boundary spacings will be different when the internal fin pitch Ps1 and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary. It should be appreciated that the rational number can be defined in any manner necessary to obtain any desired fin-to-cell boundary spacing repetition frequency in the direction of the cell height Hc and/or any desired fin-to-cell boundary spacing specification.
FIG. 1H shows a more generalized version of the fin pitch relationship diagram of FIG. 1E in which the internal fin pitch Ps1 and external fin pitch Ps2 are different, in accordance with some embodiments of the present invention. In this example, the external fin pitch Ps2 is greater than the internal fin pitch Ps1. It should be understood that the cell height Hc is equal to the average fin pitch Ps_ave multiplied by the rational number (x/y), where x and y are integers. Also, it should be understood that the integer y indicates the fin-to-cell boundary spacing repetition frequency in the direction of the cell height Hc. Also, it should be understood that the top and bottom fin-to-cell boundary spacings can be equal to each other when the rational number (x/y) reduces to an integer value, i.e., when x is evenly divisible by y. If the rational number (x/y) does not reduce to an integer value, different fin phasing variations of a given cell may be defined in a cell library, where each fin phasing variation corresponds to a different possible fin-to-cell boundary spacing relationship for the given cell. Also, the number of possible fin phasing variations for a given cell will be equal to the denominator (y) of the rational number (x/y) in its most mathematically reduced form.
As discussed above, FIG. 1H shows use of two different diffusion fin pitches Ps1 and Ps2, in accordance with some embodiments of the present invention. More specifically, in FIG. 1H every other pair of adjacently positioned diffusion fin structures is placed according to a smaller pitch Ps1. In some embodiments, the larger diffusion fin pitch Ps2 is about 80 nanometers (nm) and the smaller diffusion fin pitch Ps1 is about 60 nm. However, it should be understood that in other embodiments, the smaller diffusion fin pitch Ps1 can be any size, and the larger diffusion fin pitch Ps2 can be any size. It should be understood that some embodiments can utilize more than two diffusion fin pitches within a given cell or block. And, some embodiments may utilize a single diffusion fin pitch within a given cell or block. Also, it should be understood that any layer of the semiconductor device, or portion thereof, can be formed in a manner similar to that described herein with regard to the diffusion fin pitch(es). For example, a local interconnect layer or a higher-level interconnect layer of the semiconductor device, or portion thereof, can include interconnect conductive structures foamed on one or more corresponding pitch(es) in a manner similar to that described herein with regard to the diffusion fin pitch(es).
Transistor scaling has slowed below the 45 nanometers (nm) critical dimension due to gate oxide limitations and/or source/drain leakage scaling issues. The finfet transistor mitigates these issues by controlling the channel of the finfet transistor from three sides. The increased electrical fields in the channel of the finfet transistor improve the relationship between I-on (on drive current) and I-off (sub-threshold leakage current). Finfet transistors can be employed at the 22 nm critical dimension and below. However, due to their vertical projection, finfet transistors can have restricted placement in various circuit layouts. For instance, there can be a required finfet-to-finfet minimum spacing and/or a required finfet-to-finfet minimum pitch, among other restrictions. Embodiments are disclosed herein for cell layouts that utilize finfet transistors in a manner which complements layout scaling.
A cell, as referenced herein, represents an abstraction of a logic function, and encapsulates lower-level integrated circuit layouts for implementing the logic function. It should be understood that a given logic function can be represented by multiple cell variations, wherein the cell variations may be differentiated by feature size, performance, and process compensation technique (PCT) processing. For example, multiple cell variations for a given logic function may be differentiated by power consumption, signal timing, current leakage, chip area, OPC (optical proximity correction), RET (reticle enhancement technology), etc. It should also be understood that each cell description includes the layouts for the cell in each level (or layer) of a chip within the associated vertical column of the chip, as required to implement the logic function of the cell. More specifically, a cell description includes layouts for the cell in each level of the chip extending from the substrate level up through a particular interconnect level.
FIG. 2A shows an exemplary cell layout incorporating finfet transistors, in accordance with some embodiments of the present invention. The cell layout includes a diffusion level within which a number of diffusion fins 201A/201B are defined for subsequent formation of finfet transistors and associated connections. In some embodiments, in an as-drawn layout state, the diffusion fins 201A/201B are linear-shaped. The diffusion fins 201A/201B are oriented to be parallel to each other such that their lengths extend in a first direction (x), and such that their widths extend in a second direction (y) perpendicular to the first direction (x).
In some embodiments, such as shown in FIG. 2A, the diffusion fins 201A/201B are placed in accordance with a fixed lengthwise centerline-to-lengthwise centerline pitch 203, as measured in the second direction (y). In this embodiment, the pitch 203 of the diffusion fins 201A/201B may be related to the cell height as measured in the second direction (y), such that the diffusion fin pitch 203 can be continued across cell boundaries. In FIG. 2A, the cell abutment edges represent the cell boundaries that run parallel to the diffusion fins 201A/201B. In some embodiments, the diffusion fins for multiple neighboring cells will be placed in accordance with a common global diffusion fin pitch, thereby facilitating chip level manufacturing of the diffusion fins in multiple cells.
It should be understood that other embodiments may utilize multiple diffusion fin pitches within a given cell or among a collection of cells. For example, FIG. 2H shows a variation of the cell of FIG. 2A in which two different diffusion fin pitches 203 and 205 are used, in accordance with some embodiments of the present invention. It should be understood in some embodiments the diffusion fins 201A/201B can be placed in accordance with one or more lengthwise centerline-to-lengthwise centerline pitches, or may be placed in an unrestricted manner with regard to lengthwise centerline-to-lengthwise centerline spacing. Also, in some embodiments, the diffusion fins 201A/201B can be placed in accordance with a given pitch and some pitch locations may be vacant with regard to diffusion fin placement. Additionally, in some embodiments, diffusion fins can be placed in a spaced apart, end-to-end manner at a given diffusion fin pitch location within a cell.
In each Figure presented herein, each diffusion fin, e.g., diffusion fins 201A/201B in FIG. 2A, is of either an n-type diffusion material or a p-type diffusion material. Also, depending on the particular cell implementation, the type of material of the diffusion fins may swapped to obtain a different cell logic function. Therefore, the notation type1_diff and type2_diff is used in the Figures to denote different material types for the diffusion fins. For example, if the type1_diff material is an n-type material, then the type2_diff material is a p-type material, vice-versa.
The cell layout also includes a number of linear-shaped gate electrode structures 207. The linear-shaped gate electrode structures 207 extend in a substantially perpendicular direction to the diffusion fins 201A/201B, i.e., in the second direction (y). When fabricated, the linear-shaped gate electrode structures 207 wrap over the diffusion fins 201A/201B to form gate electrodes of finfet transistors. It should be understood that an appropriate gate oxide material is disposed, i.e., positioned/deposited, between the diffusion fins 201A/201B and the gate electrode structures 207 formed thereover.
In some embodiments, the linear-shaped gate electrode structures 207 are placed in accordance with a fixed gate pitch 209 as measured in the first direction (x) between lengthwise centerlines of adjacently positioned gate electrode structures 207. In some embodiments, the gate pitch 209 is related to the cell width as measured in the first direction (x), such that the gate pitch can be continued across cell boundaries. Therefore, in some embodiments, the gate electrode structures 207 for multiple neighboring cells can be placed in accordance with a common global gate pitch, thereby facilitating chip level manufacturing of the linear-shaped gate electrode structures 207 in multiple cells.
It should be understood that some of the gate pitch locations in a given cell may be occupied by gate electrode structures 207, while other gate pitch locations in the given cell are left vacant. Also, it should be understood that multiple gate electrode structures 207 can be placed in a spaced apart, end-to-end manner along any of the gate electrode pitch locations within a given cell. It should be further understood that in some embodiments, the gate electrode structures 207 can be placed in accordance with one or more gate pitches, or can be placed in an unrestricted manner with regard to gate pitch.
The cell layout can also include a number of horizontal linear-shaped local interconnect structures (lih) 211, and/or a number of vertical linear-shaped local interconnect structures (liv) 213. The vertical local interconnect structures 213 are oriented parallel to the gate electrode structures 207. The horizontal local interconnect structures 211 are oriented parallel to the diffusion fins 201A/201B. In some embodiments, placement of the vertical local interconnect structures 213 is defined to be out of phase from placement of the gate electrode structures 207 by one-half of the gate pitch. Thus, in this embodiment, each vertical local interconnect structure 213 is centered between its neighboring gate electrode structures 207, when the neighboring gate electrode structures 207 are positioned on the gate pitch. Therefore, in this embodiment, adjacently placed vertical local interconnect structures 213 will have a center-to-center spacing equal to a local gate pitch or a global gate pitch, where the local gate pitch is applied within a given cell, and the global gate pitch is applied across multiple cells.
In some embodiments, placement of the horizontal local interconnect structures 211 is defined to be out of phase from placement of the diffusion fins 201A/201B by one-half of the diffusion fin pitch. Thus, in this embodiment, the horizontal local interconnect structures 211 can be centered between its neighboring diffusion fins 201A/201B, when the neighboring diffusion fins 201A/201B are positioned on the diffusion fin pitch. Therefore, in this embodiment, adjacently placed horizontal local interconnect structures 211 will have a center-to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin pitch is applied within a given cell, and the global diffusion fin pitch is applied across multiple cells.
In some embodiments, the cell layout also includes a number of linear-shaped metal 1 (met 1) interconnect structures 215. The met1 interconnect structures 215 are oriented parallel to the diffusion fins 201A/201B and perpendicular to the gate electrode structures 207. In some embodiments, placement of the met1 interconnect structures 215 is defined to be out of phase from placement of the diffusion fins 201A/201B by one-half of the diffusion fin pitch. Thus, in this embodiment, each met1 interconnect structure 215 is centered between its neighboring diffusion fins, when its neighboring diffusion fins are positioned on the diffusion fin pitch, albeit within a higher chip level. Therefore, in this embodiment, adjacently placed met1 interconnect structures 215 will have a center-to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin pitch is applied within a given cell, and the global diffusion fin pitch is applied across multiple cells. In some embodiments, the met1 interconnect structure 215 pitch, and hence the diffusion track pitch, is set at the single exposure lithographic limit, e.g., 80 nm for 193 nm wavelength light and 1.35 NA. In this embodiment, no double exposure lithography, i.e., multiple patterning, is required to manufacture the met1 interconnect structures 215. It should be understood that other embodiments can utilize met1 interconnect structures 215 that are oriented perpendicular to the diffusion fins 201A/201B and parallel to the gate electrode structures 207.
The cell layout also includes a number of contacts 217 defined to connect various met1 interconnect structures 215 to various local interconnect structures 211/213 and gate electrode structures 207, thereby providing electrical connectivity between the various finfet transistors as necessary to implement the logic function of the cell. In some embodiments, the contacts 217 are defined to satisfy single exposure lithographic limits. For example, in some embodiments, layout features to which the contacts 217 are to connect are sufficiently separated to enable single exposure manufacture of the contacts 217. For instance, the men interconnect structures 215 are defined such that their line ends which are to receive contacts 217 are sufficiently separated from neighboring men interconnect structure 215 line ends which are also to receive contacts 217, such that a spatial proximity between the contacts 217 is sufficiently large to enable single exposure lithography of the contacts 217. In some embodiments, neighboring contacts 217 are separated from each other by at least 1.5 times the gate pitch. It should be appreciated that line end cutting and the associated increased expense of double exposure lithography can be eliminated by sufficiently separating opposing line ends of the men interconnect structures 215. It should be understood that contact separation and line end separation on metal layers can be independent of each other in some embodiments, depending on choices made in the manufacturing process.
In some embodiments, the cell layout also includes a number of linear-shaped metal 2 (met2) interconnect structures 219. The met2 interconnect structures 219 are oriented parallel to the gate electrodes 207 and perpendicular to the diffusion fins 201A/201B. The met2 interconnect structures 219 can be physically connected to the men interconnect structures 215 by via 1 structures (v1) 221, as necessary to implement the logic function of the cell. Although the example cell of FIG. 2A shows the men interconnect structures 219 extending in a lengthwise manner perpendicular to the gate electrode structures 207 and the met 2 interconnect structures 219 extending in a lengthwise manner parallel to the gate electrode structures 207, it should be understood that in other embodiments the men interconnect structures 219 and met 2 interconnect structures 219 can be defined to extend in any orientation relative to the gate electrode structures 207. It should be understood that other embodiments can utilize met2 interconnect structures 219 are oriented perpendicular to the gate electrodes 207 and parallel to the diffusion fins 201A/201B.
The cell of FIG. 2A represents a multi-input logic gate having substantially aligned input gate electrodes, i.e., the center three gate electrode structures 207 that are co-aligned in the direction (y). Depending on the assignment of diffusion material type to the diffusion fins of type1 and type2, the cell of FIG. 2A can have a different logic function. For example, FIG. 2D shows the layout of FIG. 2A in which the diffusion fins 201A are formed of an n-type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material. The layout of FIG. 2D is that of a 2-input NAND gate. FIG. 2B shows a circuit diagram corresponding to the 2-input NAND configuration of FIG. 2D. FIG. 2E shows the layout of FIG. 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material. The layout of FIG. 2E is that of a 2-input NOR gate. FIG. 2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E. In FIGS. 2B-2E, each of P1 and P2 identifies a respective p-type transistor (e.g., PMOS transistor), each of N1 and N2 identifies a respective n-type transistor (e.g., NMOS transistor), each of A and B identifies a respective input node, and Q identifies an output note. It should be understood that similar notation for p-type transistors, n-type transistors, input nodes, and output nodes is also used in other figures herein.
Based on the foregoing, it should be appreciated that the logic function of a given cell layout can be changed by swapping the material types of the diffusion fins. Therefore, for each cell layout present herein, it should be understood that multiple logic functions can be represented depending on the assignment of n-type and p-type materials to the diffusion fins.
FIGS. 3 through 7 and 11 through 29 show variations on the layout of FIG. 2A, in accordance with some embodiments of the present invention. Therefore, each of the cells depicted in FIGS. 3 through 7 and 11 through 29 represent either a 2-input NAND gate or a 2-input NOR gate, depending on the assignment of n-type and p-type materials to the type1_diff and type2_diff diffusion fins. Each of cell layouts shown in FIGS. 2A through 7 and 11 through 29 have the following features:

    
    
        a multi-input logic gate with all its input electrodes substantially aligned,
        a local diffusion fin layer power supply,
        a global higher level interconnect power supply,
        a horizontal interconnect used to connect gate electrode to vertical local interconnect and to help improve manufacturability of the contact layers by enabling greater flexibility in contact placement.
    
    


It should be appreciated that each of the layouts in FIGS. 2A through 7 and 11 through 29 shows a different implementation of the same logic function. The layout of FIG. 2A shows the following features:

    
    
        gate electrodes for two or more inputs, with the gate electrodes substantially aligned,
        gate electrode end line spaces located between diffusion fins of the same diffusion type,
        gate electrode contacts between diffusion fins of the same diffusion type,
        type1_diff and type2_diff diffusion fins used for a local power supply, i.e., to the local interconnect of the cell, with met1 used for higher level interconnect (global) power supply, with both local and global power supplies shared with abutting cells,
        diffusion fins of type1_diff and type2_diff supply current to cell on a local level and can be connected to the higher level interconnect, e.g., met1, at prescribed intervals to support multiple chip power strategies,
        use of horizontal local interconnect for connection to gate electrode,
        a substantially horizontal local interconnect that connects the vertical local interconnect layer to the gate electrode layer can be used to shift locations of the gate electrode contacts, thereby serving to increase flexibility in the contact mask patterns, which can ease potential lithography issues.
    
    


FIG. 2F shows a variation of the layout of FIG. 2A in which the gate electrode structures have their ends substantially aligned on the top of the cell, as indicated by the oval 250, and on the bottom of the cell, as indicated by the oval 251, in accordance with some embodiments of the present invention.
FIG. 2G shows a variation of the layout of FIG. 2A in which contacts are formed to extend from the men interconnect structure to the horizontal local interconnect structure under the power rail at the top of the cell, as indicated by circle 260, and at the bottom of the cell, as indicated by circle 261, in accordance with some embodiments of the present invention.
As previously mentioned, FIG. 2H shows a variation of the cell of FIG. 2A in which two different diffusion fin pitches 203 and 205 are used, in accordance with some embodiments of the present invention.
It should be understood that the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cells in the various layouts depicted herein extend continuously in the horizontal direction (x) so as to service multiple cells that are positioned in a row, and possibly in adjacent rows. To illustrate this point, FIG. 2I shows a variation of the layout of FIG. 2A in which the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cell are extended to the full width of the men interconnect structures 215A/215B that serve as the power rails, in accordance with some embodiments of the present invention. It should be understood that the diffusion fins and horizontal local interconnect structures under the power rails 215A/215B, along with the power rails 215A/215B themselves, extend continuously in the (x) direction, as indicated by arrows 270.
FIG. 3 shows a variation of the layout of FIG. 2A in which the men power rails are connected to vertical local interconnect, such that the men power rails serve as local power supplies, in accordance with some embodiments of the present invention. It should be understood that the men power rails can be of variable width based on the cell library requirements. As with the layout of FIG. 2A, the layout of FIG. 3 uses multi-input logic gate with input electrodes substantially aligned.
FIG. 4 shows a variation of the layout of FIG. 2A in which a two-dimensionally varying men interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention. As with the layout of FIG. 2A, the layout of FIG. 4 uses multi-input logic gate with input electrodes substantially aligned and shared local and global power supplies. In some embodiments, bends in met1, i.e., the two-dimensional changes in direction of met1, occur on a fixed grid. In some embodiments, this met 1 fixed grid can include horizontal grid lines positioned between and extending parallel to the diffusion fins and positioned on the same pitch as the diffusion fins. Also, in some embodiments, this met 1 fixed grid can include vertical grid lines extending perpendicular to the diffusion fins and positioned so as to be centered on the vertical local interconnect.
FIG. 5 shows a variation of the layout of FIG. 2A in which the men power rails are connected to vertical local interconnect, such that the men power rails serve as local power supplies, and in which a two-dimensionally varying met1 interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention. As with the layout of FIG. 2A, the layout of FIG. 5 uses multi-input logic gate with input electrodes substantially aligned.
FIG. 6 shows a variation of the layout of FIG. 2A in which fixed, minimum width, shared local met1 power supplies are used, along with a two-dimensionally varying men interconnect structure within the cell for intra-cell routing, in accordance with some embodiments of the present invention. As with the layout of FIG. 2A, the layout of FIG. 6 uses multi-input logic gate with input electrodes substantially aligned.
FIG. 7 shows a variation of the layout of FIG. 2A having shared local and global power supplies with hard connections in the cell, and a two-dimensionally varying men interconnect structure within the cell for intra-cell routing, in accordance with some embodiments of the present invention. As with the layout of FIG. 2A, the layout of FIG. 7 uses multi-input logic gate with input electrodes substantially aligned.
FIG. 8A shows a layout of an example standard cell in which input pins are placed between diffusion fins of the same type to ease routing congestion, and in which some diffusion fins are used as interconnect conductors, in accordance with some embodiments of the present invention. FIG. 8C shows a circuit schematic of the layout of FIG. 8A, including input pins 8a, 8b, 8c, and 8d. Planar standard cells, i.e., non-finfet cells, typically have input pins located between diffusion features of the opposite type, i.e., n-type versus p-type, or between the diffusion features and the neighboring power rail, thereby creating a higher concentration of input pins in local areas of the planar cells. As demonstrated in FIG. 8A, by utilizing diffusion fins and placing some input pins between diffusion fins of the same diffusion type, the input pins can be spread apart in a more even manner over a larger area, thereby easing routing congestion for the cell. Also, as demonstrated in FIG. 8A, by selectively removing some gate electrode structures, as shown in the region 8001, the diffusion fin layers can be utilized as a substantially horizontal routing layer to connect to transistors or local interconnect that is not neighboring. For example, in the region 8001, the diffusion fins 8003 are used as horizontal routing conductors.
FIG. 8B shows a variation of FIG. 8A in which two different gate electrode pitches p1 and p2 are used, in accordance with some embodiments of the present invention. More specifically, in FIG. 8B every other pair of adjacently positioned gate electrode structures is placed according to a smaller pitch p2. In some embodiments, the larger gate electrode pitch p1 is about 80 nanometers (nm) and the smaller gate electrode pitch p2 is about 60 nm. It should be understood that some embodiments can utilize more than two gate electrode structure pitches within a given cell or block. And, some embodiments may utilize a single gate electrode structure pitch within a given cell or block. Also, it should be understood that any layer of the semiconductor device, or portion thereof, can be formed in a manner similar to that described herein with regard to the gate electrode pitch(es). For example, a local interconnect layer or a higher-level interconnect layer of the semiconductor device, or portion thereof, can include interconnect conductive structures formed on one or more corresponding pitch(es) in a manner similar to that described herein with regard to the gate electrode pitch(es).
Additionally, conductive structures in different layers (a.k.a. levels) of the semiconductor device, or portion thereof, can be positioned on respective pitch arrangements where a defined relationship exists between the conductive structure pitch arrangements of the different layers. For example, in some embodiments, diffusion fins in the diffusion fin layer are positioned in accordance with a diffusion fin pitch arrangement that can include one or more diffusion fin pitches, and metal 1 (met1) interconnect structures in the met1 layer are positioned in accordance with a met1 pitch arrangement that can include one or more met1 pitches, where one or more of the diffusion fin pitches are related to one or more of the met1 pitches by a rational number (x/y), where x and y are integer values. In some embodiments, a relationship between a diffusion fin pitch and a men pitch is defined by a rational number within a range extending from (1/4) to (4/1).
Also, in some embodiments, vertical local interconnect structures (liv) can be positioned in accordance with a vertical local interconnect pitch that is substantially equal to the gate electrode pitch. In some embodiments, the gate electrode pitch is less than 100 nanometers. Also, in a manner similar to that discussed above with regard to the diffusion fin pitch-to-met1 pitch relationship, in some embodiments the diffusion fin pitch arrangement can be related to the horizontal local interconnect pitch arrangement by a rational number (x/y), where x and y are integer values. That is, one or more diffusion fin pitches can be related to one or more horizontal local interconnect pitches by a rational number (x/y).
FIG. 9A shows an example standard cell layout in which diffusion fins are utilized as interconnect conductors, in accordance with some embodiments of the present invention. FIG. 9C shows a circuit schematic of the layout of FIG. 9A. The example standard cell layout of FIG. 9A includes multiple gate electrode line ends in a single track, such as in the gate electrode track 9001. FIG. 9B shows the layout of FIG. 9A with three sets of cross-coupled transistors identified. The first set of cross-coupled transistors is identified by the pair of lines cc1a and cc1b. The second set of cross-coupled transistors is identified by the pair of lines cc2a and cc2b. The third set of cross-coupled transistors is identified by the pair of lines cc3a and cc3b. 
FIG. 9B-1 illustrates another example of a standard cell layout with annotations that identify characteristics of the standard cell, in accordance with one embodiment of the present invention. The features depicted in FIG. 9B-1 are exactly the same as the features depicted in FIG. 9A. As shown, the various finfet transistors have been identified using notations ft # #, where the first “#” represents the transistor number, and the second “#” represents the transistor type. In one example, the transistor type can either be a p-type transistor or an n-type transistor. As used herein, the first type can either be a p-type transistor or an n-type transistor, and the second type can either be a p-type transistor or an n-type transistor that is opposite of the first type. As shown in the top portion of the standard cell, arrows have been used to identify the various transistors shown in the example cell. Identifying arrows, for example illustrate finfet transistors, where for example, ft22 means finfet transistor 2, of a second transistor type (n-type or p-type). Similar notations are provided for the other finfet transistors.
For instance, finfet transistors identified on the left side of the cell include the transistors ft12 and ft11, where ft12 is a finfet transistor 1 of the second type, and so on. Also shown is the 1st (first) common node electrical connection of the cell, i.e., the electrical connection of diffusion fins to a first common diffusion node. At the bottom of the standard cell additional finfet transistors of a 1st (first) type are identified using the marking arrows. Also shown in the cell is the 2nd (second) common node electrical connection, i.e., the electrical connection of diffusion fins to a second common diffusion node. A guide is also provided at the lower most part of the drawing, identifying the characteristics of the various components in the cell, and the associated hatching used to identify the various components, features, geometries, lines, connections, interconnections, positioning, placement, relative positioning, interconnections with relative positioning, and the like.
It should be understood that a given finfet transistor can be defined using multiple diffusion fins. For example, FIG. 9B-1 shows multiple arrows pointing to multiple diffusion fins for each of the finfet transistors ft11, ft21, ft31, ft41, ft51, ft61, ft91, ft101, ft12, ft22, ft32, ft42, ft52, ft62, ft92, ft102. The use of multiple diffusion fins to form a given finfet transistor is demonstrated in numerous instances throughout the example figures discussed herein.
Further illustrated is a 1st (first) direction, which may be the X axis, and a 2nd (second) direction which may be the Y axis. The 1st (first) and 2nd (second) directions point to the right of the cell, and to the top of the cell, respectively. However, it should be understood that the Y axis can traverse up and down across the cell, and the X axis can traverse left and right across the cell. In still another way of characterizing, the direction can be to associate the Y axis as a vertical direction, and the x-axis as a horizontal direction. Also shown for sake of completeness is a dashed line “ - - - ” to identify the cell abutment edge.
When various cells are placed together in a layout, such as to define an integrated circuit, the various cells are lined up to the abutment edges. The alignment to the abutment edges may, in one embodiment, allow cells to each include their own abutment edges, and each cell's abutment edge will overlap the abutment edge of an adjacent cell, depending on the placement of the cells for the circuit, as defined by the integrated circuit being designed, and ultimately formed into an electronic chip.
FIG. 9C-1 illustrates another example of the standard cell, in accordance with one embodiment of the present invention. The features depicted in FIG. 9C-1 are exactly the same as the features depicted in FIG. 9A. At the top of the figure, identifying annotations have been added, with pointers to specific locations, positions, orientations, and relative positions to features shown in the cell. Gate level features (GLF) are shown as being associated with specific contacts. For example, GLF contact 2 is shown with a directional arrow, just as GLF contact 4, GLF contact 6, GLF contact 7, GLF contact 1, GLF contact 3, and GLF contact 5.
Additionally shown is an electrical connection 1 with type 2 FIN, as denoted by the heavy dashed line. Electrical connection 2 with type 2 FIN is also identified near the top part of the cell, as denoted by the heavy dashed line. Electrical connection with type 1 FIN is illustrated near the bottom portion of the cell, as denoted by the heavy dashed line. Also shown are the various centerlines of the FINs. For example, centerlines associated with the 1st (first) FIN up to the 10th (tenth) FIN are shown near the right portion of the cell, as identifiers illustrating the horizontal positioning of the centerlines across the horizontal direction of the cell. As noted above, the horizontal direction of the cell may be referred to as an X direction. The gate electrodes, that define the finfet transistors are oriented vertically along the Y direction, or vertically in different portions of the cell relative to the horizontal direction. Further shown in FIG. 9C-1 are conductive segments (CS) and associated centerlines, such as centerline 1, and centerline 2. The vertically oriented conductive segments (CS) may correspond to a vertically oriented gate electrode structure or a vertically oriented local interconnect structure, or the like.
The centerline segments are, in this example generalized for purposes of understanding the nature of their positioning, orientation, interconnection, and relationship to other features in the cell provided as an example in FIG. 9C-1. The construction, orientation, positioning, and methodology associated with the layout features, and resulting integrated circuits made using the layouts, can also apply to various other layout designs that define other circuit elements of a standard cell library. Therefore, it should be understood that the example standard cells used to illustrate the positioning, orientation, layout, and interconnections are only exemplary and can be expanded and utilized to make standards cells that provide various types of integrated circuit functionality, not just the functionality shown by one particular cell used to describe the definitional positioning, orientation, connections, layouts, and associated functionality.
FIG. 10 shows an example standard cell layout with gate electrode contacts positioned substantially over the diffusion fins, instead of between the diffusion fins, in accordance with some embodiments of the present invention. The example standard cell layout of FIG. 10 also shows variable-width met1 local power structures. In the example standard cell layout of FIG. 10, the contact layer is vertically aligned over the diffusion fins instead of between them. This technique could enable sharing on an abutment edge between diffusion fin structures without a dummy diffusion fin, providing a more efficient layout. It should be understood that a dummy diffusion fin is a diffusion fin that does not form a transistor. Also, it should be appreciated that this technique of vertically aligning the contact layer over the diffusion fins can change the vertical alignment relationship between the men interconnect structures and the diffusion fins.
FIG. 11 shows an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. In the example layout of FIG. 11, the gate electrode layer includes the following features:

    
    
        substantially linear gate electrode structures,
        three or more linear-shaped gate electrode structures on gate electrode layer, two of which are dummies, i.e., gate electrode level structures that do not form a gate electrode of a transistor,
        three or more gate electrode structures on gate electrode layer that have the same vertical dimension (length), i.e., same length in the y direction perpendicular to the lengthwise direction of the diffusion fins (x direction),
        gate electrode structures on gate electrode layer substantially evenly spaced at substantially equal lengthwise centerline-to-lengthwise centerline pitch,
        dummy gate electrode structures shared with adjacent cell on left and/or right, and
        dummy gate electrode structures cut under men power rails.
    
    


In the example layout of FIG. 11, the diffusion fins include the following features:

    
    
        substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments,
        one or more diffusion fins for each of p-type and n-type, FIG. 11 shows two diffusion fins of n-type and two diffusion fins of p-type, but other embodiments can include any number of diffusion fins of either type,
        same number of p-type and n-type diffusion fins, other embodiments may have different number of p-type versus n-type diffusion fins
        one or more diffusion fins omitted under power rails,
        one of more diffusion fins omitted between p-type and n-type sections, and
        each diffusion fin of substantially equal width and length.
    
    


In the example layout of FIG. 11, the local interconnect include the following features:

    
    
        gate electrodes and diffusion fin source/drain connections are on different conductor layers, and these different conductor layers are isolated from each other,
        substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch.
        positive overlap of local interconnect with diffusion fins.
    
    


In the example layout of FIG. 11, the higher level men interconnect layer includes the following features:

    
    
        gate conductor contact between p-type and n-type diffusion fins,
        contacts gridded in both directions,
        contacts connect local interconnect and gate conductors to the metal layer above,
        substantially linear metal; metal on a pitch; metal on a pitch that is same as diffusion fin pitch with half-pitch offset vertically,
        output node and input node pins on same layer,
        wide power rails on top and bottom edges, each shared; power rails connect to left and right by abutment,
        output and input nodes on highest metal level; contacts positioned between p-type and n-type diffusion fins, and
        power rail contacts to local interconnect shared with abutting cells on top and bottom.
    
    


FIGS. 12A/B show a variation of the layout of FIG. 11 having minimum width men power rails, in accordance with some embodiments of the present invention. FIG. 12B shows the same layout as FIG. 12A, with the layout depicted in a merged format for clarity. The example layout of FIGS. 12A/B also has all men of the same width, on the same pitch, including the power rails. Also, in the layout of FIGS. 12/B, met1 is positioned at the same (y) direction locations as the diffusion fin pitch.
FIGS. 13A/13 show a variation of the layout of FIGS. 12A/B that does not have contacts from each of local interconnect and gate electrode structures to met1, in accordance with some embodiments of the present invention. FIG. 13B shows the same layout as FIG. 13A, with the layout depicted in a merged format for clarity. In this embodiment, met1 is formed to directly connect with the local interconnect and gate electrode structures. Also, in other embodiments, either the local interconnect structure, gate electrode structures, or both local interconnect and gate electrode structures can directly connect to met1.
FIGS. 14A/B show a variation of the layout of FIG. 11 having minimum width men power rails, with all men structures of the same width and on the same pitch, including the power rails, in accordance with some embodiments of the present invention. FIG. 14B shows the same layout as FIG. 14A, with the layout depicted in a merged format for clarity.
FIGS. 15A/B show a variation of the layout of FIGS. 14A/B having met1 routing structures populated so each (y) location has a men structure, in accordance with some embodiments of the present invention. FIG. 15B shows the same layout as FIG. 15A, with the layout depicted in a merged format for clarity.
FIG. 15C-1 illustrates an example of a standard cell, in accordance with one embodiment of the present invention. The features depicted in FIG. 15C-1 are exactly the same as the features depicted in FIG. 15A. In this example cell, notations and annotations have been provided to illustrate specific positioning, orientations, relative orientations, relative positioning, and associated methodologies used to define cells for finfet transistors, used in standard cell libraries. In this example illustration, centerlines for metal lines are identified in a leftmost portion of the figure. Each of the metallization centerlines are orientated in a horizontal positioning, or in the X direction corresponding to the +/−X axis.
The finfet transistors of the various types are shown, and identified by the notations described above, such as ft12, ft22, ft11, ft21, etc. Also shown are identification of centerlines along the rightmost side of the example standard cell. The centerline spacings, relative to each of the centerlines, are also shown using identifying arrows. The cell abutment edge is also identified in the cell, for purposes of clarity. As described above, the cell abutment edge defines the location where an adjacent cell will be placed, in an overlapping configuration, such that cell abutment edges overlap each other.
Further noted is that the cells, which are illustrated herein are utilized to make integrated circuits. The integrated circuits are made using the standard cell libraries, where tools are used to select specific cells to match the functionality desired for the integrated circuit. The standard cells, however, will include their defined construction and orientation for the transistors, which in one embodiment follow the methodology defined herein.
FIG. 15D-1 illustrates another example of a standard cell, which may be part of a standard cell library utilized to make integrated circuits, based on a design, layout, or construction defined by a circuit designer. The features depicted in FIG. 15D-1 are exactly the same as the features depicted in FIG. 15A. As shown, additional notations, annotations, descriptions, and identifier lines and arrows have been added to define the various components and placements of the specific features in the cell. At the topmost portion of the cell, illustration is made by identifying the conductive contacting structure (CCS), which may be a contact or a local interconnect structure, or a combination of both a contact and a local interconnect structure. Also, it should be understood that when a CCS is shown as both a contact and a local interconnect structure in a given cell layout, the CCS may be manufactured as either a contact or a local interconnect structure. This CCS illustration/description concept is used through the figures and description provided herein. The cell abutment edge (CAE) is also shown at the topmost portion of the cell and the bottommost portion of the cell. As noted above, the cell abutment edge is used to define the location where an adjacent cell, when placed to define a circuit, will have its corresponding cell abutment edge overlap.
In this example, additional arrows have provided to identify spacings between the cell abutment edge and the FIN centerlines. Also shown are the type 1 FIN widths and the type 2 FIN widths. Further illustrated and pointed out by appropriate arrows are gate level feature (GLF) conductive contacting structure (CCS) features. Also illustrated is, on the left side of the figure, a centerline spacing between the type 1 and type 2 FIN. Further shown, using the guides for the hatching and shading, are the different types of diffusions used in the cell, the gate electrode, the metal, the contacts, the local interconnects vertical (LIV), and other identifying structures. For completeness, illustration of arrows showing the centerline spacing between type 1 FINs and centerline spacing between type 2 FINs are also provided.
Again, the spacings, illustrations, relative positioning, and orientations of the features are provided simply as an example of a cell, which may be a cell that is part of a standard cell library used to make integrated circuits. A resulting circuit can therefore be made into a physical structure, known as a chip. The chip can then be integrated into an integrated circuit, or an electronic device, etc. The electronic device can be in the form of a computing device, a portable device, a mobile device, a computer, a telephone, a digital assistant, a tablet, or any other form of device that can utilize a chip that processes functions or instructions.
FIGS. 16A/13 show a variation of the layout of FIG. 11 having gate electrode structure contacts placed between p-type diffusion fins, in accordance with some embodiments of the present invention. FIG. 16B shows the same layout as FIG. 16A, with the layout depicted in a merged format for clarity. The example layout of FIGS. 16A/B also shows diffusion fins positioned under the men power rails and connected to VSS/VDD. Also, the diffusion fin VDD/VSS structures are shared with the cells above and/or below. For ease of illustration, the contact layer is not shown in the layout of FIGS. 16A/B.
FIGS. 17A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. FIG. 17B shows the same layout as FIG. 17A, with the layout depicted in a merged format for clarity. In the example layout of FIGS. 17A/B, the gate electrode layer includes the following features:

    
    
        substantially linear gate electrode structures,
        three or more linear structures on gate electrode layer, at least two of which are dummies,
        dummy structures on gate electrode layer are of same vertical dimension (length), i.e., same length in the y direction perpendicular to the lengthwise direction of the diffusion fins (x direction),
        structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction,
        dummy structures shared with adjacent cell on left and/or right,
        dummy structures as well as gate electrode structures drawn as a single line and then cut under power rails as well as where needed; gate electrode structure cuts drawn on separate layer; gate electrode layer shown as final result with cuts in FIGS. 17A/B,
        three or more segments of gate electrode, controlling two of more type p-type and n-type transistors,
        multiple gate electrodes structures in the same x location, each connected to a different net; and connected to two different input nets.
    
    


In the example layout of FIGS. 17A/B, the diffusion fins include the following features:

    
    
        substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments,
        one or more diffusion fins for each of p-type and n-type,
        same number of p-type and n-type diffusion fins,
        shared diffusion fins under power rails,
        diffusion fins may or may not be omitted between p-type and n-type sections; FIGS. 17A/B show all fins present,
        each diffusion fin of substantially equal width and length, with the diffusion fin width measured in the y direction and the diffusion fin length measured in the x direction,
        diffusion fins drawn as continuous lines; separate cut mask drawn to separate them into segments; FIGS. 17A/B show diffusion fin segments after separation; it should be understood that in some embodiments the diffusion fin line ends can be drawn in the diffusion fin level layout or formed using the cut mask.
    
    


In the example layout of FIGS. 17A/B, the local interconnect include the following features:

    
    
        gate electrodes and diffusion fin source/drain connections are on different conductor layers; these different conductor layers may be merged during fabrication,
        substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch.
        positive, zero, or negative overlap of local interconnect with diffusion fins,
        direct connection of local interconnect to diffusion fin source/drain and gate electrode structures,
        shared local interconnect under power rail; local interconnect under power rail may be omitted in some embodiments.
    
    


In the example layout of FIGS. 17A/B, the higher level men interconnect layer includes the following features:

    
    
        gate electrode structure contact between diffusion fins,
        contacts gridded in one or both of the x and y directions,
        contacts connect local interconnect and gate conductors to the metal layer above,
        metal locations may be fixed in one or both of x and y directions,
        output node and input node pins on same layer,
        wide power rails on top and bottom are shared; power rails connect to left and right by abutment; power rails contact to local interconnect are shared,
        metal can have bends. In some embodiments, the bends in metal interconnect can be centered between adjacent diffusion fins. Also, in some embodiments, the vertical segments of the metal interconnect that extend in the y direction can be aligned with the vertical local interconnect so as to extend along an over the vertical local interconnect in the y direction.
    
    


FIGS. 18A/B show a variation of the layout of FIGS. 17A/B in which the contacts connect to the horizontal local interconnect, and in which the horizontal local interconnect connects directly to the vertical local interconnect, in accordance with some embodiments of the present invention. FIG. 18B shows the same layout as FIG. 18A, with the layout depicted in a merged format for clarity. In the layout of FIGS. 18A/B, the cuts on diffusion fin, gate electrode, and local interconnect layers are not shown.
FIGS. 19A/B show a variation of the layout of FIGS. 17A/B in which the power rail contact to local interconnect are not shared, and in which there is no shared local interconnect under the power rails, in accordance with some embodiments of the present invention. FIG. 19B shows the same layout as FIG. 19A, with the layout depicted in a merged format for clarity.
FIGS. 20A/B show a variation of the layout of FIGS. 19A/B in which the diffusion fins are offset by a diffusion fin half-pitch with respect to the cell boundary, in accordance with some embodiments of the present invention. FIG. 20B shows the same layout as FIG. 20A, with the layout depicted in a merged format for clarity. The layout of FIGS. 20A/B also includes diffusion fin locations which are the same as the men locations. Also, the diffusion fins are not shared on the top and bottom of the cell. FIGS. 20A/B also show the contacts positioned on the top of the gate electrodes and diffusion fins. FIGS. 20A/B also show different diffusion fin/local interconnect overlaps. It should be understood that in the particular layout of FIGS. 20A/B, although the horizontal local interconnect lih and vertical local interconnect liv are shown to overlap each other in region 2001, the horizontal local interconnect lih and vertical local interconnect liv do not contact each other in region 2001. This is also true for region 2001 in FIGS. 21A/B to follow. However, it should also be understood that in some other layouts, the horizontal local interconnect lih and vertical local interconnect liv can be made to contact each other at locations where they cross each other.
FIGS. 21A/B show a variation of the layout of FIGS. 20A/B having minimum width power rails and negative vertical local interconnect overlap of the diffusion fins, in accordance with some embodiments of the present invention. FIG. 21B shows the same layout as FIG. 21A, with the layout depicted in a merged format for clarity.
FIGS. 22A/B show a variation of the layout of FIGS. 17A/B having minimum width power rails, no shared local interconnect or diffusion fins under the power rails, and a larger space between p-find and n-fins, in accordance with some embodiments of the present invention. FIG. 22B shows the same layout as FIG. 22A, with the layout depicted in a merged format for clarity.
FIGS. 23A/B show a variation of the layout of FIGS. 17A/B, in accordance with some embodiments of the present invention. FIG. 23B shows the same layout as FIG. 23A, with the layout depicted in a merged format for clarity. The layout of FIGS. 23A/B has the following features:

    
    
        uni-directional metal interconnect structures, i.e., linear-shaped metal interconnect structures,
        no shared local interconnect or fins under power rails,
        one input pin on highest metal layer, and another input pin and the output pin on the metal layer below,
        gate electrode contact isolated from local interconnect.
    
    


Also, FIGS. 23A/B show the diffusion fins before they are cut on the left and right edges.
FIGS. 24A/B show a variation of the layout of FIGS. 23A/B, in accordance with some embodiments of the present invention. FIG. 24B shows the same layout as FIG. 24A, with the layout depicted in a merged format for clarity. The layout of FIGS. 24A/B has the following features:

    
    
        diffusion fin pitch smaller than metal pitch; diffusion fin pitch one-half of the metal pitch,
        gate electrode and local interconnect cuts shown between diffusion fins; an alternate implementation can have cuts above diffusion fin cuts; this would reduce number of diffusion fins in one or more transistors,
        one input pin on highest metal layer, another input pin and the output pin on the metal layer below,
        spacing between p-type and n-type diffusion fins larger than minimum; one or more diffusion fins omitted between p-type and n-type diffusion fin sections,
        gate electrode contact placed on diffusion fin,
        local interconnect contact placed on diffusion fin, and
        vertical met2 has a different offset in the x direction within the cell.
    
    


FIGS. 25A/B show a variation of the layout of FIGS. 23A/B, in which the cell is doubled in height, in accordance with some embodiments of the present invention. FIG. 25B shows the same layout as FIG. 25A, with the layout depicted in a merged format for clarity. The layout of FIGS. 25A/B includes twice the total number of diffusion fins in the layout of FIG. 23A/B. The diffusion fin cuts are shown in the layout of FIG. 25A/B.
FIGS. 26A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. FIG. 26B shows the same layout as FIG. 26A, with the layout depicted in a merged format for clarity. In the example layout of FIGS. 26A/B, the gate electrode layer includes the following features:

    
    
        substantially linear gate electrode structures,
        three or more linear structures on gate electrode layer, at least two of which are dummies,
        dummy structures on gate electrode layer are of same dimension,
        structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction,
        dummy structures shared with adjacent cell on left and/or right,
        dummy structures cut under power rails,
        single gate electrode structure controlling two or more p-type and n-type transistors, to be separated later in the manufacturing process to form two or more distinct gate electrodes, such as depicted by gate electrode structures 2601 and 2603,
        gate electrodes in the same x location connected to two or more different nets, connected to two or more different input nets, such as depicted by gate electrode structure 2601 connected to input net 2605, and by gate electrode structure 2603 connected to input net 2607, and
        two or more dummy segments in same x location.
    
    


In the example layout of FIGS. 26A/B, the diffusion fins include the following features:

    
    
        substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments,
        one or more diffusion fins for each of p-type and n-type,
        same number of p-type and n-type diffusion fins,
        one or more diffusion fins omitted under power rails,
        no diffusion fins omitted between p-type and n-type sections,
        each diffusion fin of substantially equal width and length, and
        p-type diffusion fins positioned between n-type diffusion fins, vice-versa.
    
    


In the example layout of FIGS. 26A/B, the local interconnect include the following features:

    
    
        gate electrodes and diffusion fin source/drain connections are on different conductor layers; these different conductor layers are isolated from each other,
        substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch, and
        positive overlap of local interconnect with diffusion fins.
    
    


In the example layout of FIGS. 26A/B, the higher level met1 interconnect layer includes the following features:

    
    
        gate electrode structure contact between diffusion fins,
        contacts gridded in one or both of the x and y directions,
        contacts connect local interconnect and gate conductors to the metal layer above,
        substantially linear-shaped conductor on output node,
        output node and input node pins on different layers,
        power rail in middle, opposite power rail at top and bottom; top and bottom power rails shared; all power rails connect to left and right by abutment, and
        output node on highest metal level.
    
    


FIGS. 27A/B show a variation of the layout of FIGS. 26A/B, in accordance with some embodiments of the present invention. FIG. 27B shows the same layout as FIG. 27A, with the layout depicted in a merged format for clarity. The layout of FIGS. 27A/B includes the following features:

    
    
        gate conductor is drawn with a cut layer, such as a cut layer that includes the cut shape 2701,
        two gate conductor segments at same x location, each connecting to a different net, each connected to an input net, each controlling a p-type and an n-type transistor constructed with multiple fins, such as gate conductors 2703 and 2705, and
        one input pin on highest metal layer, another input pin and the output pin on the metal layer below.
    
    


FIGS. 28A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. FIG. 28B shows the same layout as FIG. 28A, with the layout depicted in a merged format for clarity. In the example layout of FIGS. 28A/B, the gate electrode layer includes the following features:

    
    
        substantially linear gate electrode structures,
        three or more linear structures on gate electrode layer, at least two of which are dummies,
        three or more gate electrode structures are of same dimension,
        structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction,
        dummy structures shared with adjacent cell on left and/or right,
        dummy structures cut under power rails,
    
    


It should be understood that any of the figures presented herein, including the example layout of FIGS. 28A/B, can have the type 1 diffusion fins defined as p-type diffusion fins and the type 2 diffusion fins defined as n-type diffusion fins, or can have the type 1 diffusion fins defined as n-type diffusion fins and the type 2 diffusion fins defined as p-type diffusion fins, depending on the particular implementation embodiment. In the example layout of FIGS. 28A/B, the diffusion fins include the following features:

    
    
        substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments,
        one or more diffusion fins for each of p-type and n-type,
        different number of p-type and n-type diffusion fins,
        one or more diffusion fins omitted under power rails,
        one or more diffusion fins omitted between p-type and n-type sections,
        each diffusion fin of substantially equal width and length.
    
    


In the example layout of FIGS. 28A/B, the local interconnect include the following features:

    
    
        gate electrodes and diffusion fin source/drain connections are directly from a conductor layer,
        substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch,
        zero or negative overlap of local interconnect with diffusion fins and gate electrode structures,
        local interconnect can be constructed in two steps, vertical local interconnect structures first, followed by horizontal local interconnect structures; each of the steps creates a set of linear, uni-directional local interconnect structures, and
        alternatively, two separate local interconnect layers—one vertical local interconnect layer, and one horizontal local interconnect layer.
    
    


In the example layout of FIGS. 28A/B, the higher level met1 interconnect layer includes the following features:

    
    
        diffusion fins can be positioned underneath the power rails
        contacts gridded in one or both of the x and y directions,
        contacts connect all local interconnects to the metal layer above, and
        contacts can be placed anywhere.
    
    


FIG. 28C-1 illustrates a standard cell, or a cell that may be part of a cell library that is utilized to make an integrated circuit. The features depicted in FIG. 28C-1 are exactly the same as the features depicted in FIG. 28A. In this example, identification pointers and dash-marks are provided to show features of the standard cell. At the leftmost portion of the figure, centerline locations are marked for the various FINS, such as 1st (first) FIN location centerline to 11th (eleventh) FIN location centerline. At the topmost portion of the figure, the FIN conductive contacting structure (CCS) 2 and 4 are identified, along with ft12 (finfet 1 of a second type) and ft22 (finfet 2 of a second type). At the bottom of the cell, the FIN CCS 1 and 3 are identified, along with ft11 (finfet 1 of a first type) and ft21 (finfet 2 of a first type). At the right most portion of the cell, identifying arrows are provided showing the spacings between the type 1 FIN centerlines and the spacings between the type 2 FIN centerlines. Further shown and illustrated by the example arrow, is the spacing between type 1 and type 2 FIN centerlines. For completeness, the 1st (first) and the 2nd (second) GLF CCS features are shown extending to the gate electrode features, which run vertically, or in the Y direction corresponding to the +/−Y axis, or up/down directions.
FIGS. 29A/B show a variation of the layout of FIGS. 28A/B in which there are no local interconnect structures present between two gate electrode structures of n-type transistors, in accordance with some embodiments of the present invention. FIG. 29B shows the same layout as FIG. 29A, with the layout depicted in a merged format for clarity.
FIGS. 30A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. FIG. 30B shows the same layout as FIG. 30A, with the layout depicted in a merged format for clarity. In the example layout of FIGS. 30A/B, the gate electrode layer includes the following features:

    
    
        substantially linear gate electrode structures,
        three or more linear structures on gate electrode layer, at least two of which are dummies,
        three or more gate electrode structures are of same dimension,
        structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction,
        dummy structures shared with adjacent cell on left and/or right,
        dummy structures cut under power rails,
    
    


In the example layout of FIGS. 30A/B, the diffusion fins include the following features:

    
    
        substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments,
        one or more diffusion fins for each of p-type and n-type,
        same number of p-type and n-type diffusion fins,
        one or more diffusion fins omitted under power rails,
        one or more diffusion fins omitted between p-type and n-type sections,
        each diffusion fin of substantially equal width and length.
    
    


In the example layout of FIGS. 30A/B, the local interconnect include the following features:

    
    
        gate electrodes and diffusion fin source/drain connections are directly from a conductor layer,
        substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch,
        zero or negative overlap of local interconnect with diffusion fins and gate electrode structures,
        local interconnect can be constructed in two steps, vertical local interconnect structures first, followed by horizontal local interconnect structures; each of the steps creates a set of linear, uni-directional local interconnect structures, and
        in some embodiments, vertical and horizontal local interconnect structures can be formed to cross and connect with each other, thereby forming a two-dimensionally varying local interconnect structure, i.e., a local interconnect structure with bends,
        alternatively, two separate local interconnect layers—one vertical local interconnect layer, and one horizontal local interconnect layer.
    
    


In the example layout of FIGS. 30A/B, the higher level met1 interconnect layer includes the following features:

    
    
        diffusion fins can be positioned underneath the power rails
        contacts gridded in one or both of the x and y directions,
        met1 interconnect structures are positioned in accordance with same pitch as gate electrode structures,
        contacts connect all local interconnects to the metal layer above, and
        contacts can be placed anywhere.
    
    


FIG. 30C-1 illustrates the example FIN centerlines (CL) along the leftmost portion of the cell, in accordance with one embodiment of the present invention. The features depicted in FIG. 30C-1 are exactly the same as the features depicted in FIG. 30A. It should be understood that the identifying arrows, dash lines and pointers are used to facilitate identification of the structures shown in the cell, the relative position of the features, the specific positioning of the spacings, interconnections, etc. At the leftmost portion of the cell, example positioning for 1st (first) FIN centerline location to 14th (fourteenth) FIN centerline location, are shown. At the rightmost portion of the cell, the example spacings between the type 1 FIN centerlines are shown, as well as the example spacings between the type 2 FIN centerlines. The example spacing between type 1 and type 2 FIN centerlines are also shown. FIG. 30C-1 also identifies the cell circuit as including an equal number of FINs of each type, use of different FIN pitches, use of different spacings between FINs of different types, and use of different spacings between cell abutment edges (CAE) and FINS, among other features. FIG. 30C-1 also highlights use of conductive contacting structures (CCS) and their relationships to each other and to other features within the cell circuit.
FIG. 31A shows an example sdff cell layout with gate electrode and local interconnect line end gaps centered substantially between diffusion fins, in accordance with some embodiments of the present invention. In FIG. 31A, the gate electrode line end gaps are circled. FIG. 31B shows the example sdff cell layout of FIG. 31A, with the local interconnect line end gaps centered substantially between the diffusion fins circled. Based on FIGS. 31A through 31B, it should be understood that a cell library architecture can be generated in which all gate electrode and vertical interconnect line end gaps are centered substantially between the diffusion fins. FIG. 31C shows the example sdff cell layout of FIGS. 31A and 31B with annotation of the region 3105 between two adjacent gate electrode structures in which the diffusion fin ends overlap each other in the x direction, in accordance with some embodiments of the present invention.
FIGS. 32-34 show three examples of a part of a standard cell circuit layout, in accordance with some embodiments of the present invention. FIG. 32 shows an example layout in which all contact layer structures are placed between the diffusion fins. FIGS. 33 and 34 shows example layouts in which all contact layer structures are placed on the diffusion fins. In the example of FIG. 32, the gate electrode line end gaps in some instances are substantially centered over the diffusion fins, as noted by circles 3201, and in some instances the gate electrode line end gaps are substantially centered between the diffusion fins, as noted by circles 3203. By using a cell architecture that places all of the contact layer structures over the diffusion fins, all gate electrode line end gaps can be substantially centered between the diffusion fins, as noted by circles 3301 in FIGS. 33 and 34. One benefit here is that the gate electrode line end gaps are all on a fixed pitch. From a manufacturing perspective, it does not matter whether the gate electrode line end gaps are centered on the diffusion fins or between the diffusion fins. However, it does matter that the gate electrode line end gaps are not mixed, as in the example of FIG. 32. Having the gate electrode line end gaps all on the same pitch should result in a gate electrode manufacturing process that is either less expensive, more reliable or both.
FIGS. 35A-69A show various cell layouts which demonstrate examples of different ways in which a cross-coupled transistor configuration can be implemented using finfet transistors. The cross-couple layouts of FIGS. 35A-69A are shown in the context of a two-input multiplexor circuit (MUX2). FIG. 35C shows a circuit schematic of the layouts of FIGS. 35A/B through 47A/B and 63A/B through 67A/B, in accordance with some embodiments of the present invention.
FIG. 43C-1 illustrates another example, of a standard cell or cells, that may be part of a standard cell library, in accordance with one embodiment of the present invention. The features depicted in FIG. 43C-1 are exactly the same as the features depicted in FIG. 43A. In this illustration, the centerline for the FINs 1-13 are shown on the leftmost side of the figure. The topmost side of the figure shows the centerlines for the gate level features (GLFs). At the rightmost portion of the figure, the spacings for the FIN centerlines 1-12 are illustrated. Also shown is an example dummy FIN centerline. The bottommost portion of the cell illustrates the GLF centerlines spacings for the 1st (first) through the 8th (eighth) GLFs. As noted above, the example centerlines, spacings, positionings, relative positioning of the features shown in the cell, are exemplary for a specific type of cell and the logic/circuit-logic that the cell defines. The construction of the specific spacings, orientations, and methodology used to define the position can apply to any cell, whether the cell is part of a cell library or not, and can flexibly be applied to any standard cell, whether the standard cell uses finfets or regular transistors (i.e., non-finfet transistors).
FIG. 43D-1 illustrates additional features associated with a cell, which may be part of a standard cell library, in accordance with one embodiment of the present invention. The features depicted in FIG. 43D-1 are exactly the same as the features depicted in FIG. 43A. In this example, specific identification of features that define finfets ft12, ft22, ft32, ft42, ft52, ft62, ft11, ft21, ft31, ft41, ft51, ft61, are identified. Also shown in the cell, are exemplary electrical connections. The electrical connections, for purposes of clarity are shown by the heavy dashed lines. It should be understood that the heavy dashed lines simply identify where the electrical connections will occur, such as by other interconnect metallization and vias. The interconnect metallization may be formed on various layers, which are not shown in this figure, but defined in the various layers above the illustrated features of the cell. The interconnect layers of a cell, define the final interconnections that define the transistor and logic connections used to make a circuit, and that circuit can be defined from a plurality of cells, which ultimately are defined into an integrated circuit chip that is integrated into a physical electronic device.
FIG. 43E-1 illustrates additional features of a cell, which may be part of the cell of a cell library, in accordance with one embodiment of the present invention. The features depicted in FIG. 43E-1 are exactly the same as the features depicted in FIG. 43A. In this example, notations are provided to identify the various GLF features, the GLF CCS features, the relative position of the features, such as the positioning of the GLF CCS positions, the common node electrical connections, the CCS overlap11 of GLF, the CCS overlap13 of GLF, the GLF overlap 22 of CCS, the CCS overlap 12 of GLF, etc. Also shown are the ft31 to ft42 electrical connection, the GLF ends aligned, the 1st (first) CS end alignment position and other features, positioning, relative positionings, orientations, alignments, abutments, electrical connections, and relative orientations.
FIG. 45C-1 illustrates additional identifying information, such as the FIN centerlines, the GLF centerlines, the GLF centerline spacings, etc. The features depicted in FIG. 45C-1 are exactly the same as the features depicted in FIG. 45A. Further shown is a dummy FIN centerline, and the centerlines for the FINS 1st (first)-6th (sixth). The centerline spacings between the centerlines are also illustrated.
FIG. 46C-1 illustrates an example where a cell, of a standard cell library, defines the various positionings of the FIN centerlines, and the centerline spacings. The features depicted in FIG. 46C-1 are exactly the same as the features depicted in FIG. 46A. The relative positioning, orientations, and alignments are illustrated as one example, and may be applied to any standard cell or cell that is used in the making of an integrated circuit.
FIG. 46D-1 illustrates an example of a cell, which may be used in a standard cell library, in accordance with one embodiment of the present invention. The features depicted in FIG. 46D-1 are exactly the same as the features depicted in FIG. 46A. In this illustration, notations are provided to identify the specific finfets of the 1st (first) type and the 2nd (second) type. In the illustration, finfets ft12, ft22, ft32, ft42, ft52, and ft62 define finfet transistors of the 2′′ type. Finfets ft11, ft21, ft31, ft41, ft51, and ft61 define finfet transistors of the 1st (first) type. The electrical connections are shown as identified by the heavy dashed lines. These identifying heavy dashed lines define where the electrical connections will be made, in a resulting integrated circuit.
FIG. 46E-1 illustrates additional annotations and identifying arrows and boxes, that describe the position and relative positions of the features in a cell, of a standard cell library, in accordance with one embodiment of the present invention. The features depicted in FIG. 46E-1 are exactly the same as the features depicted in FIG. 46A. In this illustration, at the topmost portion of the cell an identifying box and arrow points to a conductive segment (CS) that forms gate electrodes of a cross-couple finfet transistors (xcouple xtor/s) of only one type and that extends next to finfets transistors of opposite types. Additional notations were also provided regarding the GLF features, the CCS features and overlaps to GLFs, the alignments to specific features, the common node electrical connection, the CCS overlaps to GLFs, the alignment positions for ends, etc. It should be noted again that the identifying features shown in the cell are only exemplary, but do define relative positionings and orientations of specific features, separations, centerlines, centerline spacings, spacings between centerlines, and general orientation of features. The features are also identified by the illustrated hatching and guide provided in the figure.
FIG. 46F-1 illustrates additional notations, positionings, relative positionings, and interconnections for the finfet transistors of a cell, in accordance with one embodiment of the present invention. The features depicted in FIG. 46F-1 are exactly the same as the features depicted in FIG. 46A. As shown in the topmost and lowermost portions of the cell, are identifiers for example FIN CCS 2nd (second)-FIN CCS 14th (fourteenth). At the leftmost portion of the cell is illustrated the FIN overlap 2 of CCS, the FINs connecting between 6th (sixth) and 8th (eighth) FIN CCSs, the FIN edges coincident with CCS, the CCS overlap1 of FIN, the 1st (first) FIN CCS, the ft31 to ft42 electrical connection, etc. The common node electrical connection is also illustrated, as well as the FINs connecting between 9th (ninth) and 11th (eleventh) FIN CCSs. These example interconnections, positioning, orientations, and connections, are shown as an example. The cells defined using this methodology and structure, can be used to define efficient layouts for integrated circuits made using the defined cells. Integrated circuits, as noted above, may be defined in the form of integrated circuit chips. The integrated circuit chips are fabricated using the layouts that follow example constructions defined by the orientations, positioning, and interconnections shown in the example figures. Also, as shown in FIG. 46F-1, the number of FINs used in making a given FIN connection can vary in different embodiments, and at different locations through a given cell circuit. For example, FIG. 46F-1 highlights the use of multiple FINs to make an electrical connection by the heavy dashed lines extending along the multiple FINs between the 6th FIN CCS and the 8th FIN CCS. This illustration concept for use of multiple FINs to make a given electrical connection is used in numerous places throughout figures described herein.
FIG. 46F-2 illustrates an example cell, which may be part of a cell library, that may be used to make an integrated circuit. The features depicted in FIG. 46F-2 are exactly the same as the features depicted in FIG. 46A. The cell, in this illustration shows various notations associated with the FIN CCS 1st (first)-14th (fourteenth). The example also shows a uniformity extending portion (UEP), such as UEP 1, UEP 2, and UEP 3. In this example, the uniformity extending portions are provide an increase in structure regularity across the cell to improve fabrication of the circuit, such as by improving lithographic resolution of cell features during fabrication.
FIG. 48C shows a circuit schematic of the layouts of FIGS. 48A/B through 58A/B, in accordance with some embodiments of the present invention. FIG. 59C shows a circuit schematic of the layout of FIGS. 59A/B, in accordance with some embodiments of the present invention. FIG. 60C shows a circuit schematic of the layouts of FIGS. 60A/B through 62A/B and FIGS. 68A/B through 69A/B, in accordance with some embodiments of the present invention. FIG. 71C shows a circuit schematic of the layouts of FIGS. 71A/B and 77A/B, in accordance with some embodiments of the present invention. FIG. 72C shows a circuit schematic of the layouts of FIGS. 72A/B through 76A/B, in accordance with some embodiments of the present invention. The transistors on the left and right edges are added to the cross-couple to achieve MUX2 functionality. For other functions with cross-couple circuits, these may be different. FIGS. 35B-69B show the same layouts as FIGS. 35A-69A, respectively, with the layouts depicted in a merged format for clarity, and with the nodes of the circuit identified based on the cell layout's circuit schematic. Also, cross-coupled transistor connections are identified in FIGS. 35A-69A by lines cc1 and cc2.
FIGS. 35A/B through 47A/B and 63A/B through 67A/B show cross-couple transistor configurations having transmission gate in both logic paths, requiring all the internal nodes to have a connection between p-type and n-type. FIGS. 48A/B through 57A/B show cross-couple transistor configurations having transmission gate in the logic path with larger transistors, and tristate gate in other paths. Tristate gate does not require a connection between p-type diffusion and n-type diffusion on the internal node.
FIGS. 58A/B through 59A/B show cross-couple transistor configurations having transmission gate in the logic path with smaller transistors, and tristate gate in other paths. Tristate gate does not require a connection between p-type diffusion and n-type diffusion on the internal node.
FIGS. 60A/B through 62A/B and 68A/B through 69A/B show cross-couple transistor configurations having tristate gate in both logic paths.
FIGS. 63A/B through 69A/B show cell layouts that have a number of p-type diffusion fins equal to a number of n-type diffusion fins. Some of the other FIGS. 35A/B through 62A/B show cell layouts that a number of p-type diffusion fins not equal to a number of n-type diffusion fins.
FIGS. 40A/B shows a cell layout that utilizes tighter spacing between horizontal/vertical local interconnect structures. FIGS. 37A/B, 45A/B, and 49A/B show cell layout examples that utilize a larger spacing between diffusion fins. FIGS. 63A/B through 69A/B show cell layout examples that utilize tighter spacing between diffusion fins. FIGS. 43A/B and 44A/B show cell layout examples that utilize a diffusion fin as a wire.
FIGS. 35A/B through 41A/B, 48A/B through 65A/B, and 68A/B through 69A/B shows cell layout examples that utilize a dense gate electrode structure implementation without split gates. FIGS. 42A/B through 47A/B and 66A/B through 67A/B show cell layout examples that utilize a split gate implementation with less wiring and larger transistor sizes.
FIGS. 35A/B through 69A/B show cell layout examples that demonstrate a number of different wiring examples for various cell layouts. FIGS. 35A/B through 69A/B show cell layout examples that demonstrate use of a fully populated gate electrode layer, including extension of gate electrode end caps and use of dummy structures where possible within the gate electrode layer. Some of the cell layouts shown in FIGS. 35A/B through 69A/B show examples of dummy gate electrode layer structures without the cuts at the top and bottom of the cell, i.e., prior to cut mask operation during the fabrication process. Some of the cell layouts, e.g., FIGS. 53A/B through 55A/B and 66A/B shows example cell layouts where power buses are omitted.
These cross-coupled transistor configuration of FIGS. 35A/B through 69A/B include structures formed on each layer as well as on a combination of layers, and many of the cell layout features mentioned above can be applied independent of each other. It should be understood that the cell layouts of FIGS. 35A/B through 69A/B show examples of what can be done with the finfet-based cross-coupled transistor configuration, and in no way represent an all inclusive set of possible cell layout configurations. Any of the features demonstrated in the various cell layout examples of FIGS. 35A/B through 69A/B can be combined to generate additional cell layouts.
Technologies for which the optical resolution is not sufficient to resolve line patterns directly will use some form of pitch division. The pitch division can be self-aligned, using spacers, or through multiple exposure steps at an achievable resolution. For example, for an ArF excimer laser scanner using water immersion of the final lens and a portion of the wafer to be exposed, the optical resolution is limited to  ̃40 nm. This corresponds to a k1 value of 0.28 for a wavelength of 193 nm and an effective numerical aperture of 1.35. For diffusion fin layers and gate electrode layers and other layers formed with pitch division (for example, spacer double patterning, spacer quadruple patterning, multiple exposure Litho-Etch-Litho-Etch, etc. . . . ), even though the layout is done with uniform pitches (lengthwise centerline-to-lengthwise centerline pitches) for the conductive structures, i.e., for the lines, the as-fabricated conductive structures can end up slightly off target due to processing variations, such that multiple (e.g., two, four, etc. . . . ) pitches end up on the wafer.
Pitch division can be applied multiple times, for example pitch-division-by-2, pitch-division-by-4, with either the self-aligned spacer approach or multiple lithographic exposures. Pitch-division-by-4 has been reported to achieve lines/spaces of about 11 nm. One limitation of pitch division is that the resultant line patterns can have slightly different pitches within a pattern. For pitch-division-by-2, this means that groups of two lines will have one pitch, the next group of two lines can have a slightly different pitch, the next group of two lines will have the same pitch as the first group, etc. The result on a finished wafer will be lines which were intended to be on a uniform, fixed pitch but will end up on two or four or other multiple pitches. For self-aligned spacers, the original core line pattern will be drawn on a fixed, uniform pitch. For multiple exposures, each of the exposures will have lines drawn on a uniform fixed pitch. The non-uniform pitch introduced by the pitch division process may be on the order of 10% or less of the final pitch. For example, for a final target pitch of 50 nm, the pitches of each group of two lines may differ by less than 5 nm.
Restricted Gate Level Layout Architecture
The various circuit layouts incorporating finfet transistors, as discussed above, can be implemented within a restricted gate level layout architecture. For the gate level, a number of parallel virtual lines are defined to extend across the layout. These parallel virtual lines are referred to as gate electrode tracks, as they are used to index placement of gate electrodes of various transistors within the layout. In some embodiments, the parallel virtual lines which form the gate electrode tracks are defined by a perpendicular spacing therebetween equal to a specified gate electrode pitch. Therefore, placement of gate electrode segments on the gate electrode tracks corresponds to the specified gate electrode pitch. In another embodiment, the gate electrode tracks can be spaced at variable pitches greater than or equal to a specified gate electrode pitch.
FIG. 70A shows an example of gate electrode tracks 70-1A through 70-1E defined within the restricted gate level layout architecture, in accordance with some embodiments of the present invention. Gate electrode tracks 70-1A through 70-1E are formed by parallel virtual lines that extend across the gate level layout of the chip, with a perpendicular spacing therebetween equal to a specified gate electrode pitch 70-3.
Within the restricted gate level layout architecture, a gate level feature layout channel is defined about a given gate electrode track so as to extend between gate electrode tracks adjacent to the given gate electrode track. For example, gate level feature layout channels 70-5A through 70-5E are defined about gate electrode tracks 70-1A through 70-1E, respectively. It should be understood that each gate electrode track has a corresponding gate level feature layout channel. Also, for gate electrode tracks positioned adjacent to an edge of a prescribed layout space, e.g., adjacent to a cell boundary, the corresponding gate level feature layout channel extends as if there were a virtual gate electrode track outside the prescribed layout space, as illustrated by gate level feature layout channels 70-5A and 70-5E. It should be further understood that each gate level feature layout channel is defined to extend along an entire length of its corresponding gate electrode track. Thus, each gate level feature layout channel is defined to extend across the gate level layout within the portion of the chip to which the gate level layout is associated.
Within the restricted gate level layout architecture, gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with the given gate electrode track. A contiguous gate level feature can include both a portion which defines a gate electrode of a transistor, i.e., of a finfet transistor as disclosed herein, and a portion that does not define a gate electrode of a transistor. Thus, a contiguous gate level feature can extend over both a diffusion region, i.e., diffusion fin, and a dielectric region of an underlying chip level.
In some embodiments, each portion of a gate level feature that forms a gate electrode of a transistor is positioned to be substantially centered upon a given gate electrode track. Furthermore, in this embodiment, portions of the gate level feature that do not form a gate electrode of a transistor can be positioned within the gate level feature layout channel associated with the given gate electrode track. Therefore, a given gate level feature can be defined essentially anywhere within a given gate level feature layout channel, so long as gate electrode portions of the given gate level feature are centered upon the gate electrode track corresponding to the given gate level feature layout channel, and so long as the given gate level feature complies with design rule spacing requirements relative to other gate level features in adjacent gate level layout channels. Additionally, physical contact is prohibited between gate level features defined in gate level feature layout channels that are associated with adjacent gate electrode tracks.
FIG. 70B shows the exemplary restricted gate level layout architecture of FIG. 70A with a number of exemplary gate level features 7001-7008 defined therein, in accordance with some embodiments of the present invention. The gate level feature 7001 is defined within the gate level feature layout channel 70-5A associated with gate electrode track 70-1A. The gate electrode portions of gate level feature 7001 are substantially centered upon the gate electrode track 70-1A. Also, the non-gate electrode portions of gate level feature 7001 maintain design rule spacing requirements with gate level features 7002 and 7003 defined within adjacent gate level feature layout channel 70-5B. Similarly, gate level features 7002-7008 are defined within their respective gate level feature layout channels, and have their gate electrode portions substantially centered upon the gate electrode track corresponding to their respective gate level feature layout channel. Also, it should be appreciated that each of gate level features 7002-7008 maintains design rule spacing requirements with gate level features defined within adjacent gate level feature layout channels, and avoids physical contact with any another gate level feature defined within adjacent gate level feature layout channels.
A gate electrode corresponds to a portion of a respective gate level feature that extends over a diffusion structure, i.e., over a diffusion fin, wherein the respective gate level feature is defined in its entirety within a gate level feature layout channel. Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel. As illustrated by the example gate level feature layout channels 70-5A through 70-5E of FIG. 70B, each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary.
Some gate level features may have one or more contact head portions defined at any number of locations along their length. A contact head portion of a given gate level feature is defined as a segment of the gate level feature having a height and a width of sufficient size to receive a gate contact structure. In this instance, “width” is defined across the substrate in a direction perpendicular to the gate electrode track of the given gate level feature, and “height” is defined across the substrate in a direction parallel to the gate electrode track of the given gate level feature. The gate level feature width and height may or may not correspond to the cell width W and cell height H, depending on the orientation of the gate level features within the cell. It should be appreciated that a contact head of a gate level feature, when viewed from above, can be defined by essentially any layout shape, including a square or a rectangle. Also, depending on layout requirements and circuit design, a given contact head portion of a gate level feature may or may not have a gate contact defined thereabove.
A gate level of the some embodiments disclosed herein is defined as a restricted gate level, as discussed above. Some of the gate level features form gate electrodes of transistor devices. Others of the gate level features can form conductive segments extending between two points within the gate level. Also, others of the gate level features may be non-functional with respect to integrated circuit operation. It should be understood that the each of the gate level features, regardless of function, is defined to extend across the gate level within their respective gate level feature layout channels without physically contacting other gate level features defined with adjacent gate level feature layout channels.
In some embodiments, the gate level features are defined to provide a finite number of controlled layout shape-to-shape lithographic interactions which can be accurately predicted and optimized for in manufacturing and design processes. In this embodiment, the gate level features are defined to avoid layout shape-to-shape spatial relationships which would introduce adverse lithographic interaction within the layout that cannot be accurately predicted and mitigated with high probability. However, it should be understood that changes in direction of gate level features within their gate level layout channels are acceptable when corresponding lithographic interactions are predictable and manageable.
It should be understood that each of the gate level features, regardless of function, is defined such that no gate level feature along a given gate electrode track is configured to connect directly within the gate level to another gate level feature defined along a different gate electrode track without utilizing a non-gate level feature. Moreover, each connection between gate level features that are placed within different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, which may be defined in higher interconnect levels, i.e., through one or more interconnect levels above the gate level, or by way of local interconnect features at or below the gate level.
FIGS. 71A/B through 77A/B show a number of example SDFF circuit layouts that utilize both tri-state and transmission gate based cross-coupled circuit structures, in accordance with some embodiments of the present invention. FIG. 71C shows a circuit schematic for FIGS. 71A/B and 77A/B, in accordance with some embodiments of the present invention. FIG. 72C shows a circuit schematic for FIGS. 73A/B through 76A/B, in accordance with some embodiments of the present invention. FIGS. 71B-77B show the same layouts as FIGS. 71A-77A, respectively, with the layouts depicted in a merged format for clarity, and with the nodes of the circuit identified based on the cell layout's circuit schematic. The example SDFF circuit layouts of FIGS. 71A/B through 77A/B include the following features:
1. Gate conductors:

    
    
        a. Substantially evenly spaced gate conductors.
        b. Uniform gate conductor line end gaps formed with cut mask, combined with large gate conductor line end gaps to avoid local interconnect, or if there is sufficient space to permit larger gate conductor line end gaps that do not require cuts.
        c. Some gate conductors used as wires in some instances to reduce metal usage, i.e., to reduce higher level interconnect usage.
    
    


2. Diffusion fins:

    
    
        a. Substantially evenly spaced diffusion fins.
        b. Diffusion fins omitted between p-type and n-type, and on top and bottom cell edges.
        c. Diffusion fin width-to-space relationship may vary, or may have a substantially equal relationship such as depicted in the examples of FIGS. 71A/B through 77A/B.
    
    


3. Local interconnect:

    
    
        a. Local interconnect structures can connect directly to diffusion fins and gate conductors.
        b. Local interconnect structures can connect to metal 1 (met 1 or M1) through a contact layer.
        c. Horizontal and vertical local interconnect structures, such as shown in FIGS. 76A/B by way of example, can be fabricated using separate design layers, i.e., fabricated using separate mask layers.
        d. Horizontal and vertical local interconnect structures can be on the same layer, i.e., on the same mask layer, as shown in the examples of FIGS. 71A/B through 75A/B and 77A/B. Also, during manufacturing, the horizontal and vertical local interconnect structures can be fabricated in two distinct steps, or in a single step.
        e. Local interconnect structures can have positive, zero, or negative overlap with diffusion fins and gate conductors.
        f. Vertical local interconnect can be on similar pitch as gate conductor with half-pitch offset from gate conductors.
    
    


4. Contacts:

    
    
        a. Contacts can be defined to connect local interconnect structures to metal 1 (met1 or M1).
        b. Local interconnect structures can have positive, zero, or negative overlap on contact.
        c. Metal 1 (met1 or M1) can have positive, zero, or negative overlap on contact.
        5. Metal 2 (met2 or M2)
        a. Metal 2 structures can be uni-directional, i.e., linear-shaped, in some embodiments.
        b. Metal 2 structures can extend in horizontal (x) and/or vertical (y) directions.
    
    


The example SDFF circuit layout of FIGS. 71A/B shows the following features, among others:

    
    
        Metal 2 is not used for internal wiring.
        Metal 2 is used for power rails.
        Tri-state and transmission gate cross-coupled transistor structures are utilized.
        Local interconnect structures extend in both horizontal (x) and vertical (y) directions.
        Some gate conductors are used as wires, and do not form a gate electrode of a transistor.
        Gate conductor cuts are provided in various locations and combinations.
        Gate conductor cuts are uniform in size.
        Gate conductor layer is fully populated, i.e., at least one gate conductor is positioned at each available gate conductor pitch position within the cell.
    
    


The example SDFF circuit layout of FIGS. 72A/B shows the following features, among others:

    
    
        Metal 2 structures are used for internal wiring in vertical (y) direction.
        Denser circuit layout than the example of FIGS. 71A/B.
        Both tri-state and transmission gate cross-coupled transistor structures are utilized.
        Gate conductor layer is fully populated, i.e., at least one gate conductor is positioned at each available gate conductor pitch position within the cell.
        Gate conductor cuts are shown.
        Substantially uniform gate conductor cuts are utilized in various combinations and/or locations to optimize layout.
    
    


The example SDFF circuit layout of FIGS. 73A/B shows a version of the SDFF circuit that uses both the gate conductor and metal 2 layers for vertical (y-direction) wiring. The example SDFF circuit layout of FIGS. 74A/B shows a version of the SDFF circuit that uses horizontally oriented, i.e., in the x-direction, metal 2 structures for internal wiring. The example SDFF circuit layout of FIGS. 75A/B shows an alternate version of the SDFF circuit that again uses horizontally oriented, i.e., in the x-direction, metal 2 structures for internal wiring. The example SDFF circuit layout of FIGS. 76A/B shows a variation of the layout of FIG. 72A/B with horizontal local interconnect and vertical local interconnect used as separate conductors to allow for removal of the internal metal 2 conductors. The example SDFF circuit layout of FIGS. 77A/B shows a partial SDFF layout illustrating an alternate way to define circuit structures so as to minimize use of metal 2 and maximize transistor density.
It should be understood based on the circuit layouts and description provided herein that in some embodiments one or more of the following features can be utilized:

    
    
        a separation distance between co-aligned and adjacently positioned diffusion fin ends (i.e., diffusion fin cut distance) can be less than a size of the gate electrode pitch,
        a vertical local interconnect structure may overlap a diffusion fin (that is horizontally oriented) on one edge (horizontally oriented edge) of the diffusion fin; in this case, some cuts (in a cut mask) used to separate vertical local interconnect structures can be defined to touch or overlap a diffusion fin,
        a horizontal local interconnect structure may overlap a gate electrode structure (that is vertically oriented) on one edge (vertically oriented edge) of the gate electrode structure,
        a size of a gate end cap (i.e., a distance by which a gate electrode structure extends beyond an underlying diffusion fin) can be less than a size of one or more diffusion fin pitches, or less than a size of an average diffusion fin pitch,
        a separation distance between co-aligned and adjacently positioned gate electrode structure ends (i.e., gate electrode structure cut distance) can be less than or equal to a size of one or more diffusion fin pitches, or less than a size of an average diffusion fin pitch,
        a lengthwise centerline separation distance between adjacently positioned n-type and p-type diffusion fins (as measured in the direction perpendicular to the diffusion fins) can be defined as an integer multiple of one or more diffusion fin pitches, or as an integer multiple of an average diffusion fin pitch.
    
    


In an example embodiment, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is structured to project from a surface of the substrate. The first diffusion fin is structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is structured to project from the surface of the substrate. The second diffusion fin is structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Also, either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.
The above-mentioned first and second transistors can be located at different positions in the second direction. Also, each of the first and second transistors can be a three-dimensionally gated transistor.
The above-mentioned first transistor includes a first linear-shaped gate electrode structure that extends lengthwise in a second direction perpendicular to the first direction as viewed from above the substrate. The above-mentioned second transistor includes a second linear-shaped gate electrode structure that extends lengthwise in the second direction perpendicular to the first direction as viewed from above the substrate. At least one of the first and second ends of the first diffusion fin can be positioned in the first direction between the first and second linear-shaped gate electrode structures. And, at least one of the first and second ends of the second diffusion fin can be positioned in the first direction between the first and second linear-shaped gate electrode structures. The first linear-shaped gate electrode structure is positioned next to and spaced apart from the second linear-shaped gate electrode structure.
The semiconductor device can also include a linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. The linear-shaped local interconnect structure can be substantially centered in the first direction between the first and second linear-shaped gate electrode structures. The linear-shaped local interconnect structure can connect to one or more of the first and second diffusion fins.
The semiconductor device can also include a linear-shaped local interconnect structure that extends in the first direction and that is positioned between the first and second diffusion fins. This linear-shaped local interconnect structure can be substantially centered in the second direction between the first and second diffusion fins. Also, this linear-shaped local interconnect structure can connect to one or more of the first and second gate electrode structures.
The above-mentioned linear-shaped local interconnect structure that extends in the first direction can be referred to as a first linear-shaped local interconnect structure. The semiconductor device can also include a second linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. The second linear-shaped local interconnect structure can be substantially centered in the first direction between the first and second linear-shaped gate electrode structures. Also, the second linear-shaped local interconnect structure can connect to one or more of the first diffusion fin, the second diffusion fin. Additionally, in some embodiments, the first linear-shaped local interconnect structure can be a first linear segment of a two-dimensionally varying non-linear local interconnect structure, and the second linear-shaped local interconnect structure can be a second linear segment of the two-dimensionally varying non-linear local interconnect structure. And, in some instances, the first and second linear-shaped local interconnect structures can be connected to each other.
The semiconductor device can also include a contact structure positioned between the first and second diffusion fins. In some embodiments, the contact structure can be substantially centered between the first and second diffusion fins. In some embodiments, the contact structure can connect to either the first gate electrode structure or the second gate electrode structure.
The semiconductor device can also include a contact structure positioned between the first and second gate electrode structures. In some embodiments, the contact structure can be substantially centered between the first and second gate electrode structures. Also, in some embodiments, the semiconductor device can include a conductive interconnect structure positioned in the second direction between first and second diffusion fins, where the contact structure connects to the conductive interconnect structure. In some embodiments, the conductive interconnect structure is a lowest level interconnect structure extending in the first direction that is not a diffusion fin.
The semiconductor device can also include a conductive interconnect structure positioned in the first direction between first and second diffusion fins, where the contact structure connects to a conductive interconnect structure. In some embodiments, the conductive interconnect structure is higher-level interconnect structure.
The semiconductor device can also include one or more interconnect structures, where some of the one or more interconnect structures include one or more interconnect segments that extend in the first direction. In some embodiments, some of the one or more interconnect segments that extend in the first direction are positioned between the first and second diffusion fins. Also, in some embodiments, some of the one or more interconnect segments that extend in the first direction are positioned over either the first diffusion fin or the second diffusion fin. In some embodiments, the one or more interconnect segments that extend in the first direction are positioned in accordance with a second direction interconnect pitch as measured in the second direction between respective first direction oriented centerlines of the one or more interconnect segments.
In some embodiments, the first and second diffusion fins can be positioned in accordance with a diffusion fin pitch as measured in the second direction between respective first direction oriented centerlines of the first and second diffusion fins, where the second direction interconnect pitch is a rational multiple of the diffusion fin pitch, with the rational multiple defined as a ratio of integer values.
In some embodiments, each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, where the first and second diffusion pitches successively alternate in the second direction, and where an average diffusion fin pitch is an average of the first and second diffusion fin pitches, and
where the second direction interconnect pitch is a rational multiple of the average diffusion fin pitch, with the rational multiple defined as a ratio of integer values. In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch. In some embodiments, the first diffusion fin pitch is different than the second diffusion fin pitch.
The above-mentioned one or more interconnect structures can include either a local interconnect structure, a higher-level interconnect structure, or a combination thereof, where the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and where the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate.
In some embodiments, each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, where the first and second diffusion pitches successively alternate in the second direction, and where an average diffusion fin pitch is an average of the first and second diffusion fin pitches. Also, the one or more interconnect segments that extend in the first direction can be centerline positioned in accordance with either a first interconnect pitch as measured in the second direction or a second interconnect pitch as measured in the second direction, where the first and second interconnect pitches successively alternate in the second direction, and where an average interconnect pitch is an average of the first and second interconnect pitches. Also, the average interconnect pitch is a rational multiple of the average diffusion fin pitch, with the rational multiple defined as a ratio of integer values.
In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch. In some embodiments, the first diffusion fin pitch is different than the second diffusion fin pitch, and the first interconnect pitch is different than the second interconnect pitch. In some embodiments, the first diffusion fin pitch is equal to the first interconnect pitch, and the second diffusion fin pitch is equal to the second interconnect pitch.
The semiconductor device can also include one or more interconnect structures, where some of the one or more interconnect structures include one or more interconnect segments that extend in the second direction. In some embodiments, some of the one or more interconnect segments that extend in the second direction are positioned between the first and second gate electrode structures. In some embodiments, some of the one or more interconnect segments that extend in the second direction are positioned over either the first gate electrode structure or the second gate electrode structure.
In some embodiments, the one or more interconnect segments that extend in the second direction are positioned in accordance with a first direction interconnect pitch as measured in the first direction between respective second direction oriented centerlines of the one or more interconnect segments. Also, the first and second gate electrode structures can be positioned in accordance with a gate electrode pitch as measured in the first direction between respective second direction oriented centerlines of the first and second gate electrode structures. The first direction interconnect pitch can be a rational multiple of the gate electrode pitch, with the rational multiple defined as a ratio of integer values.
The above-mentioned one or more interconnect structures can include either a local interconnect structure, a higher-level interconnect structure, or a combination thereof, where the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and where the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate.
In some embodiments, the semiconductor device can also include a first plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin. Each diffusion fin of the first plurality of transistors is structured to project from the surface of the substrate. Each diffusion fin of the first plurality of transistors is structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the first plurality of transistors are substantially aligned with each other in the first direction.
Also, the semiconductor device can include a second plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin. Each diffusion fin of the second plurality of transistors is structured to project from the surface of the substrate. Each diffusion fin of the second plurality of transistors is structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the second plurality of transistors are substantially aligned with each other in the first direction. And, one or more of the first ends of the diffusion fins of the second plurality of transistors are positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors.
In some embodiments, each of the first ends of the diffusion fins of the second plurality of transistors is positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors. In some embodiments, at least one of the diffusion fins of the second plurality of transistors is positioned next to and spaced apart from at least one diffusion fin of the first plurality of transistors. Also, in some embodiments, the first plurality of transistors can include either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors, and the second plurality of transistors can include either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors. In some embodiments, the first plurality of transistors are n-type transistors and the second plurality of transistors are p-type transistors.
In some embodiments, the first and second pluralities of diffusion fins are positioned to have their respective first direction oriented centerlines substantially aligned to a diffusion fin alignment grating defined by a first diffusion fin pitch as measured in the second direction and a second diffusion fin pitch as measured in the second direction. The first and second diffusion fin pitches occur in an alternating sequence in the second direction. Also, in some embodiments, the diffusion fins of the first and second pluralities of transistors collectively occupy portions at least eight consecutive alignment positions of the diffusion fin alignment grating.
In an example embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate, such that the first transistor has a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is formed to project from a surface of the substrate, and such that the first diffusion fin is formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The method also includes forming a second transistor on the substrate, such that the second transistor has a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is formed to project from the surface of the substrate, and such that the second diffusion fin is formed to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is formed at a position next to and spaced apart from the first diffusion fin. Also, the first and second transistors are formed such that either the first end or the second end of the second diffusion fin is formed at a position in the first direction between the first end and the second end of the first diffusion fin.
It should be understood that any circuit layout incorporating finfet transistors as disclosed herein can be stored in a tangible form, such as in a digital format on a computer readable medium. For example, a given circuit layout can be stored in a layout data file, and can be selectable from one or more libraries of cells. The layout data file can be formatted as a GDS II (Graphic Data System) database file, an OASIS (Open Artwork System Interchange Standard) database file, or any other type of data file format suitable for storing and communicating semiconductor device layouts. Also, multi-level layouts of a cell incorporating finfet transistors as disclosed herein can be included within a multi-level layout of a larger semiconductor device. The multi-level layout of the larger semiconductor device can also be stored in the form of a layout data file, such as those identified above.
Also, the invention described herein can be embodied as computer readable code on a computer readable medium. For example, the computer readable code can include a layout data file within which a layout of a cell incorporating finfet transistors as disclosed herein is stored. The computer readable code can also include program instructions for selecting one or more layout libraries and/or cells that include finfet transistors as disclosed herein. The layout libraries and/or cells can also be stored in a digital format on a computer readable medium.
The computer readable medium mentioned herein is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. Multiple computer readable media distributed within a network of coupled computer systems can also be used to store respective portions of the computer readable code such that the computer readable code is stored and executed in a distributed fashion within the network.
In an example embodiment, a data storage device has computer executable program instructions stored thereon for rendering a layout of a semiconductor device. The data storage device includes computer program instructions for defining a first transistor to be formed on a substrate, such that the first transistor is defined to have a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is defined to project from a surface of the substrate, and such that the first diffusion fin is defined to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The data storage device also includes computer program instructions for defining a second transistor to be formed on the substrate, such that the second transistor is defined to have a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is defined to project from the surface of the substrate, and such that the second diffusion fin is defined to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is defined to be positioned next to and spaced apart from the first diffusion fin, and such that the second diffusion fin is defined to have either its first end or its second end positioned in the first direction between the first end and the second end of the first diffusion fin.
It should be further understood that any circuit layout incorporating finfet transistors as disclosed herein can be manufactured as part of a semiconductor device or chip. In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on a semiconductor wafer. The wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions and/or diffusion fins are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.

## Claims

1. An integrated circuit, comprising:
a first finfet transistor of a first transistor type;
a first finfet transistor of a second transistor type;
a second finfet transistor of the first transistor type;
a second finfet transistor of the second transistor type,
each of the first and second finfet transistors of the first transistor type and each of the first and second finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in a parallel direction, the gate electrodes of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrodes of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each of the first and second finfet transistors of the first transistor type formed in part by a respective diffusion fin of a first diffusion type electrically connected to a common node,
each of the first and second finfet transistors of the second transistor type formed in part by a respective diffusion fin of a second diffusion type electrically connected to the common node, the diffusion fins of the first diffusion type collectively separated from the diffusion fins of the second diffusion type in the parallel direction by an inner non-diffusion region,
the gate electrodes of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed by a first conductive structure so as to be electrically connected to each other through the first conductive structure, the gate electrode of the second finfet transistor of the first transistor type formed by a second conductive structure, the gate electrode of the second finfet transistor of the second transistor type formed by a third conductive structure, each of the first, second, and third conductive structures including portions extending over the inner non-diffusion region;
a first conductive contacting structure connected to the portion of the second conductive structure that extends over the inner non-diffusion region; and
a second conductive contacting structure connected to the portion of the third conductive structure that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.

2. An integrated circuit as recited in claim 1, wherein at least one end of the second conductive structure and at least one end of the third conductive structure are aligned to a first common position in the parallel direction.

3. An integrated circuit as recited in claim 2, wherein at least a portion of the first conductive contacting structure and at least a portion of the second conductive contacting structure are aligned to a second common position in the parallel direction.

4. An integrated circuit as recited in claim 3, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape.

5. An integrated circuit as recited in claim 4, further comprising:
a non-transistor linear-shaped gate level feature, wherein each linear-shaped conductive structure that forms at least one gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and the first, second, third, and fourth finfet transistors of the second transistor type is positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate level features, the second direction perpendicular to the parallel direction, and wherein the non-transistor linear-shaped gate level feature is also positioned according to the gate pitch.

6. An integrated circuit as recited in claim 1, wherein the second conductive structure is electrically connected to the third conductive structure through an electrical connection that extends in part through a single interconnect level.

7. An integrated circuit as recited in claim 6, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and of the first, second, third, and fourth finfet transistors of the second transistor type positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate electrodes, the second direction perpendicular to the parallel direction.

8. An integrated circuit as recited in claim 7, wherein at least a portion of the first conductive contacting structure and at least a portion of the second conductive contacting structure are aligned to a common position in the parallel direction.

9. An integrated circuit as recited in claim 8, wherein the part of the electrical connection that extends through the single interconnect level is formed by a linear-shaped interconnect conductive structure.

10. An integrated circuit as recited in claim 9, wherein each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type is formed as part of a corresponding linear-shaped conductive structure, and wherein each of the first, second, and third conductive structures is linear-shaped.

11. An integrated circuit as recited in claim 1, further comprising:
a non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the first diffusion type, and the non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the second diffusion type.

12. An integrated circuit as recited in claim 11, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape, and
wherein the non-transistor gate level feature is linear-shaped.

13. An integrated circuit as recited in claim 12, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.

14. An integrated circuit as recited in claim 13, wherein each linear-shaped conductive structure that forms at least one gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and the first, second, third, and fourth finfet transistors of the second transistor type is positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate level features, the second direction perpendicular to the parallel direction, and wherein the non-transistor linear-shaped gate level feature is also positioned according to the gate pitch.

15. An integrated circuit as recited in claim 14, wherein a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the first transistor type is substantially equal to a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the second transistor type.

16. An integrated circuit as recited in claim 1, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.

17. An integrated circuit as recited in claim 16, further comprising:
a non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the first diffusion type, and the non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the second diffusion type.

18. An integrated circuit as recited in claim 17, wherein the second conductive structure is electrically connected to the third conductive structure through an electrical connection that extends in part through a single interconnect level.

19. An integrated circuit as recited in claim 18, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type;
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape; and
a non-transistor linear-shaped gate level feature.

20. An integrated circuit as recited in claim 19, wherein the part of the electrical connection that extends through the single interconnect level is formed by a linear-shaped interconnect conductive structure.

21. An integrated circuit as recited in claim 1, further comprising:
a gate level feature that forms a gate electrode of a finfet transistor of the first transistor type and that extends between at least two diffusion fins of the second diffusion type.

22. An integrated circuit as recited in claim 21, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.

23. An integrated circuit as recited in claim 22, wherein a centerline-to-centerline distance as measured in a second direction between the gate electrodes of the first and second finfet transistors of the first transistor type is substantially equal to a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the second transistor type, the second direction perpendicular to the parallel direction.

24. An integrated circuit as recited in claim 23, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape.

25. A method for creating a layout of an integrated circuit, comprising:
operating a computer to define a layout of a first finfet transistor of a first transistor type;
operating the computer to define a layout of a first finfet transistor of a second transistor type;
operating the computer to define a layout of a second finfet transistor of the first transistor type;
operating the computer to define a layout of a second finfet transistor of the second transistor type,
each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type having a respective gate electrode layout feature extending lengthwise in a parallel direction, the gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each layout of the first and second finfet transistors of the first transistor type including a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node,
each layout of the first and second finfet transistors of the second transistor type including a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node, the diffusion fin layouts of the first diffusion type collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region,
the gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the first transistor type formed as part of a second conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the second transistor type formed as part of a third conductive structure layout feature, each of the first, second, and third conductive structure layout features including portions extending over the inner non-diffusion layout region;
operating the computer to define a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region; and
operating the computer to define a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.

26. A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:
program instructions for defining a layout of a first finfet transistor of a first transistor type;
program instructions for defining a layout of a first finfet transistor of a second transistor type;
program instructions for defining a layout of a second finfet transistor of the first transistor type;
program instructions for defining a layout of a second finfet transistor of the second transistor type,
each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type having a respective gate electrode layout feature extending lengthwise in a parallel direction, the gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each layout of the first and second finfet transistors of the first transistor type including a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node,
each layout of the first and second finfet transistors of the second transistor type including a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node, the diffusion fin layouts of the first diffusion type collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region,
the gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the first transistor type formed as part of a second conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the second transistor type formed as part of a third conductive structure layout feature, each of the first, second, and third conductive structure layout features including portions extending over the inner non-diffusion layout region;
program instructions for defining a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region; and
program instructions for defining a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.