# Patent

## Title
Static VAR generator compensating control circuit and method for using

## Abstract

An electric vehicle traction motor control circuit includes a main thyristor in series with the motor armature. A second thyristor is connected in series with a commutating capacitor across the main thyristor which can be switched off by firing the second thyristor so that the motor current is diverted into the commutating capacitor. A third thyristor is connected in series with an inductor across the commutating capacitor and serves when fired to reverse the voltage residing on the commutating capacitor following commutating. The reversed voltage on the capacitor is detected and is used to control upper and lower current limit signals set by a driver operable control so that the capacitor is not called upon to receive a large current when it is in a low voltage condition.

## Background
This invention relates to an electric vehicle motor control of the general kind in which motor current is controlled by periodically making and breaking a main current path to the motor when the motor current falls below a lower limit and rises above an upper limit respectively, the limits being variable under the control of the vehicle driver.

In one known arrangement the main current path is constituted by a first thyristor connected in series with the motor between a pair of supply rails. To turn off the main thyristor it is required to divert all the motor current through a communicating path which consists of a second thyristor, first inductor and a capacitor in series across the main thyristor. A third thyristor is connected in series with a second inductor across the capacitor and is arranged when fired to reverse the voltage across the capacitor.

With such arrangements various firing orders have been proposed for the thyristors. One possibility is to fire the main thyristor and the third thyristor simultaneously when the lower limit is reached and to fire the second thyristor when the upper limit is reached. With this arrangement problems arise if the upper limit is not reached, because the reversed charge on the capacitor may leak away so that when the second thyristor is eventually fired, proper commutation does not occur. To overcome this, and other linked problems, the control circuits associated with the thyristor, have in the past been relatively complex, to provide minimum and maximum on and off times for the main thyristor.

Other approaches to this problem have also been proposed but all put unwanted constraints on the control system.

It is an object of the present invention to provide an improved control circuit in which the problems referred to are substantially avoided.

An electric vehicle traction motor control circuit in accordance with the invention comprises a main thyristor in series with the motor armature between a pair of supply rails, a second thyristor arranged on firing to divert current from the main thyristor into a commutating capacitor, a third thyristor connected in series with an inductor across the commutating capacitor and arranged on firing to reverse the voltage on the commutating capacitor, driver operable control means for determining upper and lower motor current limits, means sensitive to the magnitude of a voltage stored on the commutating capacitor for varying said motor current limits independently of said driver operable control means first firing control means for firing the main thyristor when the actual motor current is less than said lower limit, second firing control means for firing the second thyristor when the actual motor current exceeds the upper limit and third firing control means for the third thyristor.

An example of the invention is shown in the accompanying drawings in which:

FIG. 1 is a circuit diagram of a thyristor chopper and motor circuit;

FIG. 2 is a circuit diagram of a commutating capacitor voltage sensing circuit;

FIG. 3 is a circuit diagram of a current comparator circuit and the firing circuit for one of the thyristors of the chopper circuit of FIG. 1;

FIGS. 4 and 5 are circuit diagrams of firing circuits for the two other thyristors of FIG. 1 respectively; and

FIGS. 6 and 7 are circuit diagrams of other logic circuit elements included in the control circuit.

Referring firstly to FIG. 1 the motor in this case has an armature winding 10 and a field winding 11. A contact F connects one side of the armature winding 10 to a positive supply rail 12 (at about 200 V relative to a rail 13) and a contact R connects the other side of the armature 10 to the rail 12. The two sides of the armature 10 are also connected to two fixed contacts of a change-over switch F/RB, the common contact of which is connected via an inductor 14 the field winding 11, a main thyristor SCR1 and a main fuse 15 in series to the rail 13. Four diodes D.sub.1 to D.sub.4 connect the two sides of the armature 10 to the rails 12, 13, with the diode D.sub.1 having its anode connected to the same side of the armature as the contact F and its cathode connected to the rail 12, the diode D.sub.2 having its cathode connected to the anode of the diode D.sub.1 and its anode connected to the rail 13, the diode D.sub.3 having its anode connected to the other side of the armature 10 and its cathode connected to the rail 12 and the diode D.sub.4 having its cathode connected to the anode of the diode D.sub.3 and its anode connected by a brake current fuse 16 to the rail 13. A further diode D.sub.5 has its anode connected to the anode of the thyristor SCR1 and its cathode connected to the rail 12. A sixth diode D.sub.6 has its cathode connected to the common contact of the switch F/RB and its anode connected to the rail 13.

For commutating the current through the thyristor SCR1 there is a second thyristor SCR2 connected in series with a saturable core inductor 17, a fuse 18 and a commutating capacitor 19 between the anode of the thyristor SCR1 and the rail 13. A third thyristor SCR3 is connected in series with an inductor 20 across the capacitor 19.

For normal forward motoring the contact F is closed and the switch F/RB is closed to the right by contactors driven by circuits which do not form part of the present invention and an understanding of which is not necessary for an understanding of the present invention. When the main thyristor is conductive current flows through contact F, "forwardly" through the armature through the switch F/RB, the inductor 14, the field winding 11, the thyristor SCR1 and the main fuse 15. When the thyristor SCR2 is first (assuming that there is a negative voltage on the "upper" plate of the capacitor 19 at this stage), the current referred to is diverted from the main thyristor SCR1 into the capacitor 19 via the inductor 17. This causes the thyristor SCR1 to turn off. The diverted current causes the capacitor 19 to charge up until the voltage on the upper plate of the capacitor 19 is the same as that at the anode of the thyristor SCR1. At this stage the inductor 17 continues to cause current to flow into the capacitor 19 and the inductor 14 acts to maintain current in the armature and field windings via the "freewheel" diode D.sub.5. Inductor 17 and capacitor 19 act as a resonant circuit but when the voltage on capacitor 19 reaches its peak, (i.e. when the current in the inductor 17 falls to zero) the thyristor SCR2 turns off and the charge is then held on the capacitor 19. The armature and field winding current decays away.

Firing of the thyristor SCR3 causes the inductor 20 to be connected across the charged capacitor 19. The capacitor 19 thus discharges into the inductor 20, current continuing to flow until a peak negative voltage is attained, which peak is held until the next commutation is required.

For reverse running contact F is opened, contact R is closed and switch F/RB is closed to the left. For regenerative braking when the motor is running forwardly both contacts F and R are opened and switch F/RB is closed to the left. Current induced in the armature, then flows through the switch F/RB, the inductor 14, the field winding 11, the thyristor SCR1, the fuses 15 and 16 and the diode D.sub.4.

FIG. 1 also shows an armature current sensing arrangement comprising a ferromagnetic loop 21 surrounding one of the conductors leading to the armature winding 10, a Hall effect device 22 in a gap in this loop and a differential amplifier A.sub.1 with its inputs connected by resistor R.sub.1 and R.sub.2 to the terminals of the device 22. A feedback resistor R.sub.3 connects the inverting input terminal of the amplifier A.sub.1 to its output terminal and a bias resistor R.sub.4 connects the non-inverting terminal to earth. A resistor and thermistor network 23 is provided at the output of the amplifier A.sub.1 to provide temperature compensation.

A circuit is also provided to detect the instant at which the voltage on the inductor 17 reverses and the diode D.sub.5 starts to conduct during commutation. In the example shown this circuit includes a diode D.sub.7, a resistor R.sub.5 and the light emitting diode of an opto-coupler O.sub.1 connected in series across the inductor 17. The transistor of the opto-coupler is included in a "ready" circuit (not shown in detail) which produces an output pulse at a terminal 24 for as long as there is a reversed voltage on the inductor 17. The "ready" pulse may alternatively be generated by means of a current detector on the conductor associated with the freewheel diode D.sub.5. Such detector may be a current transformer or another Hall effect type detector, the latter being preferred.

Turning now to FIG. 2 there is shown a circuit which is used to monitor the voltage on the capacitor 19 after firing of the thyristor SCR3. This circuit includes a pnp transistor Q.sub.1 which has its collector connected to the rail 13 and its base connected by a high ohmic value resistor R.sub.5 to the capacitor 19. The emitter of the transistor Q.sub.1, is connected via a current limiting resistor R.sub.6 and the light emitting diode of an opto-coupler O.sub.2 to a rail 25. A resistor R.sub.7 is connected between the base of the transistor Q.sub.1 and the rail 25 and a diode D.sub.8 has its cathode connected to the rail 25 and its anode connected to the base of transistor Q.sub.1 to provide protection of the transistor Q.sub.1 in the period whilst the capacitor voltage is positive following commutation. The rail 25 has a zener diode regulated supply from the rail 12. To this end a resistor R.sub.9 connects the rail 12 to the rail 25 and a zener diode ZD.sub.1 has its cathode connected to the rail 25 and its anode connected to the rail 13, a smoothing capacitor C.sub.1.

The photo-transistor of the opto-coupler O.sub.2 has its collector connected to a +15 V supply rail 26 associated with a ground rail 27 and a -15 V supply rail of a power supply which is isolated from the main traction power supply rails 12, 13. The emitter of this photo-transistor is connected by a resistor R.sub.10 to the rail 27 and a resistor R.sub.11 connects its base to its emitter. The photo-transistor of another opto-coupler O.sub.3 is likewise connected with resistors R.sub.12 and and R.sub.13. The emitters of these two transistors are also connected by resistors R.sub.14 and R.sub.15 respectively to the inverting and non-inverting input terminals of an operational amplifier A.sub.1. A resistor R.sub.16 connects the non-inverting input terminal of the amplifier A.sub.1 to the rail 27 and the output terminal of the amplifier A.sub.1 is connected to the cathode of a diode D.sub.9 with its anode connected to the base of an pnp transistor Q.sub.2 with a potentiometer R.sub.17 connecting the emitter of the transistor Q.sub.2 to the rail 27. The collector of the transistor Q.sub.2 is connected via light emitting diode of the opto-coupler O.sub.3 to the rail 28. A resistor R.sub.18 connects the base of the transistor Q.sub.2 to the rail 27. The emitter of the transistor Q.sub.2 is connected by a resistor R.sub.19 and a capacitor C.sub.2 in parallel to the inverting input terminal of the amplifier A.sub.1.

The circuit described provides a voltage across the potentiometer R.sub.17 which is substantially linearly related to the voltage across the capacitor 19 (except when this latter voltage is positive following commutation). The use of the opto-isolator O.sub.3 in the feedback loop of the amplifier A.sub.1 provides compensation for the non-linearity and variations of gain with temperature of the opto-isolator O.sub.2, assuming the two opto-isolators O.sub.2 and O.sub.3 to be reasonably matched.

The slider of the potentiometer R.sub.17 is connected both to a sample and hold circuit based on operational amplifiers A.sub.2 and A.sub.3 and to a threshold voltage detector based on an operational amplifier A.sub.4. The sample and hold circuit includes an n-channel field effect transistor Q.sub.3 with its drain connected to the output terminal of the amplifier A.sub.2 and its source connected to one side of a capacitor C.sub.3 which has its other side connected to the rail 27. The inverting input terminal of the amplifier A.sub.2 is connected by a resistor R.sub.19 to the slider of the potentiometer R.sub.17 and its non-inverting input terminal is connected by a resistor R.sub.20 to the rail 27 and by a resistor R.sub.21 to the rail 28. A feedback resistor R.sub.22  connects the output terminal of the amplifier A.sub.2 to the inverting input terminal thereof so that the amplifier A.sub.2 acts as a linear inverting amplifier.

A bias resistor R.sub.23 connects the output terminal of the amplifier A.sub.2 to the gate of the field effect transistor Q.sub.3 which is also connected to the anode of a diode D.sub.10. The cathode of the diode D.sub.10 is connected by a resistor R.sub.24 to the collector of an npn transistor Q.sub.4 which has its emitter connected to the rail 28 and its collector connected by a resistor R.sub.25 to the rail 26. The base of the transistor Q.sub.4 is connected to the common point of two resistors R.sub.26, R.sub.27 in series between the collector of a pnp transistor Q.sub.5 and the rail 28. The emitter of the transistor is connected to the rail 26 and it is biased off by a resistor R.sub.28 connected between the rail 26 and the base of the transistor Q.sub.4 which is also connected by a resistor R.sub.29 to a terminal 29 (see FIG. 7).

Whilst the terminal 29 is at a voltage close to that on the rail 26, the transistors Q.sub.4 and Q.sub.5 are off and the field effect transistor Q.sub.3 is non-conductive. When the voltage on the terminal 29 falls as will be explained hereinafter, the transistor Q.sub.4 and Q.sub.5 turn on and the field effect transistor Q.sub.3 assumes a low resistance state, allowing the capacitor C.sub.3 to charge or discharge rapidly to the voltage then existing at the output terminal of the amplifier A.sub.2.

The amplifier A.sub.3 is connected as a voltage follower to provide a very high input impedance so as not to discharge the capacitor C.sub.3. A resistor R.sub.30 connects the capacitor C.sub.3 to the non-inverting input terminal of the amplifier A.sub.3, a resistor R.sub.31 connecting the output terminal of the amplifier A.sub.3 to its inverting input terminal. The output terminal of the amplifier A.sub.3 is also connected to the cathode of a diode D.sub.11, of which is connected by a normally closed relay contact to a terminal 30 (FIG. 3).

The amplifier A.sub.4 is connected as a comparator with hysteresis. Its inverting input terminal is connected by a resistor R.sub.32 to the slider of the potentiometer R.sub.17, and its non-inverting input terminal is connected to the common point of a pair of resistors R.sub.33, R.sub.34 in series between the rails 27, 28 and also, by a resistor R.sub.35, to its output terminal which is connected to a terminal 31.

Turning now to FIG. 3, there is shown schematically the arrangement in which the signals from the current transducer circuit of FIG. 1 and the capacitor voltage circuit of FIG. 2 are used. The current signal is applied via a resistor R.sub.41 to the inverting input terminal of an operational amplifier A.sub.5 connected as a comparator with hysteresis. The required hysteresis is obtained by means of resistors R.sub.42, R.sub.43 connected in series between the output terminal of the amplifier A.sub.5 and the rail 27 with their common point connected to the non-inverting input terminal of the amplifier A.sub.5. The inverting input terminal of the amplifier A.sub.5 is connected by a resistor R.sub.44 to a motor current demand signal generating circuit 32, of which the output stage is shown. It receives input signals from a speed transducer circuit 33 and from accelerator and brake pedal operated potentiometers 34 and 35 and produces a d.c. output signal representative of the desired average motor current varying in accordance with a complex function of speed and pedal depression. Details of a similar circuit arrangement may be found in prior U.K. Patent Application No. 8364/75.

The output stage is constituted by an operational amplifier A.sub.100 which operates either in inverting or non-inverting mode according to whether a transistor Q.sub.100 is on or not. The inverting input terminal of the amplifier A.sub.100 is connected by a resistor R.sub.150 to a point in the circuit 32 and two resistors R.sub.151, R.sub.152 of the same value connect the same point to the non-inverting input terminal. A resistor R.sub.153 combined with a capacitor C.sub.100 in series connect the output terminal of the amplifier A.sub.100 to the earth rail 27. A resistor R.sub.154 connects the junction of the resistor R.sub.153 with the capacitor C.sub.100 to the anode of a diode D.sub.100, the cathode of which is connected to the base of a transistor Q.sub.101 connected as an emitter follower. Two resistors R.sub.155, R.sub.156 in series connect the emitter of the transistor Q.sub.101 to the rail 27 with the junction of these resistors connected to the inverting input terminal of the amplifier A.sub.100 by a feedback resistor R.sub.157. The emitter of the transistor Q.sub.101 is connected by the resistor R.sub.44 to the inverting input terminal of the amplifier A.sub.5.

The terminal 30 is connected to the base of the emitter follower transistor Q.sub.101. If the output of the amplifier A.sub.5 is high the voltage at its non-inverting input terminal is at a fixed positive level which must be exceeded by the voltage at its inverting input terminal before the amplifier output can go negative. Similarly when the output of the amplifier A.sub.5 is low, there is a fixed negative voltage applied to the non-inverting input terminal of the amplifier A.sub.5. The signals applied via resistors R.sub.41 and R.sub.44 are of opposite polarity and these resistors may be regarded as forming a potential divider so that for a given demand signal the output of the amplifier A.sub.5 will go low when an upper current limit is exceeded and will go high when the motor current is less than a low current limit, both limits being variable by the driver using the pedals 34, 35.

The effect of the capacitor voltage signal applied via terminal 30 is to decrease the level to which the current demand signal may rise if capacitor voltage is too low.

The output terminal of the amplifier A.sub.5 is connected by a diode D.sub.12 and a resistive potential divider R.sub.46, R.sub.47 to the base of an npn transistor Q.sub.6 with its emitter grounded to the rail 27 and its collector connected by a resistor R.sub.48 to the rail 26. The collector of the transistor Q.sub.6 is connected to a terminal 36 (FIG. 4) and also to the cathode of a diode D.sub.13 with its anode connected by a resistor R.sub.49 to the rail 26. A diode D.sub.14 connects the anode of the diode D.sub.13 to a terminal 37 (FIG. 7). A zener diode ZD.sub.2 has its cathode connected to the anode of the diodes D.sub.13 and D.sub.14 and its anode connected by a resistor R.sub.50 to the rail 27. The resistor R.sub.49 and the zener diode ZD.sub.2 are chosen so that the zener diode ZD.sub.2 does not conduct if either of the diodes D.sub.13, D.sub.14 is conducted, i.e. if the transistor Q.sub.6 is on or the terminal 39 voltage is low.

An npn transistor Q.sub.7 has its emitter connected to the rail 27 and its base connected to the anode of the zener diode ZD.sub.2, its collector being connected by a resistor R.sub.51 to the rail 26. The transistor Q.sub.7 turns on whenever the zener diode ZD.sub.2 is conducting.

The emitter of the transistor Q.sub.7 is connected by a resistive potential divider R.sub.52, R.sub.53 to the base of an npn transistor Q.sub.8 which controls an oscillator based on a unijunction transistor Q.sub.9 and a capacitor C.sub.4. The secondary base of the unijunction transistor Q.sub.9 is connected by two resistors R.sub.54, R.sub.55 in series to the rail 27 and its primary base is connected by a resistor R.sub.56 to the rail 26. There are two separate charging paths for the capacitor C.sub.4 which determine the frequency of the oscillator. One such path is constituted by a resistor R.sub.57 connected in series with the capacitor C.sub.4 between the rails 26, 27. The other path is constituted by a resistor R.sub.58, a diode D.sub.15, a diode D.sub.16 and a resistor R.sub.59 in series across the resistor R.sub.57, the total resistance of the resistors R.sub.58, R.sub.59 being significantly less than the resistance of the resistor R.sub.57. A diode D.sub.17 is connected across the series combination of the resistor R.sub.59 and the diode D.sub.16, with its polarity reversed relative to that of the diode D.sub.16. The anode of the diode D.sub.16 and the cathode of the diode D.sub.17 are connected to the collector of the transistor Q.sub.8. The anode of the diode D.sub.15 is connected to the anode of a diode D.sub.18, the cathode of which is connected to the anode of a thyristor SCR4 which has its cathode connected to the rail 27.

When the transistor Q.sub.8 is conducting, the oscillator does not operate since the capacitor C.sub.4 is held discharged. When the transistor Q.sub.8 is turned off, i.e. when the transistor Q.sub.7 turns on, the oscillator starts to run at a relatively high frequency until the thyristor SCR4 is fired as will be explained hereinafter. Thereafter, for as long as the transistor Q.sub.8 is off, the oscillator will operate at a low frequency determined by the resistor R.sub.57.

The common point of the resistors R.sub.54, R.sub.55 is connected to the base of a transistor Q.sub.10 which has its emitter connected to the rail 27 and its collector connected by a resistor R.sub.60 to the rail 26. The collector of the transistor Q.sub.10 is connected to the TRIGGER terminal of an integrated circuit timer T.sub.1 (shown as one half of a dual timer circuit type NE556  manufactured by signetics). The DISCHARGE and THRESHOLD terminals of this timer circuit are connected to the junction of a resistor R.sub.61 and a capacitor C.sub.5 in series between the rails 26 and 27. The CONTROL VOLTAGE terminal of the circuit is connected to the rail 27 by a capacitor C.sub.6 and the RESET terminal is connected to the collector of an npn transistor Q.sub.11 which has its emitter connected to the rail 27 and its collector connected by a resistor R.sub.62 to the rail 26. The base of the transistor Q.sub.11 is connected by a resistor R.sub.63 to the rail 27 and by a resistor R.sub.64 to the cathode of a diode D.sub.19 having its anode connected to the collector of the transistor Q.sub.7. The base of the transistor Q.sub.11 is also connected by a resistor R.sub.65 to the cathode of a diode D.sub.20, the anode of which is connected to a terminal 40.

The OUTPUT terminal of the timer circuit T.sub.1 is connected to a terminal 41 and thence to the gate of the main thyristor SCR1. This OUTPUT terminal is also connected by a normally closed override contact 42 and a resistor R.sub.66 to gate of the thyristor SCR4, this gate being also connected by a resistor R.sub.67 to the rail.

Assuming the voltage at terminal 40 is low and that at terminal 89 is high turning off of the transistor Q.sub.6 by a negative transition in the output of the output of the current comparator operational amplifier A.sub.5 causes transistor Q.sub.7 to turn on which in turn causes the oscillator to commence oscillating at relatively high frequency, and, because, in these circumstances, the transistor Q.sub.11 is turned off, the timer T.sub.1 will be triggered the resistors R.sub.58 and R.sub.59 and the capacitor C.sub.4 fixing the delay before such triggering at approximately 70 .mu.S. The timer OUTPUT terminal now goes high for 20 .mu.S, set by the resistor R.sub.61 and the capacitor C.sub.5. This output pulse fires the thyristors SCR1 and SCR4, the latter interrupting the previous charging path for the capacitor C.sub.4. The resistor R.sub.57 and the capacitor C.sub.4 set the repetition frequency of the oscillator at approximately 200 Hz so that additional firing pulses are produced by the timer T.sub.1 at this frequency, in case the current level in the thyristor SCR1 is insufficient for it to hold the thyristor SCR1 conductive when the output of the current comparator operational amplifier A.sub.5 goes high (indicating that the actual current has reached the upper limit), transistor Q.sub.6 turns on, turning off transistor Q.sub.7 which turns on transistors Q.sub.8 and Q.sub.11. Transistor Q.sub.11 holds the RESET terminal of the timer T.sub.1 low so that it cannot be triggered and transistor Q.sub.8 maintains the capacitor C.sub.4 discharged so that the oscillator ceases to run.

The terminals 36, 39 and 40 provide input signals to the circuit of FIG. 4 which controls firing of the thyristor SCR2. A resistor R.sub.70 connects the terminal 36 to the anode of a zener diode ZD3, the cathode of which is connected by a resistor R.sub.71 to the rails 26 so that the zener diode ZD3 only conducts when the transistor Q.sub.6 of FIG. 3 is on (i.e. when the current comparator operation amplifier A.sub.5 output is high). The cathode of the zener diode ZD3 is connected to the base of a pnp transistor Q.sub.12, the emitter of which is connected to the rail 26 and the collector of which is connected to the rail 27 by a resistor R.sub.72. The collector of the transistor Q.sub.12 is connected by a resistor R.sub.73 and a capacitor C.sub.6 in series to the base of a npn transistor Q.sub.13 which has its emitter connected to the rail 27 and its collector connected by a resistor R.sub.74 to the rail 26. The base of the transistor Q.sub.13 is connected to the cathode of a protective diode D.sub.22 which has its anode grounded to rail 27 and is also connected by a resistor R.sub.75 to the rail 27 to bias the transistor Q.sub.13 off.

It will be appreciated that when the transistor Q.sub.12 turns on the transistor Q.sub.13 will be turned on for as long as it takes the capacitor to charge up (the time constant R.sub.73 C.sub.6 being approximately 10 .mu.S).

The collector of the transistor Q.sub.12 is also connected by a resistor R.sub.76 and a diode D.sub.23 in series to one side of a capacitor C.sub.7, the other side of which is connected to the rail 27. Said one side of said capacitor C.sub.7 is connected to the emitter of a unijunction transistor Q.sub.14, which has its secondary base connected by a resistor R.sub.77 to the rail 27 and its primary base connected to the rail 26 by a resistor R.sub.78. The secondary base of the unijunction transistor Q.sub.14 is also connected by a resistor R.sub.79 and a diode D.sub.24 in series to the base of the transistor Q.sub.13.

The resistor R.sub.76, capacitor C.sub.7 and unijunction transistor Q.sub.14 form an oscillator, operating under the control of the transistor Q.sub.12 at a frequency of about 3 KHz. This oscillator is arranged to be inhibited by an npn transistor Q.sub.15 with its collector emitter connected across the capacitor C.sub.7 and biased off by a resistor R.sub.80 connected between its base and the rail 27. The base of the transistor Q.sub.15 is also connected to the cathode of a thyristor SCR5 the anode of which is connected by a resistor R.sub.81 to the collector of the transistor Q.sub.12. The base of the transistor Q.sub.15 is further connected to the collector of an npn transistor Q.sub.16 having its emitter connected to the rail 27 and its base connected by a resistor R.sub.82 to the rail 27. A diode D.sub.24 has its cathode connected to the base of the transistor Q.sub.16 and its anode connected by a resistor R.sub.83 to the terminal 40. A diode D.sub.25 connects the anode of the diode D.sub.24 to the terminal 39 so that the transistor Q.sub.16 can only turn on when the signals at both terminals 39 and 40 are high.

The thyristor SCR5 has its gate connected by a resistor R.sub.84, a diode D.sub.26 and a normal closed override contact 43 to the OUTPUT terminal to another integrated circuit timer T.sub.2 (constituted by the other half of the NE556 circuit of time T.sub.1). The INPUT terminal of the timer T.sub.2 is connected to the emitter of the transistor Q.sub.13 and its CONTROL VOLTAGE terminal is connected by a capacitor C.sub.8 to the rail 27. The THRESHOLD and DISCHARGE terminals of the timer T.sub.2 are both connected by a resistor R.sub.85 to the rail 26 and by a capacitor C.sub.9 to the rail 27, the resistor R.sub.85 and the capacitor C.sub.9 setting the on-time of the monostable multivibrator constituted by the timer T.sub.2 and its associated components at about 20 .mu.S. The OUTPUT terminal of the timer T.sub.2 is also connected to the gate of the second thyristor SCR2 (FIG. 1) and to a terminal 44.

The RESET terminal of the timer T.sub.2 is connected by a resistor R.sub.86 to the rail 26 and by the collector-emitter path of an npn transistor Q.sub.17 to the rail 27. The base of the transistor Q.sub.17 is connected by a resistor R.sub.87 to the rail 27 and by a resistor R.sub.88 to the anode of a zener diode ZD4 having its cathode connected to the cathode of three diodes D.sub.26, D.sub.27, and D.sub.28 respectively. The anodes of the diodes D.sub.26, D.sub.27, and D.sub.28 are connected to three terminals 45, 46 and 46 see FIG. 5 respectively, so that a high voltage signal at any of these terminals will turn on the transistor Q.sub.17 and reset the timer T.sub.2. A capacitor C.sub.10 is connected between the cathode of the zener diode ZD4 and the rail 27.

Provided that the signal voltages at the terminals 45, 46 and 47 are all low when the transistor Q.sub.12 is turned on by output of the current comparator operational amplifier A.sub.5 going low, the timer T.sub.2 will be triggered immediately and the oscillator around the unijunction transistor Q.sub.14 starts to run providing further triggering pulses to the timer T.sub.2. The first output pulse from the timer T.sub.2 turns on the thyristor SCR5 which, unless the transistor Q.sub.16 is on, turns on the transistor Q.sub.15 on, thereby holding the capacitor C.sub.7 discharged and stopping the oscillator from running.

A normally open contact 48 connects the terminal 36 via a resistor R.sub.89 and a diode D.sub.29 to the emitter of the unijunction transistor Q.sub.14, so that when the contact 48 is closed (when a "creep" condition has been selected) the oscillator runs at a significantly lower frequency of say 400 Hz when the output of the current comparator operational amplifier A.sub.5 is low. In this condition the transistor Q.sub.12 is off so that firing of the thyristor SCR5 does not provide current to turn on the transistor Q.sub.15 and stop the oscillator.

Turning now to FIG. 5 the OUTPUT terminal of the timer T.sub.2 (FIG. 4) is connected via the terminal 44 to through two resistors R.sub.90, R.sub.91 in series to the rail 27. The common point of these resistors is connected to the base of an npn transistor Q.sub.18, the emitter of which is grounded to the rail 27. The collector of the transistor Q.sub.18 is connected by a resistor R.sub.92 to the rail 26 and is also connected to the TRIGGER terminal of another timer integrated circuit T.sub.3 which is connected as a monostable multivibrator with a pulse duration of about 2.5 mS. The THRESHOLD and DISCHARGE terminals of the timer T.sub.3 are the rail 27 by a capacitor C.sub.11 and to the rail 26 by a resistor R.sub.93 and variable reset R.sub.94 in series. A capacitor C.sub.12 connects the CONTROL VOLTAGE terminal of the timer T.sub.3 to the rail 26 and the RESET terminal is connected to a terminal R.sub.1. The OUTPUT terminal is connected to a terminal 49 (FIGS. 6 and 7).

The output terminal of the timer T.sub.3 is also connected via a capacitor C.sub.13 to one end of a resistor R.sub.95 the other end of which is connected to the rail 26. A diode D.sub.29 has its cathode connected to the rail 26 and its anode connected to the junction between the capacitor C.sub.13 and the resistor R.sub.95 so that a negative going pulse is produced at this junction when the timer T.sub.3 resets. This junction is also connected to the TRIGGER terminal of another timer T.sub.4, again connected as a monostable multivibrator with a pulse duration of about 20 .mu.S. The THRESHOLD and DISCHARGE terminals of the timer T.sub.4 are connected to the rail 26 by a resistor R.sub.96 and to the rail 26 by a capacitor C.sub.14. A capacitor C.sub.15 connects the CONTROL VOLTAGE terminal of the timer T.sub.4 to the rail 27 and its RESET terminal is connected to a terminal R.sub.2. The output terminal of the timer T.sub.4 is connected via the terminal 45 to the gate of the thyristor SCR.sub.3 and also to the reset circuit of the timer T.sub.2 (FIG. 4).

The OUTPUT terminal of the timer T.sub.4 is also connected by two resistors R.sub.98, R.sub.99 in series to the rail 27, the junction of these resistors being connected to the base of an npn transistor Q.sub.19 which has its emitter connected to the rail 27. The collector of the transistor Q.sub.19 is connected by a load resistor R.sub.100 to the rail 26 and is also connected to the TRIGGER terminal of yet another timer T.sub.5 connected as a monostable multivibrator with a pulse duration of 300 .mu.S. The THRESHOLD and DISCHARGE terminals of the timer T.sub.5 are connected to the rail 27 by a capacitor C.sub.16 and to the rail 26 by a resistor R.sub.101 and a variable resistor R.sub.102 in series. The CONTROL VOLTAGE terminal of the timer T.sub.5 is connected by a capacitor C.sub.17 to the rail 27 and its RESET terminal is connected directly to the rail 26.

A capacitor C.sub.18 connects the OUTPUT terminal of the timer T.sub.5, which terminal is also connected to the terminal 46, to the TRIGGER terminal of a further timer circuit T.sub.6 connected as a monostable multivibrator with a pulse length of 100 .mu.S. The THRESHOLD and DISCHARGE terminals of the timer T.sub.6 are connected to the rail 27 by a capacitor C.sub.19 and to the rail 26 by a resistor R.sub.103. The CONTROL VOLTAGE terminal of the timer T.sub.6 is connected by a capacitor C.sub.20 to the rail 26 and its RESET terminal is connected directly to the rail 26. The TRIGGER terminal is connected by a resistor R.sub.104 and a diode D.sub.30 to the rail 27 so as to convert the trailing edge of the output pulse of the timer T.sub.5 into a negative-going triggering inpulse for the timer T.sub.6. The output terminal of the timer T.sub.6 is connected to the terminal 47.

Turning now to FIG. 6, there is shown a simple circuit which converts the low signal which exists at terminal 31 when the capacitor 19 voltage is too low into a high level signal for use in the circuits of FIGS. 3 and 4. This circuit includes a resistor R.sub.110 connecting the anode of a diode D.sub.31 to the rail 26. The terminal 31 is connected to the anode of this diode by a normally closed contact which is energised if it is required to override the Vlow control signal. The cathode of the diode D.sub.31 is connected by a resistor R.sub.111 to the base of an npn transistor Q.sub.20 which base is also connected by a resistor R.sub.111 to the rail 27. The transistor Q.sub.20 has its emitter connected to the rail 27 and its collector connected to the terminal 40 and by a resistor R.sub.113 to the rail 26.

The R.sub.2 reset signal for resetting the timer T.sub.4 is generated by inverting a demand cutoff signal generated under certain circumstances during change overs between forward and reverse motoring and braking. This particular feature is not essential to the present invention and the derivation of the demand cutoff signal will not be described herein. The demand cutoff terminal 50 is connected by a resistor R.sub.114 to the base of an npn transistor Q.sub.21 which has its emitter connected to the rail 27. A resistor R.sub.115 connects the base of the transistor Q.sub.21 to the rail 27 and a resistor R.sub.116 connects the collector of the transistor Q.sub.21 to the rail 26, which collector is also connected to the terminal R.sub.2 and to the cathode of a diode D.sub.32. The anode of the diode D.sub.32 is connected by a capacitor C to the rail 26 and also to the anodes of two diodes D.sub.33, D.sub.34 and a zener diode ZD5. The cathode of the diode D.sub.33 is connected to terminal 49 and that of the zener diode ZD5 is connected by two resistors R.sub.117 and R.sub.118 in series to the rail 26. The junction of this resistor is connected to the base of a pnp transistor Q.sub.22 with its emitter connected to the rail 26 and its collector connected by a resistor R.sub.119 to the rail. The cathode of the diode D.sub.34 is connected to the collector of an npn transistor Q23 with its emitter grounded to rail 27 and its collector connected by a resistor R.sub.120 to the rail 27. The base of the transistor Q.sub.23 is connected by resistor R.sub.121 to the rail 27 and also to the anode of a zener diode ZD6 the cathode of which is connected to the terminal 24 and, by a resistor R.sub.122 to the rail 26. This transistor Q.sub.22 can be turned on by a positive going signal at the terminal 24 or at the terminal 50 or a negative going signal at the terminal 49.

The collector of the transistor Q.sub.22 is connected to the TRIGGER terminal of another timer circuit T.sub.7 connected as a monostable multivibrator with a pulse duration of 100 .mu.S. The THRESHOLD and DISCHARGE terminals of the timer T.sub.7 are connected by a capacitor C.sub.22 to the rail 27 and by a resistor R.sub.123 to the rail 26. The CONTROL VOLTAGE terminal is connected by a capacitor C.sub.23 to the rail 27 and the RESET terminal is connected directly to the rail 26.

The OUTPUT terminal of the timer C.sub.7 is coupled by a capacitor C.sub.24 to the TRIGGER terminal of another timer T.sub.8. This TRIGGER terminal is connected to the rail 26 by a resistor R.sub.124 and a diode D.sub.35 in parallel so that the timer T.sub.8 is triggered by the falling edge of the output pulse of the timer T.sub.7. The timer T.sub.8 is connected as a monostable multivibrator with a pulse duration of 50 .mu.S. Its THRESHOLD and DISCHARGE terminals are connected to the rail 27 by a capacitor C.sub.25 and to the rail 26 by a resistor R.sub.125. The CONTROL VOLTAGE terminal of the timer T.sub.8 is connected to the rail 27 by a capacitor C.sub.26. The RESET terminal of the timer T.sub.8 is connected to the collector of an npn transistor Q.sub.24 which has its emitter grounded to rail 27 and its collector connected to the rail 26 by a resistor R.sub.126. The base of the transistor Q.sub.24 is connected to the collector of an npn transistor Q.sub.25, the emitter of which is connected to the rail 27 and the collector of which is connected by a resistor R.sub.127 to the rail 26. The base of the transistor Q.sub.25 is connected to the junction of two resistors R.sub.128, R.sub.129 connected in series between the OUTPUT terminal of the timer T.sub.8 and the rail 27 and also connected by a resistor R.sub.130 to the cathode of a diode D.sub.36 with its anode connected to the collector of the transistor Q.sub.23.

The OUTPUT terminal of the timer T.sub.8 is also connected by two resistors Rhd 131 and R.sub.132 in series to the rail 27, with the junction of these resistors connected to the base of an npn transistor Q.sub.26. The emitter of the transistor Q.sub.26 is connected to the rail 27 and its collector is connected via a normally closed override contact 51 to the R.sub.1 terminal and also by a resistor R.sub.133, to the rail 26.

The timer T.sub.7 is triggered when the transistor Q.sub.22 turns off either as a result of the signal at terminal 49 going high (caused by triggering of timer T.sub.3) or as a result of the signal at terminal 24 going low. At the end of the output pulse from the timer T.sub.7, the timer T.sub.8 is triggered, provided to signal at terminal 24 remains low. Once triggered the timer T.sub.8 is not reset if the signal at terminal 24 goes high.

Turning finally to FIG. 7, two simple logic circuits are shown. Firstly there is an npn transistor Q.sub.27 controlling the signal at the terminal 29 in accordance with the signals at the terminals 46 and 49. The emitter of the transistor Q.sub.27 is connected to the rail 27 and its base is connected to the same rail by a resistor R.sub.135. This base is also connected to the anode of a zener diode ZD7, the cathode of which is connected by a resistor R.sub.136 to the cathodes of two diodes D.sub.37 and D.sub.38, which have their anodes connected to the terminals 46 and 49 respectively. A capacitor C.sub.27 is connected between the cathodes of these diodes and the rail 27. The collector of the transistor Q.sub.27 is connected to the terminal 29 and by a resistor R.sub.137 to the rail 26. It will be appreciated that the signal at the terminal 29 goes high to cause the field effect transistor Q.sub.3 (FIG. 2) to become conductive, only when the signals at terminals 46 and 49 are both low.

The remainder of FIG. 7 controls the signal at terminal 37 in accordance with the signals at terminals 46, 47 and 49. An npn transistor Q.sub.28 has its emitter connected to the rail 27 and its base connected to the same rail by a resistor R.sub.140. This base is also connected to the anode of a zener diode ZD8, the cathode of which is connected by a resistor R.sub.141 to the cathodes of three diodes D.sub.39, D.sub.40 and D.sub.41 with their anodes connected to the terminals 46, 47 and 49 respectively. A capacitor C.sub.28 is connected between the cathodes of these diodes and the rail 27. The collector of the transistor Q.sub.28 is connected to the terminal 37 and also, by a resistor R.sub.142 to the rail 26.

In normal running the sequence of operations is as follows:

The thyristor SCR1 is fired when the output of the current comparator operational amplifier A.sub.5 goes low provided that the signal at terminal 39 is high (i.e. There ae currently no pulses being produced by timers T.sub.3, T.sub.5 and T.sub.6) and the signal at terminal 40 is low (i.e. there is an adequate charge for commutation on the capacitor 19).

When the output of the amplifier A.sub.5 goes high the timer T.sub.1 is held reset (it will not still be producing its output pulse) via transistor Q.sub.11 turning on when transistor Q.sub.6 turns on. Also, transistor Q.sub.12 turns on, causing transistor Q.sub.13 to turn on momentarily and triggering the timer T.sub.2 provided that the signals at terminals 45, 46 and 47 are all low (i.e. provided none of timers T.sub.5, T.sub.6 or T.sub.7 is producing a pulse). This causes firing of the thyristor SCR2 to commutate the main thyristor SCR1 current.

When the thyristor SCR2 ceases to conduct (indicating completion of commutation) the signal at the terminal 24 goes low, so that, provided the signal at terminal 49 is high (which condition exists for 2.5 mS following firing of the thyristor SCR2 because of timer T.sub.3), the timer T.sub.7 is triggered. At the end of the timer T.sub.7 output pulse timer T.sub.8 is fired (assuming that the signal at the terminal 24 has not meanwhile gone high) and the output of the timer T.sub.8 turns on the transistor Q.sub.26 and thereby resets the timer T.sub.3. Such resetting of the timer T.sub.3 causes triggering of the timer T.sub.4 which fires the thyristor SCR3. In the event of the reset pulse at R.sub.1 being "missed" for any reason, the timer T.sub.3 resets and triggers the timer T.sub.4 after its full 2.5 mS delay.

Firing of the thyristor SCR3, causes triggering of the timer T.sub.5 which triggers the timer T.sub.6 after 300 .mu.S, i.e. sufficient time for the voltage on the capacitor 19 to reverse and settle. During the 100 .mu.S pulse duration of the timer, T.sub.6, the f.e.t. Q.sub.3 is conductive and the voltage on the capacitor 19 is sampled so that the signal at terminal 30 is adjusted to set the upper and lower current limits for the next cycle. Only when the signal at the terminal 47 goes low at the end of this 100 .mu.S does the signal at the terminal 37 go high again to allow the next cycle to start.

Firing of thyristor SCR1 and SCR2 is prevented if the signal at terminal 31 goes low, but this can be overridden if required, for test purposes.

In the creep mode contact 48 is closed and the thyristors SCR2 and SCR3 are fired alternately whilst the signal at terminal 36 is high (i.e., after the motor current falls below its lower limit) so that some current can flow in the motor when the signal at terminal 36 goes low such alternate firing ceases until the motor current falls again below its lower limit.

## Claims

1. An electric vehicle traction motor control circuit comprising a main thyristor in series with the motor armature between a pair of supply rails, a second thyristor arranged on firing to divert current from the main thyristor into a commutating capacitor, a third thyristor connected in series with an inductor across the commutating capacitor and arranged on firing to reverse the voltage on the commutating capacitor, driver operable control means for determining upper and lower motor current limits, means sensitive to the magnitude of a voltage stored on the commutating capacitor for downwardly adjusting said motor current limits independently of said driver operable control means if said stored voltage is too low to ensure commutation, first firing control means for firing the main thyristor when the actual motor current is less than said lower limit, second firing control means for firing the second thyristor when the actual motor current exceeds the upper limit and third firing control means for the third thyristor.

2. An electric vehicle traction motor control circuit as claimed in claim 1 in which said capacitor voltage sensitive means comprises means coupling said capacitor voltage to an amplifier, the output of which is related to the capacitor voltage, and a sample and hold circuit, whereby the output voltage of said amplifier is sampled periodically in synchronism with the operation of the motor control circuit.

3. An electric vehicle traction motor control circuit as claimed in claim 2 in which said sample and hold circuit has a control terminal connected to the firing control means so as to cause sampling of the amplifier outlet in an interval between firing of the third thyristor and firing of the second thyristor.

4. An electric vehicle traction motor control circuit as claimed in claim 3 in which a delay circuit is provided which is connected to the third thyristor firing means for causing said sample and hold circuit to sample the amplifier output a fixed delay after firing of the third thyristor.

5. An electric vehicle traction motor control circuit as claimed in claim 1 in which said driver operable control means includes a current demand signal generator and said first and second firing control means includes a common comparator having a feedback circuit whereby said upper and lower limits are established, said comparator receiving the demand signal and a signal corresponding to the actual motor current and said commutating capacitor voltage sensing means acting to overringly limit the demand signal to a level determined by the commutating capacitor voltage.

6. An electric vehicle traction motor control circuit as claimed in claim 5 in which said current demand signal generator is connected to the comparator through the intermediary of a circuit including an operational amplifier, a pair of series resistors connecting the output terminal of the operational amplifier to the base of an emitter follower transistor the emitter of which is connected to the comparator, a capacitor connecting the junction of the series resistor to a supply rail and a feedback resistor connecting the emitter of the emitter follower transistor to the inverting input terminal of the operational amplifier, the commutating capacitor voltage sensitive means including a diode connected to the base of said emitter follower transistor whereby said means can reduce the base voltage of the emitter follower transistor, but not increase such base voltage.