# Patent

## Title
Transition time measurement of PAM4 transmitters

## Abstract

Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmitting a four-level test pattern, which is captured and digitized. The digitized data is processed to generate a linear-fitted waveform. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured and used to derive 20% and 80% VMA levels in an eye diagram. The rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and the fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

## Background
FIELD OF THE INVENTION
The field of invention relates generally to high-speed interconnects and, more specifically but not exclusively relates to techniques for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter.
BACKGROUND INFORMATION
Ever since the introduction of the microprocessor, computer systems have been getting faster and faster. In approximate accordance with Moore's law (based on Intel® Corporation co-founder Gordon Moore's 1965 publication predicting the number of transistors on integrated circuits to double every two years), the speed increase has shot upward at a fairly even rate for nearly three decades. At the same time, the size of both memory and non-volatile storage has also steadily increased, such that many of today's personal computers are more powerful than supercomputers from just 10-15 years ago. In addition, the speed of network communications has likewise seen astronomical increases.
Increases in processor speeds, memory, storage, and network bandwidth technologies have resulted in the build-out and deployment of networks with ever substantial capacities. More recently, the introduction of cloud-based services, such as those provided by Amazon (e.g., Amazon Elastic Compute Cloud (EC2) and Simple Storage Service (S3)) and Microsoft (e.g., Azure and Office 365) has resulted in additional network build-out for public network infrastructure, in addition to the deployment of massive data centers to support these services which employ private network infrastructure.
A typical data center deployment includes a large number of server racks, each housing multiple rack-mounted servers or blade servers. Communications between the rack-mounted servers is typically facilitated using the Ethernet (IEEE 802.3) protocol over copper wire cables. In addition to the option of using wire cables, blade servers and network switches and routers may be configured to support communication between blades or cards in a rack over an electrical backplane or mid-plane interconnect.
In recent years, the speed of Ethernet connections over copper wiring has reached the 10 Gigabits per second (Gpbs) and 40 Gpbs level. Moreover, The IEEE (Institute of Electrical and Electronics Engineers) is currently developing a specification (IEEE 802.3bj) defining a new backplane PHY type called 100 GBASE-KP4 that is targeted for a bandwidth of 100 Gbps over electrical backplanes with a loss up to 33 dB at 7 GHz. A similar specification for a new 100 Gbps over a cable connection is also being defined by the IEEE.



BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:
FIG. 1 is a schematic diagram illustrating the structure of a 100 GBASE-KP4 link, according to one embodiment;
FIG. 2 is a diagram illustrating mapping for PAM4 encoding;
FIG. 3 is a training state diagram for a 10 GBASE-KR PHY;
FIG. 4a is a diagram showing the components of a training frame, according to one embodiment;
FIG. 4b is a schematic diagram illustrating a training frame and exemplary signaling, according to one embodiment;
FIG. 5a is a schematic diagram illustrating the relationship between the Data Link and Physical layers of the OSI reference model and IEEE 802.3 LAN CSMA/CD LAN model layers corresponding to the current draft of 100 GBASE-KP4 defined in IEEE P802.3bj Draft 1.2;
FIG. 5b is a schematic diagram illustrating further details of selected LAN CSMA/CD layers in FIG. 5a; 
FIG. 6 is a transmit adaption process diagram illustrating operations performed by the PMA sublayer during link up transmit operations.
FIG. 6a is a transmit adaption process diagram illustrating operations performed by the PMA sublayer during transmission of the Frame Marker and Control Channel portions of an ALERT frame; according to one embodiment;
FIG. 6b is a transmit adaption process diagram illustrating operations performed by the PMA sublayer during transmission of the Training Pattern portion of an ALERT frame; according to one embodiment;
FIG. 7 is a receive adaption process diagram illustrating operations performed by the PMA sub-layer during link up receive operations.
FIG. 7a is a receive adaption process diagram illustrating operations performed by the PMA sublayer during receiving of the Frame Marker and Control Channel portions of an ALERT frame; according to one embodiment;
FIG. 7b is a receive adaption process diagram illustrating operations performed by the PMA sublayer during receiving of the Training Pattern portion of an ALERT frame; according to one embodiment;
FIG. 8 is a flowchart illustrating operations performed during a transition time measurement test procedure, according to one embodiment;
FIG. 9 is a schematic diagram illustrating a functional model for a transmit equalizer, according to one embodiment;
FIG. 10 is a table illustrating exemplary encodings for cells in Coefficient Update fields;
FIG. 11 is a table illustrating exemplary encodings for cells in Status Report fields;
FIG. 12 is a table illustrating parameters used to compute a linear pulse fit and equalizing filter values;
FIG. 13a is an eye diagram corresponding to a linear-fitted transmitter waveform;
FIG. 13b shows how a transition rise time is calculated using the eye diagram of FIG. 13a, according to one embodiment;
FIG. 13c shows how a transition fall time is calculated using the eye diagram of FIG. 13a, according to one embodiment;
FIG. 14 illustrates an exemplary set of four PRBS13 initiation states;
FIG. 15a is a schematic diagram of a transmitter test fixture, according to one embodiment;
FIG. 15b is a schematic diagram of a transition time test measurement system, according to one embodiment; and
FIG. 16 is a schematic diagram illustrating an architecture for a network node employing a network chip configured to meet the transmitter rise and fall transition time requirements defined for a 100 GBASE-KP4 transmitter.



DETAILED DESCRIPTION
Embodiments of methods, apparatus and systems for measuring signal transition times for four-level pulse modulated amplitude (PAM4) transmitters are described herein. In the following description, numerous specific details are set forth (such as implementation of a PAM4 transmitter for a 100 Gbps Ethernet link) to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Embodiments for measuring transition times for PAM4 transmitters including the transmitters for the proposed 100 GBASE-KP4 PHY are disclosed herein. In order to preserve compatibility with existing training mechanisms, some aspects of link training for the 100 GBASE-KP4 PHY are common to similar aspects defined for the IEEE 10 GBASE-KR PHY, which is targeted at 10 Gbps links and is currently employed in various types of equipment such as switches and routers. Additionally, there are other common aspects that are defined in IEEE Std 802.3ap-2007. While these common aspects may be identified and briefly discussed herein, corresponding detailed discussions of how these aspects may operate or be implemented are generally not provided herein in order to not obscure inventive aspects of the embodiments. Other aspects of some embodiments are described in further detail in IEEE P802.3bj Draft 1.2 and IEEE P802.3bh Draft 3.1.
The Physical layer (also referred to a “PHY”) structure of one embodiment of a 100 GBASE-KP4 link is illustrated in FIG. 1. The PHY defines the physical structure of the interconnect and is responsible for dealing with details of operation of the signals on a particular link between two link partners, such as depicted by components A and B. This layer manages data transfer on the signal wires, including electrical levels, timing aspects, and logical issues involved in sending and receiving each bit of information across the parallel lanes. As shown in FIG. 1, the physical connectivity of each interconnect link is made up of four differential pairs of signals 100, comprising lanes 0-3 in each direction. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components. This supports traffic in both directions simultaneously.
Components with 100 GBASE-KP4 ports communicate using a pair of uni-directional point-to-point links, defined as a link pair, as shown in FIG. 1. Each port comprises a Transmit (Tx) link interface and a Receive (Rx) link interface. For the illustrated example, Component A has a Tx port 102 that is connected to Component B Rx port 104. Meanwhile, Component B has a Tx port 104 that is connected to Component B Rx port 108. One uni-directional link transmits from Component A to Component B, and the other link transmits from Component B to Component A. The “transmit” link and “receive” link is defined relative to which component port is transmitting and which is receiving data. In the configuration illustrated in FIG. 1, the Component A transmit link transmits data from the Component A Tx port 102 to the Component B Rx port 104. This same Component A transmit link is the Port B receive link.
The 100 GBASE-KP4 PHY uses a four-level pulse amplitude modulation (referred to as PAM4) signal to send and receive data across the channel. As shown in FIG. 2, PAM4 consists of four logical levels that are mapped as follows:













0
maps to −1


1
maps to −1⁄3


2
maps to +1⁄3


3
maps to +1









Logical levels 0 and 3 respectively correspond to low and high level signals having signal levels −1 and +1, while logical levels 1 and 2 correspond to intermediate level signals have signal levels −1⁄3 and +1⁄3.

The physical signaling for the 100 GBASE-KP4 PHY employs a Unit Interval (UI) having a time corresponding to 13.59375 Gbd symbols ( ̃73.6 psec). In one embodiment a Training Frame Word (TFW) of 46 UI is employed for link training Each TFW corresponds to one full 92-bit terminated blocks (TB92).
In one embodiment, the format for the training sequence for the 100 GBASE-KP4 PHY is similar to that employed for the 10 GBASE-KR PHY defined in the IEEE Std. 802.3ap-2007 specification. The training state diagram for 10 GBASE-KR PHY is shown in FIG. 3. A significant difference between the 10 GBASE-KR PHY and the 100 GBASE-KP4 PHY is that the former defines a NRZ (Non-return to Zero) two-level (PAM2) PHY rather than a four-level PAM4 signal.
The 100 GBASE-KP4 link is established using the following sequence:
(1) Auto-negotiate capabilities to link partner
(2) Send out training sequence to tune PHY for the channel's characteristics

    
    
        Obtain Frame Lock
        TX FFE handshake: Adapt Tx coefficients to channel characteristics
        DSP converged: Train Rx to channel
        Status Exchange Ready or not?
    
    


(3) Countdown to data mode and Send out idle symbols
The training frame is a fixed length structure that is sent continuously during training. As shown in FIG. 4a, in one embodiment, a training frame 400 includes a Frame Marker 402 comprising 1 TB92, a Control Channel including a Coefficient Update 404 comprising 4 TB92 and a Status Report 406 comprising 5 TB92, and a Training Pattern 408 comprising 338 TB92 for a total of length of 348 TB92s or 348 TFWs. Further details of training frame 400 are shown in FIG. 4b and discussed below.
In one embodiment, training Frames are delimited by the bit pattern, hexadecimal 3FFFFFF800000 (23 ones followed by 23 zeros in which the ones are +1 PAM4 symbols and the zeros are −1 PAM4 symbols), as expressed in 13.59375 Gbd symbols. This is illustrated by the Frame Markers shown in FIG. 4b. 
FIG. 5a shows details of the relationship between the Data Link and Physical layers of the OSI reference model and IEEE 802.3 LAN CSMA/CD LAN model layers corresponding to the current draft of 100 GBASE-KP4 defined in IEEE P802.3bj Draft 1.2. FIG. 5b shows further details of selected LAN CSMA/CD layers, including a MAC (Media Access Control) layer 500, a 100 GBASE-R Physical Coding Sublayer (PCS) sublayer 502, a Forward Error Correction (FEC) sublayer 504, a Physical Media Attachment (PMA) sublayer 506, a Physical Media Dependent (PMD) sublayer 508, and an Auto-Negotiation (AN) sublayer 510. Data is received in digital format as a binary bit stream by MAC layer 500, which processes and forwards the binary data to 100 GBASE-R PCS sublayer 502, which applies digital rules to the binary data to transform the data as described below. The transformed digital data are then passed to FEC sublayer 504, which performs Forward Error Correction. FEC uses the coding gain to increase the link budget and BER performance on a given channel. The link budget consists of the electrical parameters which define the connection between the transmit circuitry and the receive circuitry, such as insertion loss, return loss, pulse response, etc.
In the transmit direction, the role of PMA sublayer 506 is to adapt the signal output by FEC sublayer 504 to a PAM4 encoded signal to be passed to PMD sublayer 508 and AN sublayer 510 for transfer over the attached medium. One embodiment of the adaptation processes shown in FIG. 6 includes an insert overhead block 602, an insert termination bits block 604, a Gray coding block 606, a [1/(1+D) mod 4] precoding block 608, and a PAM4 encoding block 610.
In further detail, incoming data 600 in FIG. 6 is received by PMA sublayer 506 from FEC sublayer 504 comprising a PMA:IS_UNITDATA_i.request (where i=0 to 3) primitive used to define the transfer of four streams of a data from the PMA client to PMA. The data conveyed by PMA:IS_UNITDATA—0.request to PMA:IS_UNITDATA—3.request consists of four parallel streams of encoded bits, one stream for each of lanes 0-3. Each tx_bit parameter is either a ‘1’ or ‘0’. The start parameter is TRUE to indicate that the concurrent tx_bit is the first bit of the first, second, third, or fourth FEC symbol in the FEC codeword, or is otherwise FALSE. On each transaction, tx-bit is assigned F(i, m, n), where i is the lane number, m is an index indicating the FEC codeword number and increments at the start of each codeword, and n is an index indicating the bit number within the codeword.
Insert overhead block 602 creates a sequence of overhead frames by inserting 40 overhead bits for every 31280 FEC bits. The FEC bits, F(i, m, n) are mapped into a continuous sequence of overhead frames. The overhead frame is 31320 bits in length. Each bit in the overhead frame is denoted V(i, p, q), where: i is the lane number; p is an index that indicates the frame number and increments at the start of each frame; and q is an index that indicates the bit number within a frame with a range 1 to 31320. The first 40 bits of the frame, V(i, p, 1) to V(i, p, 40) are the overhead bits. The next 31280 bits, V(i, p, 41) to Vi, p, 31320) are composed of the bits from 23 consecutive FEC codewords.
The overhead bits are inserted in the frame as follows:
V(i, p, 1)=H(i, p, 1)
V(i, p, 2)=H(i, p, 2)
V(i, p, . . . )=H(i, p, . . . )
V(i, p, 40)=H(i, p, 40)
The FEC codeword bits are aligned such that V(i, p, 41) is the first bit of a codeword, e.g., V(i, p, 41)=F(i, m, 1). The FEC bits are inserted into the frame in the order in which they were received from the FEC, e.g., V(i, p, 42)=F(i, m, 2), V(i, p, 43)=F(i, m, 3), and so on.
Insert termination bits block 604 creates a sequence of termination blocks by inserting a two termination bits for every 90 overhead frame bits. The termination block is the 92 bits in length, the same as a TFW. Each bit in a termination block is denoted T(i, r, s), where: i is the lane number; r is an index indicating block number and increments at the start of each block; and s is an index indicating the bit number within a termination block with a range 1 to 92. The first two bits of each termination block, T(i, r, 1) and T(i, r, 2) are populated with the output of a 13-bit Pseudo Random Bit Sequence (PRBS13) Generator R(i,v), where T(i, r, 1)=R(i,v) and T(i, r, 2)=R(i,v+1). The remaining 90 bits of each termination block, T(i, r, 3) to T(i, r, 92), are overhead frame bits, as discussed above. The frame bits are aligned with the termination blocks such that the first bit of an overhead bit, V(i, p, 1), corresponds to the third bit of a termination block, T(i, r, 3). Overhead frame bits are mapped to the termination blocks in order of location within the overhead frame, e.g., T(i, r, 4)=V(i, p, 2), T(i, r, 5)=V(i, p, 3), and so on. The termination bit PRBS13 generator is initialized during the training process. When training is complete the state of the termination bit PRBS13 generator is retained and the resulting output is used for the termination bits in the PMA frame.
The PMA sublayer next maps consecutive pairs of bits to one of four Gray-coded via Gray coding block 606. Each pair of bits, {A, B}, of each termination block are converted to a Gray-coded symbol with one of the four Gray-coded levels as follows:
{0, 0} maps to 0,
{0, 1} maps to 1,
{1, 1} maps to 2, and
{1, 0} maps to 3.
Gray-coded symbols corresponding to each termination block are denoted G(i, r, t), where: i is the lane number; r is an index indicating the termination block number; and t is an index indicating the symbol number within a termination block with a range 1 to 46. Pairing of bits is such that the first two bits of each termination block, T(i, r, 1) and T(i, r, 2), form a pair. Each bit pair {T(i, r, 2t−1), T(i, r, 2t)} maps to {A, B} and the Gray-coded result is assigned to G(i, r, t). The gray-coded symbol G(i, r, 1) is formed from the first two bits of a termination block, the termination bits, thus forming a termination symbol.
Precoding of the Gray-coded symbols is next performed by [1/(1+D) mod 4] precoding block 608. The precoder output symbols are denoted, P(i, r, t), where: i is the lane number; r is an index indicating the termination block number; and t is an index indicating the symbol number within a termination block with a range 1 to 46. For each Gray-coded symbol G(i, r, t), a precoded symbol, P(i, r, t) is determined by the following algorithm:
If t=1 then

P(i,r,t)=G(i,r,t)

Else

P(i,r,t)=(G(i,r,t)−P(i,r,t−1))mod 4

End If
The bits contributing to the Gray-coded termination symbol, G(i, r, 1), are the termination bits. The precoding algorithm applies this symbol directly to the output rather than combining it with the previous non-deterministic symbols and thus this termination symbol is always deterministic.
The last operation performed by PMA sublayer 506 is PAM4 encoding performed by PAM4 encoding block 610. The PAM4 encoded symbols are denoted M(i, u), where i is the lane number and u is an index indicating the symbol number. Each consecutive precoder output symbol, P(i, r, t), is mapped to one of four PAM4 levels and assigned to the PAM4 encoder output M(i, u). Mapping from the precoder output symbol P(i, r, t) to a PAM4 encoded symbol M(i, u) is shown in FIG. 2 and discussed above.
In the received direction, the role of the 100 GBASE-KP4 PMA is to adapt the PAM4 encoded signal from the PMD to a FEC encoded signal to be passed to the FEC for further processing. One embodiment of the adaptation processes are shown in FIG. 7 and include a PAM4 decoding block 700, a [(1+D) mod 4] coding block 702, an inverse Gray coding block 704, a remove termination bits block 706, and a remove overhead block 708. In general terms, each of these blocks performs an inverse operation to a corresponding block in FIG. 6 described above. Accordingly, further details are not provided herein.
To simplify the link establishment process discussed above when TRANSMIT(TRAINING) as shown in FIG. 3, the PAM4 multi-level signaling is not used for the Frame Marker, Coefficient Update, and Status Report data. During the transmission of Frame Marker 402, Coefficient Update 404, and Status Report 406, the PAM4 transmitter bypasses the overhead frame, termination block, gray coding, and 1/(1+D) mod 4 precoding stages of the PMA transmit and receive functional specifications. This is illustrated in FIG. 6a, wherein data 614 is redirected by a multiplexer (MUX) 612 to PAM4 encoding block 610, by passing each of insert overhead block 602, insert termination bits block 604, Gray coding block 606, and [1/(1+D) mod 4] precoding block 608. Therefore, the output levels are restricted to the −1 PAM4 symbol level for a logic 0 and the +1 PAM4 symbol level for a logic 1 to enable easy receiver lock to the training pattern over poor quality and non-equalized channels.
The corresponding receiver operations for processing received data during transmission of Frame Marker 402, Coefficient Update 404, and Status Report 406 are shown in FIG. 7a. As illustrated, a MUX 712 is configured to output data 714 from PAM4 decoding block 600, bypassing the operations of [(1+D) mod 4] coding block 702, inverse Gray coding block 704, remove termination bits block 706, and remove overhead block 708.
In one embodiment, Training Pattern 408 uses the PMA transmit and receive functional specifications as currently defined in IEEE P802.3bj Draft 1.2 to enable the transmitter and receiver to exercise termination block, gray coding, and 1/(1+D) mod 4 precoding stages, while the overhead framer is bypassed. Corresponding block diagrams to facilitate the transmitter and receiver operations are shown in FIGS. 6b and 7b, respectively. Training Pattern 408 employs all four levels of PAM4 signaling to facilitate receiver calibration.
In one embodiment, input data 616 to the termination block logic (i.e., insert termination bits block 604 in FIG. 6b) comprises a 13-bit Pseudo Random Bit Sequence known as PRBS13. PRBS13 is a 8191 bit sequence derived from a Fibonacci LFSR with polynomial function,

G(x)=1+x+x2+x12+x13 

In one embodiment, each TFW termination block in the training pattern comprises 92 bits of PRBS13, with the first two bits comprising termination bits. In one embodiment training pattern 408 comprises three full sequences (i.e., 8191 bits) of PRBS13 data plus a truncated PRBS13 sequence of 6523 bits for a total of 31096 bits that are transmitted during the 338 TB92 blocks (338 TFWs) corresponding to Training Pattern 408, as shown in FIGS. 4b, 4c and 13. In one embodiment, the second PRBS13 sequence comprises a bit inversion of the first, as depicted by PRBS13a and PRBS13b in FIG. 4c, while the first and third PRBS13 sequences PRBS13a and PRBS13c are the same. In addition the truncated PRBS13 sequence is also an inverted portion of the first 6523 bits of PRBS13a.
Transition Time Measurement
In high-speed signaling communication standard, the transmitted data is converted by a physical medium-dependent (PMD) device to a physical voltage signal. Ideally, the voltage signal should have one of M several possible voltage levels (e.g. M=2 for the PAM2 signaling scheme, which maps “0” bits to one level and “1” bits to another level). The transitions between these levels should occur only at specific times (integer multiples of a UI) that correspond to a perfect clock. Accordingly, a clock with the same frequency is used in a receiver in order to sample the received signal and reconstruct the transmitted data.
In practice, the voltage levels generated by transmitters deviate from the desired levels, as do the timing of transitions between levels. The voltage deviations create noise that adds up to other noise sources and reduces the noise immunity of the receiver. The timing deviations may also be considered as additional noise, and might also cause the receiver clock to sample at incorrect times. Thus, communication standards that specify voltages and frequencies, typically limit the allowed deviations from the specified values.
Timing deviations observed on the transmitted signal are called “jitter”. Jitter specifications are an important part of high-speed signaling standards. As the signaling speed increases, the UI gets shorter and jitter should decrease proportionally. The jitter specifications are thus typically stated as fractions of a UI.
Jitter is typically separated into low frequency and high frequency components. Low frequency jitter (sometimes called “drift or “wander”) typically originates from PLL phase noise. It is assumed to be tracked by the receiver, and thus is of low interest. High frequency jitter is created either from PLL phase noise or from other causes; It is assumed to be impossible to track, and thus must be limited to prevent sampling errors in the receiver. It is sometimes further divided into components of deterministic jitter (DJ) and random jitter (RJ) to capture its statistical properties. Duty cycle distortion (DCD) is a special kind of DJ sometimes measured separately—difference between even and odd bit width (a common phenomenon in some transmitters, which has a large effect on receiver performance). DCD is also called even-odd jitter (EOJ).
For a 100 GBASE-KP4 link, transition time measurements are problematic, since the lossy printed circuit board can distort the test pattern and increase the measured “noise” (Δv2 and Δv5), although it is actually a linear effect that is mitigated by equalization.
Under a current IEEE proposal, it is assumed that a PAM4 transmitter is capable of producing a PAM2 waveform with only 2 logic levels. This requires special test modes or manipulation of internal logic paths. Moreover, there are other major problems with this approach. First, transition time measurement methods are specific to PAM2 modulation, and cannot be easily translated to higher-order PAM schemes, such as PAM4. Second, since both jitter and noise are transmitter effects that contribute to noise during a transition time measurement, it would be better to make the measurement after these artifacts have been removed. In addition, the proposed measurement scheme contains many steps, some of which require non-trivial calculations that are typically done by specialized test equipment.
In accordance with aspects of the embodiments now disclosed, distortion measurement is done in a somewhat similar manner to the method defined in clause 85 of IEEE 802.3, but with a PAM4 modulated signal instead of the original PAM2 defined for clause 85. The original method measures the linear characteristics of the transmitter by fitting a linear transfer function to the measurement; the new method focuses on the difference between the measurement and the linear-fit waveform. The fitting error includes the transmitter noise components that affect the receiver—both due to jitter and to any other effects—and thus inherently combines the previous jitter and noise specifications into one entity, and allows some trade-off between them. The fitting error signal is inspected at multiple phases of the clock driving the signal, and its worst-case phase is used to specify the signal-to-noise-and-distortion (SNDR) of the transmitter, which serves as a single figure of merit.
One novel and inventive aspect of the new transition time measurement technique is the use of a linear fitted waveform to measure the rise and fall times of the PAM4 signals. In one embodiment, the waveform is measured using a Preset setting, in which transmitter equalization is disabled. The transition times are measured from the 20% to the 80% point of the peak to peak voltage difference between a −1 PAM4 symbol and +1 PAM4 symbol of the fitted waveform eye.
With reference to the flowchart 800 of FIG. 8, one embodiment for measuring transition times for a PAM4 transmitter signal proceeds as follows. First, in a block 802, the transmitter is configured in a Preset configuration under which transmitter equalization (EQ) is turned off. The 100 GBASE-KP4 transmit function includes programmable equalization to compensate for the frequency-dependent loss of the channel and facilitate data recovery at the receiver. The functional model for the transmit equalizer is the three tap transversal filter, as shown in FIG. 9. The state of the transmit equalizer and hence the transmitted output waveform may be manipulated via the PMD control function or via a management interface. In one embodiment, the transmit function responds to a set of commands issued by a link partner's receive function and is conveyed by a back-channel communications path. With further reference to FIG. 10, in one embodiment the taps c(−1), c(0), and c(1) may be configured by setting applicable values in the coefficient update fields of a training frame, as follows.
The preset control is sent to request that the coefficients be set to a state where equalization is turned off. When received, the pre-cursor (k=−1) (Coefficient (−1) update) and post-cursor (k=+1) (Coefficient (+1) update) coefficients are set to a zero value and the main (k=0) (Coefficient (0) update) coefficient is set to its maximum value. The preset control is initially sent when all coefficient status report fields (see FIG. 11) indicate not_updated [0 0], and will then continue to be sent until the status for all coefficients indicates updated or maximum. At that point, the outgoing preset control may be set to zero. With reference to the status report fields shown in FIG. 11, a maximum status value [1 1] is returned when the main coefficient is updated. Similarly a maximum status value will be returned for the pre-cursor and/or post-cursor coefficients when the coefficient is updated and zero is its maximum supported value. Alternatively, an updated status value [0 1] will be returned for the pre-cursor and/or post-cursor coefficients when the coefficient is updated and it supports additional settings above the value zero.
After the Preset transmitter configuration is set, a test pattern is repetitively transmitted from the transmitter, as shown in a block 804. In one embodiment, the training pattern portion of training frame 400 of FIG. 4b is used for the test pattern. In one embodiment, the test pattern comprises a 13-bit Quardinary (i.e., four-level) PRBS (QPRBS13) that is repetitively transmitted.
As the test pattern is transmitted, transmitted signal waveform data is captured in block 808 using a sampling rate M times the signaling rate over one or more complete test pattern cycles. In one embodiment M≧7 or greater. The captured waveform represents an integer number of repetitions of the test pattern totaling N bits. Hence the length of the captured waveform should be MN samples. The waveform should be aligned such that the first M samples of the waveform correspond to the first bit of the test pattern, the second M samples to the second bit, and so on. The captured waveform is defined as y(k).
Next, in block 808, a linear fit to the captured waveform and a linear fit pulse response p(k) is computed. For aligned symbol values x(n), PAM4 signal levels −1, −1⁄3, 1⁄3, and 1 are used to represent symbol values of 0, 1, 2, and 3, respectively. The parameters of the linear fit pulse and the equalizing filter are shown in the table of FIG. 12.
Given the captured waveform y(k) and corresponding aligned symbols x(n) derived from the operation of block 808, the following M-by-N waveform matrix Y is defined, as shown in Equation (1).




  
    
      
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                      ⁢
                      
                        
                      
                      ⁢
                      M
                    
                    )
                  
                
              
              
                ...
              
              
                
                  y
                  ⁡
                  
                    (
                    MN
                    )
                  
                
              
            
          
          ]
        
      
    
    
      
        (
        1
        )
      
    
  




Next, the symbols vector x are rotated by the specified linear fit pulse delay Dp (see FIG. 12) to yield xr as shown in Equation (2).

xr=[x(Dp+1)x(Dp+2) . . . x(N)x(1) . . . x(Dp)]  (2)

The following matrix X is then defined to be an N-by-N matrix derived from xr, as shown in Equation (3).





  
    
      
        X
        =
        
          [
          
            
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
              
              
                ...
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    N
                    )
                  
                
              
            
            
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    N
                    )
                  
                
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
              
              
                ...
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    
                      N
                      -
                      1
                    
                    )
                  
                
              
            
            
              
                ...
              
              
                ...
              
              
                ...
              
              
                ...
              
            
            
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    3
                    )
                  
                
              
              
                ...
              
              
                
                  
                    x
                    r
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
              
            
          
          ]
        
      
    
    
      
        (
        3
        )
      
    
  




Next, the matrix X1 is defined to be the first Np rows of X concatenated with a row vector of ones of length N. The M-by-(Np+1) coefficient matrix, P, corresponding to the linear fit is then defined by Equation (4). The superscript “T” denotes the matrix transpose operator.

P=YX1T(X1X1T)−1  (4)

The error waveform, e(k), is then read column-wise from the elements of E as shown in Equation (5).





  
    
      
        E
        =
        
          
            
              PX
              1
            
            -
            Y
          
          =
          
            [
            
              
                
                  
                    e
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    e
                    ⁡
                    
                      (
                      
                        M
                        +
                        1
                      
                      )
                    
                  
                
                
                  ...
                
                
                  
                    e
                    ⁡
                    
                      (
                      
                        
                          M
                          ⁡
                          
                            (
                            
                              N
                              -
                              1
                            
                            )
                          
                        
                        +
                        1
                      
                      )
                    
                  
                
              
              
                
                  
                    e
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  
                    e
                    ⁡
                    
                      (
                      
                        M
                        +
                        2
                      
                      )
                    
                  
                
                
                  ...
                
                
                  
                    e
                    ⁡
                    
                      (
                      
                        
                          M
                          ⁡
                          
                            (
                            
                              N
                              -
                              1
                            
                            )
                          
                        
                        +
                        2
                      
                      )
                    
                  
                
              
              
                
                  ...
                
                
                  ...
                
                
                  ...
                
                
                  ...
                
              
              
                
                  
                    e
                    ⁡
                    
                      (
                      M
                      )
                    
                  
                
                
                  
                    e
                    ⁡
                    
                      (
                      
                        2
                        ⁢
                        
                          
                        
                        ⁢
                        M
                      
                      )
                    
                  
                
                
                  ...
                
                
                  
                    e
                    ⁡
                    
                      (
                      MN
                      )
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        5
        )
      
    
  




The matrix P1 is then defined to be a matrix consisting of the first Np columns of the matrix P as shown in Equation (6). The linear fit pulse response, p(k), is then read column-wise from the elements of P1.





  
    
      
        
          P
          1
        
        =
        
          [
          
            
              
                
                  p
                  ⁡
                  
                    (
                    1
                    )
                  
                
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      M
                      +
                      1
                    
                    )
                  
                
              
              
                ...
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      
                        M
                        ⁡
                        
                          (
                          
                            
                              N
                              p
                            
                            -
                            1
                          
                          )
                        
                      
                      +
                      1
                    
                    )
                  
                
              
            
            
              
                
                  p
                  ⁡
                  
                    (
                    2
                    )
                  
                
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      M
                      +
                      2
                    
                    )
                  
                
              
              
                ...
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      
                        M
                        ⁡
                        
                          (
                          
                            
                              N
                              p
                            
                            -
                            1
                          
                          )
                        
                      
                      +
                      2
                    
                    )
                  
                
              
            
            
              
                ...
              
              
                ...
              
              
                ...
              
              
                ...
              
            
            
              
                
                  p
                  ⁡
                  
                    (
                    M
                    )
                  
                
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      M
                    
                    )
                  
                
              
              
                ...
              
              
                
                  p
                  ⁡
                  
                    (
                    
                      MN
                      P
                    
                    )
                  
                
              
            
          
          ]
        
      
    
    
      
        (
        6
        )
      
    
  




The fitted waveform is calculated from the matrix product Ŷ=PX1; the data is folded into a set of waveforms y(n), each spanning 2 UI:

y(n)=[Ŷ(1,2n−1)Ŷ(2,2n−1) . . . Ŷ(M,2n−1)Ŷ(1,2n)Ŷ(2,2n) . . . Ŷ(M,2n)]T 

This set of waveforms, drawn on top of each other, is referred to as a 2-UI eye diagram, and represents sets of linear-fitted captured waveforms corresponding to changes in voltage levels when transmitted signal levels are switched between the four PAM4 logical signal levels (−1, − 1/3, + 1/3, +1).

Continuing at a block 810, the next operation is to measure the voltage modulation amplitude (VMA) values for the +1 PMA signal level and the −1 PMA signal level. As shown in FIG. 13b, in one embodiment this is performed by measuring VMA proximate to the midpoint between the eyes (over approximately 20% of a UI). The −1 PMA VMA value is defined to be 0% VMA, while the +1 PMA VMA value is defined to be 100% VMA. Voltage levels for 20% VMA and 80% VMA are then determined relative to the 0% and 100% VMA voltage levels, as further shown in FIG. 13b. 
At this point the transition rise and fall times are measured, as respectively depicted in blocks 812 and 814. The transition rise time Tr is determined by measuring the time between the 20% and 80% VMA voltage levels corresponding to a PAM4 signal transitioning from a −1 PMA signal level to a +1 PMA signal level, as shown in FIG. 13b. A transition fall time Tf is determined in a similar manner by measuring the time between the 80% and 20% VMA voltage levels corresponding to a PAM4 signal transitioning from a +1 PMA signal level to a −1 PMA signal level, as shown in FIG. 13c. The foregoing measurements may be performed using a graphical representation of the eye diagram, or may be calculated using a numerical method of captured data.
The foregoing process is performed for each of the four transmitter lanes. In one embodiment, the transmitted test patterns employ initial states for the PRBS13, gray code, and precoder data sequences shown in FIG. 14. For each physical lane i=0 . . . 3, the training sequence shall start from state Si. This will also uniquely identify the lanes if they are swapped, and save lane order identification later on.
FIGS. 15a and 15b respectively show a transmitter text fixture configuration and a transmitter transition test system configuration, according to one embodiment. In the illustrated embodiment, the device under test (DUT) may comprise a network interface chip, such as a Network Interface Controller (NIC) chip, or it may comprise an apparatus including a network interface or the like. As shown in FIG. 15a, a device 1500 is mounted to a device package 1502, which in turn in mounted to a printed circuit board (PCB) in which wiring paths are embedded for facilitating a 100 GBASE-KP4 Ethernet backplane link. SLi<p>, and SLi<n> correspond to the signal paths for the plus and minus differential signals for a given lane Li.
Under the test system configuration of FIG. 15b, signals from the transmitter of a DUT 1550 are received and captured by a waveform capture apparatus 1552 comprising a digital oscilloscope or data acquisition module. A post processing module or apparatus 1554 is interfaced to waveform capture apparatus 1552, and is configured to perform the post-processing operations of blocks 808, 810, 812, and 814 of flowchart 800. In one embodiment, facilities for implementing post processing operations are provided via waveform capture apparatus 1552, such that a single apparatus is used for capturing transmitter waveform signals and determining transition time rise and fall times. In one embodiment the single apparatus comprises a computer with a data acquisition board configured to perform waveform capture. In another embodiment, a programmable digital oscilloscope is used. In either case, the post processing operations of blocks 808, 810, 812, and 814 may be implemented via corresponding software instructions that are configured to be executed by a processor or embedded logic in either the computer or programmable digital oscilloscope, as applicable.
In one embodiment, the transition times Tr and Tf for a 100 GBASE-KP4 meet qualification criteria if they are >18 ps (25% of  ̃73 ps UI), as determined by the foregoing transition time measurement technique. Accordingly, an apparatus including a network interface having a transmitter configured to implement a 100 GBASE-KP4 link is qualified under the proposed 100 GBASE-KP4 if the measured transition rise and fall times are >18 ps for each lane.
FIG. 16 shows an architecture 1600 for a network node employing an apparatus comprising a network chip 1602 including transmitter circuitry configured to transmit PAM4 signals meeting the rise and fall transition time requirements defined by 100 GBASE-KP4, where the rise and fall transition times are measured in accordance with aspects of the embodiments disclosed herein. Network chip 1602 comprises PHY circuitry 1604 including a PCS module 1606, an auto-negotiation module 1608, a link training module 1610, a transmitter port 1612 including transmitter circuitry 1613 and a receiver port 1614 including receiver circuitry 1615. Network chip 1602 further includes a DMA (Direct Memory Access) interface 1616, a Peripheral Component Interconnect Express (PCIe) interface 1618, a MAC module 1620 and a Reconciliation Sublayer (RS) module 1622. Network node 1600 also comprises a System on a Chip (SoC) 1624 including a Central Processing Unit (CPU) 1626 having one or more processor cores, coupled to a memory interface 1628 and a PCIe interface 1630 via an interconnect 1632. Memory interface 1628 is further depicted as being coupled to memory 1634. Under a typical configuration, network chip 1602, SoC 1624 and memory 1634 will be mounted on or otherwise operatively coupled to a circuit board 1636 that includes wiring traces for coupling these components in communication, as depicted by single lines connecting DMA 1616 to memory 1634 and PCIe interface 1618 to PCIe interface 1630 at a PCIe port 1638.
In one embodiment, MAC module 1620 is configured to implement aspects of the MAC layer operations performed by embodiments described herein. Similar, RS module 1622 is configured to implement reconciliation sub-layer operations performed by embodiments described herein, such as illustrated in FIG. 5a. 
Link training module 1610 is further depicted as including QPRBS13 test pattern generator 1640, which in one embodiment is configured to generate the QPRBS13 test pattern sequences using the initial states shown in FIG. 14. Auto-negotiation module 1608 is further depicted as including a base page 1642. During link initialization prior to transmitter testing, auto-negotiation module 1608 is implemented for auto-negotiation of link speed and capabilities. The auto-negotiation format consists of a base-page (e.g., base page 1642), which is the first set of formatted information exchanged with the link partner, as depicted by a link partner 1644 including a receiver port 1646 and a transmitter port 1648. In one embodiment the configuration of node 1600 and link partner 1644 are similar. In one embodiment, the format of base page 1642 is in accordance with the base page format defined in IEEE 802.3bh Draft 3.1. Link training module 1610 is further configured to perform link training operations relating to initialization for a link 1650 communicatively coupled between network chip 1602 and link partner 1644 in accordance with aspects of the embodiments disclosed herein.
In one embodiment, network chip 1602 comprises a 100 Gbps Ethernet Network Interface Controller (NIC) chip. However, the circuitry and components of network chip 1602 may also be implemented in other types of chips and components, including SoCs, multi-chip modules, and NIC chips including support for multiple network interfaces (e.g., wired and wireless).
In addition, embodiments of the present description may be implemented not only within a semiconductor chip such as a NIC, but also within non-transient machine-readable media. For example, the designs described above may be stored upon and/or embedded within non-transient machine readable media associated with a design tool used for designing semiconductor devices. Examples include a netlist formatted in the VHSIC Hardware Description Language (VHDL) language, Verilog language or SPICE language, or other Hardware Description Language. Some netlist examples include: a behavioral level netlist, a register transfer level (RTL) netlist, a gate level netlist and a transistor level netlist. Machine-readable media also include media having layout information such as a GDS-II file. Furthermore, netlist files or other machine-readable media for semiconductor chip design may be used in a simulation environment to perform the methods of the teachings described above.
As discussed above, various aspects of the embodiments herein may be facilitated by execution of corresponding software instructions on a machine, such as a computer or module in a digital oscilloscope. Thus, embodiments of this invention may be used as or to support a software program, software modules, and/or firmware comprising instructions configured to be executed on a machine comprising some form of processing core (such as the CPU of a computer, one or more cores of a multi-core processor, etc.), or a virtual machine running on a processor or core or otherwise implemented or realized upon or within a machine-readable medium. A tangible, non-transitory machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include a read only memory (ROM), non-volatile memory (e.g., flash memory); a random access memory (RAM); a magnetic disk storage media; an optical storage media, etc.
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

## Claims

1. A method for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter, comprising:
repetitively transmitting a test pattern with the PAM4 transmitter;
capturing a waveform of the test pattern to produce digitized waveform data;
generating a linear-fitted waveform based on the digitized waveform data;
measuring, using the linear-fitted waveform, a voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level;
deriving a 20% VMA level and an 80% VMA level as a function of the VMA levels for the −1 and +1 PAM4 signal levels;
determining a rise transition time by measuring a time interval between when a rising PAM4 signal from a −1 PAM4 signal level to a +1 PAM4 signal level crosses the 20% VMA voltage level and crosses the 80% VMA voltage level; and
determining a fall transition time by measuring a time interval between when a falling PAM4 signal from a +1 PAM4 signal level to a −1 PAM4 signal level crosses the 80% VMA voltage level and crosses the 20% VMA voltage level.

2. The method of claim 1, wherein the test pattern comprises a 13-bit Quardinary Pseudo Random Bit Sequence (QPRBS13).

3. The method of claim 1, wherein generating the linear fitted waveform comprises:
computing a linear fit of the captured waveform of the test pattern using a numerical process.

4. The method of claim 1, wherein the transmitter is configurable to effect a plurality of transmitter equalization settings, and the test pattern is transmitted using a transmitter equalization setting under which equalization is turned off.

5. The method of claim 1, further comprising extracting a two unit interval window from the linear-fitted waveform, the two unit interval window having first and second sets of eyes.

6. The method of claim 1, further comprising respectively defining the 0% VMA voltage level and the 100% VMA voltage level based on a voltage level for the −1 PAM4 signal level to and the +1 PAM4 signal level during a timeframe approximately centered between the first and second sets of eyes.

7. The method of claim 1, further comprising performing the method for each of a plurality of lanes in a multi-lane communication link.

8. The method of claim 7, wherein the multi-lane communications link comprises a 100 Gigabits per second Ethernet Link.

9. The method of claim 1, further comprising:
capturing the waveform of the test pattern with one of a digital oscilloscope of acquisition module and storing corresponding digital test data;
implementing post processing operations on the digital test data via execution of software instructions to determine the rise transition time and the fall transition time.

10. A test system for measuring rise and fall transition times for a four-level pulse modulated amplitude (PAM4) transmitter, comprising:
a device under test (DUT) fixture configured to interface with a DUT including a PAM4 transmitter;
a waveform capture apparatus, configured to digitally capture a waveform of a signal comprising a test pattern transmitted by the PAM4 transmitter of the DUT during a test procedure and store corresponding digitized waveform data;
a post processing apparatus configured to,
generate a linear-fitted waveform based on the digitized waveform data;
measure, using the linear-fitted waveform, a voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level;
derive a 20% VMA level and an 80% VMA level as a function of the VMA levels for the −1 and +1 PAM4 signal levels;
determine a rise transition time by measuring a time interval between when a rising PAM4 signal from a −1 PAM4 signal level to a +1 PAM4 signal level crosses the 20% VMA voltage level and crosses the 80% VMA voltage level; and
determine a fall transition time by measuring a time interval between when a falling PAM4 signal from a +1 PAM4 signal level to a −1 PAM4 signal level crosses the 80% VMA voltage level and crosses the 20% VMA voltage level.

11. The test system of claim 10, wherein the test pattern comprises a 13-bit Quardinary Pseudo Random Bit Sequence (QPRBS13).

12. The test system of claim 10, wherein the post processing apparatus is further configured to compute a linear fit of the captured waveform of the test pattern using a numerical process.

13. The test system of claim 10, wherein the PAM4 transmitter of the DUT is configurable to effect a plurality of transmitter equalization settings, and the test system further includes a link partner that is enabled, during the testing procedure, to configured the PAM4 transmitter to operate in a transmission configuration under which transmission equalization is turned off.

14. The test system of claim 10, wherein the post processing apparatus is further configured to extract a two unit interval window of the linear-fitted waveform comprising an eye diagram having first and second sets of eyes.

15. The test system of claim 10, wherein the post processing apparatus is further configured to respectively define the 0% VMA voltage level and the 100% VMA voltage level based on a voltage level for the −1 PAM4 signal level and the +1 PAM4 signal level during a timeframe approximately centered between the first and second sets of eyes.

16. The test system of claim 10, wherein the PAM4 transmitter is configured to transmit signals over a plurality of lanes, and the waveform capture apparatus is configured to digitally capture a respective waveform signal for each of the plurality of lanes.

17. The test system of claim 10, wherein the test system is configured to qualify the rise and fall transition times for a 100 GBASE-KP4 transmitter.

18. A tangible non-transitory machine-readable medium having software instructions stored thereon, configured to be executed on a machine to measure rise and fall transition times for a four-level pulse modulated amplitude (PAM4) transmitter by performing operations comprising:
receiving digitized waveform data corresponding to a transmitted PAM4 signal waveform comprising a test pattern that has been digitally captured;
generating a linear-fitted waveform based on the digitized waveform data;
measuring, using the linear-fitted waveform, a voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level;
deriving a 20% VMA level and an 80% VMA level as a function of the VMA levels for the −1 and +1 PAM4 signal levels;
determining a rise transition time by measuring a time interval between when a rising PAM4 signal from a −1 PAM4 signal level to a +1 PAM4 signal level crosses the 20% VMA voltage level and crosses the 80% VMA voltage level; and
determining a fall transition time by measuring a time interval between when a falling PAM4 signal from a +1 PAM4 signal level to a −1 PAM4 signal level crosses the 80% VMA voltage level and crosses the 20% VMA voltage level.

19. The tangible non-transitory machine-readable medium of claim 18, wherein the software is configured to perform further operations when executed on the machine comprising computing a linear fit of the captured waveform of the test pattern using a numerical process.

20. The tangible non-transitory machine-readable medium of claim 18, wherein the software is configured to perform further operations when executed on the machine comprising extracting a two unit interval window of the linear-fitted waveform comprising an eye diagram having first and second sets of eyes.

21. The tangible non-transitory machine-readable medium of claim 18, wherein the software is configured to perform further operations when executed on the machine comprising:
defining the 0% VMA voltage level based on a voltage level for the −1 PAM4 signal level during a timeframe approximately centered between the first and second sets of eyes; and
defining the 100% VMA voltage level based on a voltage level for the +1 PAM4 signal level during a timeframe approximately centered between the first and second sets of eyes.

22. The tangible non-transitory machine-readable medium of claim 18, wherein the software is configured, via execution on a machine, to qualify the rise and fall transition times for a 100 GBASE-KP4 transmitter.

23. An apparatus, comprising:
Physical Layer (PHY) circuitry, including,
a Physical Coding Sublayer (PCS) module;
an auto-negotiation module;
a link training module;
a transmitter port including transmitter circuitry; and
a receiver port including receiver circuitry;

a Media Access Control (MAC) module;
a Reconciliation Sublayer (RS) module; and
a Peripheral Component Interconnect Express (PCIe) interface;
wherein the transmitter port is configured to transmit a plurality of four-level pulse modulated amplitude (PAM4) signals via four lanes, and wherein a design of the apparatus has been qualified to confirm the transmitted PAM4 signals meet rise and fall transition times for a 100 GBASE-KP4 transmitter by performing operations comprising:
four each of the four lanes,
repetitively transmitting a test pattern with the PAM4 transmitter;
capturing a waveform of the test pattern to produce digitized waveform data;
generating a linear-fitted waveform based on the digitized waveform data;
measuring, using the linear-fitted waveform, a voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level;
deriving a 20% VMA level and an 80% VMA level as a function of the VMA levels for the −1 and +1 PAM4 signal levels;
determining a rise transition time by measuring a time interval between when a rising PAM4 signal from a −1 PAM4 signal level to a +1 PAM4 signal level crosses the 20% VMA voltage level and crosses the 80% VMA voltage level; and
determining a fall transition time by measuring a time interval between when a falling PAM4 signal from a +1 PAM4 signal level to a −1 PAM4 signal level crosses the 80% VMA voltage level and crosses the 20% VMA voltage level.

24. The apparatus of claim 23, wherein the test pattern comprises a 13-bit Quardinary Pseudo Random Bit Sequence (QPRBS13), and wherein a different initial state of the QPRBS13 test pattern is used for each of the four lanes.

25. The apparatus of claim 23, wherein the transmitter circuitry is configurable to effect a plurality of transmitter equalization settings, and the test pattern is transmitted using a transmitter equalization setting under which equalization is turned off.