# Patent

## Title
Programmable graphics processor for multithreaded execution of programs

## Abstract

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

## Background
RELATED APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 10/696,714, entitled “Shader Cache Using a Coherency Protocol,” filed Oct. 29, 2003, now U.S. Pat. No. 7,103,720, a continuation-in-part of U.S. patent application Ser. No. 10/736,437, entitled “Methods of Processing Graphics Data Including Reading and Writing Buffers,” filed Dec. 15, 2003, now U.S. Pat. No. 7,139,003, and a continuation-in-part of U.S. patent application Ser. No. 11/292,614, entitled “System and Method for Processing Thread Groups in a SIMD Architecture,” filed Dec. 2, 2005 now U.S. Pat. No. 7,836,276. The entire contents of the foregoing applications are incorporated by reference herein.


FIELD OF THE INVENTION
One or more aspects of the invention relate generally to multithreaded processing, and more particularly to processing graphics data in a programmable graphics processor.
BACKGROUND
Current graphics data processing includes systems and methods developed to perform a specific operation on graphics data, e.g., linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. These graphics processors include several fixed function computation units to perform such specific operations on specific types of graphics data, such as vertex data and pixel data.
More recently, the computation units have a degree of programmability to perform user specified operations such that the vertex data is processed by a vertex processing unit using vertex programs and the pixel data is processed by a pixel processing unit using pixel programs. When the amount of vertex data being processed is low relative the amount of pixel data being processed, the vertex processing unit may be underutilized. Conversely, when the amount of vertex data being processed is high relative the amount of pixel data being processed, the pixel processing unit may be underutilized.
Accordingly, it would be desirable to provide improved approaches to processing different types of graphics data to better utilize one or more processing units within a graphics processor.
SUMMARY OF THE INVENTION
The present invention provides a unified approach for graphics data processing. Sample data of different types, e.g., vertex data and pixel data, are processed through the same execution pipeline.
A processing unit according to an embodiment of the present invention includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
Each execution pipeline has a plurality of sets of parallel data execution paths that run at a higher clock speed than the clock speed of the processing unit. As a result, a large number of pixels or vertices can be processed in parallel through the execution pipeline. The total number of pixels or vertices that can be processed through the execution pipelines per clock cycle of the processing unit is equal to: (the number of execution pipelines)×(the number of sets of parallel data execution paths in each execution pipeline)×(the number of parallel data execution paths in each set)×(the ratio of the clock speed of the parallel data execution paths to the processing unit clock speed).



BRIEF DESCRIPTION OF THE DRAWINGS
Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of the present invention; however, the accompanying drawing(s) should not be taken to limit the present invention to the embodiment(s) shown, but are for explanation and understanding only.
FIG. 1 illustrates one embodiment of a computing system according to the invention including a host computer and a graphics subsystem.
FIG. 2 is a block diagram of an embodiment of the programmable graphics processing pipeline of FIG. 1.
FIG. 3 is a block diagram of an embodiment of the execution pipeline of FIG. 2.
FIG. 4 is a block diagram of an alternate embodiment of the execution pipeline of FIG. 2.
FIGS. 5A and 5B are flow diagrams of exemplary embodiments of thread assignment in accordance with one or more aspects of the present invention.
FIGS. 6A and 6B are exemplary embodiments of a portion of the thread storage resource storing thread state data within an embodiment of the thread control unit of FIG. 3 or FIG. 4.
FIGS. 7A and 7B are flow diagrams of exemplary embodiments of thread allocation and processing in accordance with one or more aspects of the present invention.
FIGS. 8A and 8B are flow diagrams of exemplary embodiments of thread assignment in accordance with one or more aspects of the present invention.
FIGS. 9A and 9B are flow diagrams of exemplary embodiments of thread selection in accordance with one or more aspects of the present invention.
FIG. 10 is a block diagram of another embodiment of the programmable graphics processing pipeline of FIG. 1.
FIG. 11 illustrates an embodiment of the texture processing cluster of FIG. 10.
FIG. 12 is a block diagram of another embodiment of the execution pipeline of FIG. 2 or FIG. 11.
FIG. 13 is a block diagram of an embodiment of the instruction dispatch unit of FIG. 12.
FIG. 14 is a flow diagram that illustrates the steps of processing graphics data in accordance with one or more aspects of the present invention.



DETAILED DESCRIPTION
In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.
FIG. 1 is an illustration of a computing system generally designated 100 and including a host computer 110 and a graphics subsystem 170. Computing system 100 may be a desktop computer, server, laptop computer, palm-sized computer, tablet computer, game console, cellular telephone, computer based simulator, or the like. Host computer 110 includes host processor 114 that may include a system memory controller to interface directly to host memory 112 or may communicate with host memory 112 through a system interface 115. System interface 115 may be an I/O (input/output) interface or a bridge device including the system memory controller to interface directly to host memory 112. Examples of system interface 115 known in the art include Intel® Northbridge and Intel® Southbridge.
Host computer 110 communicates with graphics subsystem 170 via system interface 115 and a graphics interface 117 within a graphics processor 105. Data received at graphics interface 117 can be passed to a front end 130 or written to a local memory 140 through memory controller 120. Graphics processor 105 uses graphics memory to store graphics data and program instructions, where graphics data is any data that is input to or output from components within the graphics processor. Graphics memory can include portions of host memory 112, local memory 140, register files coupled to the components within graphics processor 105, and the like.
Graphics processor 105 includes, among other components, front end 130 that receives commands from host computer 110 via graphics interface 117. Front end 130 interprets and formats the commands and outputs the formatted commands and data to an IDX (index processor) 135. Some of the formatted commands are used by programmable graphics processing pipeline 150 to initiate processing of data by providing the location of program instructions or graphics data stored in memory. IDX 135, programmable graphics processing pipeline 150 and a raster analyzer 160 each include an interface to memory controller 120 through which program instructions and data can be read from memory, e.g., any combination of local memory 140 and host memory 112. When a portion of host memory 112 is used to store program instructions and data, the portion of host memory 112 can be uncached so as to increase performance of access by graphics processor 105.
IDX 135 optionally reads processed data, e.g., data written by raster analyzer 160, from memory and outputs the data, processed data and formatted commands to programmable graphics processing pipeline 150. Programmable graphics processing pipeline 150 and raster analyzer 160 each contain one or more programmable processing units to perform a variety of specialized functions. Some of these functions are table lookup, scalar and vector addition, multiplication, division, coordinate-system mapping, calculation of vector normals, tessellation, calculation of derivatives, interpolation, and the like. Programmable graphics processing pipeline 150 and raster analyzer 160 are each optionally configured such that data processing operations are performed in multiple passes through those units or in multiple passes within programmable graphics processing pipeline 150. Programmable graphics processing pipeline 150 and a raster analyzer 160 also each include a write interface to memory controller 120 through which data can be written to memory.
In a typical implementation programmable graphics processing pipeline 150 performs geometry computations, rasterization, and pixel computations. Therefore, programmable graphics processing pipeline 150 is programmed to operate on surface, primitive, vertex, fragment, pixel, sample or any other data. For simplicity, the remainder of this description will use the term “samples” to refer to graphics data such as surfaces, primitives, vertices, pixels, fragments, or the like.
Samples output by programmable graphics processing pipeline 150 are passed to a raster analyzer 160, which optionally performs near and far plane clipping and raster operations, such as stencil, z test, and the like, and saves the results or the samples output by programmable graphics processing pipeline 150 in local memory 140. When the data received by graphics subsystem 170 has been completely processed by graphics processor 105, an output 185 of graphics subsystem 170 is provided using an output controller 180. Output controller 180 is optionally configured to deliver data to a display device, network, electronic control system, other computing system 100, other graphics subsystem 170, or the like. Alternatively, data is output to a film recording device or written to a peripheral device, e.g., disk drive, tape, compact disk, or the like.
FIG. 2 is an illustration of programmable graphics processing pipeline 150 of FIG. 1. At least one set of samples is output by IDX 135 and received by programmable graphics processing pipeline 150 and the at least one set of samples is processed according to at least one program, the at least one program including graphics program instructions. A program can process one or more sets of samples. Conversely, a set of samples can be processed by a sequence of one or more programs.
Samples, such as surfaces, primitives, or the like, are received from IDX 135 by programmable graphics processing pipeline 150 and stored in a vertex input buffer 220 including a register file, FIFO (first in first out), cache, or the like (not shown). The samples are broadcast to execution pipelines 240, four of which are shown in the figure. Each execution pipeline 240 includes at least one multithreaded processing unit, to be described further herein. The samples output by vertex input buffer 220 can be processed by any one of the execution pipelines 240. A sample is accepted by an execution pipeline 240 when a processing thread within the execution pipeline 240 is available as described further herein. Each execution pipeline 240 signals to vertex input buffer 220 when a sample can be accepted or when a sample cannot be accepted. In one embodiment, programmable graphics processing pipeline 150 includes a single execution pipeline 240 containing one multithreaded processing unit. In an alternative embodiment, programmable graphics processing pipeline 150 includes a plurality of execution pipelines 240.
Execution pipelines 240 may receive first samples, such as higher-order surface data, and tessellate the first samples to generate second samples, such as vertices. Execution pipelines 240 may be configured to transform the second samples from an object-based coordinate representation (object space) to an alternatively based coordinate system such as world space or normalized device coordinates (NDC) space. Each execution pipeline 240 may communicate with texture unit 225 using a read interface (not shown in FIG. 2) to read program instructions and graphics data such as texture maps from local memory 140 or host memory 112 via memory controller 120 and a texture cache 230. Texture cache 230 serves to increase effective memory bandwidth. In an alternate embodiment texture cache 230 is omitted. In another alternate embodiment, a texture unit 225 is included in each execution pipeline 240. In another alternate embodiment, program instructions are stored within programmable graphics processing pipeline 150. In another alternate embodiment, each execution pipeline 240 has a dedicated instruction read interface to read program instructions from local memory 140 or host memory 112 via memory controller 120.
Execution pipelines 240 output processed samples, such as vertices, that are stored in a vertex output buffer 260 including a register file, FIFO, cache, or the like (not shown). Processed vertices output by vertex output buffer 260 are received by a primitive assembly/setup unit 205. Primitive assembly/setup unit 205 calculates parameters, such as deltas and slopes, to rasterize the processed vertices and outputs parameters and samples, such as vertices, to a raster unit 210. Raster unit 210 performs scan conversion on samples, such as vertices, and outputs samples, such as fragments, to a pixel input buffer 215. Alternatively, raster unit 210 resamples processed vertices and outputs additional vertices to pixel input buffer 215.
Pixel input buffer 215 outputs the samples to each execution pipeline 240. Samples, such as pixels and fragments, output by pixel input buffer 215 are each processed by only one of the execution pipelines 240. Pixel input buffer 215 determines which one of the execution pipelines 240 to output each sample to depending on an output pixel position, e.g., (x,y), associated with each sample. In this manner, each sample is output to the execution pipeline 240 designated to process samples associated with the output pixel position. In an alternate embodiment, each sample output by pixel input buffer 215 is processed by one of any available execution pipelines 240.
Each execution pipeline 240 signals to pixel input buffer 240 when a sample can be accepted or when a sample cannot be accepted as described further herein. Program instructions configure programmable computation units (PCUs) within an execution pipeline 240 to perform operations such as perspective correction, texture mapping, shading, blending, and the like. Processed samples are output from each execution pipeline 240 to a pixel output buffer 270. Pixel output buffer 270 optionally stores the processed samples in a register file, FIFO, cache, or the like (not shown). The processed samples are output from pixel output buffer 270 to raster analyzer 160.
FIG. 3 is a block diagram of an embodiment of execution pipeline 240 of FIG. 1 including at least one multithreaded processing unit 300. An execution pipeline 240 can contain a plurality of multithreaded processing units 300, each multithreaded processing unit 300 containing at least one PCU 375. PCUs 375 are configured using program instructions read by a thread control unit 320. Thread control unit 320 gathers source data specified by the program instructions and dispatches the source data and program instructions to at least one PCU 375. PCUs 375 performs computations specified by the program instructions and outputs data to at least one destination, e.g., pixel output buffer 160, vertex output buffer 260 and thread control unit 320.
A single program may be used to process several sets of samples. Thread control unit 320 receives samples or pointers to samples stored in pixel input buffer 215 and vertex input buffer 220. Thread control unit 320 receives a pointer to a program to process one or more samples. Thread control unit 320 assigns a thread to each sample to be processed. A thread includes a pointer to a program instruction (program counter), such as the first instruction within the program, thread state information, and storage resources for storing intermediate data generated during processing of the sample. Thread state information is stored in a TSR (thread storage resource) 325. TSR 325 may be a register file, FIFO, circular buffer, or the like. An instruction specifies the location of source data needed to execute the instruction. Source data, such as intermediate data generated during processing of the sample is stored in a register file 350. In addition to register file 350, other source data may be stored in pixel input buffer 215 or vertex input buffer 220. In an alternate embodiment source data is stored in local memory 140, locations in host memory 112, and the like.
Alternatively, in an embodiment permitting multiple programs for two or more thread types, thread control unit 320 also receives a program identifier specifying which one of the two or more programs the program counter is associated with. Specifically, in an embodiment permitting simultaneous execution of four programs for a thread type, two bits of thread state information are used to store the program identifier for a thread. Multithreaded execution of programs is possible because each thread may be executed independent of other threads, regardless of whether the other threads are executing the same program or a different program. PCUs 375 update each program counter associated with the threads in thread control unit 320 following the execution of an instruction. For execution of a loop, call, return, or branch instruction the program counter may be updated based on the loop, call, return, or branch instruction.
For example, each fragment or group of fragments within a primitive can be processed independently from the other fragments or from the other groups of fragments within the primitive. Likewise, each vertex within a surface can be processed independently from the other vertices within the surface. For a set of samples being processed using the same program, the sequence of program instructions associated with each thread used to process each sample within the set will be identical, although the program counter for each thread may vary. However, it is possible that, during execution, the threads processing some of the samples within a set will diverge following the execution of a conditional branch instruction. After the execution of a conditional branch instruction, the sequence of executed instructions associated with each thread processing samples within the set may differ and each program counter stored in TSR 325 within thread control unit 320 for the threads may differ accordingly.
FIG. 4 is an illustration of an alternate embodiment of execution pipeline 240 containing at least one multithreaded processing unit 400. Thread control unit 420 includes a TSR 325 to retain thread state data. In one embodiment TSR 325 stores thread state data for each of at least two thread types, where the at least two thread types may include pixel, primitive, and vertex. Thread state data for a thread may include, among other things, a program counter, a busy flag that indicates if the thread is either assigned to a sample or available to be assigned to a sample, a pointer to a source sample to be processed by the instructions associated with the thread or the output pixel position and output buffer ID of the source sample to be processed, and a pointer specifying a destination location in vertex output buffer 260 or pixel output buffer 270. Additionally, thread state data for a thread assigned to a sample may include the sample type, e.g., pixel, vertex, primitive, or the like. The type of data a thread processes identifies the thread type, e.g., pixel, vertex, primitive, or the like.
Source samples are stored in either pixel input buffer 215 or vertex input buffer 220. Thread allocation priority, as described further herein, is used to assign a thread to a source sample. A thread allocation priority is specified for each sample type and thread control unit 420 is configured to assign threads to samples or allocate locations in a register file 350 based on the priority assigned to each sample type. The thread allocation priority may be fixed, programmable, or dynamic. In one embodiment the thread allocation priority may be fixed, always giving priority to allocating vertex threads and pixel threads are only allocated if vertex samples are not available for assignment to a thread.
In an alternate embodiment, thread control unit 420 is configured to assign threads to source samples or allocate locations in register file 350 using thread allocation priorities based on an amount of sample data in pixel input buffer 215 and another amount of sample data in vertex input buffer 220. Dynamically modifying a thread allocation priority for vertex samples based on the amount of sample data in vertex input buffer 220 permits vertex input buffer 220 to drain faster and fill vertex output buffer 260 and pixel input buffer 215 faster or drain slower and fill vertex output buffer 260 and pixel input buffer 215 slower. Dynamically modifying a thread allocation priority for pixel samples based on the amount of sample data in pixel input buffer 215 permits pixel input buffer 215 to drain faster and fill pixel output buffer 270 faster or drain slower and fill pixel output buffer 270 slower. In a further alternate embodiment, thread control unit 420 is configured to assign threads to source samples or allocate locations in register file 350 using thread allocation priorities based on graphics primitive size (number of pixels or fragments included in a primitive) or a number of graphics primitives in vertex output buffer 260. For example a dynamically determined thread allocation priority may be determined based on a number of “pending” pixels, i.e., the number of pixels to be rasterized from the primitives in primitive assembly/setup 205 and in vertex output buffer 260. Specifically, the thread allocation priority may be tuned such that the number of pending pixels produced by processing vertex threads is adequate to achieve maximum utilization of the computation resources in execution pipelines 240 processing pixel threads.
Once a thread is assigned to a source sample, the thread is allocated storage resources such as locations in a register file 350 to retain intermediate data generated during execution of program instructions associated with the thread. Alternatively, source data is stored in storage resources including local memory 140, locations in host memory 112, and the like.
A thread selection unit 415 reads one or more thread entries, each containing thread state data, from thread control unit 420. Thread selection unit 415 may read thread entries to process a group of samples. For example, in one embodiment a group of samples, e.g., a number of vertices defining a primitive, four adjacent fragments arranged in a square, or the like, are processed simultaneously. In the one embodiment computed values such as derivatives are shared within the group of samples thereby reducing the number of computations needed to process the group of samples compared with processing the group of samples without sharing the computed values.
In multithreaded processing unit 400, a thread execution priority is specified for each thread type and thread selection unit 415 is configured to read thread entries based on the thread execution priority assigned to each thread type. A thread execution priority may be static, programmable, or dynamic. In the preferred embodiment, the thread execution priority is static and is assigned based on thread type. For example, the execution of vertex threads is given higher priority than the execution of pixel threads.
In an alternative embodiment, thread selection unit 415 is configured to read thread entries based on the amount of sample data in pixel input buffer 215 and the amount of sample data in vertex input buffer 220. In a further alternate embodiment, thread selection unit 415 is configured to read thread entries using on a priority based on graphics primitive size (number of pixels or fragments included in a primitive) or a number of graphics primitives in vertex output buffer 260. For example a dynamically determined thread execution priority is determined based on a number of “pending” pixels, i.e., the number of pixels to be rasterized from the primitives in primitive assembly/setup 205 and in vertex output buffer 260. Specifically, the thread execution priority may be tuned such that the number of pending pixels produced by processing vertex threads is adequate to achieve maximum utilization of the computation resources in execution pipelines 240 processing pixel threads.
Thread selection unit 415 reads one or more thread entries based on thread execution priorities and outputs selected thread entries to instruction cache 410. Instruction cache 410 determines if the program instructions corresponding to the program counters and sample type included in the thread state data for each thread entry are available in instruction cache 410. When a requested program instruction is not available in instruction cache 410 it is read (possibly along with other program instructions stored in adjacent memory locations) from graphics memory. A base address, corresponding to the graphics memory location where a first instruction in a program is stored, may be used in conjunction with a program counter to determine the location in graphics memory where a program instruction corresponding to the program counter is stored. In an alternate embodiment, instruction cache 410 can be shared between multithreaded processing units 400 within execution pipeline 240.
The program instructions corresponding to the program counters from the one or more thread entries are output by instruction cache 410 to a scheduler, instruction scheduler 430. The number of instructions output each clock cycle from instruction cache 410 to instruction scheduler 430 can vary depending on whether or not the instructions are available in the cache. The number of instructions that can be output each clock cycle from instruction cache 410 to instruction scheduler 430 may also vary between different embodiments. In one embodiment, instruction cache 410 outputs one instruction per clock cycle to instruction scheduler 430. In an alternate embodiment, instruction cache 410 outputs a predetermined number of instructions per clock cycle to instruction scheduler 430.
Instruction scheduler 430 contains storage resources to store a predetermined number of instructions in an IWU (instruction window unit) 435. Each clock cycle, instruction scheduler 430 evaluates whether any instruction within the IWU 435 can be executed based on the availability of computation resources in an execution unit 470 and source data stored in register file 350. An instruction specifies the location of source data needed to execute the instruction. In addition to register file 350, other locations of source data include pixel input buffer 215, vertex input buffer 220, locations in local memory 140, locations in host memory 112, and the like. A resource tracking unit, resource scoreboard 460, tracks the status of source data stored in registers in register file 350. Specifically, registers scheduled to be written during processing, i.e., destination registers, are marked as “write pending.” When a destination register is written, its status is updated and the “write pending” mark is removed. In one embodiment a destination register is marked as “write pending” by setting a bit in resource scoreboard 460 corresponding to the destination register. The bit is cleared when the destination register is written, indicating that data stored in the register is available to be used as source data. Similarly, resource scoreboard 460 may also track the availability of the computation resources in an execution unit 470.
When instruction scheduler 430 determines which instructions and associated threads will be executed, instruction scheduler 430 processes loop, call, return, or branch instructions using sequencer 425. Sequencer 425 determines a program counter associated with a thread executing a loop, call, return, or branch instruction. For example, execution of a branch instruction may result in a program counter changing to a different value, either earlier or later in the program when the branch is taken. Instruction scheduler 430 outputs an updated program counter to thread control unit 420. Alternatively, instruction scheduler 430 outputs a difference value to update the program counter in thread control unit 420.
For execution of other instructions (not loop call, return, or branch instructions) instruction scheduler 430 updates destination register status and computation resource availability in resource scoreboard 460 as needed, and increments each program counter in thread control unit 420 associated with a thread output to instruction dispatcher 440 to point to the next instruction in the thread. In this manner, instruction scheduler 430 is able to schedule the execution of the instructions associated with each thread such that the processing of a sample is one or more instructions ahead of the processing of another sample. As a result of instruction scheduler 430 not being constrained to schedule instructions for execution on each sample within a set of data synchronously, the program counter for each thread may vary from program counters for other threads.
Instruction dispatcher 440 gathers the source data from pixel input buffer 215, vertex input buffer 220 or register file 350 specified in an instruction and outputs the instruction and source data to execution unit 470 including at least one PCU 375. Alternatively, instruction dispatcher 440 also gathers the source data from local memory 140, host memory 112, or the like. Execution unit 470 is configured by the program instruction to simultaneously process samples using PCUs 375 to perform operations such as linear interpolation, derivative calculation, blending, and the like, and output the processed sample to a destination specified by the instruction. The destination may be vertex output buffer 260, pixel output buffer 270, or register file 350. Alternatively, the destination may also include local memory 140, host memory 112, or the like. Execution unit 470 can simultaneously process samples of different types, and, likewise, execute threads of different types.
When execution of an instruction is complete, execution unit 470 updates resource scoreboard 460 to indicate that destination registers are written and the computation resources used to process the instruction are available. In an alternate embodiment, resource scoreboard 460 snoops an interface between execution unit 470 and register file 350 to update register status.
When the program instructions associated with a thread have completed execution, the storage resources allocated to retain intermediate data generated during execution of the thread become available for allocation to another thread, i.e., the storage resources are deallocated and the thread is flagged as available in thread control unit 420. When a program instruction stored in instruction cache 410 has completed execution on each sample within the one or more sets that the program instruction is programmed to process, the program instruction is retired from instruction cache 410 (by being overwritten).
FIG. 5A is a flow diagram of an exemplary embodiment of thread processing in accordance with one or more aspects of the present invention. In step 510 thread control unit 320 or 420 receives a pointer to a vertex program or a pixel program to process graphics data, e.g., vertices, surfaces, fragments, pixels, and the like. In step 515 thread control unit 320 or 420 determines if the program is a vertex program or a pixel program, and if the program is a vertex program thread control unit 320 or 420 proceeds to step 525. In step 525 thread control unit 320 or 420 assigns a vertex thread to a vertex to be processed by the vertex program.
If, in step 515 thread control unit 320 or 420 determines the program is a pixel program, in step 545 thread control unit 320 or 420 assigns a pixel thread to a pixel or fragment to be processed by the shader program.
FIG. 5B is a flow diagram of another exemplary embodiment of thread processing in accordance with one or more aspects of the present invention including the steps shown in FIG. 5A. In step 510 thread control unit 320 or 420 receives a pointer to a vertex program or a pixel program to process graphics data. In step 515 thread control unit 320 or 420 determines if the program is a vertex program or a pixel program, and if the program is a vertex program thread control unit 320 or 420 proceeds to step 520. In step 520 thread control unit 320 or 420 uses a thread allocation priority to determine if a vertex thread may be allocated. If a vertex thread may not be allocated based on the thread allocation priority, thread control unit 320 or 420 returns to step 510. If, in step 520 a vertex thread may be allocated based on the thread allocation priority, in step 525 thread control unit 320 or 420 determines if a vertex thread is available for assignment. If, in step 525 thread control unit 320 or 420 determines a vertex thread is not available, thread control unit 320 or 420 returns to step 510. If, in step 525 thread control unit 320 or 420 determines a vertex thread is available, in step 530 thread control unit 320 or 420 assigns a vertex thread to a vertex to be processed by the vertex program.
If, in step 515 thread control unit 320 or 420 determines the program is a pixel program, in step 535 thread control unit 320 or 420 uses a thread allocation priority to determine if a pixel thread may be allocated. If a pixel thread may not be allocated based on the thread allocation priority, thread control unit 320 or 420 returns to step 510. If, in step 535 a pixel thread may be allocated based on the thread allocation priority, in step 540 thread control unit 320 or 420 determines if a pixel thread is available for assignment. If, in step 525 thread control unit 320 or 420 determines a pixel thread is not available, thread control unit 320 or 420 returns to step 510. If, in step 540 thread control unit 320 or 420 determines a pixel thread is available, in step 545 thread control unit 320 or 420 assigns a pixel thread to a pixel or fragment to be processed by the shader program.
Following assignment of a vertex thread, thread control unit 320 dispatches vertex program instructions and source data to PCUs 375 for processing and processed vertex data is output by PCUs 375 to vertex output buffer 260. Thread control unit 420 provides pointers to vertex program instructions to instruction cache 410 and processed vertex data is output by execution unit 470 to vertex output buffer 260. In an embodiment, the processed vertex data is rasterized by primitive assembly/setup unit 205 and raster unit 210 to produce second graphics data, e.g., pixels or fragments. Primitive assembly/setup unit 205 and raster unit 210 effectively convert data processed by a first sample type into data to be processed by a second sample type.
After assigning threads to pixels or fragments to be processed by a shader program, thread control unit 320 dispatches shader program instructions and source data to PCUs 375 for processing. Likewise, thread control unit 420 provides pointers to shader program instructions to instruction cache 410. Instruction cache 410 reads the thread state data for the thread from thread control unit 420 and outputs program instructions to instruction scheduler 430. Instruction scheduler 430 determines resources for processing the program instructions are available and outputs the program instructions to instruction dispatcher 440. Instruction dispatcher 440 gathers any source data specified by the instructions and dispatches the source data and the instructions to execution unit 470 for execution.
FIG. 6A is an exemplary embodiment of a portion of TSR 325 storing thread state data within an embodiment of the thread control unit 320 or 420. Locations 610, 611, 612, 613 within the portion of TSR 325 may each store thread state data such as, a sample type, a program counter, a busy flag, a source sample pointer, a destination pointer, and the like. A thread pointer 605 indicates the next thread to be processed. In this embodiment each location may store thread state data of any sample type, therefore the thread state data for each sample type may be interleaved location by location within TSR 325. Thread control unit 320 or 420 uses the thread state data to determine how many threads are available for allocation and how many threads are assigned to each sample type. Thread pointer 605 is updated after one or more threads are selected for processing. In one embodiment thread pointer 605 is updated, skipping over unassigned, i.e., available threads. In another embodiment thread pointer 605 is updated, skipping over unassigned and lower priority threads based on a thread execution priority specified for each thread type. A thread execution priority may be fixed, programmable, or dynamic as previously described.
FIG. 6B is an alternate exemplary embodiment of portions of TSR 325 storing thread state data within an embodiment of the thread control unit 320 or 420. Locations within the portions of TSR 325 may each store thread state data such as, a program counter, a busy flag, a source sample pointer, a destination pointer, and the like. Portion 620 includes locations allocated for storing thread state data for a first sample type. Portion 630 includes locations allocated for storing thread state data for a second sample type. Portion 640 includes locations allocated for storing thread state data for a third sample type. A sample type for each location within the portions of TSR 325 is implicit because the sample type is specified for the portion 620, 630, and 640 containing the location. Thread control unit 320 or 420 uses the thread state data to determine how many threads of each sample type are available and how many threads are assigned to each sample type. Thread pointer 625 indicates the next thread of the first sample type to be processed. Thread pointer 635 indicates the next thread of the second sample type to be processed. Thread pointer 645 indicates the next thread of the third sample type to be processed. Thread pointers 625, 635 and 645 are updated as needed after one or more threads are selected for processing. Threads may be selected for processing based on thread execution priority. In one embodiment thread pointers 625, 635 and 645 are updated, skipping over unassigned, i.e., available threads.
The maximum size of each portion 620, 630 and 640 may be a fixed value for an embodiment or may be programmed using a sample portion opcode. For example, the sample portion opcode specifies a maximum portion size for a sample type and the maximum portion size is stored in a register accessible by thread control unit 320 or 420. Furthermore, a size of each portion 620, 630 or 640 may be determined based on graphics primitive size (number of pixels or fragments included in a primitive), a number of graphics primitives in vertex input buffer 220, a number of memory accesses required by a program or a number of program instructions within the program.
The maximum number of threads that can be executed simultaneously is related to the number of execution pipelines 240, the size of storage for thread state data, the amount of storage for intermediate data generated during processing of a sample, the latency of execution pipelines 240, and the like. Likewise, a number of threads of each sample type that may be executed simultaneously may be limited in each embodiment. Therefore, not all samples within a first set of samples of a first type can be processed simultaneously when the number of threads available for processing samples of the first type is less than the number of samples of the first type. Conversely, when the number of threads available for processing samples of a second type exceeds the number of samples of the second type within a second set, more than one set can be processed simultaneously. When processing throughput is limited for samples of the first type, the number of threads available for the first type may be increased by allocating unused threads for processing samples of the first type. For example, locations in portion 620 may be allocated to portion 630.
FIG. 7A is a flow diagram of an exemplary embodiment of thread allocation and processing in accordance with one or more aspects of the present invention. In step 710 a number of threads are allocated for a first sample type and a maximum portion of TSR 325 allocated for threads to process the first type is set. The number of threads allocated to process the first sample type may be based on a representative size of primitives defined by the graphics data. For example, when the representative size of the primitives is large, a higher ratio of threads processing pixel samples to threads processing vertex samples can result in better performance than a lower ratio of threads processing pixel samples to threads processing vertex samples. Conversely, when the representative size of the primitive small, a lower ratio of threads processing pixel samples to threads processing vertex samples can result in better performance than a higher ratio of threads processing pixel samples to threads processing vertex samples. In step 715 a number of threads are allocated for a second sample type and a maximum portion of TSR 325 allocated for threads to process samples of the second type is set. In step 720 first program instructions associated with the first sample type are executed to process graphics data and produce processed graphics data. For example, surfaces may be tessellated to produce vertices or vertices may be sampled to produce fragments. In step 725 second program instructions associated with the second sample type are executed to process the processed graphics data.
FIG. 7B is a flow diagram of an alternate exemplary embodiment of thread allocation and processing in accordance with one or more aspects of the present invention. In step 750 a number of threads to be allocated for each sample type is determined. The number of threads to be allocated may be based on a representative size of primitives defined by graphics data, a number of program instructions to process the graphics data or a number of memory accesses needed to execute the program instructions to process the graphics data. Furthermore, numbers of threads for a sample type to be allocated for portions of graphics data may be determined. In step 755 a first number of threads determined for allocation to a first sample type are allocated to the first sample type. In step 760 the number of threads determined for allocation to a second sample type are allocated to the second sample type.
In step 765 first program instructions associated with the first sample type are executed to process graphics data and produce processed graphics data. In step 770 second program instructions associated with the second sample type are executed to process at least one of the graphics data or the processed graphics data. In step 775 a third number of threads determined for allocation to a first sample type are allocated to the first sample type. The third number may be allocated prior to rendering an object within a scene, a portion of a scene, a new scene or the like. Alternatively, the third number of threads may be allocated to a third sample type.
FIG. 8A is a flow diagram of an exemplary embodiment of thread assignment in accordance with one or more aspects of the present invention. In step 810 thread control unit 320 or 420 receives a sample. In step 815 thread control unit 320 or 420 identifies a sample type, e.g., vertex, pixel or primitive, associated with the sample received in step 810. In step 820 thread control unit 320 or 420 uses thread state data, e.g., busy flag, to determine if a thread to process samples of the sample type is available, i.e., unassigned. In an alternate embodiment, thread control unit 320 computes a number of available threads for each sample type using a number of threads allocated for the sample type and a number of threads assigned to the sample type. The number of threads assigned is incremented when a thread is assigned and decremented when execution of a thread is completed. If in step 820 a thread is available to process the sample, in step 825 a thread is assigned to the sample by thread control unit 320 or 420. When a thread is not available in step 820, thread control unit 320 or 420 does not proceed to step 825 until a thread becomes available. In step 825 the busy flag portion of the thread state data is marked unavailable and the program counter corresponding to the first instruction to process the sample is stored in the thread state data. In step 825 thread control unit 320 or 420 also stores the position corresponding to the sample as part of the thread state data stored in TSR 325.
The occurrence of image artifacts caused by failing to maintain sample processing order for each output pixel position between frames or within a frame can be significantly reduced or eliminated by processing pixel type samples, e.g., pixels, fragments, and the like, for each output pixel location, in the order in which the pixel type samples are received. Processing the pixel type samples for each output pixel location in the order in which the pixel type samples are received can be achieved by permitting pixel type samples corresponding to each output pixel location to be processed by a dedicated multithreaded processing unit 400 and by preventing the occurrence of position hazards. A position hazard exists when more than one pixel type sample corresponding to an output pixel position within an output buffer is being processed by any multithreaded processing unit 400 because the order in which samples will be processed is not deterministic, i.e., is not necessarily the same as the order in which the samples are received.
In one embodiment each multithreaded processing unit 400 is configured to process several output pixel locations distributed across an output image. In an alternate embodiment each multithreaded processing unit 400 is configured to process several adjacent output pixel locations within the output image. In another embodiment each multithreaded processing unit 400 is configured to process regions of four adjacent pixels arranged in a square, with each square distributed within the output image.
Thread control unit 320 or 420 may be configured to accept only one pixel type sample from pixel input buffer 215 corresponding to each output pixel position within an output buffer and wait until the one pixel type sample is processed before accepting another pixel type sample corresponding to the same output pixel position within the output buffer. The output pixel position is stored as a portion of portion of thread state data in TSR 325 within thread control unit 320 or 420. An output buffer ID specifying a unique output buffer containing output pixel positions is also optionally stored as a portion of portion of thread state data in TSR 325 within thread control unit 320 or 420. A process independent of order received (PIOR) flag is used to disable the prevention of position hazards. Disabling the PIOR flag during rendering eliminates image artifacts that can be introduced when pixel type sample processing order for each output pixel location within an output buffer is not maintained between frames or within a frame. Enabling the PIOR flag during rendering can improve performance. Furthermore, a PIOR flag may be dedicated for each sample type to selectively enable or disable PIOR for each sample type.
In an alternate embodiment each multithreaded processing unit 400 is configured to process pixel type samples corresponding to any output pixel position and pixel input buffer 215 can be configured to output only one pixel type sample corresponding to each output pixel position within an output buffer. In the alternate embodiment pixel input buffer 215 waits until the one pixel type sample corresponding to an output pixel position within an output buffer is processed before outputting another pixel type sample corresponding to the same output pixel position within the output buffer.
FIG. 8B is a flow diagram of an alternative exemplary embodiment of thread assignment including position hazard detection in accordance with one or more aspects of the present invention. In step 850 thread control unit 320 or 420 receives a sample. In step 855 thread control unit 320 or 420 identifies a sample type, e.g., vertex, pixel or primitive, associated with the sample received in step 810. In step 860 thread control unit 320 or 420 determines if the PIOR flag is disabled for the sample type determined in step 855, and, if so, in step 865 thread control unit 320 or 420 determines if a position hazard exists for the sample. If in step 865 thread control unit 320 or 420 determines a position hazard exists for the sample, thread control unit 320 or 420 remains in step 865.
A position hazard exists when an output pixel position associated with a first sample assigned to a first thread is equal to an output pixel position associated with a second sample assigned to a second thread and an output buffer ID associated with the first sample is equal to an output buffer ID associated with the second sample. If in step 865 thread control unit 320 or 420 determines a position hazard does not exist for the sample, in step 870 thread control unit 320 or 420 uses thread state data stored in TSR 325 to determine if a thread is available to process a sample of the sample type, as described further herein. If in step 870 a thread is available to process the sample, in step 875 a thread is assigned to the sample by thread control unit 320 or 420. When a thread is not available in step 870, thread control unit 320 or 420 does not proceed to step 875 until a thread becomes available.
In step 875 the busy flag portion of the thread state data is marked unavailable and the program counter corresponding to the first instruction to process the sample is stored in the thread state data. In step 875 thread control unit 320 or 420 also stores at least a portion of the output pixel position and output buffer ID associated with the sample as the thread state data. In step 877 thread control unit 320 or 420 determines if storage resources for storing intermediate data generated during execution of the thread are available. The storage resources may be in graphics memory. When storage resources are not available in step 877, thread control unit 320 or 420 does not proceed to step 880 until a storage resources become available.
In step 880 thread control unit 320 dispatches the thread assigned to the sample and source data to at least one PCU 375. In step 850 the thread busy flag portion of the thread state data is marked as available in TSR 325 within thread control unit 320 and the storage resources allocated to the thread in step 875 are effectively deallocated. Likewise, in step 880 thread selection unit 415 reads the thread state data for the thread from thread control unit 420 and outputs the thread state data to instruction cache 410. Instruction cache 410 outputs the program instructions to instruction scheduler 430. Instruction scheduler 430 determines resources for processing the program instructions are available and outputs the program instructions to instruction dispatcher 440. Instruction dispatcher 440 gathers any source data specified by the instructions and dispatches the program instructions and the source data to execution unit 470. When execution unit 470 determines there are no more program instructions in the thread, in step 850 the thread busy flag portion of the thread state data is marked as available in thread control unit 420 and the storage resources allocated to the thread in step 875 are effectively deallocated.
In an alternate embodiment steps 860 and 865 are completed by instruction scheduler 430 instead of being completed by thread control unit 420. In yet another alternate embodiment steps 860 and 865 are completed by instruction dispatcher 440 prior to gathering source data instead of being completed by thread control unit 420.
Assigning a thread execution priority to each thread type to balance processing of each sample type dependent on the number of threads needed for each sample type may improve performance of multithreaded processing of graphics data. Alternatively, a thread execution priority is determined for each thread type based on the amount of sample data in pixel input buffer 215 and the amount of sample data in vertex input buffer 220, graphics primitive size (number of pixels or fragments included in a primitive), or a number of graphics primitives in vertex input buffer 220. FIG. 9A is a flow diagram of an exemplary embodiment of thread selection in accordance with one or more aspects of the present invention. In step 910 thread state data is used to identify threads that are assigned, i.e., ready to be processed. In step 915 thread control unit 320 or thread selection unit 415 selects at least one thread for processing.
In step 920 thread control unit 320 reads one or more program instructions, updates at least one thread pointer, schedules the one or more program instructions for execution, gathers any source data specified by the one or more program instructions, and dispatches the one or more program instructions and the source data. In step 920 thread selection unit 415 reads thread state data for the at least one thread from thread control unit 420. Thread control unit 420 updates at least one thread pointer and thread selection unit 415 outputs the thread state data for the at least one thread to instruction cache 410. Instruction cache 410 outputs the one or more program instructions to instruction scheduler 430. Instruction scheduler 430 determines resources for processing the one or more program instructions are available and outputs the one or more program instructions to instruction dispatcher 440. In step 925 thread control unit 320 or 420 updates the program counter stored in TSR 325 for each of the at least one thread selected for processing and returns to step 910.
FIG. 9B is a flow diagram of an alternate exemplary embodiment of thread selection using thread execution priorities in accordance with one or more aspects of the present invention. Thread execution priority is specified for each thread type and thread control unit 320 or thread selection unit 415 is configured to select threads for processing based on a thread execution priority assigned to or determined for each thread type. In one embodiment, a thread execution priority is determined based on an amount of sample data in pixel input buffer 215 and another amount of sample data in vertex input buffer 220 and optionally stored in the thread execution priority register. In another embodiment, a thread execution priority is determined based on graphics primitive size (number of pixels or fragments included in a primitive) or a number of graphics primitives in vertex input buffer 220 and optionally stored in the thread execution priority register.
In step 950 thread control unit 320 or thread selection unit 410 obtains a thread execution priority for each thread type, for example by reading thread execution priority data stored in the thread execution priority register. Thread control unit 320 or thread selection unit 410 determines the priority order of the thread types, e.g., highest priority to lowest priority. In step 955 thread state data is used to identify any threads of the highest priority thread type that are assigned, i.e., ready to be processed. In step 960 thread control unit 320 or thread selection unit 410 determines if there are any threads of the highest priority thread type ready to be processed. If there are no threads of the highest priority thread type ready to be processed, in step 980 thread control unit 320 or thread selection unit 410 identifies a priority thread type, for example using a round-robin method to select the priority thread type using the priority order of the thread types determined in step 950.
In step 955 thread state data is used to identify any threads of the priority thread type that are assigned, i.e., ready to be processed. In step 960 thread control unit 320 or thread selection unit 410 determines if there are any threads of the priority thread type ready to be processed. In step 960 if there is at least one thread of the priority thread type, in step 965 thread control unit 320 or thread selection unit 410 selects at least one thread of the priority thread type for processing.
In step 970 thread control unit 320 reads one or more program instructions, updates at least one thread pointer, schedules the one or more program instructions for execution, gathers any source data specified by the one or more program instructions, and dispatches the one or more program instructions and the source data. In step 970 thread selection unit 410 reads thread state data for the at least one thread from thread control unit 420. Thread control unit 420 updates at least one thread pointer and thread selection unit 410 outputs the thread state data to instruction cache 410. Instruction cache 410 outputs the one or more program instructions to instruction scheduler 430. Instruction scheduler 430 determines resources for processing the one or more program instructions are available and outputs the one or more program instructions to instruction dispatcher 440. In step 975 thread control unit 320 or instruction scheduler 430 updates the program counter stored in TSR 325 for each of the at least one thread selected for processing and proceeds to step 980.
FIG. 10 is a block diagram of another embodiment of the programmable graphics processing pipeline 150 of FIG. 1. Samples, such as surfaces, primitives, or the like, are received from IDX 135 by programmable graphics processing pipeline 150 and processed, and the processed samples are output to raster analyzer 160. During processing, local memory 140 or host memory 112 may be accessed via memory controller 120. In this embodiment, programmable graphics processing pipeline 150 includes a plurality of texture processing clusters (TPCs) 1010. The TPCs 1010 are typically independently running units and the number of TPCs 1010 can be varied depending on the processing requirements and geometric constraints of the processor. In the embodiment illustrated in FIG. 10, eight TPCs are shown.
FIG. 11 illustrates an embodiment of the texture processing cluster 1010 of FIG. 10. The TPC 1010 operates in the same manner as the programmable graphics processing pipeline 150 described above with reference to FIG. 2, except that two execution pipelines 240 are provided in the TPC 1010 as compared to four execution pipelines 240 in the embodiment of FIG. 2. In FIG. 11, setup 205 and raster unit 210 are global units that work with all of the TPCs and are thus illustrated outside of the particular TPC 1010 shown in the figure.
FIG. 12 is a block diagram of another embodiment of the execution pipeline 240 of FIG. 2 or FIG. 11. The execution pipeline 240 illustrated in FIG. 12 is a single-instruction, multiple-data (SIMD) execution pipeline, and includes an instruction processing section 1210 and a data processing section 1220. The instruction processing section 1210 operates at a clock rate that is half the clock rate of the data processing section 1220. For convenience, the clock for the instruction processing section 1210 will be referred to hereafter as the T clock, and the clock for the data processing section 1220 will be referred to hereafter as the H clock.
The instruction processing section 1210 includes an instruction dispatch unit 1212 for issuing an instruction to be executed by the execution pipeline 240, a register file 1214 that stores the operands used in executing the instruction, and a pair of operand collection units 1216, 1218. The operand collection unit 1216 is coupled to a first set of parallel data execution paths 1222 and collects operands to be supplied to the first set of parallel data execution paths 1222. The operand collection unit 1218 is coupled to a second set of parallel data execution paths 1224 and collects operands to be supplied to the second set of parallel data execution paths 1224. In the embodiment illustrated herein, the first set of parallel data execution paths is configured to execute instructions of a first type, e.g., multiply and add (MAD), and the second set of parallel data execution paths is configured to execute instructions of a second type, e.g., special function instructions such as curve fitting for sines and cosines, reciprocal, reciprocal square root, exponential, logarithmic, interpolation, etc. (SFU). As an example, pixel shader input interpolation may be carried out using the parallel data execution paths 1224. Certain instructions may be carried out in either set of parallel data execution paths 1222, 1224. For example, instructions MOV and FMUL may be executed in either set of parallel data execution paths 1222, 1224. Each set of parallel data execution paths 1222, 1224 has 8 parallel and identically configured data paths.
When the instruction dispatch unit 1212 issues an instruction, the instruction dispatch unit 1212 sends configuration signals to one of the two sets of parallel data execution paths 1222, 1224. If the instruction is of the MAD type, the configuration signals are sent to the first set of parallel data execution paths 1222. If the instruction is of the SFU type, the pipeline configuration signals are sent to the second set of parallel data execution paths 1222. If the instruction is a texture fetch instruction, the instruction is processed by a texture execution pipeline provided in the texture unit 225.
Upon issuing an instruction, the instruction dispatch unit 1212 also transmits a mask that corresponds to a convoy (which in the embodiment illustrated herein is a group of 32) of sample data (e.g., pixel data or vertex data) associated with the issued instruction. If the issued instruction is of the MAD type, the operand collection unit 1216 reads the registers within the register file 1214 that are associated with the convoy of sample data and, for each sample data in the convoy, collects a set of operands that are needed to execute the issued instruction. A single set of operands may include one or more operands. Typically a set of operands associated with an instruction of the MAD type includes two or three operands, and a set of operands associated with an instruction of the SFU type includes one operand.
If the issued instruction is of the SFU type, the operand collection unit 1218 reads the registers within the register file 1124 that are associated with the convoy of sample data and, for each sample data in the convoy, collects a set of operands that are needed to execute the issued instruction. For each cycle of the T clock, each of the operand collection units 1216, 1218 is able to collect 16 sets of operands. These sets are supplied to the two sets of parallel data execution paths 1222, 1224 at a rate of eight sets per H clock cycle. Therefore, the 32 sets of operands associated with a convoy of sample data are processed in two T clock cycles or four H clock cycles.
The results from the two sets of parallel data execution paths 1222, 1224 are collected in a pair of accumulators 1226, 1228. The accumulator 1226 collects results from the first set of parallel data execution paths 1222 and the accumulator 1228 collects execution results from the second set of parallel data execution paths 1224. The sets of parallel data execution paths 1222, 1224 and the accumulators 1226, 1228 are part of the data processing section 1220 and operate at a clock rate that is twice the clock rate of the instruction processing section 1210. The accumulators 1226, 1228 write the results back to the register file 1214 every two H clock cycles, or every one T clock cycle, because the register file 1214 operates at the T clock rate. Thus, each of the accumulators 1226, 1228 collects 16 sets of execution results before it writes back to the register file 1214. After a thread of instructions has been completed for a convoy of sample data, the final results are stored in vertex output buffer 260 or pixel output buffer 270.
The H clock is configured to be a fast clock, because of the types of operations, primarily math operations, being carried out in the two sets of parallel data execution paths 1222, 1224. The efficient operating speed for math operations, however, is generally different from the efficient operating speed for instruction processing and for the register file 1214. The instruction processing and the register file 1214 operate more efficiently with a slower clock. Therefore, the execution pipeline 240 is configured with two clock domains, with the instruction processing being carried out at the T clock rate and the data processing being carried out at the H clock rate, which is equal to twice the T clock rate. In the embodiment of the invention illustrated herein, the T clock rate is equal to the clock rate of graphics processor 105.
FIG. 13 is a block diagram of an embodiment of the instruction dispatch unit 1212 of the instruction processing section 1210 of FIG. 12. The instruction dispatch unit 1212 includes an instruction buffer 1310 with a plurality of slots. Each slot corresponds to a convoy of threads (which in the embodiment illustrated herein is a group of 32 threads). The number of slots in this exemplary embodiment is 24 and each slot can hold up to two instructions and a multi-bit dependency mask for each of the instructions. The multi-bit dependency mask for an instruction provides an indication as to whether the instruction needs to use (depends on) a register that is currently busy. If any one of the slots in the instruction buffer 1310 has a space for another instruction, a fetch 1312 is made from memory into an instruction cache 1314. After the fetch 1312, the instruction undergoes a decode 1316 and scoreboard processing 1321. During scoreboard processing 1321, register identifiers (IDs) of source and destination registers specified in the instruction are compared with the register IDs stored in a scoreboard memory 1322, and a multi-bit value that represents the aggregate comparison result is generated as an output. This output is added to the instruction buffer 1310 as the multi-bit dependency mask along with the instruction. In addition, the register ID of the destination register specified in the instruction is added to the scoreboard memory 1322. Further details of the scoreboard processing 1321 are described in U.S. patent application Ser. No. 11/301,589, entitled “Scoreboard for Multi-Threaded Processor,” filed Dec. 13, 2005, the entire contents of which are incorporated by reference herein.
The instruction dispatch unit 1212 further includes an issue logic 1320. The issue logic 1320 examines the instructions and their multi-bit dependency masks stored in the instruction buffer 1310 and issues an instruction out of the instruction buffer 1310 that is not dependent on any of the instructions in flight (e.g., an instruction having a dependency mask equal to zero), provided that there is available memory space in the scoreboard memory 1322 to store the register ID of a destination register specified in the instruction. If not, the issue logic 1320 does not issue the instruction until memory space in the scoreboard memory 1322 becomes available. In conjunction with the issuance out of the instruction buffer 1310, the issue logic 320 sends configuration signals to the appropriate set of parallel data execution paths 1222, 1224.
FIG. 14 is a flow diagram that illustrates the steps of processing graphics data in accordance with one or more aspects of the present invention. In step 1410, sample data is received for vertex processing. Then, in step 1412, vertex processing is performed on the sample data using a SIMD execution pipeline (e.g., the execution pipeline 240 illustrated in FIG. 12) and the vertex data output is stored in vertex output buffer 260. The vertex data is then supplied to primitive assembly/setup unit 205 which performs calculations to rasterize the processed vertex data (step 1414). In step 1416, raster unit 210 scan converts the rasterized vertex data to generate pixel data that is input into pixel input buffer 215. Then, in step 1418, the pixel data is processed through the same SIMD execution pipeline that was used in step 1412 for vertex processing. The results of the pixel processing are then saved to pixel output buffer 270 and output to raster analyzer 160.
The parallel data execution paths 1222, 1224 include a number of pipeline stages and, as a result, exhibit execution latency. As a result, multiple instructions can be processed in the parallel data execution paths 1222, 1224 at the same time. Accordingly, during step 1412, when vertex processing is being performed on the same data through the SIMD execution pipeline, other vertex processing or pixel processing may be carried out through the SIMD execution pipeline at the same time.
The total number of pixels that can be processed through the execution pipeline 240 illustrated in FIG. 12, per clock cycle of the processing unit, is equal to 2×8×2=32. Since there are two execution pipelines 240 for each TPC 1010, this means each TPC 1010 can process 64 pixels per clock cycle of the processing unit. In addition, there are eight TPCs 1010. Thus, in the embodiment of the present invention illustrated in FIGS. 10-13, the total number of pixels that can be processed per clock cycle of the processing unit is 512.
The total number of vertices that can be processed through the execution pipeline 240 illustrated in FIG. 12, per clock cycle of the processing unit, is equal to 16. Since there are two execution pipelines 240 for each TPC 1010, this means each TPC 1010 can process 32 vertices per clock cycle of the processing unit. In addition, there are eight TPCs 1010. Thus, in the embodiment of the present invention illustrated in FIGS. 10-13, the total number of vertices that can be processed per clock cycle of the processing unit is 256.
In addition, it is possible to process both pixels and vertices through execution pipelines 240 of the TPC 1010. Per clock cycle of the processing unit, the number of pixels and vertices that can be processed through the execution pipelines 240 of the TPC 1010 is equal to 48 pixels+16 vertices, or 32 pixels+32 vertices, or 32 pixels+16 vertices, or 16 pixels+16 vertices.
While foregoing is directed to embodiments in accordance with one or more aspects of the present invention, other and further embodiments of the present invention may be devised without departing from the scope thereof, which is determined by the claims that follow. Claims listing steps do not imply any order of the steps unless such order is expressly indicated.

## Claims

1. A processing unit comprising:
a first input section for receiving pixel data;
a second input section for receiving vertex data;
a first execution pipeline coupled to the first input section and the second input section, wherein the first execution pipeline includes a plurality of parallel data execution paths through which a group of pixel data or vertex data is processed in parallel;
a first output section coupled to the first execution pipeline for storing pixel data processed by the first execution pipeline;
a second output section coupled to the first execution pipeline for storing vertex data processed by the first execution pipeline, and
a second execution pipeline coupled to the first input section, the second input section, the first output section, and the second output section.

2. The processing unit according to claim 1, further comprising a third execution pipeline for carrying out texture fetch operations.

3. The processing unit according to claim 2, further comprising a fourth execution pipeline for carrying out load/store operations.

4. The processing unit according to claim 1, wherein the plurality of parallel data execution paths include a first set of parallel data execution paths for performing multiply and add operations on the group of pixel data or vertex data and a second set of parallel data execution paths for performing special operations on the group of pixel data or vertex data.

5. The processing unit according to claim 4, wherein the special operations include pixel shader input interpolation.

6. The processing unit according to claim 4, wherein some operations may be performed on either of the first and second sets of parallel data execution paths.

7. The processing unit according to claim 1, wherein the execution pipeline includes a control section that is coupled between the first and second input sections and the first and second output sections and configured for specifying operations to be performed on the group of pixel data or vertex data through the plurality of parallel data execution paths.

8. The processing unit according to claim 7, wherein the control section operates at a dock rate that is less than a dock rate of the plurality of parallel data execution paths.

9. The processing unit according to claim 7, further comprising an accumulator that is coupled between the plurality of parallel data execution paths and the control section and configured to collect execution results from the plurality of parallel data execution paths and write the execution results to the control section.

10. The processing unit according to claim 9, wherein the accumulator writes the execution results to the control section at a clock rate that is less than a clock rate of the plurality of parallel data execution paths.

11. The processing unit according to claim 1, wherein the first input section is coupled to the second output section, and the pixel data received through the first input section is processed from the vertex data that is output from the second output section.

12. The processing unit according to claim 11, further comprising a setup unit for rasterizing the vertex data output from the second output section and a raster unit for performing scan conversion of the rasterized vertex data to generate the pixel data received through the first input section.

13. A computer system comprising:
a processing unit for processing graphics data; and
a memory unit associated with the processing unit,
wherein the processing unit includes a first input section for receiving pixel data, a second input section for receiving vertex data, a first execution pipeline coupled to the first input section and the second input section for processing either vertex data or pixel data and having a plurality of parallel data execution paths through which a group of pixel data or vertex data is processed in parallel, and a second execution pipeline coupled to the first input section, the second input section, the first output section, and the second output section.

14. The computer system according to claim 13, wherein the processing unit further includes a setup unit for rasterizing the vertex data processed through the execution pipeline and a raster unit for performing scan conversion of the rasterized vertex data to generate the pixel data received through the first input section.

15. The computer system according to claim 14, wherein the plurality of parallel data execution paths include a plurality of sets of parallel data execution paths, each performing different types of operations on the group of pixel data or vertex data.

16. The computer system according to claim 15, wherein the number of parallel data execution paths in the plurality of sets is the same, and the dock speed of the parallel data execution paths in the plurality of sets is the same.

17. The computer system according to claim 16, wherein the processing unit includes multiple execution pipelines, each coupled to the first input section and the second input section for processing either vertex data or pixel data, and wherein the total number of pixels or vertices processed through the execution pipelines per dock cycle of the processing unit is equal to: (the number of execution pipelines) X (the number of sets of parallel data execution paths) X (the number of parallel data execution paths in each of the sets) X (the ratio of the dock speed of the parallel data execution paths to the processing unit dock speed).