# Patent

## Title
Wideband transimpedance optical receiver

## Abstract

An automatic gain control circuit in which a current source is provided for charging a capacitor and a current source is provided for discharging it, there being means for controlling the ratio of the currents supplied by each source in response to the amplitude of the alternating wave being controlled.

## Background
This application is a continuation-in-part of my U.S. patent application Ser. No. 06/595,756, filed on Apr. 2, 1984, and entitled "Transducer Coupling".

Circuits for deriving an automatic gain control voltage having an amplitude corresponding to the variations in the amplitude of the peaks of an alternating current wave generally utilize rectifying circuits having a diode connected between a source of the alternating current wave and a parallel combination of a capacitor and a resistor. When the amplitude of successive peaks of the wave is increasing, the capacitor is charged by current flowing through the diode so as to increase the voltage across the capacitor; and when the amplitude of successive peaks is decreasing, the capacitor is discharged by charge leaking through the resistor so as to decrease the voltage across the capacitor Whereas the time constant of the charging circuit can be made so short as to enable the voltage across the capacitor to follow rapid increases in the amplitude of the peaks, it is necessary for the time constant of the discharging circuit, which is the product of the resistance of the resistor and the capacitance of the capacitor, to be a compromise between the value required to permit the voltage across the capacitor to follow a sharp decrease in the amplitude between successive peaks and the value required to prevent a significant drop in voltage across the capacitor between peaks in a situation where the amplitude of the peaks remains constant. Thus, the automatic gain control voltage across the capacitor can follow sudden increases in ampliutde of the wave but does not follow sudden decreases in its amplitude as well.

In a circuit of this invention, the charge and discharge time constants can be made the same and short enough to permit the automatic gain control voltage to follow sudden changes in the amplitude of the wave in either direction while at the same time permitting the voltage to remain constant in a situation where there is no change in the amplitude of the wave. It is also possible to make the time constants long and/or different, if desired. In accordance with this invention, this is accomplished by providing two current sources for respectively charging and discharging the capacitor across which the automatic gain control voltage is to be developed and controlling these sources in response to the amplitude of the alternating wave in such manner that the ratio of the charges they pass during a period having a duration equal to half a cycle of the alternating wave depends on whether the amplitude of the wave is greater or less than a predetermined value at which the charges passed are the same. A simple way of doing this is to enable one of the current sources during a period when a half-cycle of the wave exceeds a given level and to enable the other current source during a shorter period when a half-cycle exceeds a higher level. As the amplitude of the wave varies, the ratio of the lengths of the periods during which the current sources are respectively made operative will also vary. In addition, it is necessary that the current source that is enabled for the shorter period be capable of supplying more integrated current during its portion of a half-cycle so that there will be an amplitude of the wave at which the charge supplied by one current source will equal the charge removed by the other current source.

If, as in some embodiments, the current sources are controlled by portions of the wave occurring during their respective periods of enablement, the current gain of the source having the shorter period should be greater than the current gain of the source having the longer period. In another embodiment having constant current sources that are enabled for periods of different lengths, the amplitude of the constant current supplied by the source having the shorter period should be greater than the amplitude of the constant current supplied by the other source.

At the desired amplitude of the wave, the charge added to the capacitor by one current source during its period of enablement is the same as the charge removed from the capacitor by the other current source during its period of enablement so that the net change in charge is zero and the voltage across the capacitor has the same value after the periods that it had before they began. Should the amplitude of the wave increase, the ratio of the lengths of the periods changes so that there is a net change in charge on the capacitor that causes a change in voltage across it in one direction. Should the amplitude of the wave decrease, the ratio of the lengths of the periods changes oppositely so that there is a net change in charge on the capacitor that causes a change in voltage across it in the opposite direction.

FIG. 1 is a schematic representation of one form of circuit embodying the invention;

FIG. 1A ilustrates a wave referenced to ground for which a signal corresponding to its amplitude variation is to be derived;

FIG. 1B illustrates the wave of FIG. 1A referenced to the input of one of the transistors used in the circuit;

FIG. 1C illustrates the currents provided by the current sources of FIG. 1 in a given example;

FIG. 1D is a composite of the currents of FIGURE 1C;

FIG. 1E illustrates the stair step change in voltage that is produced across the output capacitor in the given example;

FIG. 2 is a schematic representation of a circuit embodying the invention in which constant current sources are controlled by comparators;

FIG. 2A represents an input wave V.sub.IN for the circuit of FIG. 2 having the desired amplitude;

FIG. 2B illustrates the current provided by the constant current source of FIG. 2 that has the longer period in response to the input wave V.sub.IN of FIG. 2A;

FIG. 2C illustrates the current provided by the constant current source of FIG. 2 having thge shorter period in response to the input wave V.sub.IN of FIG. 2A;

FIG. 2D illustrates the current flowing through the capacitor of FIG. 2 across which the automatic gain control voltage is developed, in response to an input wave of FIG. 2A;

FIG. 2E illustrates the voltage produced across the capacitor of FIG. 2 across which the automatic gain control voltage is developed in response to an input wave of FIG. 2A;

FIG. 3 is a schematic representation of a circuit embodying the invention in which operational amplifiers are the current sources;

FIG. 3A represents an input wave V.sub.IN that is the same as that shown in FIG. 2A;

FIG. 3B illustrates the current provided by the current source of FIG. 3 having the longer period in response to the input wave of FIG. 3A;

FIG. 3C illustrates the current provided by the current source of FIG. 3 having the shorter period in response to the input wave of FIG. 3A;

FIG. 3D illustrates the current flowing through the capacitor in FIG. 3 across which the automatic gain control voltage is developed in response to the input wave of FIG. 3A; and

FIG. 3E illustrates the voltage produced across the capacitor of FIG. 3 across which the automatic gain control voltage is developed in response to the input wave of FIG. 3A.

FIG. 1 is a schematic diagram of an AGC system utilizing a circuit shown and described in the above-referenced patent application that derives the AGC voltage in accordance with this invention. An unregulated alternating voltage source 2 is coupled to means 4 for controlling its amplitude in accordance with an AGC voltage produced on a lead 6 by an AGC circuit 8. The regulated AC voltage is supplied to any desired load 9 via a lead 10.

A capacitor 12 is connected between the output of the amplitude control means 4 and the bases of dual NPN transistors Q.sub.1 and Q.sub.2, and a resistor 14 is connected between the bases and a point of potential -V. Q.sub.2 is a current source providing a current I.sub.2. Resistors 16 and 18 are respectively connected between the emitters of Q.sub.1 and Q.sub.2 and -V so that the collector currents will be proportional to base voltage above V.sub.BE, which is approximately 0.6 volt. The collector of Q.sub.1 is connected to +V via series resistors 20 and 22, and their junction is connected to the base of an NPN transistor Q.sub.3 having its collector connected to the collector of Q.sub.2 and its emitter connected by a resistor 24 to +V. Q.sub.3 is a current source providing a current I.sub.1. Note that Q.sub.1, Q.sub.2 and Q.sub.3 are such that current can flow through them from +V to -V. One side of the capacitor C is connected to ground and the other side is connected via the lead 6 to the collectors of Q.sub.2 and Q.sub.3. A resistor 26 is connected between -V or +V, in this case -V, and the ungrounded side of C via a switch s.sub.1 that can be momentarily closed for start-up purposes.

Operation of the AGC circuit 8 is as follows. As Q.sub.2 turns on during positive half-cycles, it draws current I.sub.2 from the capacitor C so as to charge the capacitor C negatively. Initially, Q.sub.1 's collector current merely causes a voltage drop across the resistors 20 and 22, but as this current increases it begins to turn on the current source Q.sub.3. If Q.sub.3 has a sufficient beta, its collector current I.sub.1 will increase more than the incremental increase in Q.sub.2 's collector current I.sub.2 above the point where Q.sub.3 starts to conduct. Therefore, even though it starts to conduct later, Q.sub.3 's collector current can quickly exceed that of Q.sub.2. The period of conduction of the current source Q.sub.2 that suplies I.sub.2 is longer than the period of conduction of the current source Q.sub.3 that supplies the current I.sub.1. The current I.sub.3 flowing through the output capacitor C is the difference between I.sub.1 and I.sub.2.

There is a given peak amplitude of the AC voltage at the output of the amplitude control means 4 which will cause Q.sub.2 's and Q.sub.3 's integrated collector currents occurring during each positive half-cycle to be equal so that no net charge is delivered to the capacitor C. Greater peak amplitude than this will cause Q.sub.3 's collector current to dominate so that the voltage on the capacitor C rises incrementally for each oscillator cycle until the peak of the AC voltage at the output of the amplitude control means 4 is reduced to the given peak amplitude. Lesser peak amplitude will cause Q.sub.2 's collector current to dominate so that the voltage on the capacitor C falls incrementally with each succeeding oscillator cycle until the peak amplitude of the AC voltage at the output of the amplitude control means 4 is increased to the given amplitude. At a given frequency of the AC voltage, this operation might be described as a proportional charge pump; that is, for a given amplitude error, a net increment of charge will be transferred to or from the capacitor C during successive cycles of the input frequency. A larger error will cause a proportionally larger charge increment to be transferred to or from the capacitor C.

The waveforms of FIGS. 1A through 1E will be helpful to further visualize the operation of the AGC circuit. FIG. 1A shows the AC waveform at the output of the regulator 4 which is referenced to ground and which is the input to the AGC circuit at the left side of the capacitor 12. It happens to be a little over a volt in peak amplitude. Even though it is difficult to see with the scale used, the amplitude of the AC voltage supplied by the source 2 starts to increase at t=0. FIG. 1B shows the same AC waveform at the right side of the capacitor 12 where it is referenced to -V.

The upwardly extending positive peaks of FIG. 1C show the current flowing through the charging source Q.sub.3 and the downwardly extending negative peaks show the current flowing through the discharging source Q.sub.2. The latter are shown with inverted polarity because I.sub.2 is flowing out of the capacitor C. Note that the discharging current source Q.sub.2 is operative during a first central portion of a half-cycle of the AC wave and that the charging current source Q.sub.3 is operative during a second central portion of the half-cycle that is shorter than the first. The reason for these periods of conduction having different lengths is that Q.sub.3 is not turned on until the current supplied by Q.sub.1 causes the voltage at the junction of the resistors 20, 22 to be sufficient to bias the base of Q.sub.3 for conduction.

FIG. 1D shows the combined collector current of Q.sub.2 and Q.sub.3 on the same plot. The purpose of the capacitor C is to integrate the currents respectively flowing to and from it and to store a resultant voltage during the portion of the alternating waveform when neither Q.sub.2 or Q.sub.3 are conducting. FIG. 1E shows the control signal voltage stored on the capacitor C. One step occurs during each cycle.

At one particular amplitude of the wave, which is the desired amplitude, the current source Q.sub.3 will add as much total positive charge to the output capacitor C as the current source Q.sub.2 removes from it. Even though Q.sub.3 conducts for a shorter period, its current gain is sufficiently greater than that of Q.sub.2 that it can supply the same amount of charge. If the amplitude of the wave increases, Q.sub.1 and Q.sub.2 will be turned on earlier in a half-cycle so that their periods of conduction are increased; but Q.sub.3 will also be turned on earlier in the half-cycle so that its period of conduction is also increased. The ratio of the period of conduction of Q.sub.3 to the period of conduction of Q.sub.2 increases as does the ratio of their respective currents. Then, as the AGC circuit begins to reduce the amplitude of the wave, these ratios start to decrease. The effect of this action is shown by the relationship between the area of the positive pulses with respect to the area of the negative pulses in FIG. 1C and by the positive steps in FIG. 1E that illustrate the voltage across the capacitor C. When the amplitude reaches the desired value, as it nearly does at the right-hand end of the graphs, the area under the positive pulse once again equals the area under the negative pulse and there is no net change in the charge of the output capacitor C.

Although the conduction periods of the current sources occur during the same half-cycle of the applied alternating wave, it would be within the scope of this invention to make them occur during different half-cycles. It is only desirable that the conduction periods take place during a period having a duration of a half-cycle.

As previously noted, the effective time constant of the circuit that is related to reducing the amplitude of a wave and the effective time constant of the circuit related to increasing the amplitude of the wave can be made short and equal, but they can be made longer by increasing the values of the resistors 16 and 18, and they can be made unequal by changing the values of the resistors 22 and 24.

FIG. 2 is a schematic diagram of a circuit embodying the invention in which comparators are used to control the periods of operation of current sources. Components corresponding to those of FIG. 1 have the same designations. The AC waves from the regulator 4 are coupled via the capacitor 12 to the positive inputs of comparators C.sub.1 and C.sub.2 Resistors R.sub.1, R.sub.2 and R.sub.3 are connected in the order named between +V and ground. The negative input of C.sub.1 is connected to the junction of R.sub.1 and R.sub.2 so as to receive a DC voltage T.sub.2, and the negative input of C.sub.2 is connected to the junction of R.sub.2 and R.sub.3 so as to receive a DC voltage T.sub.1 that is less than T.sub.2. A diode d.sub.1 is connected so as to conduct current from the output of C.sub.1 to the gate electrode of a FET F.sub.1, and a resistor 28 is connected between the gate and drain electrodes of F.sub.1. Similarly, a diode d.sub.2 is connected so as to conduct current from the output of C.sub.2 to the gate electrode of a FET F.sub.2, and a resistor 30 is connected between the gate and drain electrodes of F.sub.2. A source 32 of constant current I.sub.1 is connected between +V and the source electrode of F.sub.1, and a source 34 of constant current I.sub.2 is connected between the drain electrode of F.sub.2 and -V. The current sources can be of any suitable type such as field effect or bipolar transistors but I.sub.1 must be greater than I.sub.2. The drain electrode of F.sub.1 and the source electrode of F.sub.2 are connected to the lead 6 on which the output voltage V.sub.O of the circuit that is developed across the output capacitor C appears. The start-up resistor is connected between -V and the lead 6 via a switch s, as in FIG. 1.

The operation of the circuit of FIG. 2 will now be explained with the aid of FIGS. 2A through 2E. FIG. 2A illustrates the AC voltage V.sub.IN that is applied to the positive inputs of the comparators C.sub.1 and C.sub.2. The horizontal dashed lines in FIG. 2A indicate the voltages T.sub.1 and T.sub.2. While V.sub.IN is less than T.sub.1 and therefore less than T.sub.2, the outputs of the comparators C.sub.1 and C.sub.2 have negative voltages that are respectively blocked from the gate electrodes of F.sub.1 and F.sub.2 by the diodes d.sub.1 and d.sub.2. When V.sub.IN reaches the voltage T.sub.1, the output voltage of the comparator C.sub.1 becomes positive so as to cause current to flow through the diode d.sub.1 and the resistor 28 and turn F.sub.1 on. This permits current I.sub.1 of the source 32 to flow to the output capacitor C as shown in FIG. 2B. A little later in the half-cycle, when V.sub.IN reaches the voltage T.sub.2, the output voltage of the comparator C.sub.2 becomes positive so as to cause current to flow through the diode d.sub.2 and the resistor 30 and turn F.sub.2 on.

This permits the current I.sub.2 of the source 34 to flow from the output capacitor C as shown in FIG. 2C. FIG. 2D shows the net current I.sub.3 flowing through the output capacitor C that causes the voltage across C to vary from its initial value -V. With the illustrated values of the amplitudes of V.sub.IN, T.sub.1 and T.sub.2 and the amplitudes of I.sub.1 and I.sub.2, the integrated charging of the output capacitor C by I.sub.2 is equal to the integrated dischaging by I.sub.2 so that the voltage on C after the charging and discharging are completed is the same as it was before, i.e., the start-up voltage +V In this regard, note that the area under the curve of I.sub.1 of FIG. 2B equals the area under the curve of I.sub.2 of FIG. 2C. I.sub.l lasts longer than I.sub.2 but has less amplitude. In this case, the start-up voltage is +V but it could be -V or any value that causes the voltage regulator to make the amplitude of V.sub.IN exceed T.sub.2 so that the circuit can operate as described.

If the amplitude of V.sub.IN increased as indicated by the dashed curve V.sub.IN ' of FIG. 2A, the duration of the flow of I.sub.2 would be a greater fraction of the duration of the flow of I.sub.1 so that there would be a net charge flow through C in a direction to decrease its voltage from the start-up voltage . FIG. 2E shows the change in voltage across the capacitor C.

FIG. 3 is a schematic diagram of a circuit embodying the invention in which operational amplifiers operating as voltage-to-current converters are used as the current sources. Components corresponding to those of FIG. 1 have the same designations. The AC wave from the regulator 4 is coupled via the capacitor 12 and a resistor 38 to the non-inverting input of an operational amplitifer A.sub.1 and via the capacitor 12 and a resistor 38' to the inverting input of an operational amplifier A.sub.2. The inverting input of A.sub.1 is connected via a resistor 40 to a potentiometer 42 connected between +V and ground, and the non-inverting input of A.sub.2 is connected via a resistor 40' to a potentiometer 42' that is connected between +V and ground. The potentiometer 42 supplies a voltage T.sub.1 and the potentiometer 42'  supplies a voltage T.sub.2. The output of A.sub.1 is connected via a resistor 44 to its inverting input and via series resistors 46 and 48 to its non-inverting input. The output of A.sub.2 is connected via a resistor 44' to its inverting input and via series resistors 46' and 48' to its non-inverting input. Diodes d.sub.3 and d.sub.4 are connected in series with like polarity so that they can conduct current from the junction of the resistors 46, 48 to the junction of the resistors 46', 48'. The output capacitor C is connected between the junction of the diodes d.sub.3 and d.sub.4 and ground. The current I.sub.1 that is caused to flow through d.sub.3 by A.sub.1 is equal to K.sub.1 V.sub.IN, and the current I.sub.2 that is caused to flow through d.sub.4 by A.sub.2 is equal to K.sub.2 V.sub.IN, K.sub.1 being greater than K.sub.2.

The operation of the circuit of FIG. 3 will now be explained with the aid of FIGS. 3A through 3E. FIG. 3A illustrates the AC voltage V.sub.IN that is respectively applied to the resistors 38 and 38'. The dashed lines in FIG. 3A respectively represent the voltages T.sub.1 and T.sub.2 supplied by the potentiometers 42 and 42'. During the time that V.sub.IN is less than T.sub.1 and therefore less than T.sub.2, the output of A.sub.1 is negative and the output of A.sub.2 is positive so that no current can flow through either of the diodes d.sub.3 and d.sub.4. When, however, V.sub.IN reaches the voltage T.sub.1, the output of A.sub.1 becomes positive so as to cause a current I.sub.1 =K.sub.1 V.sub.IN to flow through the diode d.sub.3 to the output capacitor C as illustrated in FIG. 3B. A little later in the half-cycle of V.sub.IN, when V.sub.IN reaches the amplitude of T.sub.2, the output of A.sub.2 becomes negative so as to cause a current I.sub.2 =K.sub.2 V.sub.IN to flow from the output capacitor C through the diode d.sub.4 as indicated in FIG. 3C. FIG. 3D shows the net current I.sub.3  flowing through the capacitor C that causes the voltage across C to vary as shown in FIG. 3E. With the illustrated values of the amplitude of V.sub.IN, T.sub.1 and T.sub.2 and the values of K.sub.1 and K.sub.2, the capacitor C is charged as much as it is discharged so that its voltage returns to its initial value of +V. In this case, the area under the curve I.sub.1 of FIG. 3B equals the area under the curve I.sub.2 of FIG. 3C.

If, however, the amplitude of V.sub.IN decreases, as indicated by the dashed line V.sub.IN of FIG. 3A, the integrated flow of I.sub.2 to the integrated flow of I.sub.1 would be smaller so that there would be a net charge flow C in a direction to increase its voltage from the start-up voltage +V.

## Claims

1. A circuit for deriving a gain control voltage that varies in value with changes in the amplitude of a periodic alternating voltage wave, comprising said input, for passing current to said capacitor only during first portions of each cycle of the alternating voltage wave, input, for passing current from said capacitor only during second portions of each cycle of the alternating voltage wave, said second portions having different duration than said first portions, the ratio of the durations of said first and second portions being related to the amplitude of the alternating voltage wave, integrated current as the other during a cycle of the alternating voltage wave when the wave has a given amplitude, more integrated current than the other during a cycle of the alternating voltage wave when its amplitude is greater than the given amplitude, and less integrated current than the other during a cycle of the alternating voltage wave when its amplitude is less than the given amplitude.

2. A circuit as set forth in claim 1 wherein said current sources respectively supply different amlunts of constant current, the current being supplied by the current source that is operative for a lesser portion of each cycle delivering the larger amount of constant current.

3. A circuit as set forth in claim 1 wherein said current sources are amplifiers that are driven by the alternating current voltage wave while they are operative and wherein the amplifier for the current source that is operative for a lesser portion of a cycle has greater current gain than the amplifier for the other current source.

4. A circuit as set forth in claim 1 wherein one of said portions occurs while the alternating voltage wave exceeds a first value and the other of said portions occurs while the alternating voltage wave exceeds a second value that is different from the first.

5. A circuit as set forth in claim 1 wherein one of said portions occurs while the alternating voltage wave exceeds a first value and the other of said portions occurs while the alternating voltage wave exceeds a second value that is different from the first.

6. A circuit for deriving an automatic gain control voltage that varies with changes in amplitude of an alternating voltage wave, comprising transistors having base, emitter and collector electrodes, and collector electrodes, ground, direct current voltage supply, connected in series across said direct current voltage supply so that current can flow through them in the same direction as it flows through the emitter-collector path or said first transistor, electrodes of said first and second transistors, and one side of said direct current voltage supply, transistor and the base electrode of said third transistor, and thrid transistors and the collector of the other.

7. A circuit for deriving an automatic gain control voltage that varies with changes in amplitude of an alternating voltage wave, comprising applied, one of said terminals being grounded, ground, for providing different direct current reference voltages to like inputs of said comparators, other inputs of said first and second comparators, between one side of said direct current voltage source and the ungrounded side of said capacitor so as to cause current to flow through said capacitor in one direction when said first switch is closed, between the other side of said direct current voltage source and the ungrounded side of said capacitor so as to cause current to flow through said capacitor in the opposite direction when said second switch is closed, so as to cause said first switch to close while the alternating voltage wave applied to an input of said first comparator has a given polarity with respect to the reference voltage applied to the other input of said first comparator, and switch so as to cause said second switch to close while the alternating voltage wave applied to an input of said second comparator has said given polarity with respect to the reference voltage applied to the other input of said second comparator.

8. A circuit for deriving an automatic gain control voltage that varies with changes in amplitude of an alternating voltage wave, comprising applied, one of said terminals being grounded, output, output, positive input of one of said operational amplifiers and the negative input of the other operational amplifier, other inputs of said first and second operational amplifiers, of said first operational amplifier and the ungrounded side of said capacitor, the polarity of said unilateral current conducting device being such as to block the flow of current when the alternating voltage wave applied to one of said inputs of said first operational amplifier is less than the direct current voltage applied to its other input and to permit the flow of current in one direction through said capacitor when the alternating voltage wave applied to one of said inputs of said first operational amplifier is greater than the direct current voltage applied to its other input, of said second operational amplifier and the ungrounded side of said capacitor, the polarity of said second unilateral current conducting device being such as to block flow of current between the input of said second operational amplifier and said capacitor, and to permit current to flow through said capacitor in a direction opposite to said one direction when the value of the alternating voltage wave applied to one of the inputs of said second operational amplifier exceeds the value of the direct current voltage applied to the other, the gain of the operational amplifier having the higher direct current voltage applied to one of its inputs being greater than the gain of the other operational amplifier.

9. A circuit comprising, charge to said capacitor when the instantaneous amplitude of the wave has a given relationship to a first threshold, charge from said capacitor when the instantaneous amplitude of the wave has a given relationship to a second threshold, said capacitor by said first source during one cycle of the periodic wave is equal to the charge removed from said capacitor during one cycle of the periodic wave when the maximum amplitude of the periodic gave has a given value, and such that the charge delivered to and removed from said capacitor during one cycle of the periodic that the charge delivered to and removed from said capacitor during one cycle of the periodic wave are unequal when the maximum amplitude of the periodic wave is different from said given value.

10. A circuit as set forth in claim 9 wherein said current sources respectively supply different amounts of constant current, the current being supplied by the current source that is operative for a lesser portion of each cycle delivering the larger amount of constant current.

11. A circuit as set forth in claim 9 wherein said current sources are amplifiers that are driven by the alternating current voltage wave while they are operative and wherein the amplifier for the current source that is operative for a lesser portion of a cycle has greater current gain than the amplifier for the other current source.