# Patent

## Title
Half-bridge circuits employing normally on switches and methods of preventing unintended current flow therein

## Abstract

A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

## Background
This application is a continuation of U.S. patent application Ser. No. 13/021,132, filed on Feb. 4, 2011, now U.S. Pat. No. 8,456,218, which is a continuation of U.S. patent application Ser. No. 12/557,199, filed on Sep. 10, 2009, now U.S. Pat. No. 7,907,001, which is a divisional application of U.S. patent application Ser. No. 11/802,388, filed on May 22, 2007, now U.S. Pat. No. 7,602,288. Each of the above applications is hereby incorporated by reference in its entirety.


BACKGROUND
1. Technical Field
This application relates generally to half-bridge circuits employing normally on switches and to electrical devices which include one or more such circuits.
2. Background of the Technology
Silicon Carbide (SiC), a wide band-gap semiconductor material, is very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. SiC power switches are logical candidates for these applications due to their excellent material physical properties such as wide energy band-gap, high breakdown field strength, high saturated electron drift velocity and high thermal conductivity compared to the conventional silicon counter part. In addition to the above advantages, SiC power devices can operate with much lower specific on-resistance than conventional silicon power devices [1]. Because of these properties, SiC unipolar devices are expected to displace silicon bipolar switches (such as the insulated gate bipolar transistor or IGBT) and rectifiers in the 600-3000 V range.
A necessary component to the value proposition that the market demands to adopt the new SiC switch technology is found in the lower specific on resistance of SiC switches. A factor of ten or more reduction is inherent to SiC devices, but only in the form most likely to produce these specific on-resistance reductions. The SiC junction field effect transistor (JFET) has demonstrated the lowest specific on-resistance of any SiC switch. In particular, the normally on version of this device will minimize the specific on-resistance at any voltage rating. The market place, however, tends to prefer normally off devices because they are perceived as being inherently safe when imbedded in an application.
An independent trend in the market place is to package powerful switches into modules that typically consist of two, four, or six switches arranged in parallel half-bridge configurations. These modules are particularly useful for the control of rotating machinery in devices known as motor drives, the operating principals of which are well known [2, 3]. FIG. 1 illustrates a single half-bridge module containing two silicon IGBT switches. Typical ratings for the switches in the modules are 600-V or 1200-V blocking potential and hundreds of amperes of conduction (e.g., 300-A, 400-A, or 600-A) but the voltages and currents can be higher or lower. The half-bridge interconnection and the constituent IGBT both have weaknesses. The former requires the added complication of an isolated gate driver for the high-side switch. The latter has a gate terminal that can be easily damaged by incorrect or excessively stressful control potentials. The market has responded by including imbedded gate driver circuitry into the switch modules so that the application external to the module does not actually apply potentials to the gate terminals of the IGBTs. This additional level of safety has dramatically increased the reliability of IGBTs used in the field.
There still exists a need, however, for improved circuits and devices which modulate the flow of electrical current from one or more electrical sources to one or more electrical loads.
SUMMARY
According to a first embodiment, a circuit is provided which comprises:

    
    
        a first normally-on switch having a source, a drain and a gate, the source of the first normally-on switch electrically connected to a load and the drain of the first normally-on switch electrically connected to a supply voltage;
        a second normally-on switch having a source, a drain, and a gate, the source of the second normally-on switch electrically connected to a common voltage and the drain of the second normally-on switch electrically connected to the load;
        a first gate driver electrically connected between the gate and the source of the first normally-on switch;
        a second gate driver electrically connected between the gate and the source of the second normally-on switch; and
        a first oscillating power supply electrically connected in parallel across the drain and the source of the first switch, the first power supply configured to power the first gate driver such that, for a given voltage applied to the input to the first power supply, the first power supply generates an output voltage which can be supplied to the gate of the first switch by the first gate driver;
        a second oscillating power supply electrically connected in parallel across the drain and the source of the second switch, the second power supply configured to power the second gate driver such that, for a given voltage applied to the input to the second power supply, the second power supply generates an output voltage which can be supplied to the gate of the second switch by the second gate driver.
    
    


The input-output characteristics of the first power supply can be coordinated with the characteristics of the first switch such that the first switch is in active current limiting mode over at least 50 percent of a voltage range of 0 to the breakdown voltage of the first switch applied to the power supply and wherein the input-output characteristics of the second power supply are coordinated with the characteristics of the second switch such that the second switch is in active current limiting mode over at least 50 percent of a voltage range of 0 to the breakdown voltage of the second switch applied to the second power supply.
The input-output characteristics of the first power supply can be coordinated with the characteristics of the first switch such that the first switch is in active current limiting mode over at least 75 percent of a voltage range of 0 to the breakdown voltage of the first switch applied to the power supply and wherein the input-output characteristics of the second power supply are coordinated with the characteristics of the second switch such that the second switch is in active current limiting mode over at least 75 percent of a voltage range of 0 to the breakdown voltage of the second switch applied to the second power supply.
The input-output characteristics of the first oscillating power supply can be coordinated with the characteristics of the first switch such that the first switch does not overheat when in passive current limiting mode and wherein the input-output characteristics of the second oscillating power supply are coordinated with the characteristics of the second switch such that the second switch does not overheat when in passive current limiting mode.
The first gate driver and the second gate driver can each comprise a totem pole driver.
A device is also provided comprising three circuits as set forth above arranged in parallel, wherein the device is a three-phase motor drive.
The circuit can further comprise an external controller which is adapted to bias the first switch to minimum on-resistance via the first gate driver. The first gate driver can be adapted to apply a bias voltage to the gate of the first switch (VGS) which is equal to the output from the first power supply (−VSS) when the external controller is not biasing the first switch to minimum on resistance.
According to a second embodiment, a circuit is provided which comprises:

    
    
        a first normally-on switch having a source, a drain and a gate, the source of the first normally-on switch electrically connected to a load and the drain of the first normally-on switch electrically connected to a supply voltage;
        a second normally-on switch having a source, a drain, and a gate, the source of the second normally-on switch electrically connected to a common voltage and the drain of the second normally-on switch electrically connected to the load;
        a first gate driver electrically connected between the gate and the source of the first normally-on switch;
        a second gate driver electrically connected between the gate and the source of the second normally-on switch; and
        an oscillating power supply electrically connected across the voltage source and the common voltage, wherein the power supply is configured to power the first and second gate drivers such that, for a given voltage applied to the input of the power supply, the power supply generates a first output voltage which can be supplied to the gate of the first switch by the first gate driver and a second output voltage which can be supplied to the gate of the second switch by the second gate driver.
    
    


According to a third embodiment, an electrical device comprising at least one circuit as set forth above is also provided.
According to a fourth embodiment, an electrical device comprising three circuits as set forth above arranged in parallel wherein the device is a three-phase motor drive is also provided.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an example of a half-bridge switch module consisting of a silicon IGBT (normally off high-side switch) in series with a second IGBT (normally off low-side switch). The module shown in FIG. 1 can also include an anti-parallel diode rectifier (not shown). Isolated power supplies can be used to derive negative and positive potentials to drive the insulated gate of the switch.
FIG. 2 is an example of a half-bridge switch module comprising a normally on switch such as a junction field effect transistor (JFET) in series with a second normally on switch. The module shown in FIG. 2 can also include an anti-parallel diode rectifier (not shown). Isolated power supplies can be used to derive negative and positive potentials to drive the insulated gate of the switch.
FIG. 3 is a schematic diagram of a power half-bridge circuit comprising a normally on junction field effect transistor (JFET) made from silicon carbide in the high and low side switch positions. As shown in FIG. 3, a power supply is connected across the input to the drain and source terminals of each JFET. The input-to-output characteristics of the power supply can be coordinated with the blocking characteristics of the JFET.
FIG. 4 is a schematic diagram of a power half-bridge circuit wherein the input to a single power supply is connected from the upper bus to the lower bus of the half-bridge module. This power supply derives two isolated outputs, one for the high-side JFET and one for the low-side JFET. The input-to-output characteristics of the power supply can be coordinated with the blocking characteristics of the JFET.
FIG. 5 is a graph showing coordination between the input-output characteristic of the power supply and the blocking characteristic of the corresponding normally on switch (e.g., JFET) protected by the power supply.
FIG. 6 is a further illustration of the coordination between the input-to-output characteristic of the power supply and the family of curves of the normally on JFET while the JFET is in the passive current limiting mode.
FIG. 7 is a schematic diagram of one physical implementation of the power supply based on a non-isolated Cuk converter that is connected across the drain-to-source terminals of the protected JFET.
FIG. 8 is a plot of the experimental data measured using the physical implementation shown in FIG. 7. In the figure the data marked “required” refers to the experimental blocking characteristic curve of the SiC JFET being controlled by the gate drive. The data marked “derived experimentally” is the input-to-output characteristic of the power supply shown in FIG. 7.
FIG. 9 is a schematic diagram of an electrical device comprising three circuits as shown in FIG. 3, arranged in parallel.
FIG. 10 is a schematic diagram of an electrical device comprising three circuits as shown in FIG. 4, arranged in parallel.
FIG. 11 shows schematically a diagram of a power half-bridge circuit having an external controller adapted to bias the first switch to minimum on-resistance via the first gate driver.



DETAILED DESCRIPTION
A method for rendering the use of normally on switches inherently safe when packaged in a module consisting of one or more switches that are in turn arranged and controlled so as to modulate the flow of electrical current from one or more electrical sources to one or more electrical loads is described. The switches can be made from a semiconductor material such as silicon or silicon carbide. The normally on switch can be a junction field effect transistor (JFET), but the methods are not limited to such switches. Any normally on switch that exhibits a proportional relationship between the potential applied across the control terminals of the device and the potential that the device can block across the controlled terminals of the device without the flow of excessive leakage current can be rendered safe by the methods described herein.
A described herein, a circuit can be added to the gate drive circuitry of each switch in the module such that a normally on switch can have the same inherent safety, from the point of view of the external terminals of the module, that is usually available only from a normally off switch. In this way, better performing normally on switches can be used in the module without compromising the safety, or the perception of safety, in the eyes of the application designer. Furthermore, the circuitry can be coordinated with the physical properties of the switch to ensure a safe (i.e., non-damaging) response to any potential applied to the switch. An exemplary, non-limiting example of the normally on switch is a silicon carbide power JFET.
As set forth above, a method for rendering a half-bridge circuit containing normally on switches, such as junction field effect transistors (JFETs) made, for example, from silicon carbide or from silicon, inherently safe from uncontrolled current flow (i.e., “shoot through”) is provided. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of such integrated power modules.
As set forth herein, a power supply may be added to the gate driver circuitry. The power supply may be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch. Such a configuration is common to a wide class of devices known as integrated power modules. The methods described herein, however, are not limited to integrated power modules. Rather, these methods are applicable to any system consisting of one or more half-bridge circuits. A common example is the three-phase electric motor drive, which uses three half-bridge circuits in parallel.
As also described herein, the terminal characteristics of the normally on switch can be coordinated to the input-to-output characteristics of the power supply. The details of the coordination and the results from a working model are described below.
An object of the present invention is to illustrate a means for rendering normally on power semiconductor switches with the same inherent safety against potentially damaging unintended flow of electrical current that is provided by the normally off switches.
A further object of the invention is to describe the interconnection of additional circuitry in the gate driver portion of the typical power switch module that provides one aspect of the means for rendering normally on switches inherently safe.
A further object of the invention is to describe the coordination between the properties of the additional circuitry and the properties of the normally on power switch that results in the inherently safe design.
A further object of the invention is to describe the constraints that define the “crossover” between active current limiting, which is provided by the additional circuitry mentioned above, and passive current limiting, which is provided by the normally on power switch itself.
As described herein, the result of these various objects is a means of rendering the normally on power switch inherently safe that is robust, technically feasible, and consistent with current and future design practice in power modules.
The benefits of the current invention are considerable. For example, better performing normally on power switches can be used in power modules, especially when the switches are made from silicon carbide, which will shrink the size and weight of these modules and make them more efficient. In addition, it is likely that more applications for power modules will become possible because of the faster switching performance typical of unipolar devices over bipolar devices.
The present invention will be described in greater detail hereafter with reference to the accompanying drawings, in which a preferred embodiment of the invention is described with silicon carbide (SiC) normally on Junction Field Effect Transistors (JFETs).
By “normally on” it is meant a transistor switch that will conduct significant current when no voltage or current bias is applied to the gating terminal of the transistor.
Silicon carbide crystallizes in more than 200 different poly-types. The most important are: 3C-SiC (cubic unit cell, zincblende); 2H-SiC; 4H-SiC; 6H-SiC (hexagonal unit cell, wurtzile); and 15R-SiC (rhombohedral unit cell). However, the 4H-polytype is more attractive for power devices thanks to its larger bandgap and higher electron mobility. Although 4H-SiC is preferred, it is to be understood that the present invention is applicable to devices made of other poly-types of silicon carbide or made from elemental silicon, by way of example.
Referring to FIG. 1, an example schematic of a two-switch half bridge commonly used by itself as a power processor in numerous power electronic applications (e.g., dc-dc converter [1] and dc-ac inverters [2]) or as a building block for three-phase inverters which typically requires three half-bridge circuits in parallel [3]. The switches illustrated in FIG. 1 are normally off insulated gate bipolar transistors (IGBT). In modules spanning the range of voltage ratings from 600 V to thousands of volts and spanning the range of current ratings from 50 A to thousands of amperes, the silicon IGBT is most common. While a negative gate potential is not generally required to cause the IGBT switch to be in the non-conducting state, FIG. 1 includes the possibility of a negative potential (−VSS in FIG. 1) because this is known to improve the efficiency of switching certain types of IGBTs in applications [4].
New switch technology in the form of normally on SiC JFETs have exhibited the lowest specific on-resistance and the lowest gate charge figures of merit among power semiconductor devices with voltage ratings substantially above 300 V, and thus have the potential to displace silicon IGBTs in many of their current and future applications [5]. The advantages of using a unipolar device, like the SiC JFET, over a bipolar device, like the Si IGBT, can accrue benefits such as better switching response, lower forward conduction loss, and relaxed thermal management. In contrast, traditional silicon unipolar devices such as the MOSFET simply cannot deliver low enough forward conduction loss to compete with the silicon IGBT, especially at voltages above 600-V. Non-traditional normally on silicon and silicon carbide unipolar devices are competitive, the latter extremely so.
As illustrated in FIG. 2, a normally on silicon JFET (also known as the static induction transistor or SIT) has been used to make power inverters [6]. However, for these devices the negative potential required to pinch-off a normally on switch and thus render it in the non-conducting state is derived from the power supply powering the gate driver in a manner similar to that commonly provided for normally off switches. The disadvantage of this approach is that if the source of isolated power is removed (e.g., by accident or by failure) then the means for supplying the necessary negative potential is also removed. This can leave the half bridge made from normally on switches in an uncontrolled conducting state which can severely damage the semiconductor switches and/or the external load or source by permitting uncontrolled and excessive electrical current flow (sometimes referred to as “shoot through”). This concern, above all, has favored the silicon IGBT over the silicon JFET in virtually all practical applications.
Referring now to FIG. 3, a schematic block diagram is shown for a power half-bridge circuit comprising a normally on junction field effect transistor (JFET) made from silicon carbide in the high and low side switch positions. The provision of negative gate potential is no longer dependent on an isolated power source, although one can still be provided as a means of redundancy. Instead, or in addition, a power supply is connected across the drain and the source terminals of the normally on switch (e.g., a JFET as depicted in FIG. 3). This power supply can have input-to-output characteristics which are coordinated with the electrical characteristics of the JFET in a manner described below. This coordination can be used to ensure that, for any combination of electrical potentials applied across the drain and source terminals of the JFET, an uncontrolled electrical current cannot flow through the JFET. In FIG. 3, two power supplies are shown, one for each switch of the half bridge. This arrangement provides maximum protection to each JFET. In one embodiment, as shown in FIG. 11, the power half-bridge circuit includes an external controller that is configured to bias the first switch to minimum on-resistance via the first gate driver.
FIG. 4 illustrates an alternative embodiment in which a single power supply with appropriately coordinated input-to-output characteristics is used to derive the negative potential for both JFETs in the half bridge. The power supply in the device shown in FIG. 4 is isolated. The device depicted in FIG. 4 can be used in applications where the source of potential that can be applied to the JFETs in the half bridge is limited to the upper and the lower bus connections spanned by the half bridge. The configuration shown in FIG. 3 can be used in all power module applications. The device shown in FIG. 4 is suitable for many common applications and has the advantage of requiring only one power supply which may reduce cost and part count.
The power supply illustrated in FIG. 3 and FIG. 4 derives power to operate from the source of potential applied to either the drain-source terminals (FIG. 3) or the upper and lower buses (FIG. 4). In addition, the power supply depicted in FIGS. 3 and 4 will start oscillating automatically upon application of a voltage to its input.
In addition, the input-to-output characteristics of the power supply can be coordinated with the semiconductor device or devices being protected. For example, the voltage that a vertical power JFET will block can be represented on a graph as illustrated in FIG. 5. On the horizontal axis or abscissa is plotted the potential applied across the gate to the source of the JFET. On the vertical axis or ordinate is plotted the potential applied across the drain to the source of the JFET when the specified leakage current flows into the drain. The solid curve on the graph traces the blocking characteristics of the JFET. The gate-source voltage can be positive or negative, but VDS@ID=Ileakage increases monotonically as the gate-source voltage decreases. If VGS>Vthreshold and ID is limited to ≦Ileakage, then no appreciable VDS can be blocked. The maximum voltage that the JFET can block is given by BVDSS which occurs when VGS=VGS(off). A “normally on device” is generally one in which Vthreshold<0. Even though it is a normally on device, it may not reach its full ability to conduct (i.e., exhibiting the minimum resistance to electrical current) until VGS>0.
Superimposed on the graph in FIG. 5 is a dashed line which represents the input-to-output characteristics of the self-oscillating power supply. When a certain VDS is applied to the input of the power supply, it will generate an output that is applied to VGS by the gate driver circuit. The locus of ordered pairs of VGS and VDS is represented by the dashed line. According to some embodiments, coordination can be used to ensure that the dashed line falls below the solid line for the majority of applied VDS. For the region where this is true, labeled “active current limiting” on the graph, it is certain that the applied VDS will produce a leakage current through the JFET that is less than Ileakage. In other words, over the range of VGS corresponding to active current limiting the JFET is safely in its non-conducting state, which means the current flowing through the JFET will be very small and inconsequential. The cross over voltage is defined as the boundary value of VGS separating the active current limiting mode from the passive current limiting mode.
When VGS is greater than the cross over voltage, the JFET is at least partly passively limiting the current. If the gate driver is not actively commanded by an external controller to bias the JFET to minimum on-resistance, then the gate driver design will inherently cause VGS=−VSS≦0. The design of gate drive circuits satisfying this requirement is simple and reliable, and known to those skilled in the art. When the JFET is passively limiting the current, it is dissipating more energy that when it is actively limiting the current. The locus of VGS vs. VDS produced by the power supply can be such that, when VGS is greater than the cross over voltage, the JFET will not overheat. To those skilled in the art, this means that the JFET remains within its safe operating area at all times.
FIG. 6 illustrates the general condition under which safe passive current limiting will be achieved. The graph plots the JFET's drain current (ID) on the ordinate and the drain-source voltage (VDS) on the abscissa. A family of curves is drawn on the graph by graphing the ordered pairs of ID vs. VDS for a constant VGS, and then incrementing VGS and redrawing the ID vs. VDS curve. In FIG. 6 it is assumed that VGS ranges from positive values to negative values. The last curve plotted is that for VGS=Vthreshold. VGS=0 V is another curve indicated on the graph. An example of a family of curves for a SiC JFET might cover −4 V≦VGS≦+3 V. The more negative that VGS becomes, the more resistive the JFET becomes, which reduces ID at any given VDS. As long as the gate driver is preventing uncontrolled current from flowing through the JFET, then VGS will be clamped to −VSS (i.e., VGS=−VSS). Since the maximum value of −VSS=0, then it is not possible for ID to fall on a line above the VGS=0 V curve. In practice, even a modest VDS will cause −VSS<0, thus ID must always fall on a line below that bounded by the VGS=0 V curve. This limiting load line is plotted on the graph in FIG. 6 as a dashed line. By definition, the safe operating area (SOA) of the JFET will be bounded at low VDS by the rated maximum allowable current of the JFET. In turn, the maximum allowable current will fall on the minimum resistance curve. In the case of a typical SiC JFET, the minimum resistance curve will occur well above the VGS=0 V curve. For example, in the range 0 V<VGS≦+3 V, as is illustrated in FIG. 6. As a result it is not possible while the gate driver clamps VGS=−VSS for the drain current through the JFET to exceed that permitted by the SOA. In other words, while in the passive current limiting mode the current flowing through the JFET may not be very small, but it will be inconsequential from the standpoint of damaging the JFET.
Referring now to FIG. 7, a schematic diagram of a circuit including an exemplary and non-limiting embodiment of a self oscillating power supply is illustrated. This circuit is the Cuk converter useful for converting an input voltage into an output voltage that is smaller in magnitude and opposite in polarity. The circuit shown in FIG. 7 includes a normally-on switch having a gate, a source and a drain, and a Totem pole driver electrically coupled to the gate of the switch. The Totem pole driver has a positive supply voltage, V+, and a negative supply voltage, V−. The circuit also includes a first capacitor, C1, a second capacitor, C2, a first inductor, L1, a second inductor L2, and a diode, D1. The first inductor, L1 is electrically connected between the drain of the switch and one terminal of the first capacitor C1, where its other terminal is electrically connected to the anode of the diode D1. The cathode of the diode D1 is electrically connected to the source of the switch. The second inductor L2 is electrically connected between the anode of the diode D1 and the negative supply voltage V− of the Totem pole driver. The second capacitor, C2 is electrically connected between the negative supply voltage V− of the Totem pole driver and the source of the switch. Additionally, the circuit further includes a third capacitor, Cin, electrically connected between the drain and source of the switch. The power supply shown in FIG. 7 is non-isolated. It is therefore suitable for use in the circuit illustrated in FIG. 3.
As illustrated in FIG. 8, the power supply shown in FIG. 7 accepts a positive input voltage ranging from 0 to 600 V and converts it into a negative output voltage ranging from 0 to −50 V. The cross over voltage for this power supply occurs at approximately VGS=−5 V which easily satisfies the safe operating area criteria for a SiC power JFET paired with the power supply.
FIG. 9 is a schematic of an electrical device comprising three circuits as depicted in FIG. 3 arranged in parallel according to one embodiment. The device depicted in FIG. 9 can be a three-phase motor drive.
FIG. 10 is a schematic of an electrical device comprising three circuits as depicted in FIG. 4 arranged in parallel according to one embodiment. The device depicted in FIG. 10 can be a three-phase motor drive.
While the foregoing specification teaches the principles of the present invention, with examples provided for the purpose of illustration, it will be appreciated by one skilled in the art from reading this disclosure that various changes in form and detail can be made without departing from the true scope of the invention.
REFERENCES


    [1] Issa Batarseh, Power Electronic Circuits. Wiley, ISBN 0-471-12662-4, 2004, pp. 224-225.
    [2] Issa Batarseh, Power Electronic Circuits. Wiley, ISBN 0-471-12662-4, 2004, pp. 426-427.
    [3] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics. Wiley, ISBN 0-471-58408-8, 1995, p. 225.
    [4] S. Abedinpour and K. Shenai, “Insulated Gate Bipolar Transistor,” Power Electronics Handbook, ed. M. Rashid. Academic Press, ISBN 0-12-581650-2, 2001, pp. 109-110.
    [5] M. S. Mazzola, L. Cheng, J. Casady, D. Seale, V. Bondarenko, R. Kelley, and J. Casady, “Scalable SiC Power Switches for Applications in More Electric Vehicles,” Proc. of 6th Int. All Electric Combat Vehicle Conf., AECV 2005, Bath, England 13-16 June, 2005.
    [6] H. Akagi, T. Sawae, and A. Nabae, “130 kHz 7.5 kW current source inverters using static induction transistors for induction heating applications,” IEEE Trans. Power Electronics, vol. 3, no. 3, pp. 303-309, 1988.

## Claims

1. A device comprising:
a half bridge configuration of multiple switches arranged in series, the multiple switches of the half bridge configuration comprising a normally-on semiconductor switch having a source, a drain, and a gate, wherein the normally-on semiconductor switch is able to block an electric potential difference between the drain and the source without an excessive leakage current, wherein the blockable electric potential difference varies with an electric potential difference across the gate and the source, wherein the half bridge configuration further comprises
an oscillating power supply electrically coupled in parallel across the drain and the source and supplied with power by the electric potential difference between the drain and the source to generate an output voltage, and
a gate driver coupled between the gate and the source to apply the electric potential difference across the gate and the source and thereby switch the normally-on semiconductor switch between an on state and an off state, wherein the gate driver is powered by the output voltage generated by the oscillating power supply,
wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for any electric potential difference between the drain and the source of the normally-on semiconductor switch, the excessive leakage current cannot flow through the normally-on semiconductor switch.

2. The device of claim 1, wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for an active current limiting range of the electric potential difference across the gate and the source, the output voltage generated by the oscillating power supply for a given electric potential difference between the drain and the source suffices to ensure that, upon application of the output voltage across the gate and the source, the blockable electric potential difference remains above the electric potential difference between the drain and the source.

3. The device of claim 2, wherein the active current limiting range encompasses a majority of the electric potential differences between the drain and the source.

4. The device of claim 2, wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for a passive current limiting range of the electric potential difference across the gate and the source, the electric potential difference between the drain and the source is so low that the normally-on semiconductor switch itself passively limits current flow between the source and the drain to be below the excessive leakage current.

5. The device of claim 1, wherein the gate driver is to apply the output voltage generated by the oscillating power supply between the gate and the source to bias the gate negatively with respect to the source in response to an absence of a control signal to turn on the normally-on semiconductor switch.

6. The device of claim 1, wherein the output voltage generated by the oscillating power supply is smaller in magnitude and opposite in polarity to the electric potential difference between the drain and the source.

7. The device of claim 1, wherein:
the multiple switches of the half bridge configuration further comprise a second normally-on semiconductor switch having a second source, a second drain, and a second gate, wherein the second normally-on semiconductor switch is able to block an electric potential difference between the second drain and the second source without a second excessive leakage current, wherein the blockable second electric potential difference varies with an electric potential difference across the second gate and the second source; and
the half bridge configuration further comprises
a second oscillating power supply electrically coupled in parallel across the second drain and the second source and supplied with power by the electric potential difference between the second drain and the second source to generate a second output voltage, and
a second gate driver coupled between the second gate and the second source to apply the electric potential difference across the second gate and the second source and thereby switch the second normally-on semiconductor switch between an on state and an off state, wherein the second gate driver is powered by the second output voltage generated by the second oscillating power supply,

wherein the second oscillating power supply and the second normally-on semiconductor switch are coordinated so that, for any electric potential difference between the second drain and the second source of the second normally-on semiconductor switch, the second excessive leakage current cannot flow through the second normally-on semiconductor switch.

8. The device of claim 1, wherein the normally-on semiconductor switch is a high-side switch in the half bridge configuration.

9. The device of claim 1, wherein the output voltage generated by the oscillating power supply varies with the electric potential difference between the drain and the source.

10. A device comprising:
a half bridge configuration of multiple switches arranged in series, the multiple switches of the half bridge configuration comprising a normally-on semiconductor switch having a source, a drain, and a gate, wherein the half bridge configuration further comprises:
an oscillating power supply electrically coupled in parallel across the drain and the source of the normally-on switch and supplied with power by a potential difference between the drain and the source, the oscillating power supply to convert the potential difference between the drain and the source into an output voltage, and
a gate driver coupled between the gate and the source of the normally-on switch to switch the normally-on semiconductor switch between an on state and an off state, wherein the gate driver is to apply the output voltage between the gate and the source to bias the gate negatively with respect to the source in response to an absence of a control signal to turn on the normally-on semiconductor switch.

11. The device of claim 10, wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for any electric potential difference between the drain and the source of the normally-on semiconductor switch, the excessive leakage current cannot flow through the normally-on semiconductor switch.

12. The device of claim 11, wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for an active current limiting range of the electric potential difference across the gate and the source, the output voltage generated by the oscillating power supply for a given electric potential difference between the drain and the source suffices to ensure that, upon application of the output voltage across the gate and the source, the blockable electric potential difference remains above the electric potential difference between the drain and the source.

13. The device of claim 12, wherein the active current limiting range encompasses a majority of the electric potential differences between the drain and the source.

14. The device of claim 12, wherein the oscillating power supply and the normally-on semiconductor switch are coordinated so that, for a passive current limiting range of the electric potential difference across the gate and the source, the electric potential difference between the drain and the source is so low that the normally-on semiconductor switch itself passively limits current flow between the source and the drain to be below the excessive leakage current.

15. The device of claim 10, wherein the gate driver is to apply the output voltage generated by the oscillating power supply between the gate and the source to bias the gate negatively with respect to the source in response to an absence of a control signal to turn on the normally-on semiconductor switch.

16. The device of claim 10, wherein the output voltage generated by the oscillating power supply is smaller in magnitude and opposite in polarity to the electric potential difference between the drain and the source.

17. The device of claim 10, wherein:
the multiple switches of the half bridge configuration further comprise a second normally-on semiconductor switch having a second source, a second drain, and a second gate; and
the half bridge configuration further comprises:
a second oscillating power supply electrically coupled in parallel across the second drain and the second source of the second normally-on switch and supplied with power by a potential difference between the second drain and the second source, the second oscillating power supply to convert the potential difference between the second drain and the second source into a second output voltage, and
a second gate driver coupled between the second gate and the second source of the second normally-on switch to switch the second normally-on semiconductor switch between an on state and an off state, wherein the second gate driver is to apply the second output voltage between the second gate and the second source to bias the second gate negatively with respect to the second source in response to an absence of a control signal to turn on the second normally-on semiconductor switch.

18. The device of claim 10, wherein the normally-on semiconductor switch is a high-side switch in the half bridge configuration.

19. The device of claim 10, wherein the output voltage generated by the oscillating power supply varies with the electric potential difference between the drain and the source.