# Patent

## Title
Edge rate control gate driver for switching power converters

## Abstract

This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

## Background
CLAIM OF PRIORITY
This patent application claims the benefit of priority, under 35 U.S.C. Section 119(e), to Mulligan et al., U.S. Provisional Patent Application Ser. No. 61/441,731, entitled “EDGE RATE CONTROL GATE DRIVER FOR SWITCHING POWER CONVERTERS,” filed on Feb. 11, 2011, which is hereby incorporated by reference herein in its entirety.


BACKGROUND
Switching power converters can generate unwanted electromagnetic interference (EMI) due to fast transitions at their switching nodes. The switching transitions can be slowed, for example, using a resistor current ballast. However, such solutions can result in non-linear switching edges that are not predictable or controllable.
OVERVIEW
This document relates generally to apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.
This section is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.



BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
FIG. 1 illustrates generally an example of a gate driver applied to a boost switching converter.
FIG. 2 illustrates generally an example of a boost converter including an edge rate control (ERC) gate driver.
FIG. 3 illustrates generally waveforms associated with an example method of operating the boost converter of FIG. 2.
FIG. 4 illustrates generally an alternative example of a boost controller with a ERC gate driver.
FIG. 5 illustrates generally and alternative example of a boost converter including a ERC gate driver.



DETAILED DESCRIPTION
The present inventors have recognized a system to reduce EMI by slowing the switching node transitions of a converter power switch in a controlled, yet efficient manner. In an example, a constant current gate driver can control the charging of gate-to-drain capacitance of the power switch. Such gate to drain capacitance can be a parasitic capacitance or an explicit capacitor of the converter power switch. Such capacitance can be a dominant parameter when controlling a power MOSFET, such as one employed in a switching power converter. In an example, rise and fall times of a power MOSFET switching node can become a function of the charging current. In certain examples, increased efficiency can be realized using switched current sources that consume little if any power outside of the intervals for transitions of a switched node state, for example between a first high logic level state and a second low logic level state.
In certain examples, a power converter can include a current source gate driver that can control the charging of capacitance of a power converter switch, such as parasitic capacitance of the power converter switch. Such parasitic capacitance can determine rise and fall times of switching nodes of the power converter. In an example, the current source gate driver can slow switch node transitions in a controlled and efficient manner. For example, the gate drive according to the present subject matter can reduce static bias current compared to similarly sized existing switching converters. In certain examples, feedback can be applied to improve speed and reliability of the power converter.
FIG. 1 illustrates generally an example of a gate driver for a boost converter 100. The boost converter 100 includes the gate driver 101, a power switch 102, an inductor 103, a second power switch, such as a diode 104, and a converter output 105. In certain examples, the boost converter 100 can include one or more of a load capacitor 106 and a load resistor 107 coupled to the converter output 105. The gate driver 101 can include an input 108 coupled to first and second driver switches 109, 110. In an example, the first driver switch 109 can be coupled to a first logic level supply Vdd and the second driver switch 110 can be coupled to a second logic level supply Vcc. The first and second driver switches 109, 110 can be coupled to each other and a driver output 111. The driver output 111 can be coupled to a control node 112 of the power switch 102, such as a gate node of a power transistor. In an example, switching action of the control node 112 can be that of a high-low-high inverter transition. Gate-to-drain capacitance of device the power switch 102 can represent a dominant element that can determine a switching speed of a switched node 113 of the boost converter 100. During a transition of an input signal, such as a received pulse width modulated (PWM) signal, the control node 112 can be pulled high or low through a very low impedance path, for example including either the first driver switch 109 or the second driver switch 110. Characteristics of a transition at the switched node 113 can be a function of the load coupled to the converter output 105 for low to high logic level transitions of a switched node Vgs of the power switch 102, and of the first logic level supply Vdd and device size of the first driver switch 109 for high to low logic level transitions of switch node 113.
FIG. 2 illustrates generally an example of a boost converter 200 including an edge rate control (ERC) gate driver 201. The boost converter 200 can include the ERC gate driver 201, a power switch 202, an inductor 203, a second power switch, such as a diode 204, and a converter output 205. In certain examples, the boost converter 200 can include one or more of a load capacitor 206 and a load resistor 207 coupled to the converter output 205. The ERC gate driver 201 can include an input 208 coupled to first and second driver switches 209, 210.
In an example, the first driver switch 209 can be coupled to a first logic level supply Vdd and the second driver switch 210 can be coupled to a second logic level supply Vcc. The first and second driver switches 209, 210 can be coupled to each other and a driver output 211. The driver output 211 can be coupled to a control node 212 of the power switch 202, such as a gate node of a power transistor. The power switch 202 can include a capacitance 213. The capacitance 213 can be associated with the structure of the power switch 202 or can include one or more capacitors associated with the power switch circuit.
The ERC gate driver 201 can include a first switched current source 214, and a second switched current source 215. In an example, each of the first switched current source 214 and the second switched current source 215 can include a current mirror. Each current mirror can include a current sense transistor 216, 217 and a current mirror transistor 218, 219. Each current mirror can detect a sensed current IC flowing through the sense transistor 216, 217 to provide a controlled mirrored current IA, IB to charge and discharge the power switch capacitance 213.
In an example, the sensed current IC for the first and second current mirrors can be set independently. In an example, a third current source 220 that can control the sensed current IC. In an example, each current mirror can provide a scaled representation of the sensed current IC as the mirror current IA, IB, such that the sense current IC is substantially smaller than the mirror current IA, IB.
In an example, the third current source 220 can include a controller. The controller can receive the input signal and can independently switch the first and second switched current sources 214, 215. In certain examples, the third current source 220 can be adjustable to allow individual or dynamic adjustment of an edge rate of a signal at the output 205. In certain examples, a controlled current can provide a smoother transition between the first state of the power switch 202 and the second state of the power switch 202. In certain examples, controlled ramping between power switch states can provide fast switching with reduced and bandwidth limited EMI.
FIG. 3 illustrates generally waveforms associated with an example method of operating the boost converter of FIG. 2. In an example, at time t0, a low logic signal, such as a pulse width modulated (PWM) signal, can be present at the input 208, and a corresponding high logic level can be at the control node (Vg) 212, or gate, of the power switch 202. In a steady state, the power switch 202 can couple the inductor to the second supply voltage Vcc such that a node common to the power switch 202 and the inductor 203, the switched node, Vgs, is at about the second supply voltage Vcc. At t1, a high PWM signal can be received at the input 208 to the ERC gate driver 201. The high PWM signal can cause current IB to begin discharging the capacitance 213 of the power switch 202, thus, pulling the voltage at the control node Vg 212 toward the second supply voltage Vcc. At t2, the control node Vg 212 can reach a point at which current through the power switch 202 is substantially equal to the current IL through the inductor 203, e.g., IL-IB. The voltage at the gate node Vg 212 can hold nearly constant and the voltage at the switched node Vgs, can begin rising in a substantially linearly fashion. At t3, the voltage at the switched node Vgs reaches approximately a diode drop above the output voltage and the diode 204 begins conducting. The voltage at the control node Vg 212 can continue to discharge the capacitance until reaching about Vcc, at t4.
In an example, a falling transition of the PWM signal at t5 can cause current IA to begin charging the capacitance 213 of the power switch 202, thus, pulling the control node Vg 212 toward the first supply voltage Vdd until it sinks current substantially equal to IA+IL at t6. With the current balanced, the voltage at the control node Vg 212 can remain nearly constant and the voltage at the switched note Vgs of the power switch 202 can begin falling in a substantially linearly fashion. At t7, the voltage at the switched note Vgs of the power switch 202 can reach approximately the second supply voltage Vcc, and the control node Vg 212 can continue to charge until reaching the first supply voltage Vdd at t8. In an example, the second supply voltage Vcc can be ground.
FIG. 4 illustrates generally an alternative example of a boost converter 400 including an ERC gate driver 401, a power switch 402, an inductor 403, a second power switch, such as a diode 404, and a converter output 405. In certain examples, the boost converter 400 can include one or more of a load capacitor 406 and a load resistor 407 coupled to the converter output 405. The ERC gate driver 401 can include an input 408 coupled to first and second driver switches 409, 410. As discussed above with reference to FIG. 2, the ERC gate driver 401 can include a first current mirror 414, a second current mirror 415, and a current source 420 to assist in controlling transition edge rates of the output 405. In addition, the boost converter 400 can include a schmitt trigger circuit 429, including a schmitt trigger 430 and first and second switches 431, 432. The schmitt trigger circuit 429 can provide hard switching of the control node 412 of the power switch 402. In an example, the schmitt trigger circuit 429 can detect that the voltage at the control node 412 of the power switch 402 is near a high or low state, Vdd or Vcc. The Schmitt trigger circuit 429 can turn on the first or second switch 431, 432, respectively, to provide the control node 412 of the power switch 402 with a low impedance path to the first supply Vdd or the second supply Vcc. The low impedance paths provided by the first and second switches 431, 432 can prevent glitches on the control node 412 from affecting a steady state of the power switch 402.
FIG. 5 illustrates generally an alternative example of a boost converter 500 including an ERC gate driver 501, a power switch 502, an inductor 503, a second power switch, such as a diode 504, and a converter output 505. In certain examples, the boost converter 500 can include one or more of a load capacitor 506 and a load resistor 507 coupled to the converter output 505. The ERC gate driver 501 can include an input 508 coupled to first and second driver switches 509, 510. As discussed above with reference to FIG. 2, the ERC gate driver 501 can include a first current mirror 514, a second current mirror 515, and a current source 520 to assist in controlling transition edge rates of the output 505. In certain examples, the boost converter 500 can include a feedback circuit 533 to control the edge rate of the boost converter output 505.
In certain examples, the feedback circuit 533 can include a reference capacitor 534, an error amplifier 535, secondary driver switches 536, 537, secondary current sources 538, 539, and an inverter 540. The feedback circuit 533 can receive a command signal indicative of a desired transition ramp of the boost converter output 505. In certain examples, the command signal can be generated across ihe reference capacitor 534 coupled to a junction Vg between the first and second driver switches 509, 510. The error amplifier 535 can control the secondary current sources 538, 539 using an error signal derived from the command signal and a feedback signal indicative of the switch output Vgs of the power switch 502. In certain examples, the feedback circuit 533 can introduce an inversion, and thus, the inverter 540 can provide the proper control signal for the secondary driver switches 536, 537. In certain examples, the feedback circuit 533 can allow faster transitions of the switched output Vgs of the power switch 502. In certain examples, the transition rate can be adjusted by selecting a different reference capacitor size. In certain examples, the closed loop nature of the feedback circuit 533 can provide a more linear transition of the switched output Vgs of the power switch 502 over open loop edge rate control. The more controlled edge rates can provide more predictable and bandwidth limited EMI, even for faster transitions and, in turn, can provide opportunities for more efficient and precise handling of the EMI. In addition, the more controlled transitions can provide a more efficient boost converter 500.
Additional Notes
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
The above description is intended to be illustrative, and not restrictive. For example, although the examples above have been described relating to PNP devices, one or more examples can be applicable to NPN devices. In other examples, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

## Claims

1. An edge rate driver for a power converter switch, the edge rate driver comprising:
an input node configured to receive a pulse width modulated signal;
a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state;
a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state;
a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch;
a second current source configured to provide discharge current for the second switch when the power converter switch transitions from the first state to the second state, the discharge current configured to discharge the parasitic capacitance of the power converter switch; and
a feedback circuit configured to receive a voltage from an output node of the power converter switch and to modulate a transition of the control node of the power converter switch, the feedback circuit configured to hard switch the control node of the power converter switch;
wherein the feedback circuit includes:
a first hard switch transistor configured to couple the control node of the power converter switch to the supply voltage during the first state;
a second hard switch transistor configured to couple the control node of the power converter switch to the reference voltage during the second state; and
a hysteretic comparator coupled to a control node of the first hard switch transistor and to a control node of the second hard switch transistor, the hysteretic comparator configured to receive the voltage from the output node of the power converter switch to control the control node of the first hard switch transistor and the control node of the second hard switch transistor.

2. The edge rate driver of claim 1, including a third current source coupled to the first current source and the second current source, the third current source configured to control a ramp rate of a voltage at an output of the power converter switch.

3. The edge rate driver of claim 1, wherein
the first current source includes a first current mirror configured to provide a first mirrored current representative of a sensed current;
wherein the third current source is configured to provide the sensed current;
wherein the second current source includes a second current mirror configured to provide a second mirrored current representative of the sensed current; and
wherein the third current source includes an adjustable current source configured to adjust a transition rate of the power converter switch.

4. A method comprising:
receiving a pulse width modulated signal at an input of an edge rate driver for a power converter switch;
coupling a control node of the power converter switch to a supply voltage during a first state using a first switch of the edge rate driver;
coupling a control node of the power converter switch to a reference voltage during a second state using a second switch of the edge rate driver;
charging a parasitic capacitance of the power converter switch using a first current source when the power converter switch transitions from the second state to the first state;
discharging the parasitic capacitance of the power converter switch using a second current source when the power converter switch transitions from the first state to the second state;
receiving a voltage from an output node of the power converter switch at a feedback circuit;
modulating a transition of the control node of the power converter switch using the feedback circuit;
coupling the control node of the power converter switch to the supply voltage during the first state using a first hard switch transistor;
coupling the control node of the power converter switch to the reference voltage during the second state using a second hard switch transistor;
receiving the voltage from the output node of the power converter switch at a hysteretic comparator; and
controlling a control node of the first hard switch transistor and a control node of the second hard switch transistor using an output of the hysteretic comparator and the received voltage from the output node of the power converter switch.

5. The method of claim 4, wherein the charging the parasitic capacitance includes providing a charge current to the first switch using a first current mirror.

6. The method of claim 5, including setting a transition rate of the power converter switch using a sense current of the first current mirror.

7. The method of claim 6, including providing the sense current using an additional current mirror.

8. The method of claim 4, wherein the charging the parasitic capacitance of the power converter switch using a first current source includes providing a charge current to the first switch using a first current mirror of the first current source.

9. The method of claim 8, wherein the discharging the parasitic capacitance includes providing a discharge current from the second switch using a second current mirror.

10. The method of claim 9, including setting a first transition rate of the power converter switch using a first sense current of the first current mirror.

11. The method of claim 10, including setting a second transition rate of the power converter switch using a second sense current of the second current mirror.

12. The method of claim 11, including providing the first sense current using a third current source.

13. The method of claim 12, including providing the second sense current using the third current source.

14. The method of claim 13, including adjusting the third current source to change at least one of the first transition rate or the second transition rate of the power converter switch.