# Patent

## Title
Compacted context state management

## Abstract

Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

## Background
FIELD
Embodiments of the invention relate to microprocessor architecture. More particularly, embodiments of the invention relate to managing context state information within a microprocessor.
BACKGROUND
Modern microprocessors may perform numerous functions requiring a change of context state. For example, a microprocessor may change context state information when switching between groups of instructions, such as software threads. In changing between software threads, for example, context state of one group of instructions may be saved to a memory location and the context state of another group of instructions may be restored from memory and loaded into the microprocessor.
In reference to software threads, “context state” may refer to a portion of each software thread's state that is to be maintained between context switches within a processor. Context state may be stored in processor architectural registers, control registers, or other storage areas, such as memory. Context state is typically represented by a number of bits, the values of which define a particular context state.
The term “context switch” typically refers to a change from one processor execution state to another, such as a software thread switch. A context switch is typically performed either by the operating system or by a user's program. For example, a context switch may occur as a result of calling a subroutine within a user's program, in which the calling program's context is saved in a storage area when the call to the subroutine occurs, and restored from the storage area when returning from the called subroutine.



BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are illustrated by way of example and not limitation in the accompanying figures.
FIG. 1 illustrates a system, memory, and processor supporting, context state management according to an embodiment of the present invention.
FIG. 2 illustrates an un-compacted save area and two compacted save areas according to an embodiment of the present invention.
FIG. 3 illustrates a method for context state management according to an embodiment of the present invention.



DETAILED DESCRIPTION
Embodiments of processors, methods, and systems for compacted context state management are described below. In this description, numerous specific details, such as component and system configurations, may be set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art, that the invention may be practiced without such specific details. Additionally, some well known structures, circuits, and the like have not been shown in detail, to avoid unnecessarily obscuring the present invention.
In the following description, references to “one embodiment,” “an embodiment,” “example embodiment,” “various embodiments,” etc., indicate that the embodiment(s) of the invention so described may include particular features, structures, or characteristics, but more than one embodiment may and not every embodiment necessarily does include the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
As used in the specification and claims, unless otherwise specified, the use of the ordinal adjectives “first,” “second,” “third,” etc. to describe an element merely indicates that a particular instance of an element or different instances of like elements are being referred to, and is not intended to imply that the elements so described must be in a particular sequence, either temporally, spatially, in ranking, or in any other manner.
Also, the terms “bit,” “flag,” “field,” “entry,” “indicator,” etc., may be used to describe any type of storage location, or the content(s) thereof, in a register, table, database, or other data structure, whether implemented in hardware of software, but are not meant to limit embodiments of the invention to any particular type of storage location or number of bits or other elements within any particular storage location. The term “clear” may be used to indicate storing or otherwise causing the logical value of zero to be stored in a storage location, and the term “set” may be used to indicate storing or otherwise causing the logical value of one, all ones, or some other specified value to be stored in a storage location; however, these terms are not meant to limit embodiments of the present invention to any particular logical convention, as any logical convention may be used within embodiments of the present invention.
For convenience and clarity, various instructions may be described using particular names (e.g., XSAVE, XSAVEOPT, XRSTOR, XSAVEC, XSAVEOPTC, XSETBV, XGETBV), however, embodiments of the invention are not limited to those particular instructions as defined or used in any particular processor instruction set architecture. Other instructions and instruction names may be used within various embodiments of the present invention.
Embodiments of the invention pertain to microprocessor architecture. More particularly, embodiments of the invention pertain to managing processor context state. At least one embodiment of the invention introduces extended functionality to some prior art context state managing techniques in order to facilitate resource and performance efficiency when reading and updating context state information within a microprocessor.
All operating system (“OS”) and/or user program typically uses a buffer or other area (“save area”) in a memory structure, such as dynamic random access memory (“DRAM”), for saving context state during a context switch. Instruction set architectures may define one or more instructions to handle the storage of context state to memory or the restoration of context state from memory. For example, in one instruction set architecture, a first state management instruction (“XSAVE”) may be used to store context state from a processor's registers to a memory, or a second state management instruction (“XSAVEOPT”) may be used to store in-use (e.g., not set to an initial or default value) or modified (e.g., changed since the last restoration of context state) context state from a processor's registers to a memory. A third state management instruction (“XRSTOR”) may be used to restore context state from the memory to the processor's registers. The save area layout map may be defined in advance, such that XSAVE or XSAVEOPT stores the context state for any particular processor feature at the same fixed offset every time. For a processor that does not implement every particular feature and/or for an OS that does not enable every available feature, holes may be left in the save area for the unimplemented and/or un-enabled features. Typical operation of a processor may involve thousands of context switches (e.g., between software threads), each using memory space for a save area. Therefore, embodiments of the present invention provide for compacting holes out of the save area to avoid wasting memory space.
FIG. 1 illustrates information processing system 100, including memory 110 and processor 120, according to an embodiment of the present invention. System 100 may represent any type of information processing system, such as a server, a desktop computer, a portable computer, a set-top box, a hand-held device such as a tablet or a smart phone, or an embedded control system.
Memory 110, processor 120, and any number of other components not shown in FIG. 1 may be connected, coupled, or otherwise in communication with each other according to any known approach, such as directly or indirectly through one or more buses, point-to-point, or other wired or wireless interfaces or connections. Any components or other portions of system 100, whether shown in FIG. 1 or not shown in FIG. 1, may be integrated or otherwise included on or in a single chip (a “system-on-a-chip” or “SOC”), die, substrate, or package.
Memory 110 may be static or dynamic random access memory, flash memory, magnetic or optical disk memory, any other type of medium readable by processor 120, or any combination of such mediums. Memory 110 includes state save area 112 to save state of processor 120.
Processor 120 may be any type of processor, including a general purpose microprocessor, such as a processor in the Core® Processor Family, the Atom® Processor Family, or other processor family from Intel Corporation, or another processor from another company, or a special purpose processor or microcontroller. Although FIG. 1 shows only one such processor 120, system 100 may include any number of processors, including any number of multicore processors, each with any number of execution cores and any number of multithreaded processors, each with any number of threads, in any combination. As shown, processor 120 includes instruction hardware 122 and state management logic 124. Processor 120 may also include any other circuitry, structures, or logic not shown in FIG. 1.
Instruction hardware 122 may include any circuitry, logic, structures, and/or other hardware to fetch, receive, recognize, decode, interpret, and/or schedule instructions to be executed by processor 120. Processor 120 may operate according to an instruction set architecture that includes any number of instructions to support context state management. Embodiments of the present invention may be practiced with a processor having an instruction set architecture of a processor family from Intel® Corporation, using instructions that may be part of a set of context state management extensions to any existing instruction set architecture, or according to any other approach.
State management logic 124 is to perform state management operations, as described below. State management logic 124 may include any circuitry, logic, or other structures to perform the state management operations. For example, state management logic 124 may include microcode, state machine logic, programmable logic, or any other form of control logic to cause processor 120 to respond appropriately to state management instructions. To do so, state management logic 124 may refer to any form of hardware, software, or firmware, within processor 120 or within any device accessible or medium readable by processor 120, such as memory 110.
Also, state management logic 124 may include logic and datapaths to read, write, and move state information into, from, and between registers and other storage locations where state information may be stored for internal use and/or to be read by software running on processor 120, and logic to perform masking and other logical operations on bit vectors and/or representations of state information. State management logic 124 may be dedicated to state management or may by used, in whole, in part, and/or together with other logic, to perform other functions, operations, instructions, etc. in processor 120.
State management logic 124 may determine what operation to perform and how to perform the operation based on information provided by an instruction, associated with an instruction (e.g., held in a particular processor register when an instruction is issued, received, or executed), and/or related to other information accessible by state management logic 124. Any known approach to conveying this information from software to state management logic 124 may be used within the scope of the present invention, such as any combination of different instructions, different instruction formats, different operand types and locations, etc. For example, a state management instruction may include a field holding the information, the name of a register holding the information, and/or an address of a memory location holding the information. According to any of these approaches, or any other known approach, the information may be referred to as a “parameter” of the instruction.
State management logic 124 may operate based on signals from instruction hardware 122, and/or based on any parameters associated with a state management instruction, to cause processor 120 to execute portions of method embodiments of the present invention, such as method 300, as illustrated in FIG. 3. For example, control logic 124 may cause processor 120 to execute portions of method embodiments of the present invention by executing one or more micro-instructions or micro-operations in response to receiving a state management instruction.
In one embodiment of the present invention, a fourth state management instruction (“XSAVEC”) may be used to store context state to a compacted save area. The save area layout may be customized to store the context state for any particular processor features without leaving gaps or holes in the layout. An OS or other software may inspect the save area to determine the features for which context state has been saved and/or to operate on the context state for particular features.
An XSAVEC instruction may have as a parameter a compaction mask to specify which features of context state are to be saved. For example, the compaction mask may be a bit vector determined by the concatenated contents of one or more processor registers (e.g., the EDX, ECX, EBX, and/or EAX registers), where each bit of the bit vector corresponds to a particular processor feature and a bit value of ‘1’ may indicate that context state corresponding to the feature is to be saved and a bit value of ‘0’ may indicate that context state corresponding to the feature is not to be saved.
Execution of an XSAVEC instruction causes context state corresponding to the hits set in the compaction mask to be stored in the save area with no gaps in the save area for context state corresponding to the other bits, such that the size of the save area may vary with each execution of the XSAVEC instruction. Furthermore, the location or offset of the context state for any particular feature or element may vary depending on the content of the compaction mask. Therefore, execution of the XSAVEC instruction may also cause the compaction mask to be saved, for example, in the 8 bytes starting at offset 520 in the save area (or the header of the save area).
In one embodiment, the compaction mask may independently specify which elements or features of context state are saved in connection with the execution of an XSAVE instruction. These embodiments may be desirable in an approach in which software may incrementally save context state. In other embodiments, the compaction mask may be logically or otherwise combined with another vector, bitstring, parameter, or other value in order to specify which elements or features of context state are saved in connection which the execution of an XSAVEC instruction.
For example, in one embodiment, the features or elements to be saved by an XSAVEC instruction may be specified by the bitwise logical AND of the compaction mask and a feature enabled mask, where the feature enabled masked may be set in connection with the execution of a fifth state management instruction (“XSETBV”). In one embodiment, XSETBV may be a privileged instruction that may be used by privileged software, such as an OS to specify or otherwise select which features from a set of available processor features are to be enabled. Therefore, context state for un-enabled features will not be saved by an XSAVE or XSAVEC instruction.
In one embodiment, a sixth state management instruction (“XGETBV”) may be used by software to read or otherwise determine which features have been enabled. For example, XGETBV may be a non-privileged instruction to provide for non-privileged software to read the feature enabled mask. A leaf or subleaf (e.g., indicated by a particular value in a particular processor register when an XGETBV instruction is issued, received, or executed) which may cause the processor to return, instead of the feature enabled mask, a vector, bitstring, parameter, or other value that indicates which elements or features of context state are in an initialized state (e.g., their values are in an initial or default state). For convenience, this leaf or subleaf of XGETBV may be referred to as the feature-in-use leaf of XGETBV and the value may be referred to as the feature-in-use mask.
In one embodiment of the present invention, a seventh state management instruction (“XSAVEOPTC”) may be used to store in-use or modified context state to a compacted save area. Again, the save area layout may be customized to store the context state for any particular processor features without leaving holes in the layout. An OS or other software may inspect the save area to determine the features for which context state has been saved and/or to operate on the context state for particular features.
Execution of an XSAVEOPTC instruction causes in-use or modified context state corresponding to the bits set in the compaction mask to be stored in the save area with no gaps in the save area for context state corresponding to the other bits, such that the size of the save area may vary with each execution of the XSAVEOPTC instruction. Furthermore, the location or offset of the context state for any particular feature or element may vary depending on the content of the compaction mask. Therefore, execution of the XSAVEOPTC instruction may also cause the compaction mask to be saved, for example, in the S bytes starting at offset 520 in the save area (or the header of the save area).
A particular bit in the header of the save area e.g., bit 63) may be designated and used to indicate whether the save area is compacted (e.g., corresponds to a save performed in connection with the execution of an XSAVEC or XSAVEOPTC instruction) or un-compacted (e.g., corresponds to a save performed in connection with the execution of an XSAVE or XSAVEOPT instruction). For example, bit 63 may be set during the execution of an XSAVEC or XSAVEOPTC instruction, and clear by default or cleared during the execution of an XSAVE or XSAVEOPT instruction). For convenience, this bit may be referred to as a compacted-save bit.
FIG. 2 illustrates un-compacted save area 210, compacted save area 212, and compacted save area 214 according to an embodiment of the present invention. Each of un-compacted save area 210, compacted save area 212, and compacted save area 214 may represent a buffer or any other data structure or area at any address or location within a memory such as memory 110 in system 100. Un-compacted save area 210 may include a header 220 having a compacted-save bit 230 having a value of zero to indicate that the corresponding save area is un-compacted. Compacted save areas 212 and 214 may each include a header 222 and 224, respectively, each having a compacted-save bit 232 and 234, respectively, set to a value of one to indicate that the corresponding save area is compacted. Compacted save areas 212 and 214 may also each include a compaction mask 240 and 250, respectively, to indicate which features or elements are included in each compacted save area.
In the example embodiment of FIG. 2, a feature set of a processor may include four features. In un-compacted save area 210, context state for a first feature, a second feature, a third feature, and a fourth feature is saved in sections 260, 270, 280, and 290, respectively, where each of sections 260, 270, 280, and 290 may be located according to their particular offset from a base or other address of the save area. The format of save area of 210 is fixed, in other words, context for any particular feature is always saved at the same location within the save area and the size of the save area is constant.
In contrast, context state for any particular feature may be stored at or in a flexible or varying offset, location, or section of a compacted save area, and the size of the save area may vary and be smaller than that of a corresponding un-compacted save area. For example, in compacted save area 212, context state for the first feature, the third feature, and the fourth feature is saved in sections 262, 272, and 282, respectively, where section 262 is located at the same offset as section 260, section 272 is located at the same offset as section 270, and section 282 is located at the same offset as section 280, such that the size of compacted save area 212 may be smaller than that of un-compacted save area 210 because compacted save area 212 does not include a section located at the same offset as section 290. Compaction mask 240 includes bit 242 having a value of one to indicate that compacted save area 212 includes context state for the first feature, bit 244 having a value of zero to indicate that compacted save area 212 does not includes context state for the second feature, bit 246 having a value of one to indicate that compacted save area 212 includes context state for the third feature, and bit 248 having a value of one to indicate that compacted save area 212 includes context state for the fourth feature. Note that although context state for the third and fourth features is saved in compacted save area 212, neither is saved at the same offset in compacted save area 212 as it is in un-compacted save area 210.
To further the example, in compacted save area 214, context state for the third feature is saved in section 264, where section 264 is located at the same offset as sections 260, such that the size of compacted save area 214 may be smaller than that of un-compacted save area 210 and of compacted save area 212, because compacted save area 214 does not include sections located at the same offset as sections 270, 280, or 290. Compaction mask 250 includes bit 252 having a value of zero to indicate that compacted save area 214 does not include context state for the first feature, bit 254 having a value of zero to indicate that compacted save area 214 does not include context state for the second feature, bit 256 having a value of one to indicate that compacted save area 214 includes context state for the third feature, and bit 258 having a value of zero to indicate that compacted save area 214 does not include context state for the fourth feature. Note that although context state for the third feature is saved in compacted save area 214, it is not saved at the same offset in compacted save area 214 as it is in un-compacted save area 210 or compacted save area 212.
Embodiments of the present invention provide for a single instruction (e.g., XRSTOR) to be used to restore context state from either a compacted save area or an un-compacted save area. In one embodiment, execution of an XRSTOR instruction includes determining whether the save area is compacted or un-compacted by reading a compacted-save bit from the header of the save area, which may be set or cleared as described above. If the save area is compacted, then execution of an XRSTOR instruction may also include reading a compaction mask from the save area to determine which elements or features of context state are included in the compacted save area and their locations in the compacted save area. In one embodiment, the context state for elements or features that are not indicated by the compaction mask as being saved or otherwise present in the save area may be restored to an initial or default value. Therefore, software may define an area of any size (e.g., 64-bytes) that may be used to initialize any enabled context state.
In one embodiment, software may restore all context state for all enabled features to initial values without allocating any backing storage for these features, by issuing an XRSTOR instruction with the compaction mask set to all zeroes and the compacted-save bit set to one. An OS or other privileged software may enable particular features without allocating backing storage in a save area for those features, for example, on a per-thread basis. Then, non-privileged software may use the feature-in-use leaf of XGETBV to determine which features are in-use (e.g., having context state not in an initial state) so that it may allocate backing storage for those features on a dynamic or “just-in-time” basis. Therefore, embodiments of the present invention may provide for more efficient use of system memory in an information processing system.
FIG. 3 illustrates method 300 for context state management according to an embodiment of the present invention. Although method embodiments of the invention are not limited in this respect, reference may be made to elements of system 100 to describe the method embodiment of FIG. 3. Method 300 may refer to state management instructions by names that may be used according to one embodiment in other embodiments, these instructions or similar instructions may have different names. Additionally, many associated actions and details may not be shown in method 300; for example, method 300 includes a context switch from a first thread to a second thread, then a context switch back to the first thread, but it does not show the saving of context for the second thread.
In box 310 of method 300, a processor is queried, e.g., by an OS issuing a processor identification (“CPUID”) instruction with an appropriate request type and/or other parameters, to enumerate the features supported by the processor. In box 312, the OS or other privileged software enables a subset of those features.
In box 314, the OS issues an instruction (“XSETBV”) to convey to the state management logic the subset of the features that are enabled. In one embodiment, XSETBV has a parameter to program a bit vector (“XFEATURE_ENABLED_MASK”) to indicate which features are enabled, e.g., using one bit per feature that has a manageable state. A corresponding instruction (“XGETBV”) may be used by software to read XFEATURE_ENABLED_MASK. The XGETBV instructions also may have a leaf to allow it to be used to read another bit vector that indicates which features are currently in use, i.e., their state values have changed since initialization. XSETBV may be a privileged instruction and XBVGET may be a non-privileged instruction.
In box 316, the processor is queried, e.g., by software issuing another instruction (e.g., “XSIZE”), to determine the size required for the state save area based on a bit vector or other parameter that specifies any subset of the set of features supported by the processor. This bit vector may be the same bit vector as the compaction mask described above, a logical combination of the compaction mask and any other bit vector, or any other bit vector. In box 318, software may allocate a portion of memory for a context state save area, where the size of the portion may be based on a value returned or otherwise provided by the XSIZE instruction.
In box 320, the processor may begin executing a first process of thread.
In box 330, in connection with a context switch from the first process or thread to a second process or thread, software may issue an instruction (“XSAVEC”) to save the current context of a subset of the features supported by the processor. XSAVEC may have a parameter (a compaction mask) that provides for selectively controlling the saving of state. The parameter may be a bit vector, with one bit per feature, to select the features for which state should be saved. This bit vector may be combined with XFEATURE_ENABLED_MASK (e.g., with a logical AND operation) by state management logic, such that state is saved only for those features that are both selected and enabled.
In box 332, execution of the XSAVEC instruction may include setting a compacted-save bit or indicator in the save area header or elsewhere in the save area. In box 334, execution of the XSAVEC instruction may include saving the compaction mask in the save area header or elsewhere in the save area.
In box 336, execution of the XSAVEC instruction may include saving context state for each feature selected by the compaction mask or based on the compaction mask combined with the XFEATURE_ENABLED_MASK or other bit vector, such that any feature for which context state is not saved is compacted out of the save area.
In box 338, the context switch may be completed. In box 340, the processor may execute the second process or thread.
In box 350, in connection with a context switch back to the first process or thread, software may issue an instruction (“XRSTOR”) to restore the context saved in box 336. In box 352, execution of the XRSTOR instruction may include reading a compacted-save bit from the save area header to determine whether the save area is compacted. If not, then in box 354, execution of the XRSTOR instruction includes restoring context state from an un-compacted save area. If so, then method 300 continues in box 360.
In box 360, execution of the XRSTQR instruction includes reading the compaction mask from the save area in order to determine which subset of features for which context is to be restored and the offset within the save area of the context for each of the subset of features, hi one embodiment, the offset for any particular’ feature may be determined based on an ordered list of features, where the offset may be based on the total save area size for all features ahead of the particular feature on the list, minus the save area for the features that have been compacted out.
In box 362, execution of the XRSTOR instruction includes restoring context state from the compacted save area for each feature for which context has been saved, according to the compaction mask or the compaction mask combined with the XFEATURE_ENABLED_MASK or other bit vector.
In box 364, execution of the XRSTOR instruction includes initializing context state for each feature which has been compacted out of the save area. In box 366, the context switch may be completed. In box 368, the processor may continue execution of the first process or thread.
Within the scope of the present invention, the method illustrated in FIG. 3 may be performed in a different order, with illustrated boxes omitted, with additional boxes added, or with a combination of reordered, omitted, or additional boxes. Many variations of method 300 and many other methods are possible within the scope of the present invention.
Embodiments or portions of embodiments of the present invention, as described above, may be stored on any form of a machine-readable medium. For example, all or part of method 300 may be embodied in software or firmware instructions that are stored on a medium readable by processor 120, which when executed by processor 120, cause processor 120 to execute an embodiment of the present invention. Also, aspects of the present invention may be embodied in data stored on a machine-readable medium, where the data represents a design or other information usable to fabricate all or part of processor 120.
Thus, embodiments of an invention related to compacted context state management have been described. While certain embodiments have been described, and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure. In an area of technology such as this, where growth is fast and further advancements are not easily foreseen, the disclosed embodiments may be readily modifiable in arrangement and detail as facilitated by enabling technological advancements without departing from the principles of the present disclosure or the scope of the accompanying claims.

## Claims

1. A processor comprising:
instruction hardware to receive a first save instruction and a second save instruction; and
state management logic to:
in response to the first save instruction, save context state of features supported by the processor in an un-compacted format in a first save area having a constant size according to a predefined save area layout map having a plurality of fixed offsets, each corresponding to a particular processor feature of the processor features supported by the processor, and clear a compacted-save bit in the first save area,
in response to the second save instruction, save a compaction mask and the context state of a subset of processor features supported by the processor in a compacted format in a second save area having a variable size according to the compaction mask to provide for a plurality of variable offsets per feature and set a compacted-save bit in the second save area, and
in response to a single restore instruction specifying a save area, read a compacted-save bit from the save area to determine whether the save area is an un-compacted save area saved in an un-compacted format or a compacted save area saved in a compacted format,
in response to determination that the compacted-save bit is set, read the compaction mask from the save area in order to determine which subset of processor features are to be restored and restore the context state of each processor feature of the subset of processor features indicated by the compaction mask.

2. The processor of claim 1, wherein the compaction mask is to indicate the subset of processor features, where the context state is to be saved only for the subset.

3. The processor of claim 2, wherein the compacted format is to include the context state for the subset without gaps for features having unsaved context state.

4. The processor of claim 3, wherein the state management logic is also to include a bitwise AND gate to combine the compaction mask with a feature-enabled mask, where an output of the bitwise AND gate is to be used to determine the subset.

5. The processor of claim 4, wherein the instruction hardware is also to receive a first state management instruction to set the feature-enabled mask.

6. The processor of claim 5, wherein the instruction hardware is also to receive a second state management instruction to read the feature-enabled mask.

7. The processor of claim 6, wherein the second state management instruction is to have a leaf instruction to read a feature-in-use mask.

8. The processor of claim 2, wherein the state management logic is also, in response to the single restore instruction when the compacted-save bit is set, read the compaction mask from the compacted format in the second save area to determine which processor features to restore.

9. The processor of claim 8, wherein the state management logic is also, in response to the single restore instruction when the compacted-save bit is set, restore the context state only from the compacted format in the second save area for the features indicated by the compaction mask.

10. The processor of claim 9, wherein the state management logic is also, in response to the single restore instruction when the compacted-save bit is set, initialize the context state for features outside the subset.

11. A method comprising:
receiving, by a processor, a first save instruction;
saving, by the processor in response to the first save instruction, context state of features supported by the processor in an un-compacted format in a first save area having a constant size according to a predefined save area layout map having a plurality of fixed offsets, each corresponding to a particular processor feature of the processor features supported by the processor,
clearing a compacted-save bit in the first save area,
receiving, by the processor a second save instruction;
saving, by the processor in response to the second save instruction, a compaction mask in a second save area having a variable size according to the compaction mask to provide for a plurality of variable offsets per feature;
saving, by the processor in response to the second save instruction, the context state of a subset of processor features supported by the processor, in a compacted format in the second save area;
setting, by the processor in response to the second save instruction, a compacted-save bit in the second save area;
reading, in response to a single restore instruction specifying a save area, a compacted-save bit from the save area to determine whether the save area is an un-compacted save area saved in an un-compacted format or a compacted save area saved in a compacted format, and
in response to determination that the compacted-save bit is set, reading the compaction mask from the save area in order to determine which subset of processor features are to be restored and restoring the context state of each processor feature of the subset of processor features indicated by the compaction mask.

12. The method of claim 11, wherein the compaction mask is to indicate the subset of processor features, where the context state is to be saved only for the subset.

13. The method of claim 12, wherein the compacted format is to include the context state for the subset without gaps for features having unsaved context state.

14. The method of claim 13, further comprising combining the compaction mask with a feature-enabled mask to determine the subset.

15. The method of claim 14, further comprising receiving a first state management instruction to set the feature-enabled mask.

16. The method of claim 15, further comprising receiving a second state management instruction to read the feature-enabled mask.

17. The method of claim 16, further comprising, in response to the single restore instruction when the compacted-save bit is set:
reading the compaction mask from the compacted format in the second save area to determine which processor features to restore; and
restoring the context state only from the compacted format in the second save area for the features indicated by the compaction mask.

18. The method of claim 16, wherein the second state management instruction is to have a leaf instruction to read a feature-in-use mask, the method further comprising:
reading, in response to the leaf instruction, the feature-in-use mask; and
saving, in response to the second save instruction with a compaction mask based on the feature in-use-mask, only in-use features.

19. The method of claim 18, further comprising:
restoring, in response to the single restore instruction when the compacted-save bit is set, initializing the context state for features outside the subset.

20. A system comprising:
a memory; and
a processor including:
instruction hardware to receive a first save instruction and a second save instruction, and
state management logic to:

in response to the first save instruction, save context state of features supported by the processor in an un-compacted format in a first save area having a constant size according to a predefined save area layout map having a plurality of fixed offsets, each corresponding to a particular processor feature of the processor features supported by the processor, and clear a compacted-save bit in the first save area,
in response to the second save instruction, save a compaction mask and the context state of a subset of processor features supported by the processor in a compacted format in a second save area having a variable size according to the compaction mask to provide for a plurality of variable offsets per feature and set a compacted-save bit in the second save area, and
in response to a single restore instruction specifying a save area, read a compacted-save bit from the save area to determine whether the save area is an un-compacted save area saved in an un-compacted format or a compacted save area saved in a compacted format,
in response to determination that the compacted-save bit is set, read the compaction mask from the save area in order to determine which subset of processor features are to be restored and restore the context state of each processor feature of the subset of processor features indicated by the compaction mask.