# Patent

## Title
Multiplication operations in memory

## Abstract

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

## Background
PRIORITY INFORMATION
This application is a Non-Provisional of U.S. Provisional Application No. 62/045,259, filed Sep. 3, 2014, the contents of which are incorporated herein by reference.
TECHNICAL FIELD
The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to apparatuses and methods related to performing multiplication operations in memory.
BACKGROUND
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).
A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered.
In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array to execute instructions). Data can be moved from the memory array to registers external to the memory array via a bus.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.
FIG. 2A illustrates a schematic diagram of a portion of a memory array in accordance with a number of embodiments of the present disclosure.
FIG. 2B is a schematic diagram illustrating a portion of sensing circuitry in accordance with a number of embodiments of the present disclosure.
FIG. 3 illustrates a schematic diagram of a portion of a memory array in accordance with a number of embodiments of the present disclosure.
FIG. 4A illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure.
FIG. 4B illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure.
FIG. 4C illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure.
FIG. 4D illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure.
FIGS. 5A-5D illustrate timing diagrams associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure.
FIGS. 6A-6B illustrate timing diagrams associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure.
FIG. 7 is a schematic diagram illustrating sensing circuitry having selectable logical operation selection logic in accordance with a number of embodiments of the present disclosure.
FIG. 8 is a logic table illustrating selectable logic operation results implemented by a sensing circuitry in accordance with a number of embodiments of the present disclosure.



DETAILED DESCRIPTION
The present disclosure includes apparatuses and methods related to multiplication operations for memory. A multiplication operation can be performed on a first element and a second element. An element can be stored in a group of memory cells coupled to an access line and to a number of sense lines. For example, a first group of memory cells coupled to a first access line can store a first element. A second group of memory cells coupled to a second access line can store a second element. The multiplication operation can multiply the first element by the second element by performing a number of operations without transferring data via an input/output (I/O) line to determine a multiplication result.
As used herein, a first element and a second element can be numerical values that are multiplied by each other. That is, a first value (e.g., a first element, which can be referred to as an operand) can be multiplied by a second value (e.g., a second element) via a controller (e.g., a controller configured to control sensing circuitry). A multiplication operation can be used to determine a multiplication result from multiplying the first value by the second value.
In a number of examples, an element can represent an object and/or other construct, which may be represented by a bit-vector. As an example, a multiplication operation can be performed to multiply objects by multiplying the bit-vectors that represent the respective objects.
A number of embodiments of the present disclosure can provide a reduction of the number of computations and/or time involved in performing a number of multiplication operations (e.g., multiplication functions) relative to previous approaches. For instance, the number of computations and/or the time can be reduced due to an ability to perform various portions of the number of multiplication operations in parallel (e.g., simultaneously). Performing a number of multiplication operations as described herein can also reduce power consumption as compared to previous approaches. In accordance with a number of embodiments, a multiplication operation can be performed on elements (e.g., data in the form of bit-vectors stored in an array) without transferring data out of the memory array and/or sensing circuitry via a bus (e.g., data bus, address bus, control bus, etc.). A multiplication operation can involve performing a number of logical operations (e.g., AND operations, OR operations, SHIFT operations, INVERT operations, and Block_OR operations, etc.). However, embodiments are not limited to these examples.
In various previous approaches, elements (e.g., a first value and a second value) to be multiplied may be transferred from the array and sensing circuitry to a number of registers via a bus comprising input/output (I/O) lines. The number of registers can be used by a processing resource such as a processor, microprocessor, and/or compute engine, which may comprise ALU circuitry and/or other functional unit circuitry configured to perform the appropriate logical operations. However, often only a single multiplication function can be performed by the ALU circuitry, and transferring data to/from memory from/to registers via a bus can involve significant power consumption and time requirements. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry (e.g., ALU), which can involve performing a sense line address access (e.g., firing of a column decode signal) in order to transfer data from sense lines onto I/O lines, moving the data to the array periphery, and providing the data to a register in association with performing a multiplication operation, for instance.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “S,” “T,” “U,” “V,” “W,” etc., particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 204 may reference element “04” in FIG. 2, and a similar element may be referenced as 304 in FIG. 3. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense
FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 160 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 160, a memory array 130, and/or sensing circuitry 150 might also be separately considered an “apparatus.”
System 100 includes a host 110 coupled to memory device 160, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 160 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.
For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 160 may include a number of arrays 130 (e.g., a number of banks of DRAM cells). An example DRAM array is described in association with FIGS. 2 and 3.
The memory device 160 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144. Address signals are received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the sense lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the I/O bus 156. The write circuitry 148 is used to write data to the memory array 130.
Controller 140 decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 110. The controller 140 can be a state machine, a sequencer, or some other type of controller.
An example of the sensing circuitry 150 is described further below in association with FIGS. 2A and 2B. For instance, in a number of embodiments, the sensing circuitry 150 can comprise a number of sense amplifiers and a number of compute components, which may comprise latch serving as an accumulator and can be used to perform logical operations (e.g., on data associated with complementary sense lines). In a number of embodiments, the sensing circuitry (e.g., 150) can be used to perform multiplication operations using data stored in array 130 as inputs and store the results of the multiplication operations back to the array 130 without transferring via a sense line address access (e.g., without firing a column decode signal). As such, a multiplication function can be performed using sensing circuitry 150 rather than and/or in addition to being performed by processing resources external to the sensing circuitry 150 (e.g., by a processor associated with host 110 and/or other processing circuitry, such as ALU circuitry, located on device 160 (e.g., on controller 140 or elsewhere)).
In various previous approaches, data associated with a multiplication operation, for instance, would be read from memory via sensing circuitry and provided to an external ALU. The external ALU circuitry would perform the multiplication functions using the elements (which may be referred to as operands or inputs) and the result could be transferred back to the array via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry (e.g., 150) is configured to perform a multiplication operation on data stored in memory cells in memory array 130 and store the result back to the array 130 without enabling a local I/O line coupled to the sensing circuitry.
As such, in a number of embodiments, registers and/or an ALU external to array 130 and sensing circuitry 150 may not be needed to perform the multiplication function as the sensing circuitry 150 can be operated to perform the appropriate computations involved in performing the multiplication function using the address space of memory array 130. Additionally, the multiplication function can be performed without the use of an external processing resource.
FIG. 2A illustrates a schematic diagram of a portion of a memory array 230 in accordance with a number of embodiments of the present disclosure. A memory cell comprises a storage element (e.g., capacitor) and an access device (e.g., transistor). For instance, transistor 202-1 and capacitor 203-1 comprises a memory cell, and transistor 202-2 and capacitor 203-2 comprises a memory cell, etc. In this example, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells. In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read). The cells of the memory array 230 are arranged in rows coupled by word lines 204-X (Row X), 204-Y (Row Y), etc., and columns coupled by pairs of complementary data lines DIGIT(n−1)/DIGIT(n−1)_, DIGIT(n)/DIGIT(n)_, DIGIT(n+1)/DIGIT(n+1)_. The individual data lines corresponding to each pair of complementary data lines can also be referred to as data lines 205-1 (D) and 205-2 (D_) respectively. Although only three pair of complementary data lines are shown in FIG. 2A, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and/or data lines (e.g., 4,096, 8,192, 16,384, etc.).
Memory cells can be coupled to different data lines and/or word lines. For example, a first source/drain region of a transistor 202-1 can be coupled to data line 205-1 (D), a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and a gate of a transistor 202-1 can be coupled to word line 204-Y. A first source/drain region of a transistor 202-2 can be coupled to data line 205-2 (D_), a second source/drain region of transistor 202-2 can be coupled to capacitor 203-2, and a gate of a transistor 202-2 can be coupled to word line 204-X. The cell plate, as shown in FIG. 2A, can be coupled to each of capacitors 203-1 and 203-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.
The memory array 230 is coupled to sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry 250 comprises a sense amplifier 206 and a compute component 231 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines). The sense amplifier 206 can comprise a cross coupled latch, which can be referred to herein as a primary latch. The sense amplifier 206 can be configured, for example, as described with respect to FIG. 2B.
In the example illustrated in FIG. 2A, the circuitry corresponding to compute component 231 comprises a static latch 264 and an additional ten transistors that implement, among other things, a dynamic latch. The dynamic latch and/or static latch of the compute component 231 can be collectively referred to herein as a secondary latch, which can serve as an accumulator. As such, the compute component 231 can operate as and/or be referred to herein as an accumulator. The compute component 231 can be coupled to each of the data lines D 205-1 and D_ 205-2 as shown in FIG. 2A. However, embodiments are not limited to this example. The transistors of compute component 231 can all be re-channel transistors (e.g., NMOS transistors), for example.
In this example, data line D 205-1 can be coupled to a first source/drain region of transistors 216-1 and 239-1, as well as to a first source/drain region of load/pass transistor 218-1. Data line D_ 205-2 can be coupled to a first source/drain region of transistors 216-2 and 239-2, as well as to a first source/drain region of load/pass transistor 218-2.
The gates of load/pass transistor 218-1 and 218-2 can be commonly coupled to a LOAD control signal, or respectively coupled to a PASSD/PASSDB control signal, as discussed further below. A second source/drain region of load/pass transistor 218-1 can be directly coupled to the gates of transistors 216-1 and 239-2. A second source/drain region of load/pass transistor 218-2 can be directly coupled to the gates of transistors 216-2 and 239-1.
A second source/drain region of transistor 216-1 can be directly coupled to a first source/drain region of pull-down transistor 214-1. A second source/drain region of transistor 239-1 can be directly coupled to a first source/drain region of pull-down transistor 207-1. A second source/drain region of transistor 216-2 can be directly coupled to a first source/drain region of pull-down transistor 214-2. A second source/drain region of transistor 239-2 can be directly coupled to a first source/drain region of pull-down transistor 207-2. A second source/drain region of each of pull-down transistors 207-1, 207-2, 214-1, and 214-2 can be commonly coupled together to a reference voltage 291-1 (e.g., ground (GND)). A gate of pull-down transistor 207-1 can be coupled to an AND control signal line, a gate of pull-down transistor 214-1 can be coupled to an ANDinv control signal line 213-1, a gate of pull-down transistor 214-2 can be coupled to an ORinv control signal line 213-2, and a gate of pull-down transistor 207-2 can be coupled to an OR control signal line.
The gate of transistor 239-1 can be referred to as node S1, and the gate of transistor 239-2 can be referred to as node S2. The circuit shown in FIG. 2A stores accumulator data dynamically on nodes S1 and S2. Activating the LOAD control signal causes load/pass transistors 218-1 and 218-2 to conduct, and thereby load complementary data onto nodes S1 and S2. The LOAD control signal can be elevated to a voltage greater than VDD to pass a full VDD level to S1/S2. However, elevating the LOAD control signal to a voltage greater than VDD is optional, and functionality of the circuit shown in FIG. 2A is not contingent on the LOAD control signal being elevated to a voltage greater than VDD.
The configuration of compute component 231 shown in FIG. 2A has the benefit of balancing the sense amplifier for functionality when the pull-down transistors 207-1, 207-2, 214-1, and 214-2 are conducting before the sense amplifier 206 is fired (e.g., during pre-seeding of the sense amplifier 206). As used herein, firing the sense amplifier 206 refers to enabling the sense amplifier 206 to set the primary latch and subsequently disabling the sense amplifier 206 to retain the set primary latch. Performing logical operations after equilibration is disabled (in the sense amp), but before the sense amplifier fires, can save power usage because the latch of the sense amplifier does not have to be “flipped” using full rail voltages (e.g., VDD, GND).
Inverting transistors can pull-down a respective data line in performing certain logical operations. For example, transistor 216-1 (having a gate coupled to S2 of the dynamic latch) in series with transistor 214-1 (having a gate coupled to an ANDinv control signal line 213-1) can be operated to pull-down data line 205-1 (D), and transistor 216-2 (having a gate coupled to S1 of the dynamic latch) in series with transistor 214-2 (having a gate coupled to an ORinv control signal line 213-2) can be operated to pull-down data line 205-2 (D_).
The latch 264 can be controllably enabled by coupling to an active negative control signal line 212-1 (ACCUMB) and an active positive control signal line 212-2 (ACCUM) rather than be configured to be continuously enabled by coupling to ground and VDD. In various embodiments, load/pass transistors 208-1 and 208-2 can each having a gate coupled to one of a LOAD control signal or a PASSD/PASSDB control signal.
According to some embodiments, the gates of load/pass transistors 218-1 and 218-2 can be commonly coupled to a LOAD control signal. In the configuration where the gates of load/pass transistors 218-1 and 218-2 are commonly coupled to the LOAD control signal, transistors 218-1 and 218-2 can be load transistors. Activating the LOAD control signal causes the load transistors to conduct, and thereby load complementary data onto nodes S1 and S2. The LOAD control signal can be elevated to a voltage greater than VDD to pass a full VDD level to S1/S2. However, the LOAD control signal need not be elevated to a voltage greater than VDD is optional, and functionality of the circuit shown in FIG. 2A is not contingent on the LOAD control signal being elevated to a voltage greater than VDD.
According to some embodiments, the gate of load/pass transistor 218-1 can be coupled to a PASSD control signal, and the gate of load/pass transistor 218-2 can be coupled to a PASSDb control signal. In the configuration where the gates of transistors 218-1 and 218-2 are respectively coupled to one of the PASSD and PASSDb control signals, transistors 218-1 and 218-2 can be pass transistors. Pass transistors can be operated differently (e.g., at different times and/or under different voltage/current conditions) than load transistors. As such, the configuration of pass transistors can be different than the configuration of load transistors.
Load transistors are constructed to handle loading associated with coupling data lines to the local dynamic nodes S1 and S2, for example. Pass transistors are constructed to handle heavier loading associated with coupling data lines to an adjacent accumulator (e.g., through the shift circuitry 223, as shown in FIG. 2A). According to some embodiments, load/pass transistors 218-1 and 218-2 can be configured to accommodate the heavier loading corresponding to a pass transistor but be coupled and operated as a load transistor. Load/pass transistors 218-1 and 218-2 configured as pass transistors can also be utilized as load transistors. However, load/pass transistors 218-1 and 218-2 configured as load transistors may not be capable of being utilized as pass transistors.
In a number of embodiments, the compute component 231, including the latch 264, can comprise a number of transistors formed on pitch with the transistors of the corresponding memory cells of an array (e.g., array 230 shown in FIG. 2A) to which they are coupled, which may conform to a particular feature size (e.g., 4F2, 6F2, etc.). According to various embodiments, latch 1364 includes four transistors 208-1, 208-2, 1309-1, and 209-2 coupled to a pair of complementary data lines D 205-1 and D_ 205-2 through load/pass transistors 218-1 and 218-2. However, embodiments are not limited to this configuration. The latch 264 can be a cross coupled latch (e.g., gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) 209-1 and 209-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 208-1 and 208-2). As described further herein, the cross coupled latch 264 can be referred to as a static latch.
The voltages or currents on the respective data lines D and D— can be provided to the respective latch inputs 217-1 and 217-2 of the cross coupled latch 264 (e.g., the input of the secondary latch). In this example, the latch input 217-1 is coupled to a first source/drain region of transistors 208-1 and 209-1 as well as to the gates of transistors 208-2 and 209-2. Similarly, the latch input 217-2 can be coupled to a first source/drain region of transistors 208-2 and 209-2 as well as to the gates of transistors 208-1 and 209-1.
In this example, a second source/drain region of transistor 209-1 and 209-2 is commonly coupled to a negative control signal line 291-1 (e.g., ground (GND) or ACCUMB control signal similar to control signal RnIF shown in FIG. 2B with respect to the primary latch). A second source/drain region of transistors 208-1 and 208-2 is commonly coupled to a positive control signal line 212-2 (e.g., VDD or ACCUM control signal similar to control signal ACT shown in FIG. 2B with respect to the primary latch). The positive control signal 212-2 can provide a supply voltage (e.g., VDD) and the negative control signal 212-1 can be a reference voltage (e.g., ground) to enable the cross coupled latch 264. According to some embodiments, the second source/drain region of transistors 208-1 and 208-2 are commonly coupled directly to the supply voltage (e.g., VDD), and the second source/drain region of transistor 209-1 and 209-2 are commonly coupled directly to the reference voltage (e.g., ground) so as to continuously enable latch 264.
The enabled cross coupled latch 264 operates to amplify a differential voltage between latch input 217-1 (e.g., first common node) and latch input 217-2 (e.g., second common node) such that latch input 217-1 is driven to either the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground), and latch input 217-2 is driven to the other of the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground).
As shown in FIG. 2A, the sense amplifier 206 and the compute component 231 can be coupled to the array 230 via shift circuitry 223. In this example, the shift circuitry 223 comprises a pair of isolation devices (e.g., isolation transistors 221-1 and 221-2) coupled to data lines 205-1 (D) and 205-2 (D_), respectively). The isolation transistors 221-1 and 221-2 are coupled to a control signal 222 (NORM) that, when activated, enables (e.g., turns on) the isolation transistors 221-1 and 221-2 to couple the corresponding sense amplifier 206 and compute component 231 to a corresponding column of memory cells (e.g., to a corresponding pair of complementary data lines 205-1 (D) and 205-2 (D_), and compute component 231-6 corresponding to DIGIT(n−1) and DIGIT(n−1)_ illustrated on the left complementary pair of sense lines and compute component 231-6 corresponding to DIGIT (n+1) and DIGIT(n+1)_ illustrated on the right complementary pair of sense lines). According to various embodiments, conduction of isolation transistors 221-1 and 221-2 can be referred to as a “normal” configuration of the shift circuitry 223.
In the example illustrated in FIG. 2A, the shift circuitry 223 includes another (e.g., a second) pair of isolation devices (e.g., isolation transistors 221-3 and 221-4) coupled to a complementary control signal 219 (SHIFT), which can be activated, for example, when NORM is deactivated. The isolation transistors 221-3 and 221-4 can be operated (e.g., via control signal 219) such that a particular sense amplifier 206 and compute component 231 are coupled to a different pair of complementary data lines (e.g., a pair of complementary data lines different than the pair of complementary data lines to which isolation transistors 221-1 and 221-2 couple the particular sense amplifier 206 and compute component 231), or can couple a particular sense amplifier 206 and compute component 231 to another memory array (and isolate the particular sense amplifier 206 and compute component 231 from a first memory array). According to various embodiments, the shift circuitry 223 can be arranged as a portion of (e.g., within) the sense amplifier 206, for instance.
Although the shift circuitry 223 shown in FIG. 2A includes isolation transistors 221-1 and 221-2 used to couple particular sensing circuitry 250 (e.g., a particular sense amplifier 206 and corresponding compute component 231) to a particular pair of complementary data lines 205-1 (D) and 205-2 (D_) (e.g., DIGIT(n) and DIGIT(n)_) and isolation transistors 221-3 and 221-4 are arranged to couple the particular sensing circuitry 250 to an adjacent pair of complementary data lines in one particular direction (e.g., adjacent data lines DIGIT(n+1) and DIGIT(n+1)_ shown to the right in FIG. 2A), embodiments of the present disclosure are not so limited. For instance, shift circuitry can include isolation transistors 221-1 and 221-2 used to couple particular sensing circuitry to a particular pair of complementary data lines (e.g., DIGIT(n) and DIGIT(n)_ and isolation transistors 221-3 and 221-4 arranged so as to be used to couple the particular sensing circuitry to an adjacent pair of complementary data lines in another particular direction (e.g., adjacent data lines DIGIT(n−1) and DIGIT(n−1)_ shown to the left in FIG. 2A).
Embodiments of the present disclosure are not limited to the configuration of shift circuitry 223 shown in FIG. 2A. In a number of embodiments, shift circuitry 223 such as that shown in FIG. 2A can be operated (e.g., in conjunction with sense amplifiers 206 and compute components 231) in association with performing compute functions such as adding and subtracting functions without transferring data out of the sensing circuitry 250 via an I/O line (e.g., local I/O line (IO/IO_)), for instance.
Although not shown in FIG. 2A, each column of memory cells can be coupled to a column decode line that can be activated to transfer, via local I/O line, a data value from a corresponding sense amplifier 206 and/or compute component 231 to a control component external to the array such as an external processing resource (e.g., host processor and/or other functional unit circuitry). The column decode line can be coupled to a column decoder (e.g., column decoder). However, as described herein, in a number of embodiments, data need not be transferred via such I/O lines to perform logical operations in accordance with embodiments of the present disclosure. In a number of embodiments, shift circuitry 223 can be operated in conjunction with sense amplifiers 206 and compute components 231 to perform without transferring data to a control component external to the array, for instance.
FIG. 2B is a schematic diagram illustrating a portion of sensing circuitry in accordance with a number of embodiments of the present disclosure. According to various embodiments, sense amplifier 206 can comprise a cross coupled latch. However, embodiments of the sense amplifier 206 are not limited to a cross coupled latch. As an example, the sense amplifier 206 in FIG. 2B can be current-mode sense amplifier and/or single-ended sense amplifier (e.g., sense amplifier coupled to one data line). Also, embodiments of the present disclosure are not limited to a folded data line architecture.
In a number of embodiments, a sense amplifier (e.g., 206) can comprise a number of transistors formed on pitch with the transistors of the corresponding compute component 231 and/or the memory cells of an array (e.g., 230 shown in FIG. 2A) to which they are coupled, which may conform to a particular feature size (e.g., 4F2, 6F2, etc.). The sense amplifier 206 comprises a latch 215 including four transistors coupled to a pair of complementary data lines D 205-1 and D_ 205-2. The latch 215 can be a cross coupled latch (e.g., gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) 227-1 and 227-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 229-1 and 229-2). As described further herein, the latch 215 comprising transistors 227-1, 227-2, 229-1, and 229-2 can be referred to as a primary latch. However, embodiments are not limited to this example.
The voltages or currents on the respective data lines D and D— can be provided to the respective latch inputs 233-1 and 233-2 of the cross coupled latch 215 (e.g., the input of the secondary latch). In this example, the latch input 233-1 is coupled to a first source/drain region of transistors 227-1 and 229-1 as well as to the gates of transistors 227-2 and 229-2. Similarly, the latch input 233-2 can be coupled to a first source/drain region of transistors 227-2 and 229-2 as well as to the gates of transistors 227-1 and 229-1. The compute component 231, which may be referred to herein as an accumulator, can be coupled to latch inputs 233-1 and 233-2 of the cross coupled latch 215 as shown; however, embodiments are not limited to the example shown in FIG. 2B.
In this example, a second source/drain region of transistor 227-1 and 227-2 is commonly coupled to an active negative control signal 228 (RnIF). A second source/drain region of transistors 229-1 and 229-2 is commonly coupled to an active positive control signal 265 (ACT). The ACT signal 265 can be a supply voltage (e.g., VDD) and the RnIF signal can be a reference voltage (e.g., ground). Activating signals 228 and 265 enables the cross coupled latch 215.
The enabled cross coupled latch 215 operates to amplify a differential voltage between latch input 233-1 (e.g., first common node) and latch input 233-2 (e.g., second common node) such that latch input 233-1 is driven to one of the ACT signal voltage and the RnIF signal voltage (e.g., to one of VDD and ground), and latch input 233-2 is driven to the other of the ACT signal voltage and the RnIF signal voltage.
The sense amplifier 206 can also include circuitry configured to equilibrate the data lines D and D— (e.g., in association with preparing the sense amplifier for a sensing operation). In this example, the equilibration circuitry comprises a transistor 224 having a first source/drain region coupled to a first source/drain region of transistor 225-1 and data line D 205-1. A second source/drain region of transistor 224 can be coupled to a first source/drain region of transistor 225-2 and data line D_ 205-2. A gate of transistor 224 can be coupled to gates of transistors 225-1 and 225-2.
The second source drain regions of transistors 225-1 and 225-2 are coupled to an equilibration voltage 238 (e.g., VDD/2), which can be equal to VDD/2, where VDD is a supply voltage associated with the array. The gates of transistors 224, 225-1, and 225-2 can be coupled to control signal 225 (EQ). As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts data line D to data line D— such that the data lines D and D— are equilibrated to equilibration voltage VDD/2. According to a number of embodiments of the present disclosure, a number of logical operations can be performed using the sense amplifier 206 and compute component 231, and the result can be stored in the sense amplifier and/or compute component.
The sensing circuitry 250 can be operated in several modes to perform logical operations, including a second mode in which a result of the logical operation is initially stored in the sense amplifier 206, and a first mode in which a result of the logical operation is initially stored in the compute component 231. Operation of the sensing circuitry 250 in the second mode is described below with respect to FIGS. 6A and 6B, and operation of the sensing circuitry 250 in the second mode is described below with respect to FIGS. 5A-5D. Additionally with respect to the first operating mode, sensing circuitry 250 can be operated in both pre-sensing (e.g., sense amps fired before logical operation control signal active) and post-sensing (e.g., sense amps fired after logical operation control signal active) modes with a result of a logical operation being initially stored in the sense amplifier 206.
As described further below, the sense amplifier 206 can, in conjunction with the compute component 231, be operated to perform various logical operations using data from an array as input. In a number of embodiments, the result of a logical operation can be stored back to the array without transferring the data via a data line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across I/O lines in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased parallel processing capability as compared to previous approaches.
FIG. 3 illustrates a schematic diagram of a portion of a memory array 301 in accordance with a number of embodiments of the present disclosure. The array 301 includes memory cells (referred to generally as memory cells 303, and more specifically as 303-0 to 303-J) coupled to rows of access lines 304-0, 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, . . . , 304-R and columns of sense lines 305-0, 305-1, 305-2, 305-3, 305-4, 305-5, 305-6, 305-7, . . . , 305-S. Memory array 301 is not limited to a particular number of access lines and/or sense lines, and use of the terms “rows” and “columns” does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not pictured, each column of memory cells can be associated with a corresponding pair of complementary sense lines (e.g., complementary sense lines 205-1 and 205-2 in FIG. 2A).
Each column of memory cells can be coupled to sensing circuitry (e.g., sensing circuitry 150 shown in FIG. 1). In this example, the sensing circuitry comprises a number of sense amplifiers 306-0, 306-1, 306-2, 306-3, 306-4, 306-5, 306-6, 306-7, . . . , 306-U coupled to the respective sense lines 305-0, 305-1, 305-2, 305-3, 305-4, 305-5, 305-6, 305-7, . . . , 305-S. The sense amplifiers 306 are coupled to input/output (I/O) line 334 (e.g., a local I/O line) via access devices (e.g., transistors) 308-0, 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, . . . , 308-V. In this example, the sensing circuitry also comprises a number of compute components 331-0, 331-1, 331-2, 331-3, 331-4, 331-5, 331-6, 331-7, . . . , 331-X coupled to the respective sense lines. Column decode lines 310-1 to 310-W are coupled to the gates of transistors 308-1 to 308-V, respectively, and can be selectively activated to transfer data sensed by respective sense amps 306-0 to 306-U and/or stored in respective compute components 331-0 to 331-X to a secondary sense amplifier 312. In a number of embodiments, the compute components 331 can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers 306.
In a number of embodiments, the sensing circuitry (e.g., compute components 331 and sense amplifiers 306) is configured to perform a multiplication operation on elements stored in array 301. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., 304-0) and to a number of sense lines (e.g., 305-0 to 305-S), and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., 304-1) and the respective number of sense lines (305-0 to 305-S). Each element of the first plurality of elements can be multiplied by a respective one of the second plurality of elements, and the result of the multiplication operation can be stored (e.g., as a bit-vector(s)) in a third group of memory cells coupled to a particular access line (e.g., 304-0 to 304-R) and to the number of sense lines (e.g., 305-0 to 305-S). The third group of memory cells can, for example, be coupled to an access line 304-R or to at least one of access lines 304-0 to 304-R. That is, the third group of memory cells can be a same group of memory cells as the first group of memory cells or the second group of memory cells (e.g., a result of a multiplication operation can be written over a currently stored element).
An example multiplication operation is described below in association with FIGS. 4A-4D, which illustrate tables showing the states of memory cells of an array (e.g., 301) at a number of particular phases associated with performing a multiplication operation in accordance with a number of embodiments described herein. The reference numbers of the rows of the tables shown in FIGS. 4A-4D correspond to respective reference numbers of the pseudocode described below. Each row of the tables indicates the values of a number of bit vectors 431 (Comp_Comp), 433 (Dynamic Mask), 435 (Static Mask), 437 (Carry), 439 (Intermediate), 441 (Intermediate 2), 443 (Srca), 445 (srcb), and 447 (Dest) at a particular phase of the multiplication operation.
The example shown in FIGS. 4A-4D is associated with multiplying a first four elements stored in memory cells coupled to access line 304-0 and to sense lines 305-0 to 305-31 by a respective second four elements stored in memory cells coupled to access line 304-1 and to sense lines 305-1 to 305-31. In the example below, the first four elements are represented by a first 32 bit wide bit-vector srca 443 (e.g., [00000111 00000100 00001000 00001100], which can be represented in hexadecimal notation as [07 04 08 c] and is shown in FIGS. 4A-4D as “0x0704080c”), with each element of the first four elements being represented by an 8 bit wide bit-vector, and the second four elements are represented by a second 32 bit wide bit-vector srcb 445 (e.g., [00000011 00000101 00000010 00000011], which can be represented in hexadecimal notation as [03 05 02 03] and is shown as “srcb” in FIGS. 4A-4D as “0x03050203”), with each element of the second four elements also being represented by an 8 bit wide bit vector. It is noted that although hexadecimal notation is used in FIGS. 4A-4D, the bit-vectors are stored as binary data patterns in the array during the multiplication operation. Also, in the examples described herein, commas and/or spaces may be used to separate elements within a bit-vector. For instance, in the example above, each 32 bit wide bit-vector comprises four elements which are separated by spaces. Embodiments are not limited to a particular element size (e.g., to a particular number of elements and/or bits per element). The result of the multiplication operation can be stored in array 301 and/or can be transferred external to the array 301 (e.g., to functional unit circuitry of a host).
As described further below, the bit vectors 433 (Dynamic Mask), 435 (Static Mask), 437 (Carry), 439 (Intermediate), 441 (Intermediate 2), and 447 (Dest) can be used in association with multiplying the first elements (e.g., the elements of the srca bit-vector 443) by the respective second elements (e.g., the elements of the srcb bit-vector 445). The bit-vectors 433, 435, 437, 439, 441, and 447 can be stored in respective groups of memory cells coupled to particular access lines, which may be referred to as temporary storage rows (e.g., rows storing data that may be updated during various phases of a multiplication operation). As an example, the bit-vectors 433, 435, 437, 439, 441, and 447 can have a same width as the srca and srcb bit-vectors 443 and 445, respectively, and can be stored in cells coupled the same sense lines as the srca and srcb bit-vectors (e.g., sense lines 305-0 to 305-31). For instance, the bit-vector 433 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-2 and to sense lines 305-0 to 305-31, the bit-vector 435 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-3 and to sense lines 305-0 to 305-31, the bit-vector 437 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-4 and to sense lines 305-0 to 305-31, the bit-vector 439 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-5 and to sense lines 305-0 to 305-31, the bit-vector 441 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-6 and to sense lines 305-0 to 305-31, and the bit-vector 447 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-R and to sense lines 305-0 to 305-31. The bit-vector 431 (Comp_Comp) represents the data stored in the sensing circuitry (e.g., compute components (e.g., 331) and/or sense amplifiers 306) corresponding to the sense lines having cells coupled thereto which store elements being multiplied (e.g., sense lines 305-0 to 305-31 in this example).
As an example, the first element of the srca bit-vector 443 (e.g., hexadecimal value “07”) can be stored (e.g., as an 8 bit wide bit-vector [00000111]) in memory cells 303-0 to 303-7, and the first element of the srcb bit-vector 445 (e.g., hexadecimal value “03”) can be stored (e.g., as an 8 bit wide bit-vector [00000011]) in memory cells coupled to access line 304-1 (e.g., ROW 1) and to sense lines 305-0 to 305-7. As an example, the most significant bits (MSBs) of the respective bit-vectors (e.g., [00000111] and [00000011]) can be stored in cells coupled to sense line 305-0, the next MSBs of the respective bit-vectors can be stored in cells coupled to sense line 305-1, . . . , and the least significant bits (LSBs) of the respective bit-vectors can be stored in cells coupled to sense line 305-8. As used herein, the left most bit of a bit-vector is considered the MSB; however, embodiments are not so limited.
In a number of examples, a multiplication operation includes performing a number of AND operations, OR operations, SHIFT operations, INVERT operations, and BlockOR operations. The multiplication operation includes performing the AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line to multiply a first element by a second element. The number of AND operations, OR operations, INVERT operations, and SHIFT operations can be performed using sensing circuitry on pitch with each of a number of columns of complementary sense lines.
The below pseudocode represents instructions executable to perform a number of multiplication operations in a memory in accordance with a number of embodiments of the present disclosure. The example pseudocode is referenced using reference numbers 1-8, which correspond to the reference numbers of the rows shown in the tables of FIGS. 4A-4D. For instance, reference number 1 (e.g., “Load srca, srcb”) corresponds to row 451-1, reference number 3 (e.g., “Obtain all Temp Rows”) corresponds to row 451-3, and reference number 8.a (e.g., “Load srcb in Comp_Comp”) corresponds to rows 451-8.a, 453-8.a, and 455-8.a shown in FIGS. 4A-4D.

    
    
        1. Load srca, srcb
        2. Determine element count in sub array for the vector width
        3. Obtain all Temp Rows
        4. Determine MSB and store in Comp_Comp, Row_Dynamic_Mask
        5. Determine MSB by shifting right with fixed vector for each length into Comp_Comp
        6. Invert Comp_Comp and store in Row_Static_Mask
        7. Find Vectors of LSBs
        
            7.a Find LSB and store in Comp_Comp, Row_Intermediate
            7.b Load Row_Dynamic_Mask in Comp_Comp and LEFT Shift 1
            7.c Perform OR operation with Row_Intermediate and store in Row_Dynamic Mask
            7.d Clear Row_Intermediate
        
        
        8. For Given Vector Fixed Width:
        
            8.a. Load src b in Comp_Comp
            8.b Do Comp_Comp AND operation with Row_Dynamic_Mask
            8.c. Store Comp_Comp in Row_Intermediate 2
            8.d. Duplicate bits for each vector by left shifting and OR with Row_Intermediate
            8.e. Load srca in Comp_Comp
            8.f. Do Comp_Comp left shift for current iteration
            8.g. Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2
            8.h. Halfadd Row_Intermediate and Row_Intermediate 2 output Dest and Row_Carry
            8.i. Load Row_Carry in Comp_Comp
            8.j. Do Comp_Comp AND operation with Row_Static_Mask
            8.k. Shift Comp_Comp Left
            8.l. For any true bits in Comp_Comp BLOCKOR
            
                8.l.i. Store Comp_Comp in Row_Carry
                8.l.ii. Halfadd Dest and Row_Carry, output Dest and Row_Carry
                8.l.iii. Load Row_Carry in Comp_Comp
                8.l.iv. Do Comp_Comp AND operation with Row_Static_Mask
                8.l.v. Shift Comp_Comp Left
            
            
            8.m. Load Dest in Comp_Comp
            8.n. Store Comp_Comp in Row_Intermediate
            8.o. Load Row_Dynamic_Mask in Comp_Comp
            8.p. Shift Comp_Comp Left
            8.q. Store Comp_Comp in Row_Dynamic_Mask
        
        
    
    


For purposes of discussion, the above pseudocode will be divided into a setup phase and a multiplication phase associated with performing a multiplication operation (e.g., multiplying the four elements of the srca bit-vector 443 by the corresponding four elements of the srcb bit-vector 445). The pseudocode referenced by reference numbers 1-7 can correspond to the setup phase. The setup phase can be performed simultaneously for a number of the multiplication operations. In this example, bit-vectors can be illustrated in bold to indicate a change in the bit-vector stored in a particular location (e.g., the bit-vector stored in Comp_Comp 431 can change from [0x0] to [0x80000000] from reference 451-3 to reference 451-4 and would be bolded to indicate the change). FIG. 4A illustrates the values of a number of bit-vectors associated with performing the setup phase of a multiplication operation. The pseudocode referenced by reference number 8 (e.g., 8.a-8.q) can correspond to the multiplication phase.
In a number of embodiments, the setup phase can be performed simultaneously for all of the elements that will be multiplied. The results (e.g., the resulting stored bit-vectors) corresponding to a number of operations performed in the setup phase are shown in FIG. 4A. Rows 451-1 to 451-7 of the table in FIG. 4A correspond to the above pseudocode instructions referenced by reference numbers 1 to 7, respectively. As such, rows 451-1 to 451-7 indicate values of the bit vectors 431, 433, 435, 437, 441, 443, 445, and 447 during execution of the setup phase as described by the above pseudocode. Reference number 1 (e.g., “Load srca, srcb”) of the above pseudocode is associated with storing a first bit-vector (e.g., srca bit-vector 443) and a second bit-vector (e.g., srcb bit-vector 445) into an array (e.g., array 301 in FIG. 3). In this example, the srca bit-vector 443 and the srcb bit-vector 445 are each 32 bit wide bit-vectors representing four 8 bit wide elements. In this example, the srca bit-vector 443 corresponds to bit-vector [00000111 00000100 00001000 00001100] (e.g., [07 04 08 0c] in hexadecimal form), and the srcb bit-vector 445 corresponds to bit-vector [00000011 00000101 00000010 00000011] (e.g., [03 05 02 03] in hexadecimal form). As an example, the srca bit-vector 443 can be stored in a first group of memory cells coupled to a particular access line (e.g., 304-0 (ROW 0) in FIG. 3) and to a particular number of sense lines (e.g., 305-0 to 305-31) and the srcb bit-vector 445 can be stored in a group of memory cells coupled to access line 304-1 (e.g., ROW 1 in FIG. 3) and to the particular number of sense lines (e.g., 305-0 to 305-31).
Row 451-1 of the table shown in FIG. 4A illustrates the values of the srca and srcb bit-vectors 443 and 445 upon being stored (e.g., loaded) in the array (e.g., 301). As noted above, although the values of the bit-vectors are shown in FIGS. 4A to 4D in hexadecimal form for convenience, designated by the leading “0x” (e.g., the value of bit-vector 443 is shown as 0x0704080c), the bit-vectors can be stored as binary data patterns in the array. The multiplication operation associated with execution of the above pseudocode includes multiplying the first element (e.g., binary [00000111]/hexadecimal [0x07]) of the srca bit-vector 443 by the first element (e.g., binary [00000011]/hexadecimal [0x03]) of the srcb bit-vector 445, the second element (e.g., binary [00000100]/hexadecimal [0x04]) of the srca bit-vector 443 by the second element (e.g., binary [00000101]/hexadecimal [0x05]) of the srcb bit-vector 445, the third element (e.g., binary [00001000]/hexadecimal [0x08]) of the srca bit-vector 442 by the third element (e.g., binary [00000010]/hexadecimal [0x02] of the srcb bit-vector 445, and the fourth element (e.g., binary [00001100]/hexadecimal [0x0c] of the srca bit-vector 443 by the fourth element (e.g., binary [00000011]/hexadecimal[0x03]) of the srcb bit-vector 445. That is, the ith element of the srca bit-vector 443 is multiplied by the ith element of the srcb bit-vector 445. Row 451-1 shown in FIG. 4A also indicates that the memory cells used to store the results of the multiplication operation (e.g., Dest bit-vector 447) are “cleared” (e.g., a logic “0” is stored in each of the cells) during the setup phase. As shown in FIG. 4A, the bit-vector 447 has a value of 0x0. As noted above, the Dest bit-vector 447 can be stored in a group of memory cells coupled to access line 304-R and to sense lines 305-0 to 305-31. Reference number 2 (e.g., “Determine element count in sub array for the vector width”) of the above pseudocode is associated with determining the element count of the srca bit-vector 443 and the srcb bit-vector 445. Determining the quantity of elements in the srca bit-vector 443 and the srcb bit-vector 445 can include determining the quantity of element pairs to be multiplied. A width of each bit-vector representing an element in the srca bit-vector 443 and the srcb bit-vector 445 and a total width of the srca and srcb bit-vectors 443 and 445 can be used to determine the element count. For example, given that there are 32 bits in a bit-vector representing srca and srcb and that each element is represented by an 8 bit wide bit-vector, each bit-vector 443 and 445 comprises 4 elements (e.g., 32/8=4). In a number of examples, the element count of the srca and/or srcb bit-vectors, the vector width of the srca and srcb bit-vectors, and/or the vector width of each element can be provided by a user as a parameter, for instance. As such, in a number of examples, the element width of the bit-vectors comprising srca 443 and/or srcb 445 can be determined based on the vector width of srca 443 and srcb 445 and on the element count. For instance, given a vector width of 32 bits and an element count of 4, the element width would be 8 bits (e.g., 32/4=8). It is noted that in this example, the pseudocode corresponding to reference number 2 does not result in changes to the bit-vectors 443, 445, and/or 447. As such, the vector values shown in row 451-2 of FIG. 4A are unchanged as compared to their values shown in row 451-1.
Reference number 3 (e.g., “Obtain all Temp Rows”) of the above pseudocode is associated with initializing a number of groups of memory cells for use as temporary storage rows. That is, the number of groups of memory cells can be groups of cells coupled to respective access lines (e.g., rows) and can be used to store data (e.g., on a temporary basis) in association with performing the multiplication operation. For example, a first group of memory cells can be coupled to a particular access line (e.g., 304-2, illustrated as ROW 2) and can store a bit-vector referred to as a “Row_Dynamic_Mask” bit-vector 433. A second group of memory cells can be coupled to another access line (e.g., 304-3, illustrated as ROW 3) and can store a bit-vector referred to as a “Row_Static_Mask” bit-vector 435. A third group of memory cells can be coupled to another access line (e.g., 304-4, illustrated as ROW 4) and can store a bit-vector referred to as a “Row_Carry” bit-vector 437. A fourth group of memory cells can be coupled to another access line (e.g., 304-5, illustrated as ROW 5) and can store a bit-vector referred to as a “Row_Intermediate” bit-vector 439. A fifth group of memory cells can be coupled to another access line (e.g., 304-6, illustrated as ROW 6) and can store a bit-vector referred to as a “Row_Intermediate2” bit-vector 441. In a number of embodiments, the “Dest” bit-vector 447 can be stored in a group of memory cells coupled to another access line (e.g., 304-R, illustrated as ROW N), which can be considered a temporary storage row. Embodiments are not limited to a particular number of temporary storage rows and/or to storage of the corresponding bit-vectors on particular access lines. Also, although the groups of memory cells used to store bit-vectors 433, 435, 437, 439, 441, and 447 may be referred to as “rows,” the respective groups of memory cells may comprise fewer than all of the cells coupled to a particular access line. In a number of examples, the bit-vectors 433, 435, 437, 439, 441, and 447 stored in memory cells corresponding to the temporary storage rows are stored in memory cells coupled to the same sense lines as the element pairs that are being multiplied.
The Row_Dynamic_Mask bit-vector 433 can be used, for instance, to indicate a particular bit position (e.g., a LSB) within elements being multiplied. The particular bit position indicated by the Row_Dynamic_Mask 433 can be used to determine a contribution of the bit at the particular bit position within the element being multiplied (e.g., the contribution being based on whether the bit is a “1” or “0”). The Row_Static_Mask 433 can be used to provide a mask to perform the multiplication operation. As described further below, the Row_Carry bit-vector 437 can be used to store a carry value from a contribution of a bit at a particular bit position within an element in order to apply the carry value to a next-most-significant bit position, for instance. A carry value can include a value of a bit at a particular bit position within an element (e.g., a “1” at an LSB position such as in bit-vector [00000001]) that carries a value of a bit to an additional bit position (e.g., a position of the 1 in bit-vector [00000010]. When a data value of a bit-vector (e.g., bit-vector [00000001] is added to a data value of another bit-vector (e.g., bit-vector [00000001], the two 1s in the LSB position can provide a carry value of 1 when added together (e.g., bit-vector [00000001] added to bit-vector [00000001] results in a bit-vector of [00000011]). The Row_Intermediate bit-vector 439 and the Row_Intermediate2 bit-vector 441 can be used to store temporary data values while performing the multiplication operation. The Dest bit-vector 447 can be used to store a result of an iteration of operations during performance of the multiplication operation and a result of the multiplication operation once the iterations of operations are complete. Row 451-3 of FIG. 4A shows each of the initialized bit-vectors 433, 435, 437, 439, 441, and 447 having a value of 0x0 (e.g., corresponding to bit-vector [00000000] in hexadecimal format).
Reference number 4 (e.g., “Determine MSB and store in Comp_Comp, Row_Dynamic_Mask”) of the above pseudocode is associated with determining the MSB of the srca 443 and/or srcb 445 bit-vectors and storing, as a bit-vector, a bit pattern indicating the MSB of the bit-vectors 443 and/or 445 in particular groups of memory cells. As an example, the bit pattern indicating the MSB of the bit-vectors 443 and/or 445 can be stored (e.g., as a bit-vector) in the group of memory cells used to store the Row_Dynamic_Mask bit-vector 433 and can be stored in the group of compute components (e.g., 331-0 to 331-31) as Comp_Comp bit-vector 431. In a number of embodiments, the bit pattern indicating the MSB of the srca and srcb bit-vectors comprises a “1” bit in the MSB position and a “0” bit in the remaining bit positions. For instance, as shown in row 451-4 of the table of FIG. 4A, the Comp_Comp bit-vector 431 and the Row_Dynamic_Mask bit-vector 433 each comprise bit-vector [0x80000000] (in hexadecimal form), which corresponds to a 32-bit wide bit-vector in which the MSB is a “1” and the remaining 31 bits are “0s”. For example, the compute component 331-0 can latch a “1” and the compute components 331-1 to 331-31 can each latch a “0”.
The pseudocode referenced at reference number 5 (e.g., “Determine MSB by shifting right with fixed vector for each length into Comp_Comp”) is associated with determining a bit-vector that can indicate a MSB position corresponding to each of the respective elements represented by srca 443 and srcb 445. The bit-vector used to indicate the MSBs corresponding to the number of elements can be determined by performing a number of logical operations (e.g., a number of iterations of SHIFT operations and OR operations) on the bit-vector 431 stored in the compute components (e.g., 331-0 to 331-31 in FIG. 3) and the Row_Dynamic_Mask bit-vector 433 (e.g., whose corresponding bits can be stored in cells coupled to a particular temporary storage row and to respective sense lines 305-0 to 305-31). The SHIFT and OR iterations can result in a binary bit-vector [10000000 10000000 10000000 10000000] (e.g., the hexadecimal bit-vector [0x80808080]) that comprises a “1” at the bit positions corresponding to the MSBs for each of the four elements represented by srca 443 and/or srcb 445. The SHIFT operations can be right SHIFT operations; however, embodiments are not limited to this example. The SHIFT operations can be performed on Comp_Comp 431. The OR operations can be performed on Row_Dynamic_Mask 433 and Comp_Comp 431.
For example, a SHIFT operation can be performed on the bit-vector [10000000 00000000 00000000 00000000 (e.g., [0x80000000]) stored in the Comp_Comp 431 at reference number 451-4. The SHIFT operation can include shifting the “1” bit over eight compute components to result in the bit-vector [00000000 100000000 00000000 00000000] (e.g., [0x00800000]). The resulting bit-vector [0x00800000] stored in the Comp_Comp 431 after shifting can be ORed with the Row_Dynamic_Mask bit-vector 433 [0x80000000], resulting in a bit-vector [0x80800000]. The bit-vector [0x80800000] can be stored as the Row_Dynamic_Mask 433 bit-vector (replacing the previous bit-vector). An additional SHIFT operation can include shifting the bit-vector [0x80800000] stored in Comp_Comp 431 eight compute components to the right, resulting in bit-vector—0x00808000]. The bit-vector [0x00808000] can be ORed with the bit-vector [0x80800000] stored as the Row_Dynamic_Mask 433, resulting in bit-vector—0x80808000]. A final SHIFT and OR operation (including eight shifts to the right and an OR operation) can result in the bit-vector [0x80808080] stored as the Row_Dynamic_Mask 433. The results of the SHIFT operations and the OR operations can be stored in the group of memory cells used to store Row_Dynamic_Mask 433 and the compute components (e.g., 331-0 to 331-31 in FIG. 3).
At reference 451-6 (e.g., “Invert Comp_Comp and store in Row_Static_Mask), an invert operation can be performed on the bit-vector stored in the Comp_Comp 431 (e.g., bit-vector [0x80808080] stored in compute components 331-0 to 331-31). The resulting bit-vector (e.g., referred to as the “Row_Static_Mask bit-vector” 435) of the invert operation (e.g., bit-vector [0x7f7f7f7f]) can be stored in a group of memory cells as the Row_Static_Mask bit-vector 435.
The pseudocode referenced at reference number 7 (e.g., “Find Vectors of LSBs”) includes finding LSBs for the vectors. At reference 451-7a (e.g., “Find LSB and store in Comp_Comp, Row_Intermediate), an LSB of the bit-vector (e.g., [0x00000001]) is determined by setting all of the Comp_Comp 431 to “1”s (e.g., compute components store bit-vector [0xffffffff]). A LEFT shift is performed on the Comp_Compe 431 so that the Comp_Comp 431 stores bit-vector [0xfffffffe]. An inverse operation is performed on the bits stored in the Comp_Comp 431, resulting in a bit-vector [0x00000001] that indicates an LSB of the bit-vector. The resulting bit-vector [0x00000001] is stored as the Row_Intermediate bit-vector 439.
At reference 451-7b (e.g., “Load Row_Dynamic_Mask in Comp_Comp and LEFT Shift 1”), the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x80808080]) is shifted in the Comp_Comp 431 left one position, resulting in bit-vector [0x01010100], as shown at reference 451-7b. At reference 451-7c (e.g., “Perform OR operation with Row_Intermediate and store in Row_Dynamic Mask”), the bit-vector [0x01010100] stored in Comp_Comp 431 is ORed with the Row_Intermediate bit-vector 439 (e.g., bit-vector [0x00000001]). The resulting bit-vector of the OR operation (e.g., bit-vector [0x01010101]) is stored as the Row_Dynamic_Mask bit-vector 433. At reference 7.d (e.g., “Clear Row_Intermediate”), the Row_Intermediate bit-vector 439 is cleared, resulting in a Row_Intermediate bit-vector 439 of [0x00000000] (indicated by [0x0]).
A multiplication phase begins at reference 8.a and concludes at reference 8.q. The multiplication phase can further be divided into a number of iterations of operations. For example, at reference 8 (e.g., “For Given Vector Fixed Width:”), an operation can include a number of iterations of operations. For instance, reference 8 refers to a “For” loop that iterates through a number of logical operations for multiplying each bit-vector's elements by corresponding elements of another bit-vector. Each iteration of the number of iterations can begin at reference 8.a and can conclude at reference 8.q. An iteration of operations can be executed to determine a data value contribution corresponding to a particular bit position of elements being multiplied. For example, a first element (e.g., [0000 0111]) and a second element (e.g., [0000 0011]) that have a bit-vector width of eight can contribute to a multiplication operation. During a first iteration of operations, a data value contribution of the first element and the second element can be determined for the least-significant-bit (LSB) position of the first element (e.g., the bit in bold of bit-vector [0000 0111]) and the second element (e.g., the bit in bold of bit-vector [0000 0011]). During a second iteration of operations, a data value contribution of the first element and the second element can be determined for the next LSB position for the first element (e.g., [0000 0111]) and the second element (e.g., [0000 0011]). The number of iterations of operations can be based on a bit-vector length of an element being multiplied. For example, in this instance, the number of iterations can be associated with an element-length of eight. At the completion of reference 8.q, temporary rows can be released at the completion of the multiplication operation. In a number of examples, the results of the multiplication operation can be stored in the array 301. In a number of examples, each iteration of the “For” loop that begins at reference 8.a can be performed sequentially. FIGS. 4B through 4D are each examples of an iteration of operations (e.g., FIG. 4B is a first iteration, FIG. 4C is a second iteration, and FIG. 4D is a third iteration) and the results of logical operations performed in the multiplication phase.
FIG. 4B illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure. FIG. 4B illustrates the values of the number of bit-vectors 431, 433, 435, 437, 439, 441, 443, 445, and 447 during the multiplication phase of a multiplication operation (e.g., the multiplication phase corresponding to the pseudocode referenced above by reference number 8). The pseudocode referenced at reference number 8 (e.g., “For Given Vector Fixed Width”) corresponds to a “For” loop described via the pseudocode referenced by reference numbers 8.a to 8.q. As such, the “For” loop corresponding to reference number 8 involves performing a number of iterations of operations (e.g., loops). As an example, the number of iterations of the operations can correspond to the fixed width of the bit-vectors representing the elements of the srca and srcb bit-vectors 443 and 445. For instance, since in this example, each of the four elements represented by srca 443 and srcb 445 comprises an 8 bit wide bit-vector, the number of iterations (e.g., the number of times the “For” loop corresponding to reference number 8 is performed in association with multiplying the four elements of srca 443 by the corresponding four elements of srcb 445) is eight (8).
At reference 8.a. (e.g., “Load srcb in Comp_Comp”) of the above pseudocode, the srcb bit-vector 445 (e.g., bit-vector [0x03050203]) can be loaded into the appropriate compute components (e.g., compute components 331-0 to 331-31 in this example) For example, the 8 bits corresponding to the first element (e.g., [0x03] or binary [00000011]) can be loaded into compute components 331-0 to 331-7 (e.g., with the MSB being loaded into compute component 331-0 and each subsequent next-most-significant bit being loaded into the subsequent corresponding compute components 331-1 to 331-7 such that a “0” is stored in compute components 331-0 to 331-5 and a “1” is stored in compute components 331-6 and 331-7). Subsequent elements (e.g., the second ([0x05], third ([0x02]), and fourth ([0x03]) element) of the srcb bit-vector 445 can be loaded into subsequent corresponding compute components 331-8 to 331-31. As such, row 451-8.a of the table shown in FIG. 4B illustrates the bit vector 431 having a value of [0x03050203].
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector 431 (e.g., bit-vector [0x03050203]) shown in row 451-8.a (e.g., previously latched in the compute components 331-0 to 331-31) and the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x01010101], which can be stored in memory cells coupled to the access line 304-2 and to sense lines 331-0 to 331-31). As used herein, performing a logical operation on a first and second bit-vector can include performing, in parallel, the logical operation on each of the respective bits at particular bit positions of the bit-vectors in parallel. As an example, the result of a logical AND operation performed on a first bit-vector “a” and a second bit-vector “b” is a bit-vector whose MSB is the result of “ANDing” the MSB of bit-vector “a” and the MSB of bit-vector “b,” whose next MSB is the result of ANDing the next MSBs of bit-vectors “a” and “b, and whose LSB is the result of ANDing the LSB of bit-vector “a” and the LSB of bit-vector “b.” For instance, performing an AND operation on a bit-vector [1110] and on bit-vector [1000] would result in bit-vector (e.g., the MSB of the resultant bit-vector is “1” since “1” AND “1” is “1”, the next MSB is “0” since “1” AND “0” is “0”, the next MSB is “0” since “1” AND “0” is “0”, and the LSB is “0” since “0” AND “0” is “0”).
Since the value of the srcb bit-vector 445 was loaded into the compute components 331-0 to 331-31, the result of “ANDing” the bit-vector 431 with the bit-vector 433 is analogous to the result of performing an AND operation on the srcb bit-vector 445 and the Row_Dynamic_Mask bit-vector 433. As such, bit-vector [00000011 00000101 00000010 00000011] (e.g., [0x03050203]) is “ANDed” with bit-vector [00000001 00000001 00000001 00000001] (e.g., [0x01010101]), which results in bit-vector [00000001 00000001 00000000 00000001] (e.g., [0x01010001]). In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., 331-0 to 331-31) as bit-vector 431. For instance, row 451-8.b illustrates the Comp_Comp bit-vector 431 as being [0x01010001].
At reference 8.c (e.g., “Store Comp_Comp in Row_Intermediate 2”), the result of the AND operation performed at reference 8.b (e.g., bit-vector [0x01010001]) is stored in (e.g., written to) the memory cells storing the Row_Intermediate_2 bit-vector 441. As an example, the Row_Intermediate_2 bit-vector 441 can be stored in cells coupled to access line 304-6 and to sense lines 305-0 to 305-31. Row 451-8.c of the table shown in FIG. 4B illustrates the Row_Intermediate_2 bit-vector 441 having a value of [0x01010001].
At reference 8.d (e.g., “Duplicate bits for each vector by left shifting and OR with Row_Intermediate 2), bits of the Intermediate 2 bit-vector 441 (e.g., [0x01010001]) are duplicated. Duplicating bits refers to filling an element with a particular bit that is in a least-significant bit position. For example, a bit (e.g., “1”) of bit-vector [0000 0001] can be duplicated by adding the “1” bit in the least significant bit position to each position of the element, resulting in bit-vector [1111 1111]. Duplication is performed by performing a SHIFT operation (e.g., a left shift operation) and an OR operation with a bit-vector (e.g., Row_Intermediate 2 bit-vector 441 illustrated as [0x01010001] at Row 451-8.c in FIG. 4B). For example, a left-shift operation can be performed in compute components (e.g., compute components 331) on the first element bit-vector [0000 0001] of the Intermediate 2 bit-vector 441 (at Row 451-8.d in FIG. 4B), resulting in a first element bit-vector of [0000 0010] being stored in corresponding compute components (e.g., Comp_Comp 431, corresponding to compute components 331-0 to 331-7 for the first element bit-vector). The first element bit-vector [0000 0010] stored in compute components can be ORed with the first element of the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0000 0001]), resulting in a first element bit-vector of [0000 0011]. The resulting first element bit-vector [0000 0011] can be stored as the Row_Intermediate 2 bit-vector 441 (e.g., written over the previous bit-vector) for the next OR operation. A second left-shift operation can be performed in compute components that result in a first element bit-vector of [0000 0110], and be ORed with the previously stored first element bit-vector of [0000 0011]. The result of this OR operation is a first element bit-vector [0000 0111] which is then stored as the Intermediate 2 bit-vector 441.
Each subsequent left-shift operation and OR operation results in duplicating bits across the first element bit-vector until the resulting first element bit-vector is [1111 1111]. The bits of the second, third, and fourth element of bit-vector [0x01010001] stored as the Intermediate 2 bit-vector 441 (at Row 451-8.c in FIG. 4B) are also duplicated. For example, the second element bit-vector [0000 0001] results in bit-vector [1111 1111]. The third element bit-vector [0000 0000] results in bit-vector [0000 0000] (since there is no “1” bit to duplicate). The fourth element bit-vector [0000 0001] results in bit-vector [1111 1111]. Each element can be duplicated simultaneously using sensing circuitry such that a least-significant bit in the first, second, third, and fourth elements are left-shifted at the same time to perform the duplication in parallel. After duplication of the Row_Intermediate 2 bit-vector 441 (e.g., the Row_Intermediate 2 bit-vector [0x01010001] at Row 451-8.c), the resulting duplicated Row_Intermediate 2 bit-vector 441 is stored as the Row_Intermediate 2 bit-vector 441 (shown at Row 451-8.d) as [0xffff00ff].
At reference 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector 443 (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., Comp_Comp 431, corresponding to compute components 331-0 to 331-31). For example, the bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components such that a first, second, third, fourth, and fifth compute component (e.g., compute components 331-0 through 331-4) store a “0”, and a sixth, seventh, and eight compute component (e.g., compute components 331-5 through 331-7) store a “1.” In this example, additional compute components (e.g., compute components 331-8 to 331-31) store the second, third, and fourth elements of the srca bit-vector 443.
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the srca bit-vector stored in Comp_Comp 431 based on an iteration of the multiplication operation. For example, for a first iteration of the multiplication operation (e.g., illustrated by Rows 451-8.a to 451-8.q in FIG. 4B) the srca bit-vector is shifted zero positions. That is, during a first iteration there is no shifting of the bits in the srca bit-vector. As described below, during a second iteration the bits are shifted one (1) position. During a third iteration the bits are shifted two positions (2), etc. Therefore, at Row 451-8.f, the srca bit-vector remains [0x0704080c].
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2), the srca bit-vector stored in Comp_Comp 431 (e.g., [0x0704080c]) is ANDed with the Intermediate 2 bit-vector 441 (e.g., [0xffff00ff]). For example, srca bit-vector [0x0704080c] is ANDed with bit-vector [0xffff00ff] to result in bit-vector [0x0704000c]. The resulting bit-vector [0x0704000c] is stored as the Row_Intermediate 2 bit-vector 441. That is, at row 451-8.g in FIG. 4B, the Row_Intermediate 2 bit-vector 441 is [0x0704000c].
At 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry), a half-add operation is performed on the Row_Intermediate bit-vector 439 and the Row_Intermediate 2 bit-vector 441. A half-add operation includes performing an XOR operation and an AND operation.
An XOR operation on two bit-vectors can be performed by a number of NAND, OR, and AND operations. The XOR operation on the two bit-vectors can include performing an AND operation on a result of a NAND operation and a result of an OR operation. For example, an XOR operation can be performed on a first bit-vector (e.g., [0011]) and a second bit-vector (e.g., [0110]). The XOR operation includes a NAND operation that can be performed on the first and second bit-vector, resulting in a bit-vector [1101] (e.g., ANDing [0011] and [0110] to result in [0010], and inversing the [0010] bit-vector to result in an XOR result of [1101]). The XOR operation includes an OR operation that can be performed on the first and second bit-vector, resulting in bit-vector [0111] (e.g., ORing [0011] and [0110]). The XOR operation includes an AND operation that can be performed on the result of the NAND operation (e.g., NAND operation result [1101]) and the result of the OR operation (e.g., OR operation result [0111]). The result of the AND operation (e.g., ANDing [1101] and [0111]) is bit-vector [0101], which is the result of an XOR operation performed on the first bit-vector (e.g., [0011]) and the second bit-vector (e.g., [0110]).
The result of the XOR operation on the Row_Intermediate bit-vector 439 and the Row_Intermediate 2 bit-vector 441 is stored, as shown at row 451-8.h, as the Dest bit-vector 447 (e.g., in a group of memory cells such as memory cells coupled to access line 304-R and sense lines 305-0 to 305-31). The result of the AND operation (e.g., [0x00000000] ANDed with [0x0704000c]) is stored as the Row_Carry bit-vector 437 (e.g., stored in memory cells coupled to access line 304-4 and to sense lines 305-0 to 305-31). That is, at row 451-8.h, the Row_Carry bit-vector 437 remains [0x00000000] (indicated by [0x0]). In addition, the Row_Intermediate bit-vector 439 (e.g., [0x00000000]) is XORed with the Row_Intermediate 2 bit-vector 441 (e.g., [0x0704000c]) and is stored, as shown at row 451-8.h as the Dest bit-vector 447. In this example, there is no half-add operation to perform since there are “0”s stored as the Row_Intermediate bit-vector 439, and the result of the AND operation results in a Row_Carry bit-vector 437 of [0x00000000]. The bit-vector [0x0704000c] stored in Comp_Comp 431, at row 451-8.h, from the XOR operation (e.g., [0x0] XORed with [0x0704000c] resulting in [0x0704000c]) is stored as the Dest bit-vector 447. Examples of the half-add operation will be described further below in the description of FIG. 4C (at Row 453-8.h in FIG. 4C).
References 8.h to 8.l will be described further below in relation to the second iteration of operations in FIG. 4C as the Row_Intermediate bit-vector 439 [0x00000000] (indicated as [0x0] in FIG. 4B) during the first iteration. At reference 8.i (e.g., “Load Row_Carry in Comp_Comp), the resulting bit-vector from the half-add operation that is stored as the Row_Carry bit-vector 437 can be loaded into the compute components (e.g., Comp_Comp 431 corresponding to compute components 331 in FIG. 3). At reference 8.j (e.g., “Do Comp_Comp AND operation with Row_Static Mask), the bit-vector [0x0] stored in compute components (e.g., Comp_Comp 431 corresponding to compute components 331 in FIG. 3) is ANDed with the Row_Static_Mask bit-vector 435 (e.g., bit-vector [0x7f7f7f7f]). At reference 8.k (e.g., “Shift Comp_Comp Left”), a SHIFT operation (e.g., a left-shift operation) is performed on the bit-vector [0x0] stored in compute components (e.g., Comp_Comp 431 corresponding to compute components 331 in FIG. 3). At reference 8.l (e.g., “For any true bits in Comp_Comp BlockOR”), a half-add operation is performed with the Row_Carry bit-vector 437 (e.g., [0x0], the Dest bit-vector 447 (e.g., [0x0704000c]), and the Row_Static_Mask bit-vector 435 (e.g., [0x7f7f7f7f]). Since, in this example, the bit-vector stored in the compute components (e.g., [0x0] stored in Comp_Comp 431 corresponding to compute components 331 in FIG. 3), there is no half-add operation to be performed. A further explanation of how the half-add operation is performed with examples will be described below in relation to FIG. 4C.
At 8.m (e.g., “Load Dest in Comp_Comp), the Dest bit-vector 447 (e.g., [0x0704000c]) is loaded into the compute components (e.g., Comp_Comp 431 corresponding to compute components 331 in FIG. 3). That is, at row 451-8.m, the Dest bit-vector 447 (e.g., [0x0704000c]) is loaded into Comp_Comp 431. At reference 8.n (e.g., “Store Comp_Comp in Row_Intermediate”), the bit-vector stored in the compute components (e.g., [0x0x0704000c]) is stored as the Row_Intermediate bit-vector 439, at Row 451-8.n. That is, at row 451-8.n, the Row_Intermediate bit-vector 439 is [0x0704000c]). At reference 8.o (e.g., “Load Row_Dynamic_Mask in Comp_Comp,” at row 451-8.o in FIG. 4B), the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x01010101]) is loaded into the compute components (e.g., Comp_Comp 431). At reference 8.p (e.g., “Shift Comp_Comp Left,” at row 451-8.p in FIG. 4B), a SHIFT operation is performed on the bit-vector (e.g., bit-vector [0x01010101]) stored in the compute components (e.g., Comp_Comp 431) resulting in a bit-vector [0x02020202] being stored in the compute components (e.g., Comp_Comp 431). At reference 8.q (e.g., “Store Comp_Comp in Row_Dynamic_Mask), the resulting bit-vector [0x02020202] stored in Comp_Comp 431 is stored as the Row_Dynamic_Mask bit-vector 433, at Row 451-8.q of FIG. 4B. That is, at row 451-8.q, the Row_Dynamic_Mask bit-vector 433 is [0x02020202].
FIG. 4C illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure. The particular phase illustrated by FIG. 4C is an example of a second iteration of the multiplication phase. The second iteration can include Row 453-8.a to 453-8.q of FIG. 4C. At reference 8.a. (e.g., “Load srcb in Comp_Comp”), the srcb bit-vector (e.g., bit-vector [0x03050203]) is loaded into the appropriate compute components (e.g., compute components 331-0 to 331-31 in this example). For example, the 8 bits corresponding to the first element (e.g., [0x03] or binary [00000011]) can be loaded into compute components 331-0 to 331-7 (e.g., with the MSB being loaded into compute component 331-0 and each subsequent next-most-significant bit being loaded into the subsequent corresponding compute components 331-1 to 331-7 such that a “0” is stored in compute components 331-0 to 331-5 and a “1” is stored in compute components 331-6 and 331-7). Subsequent elements (e.g., the second ([0x05], third ([0x02]), and fourth ([0x03]) element) of the srcb bit-vector 445 can be loaded into subsequent corresponding compute components 331-8 to 331-31. As such, row 453-8.a of the table shown in FIG. 4C illustrates the bit vector 431 having a value of [0x03050203].
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector (e.g., bit-vector [0x03050203]) shown in row 453-8.a (e.g., previously latched in the compute components 331-0 to 331-31) and the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector 0x02020202, which can be stored in memory cells coupled to the access line 304-2 and to sense lines 331-0 to 331-31) As used herein performing a logical operation on a first and second bit-vector can include performing, in parallel, the logical operation on each of the respective bits at particular bit positions of the bit-vectors in parallel. As an example, the result of a logical AND operation performed on a first bit-vector “a” and a second bit-vector “b” is a bit-vector whose MSB is the result of “ANDing” the MSB of bit-vector “a” and the MSB of bit-vector “b,” whose next MSB is the result of ANDing the next MSBs of bit-vectors “a” and “b, and whose LSB is the result of ANDing the LSB of bit-vector “a” and the LSB of bit-vector “b.” For instance, performing an AND operation on a bit-vector [1110] and on bit-vector [1000] would result in bit-vector (e.g., the MSB of the resultant bit-vector is “1” since “1” AND “1” is “1”, the next MSB is “0” since “1” AND “0” is “0”, the next MSB is “0” since “1” AND “0” is “0”, and the LSB is “0” since “0” AND “0” is “0”).
Since the value of the srcb bit-vector 445 was loaded into the compute components 331-0 to 331-31, the result of “ANDing” the bit-vector 431 with the bit-vector 433 is analogous to the result of performing an AND operation on the srcb bit-vector 445 and the Row_Dynamic_Mask bit-vector 433. As such, bit-vector [00000011 00000101 00000010 00000011] (e.g., [0x03050203]) is “ANDed” with bit-vector [00000010 00000010 00000010 00000010] (e.g., [0x02020202]), which results in bit-vector [00000010 00000000 00000010 00000010] (e.g., [0x02000202]). In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., 331-0 to 331-31) as bit-vector 431. For instance, row 453-8.b illustrates the Comp_Comp bit-vector 431 as being [0x02000202].
At reference 8.c (e.g., “Store Comp_Comp in Row_Intermediate 2), the result of the AND operation performed at reference 8.b (e.g., bit-vector [0x02000202]) is stored in (e.g., written to) the memory cells storing the Row_Intermediate_2 bit-vector 441. As an example, the Row_Intermediate_2 bit-vector 441 can be stored in cells coupled to access line 304-6 and to sense lines 305-0 to 305-31. Row 451-8.c of the table shown in FIG. 4C illustrates the Row_Intermediate_2 bit-vector 441 having a value of [0x02000202].
At reference 8.d (e.g., reference “8.d Duplicate bits for each vector by left shifting and OR with Row_Intermediate 2), bits of the Row_Intermediate 2 bit-vector 441 are duplicated. Duplicating bits refers to filling an element with a particular bit in a least-significant bit position. For example, a bit (e.g., “1”) of bit-vector [0000 0001] can be duplicated by adding the “1” bit in the least significant bit position to each position of the element, resulting in bit-vector [1111 1111]. Duplication is performed by performing a SHIFT operation (e.g., a left shift operation) and an OR operation with a bit-vector (e.g., Row_Intermediate 2 bit-vector 441 illustrated as [0x02000202] at Row 453-8.c in FIG. 4C). For example, a left-shift operation can be performed in corresponding compute components (e.g., compute components 331-0 to 331-7) storing the first element bit-vector [0000 0010] (e.g., the first element [0x02] of the bit-vector [0x02000202] stored as the Row_Intermediate 2 bit-vector 441 at Row 453-8.c), resulting in a first element bit-vector of [0000 0100] (after the left shift) being stored in corresponding compute components (e.g., compute components 331-0 to 331-7). The bit-vector [0000 0100] stored in compute components (e.g., compute components 331-0 to 331-7) can be ORed with the bit-vector [0000 0010] stored as the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x0000 0010]), resulting in a bit-vector of [0000 0110]. The resulting bit-vector [0000 0110] can be stored as the Row_Intermediate 2 bit-vector 441 for a subsequent OR operation. A second left-shift operation can be performed in compute components to result in a bit-vector of [0000 1100]. The bit-vector stored in the compute components (e.g., [0000 1100]) can be ORed with the previously stored Row_Intermediate_2 bit-vector 441 (e.g., [0000 0110]), resulting in bit-vector [0000 1110], which is then stored as the Row_Intermediate 2 bit-vector 441.
Each subsequent left-shift operation and OR operation results in duplicating bits across the first element bit-vector (e.g., [0000 0010]) until the resulting bit-vector is [1111 1110] is stored in the corresponding compute components (e.g., compute components 331-0 to 331-7). The bits of the second, third, and fourth element of bit-vector [0x02000202] of the Row_Intermediate bit-vector 441 [0x02000202] at reference 453-8.c are also duplicated. For example, the second element bit-vector [0000 0000] results in bit-vector [0000 0000] since there is no “1” bit to duplicate. The third element bit-vector [0000 0010] results in bit-vector [1111 1110]. The fourth element bit-vector [0000 0010] results in bit-vector [1111 1110]. Each element can be duplicated simultaneously using sensing circuitry such that a least-significant bit in the first, second, third, and fourth elements are left-shifted at the same time to perform the duplication in parallel. After duplication of the Row_Intermediate 2 bit-vector 441 (e.g., the Row_Intermediate 2 bit-vector [0x02000202]) at row 451-8.c), the Row_Intermediate 2 bit-vector 441 is [1111 1110, 0000 0000, 1111 1110, 1111 1110] or [0xfe00fefe], at row 451-8.d in FIG. 4C.
At 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector 443 (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., compute components 331-0 to 331-31). For example, the bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components such that a first, second, third, fourth, and fifth compute component (e.g., compute components 331-0 through 331-4) store a “0”, and a sixth, seventh, and eight compute component (e.g., compute components 331-5 through 331-7) store a “1.” Additional compute components (e.g., corresponding compute components 331-8 through 331-31) store the corresponding second, third, and fourth elements of the bit-vector, in this example. That is, at row 451-8.e, the bit-vector [0x0704080c] is loaded into the Comp_Comp 431.
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the bit-vector stored in the compute components based on an iteration of the multiplication operation. For example, during a second iteration of the multiplication operation (e.g., from row 453-8.a to row 453-8.q) the srca bit-vector is shifted one position. That is, during the second iteration the bits are shifted one (1) compute component to the left. During a third iteration the bits are shifted twice (2), etc. Therefore, at reference 8.f, the bits of the first element of the srca bit-vector (e.g., [0000 0111] or [0x07) are shifted one compute component to the left to result in a first element of the srca bit-vector of [0000 1110] or [0x0e]. The second element of the srca bit-vector (e.g., [0000 0100]) is shifted one compute component to the left to result in a second element of the srca bit-vector of [0000 1000], the third element of the srca bit-vector [0000 1000] is shifted left to result in a third element bit-vector of [0001 0000], and the fourth element of the srca bit-vector [0000 1100] is shifted left to result in a fourth element bit-vector of [0001 1000]. Therefore, the bits of srca bit-vector [0x0704080c] are shifted one compute component to the left to result in bit-vector [0x0e081018] stored, at row 453-8.f, in the Comp_Comp 431.
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2”), the bit-vector [0x0e081018] stored in Comp_Comp 431 at row 453-8.f is ANDed with the bit-vector stored as the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0xfe00fefe] at row 453-8.f). For example, bit-vector [0x0e081018] is ANDed with bit-vector [0xfe00fefe] to result in bit-vector [0x0e001018], which is stored as the Row_Intermediate 2 bit-vector 441 at row 451-8.g. At reference 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry”), a half-add operation is performed on the Row_Intermediate bit-vectors 439 (e.g., bit-vector [0x0704000c] at row 453-h of FIG. 4C) and the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x0e001018] at row 453-h). A half-add operation includes performing an XOR operation and an AND operation on a first bit-vector and a second bit-vector and storing the results as a Row_Carry bit-vector 437 and Dest bit-vector 447. For example, a first bit-vector (e.g., Row_Intermediate bit-vector 439 [0x0704000c]) is XORed with a second bit-vector (e.g., _Row_Intermediate 2 bit-vector 441 [0x0e001018]). The result (e.g., bit-vector [0x09041014]) of the XOR operation is stored as the Dest bit-vector 447, at row 453-h. The first bit-vector (e.g., bit-vector [0x0704000c]) stored as the Row_Intermediate bit-vector 439 is ANDed with the second bit-vector (e.g., bit-vector [0x0e001018]) stored as the Row_Intermediate 2 bit-vector. The result of the AND operation (e.g., bit-vector [0x06000008]) is stored as the Row_Carry bit-vector 437.
At reference 8.i (e.g., “Load Row_Carry in Comp_Comp”), the bit-vector (e.g., bit-vector [0x06000008]) stored as the Row_Carry bit-vector 437 is loaded into the compute components (e.g., computer components 331-0 to 331-31), at row 453-8.i of FIG. 4C. At reference 8.j (e.g., “Do Comp_Comp AND operation with Row_Static Mask”), the bit-vector (e.g., bit-vector [0x06000008]) stored in the Comp_Comp 431, at row 453-8.j, is ANDed with the bit-vector (e.g., bit-vector [0x7f7f7f7f]) stored as the Row_Static_Mask bit-vector 435. The result of the AND operation (e.g., [0x06000008] ANDed with [0x7f7f7f7f]) a bit-vector of [0x0x06000008], which is stored in the Comp_Comp 431, at row 453-8.j. At reference number 8.k (e.g., “Shift Comp_Comp Left”), a SHIFT operation (e.g., a left shift) is performed on the bit-vector stored, at row 453-8.k, in the Comp_Comp 431 (e.g., bit-vector [0x06000008]). The result of the left shift is a bit-vector of [0x0c000010].
At reference 8.l (e.g., “For any true bits in Comp_Comp BlockOR), a loop to determine whether three are any carry-over bits continues while the bit-vector stored in the Comp_Comp 431 includes a “1” bit. A BlockOR operation (described below) is performed to determine if the bit-vector stored in the Comp_Comp 431 comprises any “1” bits. For example, the bit-vector [0x0c000010], stored in Comp_Comp 431 at row 453-8.l, includes at least one “1” bit which indicates to continue the loop. The loop starting at reference 8.l can include, at reference 8.l.i, storing the bit-vector (e.g., bit-vector [0x0c000010] stored in the Comp_Comp 431 at row 453-8.l) as the Row_Carry bit-vector 437.
In a number of embodiments, a “BlockOR” operation can be performed in association with determining if the memory cells coupled to one or more (e.g., any) particular sense line store a particular data value (e.g., a bit of “1” or a bit of “0”). The determination of whether any of the sense lines are coupled to cells storing a particular data value can include charging (e.g., precharging) a local I/O line (e.g., local I/O line 334 in FIG. 3) coupled to a secondary sense amplifier (e.g., SSA 312 in FIG. 3) to a particular voltage. The I/O line (e.g., I/O line 334) can be precharged via control circuitry such as controller 140 shown in FIG. 1 and/or sensing circuitry such as circuitry 150 shown in FIG. 1, for instance, to a voltage such as a supply voltage (e.g., Vcc) or a ground voltage (e.g., 0V).
Performing a BlockOR operation (which may be referred to as an “AccumulatorBlockOr”), the column decode lines (e.g., column decode lines 310-0 to 310-W in FIG. 3) coupled to the selected sensing circuitry (e.g., compute components 331-0 to 331-X) can be activated in parallel (e.g., such that respective transistors 308-0 to 308-V in FIG. 3 are enable (e.g., turned on)) in order to transfer the voltages of the components of the sensing circuitry (e.g., sense amplifiers 306 and/or accumulators 331 in FIG. 3) to the local I/O line (e.g., local I/O 334 in FIG. 3). The secondary sense amplifier (e.g., SSA 312 in FIG. 3) can sense whether the precharged voltage of the local I/O line changes (e.g., by more than a threshold amount) responsive to activation of the column decode lines.
For instance, if the I/O line (e.g., I/O line 334) is precharged to a ground voltage and one or more of the selected compute components (e.g., 331-0 to 331-X) stores a logic 1 (e.g., 0V), then the SSA (e.g., SSA 312) can sense a pull up (e.g., increase) of the voltage on the I/O line (e.g., I/O line 334) to determine whether at least one of the accumulators stores a “1”. Alternatively, if the I/O line (e.g., I/O line 334) is precharged to Vcc and one or more of the selected compute components (e.g., CC 331-0 to 331-X) stores a logic 0 (e.g., 0V) to represent a stored logic “0”, then the SSA (e.g., SSA 312 can sense a pull down (e.g., decrease) of the voltage on the I/O line (e.g., I/O line 334) to determine whether at least one compute component stores a logic “0”. The determination of whether one or more compute components (e.g., CC 331-0 to 331-X) coupled to selected column decode lines (e.g., column decode lines 310-0 to 310-W) stores a particular data value (e.g., a data value of “1”) is effectively performing a logic “OR” operation. In this manner, voltages corresponding to data sensed by sense amps (e.g., SAs 306-0 to 306-U) and/or stored in compute components (e.g., compute components 331-0 to 331-X) can be transferred, in parallel, to the local I/O line (e.g., L I/O line 334) and sensed by the SSA (e.g., SSA 312) as part of a BlockOR operation. Embodiments of the present disclosure are not limited to particular precharge voltages of the local I/O line and/or to particular voltage values corresponding to logic “1” or logic “0”.
At reference 8.l.ii, the loop includes performing a half-add operation on the bit-vector (e.g., bit-vector [0x09041014]) stored as the Dest bit-vector 447 and the bit-vector (e.g., bit-vector [0x0c000010]) stored as the Row_Carry bit-vector 437. The half-add operation includes performing an XOR operation on bit-vector [0x09041014] (stored as the Dest bit-vector 447) and bit-vector [0x0c000010] (stored as the Row_Carry bit-vector 437, resulting in bit-vector [0x05041004]. The result of the XOR operation (e.g., [0x05041004]) is stored as the Dest bit-vector 447, at row 453-8.l.ii. The half-add operation also includes performing an AND operation on bit-vectors [0x09041014] and [0x0c000010], resulting in bit-vector [0x08000010]. At reference 8.l.iii (e.g., “Load Row_Carry in Comp_Comp”), the bit-vector (e.g., bit-vector [0x08000010]) stored in the compute components (e.g., compute components 331-0 to 331-31) is stored as the Row_Carry bit-vector 437.
At reference 8.l.iv (e.g., “Do Comp_Comp AND operation with Row_Static_Mask”), the bit-vector (e.g., bit-vector [0x08000010]) stored in Comp_Comp 431 is ANDed with the bit-vector (e.g., bit-vector [0x7f7f7f7f]) stored as the Row_Static_Mask bit-vector 435. The resulting bit-vector of the AND operation is bit-vector [0x08000010]. At reference 8.l.v (e.g., “Shift Comp_Comp Left”), the bits of the bit-vector (e.g., bit-vector [0x08000010]) stored in the Comp_Comp 431 are shifted by one compute component to the left, resulting in bit-vector [0x10000020]. At reference 8.l.vi (representing a second loop of references 8.l.i through 8.l.v), a half-add operation (e.g., an XOR operation and an AND operation, each stored in separate locations) is performed on the bit-vector stored in the compute components 431 (e.g., bit-vector [0x10000020]) and the Dest bit-vector 447 (e.g., bit-vector [0x05041004]). An XOR operation is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x10000020]) and the Dest bit-vector 447 (e.g., [0x05041004]). The result of the XOR operation (e.g., [0x15041024]) is stored as the Dest bit-vector 447. An AND is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x10000020]) and the Dest bit-vector 447 (e.g., [0x05041004]). The result of the AND operation (e.g., bit-vector [0x00000000]) is stored as the Row_Carry bit-vector 437, at row 453-8.l.vi. on bit-vectors [0x10000020] and [0x05041004]). The resulting [0x0] bit-vector remaining in the compute components 431 is ANDed with the Row_Static_Mask bit-vector 435, resulting in bit-vector [0x0]. The resulting [0x00000000] bit-vector (indicated by [0x0]) is left-shifted in the compute components 431 resulting in bit-vector [0x0]. A BlockOR operation is performed on the [0x0] bit-vector stored in the Comp_Comp 431 and results in a determination that there are no “1” bits in the bit-vector. The determination of no “1” bits ends the while loop.
At reference 8.m (e.g., “Load dest in Comp_Comp,” illustrated at 453-8.m in FIG. 4C), the Dest bit-vector 447 (e.g., bit-vector [0x15041024]) is loaded into the compute components (e.g., corresponding to compute components 331-0 to 331-31. At reference 8.n (e.g., “Store Comp_Comp in Row_Intermediate”), the bit-vector stored in the compute components (e.g., Comp_Comp 431 at row 453-8.n) is stored as the Row_Intermediate bit-vector 439. At reference 8.o (e.g., “Load Row_Dynamic_Mask in Comp_Comp”), the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x02020202]) is loaded into the compute components (e.g., Comp_Comp 431 at row 453-8.o). At reference 8.p (e.g., “Shift Comp_Comp Left”), a SHIFT operation is performed on the bit-vector (e.g., bit-vector [0x02020202]) stored in the compute components (e.g., Comp_Comp 431 at rotw 453-8.p) resulting in a bit-vector (e.g., bit-vector [0x04040404]) being stored in the compute components (e.g., Comp_Comp 431). At reference 8.q (e.g., “Store Comp_Comp in Row_Dynamic_Mask”), the resulting bit-vector (e.g., bit-vector [0x04040404]) stored in the Comp_Comp 431 is stored as the Row_Dynamic Mask bit-vector 433, shown at row 453-8.q in FIG. 4C.
FIG. 4D illustrates a table showing the states of memory cells of an array at a particular phase associated with performing a multiplication operation in accordance with a number of embodiments of the present disclosure. A third iteration of operations of the multiplication phase is illustrated by rows 455-8.a to 455-8.q in FIG. 4D. At reference 8.a. (e.g., “Load srcb in Comp_Comp”), the srcb bit-vector (e.g., bit-vector [0x03050203]) can be loaded into compute components 431 (e.g., into a latch of compute components 331-0 to 331-31). For example, the 8 bits of the first element of the srcb bit-vector (e.g., first element [0x03]) can be loaded into compute components (e.g., into a latch of compute components 331-0 to 331-7). That is, the MSB (e.g., a “0”) is loaded into compute component 331-0, at row 455-8.a in FIG. 4D, and each subsequent next-most-significant bit is loaded into the subsequent corresponding compute components (e.g., a “0” into compute components 331-1 to 331-5 and a “1” into compute components 331-6 and 331-7). Subsequent elements (e.g., a second, third, and fourth element) of the srcb bit-vector can be loaded into subsequent corresponding compute components (e.g., corresponding compute components 331-8 to 331-31).
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector (e.g., bit-vector [0x03050203]) previously latched in the compute components (e.g., compute components 331-0 to 331-31) and the Row_Dynamic Mask bit-vector 433 (e.g., bit-vector [0x04040404]). For example, the first element of the srcb bit-vector (e.g., bit-vector [0000 0011] or [0x03]) is ANDed with the first element of the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0000 0100] or [0x04]), resulting in bit-vector [0000 0000]. The second element of the srcb bit-vector (e.g., [0000 0101] or [0x05]) and the Row-Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed, the third element of the srcb bit-vector (e.g., [0000 0010] or [0x02]) and the Row_Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed, and the fourth elements of the srcb bit-vector (e.g., [0000 0011] or [0x03]) and the Row_Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed. The ANDing of the four elements of the srcb bit-vector with the four elements of the Row_Dynamic Mask bit-vector results in bit-vector [0000 0000, 0000 0100, 0000 0000, 0000 0000] or [0x00040000]. In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., compute components 331-0 to 331-31).
At reference 8.c (e.g., reference “Store Comp_Comp in Row_Intermediate 2”), the result of the AND operations at reference 8.b (e.g., bit-vector [0x00040000]) are stored as the Row_Intermediate 2 bit-vector 441, shown at row 453-8.c in FIG. 4D. At reference 8.d (e.g., “Duplicate bits for each vector by left shifting and OR with Row_Intermediate 2”), bits of the Row_Intermediate_2 bit-vector 441 (e.g., [0x0x00040000]) are duplicated. Duplicating bits refers to filling an element with a particular bit in a least-significant bit position. For example, a bit (e.g., “1”) of an example bit-vector [0000 0001] can be duplicated by adding the “1” bit in the least significant bit position to each position of the element, resulting in bit-vector [1111 1111]. Duplication is performed by performing a SHIFT operation (e.g., a left shift operation) and an OR operation with a bit-vector (e.g., an Row_Intermediate 2 bit-vector 441). For example, a left-shift operation can be performed on the second element bit-vector (e.g., [0000 0100]) of the bit-vector [0x00040000] that is stored in compute components (e.g., compute components 331-0 to 331-31), resulting in a second element bit-vector of [0000 1000] being stored in compute components (e.g., corresponding to compute components 331-8 to 331-15). The first element bit-vector [0x0], the third element bit-vector [0x0], and the fourth element bit-vector [0x0] result in the same bit-vector after duplication for each of the first, third, and fourth elements (e.g., a [0x0] bit-vector for each). The resulting second element bit-vector [0000 1000] stored in compute components (e.g., compute components 331-8 to 331-15) can be ORed with the second element bit-vector [0x0000 0100] stored as the Row_Intermediate 2 bit-vector 441, resulting in a bit-vector of [0000 1100]. The result of the duplication (e.g., bit-vector [0x0000 1100]) can be stored as the Row_Intermediate 2 bit-vector 441 for the next OR operation. A second left-shift operation can be performed on the bit-vector (e.g., bit-vector [0000 1100] stored in compute components to result in the second element bit-vector of [0001 1000], and be ORed with the Row_Intermediate 2 bit-vector (e.g., bit-vector [0000 1100]), resulting in a second element bit-vector (e.g., bit-vector [0001 1100]) which is then stored as the Row_Intermediate 2 bit-vector 441.
Each subsequent left-shift operation and OR operation results in duplicating bits across the second element bit-vector until the resulting second element bit-vector is [1111 1100] (or [0xfc]). The bits of the first, third, and fourth element of bit-vector [0x00040000] stored as the Row_Intermediate 2 bit-vector 441 at reference 8.c are also duplicated. However, the duplication of the first, third, and fourth elements results in the same [0x0] bit-vector for each since there is no “1” bit to duplicate. After duplication of the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x00040000]), the Row_Intermediate 2 bit-vector becomes [0000 0000, 1111 1100, 0000 0000, 0000 0000] or [0x00fc0000].
At reference 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., compute components 331-0 to 331-31 designated as Comp_Comp 431). For example, the eight (8) bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components, at row 455-8.e in FIG. 4D, such that a first, second, third, fourth, and fifth compute component (e.g., compute components 331-0 through 331-4) store a “0”, and a sixth, seventh, and eighth compute component (e.g., compute components 331-5 through 331-7) store a “1.” Additional compute components (e.g., compute components 331 coupled to sense lines 305-8 through 305-31) store the second, third, and fourth elements of the bit-vector in this example.
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the srca bit-vector based on an iteration of the multiplication operation. For example, during a third iteration of the multiplication operation (e.g., illustrated by row 455-8.a to row 455-8.q) the srca bit-vector is shifted two (2) positions. Therefore, at reference 8.f, the srca bit-vector is shifted two positions to the left (e.g., shifted over two compute components) to result in bit-vector [0x1c102030], as shown at row 455-8.f. 
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2”), the shifted srca bit-vector (e.g., [0x1c102030], previously stored in Comp_Comp 431 at reference 455-8.f) is ANDed with the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x00fc0000]). For example, the shifted srca bit-vector [0x1c102030] is ANDed with bit-vector [0x00fc0000] to result in bit-vector [0x00100000]. The resulting bit-vector [0x00100000] is stored as the Row_Intermediate 2 bit-vector 441, as show at row 455-8.g. 
At reference 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry”), a half-add operation is performed on the Row_Intermediate bit-vector 439 (e.g., [0x15041024]) and the Row_Intermediate 2 bit-vector 441 (e.g., [0x0x00100000]). A half-add operation includes performing an XOR operation and an AND operation. The XOR operation is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x00100000] from row 455-8.g) and the Dest bit-vector 447 (e.g., [0x15041024]). The result of the XOR operation (e.g., [0x15141024]) is stored as the Dest bit-vector 447. An AND operation is performed on the bit-vector (e.g., [0x00100000]) (e.g., by loading the Row_Intermediate 2 bit-vector (e.g., bit-vector [0x00100000]) into the Comp_Comp 431) and the Dest bit-vector 447 (e.g., [0x15041024]). The result of the AND operation (e.g., bit-vector [0x00000000]) is stored as the Row_Carry bit-vector 437, at row 455-8.l.h. 
At reference 8.i (e.g., “Load Row_Carry in Comp_Comp), the resulting bit-vector [0x0] from the half-add operation that is stored as the Row_Carry bit-vector 437 can be loaded, as shown at row 455-8.i, into the compute components (e.g., corresponding compute components 331-0 to 331-31). At reference 8.j (e.g., “Do Comp_Comp AND operation with Row_Static Mask”), the bit-vector [0x0] stored in Comp_Comp 431 is ANDed with a bit-vector (e.g., bit-vector [0x7f7f7f7f]) stored as the Row_Static_Mask bit-vector 435. At reference 8.k (e.g., “Shift Comp_Comp Left”), a SHIFT operation (e.g., a left-shift operation) is performed on bits in the bit-vector [0x0] stored in compute components (e.g., Comp_Comp 431 corresponding to compute components 331-0 to 331-31 in FIG. 3). The left-shift operation results in a bit-vector of [0x0] since there are no “1” bits to shift.
At reference 8.l (e.g., “For any true bits in Comp_Comp BlockOR), a BlockOR operation (as described above in relation to rows 453-l.i to 453-8.lv) is performed on the bit-vector stored in Comp_Comp 431 (e.g., [0x0]). Since there are no “1”s in the [0x0] bit-vector stored in Comp_Comp 431, the BlockOR operation ends the while loop (e.g., loop continues while there is a “1” in the bit-vector), as shown in the Comp_Comp 431 at row 455-8.l. 
At reference 8.m (e.g., “Load Dest in Comp_Comp”), the Dest bit-vector 447 is loaded into the Comp_Comp 431 (e.g., corresponding to compute components 331-0 to 331-31 in FIG. 3). That is, the bit-vector [0x15141024] is loaded into Comp_Comp 431, at row 455-8.m. At reference 8.n (e.g., “Store Comp_Comp in Row_Intermediate), the bit-vector [0x15141024] stored in the Comp_Comp 431 is stored as the Row_Intermediate bit-vector 439, as shown at row 455-8.n. At reference 8.o (e.g., “Load Row_Dynamic_Mask in Comp_Comp), the bit-vector (e.g., bit-vector [0x04040404]) stored as the Row_Dynamic_Mask bit-vector 433 is loaded into the Comp_Comp 431. At reference 8.p (e.g., “Shift Comp_Comp Left), a SHIFT operation is performed on the bit-vector (e.g., bit-vector [0x04040404]) stored in the Comp_Comp 431 resulting in a bit-vector (e.g., [0x08080808]) being in the Comp_Comp 431. At reference 8.q (e.g., “Store Comp_Comp in Row_Dynamic_Mask”), the resulting bit-vector (e.g., [0x08080808]) stored in the Comp_Comp 431 is stored as the Row_Dynamic_Mask bit-vector 433.
As subsequent iterations in this example do not change the bit-vector [0x15141024] stored in the memory cells coupled to the Dest access line 447, the subsequent iterations will not be explained in detail here. Subsequent iterations include a Row_Dynamic_Mask bit-vector of [0x08080808] during a fourth iteration, a Row_Dynamic_Mask bit-vector of [0x10101010] during a fifth iteration, a Row_Dynamic_Mask bit-vector of [0x20202020] for a sixth iteration, a Row_Dynamic_Mask bit-vector of [0x40404040] for a seventh iteration, and a Row_Dynamic_Mask bit-vector of [0x80808080] for an eighth iteration. Since a product of the two bit-vectors (e.g., srca bit-vector 443 [0x0704080c] and srcb bit-vector 445 [0x03050203) was determined after three (3) iterations, the fourth through eighth iteration continues with the same value as the Dest bit-vector (e.g., [0x15141024]), as there is no further Carry values to add into the product. The number of iterations corresponds to the fixed width of the bit-vector being multiplied (i.e., a bit-width of 8 bits in this example for each element multiplied). The resultant bit-vector [0x15141024] is a product of bit-vectors [0x0704080c] and [0x03050203]. That is, a first element [0x07] of the first bit-vector [0x0704080c] multiplied by a first element [0x03] of the second bit-vector [0x03050203] results in a first product element of [0x15] (e.g., the first element of the result bit-vector [0x15141024], stored as the Dest bit-vector 447 at row 455-8.q). A second element [0x04] of the first bit-vector multiplied by a second element [0x05] of the second bit-vector results in a second product element of [0x14]. A third element [0x08] of the first bit-vector multiplied by a third element [0x02] of the second bit-vector results in a third product element of [0x10]. A fourth element [0x0c] of the first bit-vector multiplied by a fourth element [0x03] of the second bit-vector results in a fourth product element of [0x24].
FIG. 5A illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. The functionality of the sensing circuitry 250 of FIG. 2A is described below with respect to performing logical operations and initially storing a result in the compute component 231 (e.g., secondary latch of the accumulator). The timing diagram shown in FIG. 5A illustrates signals (e.g., voltage signals) associated with performing a first operation phase of a logical operation (e.g., an R-input logical operation) using the sensing circuitry illustrated in FIG. 2A. The first operation phase described with respect to FIG. 5A can be a first operation phase of an AND, NAND, OR, or NOR operation, for instance. Performing the operation phase illustrated in FIG. 5A can involve consuming significantly less energy (e.g., about half) than previous processing approaches that may involve providing a full swing between voltage rails (e.g., between a supply and ground).
In the example illustrated in FIG. 5a, the voltage rails corresponding to complementary logic values (e.g., “1” and “0”) are a supply voltage (VDD) and a reference voltage (e.g., ground (Gnd)). Prior to performing a logical operation, an equilibration can occur such that the complementary data lines D and D— are shorted together at an equilibration voltage (VDD/2), as previously described.
The first operation phase of a logical operation described below involves loading a first operand of the logical operation into the accumulator. The time references (e.g., t1, etc.) shown in FIG. 5A do not necessarily represent a same absolute or relative time as similar time references in other timing diagrams.
At time t1, the equilibration signal 526 is deactivated, and then a selected row is enabled (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as a first input). Signal 504-0 represents the voltage signal applied to the selected row (e.g., Row Y 204-Y shown in FIG. 2A). When row signal 504-0 reaches the threshold voltage (Vt) of the access transistor (e.g., 202-1 shown in FIG. 2A) corresponding to the selected cell, the access transistor turns on and couples the data line D to the selected memory cell (e.g., to the capacitor 203-1 shown in FIG. 2A if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the data lines D and D— (e.g., as indicated by signals 505-1 and 505-2 on the data lines, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 503. Due to conservation of energy, creating the differential signal between data lines D and D— (e.g., by coupling the cell to data line D) does not consume energy, since the energy associated with enabling/disabling the row signal 504-0 can be amortized over the memory cells coupled to the row.
At time t3, the sense amplifier (e.g., 206 shown in FIG. 2A) is enabled (e.g., a positive control signal 590 (e.g., corresponding to ACT 265 shown in FIG. 2B) goes high and the negative control signal 528 (e.g., corresponding to RnIF 228 shown in FIG. 2B) goes low), which amplifies the differential signal between data lines D and D_, resulting in a voltage (e.g., VDD) corresponding to a logic “1” or a voltage (e.g., ground) corresponding to a logic “0” being on data line D (and the other voltage being on complementary data line D_), such that the sensed data value is stored in the primary latch of sense amplifier 206. The primary energy consumption occurs in charging the data line D (205-1) from the equilibration voltage VDD/2 to the rail voltage VDD. FIG. 5A shows, in example, the data line voltages 505-1 and 505-2 that correspond to a logic “1” being on data line D.
According to some embodiments, the primary latch of sense amplifier 206 can be coupled to the complementary data lines D and D— through respective pass transistors (not shown in FIG. 2A but in a similar configuration as the manner in which latch 264 is coupled to the data lines D and D— through load/pass transistors 218-1 and 218-2 shown in FIG. 2A). The Passd control signal 511 controls one pass transistor. The Passdb control signal controls the other pass transistor, and here the Passdb control signal can behave here the same as the Passd control signal.
At time t4, the pass transistors (if present) can be enabled (e.g., via respective Passd and Passdb control signals 511 applied to control lines coupled to the respective gates of the pass transistors going high). At time t5, the accumulator positive control signal 512-1 (e.g., Accumb) and the accumulator positive control signal 512-2 (e.g., Accum) are activated via respective control lines 212-1 and 212-2 shown in FIG. 2A. As described below, the accumulator control signals ACCUMB 1412-1 and ACCUM 512-2 may remain activated for subsequent operation phases. As such, in this example, activating the control signals ACCUMB 512-1 and ACCUM 512-2 enables the secondary latch (e.g., accumulator) of compute component 231 shown in FIG. 2A. The sensed data value stored in sense amplifier 206 is transferred (e.g., copied) to the secondary latch, including the dynamic latch and latch 264.
At time t6, the Passd control signal 511 (and the Passdb control signal) goes low thereby turning off the pass transistors (if present). However, since the accumulator control signals ACCUMB 512-1 and ACCUM 512-2 remain activated, an accumulated result is stored (e.g., latched) in the secondary latches (e.g., accumulator). At time t7, the row signal 504-0 is deactivated, and the array sense amps are disabled at time t8 (e.g., sense amplifier control signals 528 and 590 are deactivated).
At time t9, the data lines D and D— are equilibrated (e.g., equilibration signal 526 is activated), as illustrated by data line voltage signals 505-1 and 505-2 moving from their respective rail values to the equilibration voltage (VDD/2). The equilibration consumes little energy due to the law of conservation of energy. As described above in association with FIG. 2B, equilibration can involve shorting the complementary data lines D and D— together at an equilibration voltage, which is VDD/2, in this example. Equilibration can occur, for instance, prior to a memory cell sensing operation.
FIGS. 5B and 5C respectively illustrate timing diagrams associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. Timing diagrams shown in FIGS. 5B and 5C illustrate signals (e.g., voltage signals) associated with performing a number of intermediate operation phases of a logical operation (e.g., an R-input logical operation). For instance, timing diagram shown in FIG. 5B corresponds to a number of intermediate operation phases of an R-input NAND operation or an R-input AND operation, and timing diagram shown in FIG. 5C corresponds to a number of intermediate operation phases of an R-input NOR operation or an R-input OR operation. For example, performing an AND or NAND operation can include performing the operation phase shown in FIG. 5B one or more times subsequent to an initial operation phase such as that described with respect to FIG. 5A. Similarly, performing an OR or NOR operation can include performing the operation phase shown and described with respect to FIG. 5C one or more times subsequent to an initial operation phase such as that described with respect to FIG. 5A.
As shown in the timing diagrams illustrated in FIGS. 5B and 5C, at time t1, equilibration is disabled (e.g., the equilibration signal 526 is deactivated), and then a selected row is enabled (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as an input such as a second input, third input, etc.). Signal 504-1 represents the voltage signal applied to the selected row (e.g., Row Y 204-Y shown in FIG. 2A). When row signal 504-1 reaches the threshold voltage (Vt) of the access transistor (e.g., 202-1 shown in FIG. 2A) corresponding to the selected cell, the access transistor turns on and couples the data line D to the selected memory cell (e.g., to the capacitor 203-1 if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the data lines D and D— (e.g., as indicated by signals 505-1 and 505-2, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 503. Due to conservation of energy, creating the differential signal between D and D— (e.g., by coupling the cell to data line D) does not consume energy, since the energy associated with activating/deactivating the row signal 504-1 can be amortized over the memory cells coupled to the row.
At time t3, the sense amplifier (e.g., 206 shown in FIG. 2A) is enabled (e.g., a positive control signal 590 (e.g., corresponding to ACT 265 shown in FIG. 2B) goes high, and the negative control signal 528 (e.g., RnIF 228 shown in FIG. 2B) goes low), which amplifies the differential signal between D and D_, resulting in a voltage (e.g., VDD) corresponding to a logic 1 or a voltage (e.g., ground) corresponding to a logic 0 being on data line D (and the other voltage being on complementary data line D_), such that the sensed data value is stored in the primary latch of sense amplifier 206. The primary energy consumption occurs in charging the data line D (205-1) from the equilibration voltage VDD/2 to the rail voltage VDD.
As shown in timing diagrams illustrated in FIGS. 5B and 5C, at time t4 (e.g., after the selected cell is sensed), only one of control signals 511-1 (Passd) shown in FIG. 5B and 511-2 (Passdb) shown in FIG. 5C is activated (e.g., only one of pass transistors (if present) is enabled), depending on the particular logic operation. For example, since the timing diagram illustrated in FIG. 5B corresponds to an intermediate phase of a NAND or AND operation, control signal 511-1 (Passd) is activated at time t4 to turn on the pass transistor coupling the primary latch to data line D and the Passdb control signal remains deactivated leaving the pass transistor coupling the primary latch to data line D turned off. Conversely, since the timing diagram illustrated in FIG. 5C corresponds to an intermediate phase of a NOR or OR operation, control signal 511-2 (Passdb) is activated at time t4 to turn on the pass transistor coupling the primary latch to data line D— and control signal Passd remains deactivated leaving the pass transistor coupling the primary latch to data line D turned off. Recall from above that the accumulator control signals 512-1 (Accumb) and 512-2 (Accum) were activated during the initial operation phase described with respect to FIG. 5A, and they remain activated during the intermediate operation phase(s).
Since the accumulator was previously enabled, activating only Passd (511-1 as shown in FIG. 5B) results in accumulating the data value corresponding to the voltage signal 505-1 shown in FIG. 5B corresponding to data line D. Similarly, activating only Passdb (511-2 as shown in FIG. 5C) results in accumulating the data value corresponding to the voltage signal 505-2 corresponding to data line D_. For instance, in an example AND/NAND operation shown in the timing diagram illustrated in FIG. 5B in which only Passd (511-1) is activated, if the data value stored in the second selected memory cell is a logic “0,” then the accumulated value associated with the secondary latch is asserted low such that the secondary latch stores logic “0.” If the data value stored in the second selected memory cell is not a logic “0,” then the secondary latch retains its stored first selected memory cell data value (e.g., a logic “1” or a logic “0”). As such, in this AND/NAND operation example, the secondary latch is serving as a zeroes (0s) accumulator.
Similarly, in an example OR/NOR operation shown in the timing diagram illustrated in FIG. 5C in which only Passdb 511-2 is activated, if the data value stored in the second selected memory cell is a logic “1,” then the accumulated value associated with the secondary latch is asserted high such that the secondary latch stores logic “1.” If the data value stored in the second selected memory cell is not a logic “1,” then the secondary latch retains its stored first selected memory cell data value (e.g., a logic “1” or a logic “0”). As such, in this OR/NOR operation example, the secondary latch is effectively serving as a ones (1s) accumulator since voltage signal 505-2 on D— is setting the true data value of the accumulator.
At the conclusion of an intermediate operation phase such as that shown in FIG. 5B or 5C, the Passd signal 511-1 (e.g., for AND/NAND) or the Passdb signal 511-2 (e.g., for OR/NOR) is deactivated (e.g., at time t5), the selected row is disabled (e.g., at time t6), the sense amplifier is disabled (e.g., at time t7), and equilibration occurs (e.g., at time t8). An intermediate operation phase such as that illustrated in FIG. 5B or 5C can be repeated in order to accumulate results from a number of additional rows. As an example, the sequence of timing diagram illustrated in FIGS. 5B and/or 5C can be performed a subsequent (e.g., second) time for a third memory cell, a subsequent (e.g., third) time for a fourth memory cell, etc. For instance, for a 10-input NOR operation, the intermediate phase shown in FIG. 5C can occur 9 times to provide 9 inputs of the 10-input logical operation, with the tenth input being determined during the initial operation phase (e.g., as described with respect to FIG. 5A).
FIG. 5D illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. The timing diagram illustrated in FIG. 5D shows signals (e.g., voltage signals) associated with performing a last operation phase of a logical operation (e.g., an R-input logical operation). For instance, the timing diagram illustrated in FIG. 5D corresponds to a last operation phase of an R-input AND operation or an R-input OR operation.
For example, performing a last operation phase of an R-input can include performing the operation phase shown in FIG. 5D subsequent to a number of iterations of the intermediate operation phase(s) described in association with FIGS. 5B and/or 5C. Table 3 shown below indicates the Figures corresponding to the sequence of operation phases associated with performing a number of R-input logical operations in accordance with a number of embodiments described herein.













TABLE 3







Operation
FIG. 5A
FIG. 5B
FIG. 5C
FIG. 5D









AND
First phase
R-1

Last phase





iterations



NAND
First phase
R-1





iterations



OR
First phase

R-1
Last phase






iterations



NOR
First phase

R-1






iterations










A NAND operation can be implemented, for example, by storing the result of the R-1 iterations for an AND operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below). A NOR operation can be implemented, for example, by storing the result of the R-1 iterations for an OR operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below).
The last operation phase illustrated in the timing diagram of FIG. 5D is described in association with storing a result of an R-input logical operation to a row of the array (e.g., array 230 shown in FIG. 2A). However, as described above, in a number of embodiments, the result can be stored to a suitable location other than back to the array (e.g., to an external register associated with a controller and/or host processor, to a memory array of a different memory device, etc., via I/O lines).
As shown in timing diagram illustrated in FIG. 5D, at time t1, equilibration is disabled (e.g., the equilibration signal 526 is deactivated) such that data lines D and D— are floating. At time t2, the Passd control signal 511 (and Passdb signal) is activated for an AND or OR operation.
Activating the Passd control signal 511 (and Passdb signal) (e.g., in association with an AND or OR operation) transfers the accumulated output stored in the secondary latch of compute component 231 shown in FIG. 2A to the primary latch of sense amplifier 206. For instance, for an AND operation, if any of the memory cells sensed in the prior operation phases (e.g., the first operation phase illustrated in FIG. 5A and one or more iterations of the intermediate operation phase illustrated in FIG. 5B) stored a logic “0” (e.g., if any of the R-inputs of the AND operation were a logic “0”), then the data line D— will carry a voltage corresponding to logic “1” (e.g., VDD) and data line D will carry a voltage corresponding to logic “0” (e.g., ground). For this AND operation example, if all of the memory cells sensed in the prior operation phases stored a logic “1” (e.g., all of the R-inputs of the AND operation were logic “1”), then the data line D— will carry a voltage corresponding to logic “0” and data line D will carry a voltage corresponding to logic “1”. At time t3, the primary latch of sense amplifier 206 is then enabled (e.g., a positive control signal 590 (e.g., corresponding to ACT 265 shown in FIG. 2B) goes high and the negative control signal 528 (e.g., corresponding to RnIF 228 shown in FIG. 2B) goes low), which amplifies the differential signal between data lines D and D_ such that the data line D now carries the ANDed result of the respective input data values as determined from the memory cells sensed during the prior operation phases. As such, data line D will be at ground if any of the input data values are a logic “0” and data line D will be at VDD if all of the input data values are a logic “1.”
For an OR operation, if any of the memory cells sensed in the prior operation phases (e.g., the first operation phase of FIG. 5A and one or more iterations of the intermediate operation phase shown in FIG. 5C) stored a logic “1” (e.g., if any of the R-inputs of the OR operation were a logic “1”), then the data line D— will carry a voltage corresponding to logic “0” (e.g., ground) and data line D will carry a voltage corresponding to logic “1” (e.g., VDD). For this OR example, if all of the memory cells sensed in the prior operation phases stored a logic “0” (e.g., all of the R-inputs of the OR operation were logic “0”), then the data line D will carry a voltage corresponding to logic “0” and data line D— will carry a voltage corresponding to logic “1.” At time t3, the primary latch of sense amplifier 206 is then enabled and the data line D now carries the ORed result of the respective input data values as determined from the memory cells sensed during the prior operation phases. As such, data line D will be at VDD if any of the input data values are a logic “1” and data line D will be at ground if all of the input data values are a logic “0.”
The result of the R-input AND or OR logical operations can then be stored back to a memory cell of array 230 shown in FIG. 2A. In the examples shown in FIG. 5D, the result of the R-input logical operation is stored to a memory cell coupled to the last row enabled (e.g., row of the last logical operation operand). Storing the result of the logical operation to a memory cell simply involves enabling the associated row access transistor by enabling the particular row. The capacitor of the memory cell will be driven to a voltage corresponding to the data value on the data line D (e.g., logic “1” or logic “0”), which essentially overwrites whatever data value was previously stored in the selected memory cell. It is noted that the selected memory cell can be a same memory cell that stored a data value used as an input for the logical operation. For instance, the result of the logical operation can be stored back to a memory cell that stored an operand of the logical operation.
The timing diagram illustrated in FIG. 5D show, at time t7, the positive control signal 590 and the negative control signal 528 being deactivated (e.g., signal 590 goes low and signal 528 goes high) to disable the sense amplifier 206 shown in FIG. 2A. At time t4 the Passd control signal 511 (and Passdb signal) that was activated at time t2 is deactivated. Embodiments are not limited to this example. For instance, in a number of embodiments, the sense amplifier 206 shown in FIG. 2A may be enabled subsequent to time t4 (e.g., after the Passd control signal 511 (and Passdb signal) are deactivated).
As shown in FIG. 5D, at time t5, a selected row is enabled (e.g., by row activation signal 504 going high, which drives the capacitor of the selected cell to the voltage corresponding to the logic value stored in the accumulator. At time t6 the selected row is disabled. At time t7 the sense amplifier 206 shown in FIG. 2A is disabled (e.g., positive control signal 528 and negative control signal 590 are deactivated in FIG. 5D), and at time t8 equilibration occurs (e.g., signal 526 is activated and the voltages on the complementary data lines 505-1 (D) and 505-2 (D_) are brought to the equilibration voltage, as shown in FIG. 5D).
Although the example of performing a last operation phase of an R-input was discussed above with respect to FIG. 5D for performing AND and OR logical operations, embodiments are not limited to these logical operations. For example, the NAND and NOR operations can also involve a last operation phase of an R-input that is stored back to a memory cell of array 230 using control signals to operate the sensing circuitry illustrated in FIG. 2A.
The functionality of the sensing circuitry 250 of FIG. 2A is described below and summarized in Table 1 below with respect to performing logical operations and initially storing a result in the sense amplifier 206. Initially storing the result of a particular logical operation in the primary latch of sense amplifier 206 can provide improved versatility as compared to previous approaches in which the result may initially reside in a secondary latch (e.g., accumulator) of a compute component 231, and then be subsequently transferred to the sense amplifier 206, for instance.











TABLE 1







Operation
Accumulator
Sense Amp









AND
Unchanged
Result



OR
Unchanged
Result



NOT
Unchanged
Result



SHIFT
Unchanged
Shifted Data










Initially storing the result of a particular operation in the sense amplifier 206 (e.g., without having to perform an additional operation to move the result from the compute component 231 (e.g., accumulator) to the sense amplifier 206) is advantageous because, for instance, the result can be written to a row (of the array of memory cells) or back into the accumulator without performing a precharge cycle (e.g., on the complementary data lines 205-1 (D) and/or 205-2 (D_)).
FIG. 6A illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. FIG. 6A illustrates a timing diagram associated with initiating an AND logical operation on a first operand and a second operand. In this example, the first operand is stored in a memory cell coupled to a first access line (e.g., ROW X) and the second operand is stored in a memory cell coupled to a second access line (e.g., ROW Y). Although the example refers to performing an AND on data stored in cells corresponding to one particular column, embodiments are not so limited. For instance, an entire row of data values can be ANDed, in parallel, with a different row of data values. For example, if an array comprises 2,048 columns, then 2,048 AND operations could be performed in parallel.
FIG. 6A illustrates a number of control signals associated with operating sensing circuitry (e.g., 250 in FIG. 2A) to perform the AND logical operation. “EQ” corresponds to an equilibrate signal applied to the sense amp 206, “ROW X” corresponds to an activation signal applied to access line 204-X, “ROW Y” corresponds to an activation signal applied to access line 204-Y, “Act” and “RnIF” correspond to a respective active positive and negative control signal applied to the sense amp 206, “LOAD” corresponds to a load control signal (e.g., LOAD/PASSD and LOAD/PASSDb shown in FIG. 2A), and “AND” corresponds to the AND control signal shown in FIG. 2A. FIG. 6A also illustrates the waveform diagrams showing the signals (e.g., voltage signals) on the digit lines D and D_ corresponding to sense amp 206 and on the nodes S1 and S2 corresponding to the compute component 231 (e.g., Accum) during an AND logical operation for the various data value combinations of the Row X and Row Y data values (e.g., diagrams correspond to respective data value combinations 00, 10, 01, 11). The particular timing diagram waveforms are discussed below with respect to the pseudo code associated with an AND operation of the circuit shown in FIG. 2A.
An example of pseudo code associated with loading (e.g., copying) a first data value stored in a cell coupled to row 204-X into the accumulator can be summarized as follows:
Copy Row X into the Accumulator:
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Activate LOAD (sense amplifier data (Row X) is transferred to nodes S1 and S2 of the Accumulator and resides there dynamically);
Deactivate LOAD;
Close Row X;
Precharge;
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal (EQ signal shown in FIG. 6A) corresponding to the sense amplifier 206 is disabled at t1 as shown in FIG. 6A (e.g., such that the complementary data lines (e.g., 205-1 (D) and 205-2 (D_) are no longer shorted to VDD/2). After equilibration is disabled, a selected row (e.g., ROW X) is enabled (e.g., selected, opened such as by activating a signal to select a particular row) as indicated by “Open Row X” in the pseudo code and shown at t2 for signal Row X in FIG. 6A. When the voltage signal applied to ROW X reaches the threshold voltage (Vt) of the access transistor (e.g., 202-2) corresponding to the selected cell, the access transistor turns on and couples the data line (e.g., 205-2 (D_)) to the selected cell (e.g., to capacitor 203-2) which creates a differential voltage signal between the data lines.
After Row X is enabled, in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to set the primary latch and subsequently disabled. For example, as shown at t3 in FIG. 6A, the ACT positive control signal (e.g., 265 shown in FIG. 2B) goes high and the RnIF negative control signal (e.g., 228 shown in FIG. 2B) goes low, which amplifies the differential signal between 205-1 (D) and D_ 205-2, resulting in a voltage (e.g., VDD) corresponding to a logic 1 or a voltage (e.g., GND) corresponding to a logic 0 being on data line 205-1 (D) (and the voltage corresponding to the other logic state being on complementary data line 205-2 (D_)). The sensed data value is stored in the primary latch of sense amplifier 206. The primary energy consumption occurs in charging the data lines (e.g., 205-1 (D) or 205-2 (D_)) from the equilibration voltage VDD/2 to the rail voltage VDD.
The four sets of possible sense amplifier and accumulator signals illustrated in FIG. 6A (e.g., one for each combination of Row X and Row Y data values) shows the behavior of signals on data lines D and D_. The Row X data value is stored in the primary latch of the sense amp. It should be noted that FIG. 2A shows that the memory cell including storage element 203-2 and access transistor 202-2, corresponding to Row X, is coupled to the complementary data line D_, while the memory cell including storage element 203-1 and access transistor 202-1, corresponding to Row Y, is coupled to data line D. However, as can be seen in FIG. 2A, the charge stored in the memory cell comprising access transistor 202-2 (corresponding to Row X) corresponding to a “0” data value causes the voltage on data line D— (to which memory access transistor 202-2 is coupled) to go high and the charge stored in the memory cell comprising access transistor 202-2 corresponding to a “1” data value causes the voltage on data line D— to go low, which is opposite correspondence between data states and charge stored in the memory cell corresponding to access transistor 202-1, corresponding to Row Y, that is coupled to data line D. These differences in storing charge in memory cells coupled to different data lines is appropriately accounted for when writing data values to the respective memory cells.
After firing the sense amps, in the pseudo code above, “Activate LOAD” indicates that the LOAD control signal goes high as shown at t4 in FIG. 6A, causing load/pass transistors 218-1 and 218-2 to conduct. In this manner, activating the LOAD control signal enables the secondary latch in the accumulator of the compute component 231. The sensed data value stored in the sense amplifier 206 is transferred (e.g., copied) to the secondary latch. As shown for each of the four sets of possible sense amplifier and accumulator signals illustrated in FIG. 6A, the behavior at inputs of the secondary latch of the accumulator indicates the secondary latch is loaded with the Row X data value. As shown in FIG. 6A, the secondary latch of the accumulator may flip (e.g., see accumulator signals for Row X=“0” and Row Y=“0” and for Row X=“1” and Row Y=“0”), or not flip (e.g., see accumulator signals for Row X=“0” and Row Y=“1” and for Row X=“1” and Row Y=“1”), depending on the data value previously stored in the dynamic latch.
After setting the secondary latch from the data values stored in the sense amplifier (and present on the data lines 205-1 (D) and 205-2 (D_) in FIG. 2A) in the pseudo code above, “Deactivate LOAD” indicates that the LOAD control signal goes back low as shown at t5 in FIG. 6A to cause the load/pass transistors 218-1 and 218-2 to stop conducting and thereby isolate the dynamic latch from the complementary data lines. However, the data value remains dynamically stored in secondary latch of the accumulator.
After storing the data value on the secondary latch, the selected row (e.g., ROW X) is disabled (e.g., deselected, closed such as by deactivating a select signal for a particular row) as indicated by “Close Row X” and indicated at to in FIG. 6A, which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as indicated in FIG. 6A by the EQ signal going high at t7. As shown in each of the four sets of possible sense amplifier and accumulator signals illustrated in FIG. 6A at t7, the equilibrate operation causes the voltage on data lines D and D— to each return to VDD/2. Equilibration can occur, for instance, prior to a memory cell sensing operation or the logical operations (described below).
A subsequent operation phase associated with performing the AND or the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231 shown in FIG. 2A) and the second data value (stored in a memory cell 202-1 coupled to Row Y 204-Y) includes performing particular steps which depend on the whether an AND or an OR is to be performed. Examples of pseudo code associated with “ANDing” and “ORing” the data value residing in the accumulator (e.g., the first data value stored in the memory cell 202-2 coupled to Row X 204-X) and the second data value (e.g., the data value stored in the memory cell 202-1 coupled to Row Y 204-Y) are summarized below. Example pseudo code associated with “ANDing” the data values can include:
Deactivate EQ;
Open Row Y;
Fire Sense Amps (after which Row Y data resides in the sense amps);
Close Row Y;
The result of the logic operation, in the next operation, will be placed on the sense amp, which will overwrite any row that is active.
Even when Row Y is closed, the sense amplifier still contains the Row Y data value;
Activate AND;
This results in the sense amplifier being written to the value of the function (e.g., Row X AND Row Y);
If the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data is written to a “0”;
If the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), the sense amplifier data remains unchanged (Row Y data);
This operation leaves the data in the accumulator unchanged.
Deactivate AND;
Precharge;
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal corresponding to the sense amplifier 206 is disabled (e.g., such that the complementary data lines 205-1 (D) and 205-2 (D_) are no longer shorted to VDD/2), which is illustrated in FIG. 6A at t8. After equilibration is disabled, a selected row (e.g., ROW Y) is enabled as indicated in the pseudo code above by “Open Row Y” and shown in FIG. 6A at t9. When the voltage signal applied to ROW Y reaches the threshold voltage (Vt) of the access transistor (e.g., 202-1) corresponding to the selected cell, the access transistor turns on and couples the data line (e.g., D_ 205-1) to the selected cell (e.g., to capacitor 203-1) which creates a differential voltage signal between the data lines.
After Row Y is enabled, in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to amplify the differential signal between 205-1 (D) and 205-2 (D_), resulting in a voltage (e.g., VDD) corresponding to a logic 1 or a voltage (e.g., GND) corresponding to a logic 0 being on data line 205-1 (D) (and the voltage corresponding to the other logic state being on complementary data line 205-2 (D_)). As shown at t10 in FIG. 6A, the ACT positive control signal (e.g., 265 shown in FIG. 2B) goes high and the RnIF negative control signal (e.g., 228 shown in FIG. 2B) goes low to fire the sense amps. The sensed data value from memory cell 202-1 is stored in the primary latch of sense amplifier 206, as previously described. The secondary latch still corresponds to the data value from memory cell 202-2 since the dynamic latch is unchanged.
After the second data value sensed from the memory cell 202-1 coupled to Row Y is stored in the primary latch of sense amplifier 206, in the pseudo code above, “Close Row Y” indicates that the selected row (e.g., ROW Y) can be disabled if it is not desired to store the result of the AND logical operation back in the memory cell corresponding to Row Y. However, FIG. 6A shows that Row Y is left enabled such that the result of the logical operation can be stored back in the memory cell corresponding to Row Y. Isolating the memory cell corresponding to Row Y can be accomplished by the access transistor turning off to decouple the selected cell 202-1 from the data line 205-1 (D). After the selected Row Y is configured (e.g., to isolate the memory cell or not isolate the memory cell), “Activate AND” in the pseudo code above indicates that the AND control signal goes high as shown in FIG. 6A at t11, causing pull-down transistor 207-1 to conduct. In this manner, activating the AND control signal causes the value of the function (e.g., Row X AND Row Y) to be written to the sense amp.
With the first data value (e.g., Row X) stored in the dynamic latch of the accumulator 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the compute component 231 contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data is written to a “0” (regardless of the data value previously stored in the sense amp) since the voltage corresponding to a “1” on node S1 causes transistor 209-1 to conduct thereby coupling the sense amplifier 206 to ground through transistor 209-1, pull-down transistor 207-1 and data line 205-1 (D). When either data value of an AND operation is “0,” the result is a “0.” Here, when the second data value (in the dynamic latch) is a “0,” the result of the AND operation is a “0” regardless of the state of the first data value, and so the configuration of the sensing circuitry causes the “0” result to be written and initially stored in the sense amplifier 206. This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
If the secondary latch of the accumulator contains a “1” (e.g., from Row X), then the result of the AND operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the AND operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “1,” but the result of the AND operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-1 does not conduct, the sense amplifier is not coupled to ground (as described above), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value so the AND operation result is a “1” if the Row Y data value is a “1” and the AND operation result is a “0” if the Row Y data value is a “0”). This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
After the result of the AND operation is initially stored in the sense amplifier 206, “Deactivate AND” in the pseudo code above indicates that the AND control signal goes low as shown at t12 in FIG. 6A, causing pull-down transistor 207-1 to stop conducting to isolate the sense amplifier 206 (and data line 205-1 (D)) from ground. If not previously done, Row Y can be closed (as shown at t13 in FIG. 6A) and the sense amplifier can be disabled (as shown at t14 in FIG. 6A by the ACT positive control signal going low and the RnIF negative control signal goes high). With the data lines isolated, “Precharge” in the pseudo code above can cause a precharge of the data lines by an equilibrate operation, as described previously (e.g., commencing at t14 shown in FIG. 6A).
FIG. 6A shows, in the alternative, the behavior of voltage signals on the data lines (e.g., 205-1 (D) and 205-2 (D_) shown in FIG. 2A) coupled to the sense amplifier (e.g., 206 shown in FIG. 2A) and the behavior of voltage signals on nodes S1 and S2 of the secondary latch of the compute component (e.g., 231 shown in FIG. 2A) for an AND logical operation involving each of the possible combination of operands (e.g., Row X/Row Y data values 00, 10, 01, and 11).
Although the timing diagrams illustrated in FIG. 6A and the pseudo code described above indicate initiating the AND logical operation after starting to load the second operand (e.g., Row Y data value) into the sense amplifier, the circuit shown in FIG. 2A can be successfully operated by initiating the AND logical operation before starting to load the second operand (e.g., Row Y data value) into the sense amplifier.
FIG. 6B illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. FIG. 6B illustrates a timing diagram associated with initiating an OR logical operation after starting to load the second operand (e.g., Row Y data value) into the sense amplifier. FIG. 6B illustrates the sense amplifier and accumulator signals for various combinations of first and second operand data values. The particular timing diagram signals are discussed below with respect to the pseudo code associated with an AND logical operation of the circuit shown in FIG. 2A.
A subsequent operation phase can alternately be associated with performing the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231) and the second data value (stored in a memory cell 202-1 coupled to Row Y 204-Y). The operations to load the Row X data into the sense amplifier and accumulator that were previously described with respect to times t1-t7 shown in FIG. 6A are not repeated with respect to FIG. 6B. Example pseudo code associated with “ORing” the data values can include:
Deactivate EQ;
Open Row Y;
Fire Sense Amps (after which Row Y data resides in the sense amps);
Close Row Y;
When Row Y is closed, the sense amplifier still contains the Row Y data value;
Activate OR;
This results in the sense amplifier being written to the value of the function (e.g., Row X OR Row Y), which may overwrite the data value from Row Y previously stored in the sense amplifier as follows:
If the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data remains unchanged (Row Y data);
If the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), the sense amplifier data is written to a “1”;
This operation leaves the data in the accumulator unchanged.
Deactivate OR;
Precharge;
The “Deactivate EQ” (shown at is in FIG. 6B), “Open Row Y” (shown at t9 in FIG. 6B), “Fire Sense Amps” (shown at t10 in FIG. 6B), and “Close Row Y” (shown at t13 in FIG. 6B, and which may occur prior to initiating the particular logical function control signal), shown in the pseudo code above indicate the same functionality as previously described with respect to the AND operation pseudo code. Once the configuration of selected Row Y is appropriately configured (e.g., enabled if logical operation result is to be stored in memory cell corresponding to Row Y or closed to isolate memory cell if result if logical operation result is not to be stored in memory cell corresponding to Row Y), “Activate OR” in the pseudo code above indicates that the OR control signal goes high as shown at t11 in FIG. 6B, which causes pull-down transistor 207-2 to conduct. In this manner, activating the OR control signal causes the value of the function (e.g., Row X OR Row Y) to be written to the sense amp.
With the first data value (e.g., Row X) stored in the secondary latch of the compute component 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), then the result of the OR operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the OR operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is a “1,” but the result of the OR operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “0,” with the voltage corresponding to a “0” on node S2, transistor 209-2 is off and does not conduct (and pull-down transistor 207-1 is also off since the AND control signal is not asserted) so the sense amplifier 206 is not coupled to ground (either side), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value such that the OR operation result is a “1” if the Row Y data value is a “1” and the OR operation result is a “0” if the Row Y data value is a “0”).
If the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-2 does conduct (as does pull-down transistor 207-2 since the OR control signal is asserted), and the sense amplifier 206 input coupled to data line 205-2 (D_) is coupled to ground since the voltage corresponding to a “1” on node S2 causes transistor 209-2 to conduct along with pull-down transistor 207-2 (which also conducts since the OR control signal is asserted). In this manner, a “1” is initially stored in the sense amplifier 206 as a result of the OR operation when the secondary latch of the accumulator contains a “1” regardless of the data value previously stored in the sense amp. This operation leaves the data in the accumulator unchanged. FIG. 6B shows, in the alternative, the behavior of voltage signals on the data lines (e.g., 205-1 (D) and 205-2 (D_) shown in FIG. 2A) coupled to the sense amplifier (e.g., 206 shown in FIG. 2A) and the behavior of voltage signals on nodes S1 and S2 of the secondary latch of the compute component 231 for an OR logical operation involving each of the possible combination of operands (e.g., Row X/Row Y data values 00, 10, 01, and 11).
After the result of the OR operation is initially stored in the sense amplifier 206, “Deactivate OR” in the pseudo code above indicates that the OR control signal goes low as shown at t12 in FIG. 6B, causing pull-down transistor 207-2 to stop conducting to isolate the sense amplifier 206 (and data line D 205-2) from ground. If not previously done, Row Y can be closed (as shown at t13 in FIG. 6B) and the sense amplifier can be disabled (as shown at t14 in FIG. 4 by the ACT positive control signal going low and the RnIF negative control signal going high). With the data lines isolated, “Precharge” in the pseudo code above can cause a precharge of the data lines by an equilibrate operation, as described previously and shown at t14 in FIG. 6B.
The sensing circuitry 250 illustrated in FIG. 2A can provide additional logical operations flexibility as follows. By substituting operation of the ANDinv control signal for operation of the AND control signal, and/or substituting operation of the ORinv control signal for operation of the OR control signal in the AND and OR operations described above, the logical operations can be changed from {Row X AND Row Y} to { ̃Row X AND Row Y} (where “ ̃Row X” indicates an opposite of the Row X data value, e.g., NOT Row X) and can be changed from {Row X OR Row Y} to { ̃Row X OR Row Y}. For example, during an AND operation involving the inverted data values, the ANDinv control signal can be asserted instead of the AND control signal, and during an OR operation involving the inverted data values, the ORInv control signal can be asserted instead of the OR control signal. Activating the ANDinv control signal causes transistor 214-1 to conduct and activating the ORinv control signal causes transistor 214-2 to conduct. In each case, asserting the appropriate inverted control signal can flip the sense amplifier and cause the result initially stored in the sense amplifier 206 to be that of the AND operation using inverted Row X and true Row Y data values or that of the OR operation using the inverted Row X and true Row Y data values. A true or complement version of one data value can be used in the accumulator to perform the logical operation (e.g., AND, OR), for example, by loading a data value to be inverted first and a data value that is not to be inverted second.
In a similar approach to that described above with respect to inverting the data values for the AND and OR operations described above, the sensing circuitry shown in FIG. 2A can perform a NOT (e.g., invert) operation by putting the non-inverted data value into the dynamic latch of the accumulator and using that data to invert the data value in the sense amplifier 206. As previously mentioned, activating the ANDinv control signal causes transistor 214-1 to conduct and activating the ORinv control signal causes transistor 214-2 to conduct. The ORinv and/or ANDinv control signals are used in implementing the NOT function, as described further below:
Copy Row X into the Accumulator;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Activate LOAD (sense amplifier data (Row X) is transferred to nodes S1 and S2 of the Accumulator and resides there dynamically;
Deactivate LOAD;
Activate ANDinv and ORinv (which puts the complement data value on the data lines);

    
    
        This results in the data value in the sense amplifier being inverted (e.g., the sense amplifier latch is flipped);
        This operation leaves the data in the accumulator unchanged
    
    


Deactivate ANDinv and ORinv;
Close Row X;
Precharge;
The “Deactivate EQ,” “Open Row X,” “Fire Sense Amps,” “Activate LOAD,” and “Deactivate LOAD” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. However, rather than closing the Row X and Precharging after the Row X data is loaded into the sense amplifier 206 and copied into the dynamic latch, a complement version of the data value in the dynamic latch of the accumulator can be placed on the data line and thus transferred to the sense amplifier 206 by enabling (e.g., causing transistor to conduct) and disabling the invert transistors (e.g., ANDinv and ORinv). This results in the sense amplifier 206 being flipped from the true data value that was previously stored in the sense amplifier to a complement data value (e.g., inverted data value) stored in the sense amp. That is, a true or complement version of the data value in the accumulator can be transferred to the sense amplifier by activating and deactivating ANDinv and ORinv. This operation leaves the data in the accumulator unchanged.
Because the sensing circuitry 250 shown in FIG. 2A initially stores the result of the AND, OR, and NOT logical operations in the sense amplifier 206 (e.g., on the sense amplifier nodes), these logical operation results can be communicated easily and quickly to any enabled row, any row activated after the logical operation is complete, and/or into the secondary latch of the compute component 231. The sense amplifier 206 and sequencing for the AND, OR, and/or NOT logical operations can also be interchanged by appropriate firing of the AND, OR, ANDinv, and/or ORinv control signals (and operation of corresponding transistors having a gate coupled to the particular control signal) before the sense amplifier 206 fires.
When performing logical operations in this manner, the sense amplifier 206 can be pre-seeded with a data value from the dynamic latch of the accumulator to reduce overall current utilized because the sense amps 206 are not at full rail voltages (e.g., supply voltage or ground/reference voltage) when accumulator function is copied to the sense amplifier 206. An operation sequence with a pre-seeded sense amplifier 206 either forces one of the data lines to the reference voltage (leaving the complementary data line at VDD/2, or leaves the complementary data lines unchanged. The sense amplifier 206 pulls the respective data lines to full rails when the sense amplifier 206 fires. Using this sequence of operations will overwrite data in an enabled row.
A SHIFT operation can be accomplished by multiplexing (“muxing”) two neighboring data line complementary pairs using a traditional DRAM isolation (ISO) scheme. According to embodiments of the present disclosure, the shift circuitry 223 can be used for shifting data values stored in memory cells coupled to a particular pair of complementary data lines to the sensing circuitry 250 (e.g., sense amplifier 206) corresponding to a different pair of complementary data lines (e.g., such as a sense amplifier 206 corresponding to a left or right adjacent pair of complementary data lines. As used herein, a sense amplifier 206 corresponds to the pair of complementary data lines to which the sense amplifier is coupled when isolation transistors 221-1 and 221-2 are conducting. The SHIFT operations (right or left) do not pre-copy the Row X data value into the accumulator. Operations to shift right Row X can be summarized as follows:
Deactivate Norm and Activate Shift;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which shifted Row X data resides in the sense amps);
Activate Norm and Deactivate Shift;
Close Row X;
Precharge;
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines). The SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct, thereby coupling the sense amplifier 206 to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines).
After the shift circuitry 223 is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the left adjacent pair of complementary data lines is shifted right and stored in the sense amplifier 206.
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct (e.g., coupling the sense amplifier to the corresponding pair of complementary data lines), and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct and isolating the sense amplifier 206 from the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines). Since Row X is still active, the Row X data value that has been shifted right is transferred to Row X of the corresponding pair of complementary data lines through isolation transistors 221-1 and 221-2.
After the Row X data values are shifted right to the corresponding pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X” in the pseudo code above, which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above. Operations to shift left Row X can be summarized as follows:
Activate Norm and Deactivate Shift;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Deactivate Norm and Activate Shift;
Sense amplifier data (shifted left Row X) is transferred to Row X
Close Row X;
Precharge;
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct, and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct. This configuration couples the sense amplifier 206 to a corresponding pair of complementary data lines and isolates the sense amplifier from the right adjacent pair of complementary data lines.
After the shift circuitry is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the pair of complementary data lines corresponding to the sense circuitry 250 is stored in the sense amplifier 206.
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines), and the SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct coupling the sense amplifier to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines. Since Row X is still active, the Row X data value that has been shifted left is transferred to Row X of the left adjacent pair of complementary data lines.
After the Row X data values are shifted left to the left adjacent pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X,” which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above.
FIG. 7 is a schematic diagram illustrating sensing circuitry having selectable logical operation selection logic in accordance with a number of embodiments of the present disclosure. FIG. 7 shows a sense amplifier 706 coupled to a pair of complementary sense lines 705-1 and 705-2, and a compute component 731 coupled to the sense amplifier 706 via pass gates 793-1 and 793-2. The gates of the pass gates 793-1 and 793-2 can be controlled by a logical operation selection logic signal, PASS, which can be output from logical operation selection logic 713-5. FIG. 7 shows the compute component 731 labeled “A” and the sense amplifier 706 labeled “B” to indicate that the data value stored in the compute component 731 is the “A” data value and the data value stored in the sense amplifier 706 is the “B” data value shown in the logic tables illustrated with respect to FIG. 8.
The sensing circuitry 750 illustrated in FIG. 7 includes logical operation selection logic 713-5. In this example, the logic 713-5 comprises swap gates 742 controlled by a logical operation selection logic signal PASS*. The logical operation selection logic 713-5 also comprises four logic selection transistors: logic selection transistor 762 coupled between the gates of the swap transistors 742 and a TF signal control line, logic selection transistor 752 coupled between the gates of the pass gates 793-1 and 793-2 and a TT signal control line, logic selection transistor 754 coupled between the gates of the pass gates 793-1 and 793-2 and a FT signal control line, and logic selection transistor 764 coupled between the gates of the swap transistors 742 and a FF signal control line. Gates of logic selection transistors 762 and 752 are coupled to the true sense line (e.g., 705-1) through isolation transistor 750-1 (having a gate coupled to an ISO signal control line), and gates of logic selection transistors 764 and 754 are coupled to the complementary sense line (e.g., 705-2) through isolation transistor 750-2 (also having a gate coupled to an ISO signal control line).
Operation of logic selection transistors 752 and 754 are similar based on the state of the TT and FT selection signals and the data values on the respective complementary sense lines at the time the ISO signal is asserted. Logic selection transistors 762 and 764 also operate in a similar manner to control the swap transistors 742. That is, to OPEN (e.g., turn on) the swap transistors 742, either the TF control signal is activated (e.g., high) with data value on the true sense line being “1,” or the FF control signal is activated (e.g., high) with the data value on the complement sense line being “1.” If either the respective control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the swap transistors 742 will not be OPENed by a particular logic selection transistor.
The PASS* control signal is not necessarily complementary to the PASS control signal. For instance, it is possible for the PASS and PASS* control signals to both be activated or both be deactivated at the same time. However, activation of both the PASS and PASS* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided. Logical operations results for the sensing circuitry illustrated in FIG. 7 are summarized in the logic table illustrated in FIG. 8.
FIG. 8 is a logic table illustrating selectable logic operation results implementable by the sensing circuitry shown in FIG. 7 in accordance with a number of embodiments of the present disclosure. The four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines, can be used to select one of plural logical operations to implement involving the starting data values stored in the sense amplifier 706 and compute component 731. The four control signals, in conjunction with a particular data value present on the complementary sense lines, controls pass gates 793-1 and 793-2 and swap transistors 742, which in turn affects the data value in the compute component 731 and/or sense amplifier 906 before/after firing. The capability to selectably control the swap transistors 742 facilitates implementing logical operations involving inverse data values (e.g., inverse operands and/or inverse result), among others.
The logic table illustrated in FIG. 8 shows the starting data value stored in the compute component 731 shown in column A at 844, and the starting data value stored in the sense amplifier 706 shown in column B at 845. The other 3 top column headings (NOT OPEN, OPEN TRUE, and OPEN INVERT) in the logic table of FIG. 8 refer to the state of the pass gates 793-1 and 793-2, and the swap transistors 742, which can respectively be controlled to be OPEN or CLOSED depending on the state of the four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the pair of complementary sense lines 705-1 and 705-2 when the ISO control signal is asserted. The “Not Open” column 856 corresponds to the pass gates 793-1 and 793-2 and the swap transistors 742 both being in a non-conducting condition, the “Open True” 870 corresponds to the pass gates 793-1 and 793-2 being in a conducting condition, and the “Open Invert” 871 corresponds to the swap transistors 742 being in a conducting condition. The configuration corresponding to the pass gates 793-1 and 793-2 and the swap transistors 742 both being in a conducting condition is not reflected in the logic table of FIG. 8 since this results in the sense lines being shorted together.
Via selective control of the pass gates 793-1 and 793-2 and the swap transistors 742, each of the three columns of the first set of two rows of the upper portion of the logic table of FIG. 8 can be combined with each of the three columns of the second set of two rows below the first set to provide 3×3=9 different result combinations, corresponding to nine different logical operations, as indicated by the various connecting paths shown at 875. The nine different selectable logical operations that can be implemented by the sensing circuitry 750 are summarized in the logic table illustrated in FIG. 8.
The columns of the lower portion of the logic table illustrated in FIG. 8 show a heading 880 that includes the state of logic selection control signals. For example, the state of a first logic selection control signal is provided in row 876, the state of a second logic selection control signal is provided in row 877, the state of a third logic selection control signal is provided in row 878, and the state of a fourth logic selection control signal is provided in row 879. The particular logical operation corresponding to the results is summarized in row 847.
As such, the sensing circuitry shown in FIG. 7 can be used to perform various logical operations as shown in FIG. 8. For example, the sensing circuitry 750 can be operated to perform various logical operations (e.g., AND and OR logical operations) in association with performing multiplication operations in memory in accordance with a number of embodiments of the present disclosure.
According to various embodiments, general computing can be enabled in a memory array core of a processor-in-memory (PIM) device such as a DRAM one transistor per memory cell (e.g., 1T1C) configuration at 6F^2 or 4F^2 memory cell sizes, for example. A potential advantage of certain example apparatuses and methods described herein can be cumulative speed that can be achieved by an entire bank of data being computed in parallel without necessarily transferring data out of the memory array (e.g., DRAM) or firing a column decode. For example, data transfer time can be reduce and/or eliminated. For example, apparatuses of the present disclosure can perform ANDs or ORs simultaneously using data values in memory cells coupled to a data line (e.g., a column of 16K memory cells).
In previous approach sensing circuits where data is moved out for logical operation processing (e.g., using 32 or 64 bit registers), fewer operations can be performed in parallel compared to the apparatus of the present disclosure. In this manner, significantly higher throughput is effectively provided in contrast to conventional configurations involving a central processing unit (CPU) discrete from the memory such that data must be transferred therebetween. An apparatus and/or methods according to the present disclosure can also use less energy/area than configurations where the CPU is discrete from the memory. Furthermore, an apparatus and/or methods of the present disclosure can improve upon the smaller energy/area advantages since the in-memory-array logical operations save energy by eliminating certain data value transfers.

## Claims

1. A method for performing multiplication operations comprising:
performing a multiplication operation on:
a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and
a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;

wherein the multiplication operation includes a number of logical operations performed by a controller operating sensing circuitry and without activating column decode lines coupled to the sensing circuitry.

2. The method of claim 1, wherein performing the number of operations comprises performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations.

3. The method of claim 1, further comprising generating a result from the performance of the multiplication operation and storing the result of the multiplication operation in the group of memory cells coupled to a third access line, wherein the group of memory cells comprises at least one of the group of memory cells coupled to the first access line and the group of memory cells coupled to the second access line.

4. The method of claim 1, wherein the sensing circuitry is coupled to each of a number of columns of the number of sense lines.

5. The method of claim 4, wherein the sensing circuitry comprises a sense amplifier and a compute component.

6. The method of claim 5, wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.

7. The method of claim 1, further comprising storing the first element as a bit-vector in the first group of memory cells coupled to the first access line wherein each memory cell in the first group of memory cells stores a respective bit of the bit-vector.

8. The method of claim 7, further comprising storing the second element as a bit-vector in the second group of memory cells coupled to the first access line, wherein each memory cell in the second group of memory cells stores a respective bit of the bit-vector.

9. The method of claim 8, wherein the first element is a first value and the second element is a second value.

10. An apparatus comprising:
a first group of memory cells coupled to a first access line of an array of memory cells and configured to store a first element;
a second group of memory cells coupled to a second access line of the array and configured to store a second element; and
a controller coupled to the array and configured to multiply the first element by the second element by controlling sensing circuitry to perform a number of operations without activating column decode lines coupled to the sensing circuitry.

11. The apparatus of claim 10, wherein performing the number of operations comprises performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations.

12. The apparatus of claim 10, wherein the controller is further configured to cause the sensing circuitry to determine a least-significant bit of the first element and the second element.

13. The apparatus of claim 10, wherein the controller is further configured to cause the sensing circuitry to determine a most-significant bit of the first element and the second element.

14. The apparatus of claim 10, comprising a third group of memory cells coupled to a third access line configured to store a result of the multiplication operation.

15. The apparatus of claim 10, wherein the first group of memory cells and the second group of memory cells are coupled to a number of sense lines.

16. The apparatus of claim 15, wherein:
a first memory cell of the first group of memory cells is coupled to a first sense line of the number of sense lines and stores a first bit of the first element; and
a first memory cell of the second group of memory cells is coupled to the first sense line and stores a first bit of the second element.

17. The apparatus of claim 16, wherein:
a second memory cell of the first group of memory cells is coupled to a second sense line and stores a second bit of the first element; and
a second memory cell of the second group of memory cells is coupled to the second sense line and stores a second bit of the second element.

18. The apparatus of claim 17, wherein a first memory cell of the third group of memory cells is coupled to the first sense line and stores a first bit of the result of the multiplication operation.

19. A method for performing multiplication operations comprising:
performing a multiplication operation, using a controller to operate sensing circuitry, on:
a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and
a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;

wherein the multiplication operation includes a number of operations performed without activating column decode lines coupled to the sensing circuitry;
generating a result from performance of the multiplication operation; and
storing the result of the multiplication operation as a third element stored in a group of memory cells coupled to a third access line.

20. The method of claim 19, wherein performing the multiplication operation comprises performing a number of iterations of operations using a dynamic mask element and a static mask element, wherein each iteration of operations comprises determining a data value contribution corresponding to a particular bit position of the first element and the second element to a multiplication result.

21. The method of claim 20, wherein a first iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a first bit position of the first element and the second element to a multiplication result without performing a shift operation for the dynamic mask element and the first element.

22. The method of claim 20, wherein a second iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a second bit position of the first element and the second element to the multiplication result by performing one shift operation for the dynamic mask element and the first element.

23. The method of claim 20, wherein the dynamic mask indicates a least significant bit (LSB) position.

24. The method of claim 23, comprising storing a particular data value in the LSB position of the dynamic mask.

25. The method of claim 24, further comprising determining the LSB position by:
loading the particular data value into the sensing circuitry coupled to the number of sense lines;
shifting the particular data values stored in the sensing circuitry to the sensing circuitry one position to the right;
inverting the shifted particular data values and a data value other than the particular data value stored in a most significant bit position, wherein a result of the inversion is the particular data value being stored in the MSB position of the dynamic mask element; and
shifting the particular data value stored in the MSB position of the dynamic mask element to a right-most bit position of the dynamic mask element stored in a group of memory cells coupled to a dynamic mask access line.

26. The method of claim 23, wherein the static mask element is determined by:
loading an element indicating a most significant bit into the sensing circuitry coupled to the number of sense lines;
inverting the element indicating the most significant bit; and
storing the static mask element in a group of memory cells coupled to a static mask access line.

27. The method of claim 20, wherein performing the multiplication operation comprises determining the static mask element.

28. The method of claim 27, wherein the static mask element is determined prior to an iteration of operations during the performance of the multiplication operation.

29. An apparatus comprising:
a first number of memory cells coupled to a number of sense lines and to a first access line;
a second number of memory cells coupled to the number of sense lines and to a second access line;
a third number of memory cells coupled to the number of sense lines and to a third access line; and
a controller configured to use sensing circuitry to cause:
multiplying of each of a number of first elements stored in the first number of memory cells by a corresponding element of a number of second elements stored in the second number of memory cells using a number of operations; and
storing the results of multiplying the number of first elements by the number of second elements in the third number of memory cells, wherein column decode lines coupled to the sensing circuitry are not activated to:
perform at least one of the number of operations; and
store.

30. A method for comparing elements comprising:
performing, using a controller to operate sensing circuitry, a multiplication operation in a memory array on:
a plurality (M) of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and
a plurality (M) of second elements stored in the second group of memory cells coupled to a second access line and to the number of sense lines of the memory array;

wherein the multiplication operation comprises a number of operations performed without activating column decode lines coupled to the sensing circuitry; and
providing a multiplication operation result that indicates a product of each corresponding element of the plurality of M first elements with each corresponding element of the plurality of M second elements.

31. The method of claim 30, wherein each of the M first elements and the M second elements are comprised of N bits.

32. The method of claim 31, further comprising, identifying a most significant bit (MSB) for the M first elements and the M second elements.

33. The method of claim 32, further comprising, identifying a least significant bit (LSB) for each of the M first elements and the M second elements.

34. The method of claim 33, wherein performing the comparison operation further comprises performing a number of iterations of operations using a mask element to isolate corresponding elements from the M first elements and the M second elements, wherein the mask element is created using the MSB for the M first elements and the M second elements.

35. The method of claim 30, wherein the number M of the first elements and the second elements is based on a number (L) of columns of the array.

36. The method of claim 35, wherein the number M of the first elements and the second elements is based on a number of bits (N) per element.

37. The method of claim 36, wherein the number M of the first elements and the second elements is based on the L columns of the array divided by the N bits per element.

38. The method of claim 37, wherein a least-significant bit of the first element and the second element is stored in a memory cell coupled to a same sense line.

39. The method of claim 36, wherein each bit of the N bits of the first element and the second element are stored in memory cells coupled to respective same sense lines.

40. The method of claim 39, wherein a most-significant bit of the first element and the second element is stored in a memory cell coupled to a same sense line.