PAGE 1 –OPINION AND ORDER 

IN THE UNITED STATES DISTRICT COURT 

FOR THE DISTRICT OF OREGON 

MEMORY INTEGRITY, LLC,

 Plaintiff, 

 v. 

INTEL CORPORATION, 

 Defendant. 

Case No. 3:15-cv-00262-SI 

OPINION AND ORDER

John Mansfield, MANSFIELD LAW, 121 SW Morrison Avenue, Suite 400, Portland, OR 

97204; Bryan Atkinson, FARNEY DANIELS PC, 800 S Austin Avenue, Suite 200, Georgetown, 

TX 78626; Jonathan Baker, Michael Saunders, and Gurtej Singh, FARNEY DANIELS PC, 411 

Borel Avenue, Suite 350, San Mateo, CA 94402. Of Attorneys for Plaintiff. 

Renée E. Rothauge, MARKOWITZ HERBOLD PC, 1211 SW Fifth Avenue, Suite 3000, 

Portland, OR 97204; Michael J. Summersgill, Jordan L. Hirsch, and Sean K. Thompson, 

WILMER HALE LLP, 60 State Street, Boston, MA 02109; Grant K. Rowan, WILMER HALE 

LLP, 1875 Pennsylvania Avenue NW, Washington, DC 20006; Arthur W. Coviello, WILMER 

HALE LLP, 950 Page Mill Road, Palo Alto, CA 94304. Of Attorneys for Defendant. 

Michael H. Simon, District Judge.

Plaintiff Memory Integrity, LLC (“Memory Integrity” or “MI”) brings suit against 

Defendant Intel Corporation (“Intel”) for infringement of five patents of which Memory Integrity 

is the assignee: U.S. Patent Nos. 7,296,121 (the “’121 patent”), 7,103,636 (the “’636 patent”), 

7,107,409 (the “’409 patent”), 8,572, 206 (the “’206 patent”), and 8,898,254 (the “’254 patent”). 

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The patents in suit concern algorithms and implementing mechanisms that allow for cache 

coherency1

 in multiprocessor computer systems. 

Memory Integrity alleges that Intel has infringed each patent directly, contributorily, and 

by inducement. Intel previously moved for judgment on the pleadings against Memory 

Integrity’s claims for contributory and induced infringement. The Court granted Intel’s motion in 

part, dismissing Memory Integrity’s claims for induced infringement without prejudice and with 

leave to replead. Memory Integrity amended its complaint, and Intel again moves for judgment 

on the pleadings against Memory Integrity’s claims for induced infringement. Oral argument on 

Intel’s motion took place on November 10, 2015. For the reasons below, the Court grants Intel’s 

motion, and Memory Integrity’s induced infringement claims in the second amended complaint 

(“SAC”) are dismissed with prejudice. 

STANDARDS 

A Rule 12(c) “motion for judgment on the pleadings faces the same test as a motion 

under Rule 12(b)(6).” McGlinchy v. Shell Chem. Co., 845 F.2d 802, 810 (9th Cir. 1988). 

Dismissal for failure to state a claim under Rule 12(b)(6) “is proper if there is a ‘lack of a 

cognizable legal theory or the absence of sufficient facts alleged under a cognizable legal 

theory.’” Conservation Force v. Salazar, 646 F.3d 1240, 1242 (9th Cir. 2011) (quoting 

Balistreri v. Pacifica Police Dep’t, 901 F.2d 696, 699 (9th Cir.1988)). In addition, “to survive a 

motion to dismiss, a complaint must contain sufficient factual matter to state a facially plausible 

 1

 Cache coherence issues arise in multiprocessor systems where each individual processor 

has a small, local memory called a cache and the system has a shared main memory. Each local 

cache stores data upon which the processor is currently operating to optimize access to that data. 

The data is then saved back to the main memory after operations conclude. Two or more 

processors operating on the same data may write different values into the cached copies of the 

data, in which case the system may be unable to determine which version to save to the shared 

memory. Cache coherence mechanisms address this problem. See Computer Cache Coherency 

Corp. v. Via Techs., Inc., 2008 WL 4369770, at *2 (N.D. Cal. Sept. 23, 2008). 

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claim to relief.” Shroyer v. New Cingular Wireless Servs., Inc., 622 F.3d 1035, 1041 (9th 

Cir. 2010) (citing Ashcroft v. Iqbal, 556 U.S. 662, 678 (2009)); see also Cafasso, U.S. ex rel. v. 

Gen. Dynamics C4 Sys., Inc., 637 F.3d 1047, 1054 n.4 (9th Cir. 2011) (Iqbal standard applies to 

review of Rule 12(c) motions). 

In evaluating the sufficiency of a pleading’s factual allegations, the court must draw all 

reasonable inferences in favor of the non-moving party and accept all well-pleaded material facts 

as true. Wilson v. Hewlett-Packard Co., 668 F.3d 1136, 1140 (9th Cir. 2012); Daniels-Hall v. 

Nat’l Educ. Ass’n, 629 F.3d 992, 998 (9th Cir. 2010). That presumption of truth, however, does 

not extend to legal conclusions couched as factual allegations. Ashcroft v. Iqbal, 556 U.S. 662, 

678 (2009). The plaintiff “may not simply recite the elements of a cause of action, but must 

[provide] sufficient allegations of underlying facts to give fair notice and to enable the opposing 

party to defend itself effectively.” Starr v. Baca, 652 F.3d 1202, 1216 (9th Cir. 2011). 

Furthermore, the underlying factual allegations must “plausibly suggest an entitlement to relief.” 

Id. (emphasis added). A claim will plausibly suggest entitlement to relief “when the pleaded 

factual content allows the court to draw the reasonable inference that the defendant is liable for 

the misconduct alleged.” Iqbal, 556 U.S. at 663 (citing Bell Atl. Corp. v. Twombly, 550 U.S. 544, 

556 (2007)). The U.S. Supreme Court emphasizes: “Determining whether a complaint states a 

plausible claim for relief [is] a context-specific task that requires the reviewing court to draw on 

its judicial experience and common sense.” Id. at 679. 

In considering a motion for judgment on the pleadings, a court may consider “documents 

attached to the complaint, documents incorporated by reference in the complaint, or matters of 

judicial notice—without converting the motion . . . into a motion for summary judgment.” United 

States v. Ritchie, 342 F.3d 903, 908 (9th Cir. 2003); see Heliotrope Gen., Inc. v. Ford Motor Co., 

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189 F.3d 971, 981 n.18 (9th Cir. 1999). A court may also consider documents on which the 

complaint necessarily relies if the parties do not dispute the authenticity of the documents. See 

Lee v. City of L.A., 250 F.3d 668, 688 (9th Cir. 2001). 

BACKGROUND 

A. The ’121 Patent 

The ’121 patent, entitled “Reducing Probe Traffic in Multiprocessor Systems,” details a 

“probe filtering unit” that “receive[s] probes corresponding to memory lines from the processing 

nodes” and evaluates the probes “to determine whether a valid copy of the memory line is in any 

of the cache memories.” Dkt. 105-1 at 2, 29. The filtering unit “transmit[s] the probes only to 

selected ones of the processing nodes with reference to probe filtering information.” Id. at 29. 

Memory Integrity asserts that Intel actively induces customers to directly infringe the 

’121 patent by providing “product manuals, data sheets, presentations, instructions, and other 

materials that describe, promote, and encourage use of the core valid bits . . . to reduce the 

number of processor cores that need to be snooped.” Dkt. 105 ¶ 22. In support of its assertion, 

Memory Integrity cites a multi-volume datasheet for an Intel Xeon Processor, a presentation 

entitled “Concurrency in Computer Architectures: Implications for Parallel Software 

Development,” and another presentation entitled “Using Intel VTune Amplifier XE to Tune 

Software on the 4th Generation Intel Core Processor Family.” 

Memory Integrity provides the following quotations from Intel’s documents as evidence 

that the documents encourage use of the allegedly infringing technology: 

 For any given cache line, the LLC implements core valid bits to track which local core(s) 

have cached the line in their MLC. Core valid bits are also used by LLC to determine 

which local core(s) are needed to be snooped during responding to snoop request. Id.

¶ 23. 

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 Snoop only needed if line is in L3 and core valid bit is set. . . . Core valid bits limit 

unnecessary snoops [and] . . . [o]nly need to check the core whose core valid bit is set. 

Id. ¶ 24. 

 The L3 cache has a set of ‘core valid’ bits that indicate whether each cacheline could be 

found in any L2 caches on the same socket, and if so, which ones. The first time a line is 

brought into the L3 cache, it will have core valid bits set to 1 for whichever L2 cache it 

went into. If that line is then read by a different core, then it will be fetched from L3, 

where the core valid bits will indicate it is present in one other core. The other L2 will 

have to be snooped, resulting in a longer latency access for that line. This metric 

measures the impact of that additional access time, when the cacheline in question is only 

being read-shared. In the case of read-sharing, the line can co-exist in multiple L2 caches 

in shared state, and for future accesses more than one core valid bit will be set. Then 

when other cores request the line, no L2 caches will need to be snooped, because the 

presence of 2 or more core valid bits tells the LLC that the line is shared (for reading) and 

ok to serve. Thus the impact of this only happens the first time a cacheline is requested 

for reading by a second L2 after it has already been placed in the L3 cache. Id. ¶ 25. 

B. The ’636 Patent 

The ’636 patent, entitled “Methods and Apparatus for Speculative Probing of a Remote 

Cluster,” details a “mechanism for sending probes to nodes associated with cache blocks before a 

request associated with the probes is received at a serialization point.” Dkt. 105-2 at 2, 21. The 

mechanism probes a remote processor cluster from either a request cluster or a home cluster. Id.

at 21. 

Memory Integrity asserts that Intel actively induces customers to directly infringe the 

’636 patent by providing “product manuals, data sheets, presentations, instructions, and other 

materials that describe, promote, and encourage use of two or more [processors] in combination 

to speculatively probe a remote cluster, such as by performing a source snooping operation.” 

Dkt. 105 ¶ 34. In support of its assertion, Memory Integrity cites an Intel article entitled “The 

Feeding of High-Performance Processor Cores—Quick Interconnects and the New I/O Hubs.” 

Memory Integrity also cites two Intel technical product specifications and two Intel Xeon 

Processor datasheets. 

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Memory Integrity provides the following quotations from Intel’s documents as evidence 

that the documents encourage use of the allegedly infringing technology: 

 Cache coherence snooping can be initiated by the caching agents that request data. This 

mechanism, called source snooping, is best suited to small systems that require the lowest 

latency to access the data in system memory. . . . High-performance, small-scale systems, 

such as workstations and computationally intensive desktop machines, tend to benefit 

from the low latency and high efficiency of the source snoop cache coherence 

mechanism. This variant of the snooping mechanism is designed to provide data to the 

processors with the lowest latency possible, as it requires the fewest number of hops 

across the links. A source snooping approach also takes advantage of the low latency of 

cache accesses to emphasize forwarding data from one processor to another, rather than 

getting the data from slower DRAM memory systems. This approach reduces latency by 

about 25% over comparably sized home snooped systems, producing a significant 

performance benefit. Id. ¶ 35. 

 [Intel Server Board S2600CP Family/Intel Server System P4000CP Family] supports 

both low-latency source snooping and a scalable home snoop behavior. The coherency 

protocol provides for direct cache-to-cache transfers for optimal latency. Id. ¶ 36. 

 [Intel Xeon Processor E5-1600/E5-2600/E5-4600 v2 Product Family] supports both lowlatency source snooping and a scalable home snoop behavior. The coherency protocol 

provides for direct cache-to-cache transfers for optimal latency. Id. ¶ 37. 

 In the snoopy variant of the protocol, each caching agent broadcasts snoop messages for 

each request to each peer snoopy caching agent. The peer agents send snoop responses to 

the home agent targeted by the original request. The home agent resolves the final data 

return, based on the snoop responses and the data fetched by the memory controller 

associated with the home agent. The source snoopy variant is also called as the two-hop 

protocol, as the snoop processing is performed in the shadow of memory/directory 

lookup. Id. ¶ 38. 

 The server board includes two Socket-R (LGA2011) processor sockets and can support 

up to two processors from Intel Xeon processor E5-2600 and E5-2600 v2 product family. 

Id. ¶ 39 [Memory Integrity asserts that this material supports use of accused processors in 

combination.]. 

C. The ’409 Patent 

The ’409 patent, entitled “Methods and Apparatus for Speculative Probing at a Request 

Cluster,” details the same mechanism as the ’636 patent. Dkt. 105-3 at 2, 18. The ’409 patent, 

however, involves “local probing” of a cluster of processors. Id. at 18. 

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Memory Integrity asserts that Intel actively induces customers to directly infringe the 

’409 patent by providing “product manuals, data sheets, presentations, instructions, and other 

materials that describe, promote, and encourage use of two or more [processors] in combination 

to snoop one or more local cores before sending the request to the appropriate home agent, such 

as by use of a Read-for-Ownership (‘RFO’) operation.” Dkt. 105 ¶ 48. In support of its assertion, 

Memory Integrity cites an Intel performance analysis guide, two Intel reference manuals, and 

two Intel product specifications. 

Memory Integrity provides the following quotations from Intel’s documents as evidence 

that the documents encourage use of the allegedly infringing technology: 

 [I]f the CBo fielding the core request indicates that a core within the socket owns the line 

(for a coherent read), the request is snooped to that local core. That same CBo will then 

snoop all peers which might have the address cached (other cores, remote sockets, etc) 

and send the request to the appropriate Home Agent for conflict checking, memory 

requests and writebacks. . . . [T]he CBo has performance monitoring events for tracking 

MESI state transitions that occur as a result of data sharing across sockets in a multisocket system. Id. ¶ 49. 

 The memory cluster of the Intel Core microarchitecture uses the following to speed up 

memory operations: . . . pipelined read-for-ownership operation (RFO). . . . In the Intel 

Xeon Processor E5 Family, . . . the uncore subsystem contains more components, 

including an LLC with larger capacity and snooping capabilities to support multiple 

processors. . . . When a write to a write-combining buffer for a previously-unwritten 

cache line occurs, there will be a read-for-ownership (RFO). If a subsequent write 

happens to another write-combining buffer, a separate RFO may be caused for that cache 

line. Subsequent writes to the first cache line and write-combining buffer will be delayed 

until the second RFO has been serviced to guarantee properly ordered visibility of the 

writes. Id. ¶ 50. 

 A cacheline can be put in an Exclusive state (E) in response to a ‘read for ownership’ 

(RFO) in order to store a value. All instructions containing a lock prefix will result in a 

(RFO) since they always result in a write to the cache line. Id. ¶ 51. 

 The Intel Xeon processor employs a use-once protocol to ensure that a processor in a 

multiprocessor system may access data that is loaded into its cache on a Read-forOwnership (RFO) operation at least once before it is snooped out by another processor. 

This protocol is necessary to avoid a dual processor livelock scenario where no processor 

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in the system can gain ownership of a line and modify it before that data is snooped out 

by another processor. Id. ¶ 52. 

 See supra text from Dkt. 105 ¶ 39. 

 

D. The ’206 Patent 

The ’206 patent, entitled “Transaction Processing Using Multiple Protocol Engines,” 

details “[a] multi-processor computer system . . . in which transaction processing in each cluster 

of processors is distributed among multiple protocol engines.” Dkt. 105-4 at 2. The protocol 

engines “include[] at least one remote protocol engine for processing transactions targeting 

remote memory and at least one local protocol engine for processing transactions targeting local 

memory.” Id. at 24. 

Memory Integrity asserts that Intel actively induces customers to directly infringe the 

’206 patent by providing “product manuals, data sheets, presentations, instructions, and other 

materials that describe, promote, and encourage use of two or more [processors] in combination, 

with each processor containing multiple instances of the C-Box (also referred to as a ‘Cache 

Box’) to process memory transactions via a proprietary hashing algorithm.” Dkt. 105 ¶ 62. In 

support of its assertion, Memory Integrity cites two Intel product manuals, a multi-volume 

datasheet for an Intel Xeon Processor, an Intel performance monitoring guide, a reference 

manual for Intel Xeon Processors, and an Intel product specification. 

Memory Integrity provides the following quotations from Intel’s documents as evidence 

that the documents encourage use of the allegedly infringing technology: 

 The Intel Xeon Processor 7500 Series contains eight instances of the C-Box, each 

assigned to manage a distinct 3MB, 24-way set associative slice of the processor’s total 

LLC capacity. . . . Every physical memory address in the system is uniquely associated 

with a single C-Box instance via a proprietary hashing algorithm that is designed to keep 

the distribution of traffic across the C-Box instances relatively uniform for a wide range 

of possible address patterns. This enables the individual C-Box instances to operate 

independently, each managing its slice of the physical address space without any C-Box 

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in a given socket ever needing to communicate with the other C-Boxes in that same 

socket. Id. ¶ 63. 

 The LLC consists of multiple cache slices. The number of slices is equal to the number of 

IA cores. Each slice has logic portion and data array portion. The logic portion handles 

data coherency, memory ordering, access to the data array portion, LLC misses and 

writeback to memory, and more. The data array portion stores cache lines. Each slice 

contains a full cache port that can supply 32 bytes/cycle. The physical addresses of data 

kept in the LLC data arrays are distributed among the cache slices by a hash function, 

such that addresses are uniformly distributed. . . . In the Intel Xeon Processor E5 

Family, . . . the uncore subsystem contains more components, including an LLC with 

larger capacity and snooping capabilities to support multiple processors. . . . Id. ¶ 64. 

 The Intel® Xeon® E7 v2 processor supports scalable server and HPC platforms of two or 

more processors, including ‘glueless’ 8-way platforms . . . . The processor last level 

cache comprises a 2.5 MB section for each core slice instantiated but together they 

represent one logical cache . . . . The Coherent requests are serviced by the Cbo that holds 

the LLC slice for the specified address, determined by the hashing function. Id. ¶ 65. 

 The uncore contains eight instances of the CBo, each assigned to manage a distint [sic] 

2.5MB slice of the processor’s total LLC capacity. . . . Every physical memory address in 

the system is uniquely associated with a single CBo instance via a proprietary hashing 

algorithm that is designed to keep the distribution of traffic across the CBo instances 

relatively uniform for a wide range of possible address patterns. This enables the 

individual CBo instances to operate independently, each managing its slice of the 

physical address space without any CBo in a given socket ever needing to communicate 

with the other CBos in that same socket. . . . [T]he C-Box has performance monitoring 

events for tracking MESI state transitions that occur as a result of data sharing across 

sockets in a multi-socket system. Id. ¶ 66 [Memory Integrity also includes another 

quotation almost identical to this quotation but regarding “the uncore of Intel Xeon 

Processors based on the Ivy Bridge-EP microarchitecture,” which “contains multiple 

instances of the CBo.” Id. ¶ 67]. 

 See supra text from Dkt. 105 ¶ 39. 

E. The ’254 Patent 

The ’254 patent, also entitled “Transaction Processing Using Multiple Protocol Engines,” 

is similar to the’206 patent. The ’254 patent details a multi-processor computer system with 

separate protocol engines for processing local and remote memory transactions. Dkt. 105-5 at 2, 

21. 

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Memory Integrity asserts that Intel actively induces customers to directly infringe the 

’254 patent by providing “product manuals, data sheets, presentations, instructions, and other 

materials that describe, promote, and encourage use of [processors] with each processor 

containing multiple instances of the C-Box (also referred to as a ‘Cache Box’) to process 

memory transactions via a proprietary hashing algorithm.” Dkt. 105 ¶ 77. In support of its 

assertion, Memory Integrity cites an Intel programming guide, two Intel reference manuals, a 

multivolume datasheet for an Intel Xeon Processor, and an Intel performance monitoring guide. 

To show that Intel’s documents encourage use of technology that infringes the ’254 

patent, Memory Integrity essentially provides the same quotations as those that it provides for 

the ’206 patent. See supra text from Dkt. 105 ¶¶ 63-66.2

DISCUSSION 

The patent laws provide that “[w]hoever actively induces infringement of a patent shall 

be liable as an infringer.” 35 U.S.C. § 271(b). “[A]ctive” inducement has three elements: 

knowledge of the patent; knowledge that the induced acts will infringe; and “intent to ‘bring 

about the desired result,’ which is infringement.” Commil USA, LLC v. Cisco Sys., Inc., 135 S. 

Ct. 1920, 1928 (2015) (quoting Global-Tech Appliances, Inc. v. SEB S.A., 131 S. Ct. 2060, 2065 

(2011)) (emphasis added); see also Microsoft Corp. v. DataTern, Inc., 755 F.3d 899, 904 (Fed. 

Cir. 2014) (“Absent the knowledge and affirmative act of encouragement, no party could be 

charged with inducement.”). 

 2

 In oral argument, Memory Integrity emphasized that the ’121 and ’254 patents cover a 

single processor by itself, whereas the ’636, ’409, and ’206 patents cover a combination of two 

or more processors connected to each other. The SAC contains allegations that Intel induces its 

customers to directly infringe the ’636 and ’409 patents by selling accused instrumentalities that 

“are designed to be combined together.” Dkt. 105 ¶¶ 40, 54. The SAC does not contain similar 

allegations for the ’121, ’254, or ’206 patents. 

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As discussed in the Court’s previous opinion (Dkt. 98), each requirement is separate and 

distinct.3

 Intel does not contest the first requirement, that Intel had knowledge of Memory 

Integrity’s patents. While not admitting the second requirement of knowledge that the induced 

acts would infringe, Intel devotes little discussion to directly contesting this requirement. Intel 

does, however, vigorously contest the final requirement of active inducement: specific intent. 

A. Requirements for Specific Intent 

Specific intent to encourage infringement “can be shown by circumstantial evidence, but 

the mere knowledge of possible infringement will not suffice.” Vita-Mix Corp. v. Basic Holding, 

Inc., 581 F.3d 1317, 1328 (Fed. Cir. 2009). Thus, that a product may be used in an infringing 

manner is not sufficient to establish intent. Id. at 1328-29. Nor is actual knowledge that some 

users of the product may be infringing the patent. Id. at 1329. Similarly, “ordinary acts incident 

to product distribution, such as offering customers technical support or product updates,” will not 

support inducement liability in themselves. Metro-Goldwyn-Mayer Studios Inc. v. Grokster, Ltd., 

545 U.S. 913, 937 (2005). On the other hand, instructions that “teach an infringing use” of the 

product may be sufficient to infer “an affirmative intent to infringe the patent.” Vita-Mix Corp., 

581 F.3d at 1329 n.2; see also Metro-Goldwyn-Maye Studios, 545 U.S. at 936 (“Evidence of 

 3

 In oral argument, Memory Integrity argued that the knowledge and specific intent 

requirements are not distinct. According to Memory Integrity, “specific intent” is simply another 

way to refer to the requirement that the accused infringer know that the induced acts constitute 

patent infringement. The Federal Circuit has, however, repeatedly discussed knowledge and 

specific intent as separate elements. See In re Bill of Lading Transmission & Processing Sys. 

Patent Litig., 681 F.3d 1323, 1339 (Fed. Cir. 2012) (“To survive [defendants’] motion to 

dismiss, therefore, [plaintiff’s] amended complaints must contain facts plausibly showing that 

[defendants] specifically intended their customers to infringe the [asserted] patent and knew that 

the customer’s acts constituted infringement.”) (emphasis added); DSU Med. Corp. v. JMS Co., 

471 F.3d 1293, 1306 (Fed. Cir. 2006) (“[T]he intent requirement for inducement requires more 

than just intent to cause the acts that produce direct infringement. Beyond that threshold 

knowledge, the inducer must have an affirmative intent to cause direct infringement.”) (emphasis 

added). 

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‘active steps . . . taken to encourage direct infringement,’ . . . such as advertising an infringing 

use or instructing how to engage in an infringing use, show an affirmative intent that the product 

be used to infringe. . . .”) (citation omitted); Toshiba Corp. v. Imation Corp., 681 F.3d 1358, 

1365 (Fed. Cir. 2012) (noting that in order to be liable for induced infringement, the defendant 

must “go beyond describing the infringing mode” and “recommend[] that customers use the 

infringing mode”). What the patentee must allege is “culpable conduct, directed to encouraging 

another’s infringement.” DSU Med. Corp. v. JMS Co., 471 F.3d 1293, 1306 (Fed. Cir. 2006). 

The specific intent element of induced infringement differentiates inducement liability 

from liability for both direct infringement and contributory infringement. In contrast to a claim 

of direct infringement, contributory and induced infringement claims require a showing of 

scienter. Id. at 1305. The knowledge required for contributory liability is similar to the 

knowledge required for inducement liability. See Global-Tech, 131 S. Ct. at 2067. Unlike 

induced infringement, however, contributory infringement does not have a specific-intent 

element. Unisone Strategic IP, Inc. v. Life Techs. Corp., 2013 WL 5729487, at *4 (S.D. Cal. 

Oct. 22, 2013). Contributory infringement instead contains a no-substantial-noninfringing-use 

element that is absent from the requirements of induced infringement. See Ricoh Co. v. Quanta 

Computer Inc., 550 F.3d 1325, 1340 (Fed. Cir. 2008). 

B. Inferences of Specific Intent 

Memory Integrity cites Bill of Lading in support of the argument that general statements 

in advertisements about the benefits of using a product establish an inference of specific intent to 

infringe. See In re Bill of Lading Transmission and Processing Sys.Patent Litig., 681 F.3d 1323, 

1344 (Fed. Cir. 2012). In Bill of Lading, the Federal Circuit noted that general statements about a 

product’s benefits could allow a court to infer specific intent to induce infringement “[w]hen 

viewed in the context of the invention.” Id. In that case, the patent in suit disclosed a method that 

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“improves asset utilization and efficiency” through in-cab scanning of bills of lading while 

trucks are en route. Id. at 1341. The documents cited by the plaintiff in support of its claim of 

induced infringement specifically advertised that the allegedly infringing product could be used 

“to perform in-cab scanning of critical proof of delivery (POD) and other driver documents” and 

that “mobile in-cab scanning . . . ‘reduce[s] costs and improve[s] efficiencies.’” Id. at 1341-42. 

The Federal Circuit found these advertisements sufficient to give rise to a reasonable inference of 

specific intent because the advertisements specifically “tout[ed] the ability of [the allegedly 

infringing] products” to perform the same functions as disclosed in the asserted patent. Id.

at 1341-43. 

Memory Integrity also cites Tranxition, a case from this district, as standing for the 

proposition that identifying advertising and instructions regarding allegedly infringing 

technology is legally adequate to plead specific intent. Tranxition, Inc. v. Novell, Inc., 2013 

WL 2318846, at *5 (D. Or. May 27, 2013). In Tranxition, the plaintiff asserted a patent entitled 

“Method and System for Automatically Transitioning [o]f Configuration Settings Among 

Computer Systems.” Id. at *1 (brackets in original). The patent concerned methods for 

“migrating a computer ‘personality’ (i.e., the custom settings, files, etc. that users set on their 

computer) to another computer.” Id. The defendant marketed software entitled “ZENWorks 

Personality Migration (or Migration Assistant).” Id. The defendant advertised its software as a 

“comprehensive solution for migration, replacement, and recovery of operating system settings, 

application settings, and data files, collectively known as DNA.” See id. at *5 n.2.4

 Based on 

 4

 The website referenced in footnote two of the Tranxition opinion appears at the 

following web address using the Internet Archive WayBack Machine: https://web.archive.org 

/web/20070120031501/http://www.novell.com/documentation /zenworks7/readme 

/readme_pm_7.html. 

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these allegations, the court found that the plaintiff had pled sufficient facts to give rise to a 

reasonable inference that the defendant specifically intended to induce infringement. Id. at *5. 

Where defendants have not touted the benefits of the accused products in ways that track 

the asserted patents, courts generally do not infer specific intent. The court in Unisone Strategic 

IP, for example, concluded that allegations that “merely indicate that Defendant provides 

instruction, technical support, and training for using its own software” do not allow a court to 

“infer that Defendant had the specific intent to induce others to infringe.” 2013 WL 5729487, 

at *3; see also Avocet Sports Tech., Inc. v. Garmin Int’l, Inc., 2012 WL 2343163, at *4 (N.D. 

Cal. June 5, 2012) (holding that allegations that the defendant “provided other parties with 

‘instruction’ and ‘training’ in the use of [the defendant’s] own products” did not constitute 

evidence of specific intent to encourage others to infringe). 

Conversely, the court in Enthone inferred specific intent where the defendant “facilitated 

and supported [its] customers’ infringing uses” by providing instructions that led the accused 

products to have “the specific attributes described and claimed in [the patents-in-suit].” Enthone 

Inc. v. BASF Corp., 2015 WL 5090015, at *4 (N.D.N.Y. Aug. 27, 2015) (internal quotation 

marks and citation omitted). The court in Unilin Beheer inferred specific intent where the 

defendant instructed its customers “on how to assemble and use the [accused] products.” Unilin 

Beheer B.V. v. Tropical Flooring, 2014 WL 2795360, at *5 (C.D. Cal. June 13, 2014). In Mobile 

Telecommunications the court held that “specifically advertising certain functionality and 

instructing users on how to use a certain functionality” supported an induced infringement claim. 

Mobile Telecomms. Techs., LLC v. Amazon.com, Inc., 2014 WL 10418271, at *1 (E.D. Tex. 

Aug. 26, 2014). Where the defendant provided instructions on how to perform a patented method 

and trained employees to assist customers in performing the patented method, the Nomadix court 

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also found that the plaintiff had pled sufficient facts to establish specific intent. Nomadix, Inc. v. 

Hospitality Core Servs. LLC, 2015 WL 1525537, at *3 (C.D. Cal. Apr. 3, 2015). 

Some courts have found that merely continuing to sell an allegedly infringing product 

after acquiring knowledge of a patent’s existence gives rise to an inference of specific intent at 

the pleading stage. See, e.g., Paone v. Broadcom Corp., 2015 WL 4988279, at *13 (E.D.N.Y. 

Aug. 19, 2015). These cases are, however, inconsistent with the Federal Circuit’s reasoning in 

Bill of Lading. In Bill of Lading, the Federal Circuit went far beyond considering whether the 

defendant continued to sell the allegedly infringing products after acquiring knowledge of the 

complaint; the court also considered the alleged facts “in the context of the technology disclosed 

in [the asserted patent] and the industry to which [the defendants] sell and tout their 

products.” 681 F.3d at 1340. As previously discussed, the Federal Circuit also considered the text 

of the defendant’s advertisements and product literature. Id. at 1341-43; see also Johnstech Int’l 

Corp. v. JF Tech. Berhad, 2015 WL 2062223, at *2 (N.D. Cal. May 1, 2015) (interpreting Bill of 

Lading as inferring specific intent only “where the defendant advertises or promotes its product 

for use in an infringing manner”). Although “there is no requirement that the facts alleged mimic 

the precise language used in a claim,” the Federal Circuit has emphasized that “what is necessary 

is that facts, when considered in their entirety and in context, lead to the common sense 

conclusion that a patented method is being practiced.” Bill of Lading, 681 F.3d at 1343. 

Conair Corp. v. Jarden Corp., cited by Memory Integrity, does not suggest an alternative 

understanding of Bill of Lading. 2014 WL 3955172, at *3 (S.D.N.Y. Aug. 12, 2014). There, the 

court considered the context in which an allegedly infringing milk container attachment was 

sold: “Given that coffee drinkers frequently enjoy milk with their coffee, it would be reasonable 

to infer that [the defendant] intended and expected its customers to use the milk container 

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PAGE 16 –OPINION AND ORDER 

attachment that it allegedly included in the coffee machines that it sold.” Id. The Conair Corp.

court did not hold that merely selling an accused product after acquiring knowledge of an 

asserted patent per se establishes specific intent; the court’s holding was context-specific. The 

context of that case was an allegedly infringing product sold alongside a non-infringing product, 

the latter of which purportedly induced customers to use the former. 

Factual Allegations in the SAC 

Here, Memory Integrity has added dozens of facts to the SAC. For each claim of induced 

infringement, Memory Integrity provides several examples of Intel’s instructions and technical 

support. Memory Integrity asserts that these documents describe functionality that could infringe 

a claim in the relevant patent. These specific facts cure some of the defects of Memory 

Integrity’s first amended complaint by providing factual support rather than conclusory legal 

statements to show that Intel induced infringement of the patents in suit. Nonetheless, the SAC 

does not contain facts supporting a reasonable inference that Intel specifically intended its 

customers to infringe Memory Integrity’s patents. 

The documents and quotations that Memory Integrity has identified do not so much 

“teach an infringing use” as identify and describe allegedly infringing functionality. That is, the 

quotations do not teach how to use Intel’s products to infringe Memory Integrity’s patents, but 

simply describe how Intel’s products work—and the products appear to work in a way that, 

according to Memory Integrity, infringes Memory Integrity’s patents. 

When a product can be used both in an infringing way and a non-infringing way, the 

allegation that its purveyor specifically teaches the infringing use is sufficient factual support for 

the element of specific intent. Vita-Mix, 581 F.3d at 1328. But the mere allegation that “a user 

following the instructions may end up using the device in an infringing way” is not sufficient 

factual support. Id. at 1329 n.2. If a product works in such a way that every normal use of it is 

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PAGE 17 –OPINION AND ORDER 

infringing, that is a sufficient allegation that the product has no substantial noninfringing use—

but no substantial noninfringing use is an element of contributory infringement. Indeed, that is 

the element of contributory infringement that, by replacing a specific intent to infringe, 

differentiates contributory from induced infringement. 

At this stage of the proceedings, Memory Integrity sufficiently alleges that the accused 

products have no substantial noninfringing use and that Intel’s customers used Intel’s products to 

infringe the patents in suit. Memory Integrity does not, however, sufficiently allege that Intel’s 

documents instruct Intel’s customers on how to engage in infringing uses that the customers 

would not otherwise engage in by simply buying the products. As in Unisone and Avocet, the 

factual allegations only establish that Intel described features of the company’s own products. 

The statements offered by Memory Integrity thus evince “ordinary acts incident to product 

distribution” rather than “purposeful, culpable expression and conduct.” Metro-Goldwyn-Mayer 

Studios Inc., 545 U.S. at 937. ). Memory Integrity’s factual allegations support its claims of 

direct and contributory infringement, but the allegations do not state a claim of induced 

infringement. 

To the extent Memory Integrity alleges that Intel induces infringement of method and 

apparatus patents by selling noninfringing products designed for infringing uses, Memory 

Integrity has still failed to state an inducement claim. Memory Integrity asserts that some of 

Intel’s products do not infringe on Memory Integrity’s patents until Intel’s customers use the 

products in combination. Memory Integrity does not, however, assert that Intel specifically 

instructs or recommends that customers combine Intel’s products. Memory Integrity simply cites 

one document that states that Intel’s server boards could support up to two processors. Much like 

the allegations found insufficient to support induced infringement in E-Pass Technologies, Inc. v. 

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3Com Corp, Memory Integrity points to product sales alongside documents that do no more than 

describe the functionality of the products. 473 F.3d 1213, 1221 (Fed. Cir. 2007). “Merely 

‘describ[ing],’ an infringing mode is not the same as ‘recommend[ing],’ ‘encourag[ing],’ or 

‘promot[ing],’ an infringing use, or suggesting that an infringing use ‘should’ be performed,” and 

thus descriptions of such modes fall short of induced infringement. Takeda Pharm. U.S.A., Inc. v. 

W.-Ward Pharm. Corp., 785 F.3d 625, 631 (Fed. Cir. 2015) (alterations in original) (citations 

omitted). Additionally, the Federal Circuit has rejected the argument that direct and indirect 

infringement can be found because a “natural and intuitive way to employ” a product is 

infringing. ACCO Brands Inc. v. ABA Locks Mfg., 501 F.3d 1307, 1312-13 (Fed. Cir. 2007). 

Intel’s sale of products that customers could use in an infringing manner—without distributing 

documents or taking other actions that encourage such use—does not support an inference that 

Intel specifically intended to induce infringement. 

The context of Intel’s advertisements differentiates them from the advertisements that 

allowed for inferences of specific intent in Bill of Lading and Tranxition. The advertised features 

and benefits of the products in Bill of Lading and Tranxition closely tracked the claimed features 

and benefits of the asserted patents. The asserted patent in Bill of Lading detailed an in-cab 

scanner that enabled more efficient route planning and shipment consolidation, and the literature 

concerning the allegedly infringing products specifically advertised in-cab scanners that enabled 

more efficient route planning and shipment consolidation. Moreover, in Bill of Lading, the 

defendants failed to identify any other way in which efficiency and improved asset utilization 

could be achieved other than through the patented method. 681 F.3d at 1341. Similarly, in 

Tranxition, the asserted patent detailed a method for migrating a computer’s “personality,” and 

the advertisements for the allegedly infringing technology touted a method for migrating a 

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computer’s “DNA.” Intel’s product literature, however, does not specifically tout “a probe 

filtering unit” for “reducing probe traffic,” a method or mechanism for “speculative probing,” or 

“transaction processing using multiple protocol engines.” The text of Intel’s documents contains 

no facial connection to the wording in the asserted patents. Intel also denies that an industry 

context exists in which cache coherency and improved processing speed can be achieved through 

no other methods other than those patented by Memory Integrity. Intel’s documents do not give 

rise to an inference of specific intent in the same way that the Bill of Lading and Tranxition

advertisements did. 

Moreover, Memory Integrity does not allege, as did the plaintiff in Enthone, that Intel 

“facilitated and supported [its] customers’ infringing uses” by providing instructions that led the 

accused products “to have ‘the specific attributes described and claimed in [the patents-in-suit].’” 

2015 WL 5090015, at *4. Nor does Memory Integrity allege facts similar to those in Unilin 

Beheer, Mobile Telecommunications, or Nomadix. The SAC does not contain factual allegations 

that Intel instructed its customers on assembling and using the accused products in an infringing 

manner or that Intel trained its employees to assist customers in performing a patented method. 

The facts of this case more closely resemble the facts in Straight Path than those of the 

cases cited by Memory Integrity. See Straight Path IP Grp., Inc. v. Vonage Holdings Corp., 2014 

WL 3345618 (D.N.J. July 7, 2014). In Straight Path, the court dismissed the plaintiff’s 

inducement claims with leave to amend, and the plaintiff amended its inducement claims with 

“over 350 additional paragraphs,” including multiple specific references to the defendant’s 

website purporting to describe the operation of the accused products. Id. at *2; see Dkt. 109-2 

¶¶ 38-53. According to the Straight Path court, although the plaintiff “alleged that Defendants 

induced their customers to infringe the Asserted Patents by instructing them how to use the 

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Accused Products,” the plaintiff failed to show “that Defendants specifically intended for the 

induced acts to infringe the Asserted Patents.” Straight Path, 2014 WL 3345618, at *2 (emphasis 

in original). The new allegations that Memory Integrity added in its SAC similarly fail to show 

that Intel intended for its customers to infringe the asserted patents. 

As Memory Integrity notes, “circumstantial evidence may suffice” to establish liability 

for induced infringement. DSU, 471 F.3d at 1306 (quoting Metro-Goldwyn-Mayer, 545 U.S. 

at 934). The circumstantial evidence, however, must still be “evidence of culpable conduct, 

directed to encouraging another’s infringement.” Id. Viewing the allegations in the SAC in the 

light most favorable to Memory Integrity, the Court finds those allegations do not constitute 

evidence—even circumstantial evidence—that Intel engaged in “culpable conduct” of 

specifically intending to promote or encourage infringement of the asserted patents. 

CONCLUSION 

Intel’s Motion for Partial Judgment on the Pleadings (Dkt. 108) is GRANTED. Memory 

Integrity has had more than a year to conduct discovery directed at uncovering factual support 

for its claims. Memory Integrity has also amended its complaint twice without curing the 

deficiencies in its induced infringement claims. Accordingly, the Court finds that leave to amend 

would be futile. See DeSoto v. Yellow Freight Sys., Inc., 957 F.2d 655, 658 (9th Cir. 1992) (“A 

district court does not err in denying leave to amend where the amendment would be futile.”). 

Memory Integrity’s induced infringement claims are DISMISSED with prejudice. 

IT IS SO ORDERED. 

DATED this 13th day of November, 2015. 

 /s/ Michael H. Simon 

Michael H. Simon 

 United States District Judge 

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