# Patent

## Title
Multi-level step-up converter topologies, control and soft start systems and methods

## Abstract

A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pair.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 14/212,062, filed on Mar. 14, 2014 which claims the benefit of U.S. Provisional Application No. 61/787,557, filed on Mar. 15, 2013. The entire disclosures of the applications referenced above are incorporated herein by reference.
This application is related to U.S. Pat. No. 9,608,512, issued on Mar. 28, 2017. The entire disclosure of the application referenced above is incorporated herein by reference.


FIELD
The present disclosure relates to step-up converters, and more particularly to multi-level step-up converters and soft start modules for multi-level step-up converters.
BACKGROUND
The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Handheld consumer electronics such as cell phones and smartphones typically require high-efficiency DC-DC power supplies. Some consumer electronics require an output voltage that is larger than the input voltage that is typically supplied by a battery. Large voltage step-up ratios typically require specialized high-voltage transistor devices and large magnetic components such as inductors that determine the total volume, efficiency and cost of the power supply.
Referring now to FIGS. 1A and 1B, a step-up converter 10 according to the prior art is shown. The step-up converter 10 includes a voltage supply VIN that is connected to one end of an inductor L. First and second transistors QSR and QMS each include a control terminal and first and second terminals. The second terminal of the transistor QSR is connected to a node LX. The node LX is also connected to another end of the inductor L and to a first terminal of the transistor QMS.
The first terminal of transistor QSR is connected to an output capacitor COUT and to a load. A voltage output VOUT of the step-up converter 10 is provided at the first terminal of the transistor QSR. The step-up converter 10 operates at a duty cycle D and a period T.
In FIG. 1B, voltage is shown as a function of time at the node LX and across the transistor QMS. As can be appreciated, the voltage swing on the inductor L during operation is VOUT. Large voltage step-up ratios typically require specialized high-voltage laterally diffused MOS (LDMOS) devices. The large inductor L substantially determines the total volume, efficiency and cost of the step-up converter 10. In particular, the large size of the inductor has up to now made it commercially impractical to co-integrate the inductor with the MOS switch devices.
In FIG. 1C, a multi-level step-down converter 50 includes a voltage source VIN and transistors QMS1, QMS2, QSR1 and QSR2. The voltage source VIN is connected to a first terminal of the transistor QMS2. A first terminal of the transistor QMS2 and a second terminal of the transistor QMS1 are connected to one end of the capacitor Cfly. A second terminal of the transistor QMS1 and a first terminal of the transistor QSR1 are connected to a node LX and to one end of an inductor L. A second terminal of the transistor QSR1 and a first terminal of the transistor QSR2 are connected to another end of the capacitor Cfly. Another end of the inductor L is connected to a capacitor COUT and to a load.
Multi-level step-down converters shown in FIG. 1C have been used in high voltage (1-5 kV) applications. Switches used in the converters are rated to withstand approximately half of a maximum input voltage. However, other multi-level step-down converter topologies are typically used at lower voltages. The topology in FIG. 1C encounters problems during start-up when the switches QSR1 and QMS2 need to withstand the full input voltage due to 0V across the capacitor Cfly, which is initially uncharged. During normal operation, voltage transients at the input are immediately passed through to an Nth switch pair, which necessitates additional voltage over-rating. In practice, the low side switch QSRN requires a 2× voltage over-rating, and the high side switch QMS2 requires an N times voltage over-rating, where N is equal to the number of series-connected transistor pairs or stages and is an integer greater than one.
SUMMARY
A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pairs.
In other features, a control module is configured to control states of the N transistor pairs. The control module is configured to charge the (N−1) capacitors to predetermined levels prior to converter operation. The control module controls the states of the N transistor pairs based in part on a duty cycle D and period T. When operating in a continuous current switching mode with a duty cycle that is less than 50%, the control module is configured to control the states of the first, second, third and fourth transistors, at least one of sequentially and non-sequentially, in a first switching mode in which the first and third transistors are closed and the second and fourth transistors are open; a second switching mode in which the first and third transistors are closed and the second and fourth transistors are open; a third switching mode in which the first and fourth transistors are closed and the second and third transistors are open; and a fourth switching mode in which the first and third transistors are closed and the second and fourth transistors are open.
In other features, when operating in a continuous current switching mode with a duty cycle that is less than 50%, the control module is configured to operate, at least one of sequentially and non-sequentially, in first, second, third and fourth switching modes. During the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load. During the second switching mode, current is supplied by the inductor to the load. During the third switching mode, at least one of the (N−1) capacitors is charged. During the fourth switching mode, current is supplied by the inductor to the load.
In other features, the control module is configured to transition from the first switching mode to the second switching mode at D*T; from the second switching mode to a third switching mode at T/2; from the third switching mode to the fourth switching mode at (1⁄2+D)*T; and from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.
In other features, when operating in a continuous current switching mode with a duty cycle that is greater than 50%, the control module is configured to control the states of the first, second, third and fourth transistors, at least one of sequentially and non-sequentially, in a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed; a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open; a third switching mode in which the first and third transistors are open and the second and fourth transistors are closed; and a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open.
In other features, when operating in a continuous current switching mode with a duty cycle that is greater than 50%, the control module is configured to operate, at least one of sequentially and non-sequentially, in first, second, third and fourth switching modes. During the first and third switching mode, current flows to ground. During the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load. During the fourth switching mode, at least one of the (N−1) capacitors is charged.
In other features, the control module transitions from the first switching mode to the second switching mode at (D−1⁄2)*T; from the second switching mode to the third switching mode at T/2; from the third switching mode to the fourth switching mode at D*T; and from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.
In other features, when operating in a discontinuous current switching mode with VOUT/VIN that is less than 50%, the control module controls the states of the first, second, third and fourth transistors, at least one of sequentially and non-sequentially, in a first switching mode in which the second and third transistors are closed and the first and fourth transistors are open; a second switching mode in which the first and third transistors are closed and the second and fourth transistors are open; a third switching mode in which the second, third and fourth transistors are open and the first transistor is open; a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open; a fifth switching mode in which the first and third transistors are closed and the second and fourth transistors are open; and a sixth switching mode in which the first, second and fourth transistors are open and the third transistor is open.
In other features, when operating in a discontinuous current switching mode with VOUT/VIN that is less than 50%, the control module operates, at least one of sequentially and non-sequentially, in a first switching mode, a second switching mode, a third switching mode, a fourth switching mode, a fifth switching mode and a sixth switching mode. During the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load. During the second switching mode, current is supplied by the inductor to the load. During the third switching mode, current is not supplied to the load or the (N−1) capacitors. During the fourth switching mode, at least one of the (N−1) capacitors is charged. During the fifth switching mode, current is supplied by the inductor to the load. During the sixth switching mode, current is not supplied to the load or the (N−1) capacitors.
In other features, the control module is configured to transition from the first switching mode to the second switching mode when current is equal to a predetermined current; from the second switching mode to the third switching mode when current is zero; from the third switching mode to the fourth switching mode at T/2; from the fourth switching mode to the fifth switching mode when current is equal to a predetermined current; from the fifth switching mode to the sixth switching mode when current is zero; and from the sixth switching mode to the first switching mode at T, where T is a period and D is a duty cycle.
In other features, when operating in a discontinuous current switching mode with VOUT/VIN that is greater than 50%, the control module is configured to control the states of the first, second, third and fourth transistors, at least one of sequentially and non-sequentially, in a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed; a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open; a third switching mode in which the first, third and fourth transistors are open and the second transistor is closed; a fourth switching mode in which the first and third transistors are open and the second and fourth transistors are closed; a fifth switching mode in which the first and fourth transistors are closed and the second and third transistors are open; and a sixth switching mode in which the first, second and third transistors are open and the fourth transistor is closed.
In other features, when operating in a discontinuous current switching mode with VOUT/VIN that is greater than 50%, the control module is configured to operate, at least one of sequentially and non-sequentially, in a first switching mode, a second switching mode, a third switching mode and a fourth switching mode. During the first and fourth switching modes, current flows to ground. During the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load. During the fifth switching mode, at least one of the (N−1) capacitors is charged. During the third and sixth switching modes, current is not supplied to the load or the (N−1) capacitors.
In other features, the control module is configured to transition from the first switching mode to the second switching mode when current is equal to a predetermined current; from the second switching mode to the third switching mode when current is zero; from the third switching mode to the fourth switching mode T/2; from the fourth switching mode to the fifth switching mode when current is equal to the predetermined current; from the fifth switching mode to the sixth switching mode when current is zero; and from the sixth switching mode to the first switching mode at T, where T is a period and D is a duty cycle.
In other features, a current sensor communicates with the control module and is configured to sense current supplied by the inductor. The control module transitions between switching modes of the N transistor pairs based on a duty cycle, a period and current supplied by the inductor current. The control module transitions between switching modes of the N transistor pairs based on inductor current at least one of exceeding a current limit and being equal to zero.
In other features, a soft start module is configured to charge the (N−1) capacitors ratiometrically before converter operation. A soft start module is configured to charge the (N−1) capacitors to voltages that are ratios of an output voltage. The ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.
In other features, a soft start module is configured to sequentially charge the first one of the (N−1) capacitors to 1/N of an output voltage; charge a second one of the (N−1) capacitors to 2/N of the output voltage; and charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.
In other features, the soft start module is configured to initially charge the (N−1) capacitors to the input voltage before charging the (N−1) capacitors to predetermined values. A soft start module is configured to sequentially charge the (N−1) capacitors to (N−1) fractions of an output voltage, respectively, before converter operation. A soft start module includes a driver module configured to generate a first signal when the N transistor pairs are ready to switch; a first charging circuit configured to charge the (N−1) capacitors to the input voltage and to generate a second signal; and a second charging circuit configured to sequentially charge the (N−1) capacitors to (N−1) fractions of an output voltage, respectively, in response to the first signal and the second signal being generated.
In other features, the second charging circuit charges an (N−1)th one of the (N−1) capacitors to (N−1)/N of an output voltage.
A system comprises P multi-level, step-up converter circuits, where P is an integer greater than one, and a control module configured to control states of the P multi-level, step-up converter circuits.
A system comprises P multi-level, step-up converters. Inductor nodes for the P multi-level, step-up converters and an output capacitor node for the P multi-level, step-up converters are in communication, respectively. A control module is configured to control states of the multi-level, step-up converter and the second multi-level, step-up converter. In other features, the inductor of the P multi-level, step-up converters are magnetically coupled by a magnetic component. The magnetic component and one or more of the N transistor pairs are integrated on a single substrate.
In other features, the inductor current is sensed as a voltage across one or more of the N transistor pairs. One or more of the N transistor pairs are integrated on a single substrate. One or more of the N−1 capacitors connected between the N transistor pairs are integrated on a single substrate. One or more of the N−1 capacitors and one or more of the N transistor pairs are integrated on a single substrate. The inductor and one or more of the N transistor pairs are integrated on a single substrate.
In other features, the inductor, N−1 capacitors, and N transistor pairs are integrated to create a monolithic converter system.
In other features, the control module controls the states of the N transistor pairs using at least one of fixed-frequency duty cycle modulation using voltage mode control, peak current mode control, average current mode control, valley current mode control, constant on-time, constant off-time, output voltage, inductor current hysteretic, pulse frequency modulation (PFM) or pulse density modulation.
In other features, the period T is modified in response to a sensed output current. The period T is modified in response to a programmed output current. The period T is derived from an external clock signal. The voltages across the (N−1) capacitors are sensed and duty cycles DN of the N transistor pairs are modified to maintain predetermined voltage ratios on the (N−1) capacitors.
A control circuit for a step-up converter includes a soft start module configured to control states of N transistor pairs of the step-up converter, where N is an integer greater than two. A driver module is in communication with the soft start module and is configured to generate a first signal when N transistor pairs of the step-up converter are ready to switch. A first charging circuit is configured to charge (N−1) capacitors of the step-up converter to an input voltage of the step-up converter in response to the first signal and to generate a second signal when charging is complete. A second charging circuit is configured to sequentially charge the (N−1) capacitors of the step-up converter to (N−1) predetermined voltage values in response to the first signal and the second signal and before operation of the step-up converter begins.
In other features, the (N−1) predetermined voltage values correspond to (N−1) fractions, respectively, of an output voltage of the step-up converter. The second charging circuit is configured to charge the (N−1) capacitors ratiometrically before operation of the step-up converter. The second charging circuit is configured to charge the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter. The ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.
In other features, the second charging circuit is configured to sequentially charge the first one of the (N−1) capacitors to 1/N of an output voltage of the step-up converter; charge a second one of the (N−1) capacitors to 2/N of the output voltage of the step-up converter; and charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage of the step-up converter.
In other features, the second charging circuit is configured to sequentially charge the (N−1) capacitors to (N−1) fractions of the output voltage, respectively, before operation. The second charging circuit charges an (N−1)th one of the (N−1) capacitors to (N−1)/N of an output voltage of the step-up converter. The first charging circuit includes a current charging circuit that pulls terminals of the (N−1) capacitors low.
A system comprises the control circuit and the step-up converter. The step-up converter comprises an inductor including one end in communication with an input voltage supply and the N transistor pairs where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together and communicate with the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. The (N−1) capacitors are connected between the N transistor pairs, respectively. An output capacitor is in communication with at least one transistor of the N transistor pairs. A control module controls states of the N transistor pairs during operation of the step-up converter.
A step-up converter circuit includes an inductor including one end in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the Nth transistor pair. A control module initiates converter operation after the (N−1) capacitors are charged to (N−1) predetermined voltage values and controls states of the N transistor pairs during converter operation.
In other features, a soft start module is configured to charge the (N−1) capacitors to the (N−1) predetermined voltage values. The (N−1) predetermined voltage values correspond to (N−1) predetermined ratios of an output voltage of the step-up converter. The (N−1) predetermined ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors. A soft start module is configured to sequentially charge a first one of the (N−1) capacitors to 1/N of an output voltage of the step-up converter; charge a second one of the (N−1) capacitors to 2/N of the output voltage of the step-up converter; and charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage of the step-up converter.
In other features, a first charging circuit is configured to initially charge the (N−1) capacitors to the input voltage before charging to the (N−1) predetermined voltage values. A start-up circuit includes a soft start module configured to control states of the N transistor pairs. A driver module is in communication with the soft start module and is configured to generate a first signal when N transistor pairs of the step-up converter are ready to switch. A first charging circuit is configured to charge the (N−1) capacitors to an input voltage of the step-up converter and to generate a second signal when charging is complete. A second charging circuit is configured to sequentially charge the (N−1) capacitors to the (N−1) predetermined voltage values in response to the first signal and the second signal being generated and before operation of the step-up converter begins.
A circuit comprises a step-up converter including N stages and (N−1) capacitors, where N is an integer greater than one. A start-up module is configured to charge the (N−1) capacitors to (N−1) predetermined voltage values corresponding to (N−1) predetermined ratios of an output voltage of the step-up converter. A control module is configured to initiate converter operation after the (N−1) capacitors are charged to (N−1) predetermined voltage values and to control the N stages during converter operation.
In other features, the step-up converter comprises an inductor including one end in communication with an input voltage. The N stages comprise N transistor pairs. First and second transistors of a first pair of the N transistor pairs are connected together and communicate with the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. The (N−1) capacitors are connected between the N transistor pairs, respectively. An output capacitor is in communication with at least one transistor of the N transistor pairs.
In other features, the (N−1) predetermined ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors. The start-up module is configured to sequentially charge a first one of the (N−1) capacitors to 1/N of an output voltage of the step-up converter; charge a second one of the (N−1) capacitors to 2/N of the output voltage of the step-up converter; and charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage of the step-up converter.
In other features, a first charging circuit is configured to initially charge the (N−1) capacitors to an input voltage to the step-up converter before charging to the (N−1) predetermined voltage values. The start-up module includes a soft start module configured to control states of the N transistor pairs. A driver module is in communication with the soft start module and configured to generate a first signal when N transistor pairs of the step-up converter are ready to switch. A first charging circuit is configured to charge the (N−1) capacitors to an input voltage of the step-up converter and to generate a second signal when charging is complete. A second charging circuit is configured to sequentially charge the (N−1) capacitors to the (N−1) predetermined voltage values in response to the first signal and the second signal and before operation of the step-up converter begins.
Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.



BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
FIG. 1A is electrical schematic of a step-up converter according to the prior art;
FIG. 1B is a waveform diagram illustrating operation of the step-up converter of FIG. 1A according to the prior art;
FIG. 1C is electrical schematic of an example multi-level buck converter according to the prior art;
FIG. 2 is electrical schematic of an example multi-level step-up converter according to the present disclosure;
FIG. 3A is a waveform diagram illustrating operation of the example step-up converter of FIG. 2 operating in a continuous conduction mode with a duty cycle less than 50%;
FIG. 3B illustrates current flow and switch positions during a period for FIG. 3A;
FIG. 4A is a waveform diagram illustrating operation of the example step-up converter of FIG. 2 in a continuous conduction mode with a duty cycle greater than 50%;
FIG. 4B illustrates current flow and switch positions during a period for FIG. 4A;
FIG. 5A illustrates waveforms showing voltage at the node LX, inductor current and voltage across switches of the step-up converter of FIG. 2 during a discontinuous conduction mode with VOUT/VIN less than 50%;
FIG. 5B illustrates current flow and switch positions during a period for FIG. 5A;
FIG. 6A illustrates waveforms showing voltage at the node LX, inductor current and voltage across switches of the step-up converter of FIG. 2 according to the present disclosure during a discontinuous conduction mode with VOUT/VIN greater than 50%;
FIG. 6B illustrates current flow and switch positions during a period for FIG. 6A;
FIG. 7A is an example of a multi-level step-up converter including additional stages;
FIGS. 7B-7C show systems including multiple multi-level step-up converters connected to multiple inductors;
FIG. 8 is an electrical schematic of another example multi-level step-up converter according to the present disclosure;
FIG. 9 is a functional block diagram and electrical schematic of an example of a softstart circuit for a multi-level step-up converter according to the present disclosure;
FIG. 10 illustrates an example of a softstart state machine for the step-up converter of FIG. 9; and
FIGS. 11-13 illustrate various examples of control signals and component signals for the step-up converter illustrated in FIGS. 9 and 10.



In the drawings, reference numbers may be reused to identify similar and/or identical elements.
DETAILED DESCRIPTION
Multi-level step-up converters according to the present disclosure employ a network of switches and capacitors to modify a voltage waveform across a magnetic component such as an inductor. Multi-level step-up converters according to the present disclosure cut the voltage swing and decrease a period of the voltage waveform by a factor of N, where N is equal to the number of transistor pairs or stages and is an integer greater than one.
Multi-level step-up converters described herein decrease the volt-seconds applied to the magnetic component by a factor on the order of N2, which decreases the value of the inductor and the magnetic energy storage requirement of the inductor. This decrease allows improvement of power loss in the inductor and case size reduction. The network of switches and capacitors does not increase the power loss in the switches, due to the reduced switch voltage ratings allowed by the series switch connections. Switches with reduced voltage ratings typically exhibit superior performance, as measured by resistance per unit area and resistance per switching energy. Furthermore, in contrast to switched-capacitor circuits, it will be shown that certain preferred switch commutation patterns incur no loss due to charge equalization, and are insensitive to the finite values of the capacitances.
Referring now to FIG. 2, an example of a multi-level step-up converter 100 is shown. The multi-level step-up converter 100 has N=2 stages. The multi-level step-up converter 100 includes a voltage supply VIN that is connected to one end of an inductor L. A first pair of transistors QSR1 and QMS1 includes a control terminal and first and second terminals. The second terminal of the transistor QSR1 is connected to a node LX. The node LX is also connected to another end of the inductor L and to a first terminal of the transistor QMS1.
A second pair of transistors QSR2 and QMS2 include a control terminal and first and second terminals. A second terminal of the transistor QSR2 is connected to a first terminal of the first transistor QSR1. A second terminal of the transistor QMS1 is connected to a first terminal of the transistor QMS2.
The first terminal of transistor QSR2 is connected to an output capacitor CO. A voltage output VOUT of the multi-level step-up converter 100 is taken at the first terminal of the transistor QSR2. One end of a capacitor Cfly is connected between the second terminal of QSR2 and the first terminal of QSR1. Another end of the capacitor Cfly is connected between the second terminal of QMS1 and to a first terminal of the transistor QMS2.
The multi-level step-up topology described in the present disclosure, when operated using a start-up sequence, exhibits no voltage over-stress during start-up, which allows the use of optimally rated switches. Furthermore, because the inductor is placed at the input of the converter, input over-voltage transients during normal operation are isolated from the switches and also do not require any switch voltage over-rating.
Compared to FIG. 1A, the multi-level step-up topology described in the present disclosure also greatly reduces the impact of right-half-plane zero control challenges posed by the traditional boost topology. Specifically, because the practical implementation of the multi-level step-up converter enables a reduction in inductor value by a factor of approximately N to N2, the closed loop bandwidth can be increased without degrading phase margin and stability. This benefit applies only to step-up converters but not step-down converters, which do not exhibit a right half plane zero in the power stage transfer function.
The family of topologies described in the present disclosure is particularly suited for power conversion applications, where the switch voltage rating is small compared to the application voltages. This is especially advantageous in integrated applications, where the switch voltage ratings available in modern digital processes are limited to a few volts. For example only, a step-up converter achieving 15V output can be realized in a standard 180 nm CMOS process using only 3.3V logic devices, using an N=5 configuration. Such a large number of stages are more practical in integrated manufacturing, where the switches and level shifts and control can all be integrated on a single substrate.
Additional size reductions are possible with the present disclosure when the passive components are integrated. Recent advances in trench capacitor technology and fabrication make the integration of the flying capacitors practical, eliminating the extra interconnect pins and enabling much larger numbers of stages N. Finally, emerging integrated inductor technologies with limited energy storage densities benefit from the substantial decreases in inductor value enabled by the present disclosure, making fully integrated step-up converters possible for the first time.
Referring now to FIGS. 3A-3B, operation in a continuous conduction mode (CCM) with a duty cycle less than 50% is shown. Switching takes place at 0, D*T, T/2, and (1⁄2+D)*T and then repeats at T, where T is the period. Voltage at the node LX swings between VOUT and VOUT/2.
During a first switching mode, the transistors QSR2 and QMS1 are closed and the transistors QSR1 and QMS2 are open. Current is supplied to the load by the capacitor Cfly as shown, which allows the inductor current IL to rise during the first switching mode. During a second switching mode, the transistors QSR1 and QSR2 are closed and the transistors QMS1 and QMS2 are open. Load current is supplied by the inductor L. During a third switching mode, the transistors QSR1 and QMS2 are closed and the transistors QMS1 and QSR2 are open. The inductor L charges the capacitor Cfly. During a fourth switching mode, the transistors QSR1 and QSR2 are closed and the transistors QMS1 and QMS2 are open. The inductor L supplies current to the load. As can be appreciated, the switching modes may be sequential as shown in FIG. 3B or non-sequential.
Referring now to FIGS. 4A-4B, operation in the CCM with a duty cycle greater than 50% is shown. Switching takes place at 0, (D−1⁄2)*T, T/2, and D*T and then repeats at T, where T is the period. Voltage at the node LX swings between VOUT/2 and 0.
During a first switching mode, the transistors QMS1 and QMS2 are closed and the transistors QSR1 and QSR2 are open. Inductor current IL rises during the first switching mode. During a second switching mode, the transistors QMS1 and QSR2 are closed and the transistors QSR1 and QMS2 are open. Load current is supplied by the capacitor Cfly. During a third switching mode, the transistors QMS1 and QMS2 are closed and the transistors QSR1 and QSR2 are open. Inductor current IL rises during the third switching mode. During a fourth switching mode, the transistors QSR1 and QMS2 are closed and the transistors QMS1 and QSR2 are open. The inductor L charges the capacitor Cfly. As can be appreciated, the switching modes may be sequential as shown in FIG. 4B or non-sequential.
Referring now to FIGS. 5A and 5B, operation of the step-up converter in a discontinuous mode (DCM) with duty cycle or VOUT/VIN<50% is shown. During a first switching mode, the transistors QSR2 and QMS1 are closed and the transistors QSR1 and QMS2 are open. Current is supplied to the load by the capacitor Cfly as shown, which allows the inductor current IL to rise during the first switching mode. During a second switching mode, the transistors QSR1 and QSR2 are closed and the transistors QMS1 and QMS2 are open. Load current is supplied by the inductor L. During a third switching mode, the transistor QSR1 is closed and the remaining transistors are open. Current is not supplied to the load and the node LX is at VIN.
During a fourth switching mode, the transistors QSR1 and QMS2 are closed and the transistors QMS1 and QSR2 are open. The inductor L charges the capacitor Cfly. During a fifth period, the transistors QSR1 and QSR2 are closed and the transistors QMS1 and QMS2 are open. The inductor L supplies current to the load. During a sixth period, the transistor QSR2 is closed and the remaining transistors are open. Current is not supplied to the load and the node LX is at VIN. As can be appreciated, the switching modes may be sequential as shown in FIG. 5B or non-sequential.
Referring now to FIGS. 6A and 6B, operation of the step-up converter in the DCM with duty cycle or VOUT/VIN>50% is shown. During a first switching mode, the transistors QMS1 and QMS2 are closed and the transistors QSR1 and QSR2 are open. Inductor current IL rises during the first switching mode. During a second switching mode, the transistors QMS1 and QSR2 are closed and the transistors QSR1 and QMS2 are open. Load current is supplied by the capacitor Cfly. During a third switching mode, the transistor QMS1 is closed and the remaining transistors are open. Current is not supplied to the load and the node LX is at VIN.
During a fourth switching mode, the transistors QMS1 and QMS2 are closed and the transistors QSR1 and QSR2 are open. Inductor current IL rises during the first switching mode. During a fifth period, the transistors QSR1 and QMS2 are closed and the transistors QMS1 and QSR2 are open. The inductor L charges the capacitor Cfly. During a sixth period, the transistor QMS2 is closed and the remaining transistors are open. Current is not supplied to the load and the node LX is at VIN. As can be appreciated, the switching modes may be sequential as shown in FIG. 6B or non-sequential.
Referring now to FIG. 7A, an example of a multi-level step-up converter 150 includes a control module 152 to control switching. One or more additional capacitors Cfly and transistor pairs QSR and QMR and may be added. For example in FIG. 7A, an N-stage step-up converter with N=4 is shown. A pair of transistors QSR3 and QMS3 and a capacitor Cfly2 are connected in a similar manner. Another pair of transistors QSR4 and QMS4 and a capacitor Cfly3 are connected in a similar manner. The multi-level step-up converter 150 can be extended to arbitrary number of nested stages. Each additional stage uses low voltage (VOUT/N rated) devices, increases effective frequency without increasing switching losses, and reduces voltage ripple applied to the inductor.
Referring now to FIGS. 7B-7C, systems including first and second step-up converters connected to multiple inductors are shown. In FIG. 7B, a system 170 includes a control module 172 that generates switching signals for P multi-level step-up converters 174-1, . . . , and 174-P that are connected to inductors L1, . . . and LP, respectively, where P is an integer greater than one. Switching sequences created by the control module 172 are analogous to standard multi-phase converters with a phase count of N*P. In FIG. 7C, a system 180 includes a control module 182 that generates switching signals for P multi-level step-up converters 184-1, . . . , and 184-P that are connected to coupled inductor magnetic structure. The coupled inductor magnetic structure may include P windings on a single core, or a multiplicity of magnetic elements such as coupled inductors, transformers and inductors interconnected with each other. Switching sequences created by the control module 182 are analogous to standard multi-phase converters with a phase count of N*P.
The multi-level step-up converter reduces circuit area and passive component profiles, increases converter efficiency and prolongs the run time of battery-powered products. The multi-level step-up converter can be used for large voltage step-up ratios. Example applications include light emitting diodes (WLED) drivers in smart-phones and tablet.
For example only, the multi-level step-up converter may be used to drive a string of light emitting diodes. The multi-level step-up converter includes multiple flying capacitors Cfly and an output capacitor Cout. In the multi-level step-up converter topology, the capacitors Cfly are balanced at predetermined ratios of the output voltage. If this is ignored during startup, there can be large current spikes and the capacitors Cfly may never come into balance. As a result, switches must be chosen to handle relatively large voltage swings.
Referring now to FIG. 8, another example of a multi-level step-up converter 200 is shown to include a control module 212. An oscillator 216 may provide an oscillator signal at a predetermined frequency to the control module 212. The control module 212 may generate clock signals, delayed clock signals, ramp signals, etc. as needed for control based on the oscillator signal. The oscillator frequency may be adjusted or divided in response to the sensed load current, the programmed output voltage or current, or it may be synchronized to an external clock signal.
A load range module 222 may provide a load range signal to a lookup table or other device. The load range signal may be used to specify or determine operating parameters of the multi-level step-up converter. The lookup table (LUT) 226 uses the load range signal to access the lookup table and to provide one or more control parameters to the control module or other circuits. Examples of the control parameters include switching period T, duty cycle D, etc. In some examples, the LUT 226 divides the OSC frequency and outputs T.
A current sensor 228 may be used to determine current through the inductor such as the inductor L. The control module 212 may compare the actual current through the inductor to zero or predetermined non-zero current limits. The control module 212 controls switching of the N transistor pairs.
The control module 212 may incorporate any of the standard control algorithms that are compatible with multi-phase converters. Such algorithms include fixed-frequency duty cycle modulation (voltage mode control), peak or average or valley current mode control, constant on-time or constant off-time, output voltage or inductor current hysteretic, pulse frequency modulation (PFM) or pulse density modulation (PDM). Additionally, light load efficiency techniques such as skip mode and diode emulation may be used.
The control module 212 may also modulate the duty cycles D1 to DN of the N transistor pairs to maintain the desired voltages across the (N−1) capacitors. For example, by way of illustration, in the FIG. 3B, under steady-state operation the voltage on the capacitor Cfly is nominally VOUT/2. This voltage is maintained by balancing the duration of the charge phase (3) and the discharge phase (1). By sensing the capacitor voltage at a convenient time, for example during phase (3) when the capacitor voltage is ground-referenced, and comparing it to VOUT/2, the control module 212 can identify whether the capacitor voltage needs to increase or decrease. During subsequent cycles, the duration of phases (1) and (3) can be skewed by the control module 212 to move the capacitor voltage in the desired direction.
A level shifter 230 generates a level shifted signal based on the output current or voltage. A feedback circuit 234 receives a reference signal such as a target voltage VOUT signal and generates a feedback value based on the level shifted current or voltage. The feedback circuit 234 generates a voltage reference and compares the voltage reference to the output of the level shifter 230. In some examples, the feedback circuit 234 includes a resistive divider to generate an error signal with respect to the target VOUT. In other words, the feedback circuit 234 determines the error signal to be minimized by the system.
A compensator 238 compensates the multi-level step-up converter dynamic response. In some examples, the compensator 238 includes a linear or non-linear filter. The compensator 238 ensures system stability. The compensator 238 ensures that system response to changes to the input voltage MN or the load lOUT is within predetermined specifications.
The LUT 226 may also be used to control one or more parameters of the compensator 238. The LUT 226 may also output parameters to the control module to tune the system to lOUT corresponding to the load range output of the load range module 222. For example, a customer may set the desired lOUT using the load range module 222. In some examples, the load range module 222 may include a dimmer.
In the following description, a circuit layout for a soft start module according to the present disclosure will be provided initially followed by an operational description. FIG. 9 shows a soft start module 610 for a multi-level, step-up converter 611. A battery 612 is connected to one end of an inductor L1. Another end of the inductor L1 is connected to first terminals of switches S1 and S5. Second terminals of switches S1 and S5 are connected to first terminals of switches S2 and S6, respectively. A first flying capacitor Cfly1 is connected to the second terminals of switches S1 and S5.
Second terminals of switches S2 and S6 are connected to first terminals of switches S3 and S7, respectively. A second flying capacitor Cfly2 is connected to the second terminals of switches S2 and S6.
Second terminals of switches S3 and S7 are connected to first terminals of switches S4 and S8, respectively. A third flying capacitor Cfly3 is connected to the second terminals of switches S3 and S7. An output capacitor Cout is connected to the second terminals of the switches S4 and S8.
While diodes D1 to D4 are shown, these diodes are parasitic diodes that are associated with switches S5 to S8, respectively. The diodes D1 to D4 are shown connected across the switches S5 to S8. A load such as a light emitting diode (LED) string 614 includes two or more LEDs (connected together in series or parallel or combinations thereof) and is connected in series to a current source 11. The LED string 614 and the current source 11 are connected in parallel with the output capacitor Gout.
A node between the LED string 614 and the current source 11 generates an LED1S signal that is connected to a non-inverting input of a comparator 616. An inverting input of the comparator 616 receives a reference potential such as 150 mV. An output of the comparator 616 is input to a set input of an SR flip-flop 620. A reset input of the SR flip-flop 620 receives a signal POKDLY, which is a delayed version of the power OK (POK) signal. An output of the flip-flop 620 generates a soft start done (SSDONE) signal, which is output to a soft start state machine module 664.
The voltages are sensed during charging and compared by a capacitor sensing circuit 629 to predetermined reference potentials. For example, first terminals C1T, C2T, and C3T of capacitors Cfly1, Cfly2, and Cfly3, respectively, are connected to non-inverting inputs of comparators 630, 640 and 650, respectively. First, second and third reference potentials Vout/4, Vout/2, and 3*Vout/4 are connected to inverting inputs of the comparators 630, 640 and 650, respectively. Outputs of the comparators 630, 640 and 650 are input the soft start state machine module 664. The soft start state machine module 664 outputs S1, S2, S3 and S4 switch control signals to a switch driver module 665, which drives switching of the switches S1, S2, S3 and S4 based thereon.
The soft start state machine module 664 outputs a CHGCAPS signal to a current control circuit 674. The current control circuit 674 includes multiple current sources 12, 13, 14 and 15. In some examples, the CHGCAPS signal is used to control switches to enable the current sources 12, 13, 14 and 15. The current sources 12, 13, and 14 pull terminals of the capacitors Cfly1, Cfly2, and Cfly3 low when the CHGCAPS signal is high. The current source 15 drives Vout to battery when the CHGCAPS signal is high.
The switch driver module 665 selectively generates a DRVDONE signal when the switches are ready to switch. The DRVDONE signal is output to the soft start state machine module 664. The soft start state machine module 664 outputs an OSCEN signal to an oscillator module 678, which generates the OSC signal.
Another circuit 661 initially charges the capacitors to a predetermined voltage such as the input voltage or another voltage level. An inverting input of a comparator 662 is connected to a multiplexer 663. The multiplexer 663 selectively connects the inverting input of the comparator 662 to the terminal C1B of the capacitor Cfly1, then to the terminal C2B of the capacitor Cfly2, and then C3B of the capacitor Cfly3. A select signal for the multiplexer 663 may be generated by the soft start state machine module 664, the switch driver module 665, a separate logic circuit, or in any other suitable manner. A non-inverting input of the comparator 662 is connected to a reference potential, such as 350 mV. The multiplexer 663 changes the input to the comparator 662 to allow monitoring of Cfly1 first, then Cfly2, and then Cfly3. In some examples, the select signal selects C1B, C2B and C3B during the intervals that the corresponding flying capacitor Cfly1, Cfly2, and Cfly3, respectively, is being charged. An output of the comparator 662 (VOEQIN) is connected to an input of the soft start state machine module 664.
FIG. 10 illustrates operation of the soft start state machine module 664 of FIG. 9. FIGS. 11-13 show signals referenced in the description of FIG. 10. Control remains in a reset state 700 while the POK signal is equal to zero. Control transitions from the reset state 700 to another state 702 when the POK signal is equal to one. In the state 702, control charges the capacitors to the input voltage VIN. Control remains in the state 702 when the VOEQIN signal is equal to zero.
Control transitions from any state to state 708 when the SSDONE signal is equal to one. The SSDONE signal is equal to one when the soft start is complete and the circuit is ready for steady state operation of a multi-level step-up converter. In some examples, steady state operation may include operation based on the step-up converter topology described above. In state 708, control exits soft start, sets OSCEN equal to zero, opens switches S1 to S4 and sets the CHGCAPS signal equal to zero.
Control transitions from the state 702 to the state 710 when the VOEQIN signal is equal to one and the DRVDONE signal is equal to one. The VOEQIN signal identifies when all of the flying capacitors have been charged to a predetermined reference potential. The DRVDONE signal identifies when the switches are ready to be switched. At the state 710, control starts the oscillator and turns on the switches S1 to S4.
Control remains in the state 710 when OSC is equal to one. Control transitions from the state 710 to the state 714 when OSC=0 and condition A is true (or A=1). At state 714, control charges the capacitor Cfly1 and switches S2 to S4 are closed. Control transitions from state 714 back to state 710 when OSC=1.
Conditions A, B, C and D are defined as follows:

A=1 when Cfly1<1⁄4*Vout,

B=1 when Cfly1>1⁄4*Vout and Cfly2<1⁄2*Vout,

C=1 when Cfly1>1⁄4*Vout,Cfly2>1⁄2*Vout and Cfly3<3⁄4*Vout, and

D=1 when Cfly1>1⁄4*Vout,Cfly2>1⁄2*Vout, and Cfly3>3⁄4*Vout.

Control transitions from the state 710 to the state 718 when OSC=0 and condition B=1. At state 718, control charges the capacitor Cfly2 and switches S3 and S4 are closed. Control transitions from state 718 back to state 710 when OSC=1.
Control transitions from the state 710 to the state 722 when OSC=0 and condition C=1. At state 722, control charges the capacitor Cfly3 and switch S4 is closed. Control transitions from state 722 back to state 710 when OSC=1.
Control transitions from the state 710 to the state 726 when OSC=0 and condition D=1. At state 726, control charges the capacitor Cout and switches S1 to S4 are open. Control transitions from state 726 back to state 710 when OSC=1.
In use, the POK (power ok) signal goes high. In response, the switches S1 to S4 are off and the flying capacitors Cfly1, Cfly2, and Cfly3 are charged to VIN (the CHGCAPS signal is set equal to one). The CHGCAPS signal enables the current control circuit 674, which pulls terminals of the flying capacitors Cfly1, Cfly2, and Cfly3 low. The VOEQIN signal is generated when the C1B, C2B, and C3B node at the bottom terminal of the flying capacitor Cfly1, Cfly2, and Cfly3 are less than a predetermined reference potential such as 350 mV.
The switch driver module 665 sets the DRVDONE signal equal to one when the switches S1 to S4 are ready to switch. When both the DRVDONE signal and the VOEQIN signal are equal to one, the soft start state machine module 664 starts the oscillator module 678 (the OSCEN signal is equal to one) and turns on the switches S1 to S4. While the OSC is equal to one, the switches S1 to S4 remain on and the inductor L1 is charged as can be seen in FIG. 11. When the OSC is equal to zero, the soft start state machine module 664 selects one of the states 714, 718, 722 and 726 and charges one of the flying capacitors Cfly1, Cfly2, and Cfly3 or the output capacitor Cout depending on the value of voltages at nodes C1T, C2T and C3T, as described above.
The POKDLY signal goes from zero to one a predetermined period after the POK signal is equal to one. The POKDLY signal is input to the SR flip-flop 620. When a signal at a node between the LED string 614 and the current source 11 (the LED1S signal) is greater than a predetermined voltage potential such as 150 mV, the output of the comparator 616 goes high and the SSDONE signal becomes equal to one.
When the SSDONE signal is equal to one, the soft start state machine module 664 exits softstart and sets the OSCEN signal equal to zero. Switches S1 to S4 are open and the CHGCAPS signal is set equal to zero.
In order for a multi-level step-up converter to behave in a well-controlled manner when starting up, voltages of flying capacitors Cfly1, Cfly2, and Cfly3 should be balanced. The soft start module 610 according to the present disclosure charges each of the capacitors ratiometrically to prevent the multi-level step-up converter from having uncontrolled large currents during start up. As used herein, ratiometrically refers to charging the capacitors to a voltage that is a ratio of the output voltage. In some examples, the ratio increases monotonically from a lowest ratio on an inner capacitor to a highest ratio on an outer capacitor. One of the benefits of this approach is the ability to use switches with lower rated voltages.
For example only, the LED string may include 5 LEDs. The voltage drop across the LED string may be 16-18V. The switches can be rated at 4.8V and operated at 4.3V. Therefore, in some examples the voltage rating of the switches is less than 20% higher than the steady state operating voltage. In other examples, the voltage rating of the switches is less than 15% higher than the steady state operating voltage. In other examples, the voltage rating of the switches is less than 12% higher than the steady state operating voltage.
The softstart circuit according to the present disclosure transforms the multi-level step-up converter into a single input, multiple output (SIMO) converter during startup and supplies current pulses to each of the flying capacitors Cfly1, Cfly2, and Cfly3 and the output voltage such that the flying capacitor voltages stay ratio-ed to the output as follows:

Cfly1=1⁄4*Vout,

Cfly2=1⁄2*Vout, and

Cfly3=3⁄4*Vout.

The multi-level step-up converter requires that the capacitors Cfly1, Cfly2, and Cfly3 are balanced at predetermined ratios of the output voltage. If this is ignored during startup, then there can be large current spikes and the capacitors can possibly never come into balance. Also, with the balancing as implemented, smaller, low voltage rated MOSFETs can be used. This reduces the die size and allows improved operating efficiency. Also, the on-time of the multi-level step-up converter is proportional to the battery voltage to keep the peak current in the inductor constant regardless of battery voltage.
The invention charges the inductor to a peak current (500 mA typical) and then dumps that energy into the output, Cfly1, Cfly2, and Cfly3. The energy on each inductor cycle is sent to the capacitor that has the lowest voltage compared to the ideal ratio. This protects the capacitors and power devices in each stage of the step-up converter from going over-voltage during start-up, while charging the capacitors to the desired voltage for steady state operation.
Priority is given to Cfly1, then to Cfly2, and then to Cfly3, and then the output. The ideal ratios of voltages for the three flying caps are as follows:

Cfly1=1⁄4*Vout,

Cfly2=1⁄2*Vout, and

Cfly3=3⁄4*Vout.

While three flying capacitors are shown, two or more flying capacitors can be used. While the present disclosure is described in the context of multi-level step-up converters, the soft start module can be used with other types of converters. The present disclosure can also be extended to any level step-up converter.
As can be appreciated, the on time may be proportional to VIN to keep the inductor current approximately constant. The off time may be proportional to (VOUT−VIN).
In FIG. 13, an example of charging of the capacitors Cfly is shown. At 800, charging is shown after initial charging to VIN. Differences in the voltages at this stage are a result of voltage drops across the diodes. Thereafter, the capacitors Cfly are charged ratiometrically as described above. Once charged, the SSDONE signal can be asserted and operation of the multi-level, step-up converter may begin.
The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure.
In this application, including the definitions below, the term module may be replaced with the term circuit. The term module may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog/digital discrete circuit; a digital, analog, or mixed analog/digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor (shared, dedicated, or group) that executes code; memory (shared, dedicated, or group) that stores code executed by a processor; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.
The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, and/or objects. The term shared processor encompasses a single processor that executes some or all code from multiple modules. The term group processor encompasses a processor that, in combination with additional processors, executes some or all code from one or more modules. The term shared memory encompasses a single memory that stores some or all code from multiple modules. The term group memory encompasses a memory that, in combination with additional memories, stores some or all code from one or more modules. The term memory may be a subset of the term computer-readable medium. The term computer-readable medium does not encompass transitory electrical and electromagnetic signals propagating through a medium, and may therefore be considered tangible and non-transitory. Non-limiting examples of a non-transitory tangible computer readable medium include nonvolatile memory, volatile memory, magnetic storage, and optical storage.
The apparatuses and methods described in this application may be partially or fully implemented by one or more computer programs executed by one or more processors. The computer programs include processor-executable instructions that are stored on at least one non-transitory tangible computer readable medium. The computer programs may also include and/or rely on stored data.

## Claims

1. A system comprising:
an inductor including a first terminal in communication with an input voltage supply of a step-up converter;
N transistor pairs connected in series, where N is an integer greater than two, wherein first and second transistors of a first pair of the N transistor pairs are connected to a node, wherein the node is in communication with a second terminal of the inductor, and wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors connected between the N transistor pairs, respectively;
an output capacitor in communication with at least one transistor of the N transistor pairs; and
a controller configured to charge the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter, wherein the ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.

2. The system of claim 1 wherein the controller is configured to sequentially:
charge a first one of the (N−1) capacitors to 1/N of the output voltage;
charge a second one of the (N−1) capacitors to 2/N of the output voltage; and
charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.

3. The system of claim 1 wherein the controller is configured to initially charge the (N−1) capacitors to the input voltage before charging the (N−1) capacitors to the voltages that are ratios of the output voltage.

4. The system of claim 1 wherein the controller is configured to charge the (N−1) capacitors to the voltages that are ratios of the output voltage before operation of the step-up converter begins.

5. The system of claim 1 wherein the controller is configured to charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.

6. The system of claim 1 wherein controller is configured to:
sense the voltages across the (N−1) capacitors; and
adjust duty cycles of the N transistor pairs to maintain the ratios of the voltages.

7. The system of claim 1 wherein controller is configured to:
sense current supplied by the inductor; and
transition between switching modes of the N transistor pairs based on the current supplied by the inductor.

8. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle less than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are closed and the second and fourth transistors are open;
a second switching mode in which the first and second transistors are closed and the third and fourth transistors are open;
a third switching mode in which the second and fourth transistors are closed and the first and third transistors are open; and
a fourth switching mode in which the first and second transistors are closed and the third and fourth transistors are open.

9. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle less than 50%, the controller is configured to operate sequentially or non-sequentially in first, second, third, and fourth switching modes, and wherein:
during the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the second switching mode, current is supplied by the inductor to the load;
during the third switching mode, at least one of the (N−1) capacitors is charged; and
during the fourth switching mode, current is supplied by the inductor to the load.

10. The system of claim 9 wherein the controller is configured to transition:
from the first switching mode to the second switching mode at D*T;
from the second switching mode to a third switching mode at T/2;
from the third switching mode to the fourth switching mode at (1⁄2+D)*T; and
from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.

11. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle greater than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a third switching mode in which the first and third transistors are open and the second and fourth transistors are closed; and
a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open.

12. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle greater than 50%, the controller is configured to operate sequentially or non-sequentially in first, second, third, and fourth switching modes, and wherein:
during the first and third switching modes, current flows to ground;
during the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load; and
during the fourth switching mode, at least one of the (N−1) capacitors is charged.

13. The system of claim 12 wherein the controller is configured to transition:
from the first switching mode to the second switching mode at (D−1⁄2)*T;
from the second switching mode to the third switching mode at T/2;
from the third switching mode to the fourth switching mode at D*T; and
from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.

14. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being less than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a second switching mode in which the first and third transistors are closed and the second and fourth transistors are open;
a third switching mode in which the second, third, and fourth transistors are open and the first transistor is open;
a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open;
a fifth switching mode in which the first and third transistors are closed and the second and fourth transistors are open; and
a sixth switching mode in which the first, second, and fourth transistors are open and the third transistor is open.

15. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being less than 50%, the controller is configured to operate sequentially or non-sequentially in a first switching mode, a second switching mode, a third switching mode, a fourth switching mode, a fifth switching mode, and a sixth switching mode, and wherein:
during the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the second switching mode, current is supplied by the inductor to the load;
during the third switching mode, current is not supplied to the load or the (N−1) capacitors;
during the fourth switching mode, at least one of the (N−1) capacitors is charged; and
during the fifth switching mode, current is supplied by the inductor to the load;
during the sixth switching mode, current is not supplied to the load or the (N−1) capacitors.

16. The system of claim 15 wherein the controller is configured to transition:
from the first switching mode to the second switching mode when current is equal to a predetermined current;
from the second switching mode to the third switching mode when current is zero;
from the third switching mode to the fourth switching mode at T/2;
from the fourth switching mode to the fifth switching mode when current is equal to a predetermined current;
from the fifth switching mode to the sixth switching mode when current is zero; and
from the sixth switching mode to the first switching mode at T, where T is a period.

17. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being greater than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a third switching mode in which the first, third, and fourth transistors are open and the second transistor is closed;
a fourth switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a fifth switching mode in which the first and fourth transistors are closed and the second and third transistors are open; and
a sixth switching mode in which the first, second, and third transistors are open and the fourth transistor is closed.

18. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being greater than 50%, the controller is configured to operate sequentially or non-sequentially in a first switching mode, a second switching mode, a third switching mode, a fourth switching mode, a fifth switching mode, and a sixth switching mode, and wherein:
during the first and fourth switching modes, current flows to ground;
during the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the fifth switching mode, at least one of the (N−1) capacitors is charged; and
during the third and sixth switching modes, current is not supplied to the load or the (N−1) capacitors.

19. The system of claim 18 wherein the controller is configured to transition:
from the first switching mode to the second switching mode when current is equal to a predetermined current;
from the second switching mode to the third switching mode when current is zero;
from the third switching mode to the fourth switching mode at T/2;
from the fourth switching mode to the fifth switching mode when current is equal to the predetermined current;
from the fifth switching mode to the sixth switching mode when current is zero; and
from the sixth switching mode to the first switching mode at T, where T is a period.

20. A method comprising:
receiving an input voltage at an inductor of a step-up converter, the step-up converter including N transistor pairs connected in series, where N is an integer greater than two, first and second transistors of a first pair of the N transistor pairs being connected to a node that is connected to the inductor, third and fourth transistors of a second pair of the N transistor pairs being respectively connected to the first and second transistors, (N−1) capacitors being connected between the N transistor pairs, and an output capacitor being connected to at least one transistor of the N transistor pairs; and
charging the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter, wherein the ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.

21. The method of claim 20 further comprising sequentially:
charging a first one of the (N−1) capacitors to 1/N of the output voltage;
charging a second one of the (N−1) capacitors to 2/N of the output voltage; and
charging an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.

22. The method of claim 20 further comprising initially charging the (N−1) capacitors to the input voltage before charging the (N−1) capacitors to the voltages that are ratios of the output voltage.

23. The method of claim 20 further comprising charging the (N−1) capacitors to the voltages that are ratios of the output voltage before beginning operation of the step-up converter.

24. The method of claim 20 further comprising charging an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.

25. The method of claim 20 further comprising:
sensing the voltages across the (N−1) capacitors; and
adjusting duty cycles of the N transistor pairs to maintain the ratios of the voltages.

26. The method of claim 20 further comprising:
sensing current supplied by the inductor; and
transitioning between switching modes of the N transistor pairs based on the current supplied by the inductor.

27. A system comprising:
an inductor including a first terminal in communication with an input voltage supply of a step-up converter;
N transistor pairs connected in series, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected to a node, wherein the node is in communication with a second terminal of the inductor, and wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors connected between the N transistor pairs, respectively;
an output capacitor in communication with at least one transistor of the N transistor pairs; and
a controller configured to
generate a first signal when the N transistor pairs are ready to switch;
charge the (N−1) capacitors to the input voltage;
generate a second signal charging the (N−1) capacitors is complete; and
sequentially charge the (N−1) capacitors to (N−1) fractions of an output voltage of the step-up converter in response to the first signal and the second signal.

28. The system of claim 27 wherein the controller is configured to charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.