# Patent

## Title
Forming a hybrid channel nanosheet semiconductor structure

## Abstract

A nanosheet semiconductor structure includes a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material.

## Background
BACKGROUND
Semiconductor structures or devices may be embodied as field effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs). One or more such FETs may comprise an integrated circuit (IC or chip). As ICs are being scaled to smaller dimensions, stacked nanosheet FETs, or nanosheet FETs, have been developed to increase effective conduction width in a given area. A nanosheet is a nanostructure with a thickness in a scale ranging from, e.g., about 1 to 100 nanometers (nm). A nanosheet FET is a FET that is formed by stacking multiple such nanostructures.
SUMMARY
Illustrative embodiments of the invention provide techniques for fabricating nanosheet semiconductor structures.
For example, in one embodiment, a a nanosheet semiconductor structure comprises a first nanosheet field effect transistor (FET) structure comprising a first inner spacer comprised of a first material and a second nanosheet FET structure comprising a second inner spacer comprised of a second material. The first material is different than the second material. In one example, the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure. The first nanosheet FET structure and the second nanosheet FET structure are collectively formed to construct a hybrid channel nanosheet semiconductor structure.
While illustrative embodiments are described herein with respect to hybrid channel nanosheet FETs, alternative embodiments may be implemented with other types of semiconductor structures.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a schematic cross-sectional side view of a portion of a semiconductor device at a first-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1B is a schematic cross-sectional side view of a portion of a semiconductor device at a second-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1C is a schematic cross-sectional side view of a portion of a semiconductor device at a third-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1D is a schematic cross-sectional side view of a portion of a semiconductor device at a fourth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1E is a schematic cross-sectional side view of a portion of a semiconductor device at a fifth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1F is a schematic cross-sectional side view of a portion of a semiconductor device at a sixth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1G is a schematic cross-sectional side view of a portion of a semiconductor device at a seventh-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1H is a schematic cross-sectional side view of a portion of a semiconductor device at an eighth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1I is a schematic cross-sectional side view of a portion of a semiconductor device at a ninth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1J is a schematic cross-sectional side view of a portion of a semiconductor device at a tenth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1K is a schematic cross-sectional side view of a portion of a semiconductor device at an eleventh-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1L is a schematic cross-sectional side view of a portion of a semiconductor device at a twelfth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1M is a schematic cross-sectional side view of a portion of a semiconductor device at a thirteenth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1N is a schematic cross-sectional side view of a portion of a semiconductor device at a fourteenth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1O is a schematic cross-sectional side view of a portion of a semiconductor device at a fifteenth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1P is a schematic cross-sectional side view of a portion of a semiconductor device at a sixteenth-intermediate fabrication stage, according to an embodiment of the invention.
FIG. 1Q is a schematic cross-sectional side view of a portion of a semiconductor device at a seventeenth-intermediate fabrication stage, according to an embodiment of the invention.



DETAILED DESCRIPTION
In illustrative embodiments, techniques are provided for fabricating semiconductor devices comprised of one or more FETs. More particularly, illustrative embodiments provide techniques for fabricating semiconductor devices comprised of one or more hybrid channel nanosheet FETS. As will be explained in illustrative embodiments, such fabrication techniques advantageously improve performance of semiconductor devices.
Furthermore, it is to be understood that embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to fabrication (forming or processing) steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the steps that may be used to form a functional integrated circuit device. Rather, certain steps that are commonly used in fabricating such devices are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about,” “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
FIGS. 1A-1Q illustrate an exemplary process for fabricating a semiconductor structure for increasing control of fin reveal in a dense fin region. FIG. 1A illustrates a semiconductor structure 100 at a first-intermediate fabrication stage. For the purpose of clarity, several fabrication steps leading up to the production of the semiconductor structure 100 as illustrated in FIG. 1A are omitted. In other words, semiconductor structure 100 does not necessarily start out in the form illustrated in FIG. 1A, but may develop into the illustrated structure over one or more well-known processing steps which are not illustrated but are well-known to those of ordinary skill in the art. Also, note that the same reference numeral (100) is used to denote the semiconductor structure through the various intermediate fabrication stages illustrated in FIGS. 1A through 1K. Note also that semiconductor structure 100 can also be considered to be a semiconductor device and/or an integrated circuit, or some part thereof.
Semiconductor structure 100 in FIG. 1A is shown having n-FET region 102A comprising stack 104A and p-FET region 102B comprising stack 104B. Each stack is comprised of a substrate and alternating nanosheets of material arranged on the substrate. In one embodiment, each nanosheet may have a thickness ranging from about 1 nm to about 100 nm. For example, as shown in this illustrative embodiment, stack 104A is comprised of substrate 103A and nanosheets 105A. In one embodiment, and as shown, substrate 103A is comprised of silicon (Si). As shown, nanosheets 105A may comprise alternating nanosheets comprised of silicon-germanium (SiGe) and nanosheets comprised of Si. It is to be understood that the arrangement of SiGe and Si nanosheets on the substrate, including the number of nanosheets, is purely exemplary and should not be considered limiting.
FIG. 1B illustrates semiconductor structure 100 at a second-intermediate fabrication stage. During this stage, pad insulator 106A is formed on stack 104A, and pad insulator 106B is formed on stack 104B. Gate 108A is formed on pad insulator 106A and gate 108B is formed on pad insulator 106B. Gate hard mask 110A is formed on gate 108A and gate hard mask 110B is formed on gate 108B. Spacer 112A is deposited along n-FET region 102A and spacer 112B is deposited along p-FET region 102B, as shown in FIG. 1B. Accordingly, gate formation and spacer deposition occur in the fabrication stage illustrated in FIG. 1B.
FIG. 1C illustrates semiconductor structure 100 at a third-intermediate fabrication stage. During this stage, n-FET region 102A and p-FET region 102B are each etched as shown to form channel regions 113A and 113B. Accordingly, the nanosheets of each FET region form respective channel regions of the semiconductor structure.
FIG. 1D illustrates semiconductor structure 100 at a fourth-intermediate fabrication stage. During this stage, divots are created within channel region 113A and channel region 113B via an etching process (e.g., an isotropic etching process), and each divot is filled with an inner spacer. For example, as shown, the divots of channel region 113A are filled with inner spacer 114A, and the divots of channel region 113B are filled with inner spacer 114B. In one embodiment, inner spacer 114A and inner spacer 114B are comprised of a ceramic material. For example, inner spacer 114A and/or inner spacer 114B may be comprised of silicon-boron-carbide-nitride (SiBCN). However, any suitable material may be implemented for use as an inner spacer in accordance with the embodiments described herein.
FIG. 1E illustrates semiconductor structure 100 at a fifth-intermediate fabrication stage. During this stage, sacrificial liner 116A is deposited on n-FET region 102A and sacrificial liner 116B is deposited on p-FET region 102B. In one embodiment, sacrificial liners 116A and 116B are comprised of a ceramic material. For example, sacrificial liners 116A and/or 116B may be comprised of SiBCN. However, any suitable material may be implemented for use as a sacrificial liner in accordance with the embodiments described herein.
FIG. 1F illustrates semiconductor structure 100 at a sixth-intermediate fabrication stage. During this stage, mask 118B is patterned on sacrificial liner 116B. The function of mask 118 is to protect p-FET region 102B. After mask 118 is patterned on sacrificial liner 116B, sacrificial liner 116A is removed.
FIG. 1G illustrates semiconductor structure 100 at a seventh-intermediate fabrication stage. During this stage, the source/drain region 120A of n-FET region 102A is created by growing an epitaxial layer along the Si channel of channel region 113A of n-FET region 102A, as shown. In one embodiment, the epitaxial layer along the Si channel of channel region 113A is grow via high temperature epitaxy with phosphorus (P) implantation. Additionally, mask 118B is removed from p-FET region 102B.
FIG. 1H illustrates semiconductor structure 100 at an eighth-intermediate fabrication stage. During this stage, sacrificial liner 121A is deposited on n-FET region 102A and sacrificial liner 121B is deposited on p-FET region 102B (i.e., along sacrificial liner 116B). Sacrificial liner 121A protects the epitaxial layer of source/drain region 120A.
FIG. 1I illustrates semiconductor structure 100 at a ninth-intermediate fabrication stage. During this stage, mask 118A is patterned on sacrificial liner 121A. The function of mask 118A is to protect n-FET region 102A. After mask 118A is patterned on sacrificial liner 121A, sacrificial liners 116B and 121B are removed from p-FET region 102B.
FIG. 1J illustrates semiconductor structure 100 at a tenth-intermediate fabrication stage. During this stage, divots are created within the Si channel of channel region 113B of p-FET region 102B via an etching process, inner spacer material is deposited within the divots (e.g., inner spacer 122B), and mask 118A is removed. In one embodiment, the etching process is isotropic. Inner spacer 122B may be comprised of a silicate glass. For example, inner spacer 122B may be comprised of silicon oxycarbide (SiCO). However, any material may be implemented for use as an inner spacer in accordance with the embodiments described herein. In one embodiment, the width of inner spacer 122B is smaller than the width of inner spacer 114B to avoid exposing the SiGe channel of channel region 113B. Accordingly, conformal liner deposition is performed to create a SiCO inner spacer for the Si channel of channel region 113B.
FIG. 1K illustrates semiconductor structure 100 at an eleventh-intermediate fabrication stage. During this stage, inner spacer 114B is removed, and source/drain region 120B of p-FET region 102B is created by growing an epitaxial layer along the SiGe channel of channel region 113B of p-FET region 102B, as shown. In one embodiment, the epitaxial layer along the SiGe channel of channel region 113B is grown via high temperature epitaxy with Ge implantation. After source/drain region 120B is created, mask 118A is removed.
FIG. 1L illustrates semiconductor structure 100 at a twelfth-intermediate fabrication stage. During this stage, interlayer dielectric 128A is formed on source/drain region 120A of n-FET region 102A, and interlayer dielectric 128B is formed on source/drain region 120B of p-FET region 102B. In one embodiment, interlayer dielectric 128A and interlayer dielectric 128B are comprised of an oxide. However, interlayer dielectrics 128A and 128B may be comprised of any dielectric material in accordance with the embodiments described herein.
FIG. 1M illustrates semiconductor structure 100 at a thirteenth-intermediate fabrication stage. During this stage, a polysilicon pull process, or “poly-pull” process, is performed to remove the gate from n-FET region 102A, and a channel release is performed to remove the SiGe portion of channel region 113A. In one embodiment, performing the poly-pull process and channel release comprises performing an isotropic SiGe etch selective to Si.
FIG. 1N illustrates semiconductor structure 100 at a fourteenth-intermediate fabrication stage. During this stage, work function metal 130A is deposited in channel region 113A to replace the channel released from channel region 113A. In one embodiment, work function metal 130A is deposited via a conformal atomic layer deposition (ALD) process. As further shown, metal 132A is deposited to replace gate 108A. Metal 132A may be tungsten (W), but any metal may be used in accordance with the embodiments described herein. In one embodiment, metal 132A is deposited via a chemical vapor deposition (CVD) process. For example, metal 132A may be deposited via plasma-enhanced CVD (PECVD). A chemical mechanical planarization (CMP) may be performed after metal 132A is deposited.
FIG. 1O illustrates semiconductor structure 100 at a fifteenth-intermediate fabrication stage. During this stage, a “poly-pull” process is performed to remove the gate from p-FET region 102B, and a channel release is performed to remove the Si portion of channel region 113B.
FIG. 1P illustrates semiconductor structure 100 at a sixteenth-intermediate fabrication stage. During this stage, work function metal 130B is deposited in channel region 113A to replace the Si channel released from channel region 113B. In one embodiment, work function metal 130B is deposited via a conformal ALD process. As further shown, metal 132B is deposited to replace gate 108B. Metal 132B may be W, but any metal may be used in accordance with the embodiments described herein. In one embodiment, metal 132B is deposited via a CVD process. For example, metal 132B may be deposited via PECVD. A chemical mechanical planarization (CMP) may be performed after metal 132B is deposited.
FIG. 1Q illustrates semiconductor structure 100 at a seventeenth-intermediate fabrication stage. During this stage, metal 132A and metal 132B are recessed, and gate cap layers 134A and 134B are formed on n-FET region 102A and p-FET region 102B, respectively, to create a self-aligned source/drain contact. In one embodiment, gate cap layers 134A and 134B are formed by etching metal 132A and 132B to form recesses and depositing gate cap material within the recesses. A CMP process may be performed to remove excess portions of the deposited gate cap material (i.e., to remove overflow material). The gate cap material may be comprised of silicon mononitride (SiN). However, any material may be used as gate cap material in accordance with the embodiments described herein. Accordingly, the embodiments described herein provide for a method for fabricating a hybrid channel nanosheet FET.
It is to be understood that the methods discussed herein for fabricating semiconductor structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with embodiments can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.
Furthermore, various layers, regions, and/or structures described above may be implemented in integrated circuits (chips). The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.

## Claims

1. A nanosheet semiconductor structure comprising:
a first nanosheet field effect transistor (FET) structure comprising a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region, wherein the first SiGe channel comprises one or more SiGe nanosheets, and wherein a first inner spacer comprised of a first material is comprised in the first channel region; and
a second nanosheet FET structure comprising a second SiGe channel comprised in a second channel region of a second FET region, wherein the second SiGe channel comprises one or more SiGe nanosheets, and wherein a second inner spacer comprised of a second material is comprised in the second channel region;
wherein the first material is different than the second material.

2. The structure of claim 1, wherein the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.

3. The structure of claim 1, wherein the first FET structure further comprises:
a first substrate;
wherein the first SiGe channel region is formed on the first substrate and comprises the first SiGe channel and a first work function metal; and
a first gate comprising a first metal.

4. The structure of claim 3, wherein the first substrate is comprised of Si.

5. The structure of claim 3, wherein the first SiGe channel region further comprises a first source/drain region.

6. The structure of claim 3, wherein the first metal is comprised of tungsten (W).

7. The structure of claim 1, wherein the second FET structure further comprises:
a second substrate;
wherein the second SiGe channel region is formed on the second substrate and comprises the second SiGe channel; and
a second gate comprising a second metal.

8. The structure of claim 7, wherein the second substrate is comprised of Si.

9. The structure of claim 7, wherein the second SiGe channel region further comprises a second source/drain region.

10. The structure of claim 7, wherein the second metal is comprised of tungsten (W).

11. An integrated circuit comprising:
a first nanosheet field effect transistor (FET) structure comprising a first SiGe channel comprised in a first channel region of a first FET region, wherein the first SiGe channel comprises one or more SiGe nanosheets, and wherein a first inner spacer comprised of a first material is comprised in the first channel region; and
a second nanosheet FET structure comprising a second SiGe channel comprised in a second channel region of a second FET region, wherein the second SiGe channel comprises one or more SiGe nanosheets, and wherein a second inner spacer comprised of a second material is comprised in the second channel region;
wherein the first material is different than the second material.

12. The integrated circuit of claim 11, wherein the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.

13. The integrated circuit of claim 11, wherein the first FET structure further comprises:
a first substrate;
wherein the first SiGe channel region is formed on the first substrate and comprises the first SiGe channel and a first work function metal; and
a first gate comprising a first metal.

14. The integrated circuit of claim 13, wherein the first substrate is comprised of Si.

15. The integrated circuit of claim 13, wherein the first SiGe channel region further comprises a first source/drain region.

16. The integrated circuit of claim 13, wherein the first metal is comprised of tungsten (W).

17. The integrated circuit of claim 13, wherein the second FET structure further comprises:
a second substrate;
wherein the second SiGe channel region is formed on the second substrate and comprises the second SiGe channel; and
a second gate comprising a second metal.

18. The integrated circuit of claim 17, wherein the second substrate is comprised of Si.

19. The integrated circuit of claim 17, wherein the second SiGe channel region further comprises a second source/drain region.

20. The integrated circuit of claim 17, wherein the second metal is comprised of tungsten (W).