# Patent

## Title
Advanced e-fuse structure with hybrid metal controlled microstructure

## Abstract

A structure and method for fabricating an e-Fuse device in a semiconductor device is described. A method for fabricating an e-Fuse device includes providing a trench structure including an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. An aspect ratio reducing layer is selectively formed in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer. The trench is filled with copper, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region. The copper is annealed to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

## Background
BACKGROUND OF THE INVENTION
This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create advanced e-Fuse structures in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continue to shrink, conventional lithography is increasingly challenged to make smaller and smaller structures.
Fuses are utilized within integrated circuit devices for a variety of purposes, such as programming certain functionality into the device or to enable or disable various devices within the circuit device. Such fuse structures can break electrical connections (such as in physically destroyable fuses or anti-fuses). Some fuse structures rely upon a smaller cross-sectional area between the anode and cathode and the fuse element. As the dimensions of the circuitry become ever smaller, it is desirable to reduce the voltage needed to program integrated circuits.
Thus, it is desirable to provide processes which can be used to make improved fuse structures for integrated circuitry.
BRIEF SUMMARY
According to this disclosure, an advanced e-Fuse structure and a method for constructing the structure are described. A method for fabricating an e-Fuse device includes providing a trench structure including an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. An aspect ratio reducing layer is selectively formed in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer. The trench is filled with copper, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region. The copper is annealed to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element.
Another aspect of the invention is an e-Fuse device. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.
The foregoing has outlined some of the more pertinent features of the disclosed subject matter. These features should be construed to be merely illustrative. Many other beneficial results can be attained by applying the disclosed subject matter in a different manner or by modifying the invention as will be described.



BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings which are not necessarily drawing to scale, and in which:
FIG. 1 is a top diagram of a prior art e-Fuse structure;
FIG. 2A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 2B and 2C are cross-sectional diagrams depicting the structure after a patterning step has been performed according to a first embodiment of the invention;
FIG. 3A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 3B and 3C are cross-sectional diagrams depicting the structure after a liner deposition step has been performed according to a first embodiment of the invention;
FIG. 4A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 4B and 4C are cross-sectional diagrams depicting the structure after an aspect ratio reduction layer deposition step has been performed according to a first embodiment of the invention;
FIG. 5A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 5B and 5C are cross-sectional diagrams depicting the structure after recess of the aspect ratio reduction layer has been performed according to a first embodiment of the invention;
FIG. 6A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 6B and 6C are cross-sectional diagrams depicting the structure after removal of the block out mask has been performed according to a first embodiment of the invention;
FIG. 7A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 7B and 7C are cross-sectional diagrams depicting the structure after a copper deposition step has been performed according to a first embodiment of the invention;
FIG. 8A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 8B and 8C are cross-sectional diagrams depicting the structure after an anneal step has been performed according to a first embodiment of the invention;
FIG. 9A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 9B and 9C are cross-sectional diagrams depicting the structure after a planarization step and metal cap deposition have been performed according to a first embodiment of the invention;
FIG. 10A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 10B and 10C are cross-sectional diagrams depicting the structure after a liner deposition and an aspect ratio reduction layer steps have been performed according to a second embodiment of the invention;
FIG. 11A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 11B and 11C are cross-sectional diagrams depicting the structure after recess of the aspect ratio reduction layer has been performed according to a second embodiment of the invention;
FIG. 12A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 12B and 12C are cross-sectional diagrams depicting the structure after removal of the block out mask has been performed according to a second embodiment of the invention;
FIG. 13A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 13B and 13C are cross-sectional diagrams depicting the structure after a copper deposition step has been performed according to a first embodiment of the invention;
FIG. 14A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams;
FIGS. 14B and 14C are cross-sectional diagrams depicting the structure after an anneal step has been performed according to a first embodiment of the invention;
FIG. 15A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams; and
FIGS. 15B and 15C are cross-sectional diagrams depicting the structure after a chemical mechanical polishing step and metal cap deposition have been performed according to a first embodiment of the invention.



DETAILED DESCRIPTION OF THE DRAWINGS
At a high level, the invention includes an e-Fuse structure and method for fabricating an e-Fuse structure with improved programmability by increasing the electromigration resistance (EM-resistance) difference between the cathode and anode ends as compared to the central part of the e-Fuse element through microstructure control.
A “substrate” as used herein can comprise any material appropriate for the given purpose (whether now known or developed in the future) and can comprise, for example, Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III-V or II-VI compound semiconductors, or organic semiconductor structures, etc.
For purposes herein, a “semiconductor” is a material or structure that may include an implanted impurity that allows the material to sometimes be conductive and sometimes be a non-conductive, based on electron and hole carrier concentration. As used herein, “implantation processes” can take any appropriate form (whether now known or developed in the future) and can comprise, for example, ion implantation, etc.
For purposes herein, an “insulator” is a relative term that means a material or structure that allows substantially less (<95%) electrical current to flow than does a “conductor.” The dielectrics (insulators) mentioned herein can, for example, be grown from either a dry oxygen ambient or steam and then patterned. Alternatively, the dielectrics herein may be formed from any of the many candidate high dielectric constant (high-k) materials, including but not limited to hafnium oxide, aluminum oxide, silicon nitride, silicon oxynitride, a gate dielectric stack of SiO2 and Si3N4, and metal oxides like tantalum oxide that have relative dielectric constants above that of SiO2 (above 3.9). The dielectric can be a combination of two or more of these materials. The thickness of dielectrics herein may vary contingent upon the required device performance. The conductors mentioned herein can be formed of any conductive material, such as polycrystalline silicon (polysilicon), amorphous silicon, a combination of amorphous silicon and polysilicon, and polysilicon-germanium, rendered conductive by the presence of a suitable dopant. Alternatively, the conductors herein may be one or more metals, such as tungsten, hafnium, tantalum, molybdenum, titanium, or nickel, or a metal silicide, any alloys of such metals, and may be deposited using physical vapor deposition, chemical vapor deposition, or any other technique known in the art.
When patterning any material herein, the material to be patterned can be grown or deposited in any known manner and a patterning layer (such as an organic photoresist aka “resist”) can be formed over the material. The patterning layer (resist) can be exposed to some form of light radiation (e.g., patterned exposure, laser exposure, etc.) provided in a light exposure pattern, and then the resist is developed using a chemical agent. This process changes the characteristic of the portion of the resist that was exposed to the light. Then one portion of the resist can be rinsed off, leaving the other portion of the resist to protect the material to be patterned. A material removal process is then performed (e.g., plasma etching, etc.) to remove the unprotected portions of the material to be patterned. The resist is subsequently removed to leave the underlying material patterned according to the light exposure pattern.
For purposes herein, “sidewall structures” are structures that are well-known to those ordinarily skilled in the art and are generally formed by depositing or growing a conformal insulating layer (such as any of the insulators mentioned above) and then performing a directional etching process (anisotropic) that etches material from horizontal surfaces at a greater rate than its removes material from vertical surfaces, thereby leaving insulating material along the vertical sidewalls of structures. This material left on the vertical sidewalls is referred to as a sidewall structure. The sidewall structures can be used as masking structures for further semiconducting processing steps.
“Electromigration” is a term applied to the transport of mass in metals when the metals are subjected to high current density. “Electromigration resistance” or “EM-resistance” is a property of a metal which is resistant to this effect.
While the process steps to fabricate one embodiment of the invention are described with reference to a planar metal-oxide-semiconductor field-effect transistor (MOSFET) device, other embodiments described below are incorporated in other devices having source/drain regions and gate structures such as fin field effect transistors (FinFETs).
Electrical fuses (eFuses) are used to in semiconductor industry to implement array redundancy, field programmable arrays, analog component trimming circuits, and chip identification circuits. Programming of the prior art electrical fuses typically takes a substantial amount of current, which is undesirable in current technology node devices using low driving current. In addition, programming transistor takes up space in a semiconductor chip, as well as power consumption.
Embodiments will be explained below with reference to the accompanying drawings.
FIG. 1 is a top diagram of a prior art e-Fuse structure. The e-Fuse technology was invented by IBM to allow for dynamic real-time reprogramming of computer chips. Although computer logic is generally “hard-coded” onto a chip and cannot be changed after the chip has finished being manufactured, through the use of a set of e-Fuses, a chip manufacturer can allow for the circuits on a chip to change while it is in operation. The technology can provide in-chip performance tuning. If certain sub-systems fail, or are taking too long to respond, or are consuming too much power, the chip can instantly change its behavior by “blowing” an e-Fuse. The process creating shorts at selected e-Fuses is also called “programming”. E-Fuses are used in the semiconductor industry to implement array redundancy, field programmable arrays, analog component trimming circuits, chip identification circuits and other devices.
In the prior art e-Fuse structures, an in-plane dimensional difference between the cathode and anode located at the ends of the e-Fuse and the central stripe or fuse element. The narrow dimension of the fuse element localizes the placement of the site where a circuit open is created. During programming, a positive voltage bias is applied to the anode contact region and a negative voltage at the cathode contact region through the contacts. Increased local current density is obtained at the narrow cross-section of the fuse element, or fuselink, which also elevates the temperature. For example, as shown in FIG. 1, a two-dimensional “dog-bone” shaped e-Fuse is known, including a fuse element having a small cross-sectional area between the large cross-sectional area cathode and anode pads. The narrowing of cross-sectional area increases local current density in the fuse element. This type of fuse structure has been adopted in the semiconductor industry. Nonetheless, as the dimensions of other devices in the integrated circuits continue to shrink, there is a need for e-Fuse elements with better process control and higher programming efficiency.
The combination of high current density with the elevated temperature at the fuse element facilitates electromigration of the conductive material at the fuse element. Electrically “blowable” fuses take advantage of the electromigration (EM) effect to open an electrical connection. In a two-dimensional dog-bone shaped e-Fuse, such as that shown in FIG. 1, voids form at the small cross-section center fuse element due to high current density during programming, and eventually, create an electrically open circuit. It is also known that electromigration causes the conductive material to pile-up and form hillocks at the anode (most positive) end of the fuse element. Hillock formation is an undesirable effect.
The present invention improves upon the prior art with a novel electrical fuse structure with high programming efficiency through local heating. In addition to a dimensional difference, the invention further increases EM-resistance differences between cathode/anode and the fuse element of the e-Fuse through microstructure control. The invention uses different aspect ratios of areas of the trench in which the e-Fuse is formed to create a different grain structure in each of the two sets of areas. The grain structure created in the center part of the e-Fuse element has less EM-resistance than that created in the anode and cathode regions. The relative depth and aspect ratio of the fuse element portion is greater than the relative depth and aspect ratio of the cathode and anode regions.
FIG. 2A is a top diagram of an e-Fuse structure to show the orientation of FIGS. 2B and 2C which are cross-sectional diagrams depicting the structure after a patterning step has been performed according to a first embodiment of the invention. Although the anode and cathode regions are shown as square shaped in the drawings, in alternative embodiments of the invention, these regions could be the irregular pentagon shape of the prior art as depicted in FIG. 1 or other shapes. FIG. 2B is a cross-sectional diagram through the cathode or anode region; FIG. 2C is a cross-sectional diagram through the fuse element. In FIGS. 2B and 2C, a trench is cut through dielectric layer 201 by means of an etch process using a hard mask 203 as a patterning element. The dielectric 201 may be any suitable dielectric material such as, for example, SiC, Si4NH3, SiO2, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof disposed over a substrate (not shown). The layer of dielectric material can be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, and spin-on coating. The thickness of the blanket layer of dielectric material may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the blanket layer of dielectric material has a thickness from 50 nm to 800 nm, with a thickness from 80 nm to 300 nm being more typical. The hard mask 203 is preferably a material which has a high etch selectivity/resistivity as compared to the dielectric layer 201 such as SiN if the dielectric layer 201 was silicon oxide. The hard mask 203 can be formed utilizing a conventional deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation, and physical vapor deposition (PVD). Alternatively, the hard mask may be formed by one of thermal oxidation, and thermal nitridation. Typically, the blanket layer of hard mask material has a thickness from 10 nm to 80 nm with a thickness from 25 nm to 45 nm being more typical.
As shown in FIGS. 2B and 2C, different aspect ratios are created in the cathode/anode and fuse element regions by adjusting the height and width dimensions at both center and ends of the fuse structure. In the convention of the application, the aspect ratio (A/R) is low at the ends, A/R contact=(h1/d1), and high at the center, A/R fuse=(h2/d2). The difference of the aspect ratios, A/R fuse−A/R contacts>0.5. A/R in preferred embodiments. Normal metal grain growth, i.e. large grains, starts in the top overburden area and continues into the bottom patterned features. The overburden area or thickness is the plated Cu thickness above top of the patterned features. The driving force to have the normal grain growth continue through the pattern features is achievable in low aspect ratio features. However, due to thermodynamic related constrains, large Cu grain growth cannot continue through the high A/R features, and leaves fine grains inside the small features. In this embodiment of the invention, the depth (height, h1=h2) of the two regions is equal, and so the difference in aspect ratio is controlled by the width of the two regions (d1>>d2). By selecting the aspect ratios, as will be explained below, the respective grain structures of conductive material which fills the two regions is controlled and different in the two regions. Typically, the depths of the trench at h1 and h2 are on the order of 35 nm to 480 nm, with a depth from 65 nm to 345 nm being more typical. The widths of the anode and cathode regions and the fuse element will vary according to the design requirements of the e-Fuse. However, in preferred embodiments of the invention, the widths of the contact regions would be between 50 nm to 500 nm and the width of the fuse element would between 20 nm to 80 nm, with a thickness from 65 nm to 345 nm being more typical.
FIG. 3A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 3B and 3C are cross-sectional diagrams respectively depicting the structure at the anode/cathode and the fuse element after a liner deposition step has been performed according to a first embodiment of the invention. Presuming that the correct aspect ratios can be created, the first embodiment is preferred from a simpler processing standpoint. The deposition of liner material(s) 205 can be formed on the trench and hard mask utilizing any conventional deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, plating, chemical solution deposition and electroless plating. The thickness of the liner can vary depending on the number of metal layers within the liner 205, the type of metal layer being formed and the technique used in forming the same. Typically, the liner 205 has a thickness from 1 nm to 20 nm, with a thickness from 2 nm to 10 nm being more typical. Suitable liner materials include Ta, Ti, W, Co, Ru, and their nitride materials, TaN, TiN, WN, CoN, RuN. The liner material prevents the diffusion of the subsequent copper layer into the dielectric.
FIG. 4A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 4B and 4C are cross-sectional diagrams respectively depicting the structures in the anode/cathode regions and fuse element region after an aspect ratio reduction layer deposition step has been performed according to a first embodiment of the invention. As shown, the aspect ratio reduction layer 207 is only deposited in the cathode and anode regions. The fuse element region is shown protected by blockout mask 209 in FIG. 4C. The function of the aspect ratio reduction layer 207 is to reduce the aspect ratio in the anode and cathode regions for a subsequent copper deposition and anneal which will be explained below. Suitable materials for the aspect ratio reduction layer 207 include W, Co, Rh, Ru, Au, Ag, and Al. The material used for the aspect ratio reduction layer should be conductive, and are preferably EM-resistant. The aspect ratio reduction layer 207 can be formed by a conventional deposition process including, for example, CVD, PECVD, ALD, and PVD, sputtering, plating, chemical solution deposition and electroless plating. In the first embodiment, electroplating is preferably used to complete the metal fill in FIG. 4B. A second embodiment is discussed below which deposits a thin layer through PVD and then thermal reflow the material into the features.
FIG. 5A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 5B and 5C are cross-sectional diagrams respectively depicting the structure after recess of the aspect ratio reduction layer 207 has been performed according to a first embodiment of the invention. As shown, the aspect ratio layer 207 has been recessed through a conventional wet etch or dry plasma reaction ion etch (RIE) process. In embodiments of the invention, 30-90% of the total trench height in the anode and cathode regions will be filled with copper and preferably the copper will fill 50-70% of the total trench height in those areas. In a preferred embodiment, the etch should be sufficient to clear the aspect ratio layer from areas outside the trench. In an alternative embodiment, a metal reflow process is used to provide the aspect ratio reduction layer 207 using Al, Co, Rh, Ag, Au, W, Ru as the reflowed metal.
FIG. 6A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 6B and 6C are cross-sectional diagrams depicting the structure after removal of the block out mask has been performed according to a first embodiment of the invention. FIG. 6B shows the presence of the aspect ratio reduction layer 207 in the cathode and anode regions and FIG. 6C shows that the aspect ratio reduction layer is absent from the fuse element region. The use of the aspect ratio reduction layer increases the difference between the aspect ratio between the two sets of regions.
FIG. 7A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 7B and 7C are cross-sectional diagrams respectively depicting the structures of the anode/cathode and fuse element regions after a copper deposition step has been performed according to a first embodiment of the invention; The deposition of the copper layer 211 can be formed over the liner 205 and aspect ratio reduction layer 207 utilizing any conventional deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, plating, chemical solution deposition, electroless plating, or combination of the same. The thickness of the copper layer can vary depending on the depth of the trench and the technique used in forming the copper layer. Typically, the copper layer has an overburden thickness from 100 nm to 1000 nm, with a thickness from 300 nm to 800 nm being more typical.
FIG. 8A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 8B and 8C are cross-sectional diagrams respectively depicting the structure in the anode/cathode and fuse element regions after an anneal step has been performed according to a first embodiment of the invention. The thermal anneal of the copper layer 211 can be carried out at a selected temperature between 100 to 400 degrees Centigrade for 30 minutes ̃3 hours in a thermal furnace. The thermal anneal of the copper layer 207 can also be carried out at a selected temperature between 400 to 800 degrees Centigrade for 2 seconds ̃1 minute in a laser anneal plate.
As can be seen in the drawings, after anneal, the grains of the copper layer 211′ in the anode and cathode regions as shown in FIG. 8B are much larger than the copper layer 211′′ in the fuse element as shown in FIG. 8C. This is due to the much higher aspect ratio of the fuse element region which prevents Cu grain growth from the top overburden. In a preferred embodiment, a “bamboo” grain structure is grown in the cathode and anode regions while a “polycrystalline” grain structure is grown in the fuse element region. The fine grain structure copper 211′′ has lower EM resistance than the larger grain structure copper 211′, and thus, the fuse element is easier to “blow” during a programming operation. The “bamboo” structure is so called because the grain boundaries are “crosswise” to the length of the trench and the EM-resistance of the copper is further increased. Normal metal grain growth starts in the top overburden area and continues into the bottom patterned features. The driving force to have the grain growth continually through the pattern features is achievable in low aspect ratio features. However, due to thermodynamic related constrains, Cu grain growth cannot continue through the high A/R features, and leaves fine grains inside the small features.
FIG. 9A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 9B and 9C are cross-sectional diagrams depicting the structure after a planarization process and a metal cap layer has been performed according to first embodiment of the invention. The planarization process is preferably a chemical mechanical polishing (CMP) step. Typically, a CMP process uses an abrasive and corrosive chemical slurry (commonly a colloid) in conjunction with a polishing pad. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. As shown, the CMP step has removed the excess copper layer and the liner layer on the dielectric 201 and hard mask 203 outside the trenches. The hard mask 203 is used as an etch stop in a preferred embodiment of the invention. Other planarization processes are known to the art and are used in alternative embodiments of the invention.
The cap deposition and a patterning step has been performed to place a selectively patterned metal cap 213 on the copper 211′, 211′′ in the trench. Suitable materials for the metal cap 213 include Co, W, Rh, Ru and their alloy materials. As above, the deposition of the metal cap 213 can be formed by a conventional deposition process including, for example, CVD, PECVD, ALD, and PVD, sputtering, plating, chemical solution deposition and electroless plating. In preferred embodiments, the metal cap 209 has a thickness from 0.5 nm to 10 nm, with a thickness from 1 nm to 4 nm being more typical. The metal cap 213 can be patterned with a photolithography step.
The purpose of the metal cap 213 is to control the electromigration properties in the copper bulk layer 211′, 211′′. In the crystalline structure within a single grain, because of the uniform lattice structure of the metal ions, there is hardly any electromigration (EM). However, electrons can migrate through the grain boundaries and material interfaces, due to the current is transferred to create more electromigration failure. So in general, there will be more electromigration in the copper with more grain boundaries, i.e. the smaller grains in the fuse element, while the large grained copper in the anode and cathode regions is more EM-resistant. Further, the diffusion processes caused by electromigration can be divided into grain boundary diffusion, bulk diffusion and surface diffusion. Without the metal cap, the electromigration will be dominated by surface diffusion. With the metal cap, only grain boundary and bulk electromigration will take place, and the EM differences between the anode/cathode and fuse element regions will be magnified.
FIG. 10A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 10B and 10C are cross-sectional diagrams depicting the structure after a liner deposition and an aspect ratio reduction layer steps have been performed according to a second embodiment of the invention. As compared to the first embodiment, here a conformal layer of the aspect ratio reduction layer 307 is deposited over the liner layer 305. Hard mask 303 and dielectric 301 layers are also shown. As in the first embodiment, a block out mask 309 over the fuse element region prevents deposition of the aspect ratio reduction layer (see FIG. 10C). Suitable materials for the aspect ratio reduction layer 307 include W, Co, Rh, Ru, Au, Ag and Al. In the first embodiment, electroplating is preferably used to complete the metal fill in FIG. 4B. The second embodiment preferably deposits a thin layer through PVD and then thermal reflow the material into the features, FIGS. 10B, 11B. PVD deposited materials have higher purity than the electroplated ones. Electroplated plated materials normally have carbon impurity>1000 ppm; while PVD deposited ones contain carbon<500 ppm.
FIG. 11A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 11B and 11C are cross-sectional diagrams depicting the structure after reflow of the aspect ratio reduction layer has been performed according to a second embodiment of the invention. In the second embodiment, thermal reflow process is performed to reflow the aspect ratio reduction layer 307 into the bottom of the anode and cathode regions as shown in FIG. 11B. Depending on the material chosen for the aspect ratio layer 307, the reflow temperature will range between 150 to 500 degrees Centigrade.
FIG. 12A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 12B and 12C are cross-sectional diagrams respectively depicting the structure after removal of the block out mask has been performed according to a second embodiment of the invention. As shown, the aspect ratio reducing layer 307 is deposited in the anode and cathode regions but largely absent from the fuse element region. This increases the difference between the aspect ratios between the fuse element and anode/cathode regions.
FIG. 13A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 13B and 13C are cross-sectional diagrams respectively depicting the structure in the anode/cathode and fuse element regions after a copper deposition step has been performed according to the second embodiment of the invention. As described above with respect to the first embodiment, the depth of copper 311 in the anode and cathode regions (FIG. 13B) is less than that of fuse element region wherein the copper fills the entire depth of the trench (FIG. 13C).
FIG. 14A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 14B and 14C are cross-sectional diagrams respectively depicting the structure in the anode/cathode and fuse element regions after an anneal step has been performed according to a second embodiment of the invention. Similar to the first embodiment described above, after anneal, the grains of the copper layer 311′ in the anode and cathode regions as shown in FIG. 14B are much larger than the copper layer 311′′ in the fuse element as shown in FIG. 14C. This is due to the much higher aspect ratio of the trench in the fuse element region. In a preferred embodiment, a “bamboo” grain structure is grown in the cathode and anode regions while a “polycrystalline” grain structure is grown in the fuse element region.
FIG. 15A is a top diagram of an e-Fuse structure to show the orientation of the cross-sectional diagrams. FIGS. 15B and 15C are cross-sectional diagrams respectively depicting the structure after a planarization step and metal cap deposition have been performed according to a second embodiment of the invention. The planarization process is preferably a chemical mechanical polishing (CMP) step. The cap deposition and a patterning step has been performed to place a selectively patterned metal cap 313 on the copper 311′, 311′′ in the trench. Suitable materials for the metal cap 313 include Co, W, Rh, Ru and their alloy materials. As above, the deposition of the metal cap 313 can be formed by a conventional deposition process.
The resulting structure can be included within integrated circuit chips, which can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
While only one or a limited number of features are illustrated in the drawings, those ordinarily skilled in the art would understand that many different types of features could be simultaneously formed with the embodiment herein and the drawings are intended to show simultaneous formation of multiple different types of features. However, the drawings have been simplified to only show a limited number of features for clarity and to allow the reader to more easily recognize the different features illustrated. This is not intended to limit the invention because, as would be understood by those ordinarily skilled in the art, the invention is applicable to structures that include many of each type of feature shown in the drawings.
While the above describes a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary, as alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, or the like. References in the specification to a given embodiment indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic.
In addition, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., used herein are understood to be relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated). Terms such as “touching”, “on”, “in direct contact”, “abutting”, “directly adjacent to”, etc., mean that at least one element physically contacts another element (without other elements separating the described elements).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

## Claims

1. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
depositing a liner layer over the trench structure;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench on the liner layer while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and on the liner layer in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
performing a planarization process to remove excess liner and copper layer over the dielectric layers outside the trench; and
depositing a metal cap layer over the copper layer in the trench in the entire anode, cathode and fuse element regions.

2. The method as recited in claim 1, wherein the large grained copper structure is a bamboo structure and the fine grained structure is a polycrystalline structure.

3. The method as recited in claim 1, wherein the aspect ratio is a ratio of a height of the trench divided by a width of the trench and the difference in aspect ratios between the fuse element region and the anode and cathode regions is greater than 0.5.

4. The method as recited in claim 1, wherein the aspect ratio reducing layer is a conductive material.

5. The method as recited in claim 1, wherein the aspect ratio reducing layer is a high EM-resistance material.

6. The method as recited in claim 1, wherein the aspect ratio reducing layer is selected from the group consisting of W, Co, Rh, Ru, Au, Ag and Al.

7. The method as recited in claim 1, wherein the metal cap layer is selected from the group consisting of Co, W, Rh, and Ru and their alloy materials.

8. The method as recited in claim 1, wherein a cathode is formed in the cathode region, an anode is formed in the anode region and a fuse element is formed in the fuse element region.

9. The method as recited in claim 7, further comprising applying an electric current to the e-Fuse device, wherein the metal cap layer controls the electromigration properties preventing surface diffusion electromigration in the copper layer.

10. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer comprises:
protecting the fuse element region with a block out mask;
depositing the aspect ratio reducing layer in the anode and cathode regions; and
reducing the thickness of the aspect ratio reducing layer using an etch step.

11. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer comprises:
protecting the fuse element region with a block out mask;
depositing the aspect ratio reducing layer in the anode and cathode regions; and
reflowing the aspect ratio reducing layer using a thermal reflow process.

12. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein the Cu layer forms fifty to seventy percent of the thickness of the trench in the anode and cathode regions and a remainder of thickness of the trench in the anode and cathode regions filled by the aspect ratio reducing layer.