# Patent

## Title
System and method for designing system on chip (SoC) circuits by synchronizing a hierarchy of SMDPs

## Abstract

The embodiments herein discloses a system and method for designing SoC by synchronizing a hierarchy of SMDPs. Reinforcement Learning is done either hierarchically in several steps or in a single-step comprising environment, tasks, agents and experiments, to have access to SoC (System on a Chip) related information. The AI agent is configured to learn from the interaction and plan the implementation of a SoC circuit design. Q values generated for each domain and sub domain are stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database. An optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table is acquired and stored in a database for learning and inference. Desired SoC configuration is optimized and generated based on the optimal chip architecture and the generated chip specific graph library.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional application which claims priority from U.S. patent application Ser. No. 15/499,832, filed on Apr. 27, 2017, entitled “SYSTEM AND METHOD FOR DESIGNING SYSTEM ON CHIP (SoC) CIRCUITS THROUGH ARTIFICIAL INTELLIGENCE AND REINFORCEMENT LEARNING”.


BACKGROUND
Technical Field
The embodiments herein is related to apparatuses/systems for designing Integrated Circuits (IC). The embodiments herein is particularly related to apparatuses/systems for designing IC such as system on chip (SoC). The embodiments herein is more particularly related to a system and method for designing system on chip (SoC) using artificial intelligence (AI) and reinforcement learning techniques.
Description of Related Art
System on Chip (SOC) is an integrated circuit (IC) that integrates all the components of an electrical/electronic system into a single chip. The integrated circuit typically comprises digital functions, analog functions, mixed-signal functions and radio-frequency functions inter-alia embedded onto a single chip substrate. The integrated circuit typically includes hardware (for example, microprocessors, and microcontrollers) and also the software necessary for controlling the functionalities and implementation of the hardware.
Typically, SoCs are developed from pre-qualified hardware blocks corresponding to the hardware elements to be included there into, and along with the software drivers that control the functionalities of the said hardware elements. Typically, the hardware elements are assembled using well known Computer Aided Design (CAD) tools, and the corresponding software modules are integrated using an integrated software development environment, subsequent to the finalization of SoC circuit architecture.
The design flow for typical SoC circuits are fragmented and implemented manually. Further, the process of converting a design flow (of a SoC circuit) into a physical design is not free from (design related) errors due to a manual implementation and fragmented nature (of the corresponding design flow). Typically, functional verification (for determining whether the logic design of the SoC circuit confirms to the design specification), which forms a critical part of the transformation from design flow (of a SoC circuit) to physical design, demands the largest pool of resources (in terms of time, manpower inter-alia), due to the complexity of the SoC circuit design as well as the enormity of possible test cases/test scenarios necessary to completely verify the SoC circuit design in its entirety. Typically, the design phase of a SoC circuit involves use of a plurality of discrete tools along with the use of multiple formats and implementation procedures.
Current SoC design process includes the steps of receiving a system specification, architectural design, functional and logic design, circuit design, physical design, physical verification, and fabrication of chip. Further, each process generates data that are highly correlated. At present, there is no system and method available and exist for generalization and learnability of data generated in chip designing process.
The existing process of SoC chip design does not teach about implementing an AI framework into the manual chip design process. AI framework helps in automating the process of chip design, thereby making the design process quick, speedy and efficient. Further, the AI framework helps in learning the data generated during the chip design process.
Hence, there is a need for improving quality of design and time consumed for achieving SoC design circuits, apart from mitigating the risks associated with SoC circuit design process and rendering the (SoC circuit) design process cost effective. Further, there is a need for automating the process of SoC design for improving efficiency due to the complexities associated with the design and implementation of SoC circuits, and the utilization of multiple discrete tools and multiple design formats. Furthermore, there exists a need for a system for learnability, inferencing and prediction from current SoC design for use in future SoC designs.
The abovementioned shortcomings, disadvantages and problems are addressed herein, which will be understood by reading and studying the following specification.
OBJECTIVES OF THE EMBODIMENTS
An object of the embodiments herein is to develop a SoC design framework implemented on the basis of artificial intelligence.
Another object of the embodiments herein is to provide a SoC design framework that employs reinforcement learning techniques to improve the design and implementation of SoC circuit design.
Yet another object of the embodiments herein is to provide an artificial intelligence based framework optimized for SoC design and implementation.
Yet another object of the embodiments herein is to provide a method for learning and inferencing from SoC design that can be used for future designing of SoC.
Yet another object of the embodiments herein is to provide a SoC design framework that automates the process of SoC design and implementation.
Yet another object of the embodiments herein is to provide a SoC design framework by synchronizing a hierarchy of SMDPs.
Another object of the embodiments herein is to provide a SoC design framework that is flexible and modular in construction.
Yet another object of the embodiments herein is to provide a SoC design framework that reduces a risk and uncertainty associated with SoC design and implementation process.
Yet another object of the embodiments herein is to provide a SoC design framework that generates optimal SoC configurations.
Yet another object of the embodiments herein is to provide a SoC design framework that provides easy insights on the architecture of a SoC circuit, and enables easy customization of SoC circuits.
These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
SUMMARY
The embodiments herein discloses a SoC design framework embedded with artificial intelligence and configured to adapt and implement reinforcement learning techniques. The SoC design framework disclosed in the embodiments herein is designed to reduce the complexity in the decision making process associated with design of SoC circuits. The decisions associated with the designing of SoC circuits are multitude and typically heterogeneous in nature. The SoC design framework of the embodiments herein is configured to generalize the multitude of heterogeneous decisions into a plurality of generalized, homogenous decisions, which are in turn utilized to finalize and implement the design for the SoC circuits. The SoC design framework disclosed in the embodiments herein is designed to utilize a combination of artificial intelligence and reinforcement learning principles to arrive at optimal decisions regarding the design and implementation of SoC circuits.
According to an embodiment herein, a method is provided for designing SoC using by synchronizing a hierarchy of SMDPs is disclosed. A chip topology from an SoC specification or a database is initialized. The step of initializing comprises extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library. A plurality of domains and a plurality of subdomains is created by artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library. The artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task. The AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques. A Q values for each domain are generated using AI agent. The AI agent is configured to interact with AI environment through task to extract Q values for each domain. The chip topology is associated to a Markov Decision Process (MDP) with HAM constraints. The chip topology is branched to a plurality of SMDPs or MDPs. The plurality of SMDPs or MDPS are activated. Further, the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-value or a preset objective. The plurality of SMDPs or MDPs are synchronized after termination. A plurality of subdomains at a same level is activated. Further, the plurality of activated subdomains is terminated on achieving a preset Q-value or a preset objective. Thereafter, the plurality of subdomains are synchronized after termination. A physical verification of the plurality of SMDPs or MDPs is initiated. The extracted Q values of each domain and subdomain is stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC. Thus, an optimal chip architecture is acquired for designing SoC. The optimal chip architecture corresponds to a maximum Q value of a top level in the SMDP Q table.
According to an embodiment herein, a backup of each of the plurality of subdomains hierarchically through Hierarchical Deep SMDP network (HDSN). The step of storing the extracted Q values comprises storing Q values in a Q table for leaf level MDPs and options macros.
According to an embodiment herein, in order to achieve the preset Q-value the reinforcement learning techniques is executed and terminated. The reinforcement learning techniques is executed and terminated, when Q value converges below a preset threshold value for each domain or when a change of Q value is reduced below the preset threshold value for each SoC domain. Alternatively, the reinforcement learning techniques is executed and terminated, when a predefined number of episodes is completed for each specific domain. According to an embodiment herein, the reinforcement learning techniques is executed and terminated, when a predefined target performance or predefined exit state is reached for each specific domain. The reinforcement learning techniques is executed and terminated, when a predefined hierarchically optimal state for each domain is achieved.
According to an embodiment herein, the AI agents are configured to feedback the inferences into the graph database and a database which hold Q-values and neural network weights. Examples of AI Agent include but not limited to SoC Noc agent, SoC Power agent, SoC Physical Agent, SoC multiprocessor agent, SoC security agent and SoC clock agent. The AI agent (hereafter referred to as AI agent) is configured to generate Q values for each domain. The AI agent is configured to interact with AI environment through task to extract Q values for each domain. Subsequently, the extracted Q values of each domain and subdomain is stored in a hierarchical SMDP structure is stored in a form of SMDP Q table in a big data database for optimization for planning SoC.
According to an embodiment herein, reinforcement learning process is initiated for each domain to extract Q value. Subsequently, a maximum Q value for each domain is determined through an initialization process of any one of MDPs, SMDPs, and a hierarchy of MDPs. Thereafter, an optimal chip architecture is estimated corresponding to a maximum Q value of a top level in the SMDP Q table. Thereafter, the optimal chip architecture is stored in a database for learning and inference. The desired SoC configuration is generated and optimized based on the optimal chip architecture and the generated chip specific graph library. The step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy.
According to an embodiment herein, a relation between lower level SMDP, MDPs and options macro Q values is determined using the Deep neural network, when Q values of upper level in the Q tables are calculated. The lower level SMDP. MDPs and options macro Q values are related to Q values of the upper level in Q tables. The Deep neural network is selected from a group consisting of a recurrent network, convolutional network, LSTM, GANs and hierarchy of these networks. A Hierarchical Deep SMDP Network (HDSN) is trained or employed for acquiring optimal value of weights for estimating a relationship function between the pluralities of Q values in the Q tables. The optimal values of weights obtained by training are used to determine a process of estimating higher level Q values as a function of lower level Q values in a hierarchical RL setups. The HDSN is further trained or employed to determine a synchronization mechanism between SMDPS at the same level in the hierarchical RL implementation, by determining appropriate level of threshold Q values to terminate one Semi Markov Decision Process (SMDP) and start another SMDP in tandem. According to an embodiment herein, the step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy. Further, a relation between lower level SMDPs, and MDPs is determined using a neural network, when Q values of upper level in the Q tables are calculated.
According to an embodiment herein, the plurality of domains comprises SoC Communication and Network on a Chip, SoC power optimization, SoC clocking, SoC physical design, SoC logic verification, SoC physical verification, SoC timing, SoC DRC (Design Rule check), SoC ERC (Electric Rule check), and SoC Package. The plurality of sub domains comprises SoC throughput optimization, SoC dynamic power optimization, SoC timing optimization, SoC placement optimization, SoC safety features, SoC security features, placement, floorplan, Input/Outputs and routing.
According to an embodiment herein, the step of creating a plurality of domains and a plurality of subdomains AI setup includes configuring the plurality of agents with tasks associated to domains and sub domains. Further, the AI environment is configured to provide rewards and observation to a one or more AI agents. Furthermore, the one or more AI agents are configured to receive a feedback regarding the plurality of domains and sub domains.
According to an embodiment herein, the step of optimizing and generating desired SoC configuration includes initiating a planning process for designing Optimal SoC based on hierarchically optimal SMPDs, MDPs or option macros or a combination of all. Further, a model of MDP, SMDP and options is created using a deterministic or stochastic model selected from a group consisting of lookup table model, Linear expectation model, Linear Gaussian model, Gaussian process model, and Deep Belief network model. Furthermore, a planning and learning process is executed for a plurality of AI domains in parallel by using simulated models that are derived based on real time feedback received from the plurality of AI domains and subdomains. The hierarchical representation of planned SoC is stored in the one or more databases, by storing the learnt information about SoC in a preset format. Thereafter, the planned and stored information about SoC is retrieved from a database hierarchically to debug and create new SoC design from the database.
According to an embodiment herein, the Reinforcement learning process is performed in a single step or hierarchically in a plurality of steps comprising an AI environment, AI Agent, Tasks and experiment, based on access to a plurality of databases stored with a plurality of mutually different data-structures. The plurality of data structures comprises graph, documents and tables. The AI setup is created for each domain in SoC design with a set of environment, agent, task and experiment. The AI setup is configured to execute Reinforcement learning process with interaction of Agent and Environment for each domain and subdomains. A learned information is an output or result of the reinforcement learning process and is stored in a form of Q values or weights of neural in the database which is specific to each domain and subdomain configured in SoC design.
According to an embodiment herein, MDP and SMDP, options macros, HAM and Max-Q values are extracted and storing in a database (for example, NoSQL database, SQL database or graph database) for each domain and subdomain configured in SoC design.
According to an embodiment herein, inferences are generated from extracted SMDP, options macros, MDPs, HAMs, max-Q functions. The generated inferences are stored in the form of document databases, Graph databases or SQL databases. The stored inferences in the form of document databases, Graph databases or SQL databases are loaded into domain specific AI setup in the form of extracted MDPs, SMDPs or options macro or as a set of Environment, Agent, task and experiment in an episodic setup. Each SoC domain AI setup in the form of episodic experiment setup or MDP or SMDP or HAM or MAXQ setup with or without options macros interact with each other to arrive at Optimal Chip Architecture (OCA), when the inferences for each SoC design domain are extracted.
According to an embodiment herein, new policies of mapping state to action are validated for extracted MDPs, SMDPs, options macro, HAMs MAXQ based on policy gradient methods used in Reinforcement learning and storing the validated new policies in the databases for each of AI SOC domains and any AI subdomain in SoC design. The new policies generated in one domain is optimized and iterated with the policies generated in other AI SoC domains to derive context and to obtain hierarchically optimal, multi-domain wise, and subdomain wise optimal policies. The hierarchically optimal and individually optimal policies are stored in the database, through equations, functions, SW, options macros for future use and referred in future learning applications of all AI SoC domains and subdomains.
According to an embodiment herein, synchronization is just one SMDPs communicating with other SMDP, to notify that it has reached terminal state, when SMDPs have no dependency with each other (for example, active power and placement SMDPs). The synchronization is one of a global broadcast signal, to suggest that SMDP reached terminal state. Synchronization process also involves in making the terminated SMDP to upload its end results such as metrics of time closure by timing SMDP or when bugs are found in verification of SMDPs into global database. Alternatively, then each of these SMDPs operate in a lock step or iterative loop when there is a dependency of SMDP on another SMDP. The synchronization process involves a separate sync state when SMDP communicates with other SMDPs (for example, logic Verification and logic design). Each SMDP communicate their end results and wait for bug fixes, optimization and call that design is in decent shape to send it to PD or synthesis. According to an embodiment herein, synchronization includes using two or more SMDPs and sharing end results among many SMDPs, options macro and MDPs.
These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating the preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.



BRIEF DESCRIPTION OF THE DRAWINGS
The other objects, features and advantages will be apparent to those skilled in the art from the following description and the accompanying drawings in which:
FIG. 1 illustrates a flowchart explaining a method for designing SoC by synchronizing a hierarchy of SMDPs, according to an embodiment herein.
FIG. 2 illustrates a flowchart explaining a method for SoC design using an AI driven design setup with hierarchical multi-objective AI, according to an embodiment herein.
FIG. 3 illustrates a block diagram of an Artificial intelligence (AI) logic design set up for each domain and subdomain in the SoC design framework, according to an embodiment herein.
FIG. 4 illustrates a functional block diagram of an AI framework implemented in in the SoC design framework, according to an embodiment herein.
FIG. 5 illustrates a block diagram of an AI framework configured for hierarchical reinforcement learning, according to an embodiment herein.
FIG. 6 illustrates a flowchart explaining an interaction process between main MDP and SMDP in SoC design framework, according to an embodiment herein.
FIG. 7 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on convergence of Q value for each SoC design domain in SoC design framework, according to an embodiment herein.
FIG. 8 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on completing predefined number of experiments for each SoC design domain individually in SoC design framework, according to an embodiment herein.
FIG. 9 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on reaching or achieving predefined target performance or target state for each SoC design domain individually in SoC design framework, according to an embodiment herein.
FIG. 10 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on reaching or achieving predefined hierarchically optimal state or goal derived for each SoC design domain individually in SoC design framework by a top down approach, according to an embodiment herein.
FIGS. 11A and 11B jointly illustrates a flowchart explaining a method of synchronizing a hierarchy of SMDPs in SoC design process, according to an embodiment herein.
FIG. 12 illustrates a top view or a schematic view of a hierarchical Q-tables stored in a SQL schema or document database in SoC design process, according to an embodiment herein.
FIG. 13 illustrates a block diagram or a schematic representation of Deep Neural network used for experience replay in a HDSN in SoC design process, according to an embodiment herein.
FIG. 14 illustrates a functional block diagram of a system for generating an optimal Chip Architecture (OCA) using AI flow of hierarchical Reinforcement learning in SoC design process, according to an embodiment herein.
FIG. 15 illustrates a flow chart explaining a method of extracting MDP for each domain in SoC design process using a reinforcement learning process, according to an embodiment herein.
FIG. 16 illustrates a functional block diagram of a Big data framework in SoC design process, according to an embodiment herein.
FIG. 17 illustrates a flowchart explaining a method of abstracting SoC domains and subdomains in SoC design process, according to an embodiment herein.
FIG. 18 illustrates a block diagram of a database architecture for SoC design, according to an embodiment herein.



Although the specific features of the embodiments herein are shown in some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the embodiments herein.
DETAILED DESCRIPTION OF THE EMBODIMENTS HEREIN
In the following detailed description, a reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.
The embodiments herein discloses a SoC design framework embedded with artificial intelligence and configured to adapt and implement reinforcement learning techniques. The SoC design framework disclosed in the embodiments herein is designed to reduce the complexity in the decision making process associated with design of SoC circuits. The decisions associated with the designing of SoC circuits are multitude and typically heterogeneous in nature. The SoC design framework of the embodiments herein is configured to generalize the multitude of heterogeneous decisions into a plurality of generalized, homogenous decisions, which are in turn utilized to finalize and implement the design for the SoC circuits. The SoC design framework disclosed in the embodiments herein is designed to utilize a combination of artificial intelligence and reinforcement learning principles to arrive at optimal decisions regarding the design and implementation of SoC circuits.
According to an embodiment herein, a method is provided for designing SoC using by synchronizing a hierarchy of SMDPs is disclosed. A chip topology from an SoC specification or a database is initialized. The step of initializing comprises extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library. A plurality of domains and a plurality of subdomains is created by artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library. The artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task. The AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques. A Q values for each domain are generated using AI agent. The AI agent is configured to interact with AI environment through task to extract Q values for each domain. The chip topology is associated to a Markov Decision Process (MDP) with HAM constraints. The chip topology is branched to a plurality of SMDPs or MDPs. The plurality of SMDPs or MDPS are activated. Further, the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-value or a preset objective. The plurality of SMDPs or MDPs are synchronized after termination. A plurality of subdomains at a same level is activated. Further, the plurality of activated subdomains is terminated on achieving a preset Q-value or a preset objective. Thereafter, the plurality of subdomains are synchronized after termination. A physical verification of the plurality of SMDPs or MDPs is initiated. The extracted Q values of each domain and subdomain is stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC. Thus, an optimal chip architecture is acquired for designing SoC. The optimal chip architecture corresponds to a maximum Q value of a top level in the SMDP Q table.
According to an embodiment herein, a backup of each of the plurality of subdomains hierarchically through Hierarchical Deep SMDP network (HDSN). The step of storing the extracted Q values comprises storing Q values in a Q table for leaf level MDPs and options macros.
According to an embodiment herein, in order to achieve the preset Q-value the reinforcement learning techniques is executed and terminated. The reinforcement learning techniques is executed and terminated when Q value converges below a preset threshold value for each domain or when a change of Q value is reduced below the preset threshold value for each SoC domain. Alternatively, the reinforcement learning techniques is executed and terminated, when a predefined number of episodes is completed for each specific domain. According to an embodiment herein, the reinforcement learning techniques is executed and terminated, when a predefined target performance or predefined exit state is reached for each specific domain. The reinforcement learning techniques is executed and terminated, when a predefined hierarchically optimal state for each domain is achieved.
According to an embodiment herein, the AI agents are configured to feedback the inferences into the graph database and a database which hold Q-values and neural network weights. Examples of AI Agent include but not limited to SoC Noc agent, SoC Power agent, SoC Physical Agent, SoC multiprocessor agent, SoC security agent and SoC clock agent. The AI agent (hereafter referred to as AI agent) is configured to generate Q values for each domain. The AI agent is configured to interact with AI environment through task to extract Q values for each domain. Subsequently, the extracted Q values of each domain and subdomain is stored in a hierarchical SMDP structure is stored in a form of SMDP Q table in a big data database for optimization for planning SoC.
According to an embodiment herein, reinforcement learning process is initiated for each domain to extract Q value. Subsequently, a maximum Q value for each domain is determined through an initialization process of any one of MDPs, SMDPs, and a hierarchy of MDPs. Thereafter, an optimal chip architecture is estimated corresponding to a maximum Q value of a top level in the SMDP Q table. Thereafter, the optimal chip architecture is stored in a database for learning and inference. The desired SoC configuration is generated and optimized based on the optimal chip architecture and the generated chip specific graph library. The step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy.
According to an embodiment herein, a relation between lower level SMDP, MDPs and options macro Q values is determined using the Deep neural network, when Q values of upper level in the Q tables are calculated. The lower level SMDP, MDPs and options macro Q values are related to Q values of the upper level in Q tables. The Deep neural network is selected from a group consisting of a recurrent network, convolutional network, LSTM, GANs and hierarchy of these networks. A Hierarchical Deep SMDP Network (HDSN) is trained or employed for acquiring optimal value of weights for estimating a relationship function between the pluralities of Q values in the Q tables. The optimal values of weights obtained by training are used to determine a process of estimating higher level Q values as a function of lower level Q values in a hierarchical RL setups. The HDSN is further trained or employed to determine a synchronization mechanism between SMDPS at the same level in the hierarchical RL implementation, by determining appropriate level of threshold Q values to terminate one Semi Markov Decision Process (SMDP) and start another SMDP in tandem. According to an embodiment herein, the step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy. Further, a relation between lower level SMDPs, and MDPs is determined using a neural network, when Q values of upper level in the Q tables are calculated.
According to an embodiment herein, the plurality of domains comprises SoC Communication and Network on a Chip. SoC power optimization, SoC clocking, SoC physical design, SoC logic verification, SoC physical verification, SoC timing, SoC DRC (Design Rule check), SoC ERC (Electric Rule check), and SoC Package. The plurality of sub domains comprises SoC throughput optimization, SoC dynamic power optimization, SoC timing optimization, SoC placement optimization, SoC safety features, SoC security features, placement, floorplan, Input/Outputs and routing.
According to an embodiment herein, the step of creating a plurality of domains and a plurality of subdomains AI setup includes configuring the plurality of agents with tasks associated to domains and sub domains. Further, the AI environment is configured to provide rewards and observation to a one or more AI agents. Furthermore, the one or more AI agents are configured to receive a feedback regarding the plurality of domains and sub domains.
According to an embodiment herein, the step of optimizing and generating desired SoC configuration includes initiating a planning process for designing Optimal SoC based on hierarchically optimal SMPDs, MDPs or option macros or a combination of all. Further, a model of MDP, SMDP and options is created using a deterministic or stochastic model selected from a group consisting of lookup table model, Linear expectation model, Linear Gaussian model, Gaussian process model, and Deep Belief network model. Furthermore, a planning and learning process is executed for a plurality of AI domains in parallel by using simulated models that are derived based on real time feedback received from the plurality of AI domains and subdomains. The hierarchical representation of planned SoC is stored in the one or more databases, by storing the learnt information about SoC in a preset format. Thereafter, the planned and stored information about SoC is retrieved from a database hierarchically to debug and create new SoC design from the database.
According to an embodiment herein, the Reinforcement learning process is performed in a single step or hierarchically in a plurality of steps comprising an AI environment, AI Agent, Tasks and experiment, based on access to a plurality of databases stored with a plurality of mutually different data-structures. The plurality of data structures comprises graph, documents and tables. The AI setup is created for each domain in SoC design with a set of environment, agent, task and experiment. The AI setup is configured to execute Reinforcement learning process with interaction of Agent and Environment for each domain and subdomains. A learned information is an output or result of the reinforcement learning process and is stored in a form of Q values or weights of neural in the database which is specific to each domain and subdomain configured in SoC design.
According to an embodiment herein, MDP and SMDP, options macros, HAM and Max-Q values are extracted and storing in a database (for example, NoSQL database, SQL database or graph database) for each domain and subdomain configured in SoC design.
According to an embodiment herein, inferences are generated from extracted SMDP, options macros, MDPs, HAMs, max-Q functions. The generated inferences are stored in the form of document databases, Graph databases or SQL databases. The stored inferences in the form of document databases, Graph databases or SQL databases are loaded into domain specific AI setup in the form of extracted MDPs, SMDPs or options macro or as a set of Environment, Agent, task and experiment in an episodic setup. Each SoC domain AI setup in the form of episodic experiment setup or MDP or SMDP or HAM or MAXQ setup with or without options macros interact with each other to arrive at Optimal Chip Architecture (OCA), when the inferences for each SoC design domain are extracted.
According to an embodiment herein, new policies of mapping state to action are validated for extracted MDPs, SMDPs, options macro, HAMs MAXQ based on policy gradient methods used in Reinforcement learning and storing the validated new policies in the databases for each of AI SOC domains and any AI subdomain in SoC design. The new policies generated in one domain is optimized and iterated with the policies generated in other AI SoC domains to derive context and to obtain hierarchically optimal, multi-domain wise, and subdomain wise optimal policies. The hierarchically optimal and individually optimal policies are stored in the database, through equations, functions. SW, options macros for future use and referred in future learning applications of all AI SoC domains and subdomains.
According to an embodiment herein, synchronization is just one SMDPs communicating with other SMDP, to notify that it has reached terminal state, when SMDPs have no dependency with each other (for example, active power and placement SMDPs). The synchronization is one of a global broadcast signal, to suggest that SMDP reached terminal state. Synchronization process also involves in making the terminated SMDP to upload its end results such as metrics of time closure by timing SMDP or when bugs are found in verification of SMDPs into global database. Alternatively, then each of these SMDPs operate in a lock step or iterative loop when there is a dependency of SMDP on another SMDP. The synchronization process involves a separate sync state when SMDP communicates with other SMDPs (for example, logic Verification and logic design). Each SMDP communicate their end results and wait for bug fixes, optimization and call that design is in decent shape to send it to PD or synthesis. According to an embodiment herein, synchronization includes using two or more SMDPs and sharing end results among many SMDPs, options macro and MDPs.
FIG. 1 illustrates a flowchart explaining a method for designing SoC by synchronizing a hierarchy of SMDPs, according to an embodiment herein. According to the embodiments herein, the entire SoC circuit along with the processor, digital design, circuit design process is represented in the form of a hierarchical model (with emphasis on optimality) subsequent to implementation of reinforcement learning experiments.
The method involves receiving a SoC specification input (101). Further, the chip design (of SoC) is initialized by extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library. The Initialization of the SoC chip design flow includes library initialization (102). In Library initialization process, standard libraries like technology libraries from foundry, standard interface IP from AI SOCD database, processor IPs from database and other standard IPs which are reused are loaded into chip database. These libraries are pulled together into chip database after parsing the SoC specification input. The Soc specification input is at least one of a specification of the chip or a database which represents the previous chip plus the change in description in text or xml format. The pulled in libraries and the specific SoC specification or database provide an IO, chip skeleton, relevant IPs and partition the chip. Subsequently, a plurality of domains and a plurality of subdomains is created by artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library (103). The artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task. The AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques. The Q values for each domain are generated using AI agent. The AI agent is configured to interact with AI environment through task to extract Q values for each domain (104). The chip topology is associated to a Markov Decision Process (MDP) with HAM constraints. The chip topology is branched to a plurality of SMDPs or MDPs. The plurality of SMDPs or MDPS are activated (105). Further, the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-value or a preset objective. The plurality of SMDPs or MDPs are synchronized after termination (106). A plurality of subdomains at a same level is activated. Further, the plurality of activated subdomains is terminated on achieving a preset Q-value or a preset objective. Thereafter, the plurality of subdomains are synchronized after termination.
A physical verification of the plurality of SMDPs or MDPs is initiated. The extracted Q values of each domain and subdomain is stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC (107). Subsequently, a maximum Q value for each domain is determined through an initialization process of any one of MDPs, SMDPs, and a hierarchy of MDPs. Thereafter, an optimal chip architecture is estimated corresponding to a maximum Q value of a top level in the SMDP Q table (108). Thus, an optimal chip architecture is acquired for designing SoC. Thereafter, the optimal chip architecture is stored in a database for learning and inference. The desired SoC configuration is generated and optimized based on the optimal chip architecture and the generated chip specific graph library (109). The step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy.
According to an embodiment herein, a backup of each of the plurality of subdomains hierarchically through Hierarchical Deep SMDP network (HDSN). The step of storing the extracted Q values comprises storing Q values in a Q table for leaf level MDPs and options macros.
According to an embodiment herein, in order to achieve the preset Q-value the reinforcement learning techniques is executed and terminated. The reinforcement learning techniques is executed and terminated when Q value converges below a preset threshold value for each domain or when a change of Q value is reduced below the preset threshold value for each SoC domain. Alternatively, the reinforcement learning techniques is executed and terminated, when a predefined number of episodes is completed for each specific domain. According to an embodiment herein, the reinforcement learning techniques is executed and terminated, when a predefined target performance or predefined exit state is reached for each specific domain. The reinforcement learning techniques is executed and terminated, when a predefined hierarchically optimal state for each domain is achieved.
According to an embodiment herein, the multi-objective AI agents is configured to feedback the inferences into the graph database and a database which hold Q-values and neural network weights. The database which stores the inferences/learnt data is used for “transfer learning” process. The “Transfer learning” process is defined as a process in which the learnt task is transferred to similar tasks which are not learnt, but are estimated using transferred learning means, when a set of logically close tasks are learnt already. Examples of multi objective Agent include but not limited to SoC Noc agent, SoC Power agent, SoC Physical Agent, SoC multiprocessor agent, SoC security agent and SoC clock agent. The multi-objective AI agent (hereafter referred to as AI agent) is configured to generate Q values for each domain (104). The AI agent is configured to interact with AI environment through AI task to extract Q values for each domain.
According to an embodiment herein, the extracted Q values of each domain and subdomain in a hierarchical SMDP structure are stored hierarchically in a form of SMDP Q table in a big data database for optimization of SoC design planning process. In order to extract Q value, reinforcement learning process is initiated for each domain. The domain is any one of a NoC generation, Power optimization, Interface integration, Logic Verification, Logic synthesis, Pre layout timing closure, Physical design, post Layout timing closure and Physical verification.
FIG. 2 illustrates a flowchart explaining a method for SoC design using an AI driven design setup with hierarchical multi-objective AI, according to an embodiment herein. The SoC specification input is received (210). An abstract graph database libraries are created to store details regarding a chip design technology and standards involved and required for a chip designing process. Further a chip design knowledge library and a generic hardware and software libraries are also created and maintained (211). The details regarding chip, chip skeleton, clock. Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library or graph database library. A chip design (of SoC) is initialized based on the extracted details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library or graph database library. (212). After initialization, AI are setup for various domains in the form of MDPs, SMDPs, HAMs and MAX-Q to further optimize and generate desired SoC configuration. The AI setup represents a Multi objective AI agent. The AI setup for a domain includes multi-objective AI agents with environment, and a plurality of tasks. The AI setup for a domain is executed and repeated for a plurality of domains such as first domain, second domain, and a third domain (213, 214, 215). Then a multi objective AI environment, agents and tasks are set up by compiling the data received from the AI set up for the plurality of domains (216). The chip specific graph library and database is generated using AI environment based on the output data received from a multi objective AI environment, agents and tasks. Further, data stored in the chip specific graph library and database is fed to the AI set up for the plurality of domains in a feedback loop (217). The multi-objective AI agent for a chip is configured to generate Q values for each domain. The AI agent is configured to interact with AI environment through task to extract Q values for each domain. Subsequently, the extracted Q values of each domain and subdomain in a hierarchical SMDP structure are stored hierarchically in a form of SMDP Q table in a big data database for optimization of SoC design planning process. Further an optimal chip architecture is obtained from the optimal Q value (218).
According to an embodiment herein, a combination of HAMs, options and Max-Q learning is used to achieve end to end SoC design framework. Max-Q learning involves categorizing the entire SoC design into a hierarchy of SMDPs, for acquiring a Q value or learning a solution simultaneously across the plurality of SMDPs. In the Max-Q learning process, the core SMDP □ is divided into a plurality of sub tasks {M0, M1, M2, M3, . . . MN}, Solving for M0, solves the entire M. Instead of classic definition of Max-Q, where set M are tasks, they are recursive Max-Q, with HAM like constraints according to the embodiments herein. Each one of M0, M1, M2, . . . MN represents another Max-Q recursively.
According to an embodiment herein, a relation between a lower level SMDP, MDPs and options macro Q values is determined using a Deep Neural Network, when Q values of the upper level in the Q tables are calculated. The lower level SMDP, MDPs and options macro Q values are related to Q values of the upper level in the Q tables. The Deep neural network is selected from a group consisting of a recurrent network, convolutional network, LSTM. GANs and hierarchy of these networks. Further, a Hierarchical Deep SMDP Network (HDSN) is trained for acquiring an optimal value of weights for estimating a relationship function between the pluralities of Q values in the Q tables. The optimal values of weights are obtained by training the neural network. The optimal values are used to determine a process of estimating higher level Q values as a function of lower level Q values in a hierarchical RL setups. The HDSN is further trained or employed to determine a synchronization mechanism between SMDPS at the same level in the hierarchical RL implementation, by determining an appropriate level of threshold Q values to terminate one Semi Markov Decision Process (SMDP) and start another SMDP in tandem.
According to an embodiment herein, each of the SoC domains, i.e., Network On Chip (NoC) generation, power optimization, interface integration, logic verification, logic synthesis, pre layout timing closure, physical design, post layout timing closure and physical verification, are configured to implement (execute) an algorithm, such as, greedy algorithm or a tuned greedy algorithm, to balance the exploitation and exploration thereof. Subsequently the learning is estimated based on the number of inferences drawn from each SoC domain, when the Q values converge, or when a predetermined number of experiments are completed, or predetermined Quality of Results (QoR) standards are met. Corresponding new policies (which are a resultant of learning) for mapping ‘state’ to ‘action’ are devised and stored in domain specific databases. New policies learnt in a particular domain are optimized and combined/iterated with the policies learnt in other relevant domains, and hierarchically relevant, optimal policies are generated. Typically, new policies learnt in one domain are optimized and iterated with the policies learnt in other AI SoC domains to derive a context and to obtain hierarchically optimal, multi-domain wise, and sub domain wise optimal policies. Such hierarchically relevant, optimal policies are generated based on at least one of policy based methods, value based methods and actor-critic method of reinforcement learning. The learning methods implemented across SoC domains include DQN, linear functions, windowing functions, regression functions, and value function approximation. Hierarchically optimal and individually optimal policies are stored in the database in the form of equations, functions, SW, options macros to be reused and referred in future learning applications of all AI SoC domains and sub domains.
According to an embodiment herein, the model of environment along with options are constructed for each SoC domains and the corresponding sub domains, using the interaction with the AI environment, and in line with the accuracy required for each domain and sub domain. Supervised Reinforcement Learning principles are utilized for constructing a training model for each SoC domain and sub domain. The training model is any one of a lookup table model, linear expectation model, linear Gaussian model, Gaussian process model or any other similar deterministic or stochastic model that is designed or configured to model the MDP, SMDP and option macros together.
FIG. 3 illustrates a block diagram of an Artificial intelligence (AI) logic design set up for each domain and subdomain in the SoC design framework, according to an embodiment herein. The Artificial intelligence (AI) logic design set up for each domain and subdomain in the SoC design framework is configured to execute a hierarchical Reinforcement Learning (RL) process or technique using options, MAXQ framework. HAM and any other similar techniques. The Markov Decision Process (MDP) is derived for the main SoC design initially, with the MDP executing the hierarchical tasks. The domain specific Q-values or neural weights are utilized to extract Markov Decision Process (MDP) or Semi Markov Decision Process (SMDP) or option macros or HAM or Max-Q values. Subsequently, the extracted values are stored in domain-specific databases. The extracted SMDPs or MDPs, HAMs or option macros or Max Q-values are utilized to generate inferences pertinent to SoC circuit design, which are in turn loaded on a domain specific Artificial Intelligence setup, thereby initiating an interaction between the inferences and generating an Optimal Chip Architecture (OCA).
With respect to FIG. 3, an artificial intelligence logic design setup 220 comprising an artificial intelligence logic design task 222 and an artificial intelligence logic design agent 225. The Artificial Intelligence (AI) design task 222 comprising an artificial intelligence logic design environment 224 is configured to interact with the AI logic design agent 225, to make observations, initiate appropriate actions and subsequently receive rewards for the (performed) actions. The AI logic design agent 225 is designed as a learner module to learn from the interactions with the AI logic design environment 224. The AI logic design agent 225 is configured to perform various actions in the AI environment 224 to acquire or collect observations and rewards from the AI logic design environment 224 for the executed/performed actions/operations.
FIG. 4 illustrates a functional block diagram of an AI framework implemented in in the SoC design framework, according to an embodiment herein. With respect to FIG. 4, the AI framework 303 for chip design process receives input from a generic hardware IP block 301, generic software IP block 302. The AI framework is configured to provide optimal chip design. The optimal chip design is provided for Application software development 304 and software testing 305. Further, the optimal chip design undergoes hardware/software verification on the application prototype 306. The optimal chip design is provided for prototype IC fabrication 307. After verification, the optimal chip design is sent for volume IC fabrication 308.
FIG. 5 illustrates a block diagram of an AI framework configured for hierarchical reinforcement learning, according to an embodiment herein. With respect to FIG. 5, the multi objective AI is Multi objective reinforcement learning agent is designed and configured to learn from an interaction with environment based on the inputs received from the sample chip description file 501 after performing an initialization process 502. The example of Chip multi objective Agent includes but not limited to SoC Noc agent 503, SoC Power agent 504, SoC Physical Agent 505, SoC multiprocessor agent 507, SoC security agent and SoC clock agent 506. AI Framework is so modular in design that a plurality of similar agents is added and plugged them to AI environment and big data database called alpha DB. A Big data inference engine 512 is configured to interact with the plurality of Multi objective reinforcement learning agents 503, 504, 505, 506, 507 to receive inferences for storing into libraries 510 after performing a verification process with a verification agent 509. The output of the reinforcement learning agents are fed to GDS (Graphic Database System) and drivers 508 for planning SoC design.
According to an embodiment herein, the AI frame work comprises SoC Communication and Network on a Chip (NoC) module for connecting a plurality of blocks to one another thereby establishing connection and integration of SoC. The NoC is implemented using a SoC communication AI agent 503.
According to an embodiment herein, the SoC Power optimization module is loaded with techniques for optimizing various power components of the SoC such as leakage and dynamic power and decreasing effects of ageing in hardware due to electron migration on hardware performance using a SoC Power Agent 504.
According to an embodiment herein, SoC clocking module is a domain for clock design of entire SoC, and involves global and local optimization of clocking using a SoC clock Agent 506. This also involves estimating and clock tree optimization.
According to an embodiment herein, SoC Placement and Floor plan is arrived at optimally. SoC Placement and Floor plan includes placement of logic blocks according to reinforcement learnt algorithms and policy. SoC Placement and Floor plan includes power Island creation but is not limited to coming up with policies to optimize timing and power through placement.
According to an embodiment herein, SoC Physical design is carried out, by mapping logical design onto physical libraries of cells which contains information like power, physical layout of transistors, physical delay format and physical power routing using a SoC Physical Agent 505.
According to an embodiment herein, SoC logic verification module is configured to verify chip logic using verification agent 509. The verification process involves using various verification process and collecting metrics for reporting bugs to improve quality of SoC and provide confidence in functionality of SoC.
According to an embodiment herein, SoC physical Verification module is designed to verify the physical implementation of the SoC using verification agent 509. The verification process involves a verification of LVS Vs DRC, post layout timing, routing, IR drop, Power feature correctness, Electric rule check. Further, various policies are explored in this domain to provide optimal tradeoff for physical design (of the SoC circuit) considering all these factors.
According to an embodiment herein, SoC timing module is designed for executing pre-layout and post-layout timing closure. Timing closure involves taking particular actions and policies like solving setup time and hold time, assigning false paths.
According to an embodiment herein, SoC DRC (Design Rule check). SoC ERC (Electric Rule check) are designed and configured to learn, apply and plan ERC and DRC closure policies using deep reinforcement learning techniques.
According to an embodiment herein, packaging related policies and actions are learnt in a SoC Packaging process. The policies related to substrate design, pin-muxing, padding, power ball assignments, possible PCB load on I/O pins and the like. Policies for selecting type of packages are also learnt at the end of all tasks in this domain.
FIG. 6 illustrates a flowchart explaining an interaction process between main MDP and SMDP in SoC design framework, according to an embodiment herein. With respect to FIG. 6, the AI framework is configured to perform hierarchical Reinforcement Learning (RL) process using MDP, options, MAXQ framework, HAM and any other similar techniques. The Markov Decision Process (MDP) is derived from the SoC design specification initially. Since, SoC design requires continuous tasks for long time without making decisions, Semi Markov Decision Process (SMDP) is used rather than MDP. The main MDP or multiagent support for Soc design is created (520). The Main MDP is divided into a plurality of SMDPs that correspond to a plurality of domains in SoC design (520a, 520b, . . . 520n). For each domain, a plurality of subdomains are created (521a, 521b, . . . 521n). Each subdomains is configured to execute Reinforcement learning algorithm to obtain a plurality of option macros (522a, 522b, . . . 522n). Option/macros are used in arriving at optimal chip Architecture (OCA).
According to an embodiment herein, the SMDPs are configured to focus on closed loop action over an extended period, which is called as options macros. In SoC design, many decisions are extended over a period of time, in a closed loop format. Hence, the AI framework is designed to use option macros in SoC design activities. The options macros is applied to smaller hierarchical tasks to form HRL. The option macros are applied across SoC AI subdomains to acquire a human level intelligence in designing the SoC. The Options macros include a generalization of primitive actions to include temporally extended actions. For example, the process of fixing a setup time violation involves tasks such as retiming data path, buffering clock path, changing the VT type of the cells in the path, reflow planning and the like. Each of these tasks is included as options macro which is extended in time with closed feedback loop with EDA tools.
According to an embodiment herein, options macros or options are used in arriving at optimal chip Architecture (OCA). Each options includes a policy π: S×A→[0, 1]. Termination condition β: S+→[0, 11], and Initial state 1 ⊂ S. The option is defined by the triplet parameters [π, β, 1]. Some of the options are also derived from a past experiment of the AI setup, by storing the triplet in the database and slightly altering the policy. Policy is a mapping between the option and the following action. By slightly modifying the policy, distribution of action that needs to be taken is obtained. Further, the agent includes a chain of actions. The agent initiates another action, once the selected option is terminated using SMDP transitions. The Options macros is one of a Markov or semi-Markov with a specific timeout mechanism. Thus, the option macros are used for iterative optimization part of OCA, for example floorplan and placement optimization with respect to timing closure issue or verification test case that has long run time and is run by the agent to prove verification coverage of the design.
According to an embodiment herein, the AI framework incorporates SMDPS implemented with max-Q and Hierarchies of Abstract Machines (HAM) framework to achieve faster and most optimal architecture and design closure for SoC. The SMDPs deploy Max-Q framework and HAMs. These are Semi-Markov Options (SMO). SMO indicates that the options represents more detailed states than available to policy that selects the options. Further, HAMs are used to place constraints on the policy learnt by agent SMDPs for policy improvement. Furthermore, the HAMs are used to apply constraints across hierarchy of SMDPs. Each SMDP domain has its own HAM to provide constraints about mapping of higher level SMDP tasks to lower level SMDP tasks in a hierarchy. Also HAM provides ways to relate hierarchy of SMDPs. Since SoC design is always hierarchical, HAMs play large role in determining optimal RL algorithm to be applied across hierarchy of designs (from IP way up to SoC top) and hierarchy of tasks (from extracting optimal chip specification to optimal chip architecture (OCA) to GDSII tape out to layout). According to an embodiment herein, the HAMs are used to derive constraints for SMDPs and relation between low level and higher level tasks.
According to an embodiment herein, HAMs contain four states as used in this invention to call AI subdomain SMDPs. These states are run in all SMDPs or MDPs to determine when to call next SMDPs MDPs and option macros. According to an embodiment herein, the AI framework includes AI SOCD Action states, AI SOCD Call states, AI SOCD Choice states, AI SOCD Stop states. The AI SOCD Action states execute an action in the AI SOCD hierarchical environment. Further, AI SOCD Call states execute another AI SOCD HAM or SMDP as a subroutine. AI SOCD Choice states non-deterministically select a SMDP of AI SOCD. AI SOCD Stop states halt execution of the machine and return control to the previous call state. A top level hierarchy of the AI SOCD HAM or SMDP is the chip top agent and it calls all other agents with domain specific HAMs. Each of the HAM based SMDP is multi objective with vectored rewards, actions and Q values.
According to an embodiment herein, the SoC design framework includes the following modules/domains:
SoC Communication and Network on a Chip (NoC): This module connects blocks to one another thereby establishing connection and integration of SoC and is implemented using a SoC communication AI agent. In this sub domain, main goal of single or multiple agents represented by single or multiple SDMPs (Which can be Max-Q, HAMs or options implementation) is to create optimal communication. This SOC AI subdomain comprises environment which provides rewards and observation to single or multiple type agents. Rewards and observation is related to ease of communication among SoC end points (Masters and slaves, where example master is a processor and slave is a memory port or a configuration interface). Single or multiple agents are configured to receive feedback from environment regarding reduction in latency, Power consumption, increase in throughput of the system, optimal communication topology (NoC topology), decrease in congestion of the physically designed chip as positive reward for a given action like buffering the datapath, retiming the data path, regrouping the masters and slave into a cluster, creating power islands and rerouting the connectivity wires through dedicated channel to decrease congestion. Furthermore this domain is configured to create and discover polices as combination of these actions and implement them to obtain optimal SoC communication architecture. These AI SOC domain NoC agents are configured to interact with NoC environment to extract MDP, Implement policy gradient, store resulting Q values in the Big database and plan the optimal SoC communication structures
SoC Power optimization: The module incorporates techniques used in optimizing various power components of the SoC such as leakage and dynamic power and decreasing effects of ageing in hardware due to electron migration on hardware performance using a SoC Power Agent. SoC Power optimization subdomain involves environment which is configured to provide a feedback to an agent regarding a reduction or increase in power consumption based on agent actions. This AI SOC subdomain contains one or more power agents, which are configured to provide the balance between performance and various power components. Environment is configured to provide a feedback on performance measures like throughput, clock frequency and power consumption measures like leakage power and dynamic power of a particular block or entire SoC. This AI SOCD subdomain is configured to implement further hierarchy of Max-q framework with HAM constraints to optimize SoC power consumption per performance. Actions taken by agents are clock gating, power collapsing a block, partitioning the SoC, power rail redesign etc. These AI SOC domain Power agents are configured to interact with Power environment to extract MDP, Implement policy gradient, store resulting Q values in the Big database and plan the optimal Power structures
SoC clocking is a domain for clock design of entire SoC, which involves global and local optimization of clocking using a SoC clock Agent. This also involves estimating and clock tree optimization.
The SoC clocking AI SOC subdomain has environment which is configured to provide a feedback on number of PLLs required, estimated clock power, clock routing congestion and possible issues with clock skew. This AI SOC domain with one or many agents is configured to take actions of inserting PLLs, Clock generation logic (CGL), clock gating and clock programming register implementation. These AI SOC domain clock agents are configured to interact with clock environment to extract MDP, Implement policy gradient, store resulting Q values in the Big database and plan the optimal clocking circuitry
SoC Placement and Floor plan: in this domain SoC floor plan is arrived optimally. It includes placement of logic blocks according to reinforcement learnt algorithms and policy. It includes power island creation, it includes (but is not limited to) coming up with policies to optimize for timing and power through placement.
SoC Placement and Floorplan AI SOC Domain is configured to implement the Placement and Floorplan environment, which as hooks to Floorplan and placement EDA tools. The Environment is configured to use Floorplan and Placement EDA tools as databases and wraps around them to obtain different rewards and observation like congestion, timing, routing channels available, routing utilization and Quality of results (QoR), which may be in tool specific format, but is converted to AI framework generic format so that the AI framework is portable across the EDA vendors. This AI SOC domain is designed to implement one or more subdomains according to HAM and Max-Q implementation as explained. Each subdomain is also configured to implement one or more agents to derive optimal placement and floorplan. The actions taken by agents include, but not limited to moving the sub blocks in the design, adding buffers, reshaping the sub blocks and timing closure of the design, interaction with other AI SoC domain to obtain optimal QoR for placement and SoC floor planning.
SoC Physical design: In the domain SoC Physical design is carried out, including mapping logical design onto physical libraries of cells which contains information like power, physical layout of transistors, physical delay format and physical power routing using a SoC Physical Agent. SoC Physical design AI SoC domain is configured to implement environment to provide observation and reward for physical design quality such as routing congestion, timing, power analysis, power routing. This AI SoC domain is configured to implement multiple sub domains related to physical design for mapping logical design to technology library. It is also configured to implement one or more agents to take actions such as buffering, altering power routing, inserting power switches, inserting clock gates, retiming the data path, removing or adding additional PLLs. Agents are also configured to interact with other AI SoC domains and sub domains to obtain optimal SoC Physical design. Further this AI SoC domain and its sub domains are configured to implement the hooks to various EDA tools to obtain generic format of the observation from a tool specific format.
SoC logic verification: The module involves verifying chip logic using verification agent. The verification process involves various verifications and collecting metrics and reporting bugs to improve quality of SoC and provide confidence in functionality of SoC. SoC logic verification AI SoC domain is configured to implement the environment, to provide observation about bugs found in the design, verification coverage, test case failure, assertion failures, inferring debug log. This AI SoC domain is also configured to implement one or more sub domains according to Max-Q, HAM and options frame work to obtain the verification closure of the SoC. Each AI SoC subdomain of this AI SoC domain is configured to implement one or more agents to take actions such as generating test cases using libraries of test function, running test cases with functional simulator EDA tool, debug actions such as reading verification log files, Coverage log files, fixing the design bug and accessing databases to store Q-values at the end of each testing. There are multiple Q values that reflect the amount of verification done, number of bugs getting closed after an action such as test case generation. Also design bug fixing is done by a separate bigger SMDP in implementing Max-Q, options or HAM or combination hybrid. Also the agents related to this AI SOC domain and its sub domain are configured to interact with other AI SOC domains like top level SoC MDP via database to obtain verified optimal SoC circuit and close the verification highest coverage possible. This AI SoC domain is configured to implement hooks to various EDA Functional simulator and debug tools to obtain the information observation like code coverage, assertion coverage and start and end of a test case.
SoC physical Verification: The module verifies the physical implementation of the SoC using verification agent. The verification process involves verification of LVS Vs DRC, post layout timing, routing, IR drop, Power feature correctness, Electric rule check. Further, various policies are explored in this domain to provide optimal tradeoff for physical design (of the SoC circuit) considering all these factors.
SoC Physical Verification AI SoC domain is configured to implement environment to provide observation about the LVS, DRC errors, logs, post layout timing, IR Drop and QoR of physical design. These observations are obtained by environment from the EDA tools which is further processed to generate generic format from tool specific format and fed as reward or observation to agent. This AI SoC domain is configured to implement the multiple AI SOC subdomain, options macros via hybrid MAX-Q and HAM framework. Actions taken by agents of each of these subdomains include, but not limited to remapping libraries, reporting the error ERC errors and obtaining standard fix from database, updating Q values to the database.
SoC timing: The domain involves pre-layout and post-layout timing closure. Timing closure involves taking particular actions and policies like solving setup time and hold time, assigning false paths, etc. SoC Timing AI SoC domain has a main objective to close timing of the SoC. Timing violation includes setup and hold violation, false paths, multicycle paths and general exceptions. The environment of Timing closure AI domain, which is hooked to timing closure tool to provide rewards and observation about setup time violation, hold time violation, total negative slack, and in worst case negative slack and cross talk violations. The AI SoC Timing agents are configured to contain one or more levels of Max-Q recursive structure implemented with hybrid HAM constraints described previously. This AI SoC domain and its sub domain are configured to implement Agents, whose main actions are to fix the setup and hold violation by retiming, redesigning data paths and balancing Clock trees. Each of these actions are implemented as options as well.
SoC DRC (Design Rule check), SoC ERC (Electric Rule check): In this domain, ERC and DRC closure policies are learnt, applied and planned using deep reinforcement learning techniques. SoC DRC/ERC AI subdomains are configured to implement efficient fixing of the ERC violations like Floating gnd nets and unconnected VDD/VCC pins, Shorts of Power nets, power domain crossing without a proper level shifter and isolation cells. DRC violations includes, spacing rules between metals, minimum width rules, via rules, another set of rules are LVS rules, which ensures Layout that is generated is equivalent to netlist that is generated before physical design. It checks for shorts, opens and circuit parameter mismatch. This AI SoC domain is configured to implement the hierarchical Max-Q framework with HAM constraints as suggested above. This AI SoC domain is also configured to implement the one or more agents which are configured to take actions to fix floating grounds by connecting them, corrects shorted VDD to remove shorts by separating shorts. They are configured to take action to fix the LVS violations by fixing floating nets, correcting parameters of the layout, so become equivalent to netlist. Agents are also configured to take actions to fix DRC, such that the spacing between metals are provided according to design rules and width of the routes are set according to definition of the process rules.
SoC Package: In this domain, packaging related policies and actions are learnt. Policies related to substrate design, pin-muxing, padding, power ball assignments, possible PCB load on I/O pins and the like. Policies for selecting type of packages are also learnt at the end of all tasks in this domain. SoC Package AI SOC domain involves in providing optimal package, I/O, substrate design. This AI SoC domain is configured to implement environment which is hooked to I/O models, I/O cell libraries, Substrate models. PCB models, pad-ring configuration and pin-muxing. The environment is configured to provide the feedback, observations and rewards about I/O constraints being met, substrate constraint being met or not met, I/O models being functionally competent or qualified to meet the I/O load and drive requirement, capability of I/O cell in meeting the DRC, current and transient characteristic required to drive the load on the board as well sink in current from board components. It also gives observation about scenarios involved in the 1/O usage like concurrency on pin-muxing to provide optimal utilization of I/Os.
According to an embodiment herein, the aforementioned domains are implemented using the AI framework. Each domain is configured to incorporate an AI logic design environment, AI logic design agent, AI logic design task, AI logic design experiment. The SoC design framework envisaged by the embodiments herein aims to extract the learning from the experimentation of all the aforementioned modules, and stores the learning results in a database, preferably in the form of Q-values or neural network weights or a lookup table, or in any other appropriate format. For example, Q-values are derived from the Bellman's equation for policy iteration. Alternatively, Q-values are also derived from the options or macros or HAM or Max-q methods and stored in the database for deriving the MDP.
Typically, Q-Values are construed as action value functions, which provide the value of particular state for an action given a policy π. Q-values are defined by the function

qπ(s,a)=Eπ[Gt|St=s,At=a]

Where qπ are Q values, Gt is total reward for the policy from state ‘s’ and action ‘a’, St and At are state and action space. The Q-values are generated in the learning process and stored on the database as program variables. Apart from the value function defining the total value from state ‘s’, the policy π is defined as

Vπ(s)=Eπ[Gt|St=s]

Values with or without value function approximation are stored in the local program variable or separate database at the end of learning process.

According to an embodiment herein, Reinforcement Learning (RL) algorithm terminates for each SoC domain at the convergence of Q-values below a preset threshold value. Alternatively, the Reinforcement Learning (RL) algorithm is terminated on completion of predefined number of experiments/episodes. Further, the Reinforcement Learning (RL) algorithm is terminated once it reaches a predefined target performance or exit state. Examples of predefined state include predefined throughput target of NoC (Network on a Chip) in inter-chip Communication domain setup or predefined power numbers of the dynamic power of the chip, or predefined clock skew, or predefined number of clocks. Yet the Reinforcement Learning (RL) algorithm is terminated when a predefined hierarchically optimal goal or state is reached.
FIG. 7 illustrates a flowchart illustrating the steps involved in termination of Reinforcement Learning (RL) algorithm on convergence of Q value. According to an embodiment herein, reinforcement learning is initiated by an AI setup with a plurality of domains corresponding to the SoC design (601). Further, domain AI setup is done with domain specific AI agents, domain specific environment, and domain specific tasks. The domain AI are setup in form of MDPs, SMDPs, HAMs and MAX-Q for the initialized, compiled and non-optimized chip database to further optimize and generate desired SoC configuration. Further, AI experiment setup is done for each SoC domain. The AI experiment setup includes configuring each SoC domain to implement (execute) an algorithm, such as, greedy algorithm or a tuned greedy algorithm, to perform the exploitation and exploration (602). Subsequently, the domain specific AI agent is configured to interact with the domain specific environment via AI task to extract Q values pertaining to a specific domain. Further, the extracted Q values are stored in a database/big data (603). The process is continued for each domain until the Q values is converged, or rates of change of Q value is below a preset threshold λ (604). The learning is estimated based on the number of inferences drawn from the Q values of each SoC domain. Accordingly new policies which are a resultant of learning are devised/derived and stored in domain specific databases. New policies learnt in a particular domain are optimized and combined/iterated with policies learnt in other relevant domains, and hierarchically relevant, optimal policies for planning SoC are generated (605).
FIG. 8 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on completing predefined number of experiments or episodes for each SoC design domain individually in SoC design framework, according to an embodiment herein. According to an embodiment herein, reinforcement learning is initiated by an AI setup with a plurality of domains corresponding to the SoC design (701). Further, domain AI setup is done with domain specific AI agents, domain specific environment, and domain specific tasks. The domain AI are setup in form of MDPs, SMDPs, HAMs and MAX-Q for the initialized, compiled and non-optimized chip database to further optimize and generate desired SoC configuration. Further. AI experiment setup is done for each of the SoC domains. The AI experiment setup includes configuring each SoC domain to implement (execute) an algorithm, such as, greedy algorithm or a tuned greedy algorithm, to perform the exploitation and exploration (702). Subsequently, the domain specific AI agent interacts with the domain specific environment via AI task to extract Q values pertaining to a specific domain. Further, the extracted Q values are stored in a database/big data (703). The Reinforcement Learning (RL) algorithm is terminated on completion of predefined number of experiments/episodes (704). The learning is estimated based on the number of inferences drawn from the Q values of each SoC domain. Corresponding new policies which are a resultant of learning are devised/derived and stored in domain specific databases. New policies learnt in a particular domain are optimized and combined/iterated with policies learnt in other relevant domains, and hierarchically relevant, optimal policies for planning SoC are generated (705).
FIG. 9 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on reaching or achieving predefined target performance or target state for each SoC design domain individually in SoC design framework, according to an embodiment herein. According to an embodiment herein, reinforcement learning is initiated by an AI setup with a plurality of domains corresponding to the SoC design (801). Further, domain AI setup is done with domain specific AI agents, domain specific environment, and domain specific tasks. The domain AI are setup in form of MDPs, SMDPs, HAMs and MAX-Q for the initialized, compiled and non-optimized chip database to further optimize and generate desired SoC configuration. Further, AI experiment setup is done for each of the SoC domains. The AI experiment setup includes configuring each of the SoC domain to implement (execute) an algorithm, such as, greedy algorithm or a tuned greedy algorithm, to perform the exploitation and exploration (802). Subsequently, the domain specific AI agent interacts with the domain specific environment via AI task to extract Q values related to a specific domain. Further, the extracted Q values are stored in a database/big data (803). The Reinforcement Learning (RL) algorithm is terminated on reaching predefined target performance or exit state (804). The learning is estimated based on the number of inferences drawn from the Q values of each SoC domain. Corresponding new policies which are a resultant of learning are devised/derived and stored in domain specific databases. New policies learnt in a particular domain are optimized and combined/iterated with policies learnt in other relevant domains, and hierarchically relevant, optimal policies for planning SoC are generated (805).
FIG. 10 illustrates a flowchart explaining a method of terminating Reinforcement Learning (RL) process on reaching or achieving predefined hierarchically optimal state or goal derived for each SoC design domain individually in SoC design framework by a top down approach, according to an embodiment herein. According to an embodiment herein, reinforcement learning is initiated by an AI setup with a plurality of domains corresponding to the SoC design (901). Further, domain AI setup is done with domain specific AI agents, domain specific environment, and domain specific tasks. The domain AI are setup in form of MDPs. SMDPs, HAMs and MAX-Q for the initialized, compiled and non-optimized chip database to further optimize and generate desired SoC configuration. Further, AI experiment setup is done for each SoC domain. The AI experiment setup includes configuring each SoC domain to implement (execute) an algorithm, such as, greedy algorithm or a tuned greedy algorithm, to perform the exploitation and exploration (902). Subsequently, the domain specific AI agent interacts with the domain specific environment via a task to extract Q values pertaining to a specific domain. Further, the extracted Q values are stored in a database/big data (903). The Reinforcement Learning (RL) algorithm is terminated on reaching preset hierarchically optimal state (904). The learning is estimated based on the number of inferences drawn from the Q values of each SoC domains. Corresponding new policies which are a resultant of learning are devised and stored in domain specific databases. New policies learnt in a particular domain are optimized and combined/iterated with policies learnt in other relevant domains, and hierarchically relevant, optimal policies for planning SoC are generated (905).
FIGS. 11A and 11B jointly illustrates a flowchart explaining a method of synchronizing a hierarchy of SMDPs in SoC design process, according to an embodiment herein. The method includes initializing a chip topology from a specification or a database (1101). Further, the chip topology is associated to a Markov Decision Process (MDP) with HAM constraints (1102). Subsequently, the chip topology is associated to a plurality of SMDPs or MDPs. The plurality of SMDPs or MDPs are activated (1103). Thereafter, the plurality of SMDPs or MDPs are synchronized when the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-values or a preset objective (1104). A plurality of subdomains at a same level is activated (1105). The plurality of activated subdomains is terminated on achieving a preset Q-values or a preset objective (1106). Further, the plurality of subdomains is synchronized, when the plurality of activated subdomains is terminated on achieving a preset Q-values or a preset objective (1107). The subdomains which are dependent on synchronized subdomains are activated (1108). The dependent subdomains are terminated after achieving a preset objective (1109). Subsequently, a physical verification of the plurality of SMDPs is initiated (1110). Physical verification process is terminated after achieving a preset goal number of experiments (1111). Thereby, an optimal chip architecture for designing SoC is obtained. The chip design are stored in GDS (Graphic Database system) and forwarded to foundry for chip manufacturing 1112.
According to an embodiment herein, synchronization is done by making just one SMDPs to communicate with other SMDP, that it has reached terminal state, when one SMDP does not depend on another SMDP (for example, active power and placement SMDPs). The synchronization is one of a global broadcast signal, suggesting that SMDP has reached terminal state. The terminated SMDP also is configured to upload its end results such as metrics of time closure by timing SMDP or when bugs are found in verification SMDPs into global database. Alternatively, each SMDP is operated in a lock step or iterative loop, when one SMDP depends on another SMDP. Each SMDP communicates with other SMDPs in a separate synchronization state, (for example, logic Verification SMDP and logic design SMDP). Each SMDP communicate their end results and wait for bug fixation, optimization and call that design is in decent shape to send it to PD or synthesis.
According to an embodiment herein, two or more SMDPs are involved in a synchronization process and the end results are shared among a plurality of SMDPs, options macro and MDPs.
FIG. 12 illustrates a top view or a schematic view of a hierarchical Q-tables stored in a SQL schema or document database in SoC design process, according to an embodiment herein. The AI framework is configured to perform a hierarchical backup to AI SOCD top level SMDP from leaf level options macros or MDPs. The HAM frame work of states is used to synchronize SMDPs, when one SMDP calls other SMDP during a calls state of HAM constraints.
According to an embodiment herein, the entire SoC design is modified based on a Max-Q Framework. The SoCD 1201 is the top level SoC design task, which is decomposed into SocD0, SoCD1, SoCD2, . . . SoCDN. Each of these SocD are mapped to a plurality of AI SoC domain 1201a, 1201b. 1201c, 1201d. In an example, a root task SoCD implements a policy π, and the hierarchy of tasks {SocD0, SoCD1, SoCD2, . . . SoCDN} is used to implement the policies {π0, π1, π2, . . . πN}, which collectively represents the policy π. Further, each domain is divided into further sub domains 1202a, 1202b, 1202c to implement a hierarchy of policy and SMDPs like recursive Max-Q, HAMs or end point options/macros 1204.
According to an embodiment herein, the SMDP Q-learning is applied across AI framework using SoCD subdomains. Q values are given by




  
    
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Where Qπ (i,s,a) is Q value following policy πi of the ith SMDP,

Vπ is the value function at the state S, with action a, following policy π, and

Piπ is the transition probability to next state following policy π

According to an embodiment herein, storage of Q-value and usage are very much different because of recursive structure of Max-Q framework. Different Q-Values are generated at each level of SMDP. So equation for Q value is given by:




  
    
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where i1, i2, i3 . . . in are introduced by iterative SMDPs involved, and n denotes nth level of Q value. As millions of levels of SMDPs are involved and there are billions of Q values, the Q values are stored in the database. The database has a capacity of 100s peta bytes to enable in combining and obtaining final Q value of a current SoC design.

Final Q value of top level SMDP will be of the form:

Qπ(s,a)=Vπ(a,s)+Σs′,tpπ(s′,τ|s,a)γτQπ(s′,π(s′))

The Q value is a function of Q values of all the hierarchical SMDP Q values at a given state of top level SMDP. The Q value functions require scaling each reward before performing the summation. The scaling factor of all other Q value is determined by Deep neural net (DNN).
With respect to FIG. 12, the Q values of Hierarchical SMDP structure is stored in a Table based Databases (such as MYSQL and MSSQL) or a document based databases (such as NOSQL, Mongodb) or graph databases. Each database include a foreign key or a pointer which points to child SMDP Q-Values. Further, the top level SMDPs Q values depend on a maximum of Q values of the lower level SMDPs from the state of entry. The process of mapping top level SMDP Q values to lower level Q values continues down the hierarchy until the lowest level MDP or options macro is reached. The top level SMDP Q values is given by the following equation:

Qπ(s,a)top SMDP)=Σgi(φ)*f(max{Qiπ(s,a)})

where gi(φ) and f( ) are obtained using training on a Deep neural network and Qiπ(s,a)) is ith level Q value of a child SMDP.

According to an embodiment herein, the deep neural network is a Hierarchical Deep SMDP Network (HDSN) or Deep Max-Q network or Deep HAM networks. In HDSN (unlike DQN), the experience replay is hierarchical, where one or more Deep neural networks are used to obtain the relation between SMDPs and further to obtain relation function approximation between different Q values. In HDSN, then experience replay is used to obtain relation between different SMDPs Q value.
FIG. 13 illustrates a block diagram or a schematic representation of Deep Neural network used for experience replay in a HDSN in SoC design process, according to an embodiment herein. The HDSN is used to obtain a relation between different SMDPS in the hierarchical AI. Further, the HDSN is configured to obtain relation function approximation between different Q values.
According to an embodiment herein, the SMDP Q values obtained from the lower level SMDP tables are passed through DNN to obtain higher level Q values. Thus, DNN is used for transforming the Lower level Q values to higher level SMDP Q values. Further, the hierarchy of Q value are networked through DNN. Different network configurations are used at different level of SMDP. OCA (Optimal Chip architecture) is defined as the collection of Q tables. SMDPs, Relation between them across all hierarchy. Optimal Chip Architecture (OCA) corresponds to a maximum Q value of the top level SMDP.
According to an embodiment herein, the maximum Q value of top level SMDP is obtained across the AI SOC domain. The AI SoC domain is further decomposed into a recursive Max-Q framework or called through HAM choice states or a combination of Max-Q and HAM. For example, front end integration of the SoC is purely a decomposition of MAX-Q value function, while bottom up synthesis is a HAM, which calls for a synthesis of different states or sub block synthesis after the completion of synthesis of one module level. Max-Q is also used in functional verification, in which whole chip verification value function is split into hierarchical tasks of block level verification, top level verification. The verification process is performed to ensure that a block level verification is completed. Thus, the AI SOC design is split into a number of SMDPs to achieve the maximum Q value for top level SMDP, and OCA is obtained from the maximum Q value at the top level SMDP.
FIG. 14 illustrates a functional block diagram of a system for generating an optimal Chip Architecture (OCA) using AI flow of hierarchical Reinforcement learning in SoC design process, according to an embodiment herein. According to an embodiment herein, a chip architect optimizer based on AI hierarchical Reinforcement learning is configured to receive input from application software specification 1401, component cost metrics 1402, component performance metrics 1404, software function via a System Description Language (SDL) 1403, and hardware function via a Chip Description Language (CDL) 1405. The chip architect optimizer 1406 is further configured to perform Chip communication optimization, Chip I/O optimization, Chip placement optimization, Chip DFT/DFD optimization, and Chip verification optimization. Finally, an optimal chip architecture 1407 is generated.
FIG. 15 illustrates a flow chart explaining a method of extracting MDP for each domain in SoC design process using a reinforcement learning process, according to an embodiment herein. According to an embodiment herein, a trial and error learning of environment is executed with a plurality of single step actions. Each step action is associated to a state (1410). The execution of steps is terminated after N iteration. The value function (V) and Q values for each episode/step are stored in a database (for example, alpha DB) for each SMDPs (1412). States are identified as a major variation in value functions and q values, like Architecture performance or results when interacting with EDA tools (1413). Sample States from N steps are obtained to form MDP, with some probability distribution of transitions (1414). MDP refined and Convergence seen to optimal Q values. Thereafter, a backup is conducted to obtain value function and action values of top level MDP (1415). The MDP is refined and converged to obtain optimal Q values (1416). Thus, a top level MDP is finalized (1417).
FIG. 16 illustrates a functional block diagram of a Big data framework in SoC design process, according to an embodiment herein. Reinforcement learning is carried out hierarchically using Hierarchical reinforcement learning or Deep Hierarchical reinforcement learning or any methods of reinforcement learning that involves learning from environment and planning the Chip architecture from learnt data (1601). The learnt data is stored in database. The stored data include Q values, SMDP Action-value table, value functions, neural network weights used for function approximation, and relation between SMDPs (1602). The stored data is retrieved for learnt information on SoC. Using the stored data, AI planning of the SoC is performed by deriving various MDPs, SMDPs, options macros, HRL structures like HAM and Max-Q (1603). The planned SoC information is stored for future reuse. The planned stored include SoC information like plurality of MDPs, SMDPs planned, HRL structures, OCA, and inferences (1604).
FIG. 17 illustrates a flowchart explaining a method of abstracting SoC domains and subdomains in SoC design process, according to an embodiment herein. A new specification for electronics systems design is obtained from using learnt information and inferences stored in Big data processor (1700). Big data processor (1700) receives and uses the board level PCB information from old and existing PCB design. It uses machine readable format of existing component specification and Learnt information from SoC design from database. The big data processor (1700) is configured to receive and utilize big data for chip function (1701), big data for component performance (1702), Big Data for customer requirements and business intelligence (1703), Big Data on process and technologies nodes (1704), Real time information retrieval and technology research (1705).
By combining learnt information, the big data processor 1700 is configured to provide insight regarding new electronics systems. Other information that is used by Big data processor are cost of components, quality and availability. Output of big data processor contains the estimation of cost of new electronics components 1706, component performance 1707, application software specification 1708, CDL 1709, and SDL 1710, applications and target customers who may be interested in SoC targeted to new electronics system.
FIG. 18 illustrates a block diagram of a database architecture for SoC design, according to an embodiment herein. With respect to FIG. 18, the database scheme for generating AI based SoC chip design comprises CDL parser 1801, relational database 1802, Input Output ring and chip boundary 1803, graph database 1804, physical database 1805, and chip topology 1806.
A new specification for electronics systems design is obtained from using learnt information and inferences stored in Big data processor. Big data processor uses board level PCB information from old and existing PCB design. It uses machine readable format of existing component specification and Learnt information from SoC design from database. By combining learnt information, the big data processor provides an insight of new electronics systems. Other information that is stored into Big data processor are cost of components, quality and availability. Output of big data processor contains the estimation of cost of new electronics systems, applications and target customers who are interested in SoC targeted to new electronics system.
According to an embodiment herein, several new policies are learnt during experimentation and several options are discovered, and applied in designing the SoC architecture and circuits. Once all SMDP Q tables are filled with optimal Q values and the associated DNN is configured to approximate the relation function between SMDPs hierarchy, the optimal SoC arch is derived from top level SMDP. SoC architecture involves getting PoR SoC correct, which is done through feature SMDP sub domain. Then it requires selecting correct IP and internal connection through Power domain arch, NoC arch and Design partitioning, clocking that are mapped to each AI SoC subdomain. Optimal policies are learnt based on the stored Q values. Future SoC circuit is obtained from trained database.
The technical advantages include the realization of a SoC design and implementation framework that incorporates artificial intelligence and is capable of implementing the principles of reinforcement learning. The SoC design framework of the embodiments herein mitigates the risks and uncertainty associated with the design of SoC circuits. Further, the SoC framework allows the circuit designers to proactively experiment with the architecture of SoC circuits, in addition to enabling them to explore previously unexplored design spaces. Further, the SoC design framework disclosed by the embodiments herein, also reduces the occurrence of bugs therein while enhancing the creativity associated with SoC circuit design. Further, the SoC framework also enables the circuit designers to gain insights on the design of SoC circuits while enabling them to experiment with the (SoC circuit) design architecture. Further, the SoC design framework also reduces the turnaround time associated with the design and implementation of SoC circuits.
The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such as specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments.
It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modifications. However, all such modifications are deemed to be within the scope of the claims.

## Claims

1. A computer implemented method comprising computer-readable instructions stored on a non-transitory computer readable storage medium and executed on a computing device comprising a hardware processor and a memory for designing SoC by synchronizing a hierarchy of SMDPs, the method comprises:
initializing a chip topology from an SoC specification or a database, wherein the step of initializing comprises extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library;
creating a plurality of domains and a plurality of subdomains artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library, and wherein the artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task, wherein the AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques;
generating Q values for each domain using AI agent, wherein the AI agent is configured to interact with AI environment through task to extract Q values for each domain;
associating the chip topology to a Markov Decision Process (MDP) with HAM constraints;
branching the chip topology to a plurality of SMDPs or MDPs;
activating the plurality of SMDPs or MDPS, and wherein the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-value or a preset objective;
synchronizing the plurality of SMDPs or MDPs after termination;
activating a plurality of subdomains at a same level, and wherein the plurality of activated subdomains is terminated on achieving a preset Q-value or a preset objective;
synchronizing the plurality of subdomains after termination;
initiating a physical verification of the plurality of SMDPs or MDPs;
storing the extracted Q values of each domain and subdomain in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC; and
acquiring optimal chip architecture for designing SoC, wherein the optimal chip architecture corresponds to a maximum Q value of a top level in the SMDP Q table.

2. The method as claimed in claim 1, further comprises performing a backup of each of the plurality of subdomains hierarchically through Hierarchical Deep SMDP network (HDSN).

3. The method as claimed in claim 1, wherein the step of storing the extracted Q values comprises storing Q values in a Q table for leaf level MDPs and options macros.

4. The method as claimed in claim 1, wherein the step of achieving a preset Q-values comprises:
executing reinforcement learning process for each domain and each SoC domain, and wherein the reinforcement learning process for each domain is terminated, when Q value converges below a preset threshold value for each domain, and wherein the reinforcement learning process for each SoC domain is terminated, when a change of Q value is reduced below the preset threshold value for each SoC domain;
executing reinforcement learning process for each specific domain, and wherein the reinforcement learning process for each specific domain is terminated, when a predefined number of episodes is completed for each specific domain;
executing reinforcement learning process for each specific domain, and wherein the reinforcement learning process for each specific domain is terminated, when a predefined target performance or predefined exit state is reached for each specific domain; and
executing reinforcement learning process for each domain, and wherein the reinforcement learning process for each domain is terminated, when a predefined hierarchically optimal state for each domain is achieved.

5. The method as claimed in claim 1, wherein the step of synchronizing the plurality of subdomains further comprises triggering execution of a second subdomain after the completion of a first sub domain.

6. The method as claimed in claim 1, wherein the plurality of domains comprises SoC Communication and Network on a Chip, SoC power optimization, SoC clocking, SoC physical design, SoC logic verification, SoC physical verification, SoC timing, SoC DRC (Design Rule check), SoC ERC (Electric Rule check), and SoC Package.

7. The method as claimed in claim 1, wherein the plurality of sub domains comprises SoC throughput optimization, SoC dynamic power optimization, SoC timing optimization, SoC placement optimization, SoC safety features, SoC security features, placement, floorplan, Input/Outputs and routing.

8. The method as claimed in claim 1, wherein the step of acquiring an optimal chip architecture from the maximum Q value comprises deriving optimal policies associated with the optimal Q value, and executing actions associated with the derived optimal policy.

9. The method as claimed in claim 1, wherein a relation between lower level SMDPs, and MDPs is determined using a neural network, when Q values of upper level in the Q tables are calculated.