# Patent

## Title
Miniaturized dielectrically isolated solid state device

## Abstract

An improved, surface-passivated and electrically isolated solid-state device (including integrated circuits) comprises a silicon wafer with a PN junction or other electronic rectifying barrier contained therein and thermally grown or ion-implanted oxide or nitride isolating grooves in-situ formed in the wafer to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

## Background
This is a continuation of parent application Ser. No. 07/809,460 filed Dec. 9, 1991 (abandoned), which in turn is a continuation-in-part (CIP) of application Ser. No. 07/438,692 filed Nov. 17, 1989 (U.S. Pat. No. 5,082,793), which in turn is a CIP of application Ser. No. 05/838,758 filed Oct. 3, 1977 (U.S. Pat. No. 4,916,513) and a continuation of application Ser. No. 05/386,102 filed Aug. 6, 1973 (U.S. Pat. No. 4,946,800), each of the latter two being a CIP of application Ser. No. 05/154,300 filed Jun. 18, 1971 (abandoned), which in turn is a CIP of application Ser. No. 04/761,646 filed Sep. 23, 1968 (U.S. Pat. No. 3,585,714), which in turn is a CIP of application Ser. No. 04/490,955 filed Sep. 28, 1965 (U.S. Pat. No. 3,430,109). I hereby incorporate each of the above patents and patent applications by reference into this application. Also related are application Ser. No. 08/446,423 filed May 22, 1995 (U.S. Pat. No. 5,696,402), and copending applications Ser. Nos. 08/483,937 and 08/483,938 each filed Jun. 7, 1995, each of the latter three being a CIP of pending application Ser. No 08/313,350 filed Sep. 27, 1994, which in turn is a CIP of application Ser. No. 07/816,626 filed Dec. 9, 1991 (abandoned) and said application Ser. No. 07/809,460 filed Dec. 9, 1991.


BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuit structures and specifically in the field of dielectrically isolated and surface-passivated integrated circuit structures.
Solid-state devices in general and semiconductor devices in particular must have exacting surface properties for successful operation. These devices therefore often fall by surface failure mechanisms. The surface of a PN, p+n, p−n, PN+, pi, ni, metal-oxide, metal-semiconductor, oxide-semiconductor, interfacial rectifying barrier region, or other optoelectromagnetically active signal-translating region (including several coacting, closely spaced rectifying barriers) is especially sensitive to the ambients or contacting materials, contaminants, impurities, or submicon floating or rubbing dust particles. While not limited thereto, the invention is herein mostly described as examples applied to semiconductor devices each having a PN junction as its optoelectromagnetically active region.
My U.S. Pat. No. 3,585,714 describes new methods for simultaneously achieving device isolation, junction surface passivation, novel differential expansion of the junction region peripheral surface in integrated circuits, exposure of material hidden underneath the junction, high-density integrated circuits with round-bottomed, intersecting and isolating grooves, and/or greatly expanded peripheral surface for optoelectrical communication or for the otherwise difficult or impossible yet large (relative to the junction width) electrical contacts. Many advantages are thus obtained including: increased yield; decreased coast; improved junction region surface passivation; complete device isolation; increased packing density in integrated circuits; increased switching speed; reduced nose, instability, leakage current, and electrical shorts; improved breakdown voltage or other device characteristics; controlled carriers generation, movement, and recombination at or near the junction region peripheral surface, and regulated optoelectromagnetic interaction of the active region with the ambient or contacting material.
The same issued U.S. patent describes fully the techniques of selective material removal by mechanical, chemical, or particles bombarding means to achieve differentially expanded junction region peripheral surface particularly in integrated microcircuits. Such a surface is resistant to mobile ions, floating particles, and even micron-size rubbing contaminants and, hence, greatly reduces surface failures of the device. However, such a surface, being bare, is still not perfectly passivated. Surface layers of inert materials must, therefore, be applied or added onto the differentially expanded peripheral surface for added protection. The same patent also teaches the in-situ formation techniques of the isolating grooves made by thermal oxidation or nitridation and ion-implanted oxygen or nitrogen ions.
Unfortunately, these surface layers are far from being perfect or even inert, but are often full of pinholes, microcracks, and other defects. In addition, as pointed out in the issued patent U.S. Pat. No. 3,585,714, these layers must, at the same time, be both thick (but non-flaking) for good protection and yet thin (but non-cracking) for reduced mismatch stresses. They must also be permanently, chemically, and fairly continuously yet firmly bonded to the underlying solid-state materials and, therefore, cannot always or in all respects, be inert or neutral. These layers may, for example, be chemically active by introducing contaminants, diffusants, unwanted impurities, or chemical reactants. They may also be physically active by creating intolerable mismatch stresses and strains, microcracks, dislocations, or other physical defects in the solid state device materials. These layers may even be electronically active by providing unwanted dopants, carrier traps, barrier regions, shorting paths, or inductively-coupled and capacitively-coupled surface streaks or films.
SUMMARY OF THE INVENTION
Therefore, to overcome the foregoing and other difficulties, the general object of this invention is to provide an improved, surface-passivated solid state device having very small geometries.
An object is to provide a semiconductor device with the peripheral surface of its PN junction region uniquely buried in and surrounded by discretely spaced-apart, inert material regions and not just thin (typically 4000 A), continuous surface layers.
It is another object of the invention to provide a semiconductor device with an expanded, or differentially expanded, junction region peripheral surface similarly buried in, and surrounded by, metallurgically continuous inert material layers or regions.
Yet another object is to provide a semiconductor device with an enclosing isolation oxide region having a unique geometry, size, and position relative to the PN junction so as to achieve novel effects.
A further object is to form high-density, high-yield, but low-cost silicon integrated circuits with dielectrically isolated circuit components.
Another object of the invention is provide dielectrically isolated integrated circuits with chemically formed or ion-implanted oxide or nitride isolating grooves.
Still another object is to provide methods for low-cost, high-volume production of these new semiconductor devices. Various other objects and advantages, and a more complete understanding of the invention, will become apparent to those skilled in the art from the following description and claims, taken in conjunction with the accompanying drawing.



DESCRIPTION OF THE DRAWING
For the purpose of illustrating the invention, there is shown in the drawing the forms which are particularly preferred. It is understood, however, that this invention is not necessarily limited to the precise arrangements and instrumentalities here shown but, instead, may combine the same described embodiments or their equivalents in various forms.
FIG. 1 is a partial cross-section of a semiconductor device having therein a curved-around, junction region peripheral surface and a gas-filled isolation groove;
FIG. 2 shows portion of a silicon structure having a partly buried, PN junction region peripheral surface in contact with a round-bottomed, discretely in-situ formed silicon dioxide (or nitride) material region.
FIGS. 3a and 3b shows semiconductor devices having their PN junction region peripheral surfaces completely buried in intrinsic, or electronically inert, semiconductor materials;
FIG. 4 shows npn transistor structure in a microcircuit made by discretely in-situ formed, oxide isolation region and three-dimensional dopant diffusion;
FIG. 5 shows a high-power laser device having its buried, PN junction region peripheral surface differentially expanded for improved cooling results.
FIG. 6 is a top view of a monolithic microcircuit containing a system of normally intersecting, gas, nitride, or oxide-filled grooves;
FIG. 7 is a cross-section of the device of FIG. 6, taken along the line 7—7; and
FIG. 8 is a cross-section of a “universal integrated circuit” showing the unique circuit structure.



DESCRIPTION OF THE PREFERRED EMBODIMENTS
The PN junction devices of FIGS. 1-3 are sufficiently disclosed in my issued patent No. 3,585,714. They are being redescribed herein. A PN junction is substantially electrically nonconductive under an applied reverse bias. The electrical signal current through a PN junction is controlled by mobile carriers in the form of electrons and holes.
With reference to FIG. 1, there is shown a single-crystalline, device wafer comprising a PN junction (transition, or depletion) region 11 of appreciable thickness, t, formed between a p-type, single-crystalline silicon silicon substrate 13 and an n-type doped, epitaxial silicon layer 12 grown thereon. That the junction region 11 has finite thickness is shown by, e.g., Transistor Engineering by A. B. Phillips, McGraw Hill Co., N.Y., 1962, pp. 111 and 115. A cylindrical groove 14 of radius r is made into and past the junction region 11, which is defined by its upper and lower end or boundary planes, 15 and 16, respectively. The peripheral surface 17 of the junction region 11 is distinctly curved and curved-around. That is, the surface has two opposing sides each containing more than one distinct slope across the thickness direction. Notice that when the groove has a curved or round bottom, which is symmetrical with respect to the bisecting longitudinal plane 19 such as is shown in FIG. 1, the peripheral surface expansion is infinite at the lowest point G, but decreases gradually, and equally on both sides thereof, toward the transversally-expanding, higher level positions. Since I am illustrating the invention typically with a case where r=1 cm and t=1 um, it is only necessary to read the fourth column of Table 1 in my U.S. Pat. Nos. 3,430,109 and 3,585,714. In addition, since the groove must pass through the PN junction region to function as dielectrically isolating grooves, the maximum depth hm, i.e., groove bottom G below the PN junction, must be positive. Hence, only the lower five numbers in the fourth column of Table 1 in the patents are relevant. Four of these five numbers show that the total or integrated surface expansion for the entire 1-um junction region is 141.4, 103.6, 58.58, and 30.19 if the bottom of the cylindrical groove G is located at 0, 0.1, 1.0, and 5.0 microns, respectively, below the lower end plane 16 of the PN junction 11.
As shown in my patent U.S. Pat. Nos. 3,430,109 and 3,585,714, microscopically precise grooves or material regions may be formed by special mechanical grinding or polishing with feedback control (each of '109 and '714 @ FIG. 1), precision chemical etching ('714, column 12, lines 34-60), and aligned or focused ion, electron, or laser photons interacting with or activating the surface silicon atoms for achieving thermal evaporation (atom separation) or surface activation ('714, column 11, lines 23-58). These energetic beam processing procedures were particularly suitable, as of the 1965 filing date of my '109 patent, for forming tiny grooves of no more than 2-micron widths, with high precision in accordance with the techniques disclosed in my '109 and '714 patents. Each of the grooves can be narrow but deep ('714, column 9, line 16), and its lower surface can be generally cylindrically shaped ('714, column 9, lines 16-19 and line 70 to column 10, line 8, and FIGS. 5 and 6). The grooves may be at least partly filled (by deposition, thermal oxidation or ion implantation) with an electrically insulating matter, including oxides of silicon which are formed intentionally and in a controlled manner rather than by natural and incidental oxidation of a silicon surface newly exposed to the ambient. These large surface expansions cannot be reproducibly made by the conventional beveling technique, if at all possible. The groove 14 in FIG. 1 also contains a smaller groove 18 therein on its left side. For a smaller radius r, the surface expansion is smaller. But so is also the chip real-estate occupied by the groove or device.
This groove 14 has a bottom of zero width, achieving particularly high miniaturization for a given device feature size, in contrast with the loss of real estate due to the use of a central flat area flanked by rounded corners resulting from known previous processes such as diffusion. The central flat portion of the groove bottom present in known prior art devices appears to wastefully occupy chip real estate and, in grooves filled with solid matter (FIG. 2), may generate harmful stresses and related problems such as carrier mobility problems as discussed in my prior patents and applications. As shown in U.S. Pat. Nos. 3,430,109 and 3,585,714, the bottom G of the groove 14 may be within a few microns (even one or 1/2 microns) below the lower end plane 16 of the PN junction region 11. The elongated (cylindrical) groove 14 may be parallel to the same junction plane 16 and have its bottom line at G coinciding therewith (hm=0). The groove 14 may be purposely tilted relative thereto so that the same groove may be above the junction plane 16 at some places, substantially coincide therewith at another place, but lie below the same plane at other places, as disclosed in the patents.
While a linearly or curvedly sloping surface on the device peripheral surface is useful to achieve surface expansion of the junction region, a U-shaped or V-shaped, or turn-around peripheral surface is necessary to allow high-density packing in integrated circuits. Such U-shaped or V-shaped peripheral surfaces also form the all-important gas or solid dielectric isolating grooves. The geometry, size, material composition, formative conditions, and position (relative to the PN junction) of these grooves are very critical and will be more fully described in this specification.
The device of FIG. 2 is made, in a way preferred according to certain criteria, by selectively thermally growing an oxide groove, band, or material region 21 of depth ho transversely into a single-crystalline p-type silicon substrate 22. This is followed by in-diffusion of n-type dopants from the top surface 23. Such a diffusion is automatically guided by the inner peripheral surface of the oxide region and is, therefore, self-aligning. The masking step is non-critical. Further, the lateral area of the resultant PN junction is microscopically precisely predetermined. The result of this diffusion is the (top) doped, n-type epitaxial silicon layer 24 and the new PN junction region 25 of thickness t and maximum depth (during service) hj that does not exceed ho for many preferred embodiments. For other special applications, hj may exceed ho. See U.S. Pat. No. 3,585,714.
The PN junction 25 may be formed prior to or during the oxidation step. Notice that the differentially expanded, junction region peripheral surface 26 is surrounded by the inert oxide material region 21. Further, this oxide region electrically isolates the two sides of the device. These two sides can, therefore, be used as two independent, electrically isolated but physically integral diodes. Each of the two diodes comprises a top n-type, epitaxial layer 24, a bottom p-type substrate 22 and a PN junction region 25 therebetween. This PN junction 25 thus extends both in the common substrate or buried layer 22 and the top layer 24. These diodes share the same p-type substrate, which electrically connects the silicon pockets 24L and 24R that would otherwise be electrically isolated. They are, therefore, physically integral or non-independent; but electrically independently operable with respect to the biasing voltage applied to, and the signal translation therein, the respective PN junctions 25.
For example, while the left 24L/22 diode may be forward biased through suitable contacts such as 29L and 28, the right 24R/22 diode may be forward biased also (through contacts 29R and 28) but at a completely different voltage, may be zero-biased, or may even be reverse-biased. In this electrical sense, the two diode components of the integrated circuit devices of FIGS. 1 and 2 are isolated and independent. And this is made possible by the gas or solid oxide-filed groove (14 or 21) at the side thereof and the isolating PN junction (11 or 25) thereunder.
Dopant diffusion or introduction, electrical contacting, and controlled epitaxial layer growth are well known in the semiconductor art. If needed, additional PN junctions, e.g., 25b and 25e, may be formed in the device of FIG. 2 (See also FIGS. 4 and 8), and the various layers suitable connected to form completely isolated diodes, transistors, tetrodes.
Note that the device of FIG. 2 is not a complete device as clearly shown by the curved, cut-out lines on both the left and right sides thereof. A complete device would be similar to the integrated circuit shown in FIGS. 6 and 7 (See also FIGS. 5 and 6) in the U.S. Pat. Nos. 3,430,109 and 3,585,714) where the gas, vacuum, or solid dielectrically insulating, close-ended (or annular) grooves provide a plurality of electrically isolated silicon pockets or islands for the electrically independently operable diodes, transistors, or other active or passive components such as resistors, capacitors, and inductances.
Once known in accordance with this invention that the bottom surface of the groove must be shaped and disposed in a way illustrated in FIG. 2, ways of forming the oxide groove can readily be found in the semiconductor art by, for example, thermal oxidation or ion implantation.
For example, thermally growing SiO2 (silicon dioxide) substantially transversely into selected area of a silicon substrate can be achieved by the usual masking techniques. Diffusion through masked areas is well-developed in the semiconductor industry. Thus, silicon can readily be chemically plated or vacuum deposited with layers of such metals as platinum, rhodium, gold, and nickel; or even some nonmetals such as Si3N4 or SiC. These layers are oxidation-inhibiting for the silicon thereunder, but may be made even more so, if needed, by additional treatment or other oxidation15 preventing surface layers electrolytically plated or otherwise built thereon. Windows may then be opened by mechanical, chemical, theremovacuum, or photoengraving means through these oxidation-inhibiting layers, for oxygen in-diffusion at selected areas. A very successful silicon nitride masking technique for diffusion into silicon of oxygen, boron, gallium, phosphorous, and arsenic has been given by V. Y. Doo (See “Silicon Nitride, A New Diffusion Mask,” IEEE Transactions on Electron Devices, Vol. 13, No. 7, 1966, pp. 561-563) and also by J. A. Apels et al in “Local Oxidation of Silicon and Its Applications in Semiconductor Device Technology,” Philips Research Reports 25, page 118, 1970. Doo, for example, shows that thin layers of Si3N4 from 150 to 1200 A thick can be pyrolytically deposited on silicon from silane and ammonia with excess hydrogen at 750 to 1100° C. There layers have been successfully employed to mask the diffusion of B, P, As, Ca, and O, when the commonly used photoengraving techniques are used. Such techniques generally involve a KMER (Eastman Kodak) photoresist layer formed on the Si3N4 layer, to be exposed to ultra-violet light through a mask and selectively removed at “window” areas by hydrofluoric or phosphoric acids. Atoms of O, B, Ga, P, and As may then be thermally diffused into the silicon through these windows exclusively.
Other related technique on thermal oxidation are discussed in Kennedy, D. P. and Murley, P. C., “Calculations of impurity Atom Diffusion Through A Narrow Diffusion Mask Opening”, IBM Jour. Vol. 10, 1966, pp 6-12 (especially FIGS. 1 and 4); and Lee, T. P. and Sze, S. M. “Depletion Layer Capacitance of Cylindrical and Spherical Junctions,” Solid State Electronics, Vol. 10, 1967, pp 1105-1108.
In thermal oxidation, one mole of silicon (28.0 g or 12.0 cc) reacts with one mole of oxygen (32.0 g) to form one mole of SiO2 (64.0 g or 25.9 cc), the densities of silicon and SiO2 being 2.34 and 2.32, respectively. The volume ratio of SiO2 to the original silicon is thus 25.9/12.0=2.16. The unrestricted linear expansion for the silicon upon complete, in-situ oxidation to SiO2 is thus the cubic root of (2.16)−1.00=29.2%. Similarly, the in-situ formation of Si3N4 from Si also results in substantial linear expansion (about 4.3% if the the density of the nitride is 3.44, as reported). The tendency of this significant linear and volume expansion during the in-situ formation of the entire discrete, oxide (or nitride) region (not layer or coating) from silicon introduces compressive stresses parallel to the PN junction end planes 15 and 16, i.e., across the lateral dimension of the junction and oxide regions. Because the oxide region comprises at the top a free (or gas-exposed) surface and a rounded bottom (with no sharp corners), and because of the inherent graded seal or graded (oxygen) concentration effects present, these high stresses are spreaded out evenly over wide areas and do not cause splitting cracks. Properly directed compressive stresses from the mismatched expansion coefficients are well-known to strengthen brittle materials such as Si and SiO2. The resultant device is thus resistant to relative tangential movement (i.e., rubbing contaminations) between the semiconductor silicon and SiO2 at the junction peripheral surface 26, and also to crack formations by mismatch stresses during thermal cycling, such as from environmental conditions or from repeated, on-off operations of the device.
An oxide region consisting entirely of in-situ formed silicon oxide is advantageous for some other reasons. The oxide region is 100% dense, substantially chemically pure and uniform, and non-contaminating. It is also impervious to contaminating gases and mobile ions, being made more so by the residual compressive stresses. This is in sharp contrast to other procedures in which the cut or etched-out grooves in silicon layers are superficially oxidized into thin (e.g., 8000 A) SiO2 layers and coatings and later filled with such materials as polycrystalline silicon, glasses, oxides, or plastics. This is because flat oxide layers on silicon, as shown below, have no curvature-related strain-relief mechanisms and are thus unreliable because of crack formations in the layer through the same mismatch stresses acting harmfully here. Also, these filling materials are almost always impure, particularly when compared to Sio2 formed in-situ. Schwartzman, for example, pointed out in U.S. Pat. No. 3,383,760, Col. 4, lines 4-6 that “most glasses contain impurities that may adversely affect the PN junction”. Further, the filled materials are not 100% dense, particularly with narrow grooves in microcircuits (See, e.g., Frouin U.S. Pat. No. 3,520,139, Col. 2, lines 44-46), and do not contribute much to the beneficial compressive mismatch stresses. In addition, both the cracked oxide layer and non-dense filled materials “breathe” and thus easily contaminate the shallowly located, peripheral surface of the PN junction region.
In contrast to in-situ formed oxide layers, the discrete or spaced-apart, specially shaped and positioned, oxide regions of this invention lower, through curvature, proximity, and other unique effects, the mismatch stresses to smaller magnitudes or dosages that can be harmlessly assimilated in localized areas. There is also the beneficial compressive stress pattern, but no excessive built-ups of harmful stresses that crack, split, micrifissure, or fail the device. From electrical and chip real-estate considerations, there is a limit between the relative areas occupied by the silicon and silicon oxide regions, and on the maximum lateral dimension of the oxide region and the minimum separating distance between two neighboring oxide regions. As a rule, the relative area ratios of silicon to SiO2 should be between 1/4:1 to 4:1; the maximum lateral dimension is about 10 times the depth of the oxide region; and the minimum separating distance is about 1/4 times the lateral dimension.
Alternative to thermal oxidation, ion implantation techniques may be used to introduce oxygen and nitrogen ions to be combined with silicon atoms into inert silicon oxide or nitride material regions. Under an implanting voltage of one megavolt, oxygen and nitrogen ions can be introduced into silicon host to a depth of 1.7 +/−0.13 um and 1.87 +/−0.12 m, respectively.
Practical procedures on ion implantation are disclosed by, e.g., Shockley's in his 1957 U.S. Pat. No. 2,787,564, and Gibbons, J. F., “Ion Implantation” in Semiconductor Part I Range Distribution Theory and Experiments, Proc. of IEEE March 1968, pp 295-319. These pioneers teach in detail the method of introducing precise amount of impurities, such as oxygen, to achieve three-dimensional control in shape, size, location, and composition by modulating the energy, current, duration, and position of the ion beam, and the use of apertured masks, moving wafers, and ion deflection or separation systems. A still further discussion of the ion implantation technique know at the time of the invention and useful for making the invented structure, is discussed in Burrill, J. T., et al, “Ion Implantation as a Production Technique,”. IEEE Trans. on Electron Devices, Vol. ED. 14, No. 1, January 1967, pp 10-17. Further state-of-the-art information on ion implantation can be found in Buchanan, B. et al., “High-Energy (1 to 2.5 Mev) Ion Implantation for Obtaining Novel Semiconductor Junction Structure,” Int'l Conference on Applications of Ion Beams to Semiconductor Technology, Grenoble, 1967, pp 649-668; and in Blamiers, N. G., “A Preliminary Study of Semiconductor Structures Produced by Ion Implantation,” given at the same Int'l Conference on pp 669-684. For example, under an implanting voltage of 1 Mev, ions such as oxygen and nitrogen ions are implanted into a silicon host to a depth of 1.7 +/−0.13 um and 1.87+/−)0.12 um, respectively. The width of the groove when ion implantation is used can be from about a micron up to 1 centimeter, using a relative movement between the implanting beam and the silicon material, with corresponding adjustment of beam characteristics such as beam energy, current, profile, and focusing, as taught in the prior art cited here, so as to achieve the groove shape and disposition taught by this invention.
A rounded bottom lessens the splitting forces on the underneath silicon layer because the oxide (or nitride) region, particularly if favorably compressed during the oxide formation due to the silicon volume expansion, has a blunt, rather than a sharp tip or bottom (no notch effect). Also, the thermoelastic mismatch stresses between any two connecting materials in general and between silicon and its attached SiO2 in particular, are always continuously or nonabruptly varying around rounded bottom (curvature effect). These stresses are smaller on a curved adjoining surface than on a flat adjoining surface (curvature effect on stress pattern). The same stresses are zero or minimal in the lateral direction at the bottom if it ends as a tip or line of zero width, and minimal and symmetrically distributed when the rounded bottom is symmetrical with respect to a longitudinal bisecting plane thereof (oxide region geometry effect). It is, therefore, highly desirable to locate the PN junction at (for oriented or tiled tangency to achieve very large expansion), or within a few microns of (for proximity effect), the bottom of the round-bottomed oxide region.
Notice also that a properly shaped, sized, and positioned solid or gas-filled groove, as disclosed in U.S. Pat. No. 3,585,714, systematically varies, in a predetermined manner, the transverse or cross-sectional area of the junction region, with the depth or thickness thereof, to allow the laterally extending area of the active region to be accurately defined with microscopic precision.
The junction region 11 of the device of FIG. 1 can be prepared first before the isolating groove 14 is formed into the doped, n-type epitaxial layer 12. The junction region 25 of the device of FIG. 2 can also be prepared prior to, or during the same formation of the oxide-filled groove 21 in the doped, n-type epitaxial layer 24.
A feature of the invention, however, is to form the oxide region 21 first at a high temperature (typically 1000 to 1350° C.) followed by the junction formation. The subsequent, lower-temperature junction-forming step, by, for example, dopant diffusion at 900° C. or ion implantation at even lower temperatures, relieves excessive compressive residual stresses. But some residual, beneficial compressive stresses always remain because of the temperature differences in oxidation and junction formation.
The device of FIG. 3 is made by starting with a slab of intrinsic semiconductor material 31 with a single groove 32 made into the top surface 33, such as that in FIG. 3a. The same slab may be alignedly grooved on both the top and bottom surfaces (FIG. 3b). Next, n-type and p-type dopants are diffused in, from the top and bottom surfaces, 32 and 34, respectively. The result is a top n-type layer 35, a bottom p-type epitaxial layer 36, and an intermediate, striped or pan-cake type PN junction region 37. This junction region is well inside the slab and is completely surrounded by, and buried in, the electronically inert or non-active (at least during device operation) material 31. The same active or junction region can be relatively planar or curved, depending on the surface concentrations of the n-type and p-type dopants and also on the thickness of the slab.
The device of FIG. 4 is made by forming, in a manner similar to the making of the device of FIG. 2, an oxide, nitride, or other electronically inert material region 41 in connection with the PN junction between two silicon layers 42 and 47. A hole or slot 43 is then formed so as to introduce three-dimensional (See Pat. No. 3,585,714) p-type dopant sources and to form the p-type base region 44. Finally, a shorter hole hole or slot 45 is made to form the n-type emitter region 46. This completes a new nPN transistor structure which may, of course, also be made by the familiar repeated maskings and diffusions. By controllably varying the shape, size, and location of the holes, slots, or other depressions, as well as the type, surface concentration or total amount of the dopant or other foreign atoms introduced by diffusion or ion implantation through the newly-formed surfaces of these depressions, other unique diodes, transistors, tetrodes . . . of novel configurational designs may be made. Oxygen, nitrogen, and other foreign atoms relative to silicon may be introduced to form the required isolation inert material region or low-resistivity regions underneath an isolation PN junction to connect pockets of the otherwise electrically isolated silicon material that are separated by the oxide grooves or material regions 41.
The device of FIG. 4, like that of FIG. 2, is only a portion of a larger integrated circuit device containing a larger plurality of similar components than is shown. The npn transistor in FIG. 4 is completely isolated electrically from neighboring npn transistors (not shown), laterally by the oxide region 41 and underneath by the PN isolation junction 48, the silicon pockets and npn transistors are still completely isolated from each other. Similarly, when the emitter-base and base-collector junctions are present, as shown by 25e and 25b, respectively, the npn transistor shown is also electrically isolated from similar npn transistors on the other (e.g., left) side of the oxide region 21. Further, when the device of FIG. 4 is used as an integrated diode circuit containing n-type region 46 and p-type region 44, these diodes are also completely isolated from similar diodes on the other side of the oxide region 41, even without the use of the bottom PN junction 48. Similarly, the integrated circuit device of FIG. 2 can used as a silicon structure of passive resistors 24L, 24R, . . . , only. These resistors are then also completely electrically isolated from each other by the oxide region 21 and the PN isolation junction 25. In each of the above cases of complete electrical isolation, the individual components can be operated fully independently of each other without sharing any common semiconductor layers or electrical connectors.
The high-power laser device of FIG. 5 is made in a manner similar to the making of the device of FIG. 3b. Here, two grooves 52 and 53 are cut into an intrinsic material slab 51. Dopant diffusions are then carried out to form the n-type top region 54 and p-type bottom region 55. These two regions are separated by the buried PN junction region 56. Rapidly moving cooling fluid jets or streams 57 and 58 (such as of air, water, or brine) are introduced tangentially to the grooves, as shown. The high velocities and centrifugal forces of the jets or streams insure good thermal contact of the cooling fluid and guarantee efficient surface cooling. In this device, the light beams travel in directions normal to the figure, being bounded by two optically flat surfaces (not shown) parallel to the drawing paper. One of these two surfaces allows the laser beam to come, e.g., out of the paper. Alternately, the intrinsic material region 51 may be the replaced by thermally grown-in silicon dioxide on a silicon substrate. Note in particular that the active regions of the devices of FIGS. 3 and 5 are isolated from the ambient-exposed surfaces of the device, where degradation is likely to proceed at the fastest rate. Further, for the same current density, the total current—and thus power input to the device—is much smaller. The solid regions 31 or 51 on either side of the stripe active region are able to carry heat away from the current-carrying active region.
FIG. 6-8 have been described in my U.S. Pat. Nos. 3,430,109 and 3,585,714. FIG. 6 shows a top view of a piece of a monolithic microcircuitry chip broken off from a, e.g., 6 cm×6 cm. semiconductor wafer containing thousands or more of individual, isolated or discrete units of circuit elements. Notice that there are two groups of linear and mutually perpendicular, gas or solid-filled isolating grooves 72. FIG. 7 shows a vertical cross-section of the same microcircuitry piece taken along line 7—7 of FIG. 6. In this cross-section, the grooves are seen to originate from the top surface 73 and to have cylindrical bottoms with the bottom lines lying in the lower (end or boundary) plane 76 of the junction region 71 thereby achieving maximum surface expansion. Each of the isolated or discrete circuit elements located in the individual silicon pockets 74 may be made to operate independently of, or in a completely isolated manner relative to, the others in a special signal translation operation therein, with a performance improved by the unique shape, size, and position of the grooves.
FIG. 8 shows a portion of an integrated circuit which is “universal” because it may be designed to contain a large number of ombinations of electrically isolated, active and passive circuit components, such as diodes, triodes, tetrodes, . . . , resistors, capacitors, and the like. Yet the circuit has only five carefully chosen and physically integral, semiconducting material layers. From these layers, all these individual components are made. These layers are one on top of the other, alternately p and n in electronic conductivity type, i.e., n, p+, n+, p, and n from the top down. A substrate may be used containing the bottom one to four layers with remaining top layers epitaxially deposited thereon. From these layers and the gas or oxide filled groove YWY′W′, many active components may be formed including: four pairs of diodes, three pairs of triodes or transistors, two pairs of tetrodes, and a single pair of pentodes. From suitably connected regions in these same coacting semiconductor layers, many precision resistors, capacitors, electrically conductive paths, and other passive components can be also made. The dimension and operating characteristics of these components are accurately defined laterally by the enclosing, microscopically precise oxide grooves and transversely by the electrically rectifying PN junctions. In particular, low resistivity layers may form cross-overs, crossunders, buried collector layer, . . . , to be suitably connected by diffusion or metal films, as per conventional semiconductor technology. Note that the groove YWY′w′ comprises several subgrooves (such as at Y, W, Y′, and W′).
The bottom of the main groove YWY′W′ is within a few microns of must of these layers or PN junction, while the bottoms of most of these subgrooves are within a few microns above some PN junctions but below others.
The manufacture of these microcircuits containing both active components and passive components may involve single or repeated sequences of such selected processing steps as forming nitride insulating layer; masking and selective nitride (or oxide) removal; etching, grinding or energetic beam bombarding to form microscopically precise depressions into these exposed areas; thermal oxidation or implantation and dopant diffusion into these depressions; masking and selective oxide removal; removal of residual nitride or oxide layer after oxygen or dopant diffusion; forming low-resistivity cross-over or cross-under regions similar to Doo's p+-type region 4 in the p substrate (see U.S. Pat. No. 3,386,865); dopant diffusion or ion implantation through oxide window for PN junction formation or electrical contacting to the low-resistivity, buried cross-overs or cross-unders; and electrical contacting through windows in oxide layers covering the device surfaces.
The second and third (from top down) semiconductor layers have superscripts to indicate very heavily doped, p-type and n-type materials, respectively. These superscripts may be replaces by “−” signs in some cases to indicate very lightly doped materials. Two more useful combinations of semiconducting layers thus obtain:np-nPN and nPN-p-n. In these later combinations, we have (relatively) low-resistivity, n and p-type layers, (or n+ and p+-type) layers, 82 and 83, respectively, lying underneath the (relatively) high-resistivity n- and p-resistivity layers, 84 and 85, respectively. These low-resistivity layers may occupy regions in the substrate directly beneath the lowest PN junction to form buried cross-unders connecting isolated silicon pockets electrically.
According to this invention, oxide or nitride-isolated, monolithic solid-state circuitries having densely-packed, electronically discrete units of solid-state components can be made by means of intersecting and triangular, square, or, in general, polygonal or close-ended (or annular), isolation oxide grooves in any possible top widths or configurations and cross-sectional shapes but completely and accurately defining the lateral limits of the active region or isolated silicon pockets, regions, or islands. These cross-ended grooves are to be referred to as “annular (shaped) isolation regions.” To minimize physical damage during mechanical grooving, to facilitate microscopically precise chemical etching or cutting, to maximize device yield, or to obtain other special optoelectrical effects, the directions of the grooves may be made to coincide with crystallographic directions of extreme or maximum atomic density of either the semiconductor substrate 22, or the epitaxial layer 24, or both. The <111>directions on (111) wafer of silicon or germanium may thus be selected. On (100) materials of silicon or germanium, the <100>directions are preferred for similar reasons. A suitable system of grooves, formed on a device wafer containing even a single or several PN junction regions, may yield many discrete, electrically independently operable, active or passive circuit components.
By preparing a groove, slot, hole, or other depression into the semiconductor layer and applying or introducing the right amount of dopants or foreign atoms (such as O, N, Ga, B, P, As) at selected, unmasked locations in the resultant depression, internal point, line, surface, or massive types of three-dimensional sources of foreign atoms are then obtained, according to my U.S. Pat. No. 3,585,714. This achieves three-dimensional configuration and/or concentration profile of the diffusing atoms. Instead of diffusion, ion or proton implantation, or other similar foreign atom introduction techniques can also be used in conjunction with these special depressions to achieve similar results. Skilled persons can use any of these techniques not only to prepare the emitter, base, and collector regions of transistors (see FIG. 4); but also to form regions of differing conductivity type in the oxide-isolated silicon pockets 24L and 24R; to prepare the conventional, low-resistivity cross-unders or cross-overs located in the surface of the substrate 22 directly beneath the epitaxial layer 24 so as to interconnect regions 24L and 24R separated by the oxide isolation regions 21 (FIG. 8); to convert entire oxide-isolated silicon pockets into other low resistivity regions by dopant diffusion so as to connect from the device surface such cross-under or cross-overs; and the like.
This technique of three-dimensional, configuration or diffusional front control can be combined with the nitride shielding method disclosed above. Take example, the integrated circuit device of FIG. 2. Here, a uniform, oxidation inhibiting (or insulating) silicon nitride layer is first laid on the top surface 23 of an n-type silicon layer 24 epitaxially grown on top of a p-type substrate 22. Windows are then opened up in this nitride layer, e.g., by HF etching, without affecting much of the underlying silicon. Specifically, portions of the nitride insulation overlying the regions of the epitaxial silicon layer to be converted into the oxidized isolation regions is removed or unmasked. Grooves, holes, or other depressions are then made in the window areas by mechanical grinding, chemical etching (e.g., with HF—HNO3), or energetic particles bombardment without affecting the remaining nitride layers. These depressions are made to a microscopic accuracy in terms of the depression sharp, depth, and lateral location in the epitaxial silicon layer exposed by the removal of the nitride layer. By “microscopic” I refer in this application to dimensions, accuracies, precisions, . . . of less than one or two microns. The silicon wafer is then oxygen implanted or thermally oxidized, through the newly exposed surface of the depression to form the oxidized silicon isolation regions 21 extending through the epitaxial layer 24 into the isolation PN junction 25. This procedure subdivides the epitaxial silicon layer 24 into a plurality of oxide-enclosed and electrically isolated, pockets of semiconductor silicon material. Any residual nitride layers can easily be removed after their uses by HF or H3PO4. In addition, this procedure provides microscopically accurate control of the shape, size, and location of the resultant annular, or close-ended, oxide grooves thereby achieving similar controls of the critical depth of these grooves, of the lateral dimension (and PN junction area) of the isolated silicon pockets, of the exact shape of the diffusional front, of the planarity of the top surface 23′ of the oxide grooves, and of the coplanarity of the top oxide surface 23′ relative to the silicon layer surface 23.
The device of FIG. 2 contains only a simple, PN junction to exemplify the optoelectromagnetic, signal-translating active region. Other devices may have much more complicated structures. Specifically, the top and/or bottom layers 24 and 22 of FIG. 2 may be replaced by, for example, up to five layers of the device in FIG. 8, and contain not only p and n layers but also p+, n+, ip (very weakly p-type intrinsic), and in (very weakly n-type intrinsic) materials. The p or n materials are widely (by at least several orders of magnitude) different in electrical conductivity and dopant concentrations relative to p+ and ip or n+ and in, respectively. These layers may be prepared either before, during, or after the gas or solid-filled isolating grooves are formed, as per conventional semiconductor technology.
Note that the thermally grown-in oxide, ion-implanted oxide or nitride, or the intrinsic material regions of the devices of FIGS. 1-5 are not only electronically inert but also unetched, uncut, and otherwise similarly unmodified. This condition preserves the as-formed, metallurgical continuity. Metallurgical continuity reduces or minimizes mismatch stresses through the graded-seal effects, because the inherent compositional changes and mismatches stresses are now changing gradually and not abruptly. These material regions are thus completely different in structure, mode of operation, and result from the usual, painted-on organics of fired-on glasses.
Even the common oxide or nitride surface layers are too thin and too imperfect, and also improperly oriented and positioned relative to the PN junction region, to achieve the results of this invention. Specifically, the conventional, relatively thin and planar oxide surface layers for device junction passivation is, for example, very thin. Generally, it is only several thousand Angstroms thick, typically 4000 A. As mentioned above, too thin a layer tends to crack and gives inadequate protection, while too hick a layer often peels or flakes off and causes extensive mismatch shear stresses at the oxide-silicon interfaces. These high harmful stresses arise from several reasons. Firstly, SiO2 expands, i.e., has a temperature coefficient of thermal expansion of, about 5.0×10−7/° C. while silicon expand about ten times as much. Secondly, the oxidation step is usually done at high temperature (up to 1350° C.) in an oxidizing ambient (e.g., steam), so as to allow great build-up of the mismatch stresses during the wide cooling temperature range. Thirdly, the normally stresses at the free (i.e., gas or vacuum-exposed) surface of oxide must be zero. There is, therefore, a very steep normal stress gradient across the very thin surface layer. Fourthly, the geometry of the thin surface layer (see layer 27 in FIG. 2) allows no stresses relief, particularly when the layer is flat. These conditions generally result in pinholes, microcracks, faults, . . . , and imperfect oxide protection. Further, any oxide defect will immediately expose the underneath silicon to the ambient, again because the surface oxide layer is thin.
Contrarily, in the grown-in oxide region 21 of FIG. 2, the oxidation step is, for many applications, preferably done first when there is no junction region 25 to damage by mismatch stresses. The lower temperature (about 950° C. or lower) junction forming step actually acts as beneficial annealing and stress-reliefing operation. The depth hj of diffused junction regions usually must exceed one or two microns for reliability. Often, this depth is much greater for collector-base junction regions. A large depth hj requires deep oxide penetration ho. This means that the oxide region is less easily damaged by cracks, pinholes, and faults. Even if the oxide is so damaged, the deep, contacting junction peripheral surface 26 may still not be affected. Also, there is no free or physically exposed surface in the oxide material region 21, except at the top surface 23 which is not as extensive as the oxide surface layer 27.
Specifically, the top free surface 23′ is substantially less than 50% (e.g., no more than 40%) of the total surface of the oxide region 21, in contrast to the thin oxide layer 27 in FIG. 2. In this thin layer form, the free surface is 50% of the total surface of the layer. The free surface of the oxide region is also far away from the deeply buried junction region 25, thereby minimizing the effect of ambient on the deeply located (over two or three microns below surface 23) junction 25 through any surface-related defects in the oxide. The oxide groove 21 also terminates at its bottom in the form of a line of practically zero horizontal width. The horizontal stresses resulting from the mismatches between the oxide and silicon at this bottom, being proportional to the width, must, therefore, be zero or minimal. Because of its cylindrical bottom and planar symmetry, the same oxide groove is subjected to further reduced mismatch stresses. The microscopically nearby junction region is, therefore, also much less severely stressed than higher points on the oxide-silicon interface. In addition, the generally sloping and/or curved or multiply sloped sides contacting the peripheral surface 26, and/or the close proximity (within one or two microns) of the rounded bottom of the oxide region or groove 21 to the PN junction region 25, allow some additional stress and strain reliefs.
When very severely stressed, a solid oxide region (or even thin layer) in a turn-around V or U-shaped groove may locally separate from the silicon host at the lowest point, but without cracking or excessive loss of device passivation, if the sensitive PN junction is microscopically close to the exact bottom of the groove. When such a groove has a rounded bottom, a new effect occurs, i.e., inverted arch effect. Solid oxide regions or even thin layers in the rounded bottom has an arch structure that can withstand much greater forces without failure than if the regions or layers are flat. These results further show the critical importance of proper geometry and location of the isolation oxide material.
A flat, thin layer on any mismatched substrate is likely to crack when extended in dimension. Familiar remedies are intentional gaps in railroad tracks or concrete highways. But gaps in passivating layers on semiconductor devices are contaminating and totally intolerable. Also, once a thin is cracked or microfissed, no amount of etching, cutting, grinding, or filling will restore its integrity and imperviousness. Its passivating qualities are thus forever lost or greatly reduced.
The present invention solves this mismatch problem in several ways. The oxide is purposed broken up, during its formation period, into small patches. Being proportional to the linear dimension, the mismatch stresses are relatively small and tolerable. The isolation silicon pockets can thus be considered as gaps in an otherwise continuous oxide structure. Other solutions of the problems such as by proper oxide geometry, location, orientation, formative conditions, . . . , have already been described elsewhere in this application.
In the formation of the convention thin oxide layers, the oxygen atoms diffuse uniformly over the layered portions of the exposed silicon surface, essentially in a single direction normally of the same layer, as shown by the arrows across the layer 27 in FIG. 2. Surface oxidation parallel to the PN junction region thus develops great harmful shear stresses in the direction of the PN junction to increase the chances of shearing and contaminating damage to the PN junction.
In the formation of my oxide region, the oxygen atoms generally diffuse through windows in the Si3N4 layer, transversely downward as well as sidewise. The depression is multi-directional, as shown by arrows in the oxide region 21 of FIG. 2). The oxidation thus proceeds laterally outward in both direction from a transversely extending, moving solid core with no free surface to dissipate stresses, thereby allowing the build-up of beneficial compressive stresses in the lateral directions across the silicon pockets and PN junctions. Such laterally directed compressive stresses minimize shear and contamination, particularly to the nearly PN junction, and are an important feature of my properly designed, isolation oxide regions. Even a thin oxide layer (e.g., 0.8 micron) at the bottom of a symmetrical, 200 V-shaped groove (in which the oxide height measures 0.8/sin 10°=4.6 microns) can achieve this effect to a great degree. It is necessary, however, that the PN junction is critically located, such as at no more than one or two microns above the groove bottom; and also that the oxide so formed is unetched, uncut, or otherwise similarly undisturbed and unmodified.
Thus, while the thin surface oxide layer 27 of FIG. 2 has the improper geometry, position, orientation, and formative conditions to allow adequate stress and strain relief on the peripheral surface of the PN junction region, the properly formed, shaped, sized, positioned, and oriented oxide region 21 of the same figure achieves improved stressing and straining patterns and beneficial compressive stress on the same peripheral surface, thereby improving device surface passivation and stabilization. Hence, the transversely extending, oxide region 21 differs from the thin surface layer of even the same metallurgically continuous oxide or nitride coatings normally used for some surface protection. Even thin oxide layers can also build up useful compressive stresses if they are wedged or arched in unetched form at the exact bottom of a V or U-shaped groove. Such wedging and arching action also prevents cracking, flaking, falling out of the oxide and allows greater freedom in device passivation designs.
The invention, as described above, is not to be construed as limited to the particular forms disclosed herein, since these are to be regarded as illustrative rather than restrictive. For example, Ge, GaAs, Gap, InP, InSb, and other III-V or II-VI compounds, together with inert isolation grooves of suitable materials therefore, may be used instead of Si. Further, various combinations, equivalent substitutions, or other modifications of the preferred embodiments described herein are obviously possible in light of the description, without departing form the spirit of the invention. Accordingly, the invention is to be limited only by the scope of the appended claims.

## Claims

1. A miniaturized, dielectrically isolated, solid state, integrated circuit device comprising, in a vertical cross-section through the device:
a semiconductor material substrate of a first conductivity type; 
an oxide region formed entirely by in-situ oxidation of an upper portion of the substrate, wherein the oxide region has a lower surface that, below a selected level extending laterally, is continuously convex and continuously rounded, without any straight portion, and tapers in width continuously and progressively, and wherein the oxide region has an upper surface that does not extend below the selected level and is non-concave, said oxide region being solid throughout between its upper and lower surfaces; 
two semiconductor material pockets of a second conductivity type that are formed in-situ from an upper portion of the substrate, wherein one of the pockets has a side surface that is in continuous physical contact with a portion of a left side of the lower surface of the oxide region and is continuously concave and rounded, and the other pocket has a side surface that is in continuous physical contact with a portion of a right side of the lower surface of the oxide region and is continuously concave and rounded, said side surfaces of the two pockets being substantially mirror images of each other relative to a vertical line extending centrally through the oxide region; 
wherein the pockets have respective upper surfaces that substantially conform to said selected level at least for portions of the pockets that are adjacent to the oxide region, and the concave and rounded side surfaces of the pockets extend below the selected level; 
a respective PN junction at an interface of each of the pockets with the substrate, each of the PN junctions extending to and meeting the oxide region at the convex and rounded lower surface thereof, below said selected level, and the oxide region laterally spacing the two PN junctions from each other, each of the PN junctions being substantially non-conductive electrically under an electrical bias of a selected polarity applied between the substrate and the respective pocket; and 
said oxide region physically separating and electrically isolating the two pockets from each other laterally, each of the pockets being at least a part of a respective active electrical device and the respective active electrical devices being physically a part of the same integrated circuit device but being electrically isolated from each other laterally by the oxide region and being operable as electrically independent active devices.

2. An integrated circuit device as in claim 1 in which the oxide region compresses adjacent portions of the pockets and the substrate, including where the PN junctions meet the oxide region, by virtue of volume expansion taking place in the course of the in-situ formation of the oxide region from the substrate material.

3. An integrated circuit device as in claim 1 wherein the PN junctions are flat.

4. An integrated circuit device as in claim 1 wherein the upper surface of the oxide region is flat.

5. An integrated circuit device as in claim 1 wherein the upper surfaces of the pockets are flat.

6. An integrated circuit device as in claim 1 wherein the upper surfaces of the pockets and of the oxide region are coplanar.

7. An integrated circuit device as in claim 1 wherein the PN junctions meet the lower surface of the oxide region at a non-normal angle.

8. An integrated circuit device as in claim 1 wherein each pocket extends from one oxide region to another, laterally spaced oxide region.

9. An integrated circuit device as in claim 1 wherein said pockets are formed in situ by diffusing dopants from above.

10. A miniaturized, dielectrically isolated, solid state, integrated circuit device comprising, in a vertical cross-section through the device:
a semiconductor material substrate of a first conductivity type; 
a solid, electrically isolating region formed at an upper portion of the substrate and at least in part by oxidizing the substrate, wherein said electrically isolating region has a lower surface that, below a selected level extending laterally, is convex and progressively tapers, and wherein the electrically isolating region has an upper surface that does not extend below the selected level and is non-concave, said electrically isolating region being solid throughout between its upper and lower surfaces; 
two semiconductor material pockets of a second conductivity type that are formed in-situ from an upper portion of the substrate, wherein one of the pockets has a side surface that is in continuous physical contact with a portion of a left side of the lower surface of the electrically isolating region and is concave, and the other pocket has a side surface that is in continuous physical contact with a portion of a right side of the lower surface of the electrically isolating region and is concave, said side surfaces of the two pockets being substantially mirror images of each other relative to a vertical line extending centrally through the electrically isolating region; 
wherein the pockets have respective upper surfaces that substantially conform to said selected level at least for portions of the pockets that are adjacent to the electrically isolating region, and the concave side surfaces of the pockets extend below the selected level; 
a respective PN junction at an interface of each of the pockets with the substrate, each of the PN junctions extending to and meeting the electrically isolating region at the convex lower surface thereof, below said selected level, and the electrically isolating region laterally spacing the two PN junctions from each other, each of the PN junctions being substantially non-conductive electrically under an electrical bias of a selected polarity applied between the substrate and the respective pocket; 
said electrically isolating region physically separating and electrically isolating the two pockets from each other laterally, each of the pockets being at least a part of a respective active electrical device, and the active electrical devices being physically a part of the same integrated circuit but being electrically isolated from each other laterally by the electrically isolating region and being operable as electrically independent active devices.

11. An integrated circuit device as in claim 10 wherein the convex lower surface of the electrically isolating region and each of the concave side surfaces of the pockets is continuously rounded below said selected level so that none of said surface has any straight portion below the selected level.

12. An integrated circuit device as in claim 11 wherein said electrically isolating region is an isolating oxide region.

13. An integrated circuit device as in claim 12 wherein said electrically isolating region is formed entirely by in-situ oxidation of the substrate.

14. An integrated circuit device as in claim 13 wherein the pockets are formed in situ by introducing into the substrate at least one impurity supplied from above the substrate.

15. An integrated circuit device as in claim 13 wherein the pockets are formed in situ by doping the substrate with at least one impurity through diffusion into the substrate.

16. A laterally electrically isolated integrated circuit comprising, when viewed in a vertical cross-section:
laterally extending first and second upper semiconductor portions; 
an electrically isolating region adjoining and laterally spacing from each other said upper semiconductor portions; 
a lower semiconductor portion below and adjoining said electrically isolating region and said upper semiconductor portions; 
a first PN junction where said lower semiconductor portion adjoins said first upper semiconductor portion and a second PN junction where said lower semiconductor portion adjoins said second upper semiconductor portion; 
said electrically isolating region being metallurgically continuous with respect to all said semiconductor portions and consisting essentially of at least one of an ion-implanted oxide and an ion-implanted nitride; 
said electrically isolating region being in-situ formed with a rounded bottom surface at a central portion thereof, wherein during said in-situ oxide or nitride formation with its associated volume expansion said electrically isolating region introduces volume mismatch stresses and strains into at least one of said upper and lower semiconductor portions and said in-situ formation, metallurgical continuity, and rounded central bottom, in combination, allow stress and strain relief to the semiconductor portions; and 
said rounded central bottom of said isolating region being, both vertically and horizontally, sufficiently close to at least one of said PN junctions as to significantly reduce said volume mismatch stresses and strains thereon and thereby improve performance and reliability of said integrated circuit.

17. A laterally electrically isolated integrated circuit as recited in claim 16, in which said isolating region has slopping or rounded sides.

18. A laterally electrically isolated integrated circuit comprising, when viewed in a vertical cross-section:
laterally extending first and second upper semiconductor portions; 
an electrically isolating region adjoining and laterally spacing from each other said upper semiconductor portions; 
a lower semiconductor portion below and adjoining said electrically isolating region and said upper semiconductor portions; 
a first PN junction where said lower semiconductor portion adjoins said first upper semiconductor portion and a second PN junction where said lower semiconductor portion adjoins said second upper semiconductor portion; 
said electrically isolating region being metallurgically continuous with respect to all said semiconductor portions and consisting essentially of at least one of an ion-implanted oxide and an ion-implanted nitride; 
said electrically isolating region being in-situ formed with a rounded central bottom surface at a central portion thereof, wherein during said in-situ oxide or nitride formation with its associated volume expansion said isolating region introduces volume mismatch stresses and strains into at least one of said upper and lower semiconductor portions and said in-situ formation, metallurgical continuity, and rounded central bottom, in combination, allow stress and strain relief to the semiconductor portions; and 
said rounded central bottom of said isolating region being, both vertically and horizontally, sufficiently close to at least one of said PN junctions as to substantially reduce said volume mismatch stresses and strains thereon and thereby improve performance and reliability of said integrated circuit.

19. A laterally electrically isolated integrated circuit as recited in claim 18, in which said isolating region has rounded sides.

20. A laterally electrically isolated integrated circuit as recited in claim 18, in which said electrically isolating region has a rounded bottom throughout its width.

21. A miniaturized, dielectrically isolated, solid state, integrated circuit device comprising, in a vertical cross-section through the device:
a semiconductor material; 
an oxide region formed by in-situ oxidation of an upper portion of the semiconductor material; 
said semiconductor material comprising a substrate of a first conductivity type and a left upper region and a right upper region each of a second conductivity type, wherein respective left and right PN junctions are formed at interfaces of said substrate with the left and right upper regions; 
the left and right upper regions having respective left and right top surfaces that are substantially coplanar, the left upper region having a continuously curving right side surface adjacent a left side surface of the oxide region and the right upper region having a continuously curving left side surface adjacent a right side surface of the oxide region; 
the oxide region being substantially solid and continuous everywhere below at least the top surfaces of the left and right upper regions, the oxide region tapering in width with distance below the top surfaces of the left and right upper regions, and the oxide region having a surface below the top surfaces of the left and right regions that is continuously rounded; 
the left PN junction having a right edge meeting the rounded surface of the oxide region at a portion thereof that is to the left of a central vertical plane through the oxide region perpendicular to said vertical cross-section, and the right PN junction having a left edge meeting the rounded surface of the oxide region at a portion thereof that is to the right of the central vertical plane; 
wherein the left upper region has a right hand portion that has a vertical thickness gradually changing with closeness to the right edge of the left PN junction, and the right upper region has a left hand portion that has a vertical thickness gradually changing with closeness to the left edge of the right PN junction; 
the oxide region physically separating and electrically isolating the left and right upper regions of the semiconductor material from each other laterally, each of the left and right upper regions being at least a part of a respective active electrical device, and the respective active electrical devices being physically a part of the same integrated circuit device but being electrically isolated from each other laterally by the oxide region and being operable as electrically independent active devices.

22. An integrated circuit device as in claim 21 in which the left and right upper regions are formed by introducing dopants into the semiconductor material from above after the in-situ formation of said oxide region.

23. An integrated circuit device as in claim 17 in which the oxide region compresses adjacent portions of the left and right regions and of the substrate, including where the left and right PN junctions meet the oxide region, due to volume expansion resulting from the in-situ formation of the oxide region from the semiconductor material.