# Patent

## Title
Line detecting apparatus and method for array substrate

## Abstract

A line detecting apparatus and a line detecting method for an array substrate relates to the field of line detecting technology. The detecting method comprises: arranging an input terminal sensor (30) at a signal input terminal of a wire to be detected, arranging one output terminal sensor (41, 42, 43) at a signal output terminal of the wire to be detected, and arranging other output terminal sensor (41, 42, 43) at a signal output terminal of another wire adjacent to the wire to be detected; measuring an output voltage of the wire to be detected by a voltage detector; and determining the line conduction condition of the wire to be detected according to the output voltage as measured. When the sensors perform line scan, the coordinate of the specific location where the short-circuit or open-circuit occurs can be found directly without performing scan by PDS or AOI, thus simplifying the technical processes, shortening the time for detecting, and saving the production cost.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on International Application No. PCT/CN2013/086455 filed on Nov. 1, 2013, which claims priority to Chinese National Application No. 201310247381.9 filed on Jun. 20, 2013. The entire contents of each and every foregoing application are incorporated herein by reference.
TECHNICAL FIELD
The present disclosure relates to a field of line detecting technique, and more particularly to a line detecting apparatus and method for an array substrate.
BACKGROUND
An array substrate of a Thin Film Transistor Liquid Crystal Display (referred to as a TFT-LCD in brief) is manufactured through complicate technical flows, and the phenomena such as an open-circuit or a short-circuit are prone to occur on the lines of the substrate, and the yield rate of products can be increased by detecting and repairing the lines on the substrate where the open-circuit or the short-circuit occurs; thus the purpose of improving the detecting efficiency and saving the cost can be achieved by expediting the detecting speed of the detecting apparatus and simplifying the hardware structure of the detecting apparatus.
There are a number of parallel wires on the array substrate of the TFT-LCD, wherein the parallel wires comprise gate lines and data lines in general; when an open-circuit or a short-circuit appears in such parallel wires due to particles or metal residual and the like, the detecting approach in the prior art firstly needs to perform line scanning by a Line Detecting Sensor (LDS) to find the location where a defective line is located as a whole. As shown in FIG. 1, taking a gate line 1 as an example, a voltage input terminal 2 and an input terminal sensor 3 connected to the voltage input terminal 2 are arranged at a signal input terminal of the gate line 1, and an output terminal sensor 4, to which an equivalent resistor 5 is connected, is arranged at a signal output terminal of the gate line 1. FIG. 2 is an equivalent circuit diagram of the LDS detecting apparatus, wherein the arrow direction in the FIG. 2 represents the signal transfer direction, Vin represents an input voltage, Vout represents an output voltage, C10 represents a capacitance of the input terminal sensor, C20 represents a capacitance of the output terminal sensor, R10 represents an equivalent resistance of the wire to be detected, R20 represents a resistance of the equivalent resistor 5. Subsequent to the LDS detecting, it needs to perform scan on the defective wire by a Position Detecting Sensor (PDS for short) or by an Auto Optical Inspection (AOI for short) to find the coordinate of the specific location where the failure occurs on the defective wire. The above detecting approach in the prior art has disadvantages such as more technical processes, slower detecting speed, and higher cost.
SUMMARY
(1) The Technical Problem to be Solved
The technical problem to be solved by the embodiments of the present disclosure is how to reduce the technical processes for line detection on the array substrate, thus saving the cost.
(2) Technical Solutions
To solve the above technical problem, in embodiments of the present disclosure, there is provided a line detecting apparatus for an array substrate, comprising: a voltage input terminal; an input terminal sensor connected to the voltage input terminal; an equivalent resistor; a voltage detector connected to the equivalent resistor in parallel; at least two output terminal sensors connected to the equivalent resistor.
Further, a wire to be detected is a gate line, and the at least two output terminal sensors comprise a first output terminal sensor, a second output terminal sensor and a third output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the gate line, the second output terminal sensor and the third output terminal sensor are arranged respectively at signal output terminals of two common electrodes adjacent to the gate line.
Further, a wire to be detected is a data line, and the at least two output terminal sensors comprise a first output terminal sensor and a second output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the data line, and the second output terminal sensor is arranged at a signal output terminal of another data line adjacent to the data line.
In the embodiments of the present disclosure, there is further provided a detecting method based on the above described line detecting apparatus for array substrate, comprising: arranging the input terminal sensor at the signal input terminal of the wire to be detected, arranging the first output terminal sensor of the at least two output terminal sensors at the signal output terminal of the wire to be detected, and arranging other output terminal sensor at a signal output terminal of another wire adjacent to the wire to be detected; measuring the output voltage of the wire to be detected by the voltage detector; and determining the line conduction condition of the wire to be detected by comparing the voltage as measured to a normal output voltage.
Further, the wire to be detected is a gate line, and the at least two output terminal sensors comprise a first output terminal sensor, a second output terminal sensor and a third output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the gate line, the second output terminal sensor and the third output terminal sensor are arranged respectively at signal output terminals of two common electrodes adjacent to the gate line.
Further, the wire to be detected is a data line, and the at least two output terminal sensors comprise a first output terminal sensor and a second output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the data line, and the second output terminal sensor is arranged at a signal output terminal of another data line adjacent to the data line.
Further, when the wire to be detected has a signal to output but the signal is inconsistent with a normal value, it is determined that a short-circuit occurs on the wire to be detected, and the distance between the position where the short-circuit occurs and a zero point of coordinate is calculated according to the output voltage value of the wire to be detected measured by the voltage detector.
Further, when the wire to be detected has no signal to output, it is determined that an open-circuit occurs on the wire to be detected, and the input terminal sensor is moved in the direction toward the output terminal of the wire to be detected until the output terminal sensor detects a signal.
Further, when the input terminal sensor is moved a position where the output terminal sensor detects a signal, the distance from the position where the open-circuit occurs to the zero point of coordinate is calculated according to the output voltage value of the wire to be detected measured by the voltage detector.
Further, after completing the determination of the line conduction condition of the wire to be detected according to the output voltage of the wire to be detected as measured, the detecting method comprises: moving positions of all the output terminal sensors by one detecting unit in a direction perpendicular to the longitudinal direction of the wire to be detected so as to detect the line conduction condition of a next detecting unit.
(3) Beneficial Effect
In the line detecting apparatus and method for array substrate provided in the above technical solutions, when the sensors perform line scan, the coordinate of the specific location where the short-circuit or open-circuit occurs can be found directly without performing scan by PDS or AOI, thus reducing the technical processes, shortening the time for detecting, and saving the production cost.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of an existing LDS detecting apparatus;
FIG. 2 is an equivalent circuit diagram of an existing LDS detecting mode;
FIG. 3 is a schematic diagram of a line detecting apparatus according to an embodiment of the present disclosure in a normal state;
FIG. 4 is an equivalent circuit diagram of the line detecting apparatus according to the embodiment of the present disclosure in the normal state;
FIG. 5 is a schematic diagram of the line detecting apparatus according to the embodiment of the present disclosure in a short-circuit;
FIG. 6 is a schematic diagram of the line detecting apparatus according to the embodiment of the present disclosure in the short-circuit;
FIG. 7 is a schematic diagram of the line detecting apparatus according to the embodiment of the present disclosure in an open-circuit; and
FIG. 8 is a schematic diagram of the line detecting apparatus according to the embodiment of the present disclosure in the open-circuit;



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Detailed descriptions will be given to the implementations of the present disclosure in connection with the accompanying drawings and embodiments. Obviously, the embodiments as described are only for illustrating the present disclosure, but not intended to limit the scope of the present disclosure.
First Embodiment
As shown in FIG. 3, a line detecting apparatus for an array substrate according to an embodiment of the disclosure comprises a voltage input terminal 20; an input terminal sensor 30 connected to the voltage input terminal 20; an equivalent resistor 50 which can be an equivalent resistor of the wire in the line detecting apparatus connected to the output terminal sensor, or a resistor connected in series separately; a voltage detector 80 connected to the equivalent resistor 50 in parallel, for measuring an output voltage of the wire to be detected; at least two output terminal sensors connected to the equivalent resistor 50. Herein, the input terminal sensor 30 and the output terminal sensors are both line detecting sensors.
In the present embodiment, the wire to be detected is a gate line 10, and the at least two output terminal sensors comprise a first output terminal sensor 41, a second output terminal sensor 42 and a third output terminal sensor 43, wherein the first output terminal sensor 41 is arranged at a signal output terminal of the gate line 10, the second output terminal sensor 42 and the third output terminal sensor 43 are arranged respectively at the signal output terminals of two common electrodes 60 adjacent to the gate line 10, and one of the two common electrodes adjacent to the gate line 10 is located on one side of the gate line 10 (as shown in FIG. 3, the upper side of the gate line 10), and the other of the two common electrodes adjacent to the gate line 10 is located on the other side of the gate line 10 (as shown in FIG. 3, the lower side of the gate line 10), and specifically located on one side of the pixel area on the other side of the gate line 10 (as shown in FIG. 3, the lower side of the pixel area on the lower side of the gate line 10).
In the present embodiment, the gate line 10 and the adjacent common electrodes located on both sides of the gate line 10 are taken as one detecting unit, and the line detecting job for one detecting unit is performed at a time; when the line detecting job for one detecting unit is completed, the line detecting job for a next detecting unit is performed after moving the detecting position by integral multiple detecting units; thus, the detecting position can be moved row by row, achieving the line detecting on each gate line.
During the detecting procedure, the input terminal sensor 30 is arranged at the signal input terminal of the gate line, and a voltage is input to the voltage input terminal 20; wherein the input terminal sensor 30 detects the input voltage signal, and the voltage signal is transmitted via the gate line, and when the first output terminal sensor 41 detects a normal output voltage signal, it shows that the conduction condition of the gate line is in normal, and no phenomena such as short-circuit or open-circuit occurs; as shown in FIG. 3 and FIG. 4, none of the second output terminal sensor 42 and the third output terminal sensor 43 has signal.
When the output voltage signal detected by the first output terminal sensor 41 is inconsistent with the normal output voltage, it shows that phenomenon of a short-circuit occurs on the gate line as detected; at this time, if the second output terminal sensor 42 has a signal to be transmitted, it shows that a short-circuit occurs between the common electrode 60 to which the second output terminal sensor 42 corresponds and the gate line, as shown in FIG. 5 and FIG. 6; if the third output terminal sensor 43 has a signal to be transmitted, it shows that a short-circuit occurs between the common electrode 60 to which the third output terminal sensor 43 corresponds and the gate line; if the second output terminal sensor 42 and the third output terminal sensor 43 both have signals to be transmitted, it shows that a short-circuit occurs between each of two common electrodes and the gate line.
When the first output terminal sensor 41 receives no signal, it shows that an open-circuit occurs on the gate line 10.
Second Embodiment
The line detecting apparatus for array substrate of the present embodiment differs that of the first embodiment only in that: the wire to be detected is a data line and the at least two output terminal sensors comprise a first output terminal sensor and a second output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the data line, and the second output terminal sensor is arranged at a signal output terminal of another data line adjacent to the data line.
In the present embodiment, every two adjacent data lines are grouped together and serve as one detecting unit, and a line detecting job for one detecting unit is performed at a time; when the line detecting job for one detecting unit is completed, a line detecting for a next detecting unit is performed after moving the detecting position by integral multiple detecting units, and it can be realized that detecting position is moved by every two data lines; and thus line detecting on each data line is achieved. The two output terminal sensors in each detecting unit are set as the first output terminal sensor and the second output terminal sensor respectively.
During the detecting procedure, the input terminal sensor is arranged at the signal input terminal of one data line, and a voltage is input to the voltage input terminal; wherein the input terminal sensor detects the input voltage signal and the voltage signal is transmitted via the data line, and the first output terminal sensor and the input terminal sensor are connected to a same data line, when the first output terminal sensor detects a normal output voltage signal, it shows that the data line to be detected conducts normally, and there is no short-circuit or open-circuit phenomenon; at this time, the second output terminal sensor has no signal; and when the output voltage signal detected by the first output terminal sensor is inconsistent with the normal output voltage, it shows that phenomenon of a short-circuit occurs on the data line as detected; at this time, if the second output terminal sensor has a signal to be transmitted, it shows that a short-circuit occurs between the data line to be detected and a data line to which the second output terminal sensor corresponds; when the first output terminal sensor receives no a signal, it shows that an open-circuit occurs on a data line to which the first output terminal sensor corresponds.
Third Embodiment
A detecting method of the present embodiment is based on the above described line detecting apparatus for an array substrate in the first embodiment, comprising:
S1, arranging the input terminal sensor at the signal input terminal of the wire to be detected, arranging the first output terminal sensor of the at least two output terminal sensors at the signal output terminal of the wire to be detected, and arranging other output terminal sensor at a signal output terminal of another wire adjacent to the wire to be detected;
S2, measuring the output voltage of the wire to be detected by the voltage detector;
S3, determining the line conduction condition of the wire to be detected according to the voltage as measured;
S4, moving positions of all the output terminal sensors by one detecting unit in a direction perpendicular to the longitudinal direction of the wire to be detected so as to detect the line conduction condition of a next detecting unit.
As shown in FIG. 3, in the present embodiment, the wire to be detected is the gate line 10, and the at least two output terminal sensors comprise a first output terminal sensor 41, a second output terminal sensor 42 and a third output terminal sensor 43, wherein the first output terminal sensor 41 is arranged at a signal output terminal of the gate line 10, the second output terminal sensor 42 and the third output terminal sensor 43 are arranged respectively at the signal output terminals of the two common electrodes 60 adjacent to the gate line 10, and one of the two common electrodes adjacent to the gate line 10 is located on one side of the gate line 10, and the other of the two common electrodes adjacent to the gate line 10 is located on one side of the pixel area on the other side of the gate line 10.
In the present embodiment, the gate line 10 and the adjacent common electrodes located on both sides of the gate line 10 are taken as one detecting unit, and the line detecting job for one detecting unit is performed at a time; when the line detecting job for one detecting unit is completed, the line detecting job for a next detecting unit is performed after moving the detecting position by integral multiple detecting units.
During the detecting procedure, the input terminal sensor is arranged at the signal input terminal of the gate line, and a voltage is input to the voltage input terminal; wherein the input terminal sensor detects the input voltage signal and the voltage signal is transmitted via the gate line.
As shown in FIG. 3 and FIG. 4, when the first output terminal sensor detects a normal output voltage signal, it shows that the conduction condition of the gate line is in normal, and no phenomena such as short-circuit or open-circuit occurs; at this time, none of the second output terminal sensor and the third output terminal sensor has a signal. When the gate line conducts normally, the normal output voltage signal of the signal output terminal of the gate line is the normal output voltage Vout′ calculated from the following equation 1:




  
    
      
        
          V
          out
          ′
        
        =
        
          
            
              R
              2
            
            *
            
              V
              in
            
          
          
            
              
                
                  (
                  
                    
                      1
                      
                        
                          ω
                          0
                        
                        ⁢
                        
                          c
                          0
                        
                      
                    
                    +
                    
                      1
                      
                        
                          ω
                          1
                        
                        ⁢
                        
                          c
                          1
                        
                      
                    
                  
                  )
                
                2
              
              +
              
                
                  (
                  
                    
                      R
                      1
                    
                    +
                    
                      R
                      2
                    
                  
                  )
                
                2
              
            
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        1
      
    
  




Herein, R1 represents an equivalent resistance value of the gate line 10, which can be measured by a multimeter or the like, R2 represents the resistance value of the equivalent resistor 50, Vin represents the input voltage from the voltage input terminal 20, ω0 represents the angular frequency of the input terminal sensor 30, C0 represents the capacitance of the input terminal sensor 30, ω1 represents the angular frequency of the first output terminal sensor 41, and C1 represents the capacitance of the first output terminal sensor 41.

When the output voltage signal Vout as detected by the first output terminal sensor 41 and measured by the voltage detector 80 is inconsistent with the normal output voltage Vout′, it shows that phenomenon of a short-circuit occurs on the gate line as detected; at this time, if the second output terminal sensor 42 has a signal to be transmitted, it shows that a short-circuit occurs between the common electrode 60 to which the second output terminal sensor 42 corresponds and the gate line 10, as shown in FIG. 5 and FIG. 6; if the third output terminal sensor 43 has a signal to be transmitted, it shows that a short-circuit occurs between the common electrode 60 to which the third output terminal sensor 43 corresponds and the gate line 10; if the second output terminal sensor 42 and the third output terminal sensor 43 both have signals to be transmitted, it shows that a short-circuit occurs between each of the two common electrodes and the gate line.
When a short-circuit occurs between the gate line 10 and one of the two adjacent common electrodes 60, the distance x1 between the position where the short-circuit occurs and the zero point of coordinate can be calculated based on the following equation 2:




  
    
      
        
          V
          out
        
        =
        
          
            
              R
              2
            
            *
            
              V
              in
            
          
          
            
              
                
                  
                    
                      
                        
                          (
                          
                            L
                            -
                            
                              x
                              1
                            
                          
                          )
                        
                        2
                      
                      *
                      
                        r
                        2
                      
                    
                    +
                    
                      
                        (
                        
                          1
                          
                            
                              ω
                              i
                            
                            ⁢
                            
                              c
                              i
                            
                          
                        
                        )
                      
                      2
                    
                  
                
                *
                
                  
                    
                      
                        
                          (
                          
                            L
                            -
                            
                              x
                              1
                            
                          
                          )
                        
                        2
                      
                      *
                      
                        R
                        2
                      
                    
                    +
                    
                      
                        (
                        
                          1
                          
                            
                              ω
                              1
                            
                            ⁢
                            
                              c
                              1
                            
                          
                        
                        )
                      
                      2
                    
                  
                
              
              
                
                  
                    
                      
                        
                          (
                          
                            L
                            -
                            
                              x
                              1
                            
                          
                          )
                        
                        2
                      
                      *
                      
                        r
                        2
                      
                    
                    +
                    
                      
                        (
                        
                          1
                          
                            
                              ω
                              i
                            
                            ⁢
                            
                              c
                              i
                            
                          
                        
                        )
                      
                      2
                    
                  
                
                +
                
                  
                    
                      
                        
                          (
                          
                            L
                            -
                            
                              x
                              1
                            
                          
                          )
                        
                        2
                      
                      *
                      
                        R
                        2
                      
                    
                    +
                    
                      
                        (
                        
                          1
                          
                            
                              ω
                              1
                            
                            ⁢
                            
                              c
                              1
                            
                          
                        
                        )
                      
                      2
                    
                  
                
              
            
            +
            
              
                
                  
                    (
                    
                      
                        R
                        2
                      
                      -
                      
                        
                          x
                          1
                        
                        ⁢
                        R
                      
                    
                    )
                  
                  2
                
                +
                
                  
                    (
                    
                      1
                      
                        
                          ω
                          0
                        
                        ⁢
                        
                          c
                          0
                        
                      
                    
                    )
                  
                  2
                
              
            
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        2
      
    
  




The above equation 2 is derived from the following equations 3-6:




  
    
      
        
          Z
          1
        
        =
        
          
            
              
                
                  
                    
                      (
                      
                        L
                        -
                        
                          x
                          1
                        
                      
                      )
                    
                    2
                  
                  *
                  
                    r
                    2
                  
                
                +
                
                  
                    (
                    
                      1
                      
                        
                          ω
                          i
                        
                        ⁢
                        
                          c
                          i
                        
                      
                    
                    )
                  
                  2
                
              
            
            *
            
              
                
                  
                    
                      (
                      
                        L
                        -
                        
                          x
                          1
                        
                      
                      )
                    
                    2
                  
                  *
                  
                    R
                    2
                  
                
                +
                
                  
                    (
                    
                      1
                      
                        
                          ω
                          1
                        
                        ⁢
                        
                          c
                          1
                        
                      
                    
                    )
                  
                  2
                
              
            
          
          
            
              
                
                  
                    
                      (
                      
                        L
                        -
                        
                          x
                          1
                        
                      
                      )
                    
                    2
                  
                  *
                  
                    r
                    2
                  
                
                +
                
                  
                    (
                    
                      1
                      
                        
                          ω
                          i
                        
                        ⁢
                        
                          c
                          i
                        
                      
                    
                    )
                  
                  2
                
              
            
            +
            
              
                
                  
                    
                      (
                      
                        L
                        -
                        
                          x
                          1
                        
                      
                      )
                    
                    2
                  
                  *
                  
                    R
                    2
                  
                
                +
                
                  
                    (
                    
                      1
                      
                        
                          ω
                          1
                        
                        ⁢
                        
                          c
                          1
                        
                      
                    
                    )
                  
                  2
                
              
            
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        3
      
    
  
  
    
      
        
          Z
          2
        
        =
        
          
            
              
                (
                
                  
                    R
                    2
                  
                  +
                  
                    
                      x
                      1
                    
                    ⁢
                    R
                  
                
                )
              
              2
            
            +
            
              
                (
                
                  1
                  
                    
                      ω
                      0
                    
                    ⁢
                    
                      c
                      0
                    
                  
                
                )
              
              2
            
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        4
      
    
  
  
    
      
        Z
        =
        
          
            Z
            1
          
          +
          
            Z
            2
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        5
      
    
  
  
    
      
        
          V
          out
        
        =
        
          
            
              R
              2
            
            *
            
              V
              in
            
          
          Z
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        6
      
    
  




Herein, the signal input terminal of the gate line is taken as the zero point of coordinate, L represents the total length of the gate line 10, x1 represents the distance between the position where the short-circuit occurs and the zero point of coordinate; Vin represents the input voltage from the voltage input terminal 20, Vout represents the output voltage of the gate line 10 measured by the voltage detector 80, Z1 represents the impedance of the wire from the position where the short-circuit occurs to the output terminal sensor (comprising the output terminal sensor), and Z2 represents the impedance of the wire from the signal input terminal to the position where the short-circuit occurs and the equivalent resistor 50.
R represents the equivalent resistance value of the gate line 10 per unit length, wherein




  R
  =
  
    
      R
      1
    
    L
  




R1 represents the equivalent resistance value of the gate line 10.

r represents the equivalent resistance value of the common electrode 60 per unit length with which the gate line 10 forms a short-circuit,




  r
  =
  
    
      r
      1
    
    L
  




r1 represents the equivalent resistance value of the common electrode 60 with which the gate line 10 forms a short-circuit.

R2 represents the resistance value of the equivalent resistor 50.
ω0 represents the angular frequency of the input terminal sensor 30, C0 represents the capacitance of the input terminal sensor 30, ω1 represents the angular frequency of the first output terminal sensor 41, and C1 represents the capacitance of the first output terminal sensor 41; ωi represents the angular frequency of the output terminal sensor of the signal output terminal of the wire with which the wire to be detected forms a short-circuit, and Ci represents the capacitance of the output terminal sensor of the signal output terminal of the wire with which the wire to be detected forms a short-circuit; herein, i represents a natural number greater than 2, and i is equal to 2 or 3 in the present embodiment; ω2 represents the angular frequency of the second output terminal sensor 42, and C2 represents the capacitance of the second output terminal sensor 42, ω3 represents the angular frequency of the third output terminal sensor 43, and C3 represents the capacitance of the third output terminal sensor 43.
As shown in FIG. 7 and FIG. 8, when the voltage detector 80 detects no output signal of the gate line, it can be determined that there occurs an open-circuit on the gate line, and the first output terminal sensor 41 receives no signal; at this time, the input terminal sensor 30 is moved in the direction toward the output terminal of the gate line 10 until the first output terminal sensor 41 detects a signal, and the voltage detector 80 can detect the signal; the distance x2 between the position where the open-circuit occurs on the gate line 10 and the zero point of coordinate can be calculated from the following equation 7:




  
    
      
        
          x
          2
        
        =
        
          L
          -
          
            
              
                
                  
                    
                      (
                      
                        
                          
                            R
                            2
                          
                          *
                          
                            V
                            in
                          
                        
                        
                          V
                          out
                        
                      
                      )
                    
                    2
                  
                  -
                  
                    
                      (
                      
                        
                          1
                          
                            
                              ω
                              0
                            
                            ⁢
                            
                              c
                              0
                            
                          
                        
                        +
                        
                          1
                          
                            
                              ω
                              1
                            
                            ⁢
                            
                              c
                              1
                            
                          
                        
                      
                      )
                    
                    2
                  
                
              
              -
              
                R
                2
              
            
            R
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        7
      
    
  




The equation 7 is derived from the following equations 8 and 9:




  
    
      
        
          V
          out
        
        =
        
          
            
              R
              2
            
            *
            
              V
              in
            
          
          
            
              
                
                  (
                  
                    
                      1
                      
                        
                          ω
                          0
                        
                        ⁢
                        
                          c
                          0
                        
                      
                    
                    +
                    
                      1
                      
                        
                          ω
                          1
                        
                        ⁢
                        
                          c
                          1
                        
                      
                    
                  
                  )
                
                2
              
            
            +
            
              
                [
                
                  
                    
                      (
                      
                        L
                        -
                        
                          x
                          2
                        
                      
                      )
                    
                    ⁢
                    R
                  
                  +
                  
                    R
                    2
                  
                
                ]
              
              2
            
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        8
      
    
  
  
    
      
        
          
            (
            
              L
              -
              
                x
                2
              
            
            )
          
          ⁢
          R
        
        =
        
          
            
              
                
                  (
                  
                    
                      
                        R
                        2
                      
                      *
                      
                        V
                        in
                      
                    
                    
                      V
                      out
                    
                  
                  )
                
                2
              
              -
              
                
                  (
                  
                    
                      1
                      
                        
                          ω
                          0
                        
                        ⁢
                        
                          c
                          0
                        
                      
                    
                    +
                    
                      1
                      
                        
                          ω
                          1
                        
                        ⁢
                        
                          c
                          1
                        
                      
                    
                  
                  )
                
                2
              
            
          
          -
          
            R
            2
          
        
      
    
    
      
        equation
        ⁢
        
          
        
        ⁢
        9
      
    
  




Herein, the signal input terminal of the gate line 10 is taken as the zero point of coordinate, x2 represents the distance between the position where the open-circuit occurs and the zero point of coordinate, and L represents the total length of the gate line.

R represents the equivalent resistance value of the gate line 10 per unit length, wherein




  R
  =
  
    
      
        R
        1
      
      L
    
    .
  




Vin represents the input voltage from the voltage input terminal 20, Vout represents the output voltage of the gate line 10 measured by the voltage detector 80, and R2 represents the resistance value of the equivalent resistor 50.
ω0 represents the angular frequency of the input terminal sensor 30, C0 represents the capacitance of the input terminal sensor 30, ω1 represents the angular frequency of the first output terminal sensor 41, and C1 represents the capacitance of the first output terminal sensor 41.
Fourth Embodiment
The present embodiment proposes a detecting method based on the line detecting apparatus for array substrate of the second embodiment, and the detecting method of the fourth embodiment differs from that of the third embodiment only in that: the wire to be detected is a data line; accordingly, the at least two output terminal sensors comprise a first output terminal sensor and a second output terminal sensor, wherein the first output terminal sensor is arranged at a signal output terminal of the data line, and the second output terminal sensor is arranged at a signal output terminal of another data line adjacent to the data line; the detecting and calculating procedures in the fourth embodiment are similar to those in the third embodiment, and differences are only in that: the gate line is replaced by the data line, and the two common electrodes with which the gate line forms a short-circuit or an open-circuit are replaced by another data line.
In the present embodiment, every two adjacent data lines are grouped together and serve as one detecting unit, and a line detecting job for one detecting unit is performed at a time; when the line detecting job for one detecting unit is completed, a line detecting job for a next detecting unit is performed after moving the detecting position by integral multiple detecting units. The two output terminal sensors in each detecting unit are set as the first output terminal sensor and the second output terminal sensor respectively.
In the line detecting apparatus and method for the array substrate provided in the above embodiments, when the sensors perform line scan, the coordinate of the specific location where the short-circuit or open-circuit occurs can be found directly without performing scan by PDS or AOI, thus reducing the technical processes, shortening the time for detecting, and saving the production cost.
It should be appreciated that the above embodiments are only preferred embodiments of the present disclosure. It will be obvious that those skilled in the art may make improvements and replacements to the above embodiments without departing from the technical principle of the present disclosure. Such improvements and replacements are intended to be included within the protection scope of the present disclosure.

## Claims

1. A line detecting apparatus for an array substrate, comprising: a voltage input terminal; an input terminal sensor connected to the voltage input terminal; an equivalent resistor and a voltage detector connected in parallel; at least two output terminal sensors
wherein the input terminal sensor is arranged at a signal input terminal of a wire to be detected, a first output terminal sensor in the at least two output terminal sensors is arranged at a signal output terminal of the wire to be detected, each of other output terminal sensors in the at least two output terminal sensors is arranged at a signal output terminal of another wire adjacent to the wire to be detected respectively, a signal input terminal of the wire adjacent to the wire to be detected is floated,
wherein the equivalent resistor and the voltage detector connected in parallel are connected to one of said at least two output terminal sensors, and the voltage detector is configured to read a voltage at the signal output terminal of the wire to be detected when being connected to the signal output terminal of the wire to be detected, and to read a voltage at the signal output terminal of the wire adjacent to the wire to be detected when being connected to the signal output terminal of the wire adjacent to the wire to be detected.

2. The line detecting apparatus for array substrate of claim 1, wherein the wire to be detected is a gate line, and the at least two output terminal sensors comprise the first output terminal sensor, a second output terminal sensor and a third output terminal sensor, the first output terminal sensor is arranged at a signal output terminal of the gate line, the second output terminal sensor and the third output terminal sensor are arranged respectively at signal output terminals of two common electrodes adjacent to the gate line.

3. The line detecting apparatus for array substrate of claim 1, wherein the wire to be detected is a data line, and the at least two output terminal sensors comprise a first output terminal sensor and a second output terminal sensor, the first output terminal sensor is arranged at a signal output terminal of the data line, and the second output terminal sensor is arranged at a signal output terminal of another data line adjacent to the data line.

4. A detecting method based on the line detecting apparatus for array substrate of claim 1, comprising: arranging the input terminal sensor at a signal input terminal of a wire to be detected, arranging a first output terminal sensor of the at least two output terminal sensors at a signal output terminal of the wire to be detected, and arranging each of the other output terminal sensors at the signal output terminal of another wire adjacent to the wire to be detected; measuring an output voltage of the wire to be detected by the voltage detector; determining a line conduction condition of the wire to be detected by comparing the voltage as measured to a normal output voltage.

5. The detecting method of claim 4, wherein the wire to be detected is a gate line, and the at least two output terminal sensors comprise the first output terminal sensor, a second output terminal sensor and a third output terminal sensor, the first output terminal sensor is arranged at the signal output terminal of the gate line, the second output terminal sensor and the third output terminal sensor are arranged respectively at signal output terminals of two common electrodes adjacent to the gate line.

6. The detecting method of claim 4, wherein the wire to be detected is a data line, and the at least two output terminal sensors comprise the first output terminal sensor and a second output terminal sensor, the first output terminal sensor is arranged at the signal output terminal of the data line, and the second output terminal sensor is arranged at the signal output terminal of another data line adjacent to the data line.

7. The detecting method of claim 4, wherein it is determined that a short-circuit occurs on the wire to be detected as the wire to be detected has a signal output which is inconsistent with a normal value, and the distance between the position where the short-circuit occurs and the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.

8. The detecting method of claim 4, wherein, it is determined that an open-circuit occurs on the wire to be detected as the wire to be detected has no signal output, the input terminal sensor is moved in the direction toward the output terminal of the wire to be detected until the output terminal sensor detects a signal.

9. The detecting method of claim 8, wherein, when the input terminal sensor is moved to a position where the output terminal sensor detects a signal, the distance from the position where the open-circuit occurs to the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.

10. The detecting method of claim 4, wherein, after completing the determination of the line conduction condition of the wire to be detected according to the output voltage of the wire to be detected as measured, the detecting method comprises: moving positions of all the output terminal sensors by one detecting unit in a direction perpendicular to the longitudinal direction of the wire to be detected so as to detect the line conduction condition of a next detecting unit.

11. The detecting method of claim 5, wherein, it is determined that a short-circuit occurs on the wire to be detected as the wire to be detected has a signal output which is inconsistent with a normal value, and the distance between the position where the short-circuit occurs and the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.

12. The detecting method of claim 6, wherein it is determined that a short-circuit occurs on the wire to be detected as the wire to be detected has a signal output which is inconsistent with a normal value, and the distance between the position where the short-circuit occurs and the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.

13. The detecting method of claim 5, wherein, it is determined that an open-circuit occurs on the wire to be detected as the wire to be detected has no signal output, and the input terminal sensor is moved in the direction toward the output terminal of the wire to be detected until the output terminal sensor detects a signal.

14. The detecting method of claim 6, wherein, it is determined that an open-circuit occurs on the wire to be detected as the wire to be detected has no signal output, and the input terminal sensor is moved in the direction toward the output terminal of the wire to be detected until the output terminal sensor detects a signal.

15. The detecting method of claim 11, wherein, when the input terminal sensor is moved to a position where the output terminal sensor detects a signal, the distance from the position where the open-circuit occurs to the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.

16. The detecting method of claim 12, wherein, when the input terminal sensor is moved to a position where the output terminal sensor detects a signal, the distance from the position where the open-circuit occurs to the zero point of coordinate is determined according to the output voltage value of the wire to be detected measured by the voltage detector.