# Patent

## Title
Voltage controlled oscillator delay cell

## Abstract

A voltage-controlled oscillator design is disclosed that provides greater tuning range than a prior art differential amplifier design using “varactor” diodes. The design employs CMOS capacitors to replace varactor diodes. The CMOS capacitors are formed from PMOS transistors in which the drain of the transistor is electrically connected to the source of the same transistor, so that voltage-dependant capacitors are formed between the gate-to-source terminals and the gate-to-drain terminals of the PMOS transistor. Secondly, the monolithic inductors employed in the prior art are replaced by “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshhold, or turn-on voltage, of the transistor. The resistor/transistor combination acts inductively at the frequency of oscillation of interest.

## Background
FIELD OF THE INVENTION
The present invention relates to oscillators in general, and, more particularly, to voltage-controlled ring oscillators.
BACKGROUND OF THE INVENTION
The voltage-controlled oscillator (VCO) is an important building block in phase-locked loops, clock recovery circuits, and frequency synthesizers. High frequency and radio frequency (RF) voltage-controlled oscillators can be implemented monolithically as LC oscillators, as relaxation oscillators and ring oscillators. Ring oscillators are frequently used in the prior art to generate high frequency clock signals. Ring oscillators may be controlled by a voltage or current source to generate a variable frequency signal.
FIG. 1 depicts a block diagram of delay cells arranged as a ring voltage-controlled oscillator of the prior art. Ring oscillator 100 comprises multiple stages of amplification and delay that are connected in tandem, with the last stage coupled back to the first stage in the form of a ring around which the signals propagate. Each stage of the ring oscillator, labeled 100-1 through 100-3 in the figure, provides a phase shift. In particular, each half period the signal will propagate around the delay cell ring with an inversion. Ring oscillators can be implemented using differential pair or current-starved single-ended inverter structures.
FIG. 2 depicts a schematic of a typical differential amplifier with resistive loads to implement a single delay cell. Parasitic capacitances across the drain-to-source of transistors M1 and M2 interact at high frequency with resistors R1 and R2 to provide the requisite phase shift and gain of the delay cell. FIG. 3 is a variation of FIG. 2 in which the resistors have been replaced by MOS transistors M4 and M5. The resistors of FIG. 1 occupy a large area on a die, which can be alleviated in FIG. 2 by transistors, covering a smaller area, the latter operating in their ohmic regions to act as resistive loads. It has been recognized in the prior art that it is beneficial to use differential amplifiers for each of the stages of the ring oscillator in order to cause the oscillator to be more immune to the influence of spurious noises in the form of voltage and current spikes that might be coupled to both sides of the differential circuit. Such a spurious noise from the power supply, for example, would be coupled to both sides of the differential amplifier, and it would therefore affect both of the sides of the differential stages substantially equally. Consequently, the effect of such spurious noise is minimized on the output of the oscillator, which can be taken as the difference of the outputs of any one of the stages.
Two problems associated with using differential amplifiers in a ring oscillators are differential mode lockup and common mode lockup. Differential mode lockup refers to the phenomenon that occurs where each stage (differential amplifier) of the ring oscillator would end up with its output at either the opposite voltage limits or at the same voltage limit as the other stages. However, differential mode lockup typically only occurs in a ring oscillator with an even number of stages (e.g., 2, 4, 6, etc.). For example, in a simple two stage ring-oscillator, differential lockup could occur with the first output of stage one and the second output of stage two sitting at one voltage limit while the second output of stage one and the first output of stage two are sitting at the opposite voltage limit. Common mode lockup could occur with the first and second outputs of stage one sitting near one voltage limit while the first and second outputs of stage two are sitting near the opposite voltage limit.
Differential mode lockup can be prevented in a ring oscillator using an even number of stages by crossing the connections made between the outputs and the inputs for one pair (or an odd number of pairs) of connections in the ring oscillator. As a result, an additional phase inversion is provided in the differential signal path, and lockup of the oscillator on a differential basis is prevented. Alternatively, FIG. 4 depicts the resistive loads replaced by monolithic inductors. The inductors, along with the parasitic capacitors of the transistors M1 and M2, form an LC oscillator, which is free of the latch up problems of the resistive load delay cell. This configuration suffers from being dependent on large physical inductors that are hard to match and, together with the parasitic capacitance, hard to tune the oscillation frequency.
The oscillation frequency of LC topologies is equal to 



  
    f
    asc
  
  =
  
    1
    
      2
      ⁢
      π
      ⁢
      
        LC
      
    
  




suggesting that only the inductor and capacitor values can be varied to tune the frequency. Since it is difficult to vary the values of the monolithic inductors and the parasitic capacitances, we can replace the parasitic capacitance with a voltage dependent capacitor called a “varactor.” FIG. 5 shows diodes D1 and D2 as reversed biased PN junctions acting as varactors added as shown to the circuit of FIG. 4. VC sets the voltage across diodes D1 and D2, producing a tuning range for the capacitance values which in turn tunes the LC oscillator.

Besides the above-mentioned limitation of monolithic inductor implementations, the PN junction-type varactor has a very limited range of reverse bias voltage, yielding a limited range of tuning frequency.
SUMMARY OF THE INVENTION
To provide greater tuning range than that provided by “varactor” diodes, the diodes are replaced with PMOS transistors in series with the drains of transistors M1 and M2 of FIG. 5. The drain and sources of the PMOS transistors are electrically connected to each other, so that voltage-dependant CMOS capacitors are formed between the gate-to-source terminals and the gate-to-drain terminals of the PMOS transistor.
Secondly, the monolithic inductors of FIG. 5 are replaced by “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshold, or turn-on voltage, of the transistor, acts inductively at the frequency of oscillation of interest. The differential amplifier structure is maintained from FIG. 5.
The illustrative embodiment comprises: a first NMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal; a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first NMOS field effect transistor; a first PMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal, wherein said source terminal of said first PMOS field effect transistor is electrically connected to said source terminal of said first NMOS field effect transistor; and a second NMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal, wherein said drain terminal of said second NMOS field effect transistor is electrically connected to said drain terminal of said first PMOS field effect transistor, and wherein said drain terminal of said first PMOS field effect transistor is electrically connected to said source terminal of said first PMOS field effect transistor.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts a block diagram of delay cells arranged as a ring voltage-controlled oscillator of the prior art.
FIG. 2 depicts a schematic of a typical differential amplifier with resistive loads to implement a single delay cell.
FIG. 3 is a variation of FIG. 2 in which the resistors have been replaced by MOS transistors M4 and M5.
FIG. 4 depicts the resistive loads replaced by monolithic inductors.
FIG. 5 shows diodes D1 and D2 as reversed biased PN junctions acting as varactors added as shown to the circuit of FIG. 4.
FIG. 6 depicts a schematic diagram of the salient components of the illustrative embodiment of the present invention.
FIG. 7 depicts a schematic of the small signal model for the active inductor of FIG. 6.
FIG. 8 depicts a bode-plot of the magnitude of Zo as a function of frequency.
FIG. 9 depicts a schematic of the small signal model for the CMOS capacitor constructed from an MOS transistor.



DETAILED DESCRIPTION
FIG. 6 depicts a schematic diagram of the salient components of the illustrative embodiment of the present invention. Resistor R1 is connected at one end to a positive power supply VDD2 at 601, and at its other end to the gate terminal of NMOS transistor M6. The drain terminal of NMOS transistor M6 is connected to a second power supply rail VDD1 at 602. For the preferred embodiment, this supply voltage is about 1.8 volts. VDD2 must be greater than VDD1 by at least the threshold voltage of transistor M6 for the active inductor formed by R1 and M6 to operate, i.e., the transistor M6 must operate in its active region. The combination of R1 and M6 is called active inductor AI1, to be described in FIG. 7.
The source of transistor M6 is connected to the source of PMOS transistor M4, labeled VOUT−, while the drain terminal of transistor M4 is connected to the drain terminal of NMOS transistor M1 at 603-1. The source of transistor M4 is connected to the drain of transistor M4. Transistor M4 with drain to source terminals shorted is called CMOS capacitor CC1, to be described further in FIG. 8. The source terminal of transistor M1 is connected to the drain terminal of NMOS transistor M3, while the source terminal of transistor M3 is electrically connected to ground potential.
The remaining transistors and resistor are the mirror images of those already described so as to form a differential pair. The drain of transistor M3 is connected to the source of NMOS transistor M2. The drain of PMOS transistor M5 is connected to the drain of transistor M2 at 603-2, while the gate of transistor M5 is connected to the gate of transistor M4. The source of transistor M5 is connected to the source of NMOS transistor M7, labeled VOUT+. The drain of transistor M5 is connected to the source of transistor M5. Transistor M5 with drain to source shorted is called CMOS capacitor CC2, to be described in FIG. 8. The drain of transistor M7 is connected to power supply VDD1 at 602. The gate of transistor M7 is connected to one end of resistor R2, while the other end of transistor R2 is connected to supply voltage VDD2 at 601. The combination of R2 and M7 is called active inductor AI2, to be described in FIG. 7.
The gate of transistor M1 is labeled as differential positive input voltage Vin+, while the gate of transistor M2 is labeled as differential negative input voltage Vin−. A differential input voltage from a previous delay cell stage is connected to these inputs. The gate terminals of both transistor M4 and M5 are labeled as control voltage Vcontrol, which is the voltage control terminal that varies the LC oscillator circuit capacitance. The source of transistor M6 is labeled as differential negative output voltage Vout−, while the source of transistor M7 is labeled as differential positive output voltage Vout+. The differential output leads are connected to the differential inputs of another delay cell. A bias voltage, labeled Vblas, is connected to the gate of transistor M3 to provide a constant DC bias current to the differential pair circuit. The circuit as a whole is differential input/output to as to reduce the circuit's susceptibility to noise.
In the prior art of FIG. 5, the LC portion of the differential pair oscillator cell was realized by a physical passive inductance component, and a varactor diode that was reverse biased to provide the variable capacitor function. This variable capacitor, which sets the oscillation frequency, is controlled by a voltage applied to the cathode of the diode.
In FIG. 6, the passive inductor is replaced by what is called an active inductor. There are two active inductors in the illustrative embodiment: one comprising resistor R1 and NMOS transistor M6, and a second comprising resistor R2 and NMOS transistor M7.
FIG. 7 depicts schematics of the small signal model for the active inductors of FIG. 6. FIG. 7a represents active inductor AI1 of FIG. 6, while FIG. 7b represents active inductor AI2 of FIG. 6. The DC power supply rails at 601 and 602 have been replaced by AC ground potentials. For the analysis we will look at FIG. 7a. At node Vg, we have 



  
    
      
        
          
            
              sC
              gs1
            
            ⁡
            
              (
              
                
                  V
                  g
                
                -
                
                  V
                  o1
                
              
              )
            
          
          +
          
            
              V
              g
            
            R1
          
          +
          
            
              V
              g
            
            ⁢
            
              sC
              gd1
            
          
        
        =
        0
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          1
        
        )
      
    
  




Rearranging slightly, we have 



  
    
      
        
          V
          g
        
        =
        
          
            
              sC
              gs1
            
            ⁢
            
              R1V
              o1
            
          
          
            1
            +
            
              sR1
              ⁡
              
                (
                
                  
                    C
                    gs1
                  
                  +
                  
                    C
                    gd1
                  
                
                )
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          2
        
        )
      
    
  




At node VOUT−,

Io1=gm1(Vg−Vo1)+(Vg−Vo1)sCgs1−Vo1sCL  (Eq. 3) 

Solving (2) and (3), we have 



  
    
      
        
          Z
          o
        
        =
        
          
            
              V
              o1
            
            
              I
              o
            
          
          =
          
            [
            
              
                (
                
                  1
                  +
                  
                    sR1
                    ⁡
                    
                      (
                      
                        
                          C
                          gs1
                        
                        +
                        
                          C
                          gd1
                        
                      
                      )
                    
                  
                
                )
              
              
                
                  
                    
                      
                        
                          [
                          
                            R1
                            ⁡
                            
                              (
                              
                                
                                  
                                    C
                                    gd1
                                  
                                  ⁢
                                  
                                    C
                                    gs1
                                  
                                
                                +
                                
                                  
                                    C
                                    gs1
                                  
                                  ⁢
                                  
                                    C
                                    L
                                  
                                
                                +
                                
                                  
                                    C
                                    gd1
                                  
                                  ⁢
                                  
                                    C
                                    L
                                  
                                
                              
                              )
                            
                          
                          ]
                        
                        ⁢
                        
                          s
                          2
                        
                      
                      +
                    
                  
                
                
                  
                    
                      
                        
                          [
                          
                            (
                            
                              
                                C
                                gs1
                              
                              +
                              
                                C
                                L
                              
                              +
                              
                                
                                  g
                                  m1
                                
                                ⁢
                                
                                  R1C
                                  gd1
                                
                              
                            
                            )
                          
                          ]
                        
                        ⁢
                        s
                      
                      +
                      
                        g
                        m1
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          4
        
        )
      
    
  




From equation (4) the poles (6 and 7) and zero (5) can be identified as: 



  
    
      
        
          Z
          1
        
        =
        
          1
          
            R1
            ⁡
            
              (
              
                
                  C
                  gs1
                
                +
                
                  C
                  gd
                
              
              )
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          5
        
        )
      
    
  
  
    
      
        
          P
          1
        
        =
        
          
            g
            m1
          
          
            
              C
              gs1
            
            +
            
              C
              L
            
            +
            
              
                g
                m1
              
              ⁢
              
                R1C
                gd1
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          6
        
        )
      
    
  
  
    
      
        
          P
          2
        
        =
        
          
            
              C
              gs1
            
            +
            
              C
              L
            
            +
            
              C
              gd1
            
          
          
            R1
            ⁡
            
              (
              
                
                  
                    C
                    gs1
                  
                  ⁢
                  
                    C
                    gd1
                  
                
                +
                
                  
                    C
                    L
                  
                  ⁢
                  
                    C
                    gd1
                  
                
                +
                
                  
                    C
                    L
                  
                  ⁢
                  
                    C
                    gs1
                  
                
              
              )
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          7
        
        )
      
    
  




FIG. 8 depicts a bode-plot of the magnitude of Zo as a function of frequency. In the range of frequency between Z1 and P1, the active inductor induces a zero, increasing gain with frequency, similar in function to a real inductor. The active inductor introduces inductive impedance as a load at the oscillator frequencies of interest.

The varactor diodes are replaced by two PMOS transistors, M4 and M5, respectively. For each transistor, the source terminal is electrically connected to the drain terminals. A variable capacitor is formed by the PN junction comprising the semiconductors between the drain and gate terminal of M6, or between the drain and gate terminal of M7. In this CMOS capacitor, the gate acts as a plate and the drain and source connected together act as a second plate. The two plates are separated by silicon oxide, which acts as a dielectric, and this configuration makes the MOS transistor act as a capacitor.
The varactor effect is achieve by applying a positive voltage to the gate terminal of M4 in the range of 0.9 to 1.3 Volts for the case of a supply voltage of 1.8 volts with 0.18 micron CMOS technology. It will be clear to those skilled in the art, however, how to make and use alternative embodiments of the present invention in which the supply voltage and process technology can be varied to give different ranges of control voltage and hence different tuning ranges of the LC oscillator.
FIG. 9 depicts a schematic of the small signal model for the CMOS capacitor constructed from an MOS transistor. FIG. 8a depicts the high frequency model of the MOS transistor from the perspective of CC1 of FIG. 6, with the addition of the drain terminal being electrically connected to the source terminal. FIG. 8b depicts the small signal model of CMOS capacitor CC2 of FIG. 6. The analysis for both CMOS capacitors is the same.
Terminal B, which is electrically connected to AC ground, is the bulk or substrate connection of the device not normally shown in transistor schematics. When the drain terminal is electrically connected to the source terminal, the dependent sources, gmVgs and gmbVbs, are shorted, as well as the output resistance ro. The schematics of FIGS. 8a and 8b reduce to that of FIG. 8c, which shows a gate to bulk capacitance, Cgb, a drain to bulk capacitance, Cdb in parallel with source to bulk capacitance, Csb, and gate to drain/source capacitances Cgd and Cgs in parallel. Since Cgb and Cdb are negligible compared to Csb and the combination of Cgd and Ggs, Cgb and Cdb can be ignored. The circuit further reduces to FIG. 8d. The relationship between the gate control voltage and the device capacitance is as follows: Taking node Vg as a reference, we have 



  
    
      
        
          
            
              V
              g
            
            -
            
              V
              d
            
          
          
            
              (
              
                
                  C
                  gd
                
                +
                
                  C
                  gs
                
              
              )
            
            ⁢
            s
          
        
        =
        
          
            V
            d
          
          
            sC
            sb
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          8
        
        )
      
    
  




    
    
        and

Vg−Vd=Vgd  (Eq. 9) 

        Rearranging (8) gives 



  
    
      
        
          V
          gd
        
        =
        
          
            
              V
              d
            
            
              C
              sb
            
          
          ⁢
          
            (
            
              
                C
                gd
              
              +
              
                C
                gs
              
            
            )
          
        
      
    
    
      
        (
        
          Eq
          .
          
             
          
          ⁢
          10
        
        )
      
    
  




    
    


The voltage at the gate is proportional to the gate-drain and gate-source capacitances.
It is to be understood that the above-described embodiments are merely illustrative of the present invention and that many variations of the above-described embodiments can be devised by those skilled in the art without departing from the scope of the invention. It is therefore intended that such variations be included within the scope of the following claims and their equivalents.

## Claims

1. An apparatus comprising:
a first NMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal; 
a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first NMOS field effect transistor; 
a first PMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal, wherein said source terminal of said first PMOS field effect transistor is electrically connected to said source terminal of said first NMOS field effect transistor, and wherein said drain terminal of said first PMOS field effect transistor is electrically connected to said source terminal of said first PMOS field effect transistor; and 
a second NMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal, wherein said drain terminal of said second NMOS field effect transistor is electrically connected to said drain terminal of said first PMOS field effect transistor.

2. The apparatus of claim 1 wherein a first voltage applied to said second terminal of said first resistor is greater than a second voltage applied to said drain terminal of said first NMOS field effect transistor by at least the gate-to-source threshold voltage of said first NMOS field effect transistor.

3. The apparatus of claim 1 further comprising a third NMOS field effect transistor having a gate terminal, a source terminal, and a drain terminal, wherein said drain terminal of said third NMOS field effect transistor is electrically connected to said source terminal of said second NMOS field effect transistor.

4. The apparatus of claim 3 wherein said source terminal of said third NMOS field effect transistor is electrically connected to ground voltage.

5. The apparatus of claim 3 further comprising a fourth NMOS field effect transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said fourth NMOS field effect transistor is electrically connected to said source terminal of said second NMOS field effect transistor.

6. The apparatus of claim 5 further comprising a second PMOS field effect transistor having a gate terminal, a drain terminal, and a source terminal, wherein said drain terminal of said second PMOS field effect transistor is electrically connected to said drain terminal of said fourth NMOS field effect transistor, wherein said drain terminal of said second PMOS field effect transistor is electrically connected to said source terminal of said second PMOS field effect transistor, and wherein said gate terminal of said second PMOS field effect transistor is electrically connected to said gate terminal of said first PMOS field effect transistor.

7. The apparatus of claim 6 further comprising a fifth NMOS field effect transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said fifth NMOS field effect transistor is electrically connected to said source terminal of said second PMOS field effect transistor, and wherein said drain terminal of said fifth NMOS field effect transistor is electrically connected to said drain terminal of said first NMOS field effect transistor.

8. The apparatus of claim 7 further comprising a second resistor having a first and second terminal, wherein said first terminal of said second resistor is electrically connected to said gate terminal of said fifth NMOS field effect transistor, and wherein said second terminal of said second resistor is electrically connected to said second terminal of said first resistor.

9. The apparatus of claim 8 wherein the gate terminal of said first PMOS field effect transistor is connected to a control voltage in the range of about 0.9 Volts to about 1.3 Volts.

10. The apparatus of claim 8 wherein said first NMOS field effect transistor, said second NMOS field effect transistor, said third NMOS field effect transistor, said fourth NMOS field effect transistor, said fifth NMOS field effect transistor, said first PMOS field effect transistor, and said second PMOS field effect transistor are produced using a 0.18 micron process.

11. The apparatus of claim 8 wherein a supply voltage applied to said drain terminal of said first NMOS field effect transistor is about 1.8 volts.

12. The apparatus of claim 8 further comprising:
a positive input terminal wherein said positive input terminal is electrically connected to said gate terminal of said second NMOS field effect transistor; 
a negative input terminal wherein said negative input terminal is electrically connected to said gate terminal of said fourth NMOS field effect transistor; 
a bias input terminal wherein said bias input terminal is electrically connected to said gate terminal of said third NMOS field effect transistor; 
a control input terminal wherein said control input terminal is electrically connected to said gate terminal of said first PMOS field effect transistor; 
a positive output terminal wherein said positive output terminal is electrically connected to said source terminal of said fifth NMOS field effect transistor; and, 
a negative output terminal wherein said negative out terminal is electrically connected to said source terminal of said first NMOS field effect transistor.