# Patent

## Title
Current mirror modified level shifter

## Abstract

A current mirror modified level shifter includes a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node connected to a drain of the PMOS (MPR); a pair of NMOS including NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) coupled to drain of the PMOS (MPL), the Vm node being coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).

## Background
FIELD OF THE INVENTION
The present invention generally relates to a level shifter, and especially to a current mirror level shifter.
DESCRIPTION OF THE PRIOR ART
Recently, consumer electronic devices such as mobile telephones and non-volatile semiconductor memory media such as IC memory cards have been downsized, and there have been increasing demands for reducing the number of parts used in the equipment and media and downsizing thereof. Therefore, in the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability. For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting reliability places importance on packaging technologies that are capable of enhancing efficiency of a mounting process and improving mechanical and electrical reliability after the mounting process is completed.
For particular applications, an IC can be integrated with other ICs on an integrated circuit board (PCB). The ICs may have different operating voltages; therefore, it may be a requirement to use more than one power supply voltage setting in order to accommodate the various operating conditions of the ICs. The IC communicates with other ICs in a system using an input/output with higher or lower voltage level. In general, the low internal voltage of the IC may be electrically separated from the high I/O voltage. Therefore, the internal core circuits and I/O circuits may be coupled to different power supplies. For instance, an IC with high voltage elements can use a separate high power supply voltage to operate the circuits properly. The circuits that use the higher power supply voltage and the circuits that use other supply voltages can communicate with each other using a level shifter. A level shifter is a type of circuit that translates logical signals of one voltage level to logical signals of another voltage level.
Samsung Electronics Co., Ltd. (KR) disclosed a level shifter in U.S. Pat. No. 7,295,038, entitled “Digital circuits having current mirrors and reduced leakage current”, filed on Aug. 15, 2005. The leakage current control circuit may include a fourth PMOS transistor MP42. The output compensation circuit may include a fifth PMOS transistor MP41. The leakage current control circuit may reduce leakage current from the level control circuit by pulling up the gate voltages of the transistors MP11 and MP12 in the level control circuit to VDD2. The output compensation circuit may reduce leakage current of the output buffer by maintaining a first output signal at a high level based on a level of the first output signal. Namely, the level shifter of the prior art employed fourth PMOS transistor and fifth PMOS transistor. The structure is too complicated.
Mediatek Inc. also disclosed a type of level shifter in U.S. Pat. No. 7,777,547, entitled “Level shifter for high-speed and low-leakage operation”. The prior art disclosed a voltage level shifter capable of interfacing between two circuit systems having different operating voltage swings. The voltage level shifter comprises an input buffer having a low supply voltage for inverting an external input signal to an internal input signal, and an output buffer having a high supply voltage for inverting the internal input signal to an external output signal. The high level of the external input signal is lower than the high level of the external output signal. The voltage level shifter is designed such that the input buffer is operating to achieve a low-leakage and high-speed performance. The structure includes too many devices and the scheme is still too complicated.
FIG. 1A of the present applications shows a conventional half latch type level shifter. The scheme includes a pair of PMOS coupled to HV respectively. The gates of the pair PMOS are respectively coupled to nodes of Vob and Vot, followed by connecting to a pair of NMOS which have a grounding terminal for each one. A fighting issue occurs during the end of operation cycle as shown in FIG. 1B. The fighting issue will consume charge pump power. It also suffers the large area consumption (MNR) issue. In order to solve the issue, FIG. 2A illustrates another conventional current mirror level shifter. Based on the FIG. 1A scheme, the conventional current mirror level shifter of FIG. 2A removes the cross couple structure and implants a node between the gates of the pair of PMOS, and another node located between PMOS (MPL) and NMOS (MNL). The node between the gates is connected to the node between PMOS (MPL) and NMOS (MNL) to solve the prior art issue. However, the scheme also generates leakage issue which causes the signal delay as shown in FIGS. 2A and 2B. The leakage is:




  
    I
    HV
  
  =
  
    {
    
      
        
          
            
              I
              MPR
            
            ,
          
        
        
          
            when
            ⁢
            
              
            
            ⁢
            S
            ⁢
            
              
            
            ⁢
            E
            ⁢
            
              
            
            ⁢
            L
            ⁢
            
              
            
            ⁢
            is
            ⁢
            
              
            
            ⁢
            low
          
        
      
      
        
          
            
              
                I
                MPR
              
              +
              
                I
                MPL
              
            
            ,
          
        
        
          
            when
            ⁢
            
              
            
            ⁢
            S
            ⁢
            
              
            
            ⁢
            E
            ⁢
            
              
            
            ⁢
            L
            ⁢
            
              
            
            ⁢
            is
            ⁢
            
              
            
            ⁢
            high
          
        
      
    
  




FIG. 3 shows further current mirror level shifter consisting of a pair of PMOS M4, M5 and a pair of NMOS M1, M2. The current mirror level shifter has additional PMOS M3 between the PMOS M4 and NMOS M1, however, the scheme cannot have full swing result.
What is desired is a simplified current mirror level shifter.
SUMMARY OF THE INVENTION
An aspect of the present invention is to provide a simplified current mirror level shifter to solve the power consumption issue and reduce the leakage.
The present invention provides a current mirror modified level shifter which includes a pair of PMOS consisting of a PMOS (MPL) and a PMOS (MPR), wherein a Vot node is connected to a drain of the PMOS (MPR); a pair of NMOS consists of an NMOS (MNL) and an NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) are coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) is coupled to drain of the PMOS (MPL), the Vm node is coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).
A voltage shifter PMOS (MPS) is coupled between gates of the PMOS (MPL) and the PMOS (MPR). A source of the voltage shifter PMOS (MPS) is coupled to the gate of the PMOS (MPL), and a drain of the voltage shifter PMOS (MPS) is coupled to the gate of the PMOS (MPR). A gate of the voltage shifter PMOS (MPS) is coupled to a conductive line between the Vm node and the Va node. An output is coupled a node between the Vot node and a drain of the NMOS (MNR) through two inverters there between. A selection pad is coupled to gates of the NMOS (MNL) and the NMOS (MNR) via an inverter to invert the SEL signal to the gate of the NMOS (MNR).
A current mirror modified level shifter includes a pair of PMOS consisting of a PMOS (MPL) and a PMOS (MPR), wherein a Vot node is connected to a drain of the PMOS (MPR); a pair of NMOS consists of NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) are coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a voltage shifter PMOS (MPS) is coupled between gates of the PMOS (MPL) and the PMOS (MPR).
A source of the voltage shifter PMOS (MPS) is coupled to the gate of the PMOS (MPL), and a drain of the voltage shifter PMOS (MPS) is coupled to the gate of the PMOS (MPR). A gate of the voltage shifter PMOS (MPS) is coupled to a conductive line between the Vm node and a Va node between the PMOS (MPL) and NMOS (MNL). An output is coupled a node between the Vot node and a drain of the NMOS (MNR) through two inverters there between. A selection pad is coupled to gates of the NMOS (MNL) and an inverter, and the output of the inverter is coupled to the gate of the NMOS (MNR) to invert the SEL signal to the gate of the NMOS (MNR).



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B show an embodiment of the level shifter according to prior art.
FIGS. 2A and 2B show an embodiment of the level shifter according to prior art.
FIG. 3 shows another embodiment of the level shifter according to prior art.
FIGS. 4A and 4B show an embodiment of the level shifter according to the present invention.
FIGS. 5A and 5B show an embodiment of the level shifter according to the present invention.



DESCRIPTION OF THE PREFERRED EMBODIMENT
Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying claims.
The present invention provides a current mirror modified level shifter, having a pair of PMOS consisting of a PMOS (MPL) and a PMOS (MPR), and a pair of NMOS consisting of NMOS (MNL) and a NMOS (MNR). A suspended PMOS (MPM) is coupled to drain of the PMOS (MPL) to reduce the consumption power. Sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; the gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR). A voltage shifter PMOS (MPS) is employed to reduce the leakage, thereby improving the performance of the level shifter.
Please refer to FIG. 4A, the present invention generally relates to a level shifter with current mirror modified (CMM) scheme. The scheme includes a pair of PMOS (MPL and MPR) and a pair of NMOS (MNL and MNR). The source terminals of the pair of PMOS (MPL and MPR) are coupled to the high voltage (HV), respectively. The gates of the pair of PMOS are coupled together through a node Vm which located between the gates of the pair of PMOS (MPL and MPR). A Vot node is connected to the drain terminal of one of the pair of the PMOS. A drain terminal of another one of the pair of the PMOS is connected to the source of additional suspended PMOS (MPM). The Vm node is coupled to the node Va which is connected to the drain terminal of the suspend PMOS (MPM). The gate of the suspend PMOS (MPM) is coupled to the Vot.
The drain of the NMOS (MNL) of the pair of NMOS is coupled to the node Va and the source terminal is ground; the gate of the NMOS (MNL) is coupled to the selection pad (SEL). Further, the drain of the NMOS (MNR) of the pair of NMOS is coupled to the node Vot and the source terminal is ground; the gate of the NMOS (MNR) is coupled to the output of and inverter which located between the selection pad (SEL) and an inverter, wherein the output of the inverter is coupled to the gate NMOS (MNR). Finally, the output terminal of the CMM level shifter is coupled the node between the drain of the NMOS (MNR) and the node Vot through a buffer, for example, the buffer may include two inverters.
The suspend PMOS may block the DC current. When the SEL go high, NMOS (MNL) turn on, then the Vot will go high as well and thereby turning off the MPM to reduce the power consumption. The power consumption is low which may refer to the result shown in FIG. 4B.
Please refer to FIG. 5A, it illustrates another embodiment of the present invention. Based on the scheme (Current mirror modified enhancement level shifter; CMME) of FIG. 5A, most of the scheme is similar with FIG. 4A, a voltage shifter PMOS (MPS) is introduced between the gate terminals of the pair of the PMOSs (MPL and MPR) to raise the Vm voltage. The source of the PMOS (MPS) is coupled to the gate of the PMOS (MPL), while the drain of the PMOS (MPS) is coupled to the gate of the PMOS (MPR). The gate of the PMOS (MPS) is coupled to the conductive line between the node Vm and the node Va. When the SEL is at low stage, then the Vm node goes Vdd (high stage) to reduce the leakage, please refer to FIG. 5B.
For the present approaches, the present invention provides a suspended PMOS (MPM) and/or voltage shifter PMOS (MPS) to reduce the power consumption and/or to reduce the leakage, thereby improving the performance of the level shifter.
An embodiment is an implementation or example of the present invention. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments of the present invention, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims are hereby expressly incorporated into this description, with each claim standing on its own as a separate embodiment of this invention.

## Claims

1. A current mirror modified level shifter, comprising:
a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node is connected to a drain of said PMOS (MPR);
a pair of NMOS including a NMOS (MNL) and a NMOS (MNR), wherein sources of said PMOS (MPL) and said PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of said PMOS (MPL) and said PMOS (MPR) are coupled together through a Vm node which is located between said gates of said PMOS (MPL) and said PMOS (MPR);
a suspended PMOS (MPM) coupled to drain of said PMOS (MPL), said Vm node being coupled to a Va node between drain of said suspended PMOS (MPM) and drain of said NMOS (MNL); and
a voltage shifter PMOS (MPS) coupled between gates of said PMOS (MPL) and said PMOS (MPR).

2. The current mirror modified level shifter according to claim 1, wherein a source of said voltage shifter PMOS (MPS) is coupled to said gate of said PMOS (MPL), and a drain of said voltage shifter PMOS (MPS) is coupled to said gate of said PMOS (MPR).

3. The current mirror modified level shifter according to claim 2, wherein a gate of said voltage shifter PMOS (MPS) is coupled to a conductive line between said Vm node and said Va node.

4. The current mirror modified level shifter according to claim 1, wherein an output is coupled between said Vot node and a drain of said NMOS (MNR) through a buffer.

5. The current mirror modified level shifter according to claim 1, wherein a selection pad is coupled to gates of said NMOS (MNL) and an inverter, wherein an output of said inverter is coupled to said gate of the NMOS (MNR).

6. A current mirror modified level shifter, comprising:
a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node is connected to a drain of said PMOS (MPR);
a pair of NMOS including a NMOS (MNL) and a NMOS (MNR), wherein sources of said PMOS (MPL) and said PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of said PMOS (MPL) and said PMOS (MPR) are coupled together through a Vm node which is located between said gates of said PMOS (MPL) and said PMOS (MPR);
a suspended PMOS (MPM) coupled to drain of said PMOS (MPL), said Vm node being coupled to a Va node between drain of said suspended PMOS (MPM) and drain of said NMOS (MNL);
a voltage shifter PMOS (MPS) coupled between gates of said PMOS (MPL) and said PMOS (MPR); and
wherein a gate of said voltage shifter PMOS (MPS) is coupled to a conductive line between said Vm node and said Va node.

7. The current mirror modified level shifter according to claim 6, wherein an output is coupled between said Vot node and a drain of said NMOS (MNR).

8. The current mirror modified level shifter according to claim 6, wherein a selection pad is coupled to gates of said NMOS (MNL) and an inverter, wherein an output of said inverter is coupled to said gate of the NMOS (MNR).