# Patent

## Title
Hierarchical write-combining cache coherence

## Abstract

A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.

## Background
BACKGROUND
1. Field
The embodiments are generally directed to managing memory, and more specifically to managing memory among heterogeneous computer components.
2. Background Art
A computing device generally includes one or more processing units (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), an accelerated processing unit (APU), or the like), that access a shared main memory. The processing units may execute programs (e.g., instructions or threads) that result in accesses to main memory. Because memory accesses may traverse a memory hierarchy including levels of cache and main memory, memory accesses may have different latencies, and may be performed in a different order than what was intended by the programs. In addition there may be conflicts, e.g., when two memory accesses attempt to store data in the same memory location.
Memory accesses are also called memory events, and examples include a store event (i.e., a memory access request to write data to main memory), a load event (i.e., a memory access request to read data from main memory), and synchronization events that are used to order conflicting memory events.
Memory consistency models provide rules for ordering memory events. A type of memory consistency model, release consistency with special accesses sequentially consistent (RCsc), provides a framework for event ordering for parallel programs with synchronization. Current systems that implement an RCsc memory model, a write-through (WT) memory system and a write-combining (WC) memory system, have difficulty with synchronization events such as a store release (StRel) synchronization event.
A StRel synchronization event is a release synchronizing store instruction that acts like an upward memory fence such that prior memory operations are visible to threads that share access to the ordering point before the store event portion of the StRel completes. A load acquire (LdAcq) synchronization event is a synchronizing load instruction that acts as downward memory fence such that later operations cannot occur before the LdAcq operation.
Upon executing a StRel synchronization event in a WT memory system, data is immediately written-through to main memory which is an inefficient use of the precious bandwidth resources to main memory. In addition, the system tracks acknowledgements for individual store completions which is highly inefficient. Further, upon receiving a load acquire synchronization event, the system performs a full cache flush to invalidate clean and potentially stale data which makes data reuse in the presence of synchronization impossible.
The WC memory system uses cache hierarchies to coalesce store events. Executing a StRel synchronization event in the WC triggers a slow and intensive cache flush to determine when the prior stores have completed to a next level of hierarchy. A cache flush entails walking through an entire cache hierarchy to track outstanding store events to completion.
In addition, write-combining caches incur overhead to track dirty bytes in cache lines in the memory hierarchy.
A hierarchical directory/snooping cache coherence protocol solution is a “read for ownership” solution that could support an RCsc memory consistency model, however, the memory access requests to write data encounter long delays. A requesting processor (e.g., a CPU or GPU) has to read or own a memory block before writing to local cache and completing a store event.
BRIEF SUMMARY OF EMBODIMENTS
What is needed therefore, are approaches that enforce an RCsc memory model and can execute release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. In embodiments, a requesting processor does not have to read or own a memory block before writing in local cache and completing a store event. Certain embodiments may, in certain conditions, improve the performance of both global synchronization events (e.g., writing to main memory for completion) and local synchronization events (e.g., writing to a common ordering point such as level 2 cache for completion) since the cache hierarchy does not need to be flushed and a store event may not need to reach main memory to complete. Further embodiments include decoupling a store event from an ordering of the store event with respect to a RCsc memory model.
Certain embodiments include a method, computer program product, and a system. For example, a system embodiment includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a component maintains a partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, and direct write-throughs to memory. Some embodiments provide RCsc memory model programmability while efficiently using limited bandwidth.
Certain embodiments further include a read-only cache and a write-only combining cache at respective levels in the memory hierarchy to reduce the overhead in managing the write-combining cache. Data written to cache as a result of a store event for example, is called dirty data, and is different than the data that resides in the location in main memory. Dirty data is eventually written to main memory.
Certain embodiments also include a method for receiving a memory event. When the memory event is a store event, the method further includes: writing a first data to a write-only, level n cache, where n is an integer representing the level of cache hierarchy. The method further includes writing, to a level n pool, a store entry that includes an address of the first data in the level n cache, where the level n pool maintains a partial order among the store entry, a prior received store entry, and a release marker entry, and when a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker. When the memory event is a load event, the method further includes searching a read-only, level n cache for a second data, and determining when the second data is present in a corresponding write-only, level n cache.
A further embodiment includes a computer program product having instructions stored thereon, where the execution of the stored instructions results in a processing unit causes the following steps to be performed. First, a memory event is received. When the memory event is a store event, the next step includes writing a first data to a write-only, level n cache, where n is an integer representing the level of cache hierarchy. Subsequent steps include writing, to a level n pool, a store entry that includes an address of the first data in the level n cache, where the level n pool maintains a partial order among the store entry, a prior received store entry, and a release marker entry, and when a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker. When the memory event is a load event, the next step includes searching a read-only, level n cache for a second data, and determining when the second data is present in a corresponding write-only, level n cache.
Another embodiment includes a processing unit configured to perform the following functionality. First, the processing unit receives a memory event. When the memory event is a store event, the processing unit writes a first data to a write-only, level n cache, where n is an integer representing the level of cache hierarchy. Subsequently, the processing unit writes to a level n pool a store entry that includes an address of the first data in the level n cache, where the level n pool maintains a partial order among the store entry, a prior received store entry, and a release marker entry, and when a release marker is present, orders the store entry in the level n pool to follow a most-recent release marker. When the memory event is a load event, the processing unit searches a read-only, level n cache for a second data, and determines when the second data is present in a corresponding write-only, level n cache.
Further features and advantages of the embodiments, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. It is noted that the embodiments are not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.



BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the embodiments and, together with the description, further serve to explain the principles of the embodiments and to enable a person skilled in the pertinent art to make and use the embodiments. Various embodiments are described below with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout.
FIG. 1 illustrates an APU environment, according to an embodiment.
FIG. 2 illustrates a write-back write-combine system, according to an embodiment.
FIG. 3A illustrates a GPU with separate read-only cache and write-only cache, according to an embodiment.
FIG. 3B illustrates a GPU with separate read-only cache, write-only cache, and dirty read buffers (DRBs) according to an embodiment.
FIG. 4 illustrates a method of handling the receipt of memory events, according to an embodiment.
FIG. 5 illustrates a method of evicting entries, according to an embodiment.
FIG. 6 illustrates a method of handing memory synchronization events, according to an embodiment.
FIG. 7 illustrates a method of evicting entries from a queue, according to an embodiment.
FIG. 8 illustrates an example computer system in which embodiments may be implemented.



The embodiments will be described with reference to the accompanying drawings. Generally, the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION OF EMBODIMENTS
In the detailed description that follows, references to “one embodiment,” “an embodiment,” “an example embodiment,” etc. indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation. Alternate embodiments may be devised without departing from the scope of the disclosure, and well-known elements of the disclosure may not be described in detail or may be omitted so as not to obscure the relevant details. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Computing devices process data and provide many applications to users. Example computing devices include, but are not limited to, mobile phones, personal computers, workstations, and game consoles. Computing devices use a central processing unit (“CPU”) to process data. A CPU is a processor which carries out instructions of computer programs or applications. For example, a CPU carries out instructions by performing arithmetical, logical and input/output operations. In an embodiment, a CPU performs control instructions that include decision making code of a computer program or an application, and delegates processing to other processors in the electronic device, such as a graphics processing unit (“GPU”).
A GPU is a processor that is a specialized electronic circuit designed to rapidly process mathematically intensive applications (e.g., graphics) on electronic devices. The GPU has a highly parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common to computer graphics applications, images and videos. The GPU may receive data for processing from a CPU or generate data for processing from previously processed data and operations. In an embodiment, the GPU is a hardware-based processor that uses hardware to process data in parallel.
Due to advances in technology, a GPU also performs general purpose computing (also referred to as GPGPU computing). In the GPGPU computing, a GPU performs computations that traditionally were handled by a CPU. An accelerated processing unit (APU) includes at least the functions of a CPU and a GPU. The GPU can be a GPGPU.
In an embodiment, a GPU includes one or more compute units (CUs) that process data. A compute unit (CU) includes arithmetic logic units (ALUs) and other resources that process data on the GPU. Data can be processed in parallel within and across compute units.
In an embodiment, a control processor on a GPU schedules task processing on compute units. Tasks include computation instructions. Those computation instructions may access data stored in the memory system of a computing device and manipulate the accessed data. In an embodiment, the data may be stored in volatile or non-volatile memory. An example of volatile memory includes random access memory (RAM). Examples of RAM include dynamic random access memory (DRAM) and static random access memory (SRAM). Volatile memory typically stores data as long as the electronic device receives power. Examples of non-volatile memory include read-only memory (ROM), flash memory, ferroelectric RAM (F-RAM), hard disks, floppy disks, magnetic tape, optical discs, etc. Non-volatile memory retains its memory state when the electronic device loses power or is turned off.
FIG. 1 illustrates an APU environment, according to an embodiment. In the example shown, system 100 is an APU environment that includes CPU 110, GPU 130, main memory 150, and bus 140.
Bus 140 may be any type of communication infrastructure used in computer systems, including a peripheral component interface (PCI) bus, a memory bus, a PCI Express (PCIE) bus, front-side bus (FSB), hypertransport (HT), or another type of communication structure or communications channel whether presently available or developed in the future.
FIG. 2 illustrates a write-combining (WC) system, according to an environment. WC System 200 includes a conventional GPU and bus 140. WC System 200 includes CUs 210a and 210b, and a multi-tiered write-combining cache including Level 1 (L1) caches 220a and 220b, as well as Level 2 (L2) cache 240. L2 cache 240 is shared among CUs 210 in system 200. Bus 230 is substantially the same as bus 140 of FIG. 1.
In WC System 200, write-combining caches provide coherence for data-race-free programs (e.g., programs free of memory accesses conflicts) by writing updates to an ordering point (e.g., L2 cache 240 or main memory 150) at synchronization events. In addition, write-combining caches use a write-back policy that keeps previously written data in cache longer than the WT alternative. This policy increases the chance that the results of two store events coalesce in cache before consuming the limited bandwidth at a synchronization event to evict the data to a next-level cache in the memory hierarchy. However, the cost of a synchronization event in WC System 200 is high. Upon execution of a StRel synchronization event, for example, WC System 200 must perform a full cache flush to find and flush outstanding writes throughout the cache hierarchy to completion to ensure proper ordering of memory events. A write is data written by a store event. WC System 200 searches L1 caches 220a and 220b as well as L2 cache 240 to find data previously written, also called dirty data. Once dirty data is found, WC System 200 evicts the dirty data to a next level of cache hierarchy, or main memory 150 if a next-level cache is not present, and waits for acknowledgements to be received before processing another memory event. The cache flush process is a very slow and tedious process to be avoided.
Embodiments utilize separate read-only cache and write-only combining caches to enforce a RCsc model, and avoid tracking outstanding store events via the memory hierarchy. Embodiments utilize extra knowledge to manage a partial order of outstanding writes and release synchronization events separately from the outstanding writes that move through a memory hierarchy. Because store events are not tracked via the memory hierarchy, acknowledgement messages are not needed for store event completions resulting in reduced traffic. In addition, embodiments allow a store event to complete without having to write-through to main memory 150.
A memory fence is an operation used to delay a memory access until the previous memory access has been performed. Synchronization events utilize memory fences to provide order by making results visible (i.e., available for reading) in a globally shared memory so that other instructions in the computing device may utilize the results.
The RCsc consistency model requires that prior store events that occur before a StRel synchronization event be visible (i.e., readable) in a specified scope (e.g., global or local) and that loads after a LdAcq appear to be executed after the LdAcq. Also, the LdAcqs and StRels themselves obey sequential consistency so a StRel needs to complete the writes before a LdAcq may proceed to read the writes.
A scope is a group of threads that access a shared memory or a common ordering point. Global scope requires global synchronization and a store event is complete when the data written in main memory 150 is visible to other threads in the system. Local scope requires local synchronization and a store event is complete when the data is written to a common ordering point such as a level 2 cache, and is visible to threads that share access to that common ordering point. The ability to synchronize to a local scope when possible, instead of having to synchronize to a global scope provides considerable savings with regards to limited bandwidth access to main memory, reduced latency, and power savings.
In write-combining caches, store events are more costly to support than load events because a write-combining cache allows partial cache line writes without exclusive ownership (i.e., allows multiple writers). A system tracks dirty bytes within a cache line to merge writes to different bytes of the same cache line. Most implementations use a respective dirty byte bitmask for a cache line (e.g., 12.5% overhead for 64-byte cache lines) and write out the dirty portions of a cache line on evictions. Thus, write-combining caches incur overhead for implementing a respective dirty byte mask for a cache line in the memory hierarchy.
Typically, in current GPU and GPGPU applications, the number of load (read) events vastly outnumber store (write) events. And among the store events, a small subset require intermediate visibility before being written to main memory 150. Thus, the number of read-after-write (RAW) operations is relatively small.
Embodiments reduce the overhead by splitting a write-combining cache at one or more levels into a read-only cache and a write-only combining cache. Because the number of reads is larger than the number of writes, the read-only cache can be larger and the write-only cache can be smaller. The separation of the read-only and write-only cache encourages data path optimizations such as independent and lazy management of write bandwidth while minimizing implementation complexity. And, as GPU threads seldom perform RAW operations, the potential costs of the separation are low.
In an embodiment, a special victim buffer called a dirty read buffer (DRB) can be used to provide dirty bit masks on the smaller write-only cache. The DRB keeps track of writes (dirty data) in the write-only cache and sources requests to read dirty data in the write-only cache (i.e., a RAW operation). As RAW operations are infrequent, the DRB is a simple implementation that separates the read-only and write-only operations.
FIG. 3A illustrates a GPU with separate read-only cache and write-only combining cache, according to an embodiment. System 300 includes a memory hierarchy of read-only caches rL1 370a, rl1 370b, and rL2 380, write-only combining buffers wL1 320a, wL1 320b, and wL2 340, corresponding co-located pool components L1 pool 350a, L1 pool 350b and L2 pool 360, as well as compute units CU 310a and CU 310b. 
A read-only cache is also called clean cache and contains data identical to the location in main memory 150. A read-only cache includes at least one of but is not limited to an address that corresponds to a memory location in main memory, a cache tag, a partial address, a cache line, and an indication of whether the cache line or bytes of the cache line are invalid. The bytes are invalid if the bytes are written to a corresponding write-only cache. To search for a cache line in a cache, a system may search for at least one of an address, a cache tag, or a partial address of the cache line.
An example of the indication can include a write-only, cache-present bit. When set, the write-only, cache-present bit indicates, for example, that dirty data (i.e., newly written data will be written to main memory 150) exists in the corresponding write-only cache for the same cache line. When clear, the write-only, cache-present bit indicates, for example, that no dirty data exists in the corresponding write-only cache for the same cache line.
The write-only cache can be much smaller than the read-only cache, contains dirty data, i.e., the write-only cache contains data that is different to the location in main memory 150 as it has not yet been written to main memory 150. A write-only cache includes at least one of but is not limited to an address that corresponds to a memory location in main memory, a cache tag, a partial address, and a dirty byte bitmask.
Pool components contain knowledge to track outstanding store events separately from the ordering of store events in the memory hierarchy that occurs when enforcing an RCsc memory model. Pool components L1 pool 350a, L1 pool 350b, and L2 pool 360 contain knowledge that enables system 300 to track which prior writes and corresponding addresses that may not yet be written back to main memory 150, without having to perform a cache walk, or implementing power-hungry CAM lookups to track acknowledgements.
Pool components L1 pool 350a, L1 pool 350b, and L2 pool 360 may be implemented for example, by a synchronization First In First Out (S-FIFO) or a Bloom-filter with signatures as are well known in the art. A pool component may contain entries associated with a store event or a release synchronization event. An entry associated with a store event may include but is not limited to an address in main memory and a thread identity of a store event. A thread identity is used to recognize different threads. An entry associated with a release synchronization event is a release marker that may include but is not limited to a thread identity of a release synchronization event.
The pool and write-only combine cache do not require inclusion. That is, the write-only cache does not need to contain the data associated with all entries in the pool. For example, some data may be evicted early due to cache replacement policies or a load event with a partial hit that causes an early data eviction.
FIG. 3B illustrates a GPU with separate read-only cache, write-only cache, and dirty read buffers (DRBs) according to an embodiment. A dirty read buffer (DRB) may be collocated with a write-only and read-only cache at a corresponding level and the DRB is used to maintain a separation among read-only cache and write-only cache. A DRB may include but is not limited to include an address, and an indication of the dirty bytes in the write-only cache. In addition to the elements shown in FIG. 3A, FIG. 3B includes DRB 1 375a and DRB1 375b, as well as DRB2 385.
When a DRB is present, a read-only cache includes at least one of but is not limited to an address that corresponds to a memory location in main memory, a cache tag, a partial address, and a cache line. Unlike FIG. 3A, an indication of whether the cache line or bytes of the cache line are invalid (e.g., write-only, cache-present bit) is not necessary in the read-only cache as the information is found in the corresponding DRB, and reads to the read-only cache and the corresponding DRB can occur in parallel. When the address is found in the DRB, any corresponding data also found in the read-only cache is considered invalid. Bytes in the read-only cache are invalid if new data is written to the address of the bytes in a corresponding write-only cache. To search for a cache line in a cache, a system may search for at least one of an address, a cache tag, or a partial address of the cache line.
FIG. 4 illustrates a method of handling the receipt of memory events, according to an embodiment. In one example, system 100 and system 300 may be used to demonstrate method 400. It is to be appreciated that operations in method 400 may be performed in a different order than shown, and method 400 may not include all operations shown. For ease of discussion, and without limitation, method 400 will be described in terms of elements shown in FIG. 1, FIG. 3A, and FIG. 3B.
Method 400 begins at step 410 and proceeds to step 415.
At step 415, memory events such as a store, a load, or a release synchronization are received from a compute unit such as CU 310a. The memory events are read from a software program e.g., instruction code, in program order.
When a load event is received, at step 420, method 400 looks for the address of the data in rL1 370a and checks the write-only, cache-present bit. Method 400 proceeds to step 425.
At step 425, if the data is found in rL1 370a (a hit), and the write-only, cache-present bit is clear, the data is read and method 400 returns to step 415 to await another memory event. The write-only, cache-present bit being clear indicates that there is no dirty data in the corresponding wL1 320a waiting to be written to main memory 150 and thus the data in rL1 370 is not stale.
At step 425, when the write-only, cache-present bit is set, (i.e., dirty data for the cache line is present in wL1 320a) wL1 320a is checked to see if the load event can be fully satisfied by the dirty bytes present. If the data is found in wL1, 320a, the load event (read) is completed and method 400 proceeds to step 415.
At step 425, if the data is not found in rL1 370a (a miss), and the write-only, cache-present bit is clear, method 400 proceeds to step 427. Also, if a L2 memory hierarchy is not present, method 400 proceeds to step 430.
At step 425, when there is a partial hit in wL1 320a, for example, the write-only, cache-present bit is set, some of the data is found in wL1 320a, and a Level-2 memory hierarchy is not present, the dirty bytes are written through from wL1 320a to main memory 150 (not shown). Method 400 proceeds to step 430.
At step 425, if the data is partially found in wL1 320a, the dirty data in wL1 320a is written to wL2 340. The read request is sent to the next level of the memory hierarchy to L2 cache hierarchy. Method 400 proceeds to step 427. As noted earlier, a partial hit is an infrequent occurrence due to the low number of RAW operations.
At step 427, method 400 looks for the data, or the remaining data in the case of a partial hit, in rL2 380; if the data or the remaining data is found in rL2 380 (a hit), and the write-only, cache-present bit is clear, the data is read from rL2 380 and method 400 returns to step 415 to await another memory event.
At step 427, if the data is not found in rL2 380 (a miss) and the write-only, cache-present bit is clear, method 400 proceeds to step 430.
At step 427, when the write-only, cache-present bit is set, (i.e., dirty data for the cache line is present in wL2 340) wL2 340 is checked to see if the load event can be fully satisfied by the dirty bytes present. If the data is found in wL2 340, the read is completed and method 400 proceeds to step 415.
At step 427, when the write-only, cache-present bit is set and the data is partially found and read from wL2 340 (a partial hit), the dirty data in wL2 340 is written to main memory 150. Data at rL1 370a and rL1 370b with that address are invalidated, and method 400 proceeds to stop 430.
At step 430, the data is read from main memory 150. Method 400 proceeds to step 415.
In an embodiment, DRBs are implemented at corresponding levels of the memory hierarchy. Method 400 begins at step 410 and proceeds to step 415.
When a load event is received, at step 420, method 400 looks for the address of the data in parallel in rL1 370a and DRB1 375a. Method 400 proceeds to step 425.
At step 425, if the data is found in rL1 370a (a hit), and not in DRB1 375a, the data is read and method 400 returns to step 415 to await another memory event.
At step 425, when the address is found in DRB1 375a, (i.e., dirty data for the cache line is present in wL1 320a) DRB1 375a is checked to see if the load event can be fully satisfied by the dirty bytes present. If the data is found in DRB1 375a, the load event (read) is completed and method 400 proceeds to step 415.
At step 425, if the data is not found in rL1 370a (a miss), or DRB1 375a, method 400 proceeds to step 427. Also, if a L2 memory hierarchy is not present, method 400 proceeds to step 430.
At step 425, when there is a partial hit in DRB1 375a, for example, some of the data is found in DRB1 375a, and a Level-2 memory hierarchy is not present, the dirty bytes are written through from wL1 320a to main memory 150 (not shown). Method 400 proceeds to step 430.
At step 425, if the data is partially found in DRB1 375a (a partial hit), the dirty data in wL1 320a is written to wL2 340. The read request is sent to the next level of the memory hierarchy to L2 cache hierarchy. Method 400 proceeds to step 427.
At step 427, method 400 looks for the data, or the remaining data in the case of a partial hit, in parallel in rL2 380 and DRB2 385; if the data or the remaining data is found in rL2 380 (a hit), but not in DRB2 385, the data is read from rL2 380 and method 400 returns to step 415 to await another memory event.
At step 427, if the data is not found in rL2 380 (a miss) or DRB2 385, or if L2 memory hierarchy is not present, method 400 proceeds to step 430.
At step 427, the address is found in DRB2 385 (i.e., dirty data for the cache line is present in wL2 340) DRB2 385 is checked to see if the load event can be fully satisfied by the dirty bytes present. If the data is found in DRB2 385, the read is completed and method 400 proceeds to step 415.
At step 427, when the address is found in DRB2 385 and the data is partially found and read from DRB2 385 (a partial hit), the dirty data in wL2 340 is written to main memory 150. Data at rL1 370a and rL1 370b with that address are invalidated, and method 400 proceeds to stop 430.
At step 430, the data is read from main memory 150. Method 400 proceeds to step 415.
When a store event is received at step 415, method 400 proceeds to step 435.
At step 435, method 400 writes the data affiliated with an address to wL1 320a and the data is called dirty data as it is not the same as the memory location at the same address in main memory 150. The dirty byte bitmask of wL1 320a is updated to indicate the dirty bytes of cache line associated with the address. In addition, method 400 checks to see if the address is found in rL1 370a. When the address is found in rL1 370a, method 400 sets a flag of a cache tag, to indicate that updated data is in the wL1 320a (e.g., sets the write-only, cache-present bit in the rL1 370a). The store operation completes immediately.
In an embodiment, when a DRB is implemented, e.g., DRB1 375a, the dirty byte bitmask of DRB1 375a would be updated. In an embodiment, the write-only, cache-present bit would not be needed in rL1 370a as the read to rL1 370a can occur in parallel as a read to DRB1 375a. 
While the DRB example is not propagated throughout the rest of the specification, one skilled in the art can readily understand how a DRB could be implemented accordingly.
At step 440, a store entry is written to L1 pool 350a that can include but is not limited to the address location in main memory 150 to which the data is to be written, and a thread identity. A thread is a work item involved with the current instruction execution that includes the store event. The L1 pool 350a maintains a partial order among the store entry, any prior received store entries that may exist, and any release marker entries.
In an example, two groups of prior store entries may exist in L1 pool 350a that are separated by a release marker described below. While no particular order within a group of prior store entries exists, the first group of prior store entries is ordered to be evicted before the release marker, and the second group is ordered to be evicted after the release marker. Thus there is partial order in the pool.
The store entry is written in L1 pool 350a to follow the most-recent release marker. In the example, the store entry would be added to the second group of existing prior store entries in no particular order.
Method 400 proceeds to step 415.
When a release synchronization event such as a release, a StRel, a fence, a kernel end, or a barrier operation is received at step 415, method 400 proceeds to step 445. A release marker is written to L1 pool 350a and ordered to follow any prior write entries in L1 pool 350a. The entry of the release marker in L1 pool 350a triggers eviction of any prior write entries from the L1 pool 350a. Thus, the release marker will be evicted after the prior entries in L1 pool 350a to ensure proper visibility of prior writes.
At step 450, if the release synchronization event is a StRel, method 400 proceeds to step 455. At step 455, method 400 writes data associated with the store event portion of the StRel to wL1 320a. At step 460, a corresponding store entry associated with the store event portion of the StRel is made to L1 pool 350a and ordered to follow the most-recent release marker. The store entry includes an address location in main memory 150 to which the data is to be written, and a thread identity, for example. Method 400 checks to see if the address is found in rL1 370a. When the address is found in rL1 370a, method 400 sets the write-only, cache-present bit in the rL1 370a; the write-only, cache-present bit may be a bit or a flag in for example, a cache tag, that indicates that updated data is in the wL1 320a. The method proceeds to step 415.
At step 450, if the release synchronization event is not a StRel, method 400 proceeds to step 415.
FIG. 5 illustrates a method of evicting entries, according to an embodiment. In one example, system 100 and system 300 may be used to demonstrate method 500. It is to be appreciated that operations in method 500 may be performed in a different order than shown, and method 500 may not include all operations shown. For ease of discussion, and without limitation, method 500 will be described in terms of elements shown in FIG. 1 and FIG. 3.
Method 500 depicts the flow of operations when evictions from a pool occur. Evictions can occur, for example, when the number of entries in a pool exceeds a settable maximum value, or when a release marker is added to the pool and triggers prior write evictions. Method 500 includes operations at the L1 pool 350a and L2 pool 360, for example.
Method 500 begins at step 510 and proceeds to step 515.
At step 515, method 500 proceeds to step 520 to depict L1 pool 350a eviction operations.
At step 520, method 500 determines whether L1 pool 350a evicts a store entry or a release marker entry.
If a release marker is present in L1 pool 350a and no prior writes exist ahead of the release marker entry, method 500 determines to evict a release marker entry and proceeds to step 525.
At step 525, the release marker is evicted from L1 pool 350a to L2 pool 360. The release marker is ordered to follow any prior store entries in L2 pool 360. The addition of the release marker triggers evictions of any prior store entries from L2 pool 360, before the eviction of the release marker from L2 pool 360. When a L2 memory hierarchy is not present, the release marker is evicted from L1 pool 350a, and an acknowledgement is sent to the originating thread that the release is complete.
Method 500 proceeds to step 545.
At step 520, if a release marker is present in L1 pool 350a, the prior store entries in L1 pool 350a ahead of the release marker are determined to be evicted to a L2 pool 360, and corresponding data in wL1 320a are correspondingly evicted to wL2 340. The prior store entries can be evicted in any order with respect to prior store entries. But, prior store entries and corresponding data in wL1 320a are evicted before the oldest release marker is evicted. Thus, the written data is guaranteed to be at the next level of the hierarchy by the time the release marker is evicted.
At step 520, if L1 pool 350a is determined to evict a store entry, method 500 proceeds to step 530.
At step 530, method 500 determines if the corresponding data exists in the wL1 320a. If the corresponding data does not exist, method 500 proceeds to step 535. At step 535, a cache replacement policy as is well known in the art, may be enforced and previously evicted the data from wL1 320a; the store entry in L1 pool 350a is evicted to L2 pool 360. In addition, a special case of a load event with a partial hit may also cause an early data eviction. Thus, embodiments support early evictions from the memory hierarchy. Method 500 proceeds to step 545.
At step 530, if the corresponding data does exist in the wL1 320a, method 500 proceeds to step 540.
At step 540, the store entry in L1 pool 350a is evicted to L2 pool 360. In addition, the corresponding data in L1 cache 320a is evicted to wL2 340.
When a L2 cache hierarchy is not present (not shown), embodiments include the following: evicting the prior store entry from the L1 pool 350a; evicting data, when present, from the wL1 320a associated with the evicted prior store entry to main memory; when the evicted prior store entry is associated with a StRel release synchronization event, signaling completion of release to the originating thread.
When a L2 cache hierarchy is present and the L2 cache hierarchy is an ordering point (not shown), embodiments further include the following: evicting the prior store entry from L1 pool 350a; evicting data, when present, from the wL1 320a associated with the evicted prior store entry to the ordering point; when the evicted prior store entry is associated with a StRel release synchronization event, signaling completion of release to the originating thread. Thus, a StRel can complete at an ordering point other than main memory, and local synchronization is possible (e.g., receipt of a LdAcq can complete at wL2 340 without having to access main memory 150). Note that main memory 150 can also be an ordering point and would be a global ordering point.
Method 500 proceeds to step 545.
At step 515, method 500 proceeds to step 545 to depict L2 pool 360 eviction operations.
At step 545, method 500 determines whether L2 pool 360 evicts a store entry or a release marker entry. Evictions may occur when a release marker entry is added to L2 pool 360 that triggers evictions, or when the number of L2 pool 360 entries exceeds a configurable threshold, for example. If L2 pool 360 evicts a release marker entry, method 500 proceeds to step 550.
At step 550, the release marker is evicted from L2 pool 360. In addition, method 500 transmits an acknowledgment to the originating thread or original requester, CU 310a, that the release event is complete. The release completion provides assurance that safe forward progress is possible beyond the release synchronization event.
Note that for a StRel release synchronization event, CU 310a does not need to wait for the acknowledgement, but rather CU 310a can continue processing other memory events until executing the next LdAcq. But, for barrier and fence release synchronization events, CU 310a waits until a corresponding acknowledgement is received. Further, additional embodiments enable unsynchronized stores, if allowed by the memory model. These unsynchronized stores would not generate a store entry in L1 Pool 350a, rather, corresponding data could be written to wL1 320a. Thus, unsynchronized stores would not load pool components with unnecessary operations.
The method proceeds to step 565.
At step 545, if L2 pool 360 evicts a store entry, method 500 proceeds to step 555.
At step 555, method 500 determines if the corresponding data exists in the wL2 340. If the corresponding data does not exist, (e.g., due to a cache replacement policy enforcement) the store entry is evicted from L2 pool 360 and method 500 proceeds to step 565.
At step 555, if the corresponding data does exist, method 500 proceeds to step 560.
At step 560, the store entry is evicted from L2 pool 360. In addition, the corresponding data in wL2 340 is evicted to main memory 150. Further, if the data was from a store event portion of a StRel, method 500 signals completion of release to the originating thread.
Embodiments invalidate the data in rL1 370a and rL1 370b associated with the corresponding address. The invalidations may be completed by broadcasting invalidation messages to rL1 370a and rL1 370b caches, to ensure release consistency. The invalidations are not critical to performance as the invalidations merely delay release synchronization completions and are bound based on the number of entries in L2 pool 360 when a release synchronization event occurs. Note that write evictions and load requests do not stall waiting for invalidations. In addition, the data in rL1 370a and rL1 370b can be invalidated with a flash clear, e.g., when a LdAcq is received, all blocks in the cache are invalidated. The flash clear does not need to be associated with the corresponding address.
Method 500 proceeds to step 565.
Logically, L1 pool 350a, L1 pool 320b, and L2 pool 360 may be implemented per thread identity or group of threads (e.g., wavefront identity).
FIG. 6 illustrates a method of handing memory synchronization events, according to an embodiment. In one example, system 100 and system 300 may be used to demonstrate method 600. It is to be appreciated that operations in method 600 may be performed in a different order than shown, and method 600 may not include all operations shown. For ease of discussion, and without limitation, method 600 will be described in terms of elements shown in FIG. 1 and FIG. 3.
The top portion of FIG. 6 includes an execution order of two threads, one from compute unit CU 310a and another from CU 310b, communicating a value in a simple system that contains one level of cache including wL1 320a and wL1 320b. The lower portion of FIG. 6 illustrates method 600.
Method 600 begins at step 601 when CU 310a issues a store event, ST X (1), and writes data, 1, to a cache block in a cache line of wL1 320a, associated with address X in main memory 150. In addition, a store entry is added to L1 pool 350a that can include but is not limited to the address, X, associated with the data and a thread identity. If prior store entries are present, the new store entry is added to the group of prior store entries and no particular order is maintained. However, if a release marker is present, the new store entry would be ordered to follow the most-recent release marker. If prior store entries are present after the most-recent release marker, the new store entry would join that group and no particular order is maintained among the prior store entries.
At step 602, CU 310a issues a StRel synchronization event that triggers pool evictions through the memory hierarchy to main memory 150. A release marker (Rel) entry is added to L1 pool 350a, and is ordered to follow any prior store entries in L1 pool 350a, to be evicted after the prior write entries in L1 pool 350a are evicted.
At step 603, L1 pool 350a begins evicting prior write entries ordered before the release marker (Rel). The entry associated with address X is evicted from L1 pool 350a, and the corresponding data in the cache in wL1 320a associated with address X is evicted to main memory 150.
At step 604, the prior write entries have been evicted from L1 pool 350a, the release marker (Rel) is evicted from L1 pool 350a and an acknowledgement is sent to CU 310a to signal that the release event portion of the StRel is complete.
At step 605, CU 310a issues the store event portion of the StRel synchronization event and writes data, 2, to a cache in wL1 320a associated with address A. In addition, a L1 pool 350a store entry is added that may include but is not limited to the address, A, associated with the cached data, and a thread identity. In an embodiment, an entry of the store event portion of a StRel to L1 pool 350a will trigger L1 pool 350a evictions.
At step 606, the prior write associated with address A is eventually evicted from L1 pool 350a (e.g., if the number of pool entries exceed a settable maximum value (not shown) or another release synchronization event occurs (not shown)). When the entry associated with address A is evicted from L1 pool 350a, the data associated with address A in wL1 320a is evicted to main memory 150 and signals completion of the release event portion of the StRel synchronization event to other threads in the system. The data at address A in main memory 150 is now visible to all threads in the system.
At step 607, CU 310b issues a load acquire LdAcq synchronization event to complete the synchronization. Method 600 searches wL1 320b, to read the data at address A, and when the address A is not found (a miss), method 600 searches main memory 150. When the address A and corresponding data, 2, are found and read from main memory 150 (a hit), the data is copied (i.e., loaded) to wL1 320b and is transmitted to (i.e., read by) CU 310b. 
At step 608, CU 310b issues a load event and searches wL1 320b, to read the data at address X, and when the address X is not found (a miss), method 600 searches main memory 150. When the address X and corresponding data, 1, are found and read from main memory 150 (a hit), the data is copied to wL1 320b and is read by CU 310b. 
In an embodiment, a pool can be implemented with a synchronization First In First Out (S-FIFO) that maintains complete order for prior writes as well as a release synchronization event. For example, at step 601, when a store event occurs, an entry would be made to the tail of an S-FIFO that can include but is not limited to the address, X, associated with the data and a thread identity. If prior writes are present, the new L1 pool 350a store entry would be added to the tail of the queue and complete order is maintained among the prior writes as well as the release synchronization events.
When the S-FIFO is filled, method 600 would begin to dequeue the S-FIFO. The dequeuing is similar to a pool component exceeding a settable maximum value. The entry at the top of the S-FIFO and the corresponding cache in the wL1 320a would be evicted to the corresponding next-level S-FIFO and next-level cache, e.g. wL2 340 if present. If the next-level cache is not present, the entry at the top of the S-FIFO is removed (e.g., popped) and the corresponding data in wL1 320a is written to main memory 150.
Logically there can be a S-FIFO per thread, but physically the S-FIFO can be implemented as a single FIFO, or as many FIFOs that are partitioned based on thread identity or a group of thread identities. Thus the physical implementation can balance space versus performance concerns. In addition, it is submitted that it is within the knowledge of one skilled in the art to understand that the S-FIFO can also be implemented in an architecture that includes a read-write cache rather than separate read and write caches.
FIG. 7 illustrates a method of evicting entries, according to an embodiment. In one example, system 100 and system 300 may be used to demonstrate method 700. It is to be appreciated that operations in method 700 may be performed in a different order than shown, and method 700 may not include all operations shown. For ease of discussion, and without limitation, method 700 will be described in terms of elements shown in FIG. 1 and FIG. 3.
Method 700 depicts the flow of operations when evictions from a queue such as a First In First Out (FIFO) instead of a pool occur. Evictions can occur, for example, when the number of entries in the FIFO exceeds the size of the FIFO and the entry at the head of the FIFO is popped off the FIFO, or when a release marker is added to the tail of the FIFO and triggers prior write evictions. Method 700 includes operations at a L1 FIFO and L2 FIFO (not shown), for example.
Method 700 begins at step 710 and proceeds to step 715.
At step 715, method 700 proceeds to step 720 to depict L1 FIFO eviction operations.
At step 720, method 700 determines whether L1 FIFO evicts a store entry or a release marker entry.
When a release marker is present in L1 FIFO and no prior writes exist ahead of the release marker entry, method 700 evicts a release marker entry and proceeds to step 725.
At step 725, the release marker is evicted from the head of L1 FIFO to the tail of L2 FIFO. The addition of the release marker triggers evictions of any prior store entries from L2 FIFO until the release marker itself is evicted from the head of L2 FIFO. When a L2 cache 340 (and hence L2 FIFO) is not present, the release marker is evicted from L1 FIFO, and an acknowledgement is sent to the originating thread that the release is complete.
Method 700 proceeds to step 745.
At step 720, if a release marker is present in L1 FIFO, the prior store entries in L1 FIFO ahead of the release marker are evicted in turn, to a L2 FIFO, and corresponding data in wL1 320a are correspondingly evicted to wL2 340. The prior store entries are evicted in the order of placement in L1 FIFO. Thus, the written data is guaranteed to be at the next level of the hierarchy by the time the release marker is evicted.
At step 720, if L1 FIFO evicts a store entry, method 700 proceeds to step 730.
At step 730, method 700 determines if the corresponding data exists in the wL1 320a. When the corresponding data does not exist, method 700 proceeds to step 735. At step 735, a cache replacement policy as is well known in the art, may be enforced and previously evicted the data from wL1 320a; the store entry at the head of L1 FIFO is evicted to the tail of L2 FIFO. Thus, embodiments support early evictions from the memory hierarchy.
Method 700 proceeds to step 745.
At step 730, if the corresponding data does exist in the wL1 320a, method 700 proceeds to step 740.
At step 740, the store entry at the head of L1 FIFO is evicted to the tail of L2 FIFO. In addition, the corresponding data in wL1 320a is evicted to wL2 340.
When a L2 cache hierarchy is not present (not shown), embodiments include the following: evicting the prior store entry from the head of L1 FIFO; evicting data, when present, from the wL1 320a associated with the evicted prior store entry to main memory; when the evicted prior store entry is associated with a StRel release synchronization event, signaling completion of release to the originating.
When a L2 cache hierarchy is present and the L2 cache hierarchy is an ordering point (not shown), embodiments further include the following: evicting the prior store entry from L1 FIFO; evicting data, when present, from the wL1 320a associated with the evicted prior store entry to the ordering point; when the evicted prior store entry is associated with a StRel release synchronization event, signaling completion of release to the originating thread. Thus, a StRel can complete at an ordering point other than main memory, and local synchronization is possible (e.g., receipt of a LdAcq can complete at wL2 340 without having to access main memory 150). Note that main memory can also be an ordering point and would be a global ordering point.
Method 700 proceeds to step 745.
At step 715, method 700 proceeds to step 745 to depict L2 FIFO eviction operations.
At step 745, method 700 determines whether L2 FIFO evicts a store entry or a release marker entry. Evictions may occur when a release marker entry is added to the tail of L2 FIFO that triggers evictions, or when the number of L2 FIFO entries exceeds a configurable threshold, for example. If L2 FIFO determines to evict a release marker entry, method 700 proceeds to step 750.
At step 750, the release marker is evicted from L2 FIFO. In addition, method 700 transmits an acknowledgment to the originating thread or original requester, CU 310a, that the release event is complete. The release completion provides assurance that safe forward progress is possible beyond the release synchronization event.
Note that for a StRel release synchronization event, CU 310a does not need to wait for the acknowledgement, but rather CU 310a can continue processing other memory events until executing the next LdAcq. But, for barrier and fence release synchronization events, CU 310a waits until a corresponding acknowledgement is received. Further, additional embodiments enable unsynchronized stores, if allowed by the memory model. These unsynchronized stores would not generate a store entry in L1 FIFO, rather, corresponding data could be written to wL1 320a. Thus, unsynchronized stores would not load pool components with unnecessary operations.
The method proceeds to step 765.
At step 745, if L2 FIFO determines to evict a store entry, method 700 proceeds to step 755.
At step 755, method 700 determines if the corresponding data exists in wL2 340. If the corresponding data does not exist, (e.g., due to a cache replacement policy enforcement) the store entry is evicted from the head of L2 FIFO and method 700 proceeds to step 765.
At step 755, when the corresponding data does exist, method 700 proceeds to step 760.
At step 760, the store entry is evicted from the head of L2 FIFO. In addition, the corresponding data in wL2 340 is evicted to main memory 150. Further, if the data was from a store event portion of a StRel, method 700 signals completion of release to the originating thread.
Embodiments invalidate the data in rL1 caches 370a and 370b associated with the corresponding address. The invalidations may be completed by broadcasting invalidation messages to the L1 read-only caches, rL1 cache 370a and rL1 370b, to ensure release consistency. The invalidations are not critical to performance as the invalidations simply delay release synchronization completions and are bound based on the number of entries in L2 FIFO when a release synchronization event occurs. Note that write evictions and load requests do not stall waiting for invalidations. In addition, the data in rL1 370a and rL1 370b can be invalidated with a flash clear, e.g., when a LdAcq is received, all blocks in the cache are invalidated. The flash clear does not need to be associated with the corresponding address.
Method 700 proceeds to step 765.
Logically, L1 FIFO and L2 FIFO may be implemented per thread identity or group of threads (e.g., wavefront identity).
In another embodiment, a pool of entries can be implemented with a Bloom-filter with a set of entries. A Bloom filter is an inexact representation of a set of elements. Bloom filters are implemented with an array of bits, and that array is indexed through two or more hash functions. To insert an element in the Bloom filter, the element is hashed and corresponding bits are set. To test membership, the element is hashed and corresponding bits are checked. If all bits are set (e.g., to “1”), the element may be in the set. If any one of the bits is cleared (e.g., to “0”), the element is not in the set. Unlike a mathematical set, Bloom filters have no remove function (though a variant called a counting bloom filter does). A signature is a representation of a set of elements. The pool can be implemented with a Bloom filter, an exact list (and/or array), or a FIFO, for example.
In summary, a prior store event is guaranteed to be ordered in the memory hierarchy whenever the store event has been evicted from a pool, dequeued from a FIFO, or tested for membership in a set using a Bloom-filter.
Various aspects of the disclosure can be implemented by software, firmware, hardware, or a combination thereof. FIG. 8 illustrates an example computer system 800 in which some embodiments, or portions thereof, can be implemented as computer-readable code. For example, the methods 400-700, of FIGS. 4 through 7 can be implemented in system 800. Various embodiments are described in terms of the example computer system 800. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the embodiments using other computer systems and/or computer architectures.
Computer system 800 includes one or more processors, such as processor 804. Processor 804 can be a special purpose or a general purpose processor. Examples of processor 804 are CPU 110 and GPU 130 of FIG. 1, or a GPGPU, or APU as described earlier. Processor 804 is connected to a communication infrastructure 806 (for example, a bus or network) such as bus 140 of FIG. 1.
Computer system 800 also includes a main memory 808, such as random access memory (RAM) such as main memory 150 of FIG. 1, and may also include a secondary memory 810. Secondary memory 810 may include, for example, a hard disk drive 812, a removable storage drive 814, and/or a memory stick. Removable storage drive 814 may comprise a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. The removable storage drive 814 reads from and/or writes to a removable storage unit 818 in a well-known manner. Removable storage unit 818 may comprise a floppy disk, magnetic tape, optical disk, etc. that is read by and written to by removable storage drive 814. As will be appreciated by persons skilled in the relevant art(s), removable storage unit 818 includes a computer usable storage medium having stored therein computer software and/or data.
In alternative implementations, secondary memory 810 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 800. Such means may include, for example, a removable storage unit 822 and an interface 820. Examples of such means may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 822 and interfaces 820 that allow software and data to be transferred from the removable storage unit 822 to computer system 800.
Computer system 800 may also include a communications interface 824. Communications interface 824 allows software and data to be transferred between computer system 800 and external devices. Communications interface 824 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface 824 are in the form of signals that may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 824. These signals are provided to communications interface 824 via a communications path 826. Communications path 826 carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link or other communications channels.
In this document, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage unit 818, removable storage unit 822, and a hard disk installed in hard disk drive 812. Signals carried over communications path 826 can also embody the logic described herein. Computer program medium and computer usable medium can also refer to memories, such as main memory 808 and secondary memory 810, which can be memory semiconductors (e.g. DRAMs, etc.). These computer program products are means for providing software to computer system 800.
Computer programs (also called computer control logic) are stored in main memory 808 and/or secondary memory 810. Computer programs may also be received via communications interface 824. Such computer programs, when executed, enable computer system 800 to implement the embodiments as discussed herein. In particular, the computer programs, when executed, enable processor 804 to implement the disclosed processes, such as the steps in the methods 400-700 of FIGS. 4-7 as discussed above. Accordingly, such computer programs represent controllers of the computer system 800. Where the embodiments are implemented using software, the software may be stored in a computer program product and loaded into computer system 800 using removable storage drive 814, interface 820, hard drive 812 or communications interface 827. This can be accomplished, for example, through the use of general-programming languages (such as C or C++). The computer program code can be disposed in any known computer-readable medium including semiconductor, magnetic disk, or optical disk (such as, CD-ROM, DVD-ROM). As such, the code can be transmitted over communication networks including the Internet and internets. It is understood that the functions accomplished and/or structure provided by the systems and techniques described above can be represented in a core (such as a processing-unit core) that is embodied in program code and may be transformed to hardware as part of the production of integrated circuits. This can be accomplished, for example, through the use of hardware-description languages (HDL) including Verilog HDL, VHDL, Altera HDL (AHDL) and so on, or other available programming and/or schematic-capture tools (such as, circuit-capture tools).
Embodiments are also directed to computer program products comprising software stored on any computer useable medium. Such software, when executed in one or more data processing device, causes a data processing device(s) to operate as described herein. Embodiments employ any computer useable or readable medium, known now or in the future. Examples of computer useable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage device, etc.), and communication mediums (e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.).
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments as contemplated by the inventor(s), and thus, are not intended to limit the disclosure and the appended claims in any way.
The disclosure has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

## Claims

1. A method comprising:
receiving a memory event;
when the memory event is a store event, the method further comprises:
writing a first data to a write-only, level n cache, where n is an integer representing a level of cache hierarchy;
writing, to a level n pool, a store entry that includes an address of the first data written in the level n cache, wherein the level n pool stores store entry, a plurality of a prior received store entries, and a release marker entry, and the stored release marker entry maintains a partial release order among the store entry and the plurality of prior received store entries by dividing them into groups within the pool such that all store entries positioned before the release marker entry are to be released before all store entries positioned after the release marker entry, wherein no particular order of store entries within the particular groups exists; and
when a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker; and

when the memory event is a load event, the method further comprises:
searching a read-only, level n cache for a second data;
determining whether the second data is present in a corresponding write-only, level n cache;
when the second data is found in the read-only, level n cache and the second data is not found in the corresponding write-only, level n cache, reading the second data from the read-only, level n cache; and
when the second data is found in the corresponding write-only, level n cache, reading the second data from the write-only, level n cache.

2. The method of claim 1, further comprising:
when a partial amount of the second data is found in the corresponding write-only, level n cache, the method further comprises:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading a remaining amount of the second data from main memory; and

when a level (n+1) hierarchy is present:
writing the partial amount of the second data from the write-only, level n cache to the write-only, level (n+1) cache; and
sending a read request corresponding to the load event, to the level (n+1) hierarchy.

3. The method of claim 2, further comprising:
when the partial amount of the second data is found in the corresponding write-only, level n cache, the method further comprises:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading the second data associated with the address from main memory.

4. The method of claim 1, wherein determining whether the second data is present, comprises:
searching a corresponding dirty-read buffer (DRB) level n, for the second data.

5. The method of claim 4, further comprising:
when the second data is found in the read-only, level n cache, and the second data is not found in the corresponding DRB level n, reading the second data from the read-only, level n cache; and
when the second data is found in the corresponding DRB level n, reading the second data from the DRB level n.

6. The method of claim 4, further comprising:
when a partial amount of the second data is found in the corresponding DRB level n, the method further comprises:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading a remaining amount of the second data from main memory; and

when a level (n+1) hierarchy is present:
writing the partial amount of the second data from the write-only, level-n cache to the write-only, level (n+1) cache; and
sending a read request corresponding to the load event, to the level (n+1) hierarchy.

7. A computer-readable storage device having stored thereon instructions, execution of which, by a processing unit, cause the processing unit to perform operations comprising:
receiving a memory event;
when the memory event is a store event, the operations further comprise:
writing a first data to a write-only, level n cache, where n is an integer representing a level of cache hierarchy;
writing, to a level n pool, a store entry that includes an address of the first data written in the level n cache, wherein the level n pool stores store entry, a plurality of a prior received store entries, and a release marker entry, and the stored release marker entry maintains a partial release order among the store entry and the plurality of prior received store entries by dividing them into groups within the pool such that all store entries positioned before the release marker entry are to be released before all store entries positioned after the release marker entry, wherein no particular order of store entries within the particular groups exists; and when a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker; and

when the memory event is a load event, the operations further comprise:
searching a read-only, level n cache for a second data;
determining whether the second data is present in a corresponding write-only, level n cache;
when the second data is found in the read-only, level n cache and the second data is not found in the corresponding write-only, level n cache, reading the second data from the read-only, level n cache; and
when the second data is found in the corresponding write-only, level n cache, reading the second data from the write-only, level n cache.

8. The computer-readable storage device of claim 7, wherein the operations further comprise:
when a partial amount of the second data is found in the corresponding write-only, level n cache, the operations further comprise:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading a remaining amount of the second data from main memory; and

when a level (n+1) hierarchy is present:
writing the partial amount of the second data from the write-only, level n cache to the write-only, level (n+1) cache; and
sending a read request corresponding to the load event, to the level (n+1) hierarchy.

9. The computer-readable storage device of claim 8, wherein the operations further comprise:
when the partial amount of the second data is found in the corresponding write-only, level n cache, the operations further comprise:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading the second data associated with the address from main memory.

10. The computer-readable storage device of claim 7, wherein determining whether the second data is present further comprises:
searching a corresponding dirty-read buffer (DRB) level n, for the second data.

11. The computer-readable storage device of claim 10, wherein the operations further comprise:
when the second data is found in the read-only, level n cache, and the second data is not found in the corresponding DRB level n, reading the second data from the read-only, level n cache; and
when the second data is found in the corresponding DRB level n, reading the second data from the DRB level n.

12. The computer-readable storage device of claim 10, wherein the operations further comprise:
when a partial amount of the second data is found in the corresponding DRB level n, the operations further comprise:
when a level (n+1) cache is not present:
writing the partial amount of the second data from the write-only, level n cache to main memory; and
reading a remaining amount of the second data from main memory; and

when a level (n+1) hierarchy is present:
writing the partial amount of the second data from the write-only, level-n cache to the write-only, level (n+1) cache; and
sending a read request corresponding to the load event, to the level (n+1) hierarchy.

13. A processing unit comprising one or more compute units configured to:
receive a memory event;
when the memory event is a store event, the one or more compute units are further configured to:
write a first data to a write-only, level n cache, where n is an integer representing a level of cache hierarchy;
writing, to a level n pool, a store entry that includes an address of the first data written in the level n cache, wherein the level n pool stores store entry, a plurality of a prior received store entries, and a release marker entry, and the stored release marker entry maintains a partial release order among the store entry and the plurality of prior received store entries by dividing them into groups within the pool such that all store entries positioned before the release marker entry are to be released before all store entries positioned after the release marker entry, wherein no particular order of store entries within the particular groups exists; and
when a release marker is present, order the store entry in the level n pool to follow a most-recent release marker; and

when the memory event is a load event, the one or more compute units are further configured to:
search a read-only, level n cache for a second data;
determine whether the second data is present in a corresponding write-only, level n cache;
when the second data is found in the read-only, level n cache and the second data is not found in the corresponding write-only, level n cache, read the second data from the read-only, level n cache; and
when the second data is found in the corresponding write-only, level n cache, read the second data from the write-only, level n cache.

14. The processing unit of claim 13, wherein the one or more compute units are further configured to:
when a partial amount of the second data is found in the corresponding write-only, level n cache, the one or more compute units are further configured to:
when a level (n+1) cache is not present:
write the partial amount of the second data from the write-only, level n cache to main memory;
read a remaining amount of the second data from main memory;

when a level (n+1) hierarchy is present:
write the partial amount of the second data from the write-only, level n cache to the write-only, level (n+1) cache; and

send a read request corresponding to the load event, to the level (n+1) hierarchy.

15. The processing unit of claim 14, wherein the one or more compute units are further configured to:
when the partial amount of the second data is found in the corresponding write-only, level n cache, the one or more compute units are further configured to:
when a level (n+1) cache is not present:
write the partial amount of the second data from the write-only, level n cache to main memory; and
read the second data associated with the address from main memory.

16. The processing unit of claim 13, wherein the determining when the second data is present, the one or more compute units are further configured to:
search a corresponding dirty-read buffer (DRB) level n, for the second data.

17. The processing unit of claim 16, wherein the one or more compute units are further configured to:
when the second data is found in the read-only, level n cache, and the second data is not found in the corresponding DRB level n, read the second data from the read-only, level n cache; and
when the second data is found in the corresponding DRB level n, read the second data from the DRB level n.