# Patent

## Title
Gate driver for isolated input switching device

## Abstract

A gate driver driving a switching device is disclosed. The gate driver includes a capacitor which is coupled to the input of the switching device. The gate drive power consumption is reduced by this additional capacitor.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a National Stage of International Application No. PCT/KR2014/001964, filed Mar. 10, 2014 and published as WO 2014/171633 A1 on Oct. 23, 2014, which claims the benefit of Korean Patent Application No. 10-2013-0043721, filed on Apr. 19, 2013, the entire disclosures of which are incorporated herein by reference for all purposes.
TECHNICAL FIELD
The present invention relates to a gate driver for switching device, and more particularly, to a gate driver for improving driving efficiency of a switching device.
BACKGROUND ART
FIG. 1 is a diagram illustrating an inductor-inductor-capacitor (LLC) resonant inverter circuit consisting of conventional MOSFET switches.
In the LLC resonant inverter circuit as shown in FIG. 1, MOSFET switch M1 and MOSFET switch M2 are alternately switched to supply energy to the load. In this case, if M1 and M2 are driven at a switching frequency which is higher than a resonant frequency that is determined by an inductor L1, a capacitor C1, and a magnetizing inductance, the switches can be turned ON when the drain-source voltage of either M1 or M2 is almost zero. Such an operation is referred to as a “zero-voltage switching (ZVS)”. By performing a ZVS operation, not only can switching loss of switches be minimized, but also electromagnetic interference can be reduced.
FIG. 2 is a circuit diagram of a synchronous buck converter of a prior art.
In the synchronous buck converter that is configured as shown in FIG. 2, when M1 is ON, energy is supplied to the load via L1. Then, when MI is OFF, the inductor current free-wheels through M2, and at this time, the drain-source voltage at both ends of M2 nears zero, thus satisfying the ZVS.
FIG. 3 is an equivalent circuit diagram in the case of the ZVS performed using a conventional gate driver.
FIG. 3 shows an equivalent circuit diagram when a switch that satisfies ZVS conditions is turned ON using a conventional gate driver 10. As the ZVS condition, the drain of M1 is at the same potential as the source. In FIG. 3, the drain of M1 is set to ground level. At this time, when M2 is turned ON, M1 is also ON, thereby completing the ZVS. For M1 to be ON, a gate-source parasitic capacitor Cgs and a gate-drain parasitic capacitor Cgd have to be charged above a threshold voltage which causes the MOSFET to be ON. The power Pdriving which is provided from a power supply VDD is obtained by Equation 1 below.




  
    
      
        
          
            
              Pdriving
              =
              
              ⁢
              
                Qg
                ·
                VDD
                ·
                f
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  (
                  
                    Cgs
                    +
                    Cgd
                  
                  )
                
                ·
                
                  VDD
                  2
                
                ·
                f
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




Since Qg, which denotes charge to be supplied, is (Cgs+Cgd)*VDD, Pdriving is proportional to the total parasitic capacitance (Cg=Cgs+Cgd) of the gate, as shown in Equation 1. It is also proportional to the square of driving voltage, as well as to a switching frequency. In the case where the driving frequency is low, although gate drive loss is usually negligible compared to conduction loss caused by ON resistance Rdson of the MOSFET, the gate drive loss increases with the rise of the frequency, which means no matter how much Rdosn of the switch is improved, it is not possible to implement a system that has a good efficiency.
Technical Problem
The objective of the present invention is to provide a gate driver which enables reduction in gate drive power consumption resulting from charging a gate during driving of a switching device.
Technical Solution
The present invention provides a gate driver for driving a switching device, the gate driver including a capacitor coupled to an input of the switching device.
The gate driver may be configured to turn ON the switching device by supplying charge through the capacitor, and to discharge the capacitor when turning off the switching device.
The gate driver may be configured to turn ON the switching device by supplying charge through the capacitor; to reserve charge stored in the capacitor when turning off the switching device; and to re-use the charge reserved in the capacitor when controlling the switching device to be turned ON again. The gate driver may be configured to allow the charge preserved in the capacitor to be shared with a parasitic capacitor when the gate driver controls the switching device to be turned ON again. The parasitic capacitor of the switching device may include a gate-source parasitic capacitor and a gate-drain parasitic capacitor of the switching device.
Advantageous Effects
According to the present invention, a gate driver, specifically, a capacitor coupled gate driver (CCGD) and a charge recycle capacitor coupled gate driver (CRCCGD) are both based on a capacitor coupled driver, and, while somewhat increasing the conduction loss, the two still increase the overall efficiency by reducing the gate drive loss at a rate greater than the increase in conduction loss.
According to the present invention, particularly in an application that performs zero-voltage switching and drives, at high speed, switching devices whose inputs are isolated, such as, MOSFET and GaN device, CCGD and CRCCGD with high frequency bring about an efficiency improvement effect in comparison to the existing method.



DESCRIPTION OF DRAWINGS
FIG. 1 is a diagram illustrating inductor-inductor-capacitor (LLC) resonant inverter circuit consisting of conventional MOSFET switches.
FIG. 2 is a circuit diagram of a synchronous buck converter of a prior art.
FIG. 3 is an equivalent circuit diagram in the case of the ZVS performed using a conventional gate driver.
FIG. 4 is a graph showing a gate driving voltage and ON resistance of MOSFET.
FIG. 5 is a graph showing the maximum efficiency point according to the size of MOSFET.
FIG. 6 is a circuit diagram of a gate driver according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram showing principles of operation of the gate driver circuit of FIG. 6.
FIG. 8 is a circuit diagram of a gate driver according to another exemplary embodiment of the present invention.
FIG. 9 is a diagram showing driving waveforms of each switch shown in FIG. 8.
FIG. 10 illustrates circuit diagrams for showing operation principles of the gate driver of FIG. 8.
FIG. 11 is a diagram for explaining the analysis of Power Save Factor (PSF) when the gate driver is driven as shown in FIG. 10.
FIG. 12 is a graph showing the magnitude of gate voltage according to the capacity of capacitor Cs.
FIG. 13 is a graph showing PSF comparison between CRCCGD and CCGD.
FIG. 14 is an active rectifier efficiency test circuit diagram.
FIG. 15 is a graph showing the efficiency of an active rectifier.



MODE FOR INVENTION
The above and further aspects of the present invention will be more clearly understood through the accompanying drawings, in which exemplary embodiments of the invention are shown. Hereinafter, the exemplary embodiments are provided to describe the invention in detail such that the invention can be embodied and fully understood by those skilled in the art.
FIG. 4 is a graph showing a gate driving voltage and ON resistance of MOSFET.
FIG. 4 is a graph showing ON resistances Rdson of MOSFET according to a gate driving voltage of a 20V lateral double diffused MOS (LDMOS). The X-axis represents a gate driving voltage [V] and the Y-axis represents ON voltage of MOSFET, i.e., Rdson [mOhm]. If the threshold voltage of the 20V LDMOS is set at about 0.8 V, and when the 20V LDMOS is driven above 2 V, a desired ON characteristic can be achieved. In addition, as a gate voltage is increased, Rdson decreases, but not drastically; and even when the voltage is increased, there is only a minimal amount of reduction. A ratio between the width and the length of the MOSFET gate in the graph is 6000*NR/1.3[um/um], wherein it can be seen that as MOSFET increases in size by raising NR, Rdson decreases. As Rdson decreases with the increase of the MOSFET size, conduction loss is also reduced, while the total gate capacitance Cg increases. Therefore, gate drive loss increases, resulting in what can be seen in FIG. 5. Hence, at a point at which two efficiencies meet, the maximum efficiency (i.e., the least loss) can be satisfied. Hereinafter, a switching mechanism that increases the efficiency by reducing gate drive loss will be described in detail.
FIG. 6 is a circuit diagram of a gate driver according to an exemplary embodiment of the present invention; and FIG. 7 is a diagram showing principles of operation of the gate driver circuit of FIG. 6.
FIG. 6 represents a capacitor coupled gate driver (CCGD) circuit. The CCGD circuit includes a capacitor Cs that is serially connected between an output terminal of a driver consisting of M2 and M3 and M1. The operation of the CCGD circuit is illustrated in FIG. 7. FIG. 7 (a) shows the operation at the time when M1 is turned ON; and FIG. 7 (b) shows the operation at the time when M2 is turned OFF. As shown in FIG. 7(a), when M2 is turned ON, a charge is supplied through Cs, Vg rises, and M1 is turned ON. When M1 is turned OFF, M3 and M4 both are simultaneously turned ON, Vg becomes zero Volts (Vg=0), and Cs is discharged. If Cs is not discharged, a charge cannot be delivered to M1 gate.
During such operations as above, voltage Vg varies depending on the capacity of Cs. Given that Cg=Cgs+Cgd and Cs is represented as Equation 2, the gate voltage Vg is determined as Equation 3.




  
    
      
        Cs
        =
        
          α
          ·
          Cg
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        Vg
        =
        
          
            α
            
              1
              +
              α
            
          
          ·
          VDD
        
      
    
    
      
        (
        3
        )
      
    
  




The total capacitance Ctotal that has to be charged in the power supply is the same as the capacity of serially connected Cs and Cg and is thus represented as Equation 4.




  
    
      
        Ctotal
        =
        
          
            α
            
              1
              +
              α
            
          
          ·
          Cg
        
      
    
    
      
        (
        4
        )
      
    
  




Hence, gate drive loss Pdrv,CCGD due to CCGD may be represented as Equation 5, using Equation 1 and Equation 4.




  
    
      
        
          
            
              
                P
                
                  drv
                  ,
                  CCGD
                
              
              =
              
              ⁢
              
                
                  α
                  
                    1
                    +
                    α
                  
                
                ·
                Cg
                ·
                
                  VDD
                  2
                
                ·
                f
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  PSF
                  CCGD
                
                ·
                Cg
                ·
                
                  VDD
                  2
                
                ·
                f
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Here, PSF stands for Power Save Factor, which indicates a reduction ratio of gate drive loss in comparison to the gate drive loss during the existing driver driving the switch.
As it can be seen from Equation 3, it is possible to control voltage Vg by adjusting the capacity of Cs. As Cs is lowered, voltage Vg falls, and thus conduction loss is increased. As it can be seen from Equation 5, gate drive loss is, however, reduced. As confirmed in FIG. 4, Rdson of MOSFET is not considerably improved when a gate voltage is 2.5 V or higher, and hence the reduction of gate drive loss can be larger, when compared to conduction loss caused by the addition of Cs. If Cs is set by specifying a to satisfy such conditions, the efficiency can be improved. In the case of α=1, given VDD=5 V, Vg becomes 2.5 V. At this time, Rdson increases by about 20% and PSF=1⁄2, and thus gate drive loss is reduced by 50%. Thus, 25% of efficiency improvement can be anticipated when the above mechanism is used.
FIG. 8 is a circuit diagram of a gate driver according to another exemplary embodiment of the present invention.
FIG. 8 illustrates an enhanced gate driver to improve gate drive loss further. In the gate driver of FIG. 6, when M1 is OFF, Cs charge is discharged, and hence efficiency improvement is not significant. On the other hand, in the gate driver circuit of FIG. 8, the charge stored in Cs is used to charge Cg when M1 which was turned OFF is turned ON again, and hence gate drive loss can be further improved. The gate driver circuit of FIG. 8 is called Charge Recycle Capacitor Coupled Gate Driver (CRCCGD) since it recycles the Cs charge. For reference, FIG. 9 shows driving waveforms of each switch shown in FIG. 8.
FIG. 10 illustrates circuit diagrams for showing operation principles of the gate driver of FIG. 8.
As shown in FIG. 10(a), in the same manner as CCGD, Cg, to which Cs is serially connected, is charged during the phase in which M1 is fully turned ON. FIG. 10(b) shows a state in which M1 is turned OFF. M3 is turned ON and, in turn, Cg is discharged so that M1 is turned OFF, while a discharge path for Cs is not formed and the charge that was stored in Cs in the state as shown in FIG. 10(a) is hence preserved. FIG. 10(c) shows the operation of the gate driver when controlling M1 to be turned ON again. Before the gate driver operates as shown in FIG. 10(a), M4 and M5 are turned ON and the charge stored in Cs is shared with Cg. Accordingly, Vg voltage is charged between the maximum voltage and the minimum voltage, as shown in FIG. 9. Thereafter, as shown in FIG. 10(d), M2 is turned ON again to further charge Cg, and Cs is re-charged by the amount of charge shared with Cg.
The magnitude of Vg voltage and PSF when the gate driver is driven as described above may be analyzed as below. FIG. 11(a) illustrates an equivalent circuit in a state in which Cs and Cg are fully charged as gate driving has been completed. It is assumed that Cs is a times as large as Cg and a voltage charged in Cs at the time of completion of full charge as shown in FIG. 11(a) is ΔV. In FIG. 11(b), SW1 is turned ON so that the charge in Cs is re-used to charge Cg. Equation 6 below is satisfied according to the charge conservation theory.

α·Cg·ΔV=(1+α)·Cg·Vx  (6)

Vx voltage of Equation 6 is obtained by Equation 7.




  
    
      
        Vx
        =
        
          
            
              α
              
                1
                +
                α
              
            
            ·
            Δ
          
          ⁢
          
            
          
          ⁢
          V
        
      
    
    
      
        (
        7
        )
      
    
  




FIG. 11(c) is an equivalent circuit when M1 is fully turned ON. Even though charge is supplied from VDD to Cs and Cg, since Cs and Cg has been charged to Vx by the charge recycled as shown in FIG. 11(b), the equivalent circuit, as shown in FIG. 11(c), is obtained. Gate voltage Vg of this equivalent circuit is obtained by Equation 8.




  
    
      
        Vg
        =
        
          
            
              α
              
                1
                +
                α
              
            
            ·
            
              (
              
                VDD
                -
                
                  2
                  ⁢
                  Vx
                
              
              )
            
          
          +
          Vx
        
      
    
    
      
        (
        8
        )
      
    
  




The voltage of Cs is represented as Equation 9.




  
    
      
        Vcs
        =
        
          
            
              1
              
                1
                +
                α
              
            
            ·
            
              (
              
                VDD
                -
                
                  2
                  ⁢
                  Vx
                
              
              )
            
          
          +
          Vx
        
      
    
    
      
        (
        9
        )
      
    
  




Vcs after completion of operation as shown in FIG. 11(c) has to be equal to ΔV of FIG. 11(a). ΔV obtained from Equation 7 and Equation 9 is represented by Equation 10.




  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          V
        
        =
        
          
            
              1
              +
              α
            
            
              1
              +
              
                3
                ⁢
                α
              
            
          
          ·
          VDD
        
      
    
    
      
        (
        10
        )
      
    
  




Voltage Vg obtained from Equation 7, Equation 8, and Equation 10 is represented by Equation 11.




  
    
      
        Vg
        =
        
          
            
              2
              ⁢
              α
            
            
              1
              +
              
                3
                ⁢
                α
              
            
          
          ·
          VDD
        
      
    
    
      
        (
        11
        )
      
    
  




In the above switching operation, the operation of supplying the charge from VDD to Cs and Cg corresponds to the operation as shown in FIG. 11(c). The amount of charge supplied from VDD is the product of the capacitor serially connected to Cs and Cg and (VDD−2Vx), and is obtained by Equation 12.




  
    
      
        
          
            
              Qg
              =
              
              ⁢
              
                
                  α
                  
                    1
                    +
                    α
                  
                
                ·
                Cg
                ·
                
                  (
                  
                    VDD
                    -
                    
                      2
                      ⁢
                      Vx
                    
                  
                  )
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  α
                  
                    1
                    +
                    
                      3
                      ⁢
                      α
                    
                  
                
                ·
                Cg
                ·
                VDD
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




The power supplied from VDD is represented as Equation 13.




  
    
      
        
          
            
              
                P
                
                  drv
                  ,
                  CRCCGD
                
              
              =
              
              ⁢
              
                Qg
                ·
                VDD
                ·
                f
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  α
                  
                    1
                    +
                    
                      3
                      ⁢
                      α
                    
                  
                
                ·
                Cg
                ·
                
                  VDD
                  2
                
                ·
                f
              
            
          
        
        
          
            
              
                =
                
                ⁢
                
                  
                    PSF
                    
                      CRCCGD
                      ⁢
                      
                        
                      
                    
                  
                  ·
                  Cg
                  ·
                  
                    VDD
                    2
                  
                  ·
                  f
                
              
              ,
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




where PSFCRCCGD, denoting PSF of CRCCGD, is represented as α/(1+3α).
FIG. 12 is a graph showing the magnitude of gate voltage according to the capacity of capacitor Cs.
VDD is 5 V. In the case of CCGD, as α increases, the gate voltage becomes closer to VDD, and in the case of CRCCGD, 2⁄3*VDD is the maximum value. Where α=1, CCGD and CRCCGD both has the same Vg voltage, VDD/2.
FIG. 13 is a graph showing PSF comparison between CRCCGD and CCGD.
FIG. 13 shows variation in PSF according to the capacity of Cs. In the case of CCGD, as α increases, PSF becomes closer to 1, and consequently the power saving effect disappears. However, in the case of CRCCGD, since PSF is up to 1⁄3, an effect of an improvement of more than 67% is brought about even when any Cs is used. In the case of α=1, the two types have the same gate voltage, while PSF of CCGD is 1⁄2 and that of CRCCGD is 1⁄4. In other words, CRCCGD shows an improvement of 50% in comparison with the CCGD and an improvement of 75% in comparison with the existing gate driver. In this case, the gate voltage is halved, and thus conduction loss is increased. The conduction loss at the time of driving at 2.5 V is increased by about 20%, while gate drive loss due to CRCCGD is reduced by 75%, and hence the overall efficiency is increased.
CCGD and CRCCGD are driven using Cs capacitor that is coupled to MOSFET to be driven, and hence if the Cs capacitor is fully charged, it is not possible to charge MOSFET gate any longer. If a drain voltage decreases at the moment of M1 being turned ON, the current flowing through Cgd increases in proportion to the variation of the drain voltage according to the Miller effect, thereby bringing about the effect of amplifying Cgd. Accordingly, the effect of increase in Cg is achieved, which is similar to the effect of decrease in a. Therefore, the gate voltage cannot rise enough and hence it is difficult to drive MOSFET. For this reason, CCGD and CRCCGD are suitable to a ZVS application circuit which is turned ON when the drain potential of MOSFET is equal to the source potential, and in which the drain potential and the source potential are fixed.
FIG. 14 is an active rectifier efficiency test circuit diagram; and FIG. 15 is a graph showing the efficiency of an active rectifier.
In order to verify the efficiency improvement effect caused by CRCCGD, simulation of the efficiency of a magnetic resonance power transfer system in which the active rectifier is implemented, as shown in FIG. 14, was conducted. The active rectifier 100 was implemented using an active diode 200 consisting of MOSFTET and CRCCGD. The active diode was turned ON when voltages of both ends A and K were greater than 0, and since at the moment of being turned ON, ZVS requirements were satisfied, CRCCGD become usable. It is assumed that at the output, DC-DC converter 300 with efficiency of 90% supplies 5 W to the load. The power supplied from the active rectifier 100 thus becomes 5.5 W. The conditions for the simulation to compare the effects between the existing gate driver and CRCCGD are as follow:
(1) MOSFET: breakdown voltage of 20 V, W/L=6000*NR/1.3 [um/um]
(2) Input power source frequency: 6.78 MHz

    
    
        →Hence, switching frequency of active rectifier becomes 6.78 MHz.
    
    


(3) NR: 8 ̃22
(4) Rectifier output voltage (Vrect):  ̃8 V
(5) α of CRCCGD: α=1
(6) VDD of CRCCGD: 5 V
(7) Efficiency of converter connected to active rectifier: 90%
(8) Power consumption of final load: 5 W
The gate voltage at the time when MOSFET of an active diode is driven using a general gate driver becomes 5V. On the other hand, in the case of CRCCGD, since α=1, the gate driving voltage becomes 2.5 V by Equation 11. Hence, CRCCGD is inferior in terms of conduction loss, when compared to the implementation using the general gate driver. However, the switching frequency is 6.78 MHZ, which is very high, and thereby the gate drive loss becomes significantly high. The reduction in gate drive loss by CRCCGD may enhance the overall efficiency, thereby making it possible to achieve the result as shown in FIG. 14. It can be seen from the results of the simulation that, in all conditions, the efficiency of the circuit using CRCCGD is higher than the efficiency by the existing driver.
CCGD and CRCCGD both are based on a capacitor coupled driver, and, while somewhat increasing the conduction loss, the two still increase the overall efficiency by reducing the gate drive loss at a rate greater than the increase in conduction loss. Particularly, in the application that performs zero-voltage switching and drives, at high speed, switching devices whose inputs are isolated, such as, MOSFET and GaN device, CCGD and CRCCGD bring about the efficiency improvement effect in comparison to the existing methods.
It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

## Claims

1. A gate driver for driving a switching device, the gate driver comprising a capacitor coupled to an input of the switching device, and being configured to turn ON the switching device by supplying charge through the capacitor; to reserve charge charged in the capacitor when turning off the switching device; and to re-use the charge reserved in the capacitor when controlling the switching device to be turned ON again.

2. The gate driver of claim 1 being configured to allow the charge preserved in the capacitor to be shared with a parasitic capacitor when the gate driver controls the switching device to be turned ON again.

3. The gate driver of claim 2, wherein the parasitic capacitor of the switching device includes a gate-source parasitic capacitor and a gate-drain parasitic capacitor of the switching device.

4. The gate driver of claim 1, wherein the switching device performs zero-voltage switching and has an isolated input.

5. The gate driver of claim 1, wherein a capacity of the capacitor is set such that a rate of reduction in gate drive loss is higher than a rate of increase in conduction loss of the switching device.