# Patent

## Title
Circuit for eliminating pop sounds at power on and off by a moderate waveform

## Abstract

A circuit for eliminating pop sounds at power on and off by a moderate waveform, which includes a switch, a feedback network, an operational amplifier and an output network. When power-on, a first input terminal of the switch is connected to a low voltage, and an output terminal of the output network provides an operating DC bias which is gradually increased. When power-off, the first input terminal of the switch is connected to a reference voltage, and the output terminal of the output network provides an operating DC bias which is gradually reduced.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for eliminating noises at power on and off and, more particularly, to a circuit for eliminating pop sounds at power on and off by a moderate waveform.
2. Description of Related Art
Upon the rapid advance of electronic technology, multimedia applications are increasingly complicated. In addition to the requirement of image quality, the sound quality is required higher and higher. FIG. 1 is a schematic diagram of a typical sound signal. As shown in FIG. 1, due to the sampling, the range of the sound signal is from positive voltage to negative voltage. However, an operating voltage for a typical integrated circuit (IC) ranges from zero to VDD volts, and the sound signal is biased to VDD/2.
When the sound signal is biased, it directly adds a DC bias VDD/2 and the sound signal, which can cause a pop noise sounding “Bo” at power on due to the discontinuous DC operating voltage. Likewise, the DC operating voltage for the sound signal at power off is rapidly reduced from VDD/2 volts to zero, and the pop noise “Bo” is present. As shown in FIGS. 2A and 2B, when an output voltage of a digital to analog converter (DAC) is changed from zero to VDD/2 volts, the DAC adds the internal sound signal to the DC operating voltage. Such a way gradually increases the DC operating voltage from zero to VDD/2 volts, so the pop noise is not clearly present except for the positions B and C where the DC operating voltage is discontinuous. In addition, the DC operating voltage is increased exponentially, not linearly, when the DAC adjusts the DC operating voltage from zero to VDD/2 volts. This may cause slight noises. Further, the entire system response speed is typically limited by the DAC, and the system cannot be powered on or off rapidly. For rapid power-on or -off, it requires a DAC with the fast response speed, which relatively increases the system cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit for eliminating pop sounds at power on and off by a moderate waveform, which can reduce the pop sounds and slight noises produced at power on or off.
Another object of the present invention is to provide a circuit for eliminating pop sounds at power on and off by a moderate waveform, which can increase the system response speed to thereby save the cost.
In accordance with one aspect of the present invention, there is provided a circuit for eliminating pop sounds at power on and off by a moderate waveform. The circuit includes a switch, a feedback network, an operational amplifier and an output network. The switch has a first input terminal connected to a low voltage and a second input terminal connected to a reference voltage for switching at power on or off. The feedback network is connected to the switch in order to provide a feedback current, and has a first resistor and a second resistor. The second resistor has one terminal connected to the switch and the other terminal connected to one terminal of the first resistor. The operational amplifier has a negative input terminal connected to the first resistor and the second resistor and an output terminal connected to the other terminal of the first resistor. The output network has an output terminal, a third resistor, a fourth resistor and a capacitor. The third resistor has one terminal connected to the output terminal of the operational amplifier and the other terminal connected to the output terminal of the output network, one terminal of the fourth resistor, one terminal of the capacitor and a positive input terminal of the operational amplifier. The fourth resistor has the other terminal connected to the low voltage. The capacitor has the other terminal connected to the low voltage. When the switch is connected to the low voltage, the output terminal of the output network provides an operating DC bias, which is gradually increased, to the circuit.
In accordance with another aspect of the present invention, there is provided a circuit for eliminating pop sounds at power on and off by a moderate waveform. The circuit includes a switch, a feedback network, an operational amplifier and an output network. The switch has a first input terminal connected to a low voltage and a second input terminal connected to a reference voltage for switching at power on or off. The feedback network is connected to the switch in order to provide a feedback current, and has a first resistor, a second resistor and a fifth resistor. The second resistor has a first terminal connected to the switch and a second terminal connected to first terminals of the first resistor and the fifth resistor. The fifth resistor has a second terminal connected to the low voltage. The operational amplifier has a negative input terminal connected to the first terminal of the first resistor, the second terminal of the second resistor and the first terminal of the fifth resistor, and an output terminal connected to a second terminal of the first resistor. The output network has an output terminal and is comprised of a third resistor, a fourth resistor and a capacitor. The third resistor has a first terminal connected to the output terminal of the operational amplifier and a second terminal connected to the output terminal, a first terminal of the fourth resistor, a first terminal of the capacitor and a positive input terminal of the operational amplifier. The fourth resistor has a second terminal connected to the low voltage. The capacitor has a second terminal connected to the low voltage. When the switch is connected to the low voltage, the output terminal of the output network provides an operating DC bias, which is gradually increased, to the circuit.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic graph of a typical sound signal;
FIGS. 2A and 2B are a schematic graphs of a sound signal typically biased by a DC operation bias;
FIG. 3 is a diagram of a circuit for eliminating pop sounds at power on and off in accordance with the invention;
FIG. 4 is a diagram of an output voltage of the circuit of FIG. 3 in accordance with the invention;
FIG. 5 is a schematic graph of an operating bias computed at power on in accordance with the invention;
FIG. 6 is a schematic graph of an operating bias computed at power off in accordance with the invention; and
FIG. 7 is a circuit diagram of another embodiment of the invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 3 is a diagram of a circuit for eliminating pop sounds at power on and off by a moderate waveform in accordance with the invention. In FIG. 3, the circuit includes a switch 310, a feedback network 320, an operational amplifier 330 and an output network 340.
The switch 310 has a first input terminal 311 connected to a low voltage and a second input terminal 312 connected to a reference voltage Vref for switching at power on or off of the circuit. When power-on, the switch 310 connects the output terminal 313 to the low voltage. When power-off, the switch 310 connects the output terminal 313 to the reference voltage Vref. The reference voltage Vref is one third of a high voltage VDD.
The feedback network 320 is connected to the switch 310 in order to provide a feedback current I. The feedback network 320 is comprised of a first resistor R1 and a second resistor R2. The second resistor R2 has one terminal connected to the switch 310 and the other terminal connected to one terminal of the first resistor R1. The value of first resistor is triple of the value of second resistor.
The operational amplifier 330 has a negative input terminal connected to the first resistor R1 and the second resistor R2, and an output terminal 331 connected to the other terminal of the first resistor R1 and provides an output voltage VO.
The output network 340 has an output terminal 341. The output network 340 is comprised of a third resistor R3, a fourth resistor R4 and a capacitor C. The third resistor R3 has one terminal connected to the output terminal 331 of the operational amplifier 330, and the other terminal connected to the output terminal 341, one terminal of the fourth resistor R4, one terminal of the capacitor C and a positive input terminal of the operational amplifier 330. The fourth resistor R4 has the other terminal connected to the low voltage. The capacitor C has the other terminal connected to the low voltage. The third resistor R3 and the fourth resistor R4 have a same value.
When power-on, the output terminal 313 of the switch 310 is connected to the low voltage, and the circuit is provided with an operating bias VM, which is gradually increased, by the output terminal 341 of the output network 340. When power-off, the output terminal 313 of the switch 310 is connected to the reference voltage Vref, which is equal to VDD/3, and the circuit gradually reduces the operating bias VM at the output terminal 341 of the output network 340.
When the circuit is powered on and the output terminal 313 of the switch 310 is connected to the low voltage, the operating bias VM is an exponential function. FIG. 4 is a diagram of the operating bias VM at the output terminal 341 of the circuit of FIG. 3 in accordance with the invention, where VOS is setup to avoid a startup failure. Accordingly, VOS is a positive voltage at ramp up and a negative voltage at ramp down. Namely, when the operating bias VM is greater than and equal to zero and small than one fourth of the high voltage VDD, we have




  
    
      V
      M
    
    =
    
      2
      ⁢
      
        
          V
          OS
        
        ·
        
          (
          
            
              e
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
            -
            1
          
          )
        
      
    
  
  ,




where VOS indicates an input offset voltage of the operational amplifier 330, R indicates a value of the third resistor and C indicates a value of the capacitor.

When the operating bias VM is greater than and equal to one fourth of the high voltage VDD and small than one half of the high voltage VDD, the operating bias VM is equal to




  
    
      
        
          V
          DD
        
        4
      
      ·
      
        (
        
          1
          -
          
            e
            
              -
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
          
        
        )
      
    
    +
    
      
        V
        DD
      
      4
    
  
  ,




where VDD indicates the high voltage, R indicates a value of the third resistor and C indicates a value of the capacitor.

FIG. 5 is a schematic graph of the operating bias VM computed at power on in accordance with the invention. A signal plane for a typical single power audio amplifier is set to VDD/2 for obtaining the maximum voltage swing. Accordingly, the third resistor R3 and the fourth resistor R4 are set to a same value to thereby obtain a symmetric double log waveform at VDD/4. In this case, the operational amplifier 330 has a negative feedback gain of four. Namely, the first resistor R1 has a value triple of the second resistor R2 (R1/R2=3).
While powering on, when the operating bias VM is greater than or equal to zero and smaller than one fourth of the high voltage VDD (0≦VM<VDD/4), the input offset voltage VOS is greater than zero (VOS>0), the switch 310 connects the output terminal 313 to the low voltage (VMC=Ground), R1/R2=3, R3=R4=R, and the operating bias VM on the output terminal 341 is initialized at zero (VM(0)=0), the operating bias VM is derived as follows:




  
    
      
        
          
            V
            O
          
          =
          
            
              
                (
                
                  1
                  +
                  
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
              ×
              
                (
                
                  
                    V
                    M
                  
                  +
                  
                    V
                    OS
                  
                
                )
              
            
            =
            
              4
              ⁢
              
                (
                
                  
                    V
                    M
                  
                  +
                  
                    V
                    OS
                  
                
                )
              
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  V
                  O
                
                -
                
                  V
                  M
                
              
              
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
            =
            
              
                
                  3
                  ⁢
                  
                    V
                    M
                  
                
                +
                
                  4
                  ⁢
                  
                    V
                    OS
                  
                
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              4
            
          
          =
          
            
              
                V
                M
              
              
                R
                ⁢
                
                  
                
                ⁢
                4
              
            
            =
            
              
                V
                M
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            C
          
          =
          
            
              C
              ⁢
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
            
            =
            
              
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
                -
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              =
              
                
                  
                    2
                    ⁢
                    
                      V
                      M
                    
                  
                  +
                  
                    4
                    ⁢
                    
                      V
                      OS
                    
                  
                
                R
              
            
          
        
        ,
        
          

        
        ⁢
        
          
            
              C
              ⁢
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
            
            -
            
              
                
                  2
                  ⁢
                  
                    V
                    M
                  
                
                +
                
                  4
                  ⁢
                  
                    V
                    OS
                  
                
              
              R
            
          
          =
          0
        
        ,
        
          

        
        ⁢
        
          
            
              
                d
                
                  V
                  M
                
              
              
                d
                t
              
            
            -
            
              
                2
                RC
              
              ⁢
              
                (
                
                  
                    V
                    M
                  
                  +
                  
                    2
                    ⁢
                    
                      V
                      OS
                    
                  
                
                )
              
            
          
          =
          0.
        
      
    
    
      
        (
        1
        )
      
    
  




Equation (1) is a first-order differential equation, which is expressed as




  
    
      
        d
        y
      
      
        d
        t
      
    
    -
    
      α
      ⁢
      
        
      
      ⁢
      y
    
  
  =
  0




and has the solution expressed as y=K·eαt for K=y(0) in generic. Let x=VM+2VOS, it is derived that dx=dVM and x(0)=2VOS. Therefore, equation (1) is rewritten as:





  
    
      
        
          
            
              d
              x
            
            
              d
              t
            
          
          -
          
            
              2
              RC
            
            ⁢
            x
          
        
        =
        0.
      
    
    
      
        (
        2
        )
      
    
  




From equation (2), it is known that




  
    
      
        
          x
          =
          
            K
            ·
            
              e
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
          
        
        ,
        
          K
          =
          
            
              x
              ⁡
              
                (
                0
                )
              
            
            =
            
              2
              ⁢
              
                
                  V
                  OS
                
                .
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Accordingly, by taking x=VM+2VOS into equation (3), equation (4) can be obtained as:




  
    
      
        
          V
          M
        
        =
        
          2
          ⁢
          
            
              V
              OS
            
            ·
            
              
                (
                
                  
                    e
                    
                      
                        2
                        ⁢
                        t
                      
                      RC
                    
                  
                  -
                  1
                
                )
              
              .
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




While powering on, when the operating bias VM ranges from one fourth to one half of the high voltage VDD (VDD/4≦VM≦VDD/2), the input offset voltage VOS is greater than zero (VOS>0), the switch 310 connects the output terminal 313 to the low voltage (VMC=Ground), R1/R2=3, R3=R4=R, and the operating bias VM on the output terminal 341 is initialized at VDD/4 volts (VM(0)=VDD/4), the operating bias VM is derived as follows:




  
    
      
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  V
                  O
                
                -
                
                  V
                  M
                
              
              
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
            =
            
              
                
                  V
                  DD
                
                -
                
                  V
                  M
                
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              4
            
          
          =
          
            
              
                V
                M
              
              
                R
                ⁢
                
                  
                
                ⁢
                4
              
            
            =
            
              
                V
                M
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            C
          
          =
          
            
              C
              ⁢
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
            
            =
            
              
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
                -
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              =
              
                
                  
                    
                      -
                      2
                    
                    ⁢
                    
                      V
                      M
                    
                  
                  +
                  
                    V
                    DD
                  
                
                R
              
            
          
        
        ,
        
          

        
        ⁢
        
          
            ∴
            
              
                C
                ⁢
                
                  
                    d
                    
                      V
                      M
                    
                  
                  
                    d
                    t
                  
                
              
              +
              
                
                  
                    2
                    ⁢
                    
                      V
                      M
                    
                  
                  -
                  
                    V
                    DD
                  
                
                R
              
            
          
          =
          0
        
        ,
        
          

        
        ⁢
        
          
            
              
                d
                
                  V
                  M
                
              
              
                d
                t
              
            
            +
            
              
                2
                RC
              
              ⁢
              
                (
                
                  
                    V
                    M
                  
                  -
                  
                    
                      V
                      DD
                    
                    2
                  
                
                )
              
            
          
          =
          0.
        
      
    
    
      
        (
        5
        )
      
    
  




Equation (5) is a first-order differential equation, which is expressed as




  
    x
    =
    
      
        V
        M
      
      -
      
        
          V
          DD
        
        2
      
    
  
  ,




and has the solution expressed as y=K·eαt for K=y(0) in generic. Let





  
    
      
        d
        y
      
      
        d
        t
      
    
    -
    
      α
      ⁢
      
        
      
      ⁢
      y
    
  
  =
  0




it is derived that dx=dVM and





  
    x
    ⁡
    
      (
      0
      )
    
  
  =
  
    -
    
      
        
          V
          DD
        
        4
      
      .
    
  




Therefore, equation (5) is rewritten as:





  
    
      
        
          
            
              d
              x
            
            
              d
              t
            
          
          +
          
            
              2
              RC
            
            ⁢
            x
          
        
        =
        0.
      
    
    
      
        (
        6
        )
      
    
  




From equation (6), it is known that




  
    
      
        x
        =
        
          
            
              K
              ·
              
                e
                
                  -
                  
                    
                      2
                      ⁢
                      t
                    
                    RC
                  
                
              
            
            ⁢
            
              
            
            ⁢
            and
            ⁢
            
              
            
            ⁢
            K
          
          =
          
            
              x
              ⁡
              
                (
                0
                )
              
            
            =
            
              -
              
                
                  
                    V
                    DD
                  
                  4
                
                .
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Accordingly, by taking




  x
  =
  
    
      V
      M
    
    -
    
      
        V
        DD
      
      2
    
  




into equation (7), equation (8) can be obtained as:





  
    
      
        
          V
          M
        
        =
        
          
            
              
                V
                DD
              
              4
            
            ·
            
              (
              
                1
                -
                
                  e
                  
                    -
                    
                      
                        2
                        ⁢
                        t
                      
                      RC
                    
                  
                
              
              )
            
          
          +
          
            
              
                V
                DD
              
              4
            
            .
          
        
      
    
    
      
        (
        8
        )
      
    
  




Upon equations (4) and (8), the relationship between operating bias VM and time can be illustrated as shown in FIG. 5. From equations (4) and (8) and FIG. 5, it is known that the operating bias VM output by the circuit of the invention is a continuous waveform, which does not cause the pop sounds and slight noises at power-on.
While powering off, when the operating bias VM ranges from one fourth to one half of the high voltage VDD (VDD/4≦VM≦VDD/2), the input offset voltage VOS is smaller than zero (VOS<0), the switch 310 connects the output terminal 313 to the reference voltage (VMC=VDD/3), R1/R2=3, R3=R4=R, and the operating bias VM on the output terminal 341 is initialized at VDD/2 volts (VM(0)=VDD/2), the operating bias VM is derived as follows:




  
    
      
        
          
            
              
                
                  V
                  O
                
                =
                
                ⁢
                
                  
                    
                      V
                      DD
                    
                    3
                  
                  +
                  
                    
                      (
                      
                        1
                        +
                        
                          
                            R
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          
                            R
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                      
                      )
                    
                    ×
                    
                      (
                      
                        
                          V
                          M
                        
                        +
                        
                          V
                          OS
                        
                        -
                        
                          
                            V
                            DD
                          
                          3
                        
                      
                      )
                    
                  
                
              
            
          
          
            
              
                
                  =
                  
                  ⁢
                  
                    
                      
                        V
                        DD
                      
                      3
                    
                    +
                    
                      4
                      ×
                      
                        (
                        
                          
                            V
                            M
                          
                          +
                          
                            V
                            OS
                          
                          -
                          
                            
                              V
                              DD
                            
                            3
                          
                        
                        )
                      
                    
                  
                
                ,
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    4
                    ⁢
                    
                      V
                      M
                    
                  
                  +
                  
                    4
                    ⁢
                    
                      V
                      OS
                    
                  
                  -
                  
                    V
                    DD
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            
              I
              
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
            =
            
              
                
                  
                    V
                    O
                  
                  -
                  
                    V
                    M
                  
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              =
              
                
                  
                    3
                    ⁢
                    
                      V
                      M
                    
                  
                  +
                  
                    4
                    ⁢
                    
                      V
                      OS
                    
                  
                  -
                  
                    V
                    DD
                  
                
                R
              
            
          
          ,
          
            

          
          ⁢
          
            
              I
              
                R
                ⁢
                
                  
                
                ⁢
                4
              
            
            =
            
              
                
                  V
                  M
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
              
              =
              
                
                  V
                  M
                
                R
              
            
          
          ,
          
            

          
          ⁢
          
            
              I
              C
            
            =
            
              
                C
                ⁢
                
                  
                    d
                    
                      V
                      M
                    
                  
                  
                    d
                    t
                  
                
              
              =
              
                
                  
                    I
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      4
                    
                  
                  -
                  
                    I
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                
                =
                
                  
                    
                      2
                      ⁢
                      
                        V
                        M
                      
                    
                    +
                    
                      4
                      ⁢
                      
                        V
                        OS
                      
                    
                    -
                    
                      V
                      DD
                    
                  
                  R
                
              
            
          
          ,
          
            

          
          ⁢
          
            
              
                C
                ⁢
                
                  
                    d
                    
                      V
                      M
                    
                  
                  
                    d
                    t
                  
                
              
              -
              
                
                  
                    2
                    ⁢
                    
                      V
                      M
                    
                  
                  +
                  
                    4
                    ⁢
                    
                      V
                      OS
                    
                  
                  -
                  
                    V
                    DD
                  
                
                R
              
            
            =
            0
          
          ,
          
            

          
          ⁢
          
            
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
              -
              
                
                  2
                  RC
                
                ⁢
                
                  (
                  
                    
                      V
                      M
                    
                    +
                    
                      2
                      ⁢
                      
                        V
                        OS
                      
                    
                    -
                    
                      
                        V
                        DD
                      
                      2
                    
                  
                  )
                
              
            
            =
            0.
          
        
      
    
    
      
        (
        9
        )
      
    
  




Equation (9) is a first-order differential equation, which is expressed as




  
    
      
        d
        y
      
      
        d
        t
      
    
    -
    
      α
      ⁢
      
        
      
      ⁢
      y
    
  
  =
  0




and has the solution expressed as y=K·eαt for K=y(0) in generic. Let





  
    x
    =
    
      
        V
        M
      
      +
      
        2
        ⁢
        
          
        
        ⁢
        
          V
          OS
        
      
      -
      
        
          V
          DD
        
        2
      
    
  
  ,




it is derived that dx=dVM and x(0)=2VOS. Therefore, equation (9) is rewritten as:





  
    
      
        
          
            
              d
              x
            
            
              d
              t
            
          
          -
          
            
              2
              RC
            
            ⁢
            x
          
        
        =
        0.
      
    
    
      
        (
        10
        )
      
    
  




From equation (10), it is known that




  
    
      
        
          x
          =
          
            K
            ·
            
              e
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
          
        
        ,
        
          K
          =
          
            
              x
              ⁡
              
                (
                0
                )
              
            
            =
            
              2
              ⁢
              
                
                  V
                  OS
                
                .
              
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




Accordingly, by taking




  x
  =
  
    
      V
      M
    
    +
    
      2
      ⁢
      
        V
        OS
      
    
    -
    
      
        V
        DD
      
      2
    
  




into equation (11), equation (12) can be obtained as:





  
    
      
        
          V
          M
        
        =
        
          
            2
            ⁢
            
              
                V
                OS
              
              ·
              
                (
                
                  
                    e
                    
                      
                        2
                        ⁢
                        t
                      
                      RC
                    
                  
                  -
                  1
                
                )
              
            
          
          +
          
            
              
                V
                DD
              
              2
            
            .
          
        
      
    
    
      
        (
        12
        )
      
    
  




While powering off, when the operating bias VM is greater than or equal to zero and smaller than one fourth of the high voltage VDD (0≦VM<VDD/4), the input offset voltage VOS is smaller than zero (VOS<0), the switch 310 connects the output terminal 313 to the low voltage (VMC=VDD/3), R1/R2=3, R3=R4=R, and the operating bias VM on the output terminal 341 is initialized at VDD/4 volts (VM(0)=VDD/4), the operating bias VM is derived as follows:




  
    
      
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  V
                  O
                
                -
                
                  V
                  M
                
              
              
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
            =
            
              
                -
                
                  V
                  M
                
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            
              R
              ⁢
              
                
              
              ⁢
              4
            
          
          =
          
            
              
                V
                M
              
              
                R
                ⁢
                
                  
                
                ⁢
                4
              
            
            =
            
              
                V
                M
              
              R
            
          
        
        ,
        
          

        
        ⁢
        
          
            I
            C
          
          =
          
            
              C
              ⁢
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
            
            =
            
              
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
                -
                
                  I
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              =
              
                
                  
                    -
                    2
                  
                  ⁢
                  
                    V
                    M
                  
                
                R
              
            
          
        
        ,
        
          

        
        ⁢
        
          
            
              C
              ⁢
              
                
                  d
                  
                    V
                    M
                  
                
                
                  d
                  t
                
              
            
            +
            
              
                2
                ⁢
                
                  V
                  M
                
              
              R
            
          
          =
          0
        
        ,
        
          

        
        ⁢
        
          
            
              
                d
                
                  V
                  M
                
              
              
                d
                t
              
            
            +
            
              
                2
                RC
              
              ⁢
              
                V
                M
              
            
          
          =
          0.
        
      
    
    
      
        (
        13
        )
      
    
  




Equation (9) is a first-order differential equation, which is expressed as dy/dt−αy=0 and has the solution expressed as y=K·eαt for K=y(0) in generic. For




  
    
      V
      M
    
    =
    
      K
      ·
      
        e
        
          -
          
            
              2
              ⁢
              t
            
            RC
          
        
      
    
  
  ,
  
    K
    =
    
      
        
          V
          M
        
        ⁡
        
          (
          0
          )
        
      
      =
      
        
          V
          DD
        
        4
      
    
  
  ,




equation (14) is obtained as follows:





  
    
      
        
          V
          M
        
        =
        
          
            
              V
              DD
            
            4
          
          ·
          
            
              e
              
                -
                
                  
                    2
                    ⁢
                    t
                  
                  RC
                
              
            
            .
          
        
      
    
    
      
        (
        14
        )
      
    
  




Upon equations (12) and (14), the relationship between the operating bias VM and time can be illustrated as shown in FIG. 6. From equations (12) and (14) and FIG. 6, it is known that the operating bias VM output by the circuit of the invention is a continuous waveform, which does not cause the pop sounds and slight noises at power-on.
FIG. 7 is a circuit diagram of another embodiment of the invention. In FIG. 7, as compared to FIG. 3, the reference voltage is changed from VDD/3 to VDD. In addition, the fifth resistor R5 and the first resistor R1 have the same value, and the value of the sixth resistor R6 is half of the fifth resistor R5, i.e., R5/R6=2. The circuit left to point A is a Thevenin's circuit equivalent to that of FIG. 3 to thereby change the reference voltage Vref into VDD for conveniently integrating it into a same integrated circuit.
In view of the foregoing, it is known that the invention can eliminate the pop sounds and the slight noises caused by the DAC at power on and off in the prior art. The invention uses the operational amplifier, the resistors and the capacitor to replace the DAC used in the prior art, which can save the cost and gain the better response speed to thereby power on and off rapidly.
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.

## Claims

1. A circuit for eliminating pop sounds at power on and off, comprising:
a switch, which has a first input terminal connected to a low voltage and a second input terminal connected to a reference voltage for switching at power on or off;
a feedback network, which is connected to the switch in order to provide a feedback current and comprised of a first resistor and a second resistor, the second resistor having a first terminal connected to the switch and a second terminal connected to a first terminal of the first resistor;
an operational amplifier, which has a negative input terminal connected to the first terminal of the first resistor and the second terminal of the second resistor and has an output terminal connected to a second terminal of the first resistor; and
an output network, which has an output terminal, a third resistor, a fourth resistor and a capacitor, the third resistor having a first terminal connected to the output terminal of the operational amplifier and a second terminal connected to the output terminal of the output network, a first terminal of the fourth resistor, a first terminal of the capacitor and a positive input terminal of the operational amplifier, the fourth resistor having a second terminal connected to the low voltage, the capacitor having a second terminal connected to the low voltage;
wherein, when the switch is connected to the low voltage, the output terminal of the output network provides an operating bias, which is gradually increased, to the circuit, and the output terminal of the output network provides the operating bias, which is gradually reduced, to the circuit when the switch is connected to the reference voltage.

2. The circuit as claimed in claim 1, wherein the first resistor has a value triple of that of the second resistor.

3. The circuit as claimed in claim 2, wherein the third resistor has a value same as that of the fourth resistor.

4. The circuit as claimed in claim 3, wherein the reference voltage is one third of a high voltage.

5. The circuit as claimed in claim 4, wherein the operating bias is an exponential function of time when the switch is connected to the low voltage.

6. The circuit as claimed in claim 5, wherein the operating bias which is greater than or equal to zero and smaller than one fourth of the high voltage, the operating bias is expressed as




  
    2
    ⁢
    
      
        V
        OS
      
      ·
      
        (
        
          
            e
            
              
                2
                ⁢
                t
              
              RC
            
          
          -
          1
        
        )
      
    
  
  ,




where VOS indicates an input offset voltage of the operational amplifier, R indicates the value of the third resistor and C indicates a value of the capacitor.

7. The circuit as claimed in claim 5, wherein the operating bias which ranges from one fourth of the high voltage to one half of the high voltage is expressed as




  
    
      
        
          V
          DD
        
        4
      
      ·
      
        (
        
          1
          -
          
            e
            
              -
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
          
        
        )
      
    
    +
    
      
        V
        DD
      
      4
    
  
  ,




where VDD indicates the high voltage.

8. The circuit as claimed in claim 4, wherein the operating bias is an exponential function of time when the switch is connected to the reference voltage.

9. The circuit as claimed in claim 8, wherein the operating bias which ranges from one fourth of the high voltage to one half of the high voltage is expressed as




  
    
      2
      ⁢
      
        
          V
          OS
        
        ·
        
          (
          
            
              e
              
                
                  2
                  ⁢
                  t
                
                RC
              
            
            -
            1
          
          )
        
      
    
    +
    
      
        V
        DD
      
      2
    
  
  ,




where VOS indicates an input offset voltage of the operational amplifier, R indicates the value of the third resistor and C indicates a value of the capacitor.

10. The circuit as claimed in claim 9, wherein the operating bias which is greater than or equal to zero and smaller than one fourth of the high voltage is expressed as




  
    
      
        V
        DD
      
      4
    
    ·
    
      e
      
        -
        
          
            2
            ⁢
            t
          
          RC
        
      
    
  
  ,




where VDD indicates the high voltage.

11. A circuit for eliminating pop sounds at power on and off, comprising:
a switch, which has a first input terminal connected to a low voltage and a second input terminal connected to a reference voltage for switching at power on or off;
a feedback network, which is connected to the switch to provide a feedback current and includes a first resistor, a second resistor and a fifth resistor, the second resistor having a first terminal connected to the switch and a second terminal connected to first terminals of the first resistor and the fifth resistor, the fifth resistor having a second terminal connected to the low voltage;
an operational amplifier, which has a negative input terminal connected to the first terminal of the first resistor, the second terminal of the second resistor and the first terminal of the fifth resistor, and has an output terminal connected to a second terminal of the first resistor; and
an output network, which has an output terminal, a third resistor, a fourth resistor and a capacitor, the third resistor having a first terminal connected to the output terminal of the operational amplifier and a second terminal connected to the output terminal of the output network, a first terminal of the fourth resistor, a first terminal of the capacitor and a positive input terminal of the operational amplifier, the fourth resistor having a second terminal connected to the low voltage, the capacitor having a second terminal connected to the low voltage;
wherein, when the switch is connected to the low voltage, the output terminal of the output network provides an operating bias, which is gradually increased, to the circuit, and the output terminal of the output network provides the operating bias, which is gradually reduced, to the circuit when the switch is connected to the reference voltage.

12. The circuit as claimed in claim 11, wherein the first resistor has value same as that of the second resistor.

13. The circuit as claimed in claim 12, wherein the fifth resistor has a value half of that of the second resistor.

14. The circuit as claimed in claim 13, wherein the third resistor has a value same as that of the fourth resistor.

15. The circuit as claimed in claim 14, wherein the reference voltage is same as a high voltage.

16. The circuit as claimed in claim 15, wherein the operating bias is an exponential function of time when the switch is connected to the low voltage.