# Patent

## Title
Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in different regions

## Abstract

Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.

## Background
GOVERNMENT RIGHTS
This invention was made with Government support under Agreement HR0011-11-9-0009 awarded by DARPA. The Government has certain rights in the invention.


FIELD OF THE INVENTION
Disclosed method and structural embodiments are directed to providing an integrated optoelectronic structure containing photonic devices having different optical properties in different regions of the structure.
BACKGROUND OF THE INVENTION
Optoelectronic integrated structures are fabricated to have photonic devices with different optical properties. Often such devices are fabricated using materials that either strongly interact with guiding light through one of an absorption/gain process for photon signal detection, or which allow guided light to propogate with minimal attenuation, such as in a waveguide. The conventional manner of achieving these different results is to use different elements and materials in differing spatial locations in the optoelectronic integrated circuit. In group III-V photonic integrated circuits, materials such as In1-xGaxAs1-yPy of varying mole fractions can be employed for this purpose. In silicon-based optoelectronic integrated circuits other materials such as germanium or alloys thereof are utilized in combination with silicon. The integration of different materials in different regions in an optoelectronic integrated structures can add significantly to the cost and complexity of fabrication.
It would be desirable to provide a low cost and easily integrated optoelectronic integrated structure in which the same optical material can, in some regions, provide an optical device which functions as signal detector having associated high signal attenuation, and other regions as a low loss waveguide.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-section of a starting substrate for use in fabricating structural embodiments described herein;
FIG. 2 is a cross-section of the FIG. 1 structure after trench etching;
FIG. 3 is a cross-section of the FIG. 2 structure after a trench fill;
FIG. 4 is a cross-section of the FIG. 3 structure after a planarization of the trench fill and the deposition of oxide and polysilicon materials;
FIG. 5 is a cross-section of the FIG. 4 structure after a patterned photoresist is applied;
FIG. 6 is a cross-section of the FIG. 5 structure after an etch operation;
FIG. 7 is a cross-section of the FIG. 6 structure after application of an amorphous silicon layer;
FIG. 8 is a cross-section of the FIG. 7 structure after a patterned photoresist is applied;
FIG. 9 is a cross-section of the FIG. 8 structure after an etch operation;
FIG. 10 is a cross-section of the FIG. 9 structure after a further etch operation;
FIG. 11 is a cross-section of a starting structure for a second structural embodiment of the invention;
FIG. 12 is a cross-section of the FIG. 11 structure after application of a photoresist and illustrating an implant;
FIG. 13 is a cross-section of the FIG. 12 structure after removal of the photoresist;
FIG. 14 is a cross-section of the FIG. 13 structure after an etching operation;
FIG. 15 is a cross-section of the FIG. 14 structural after transistor implants;
FIG. 16 is a cross-section of FIG. 15 structure after application of an oxide material followed by a nitride material;
FIG. 17 is a cross-section of the FIG. 16 structure after an etch operation;
FIG. 18 is a cross-section of the FIG. 17 structure after a silicide operation;
FIG. 19 is a cross-section of the FIG. 18 structure after a further etching operation;
FIG. 20 is a cross-section of the FIG. 19 structure after selective removal of a nitride material; and
FIG. 21 is a cross-section of the FIG. 20 structure after formation of an oxide material and conductive vias.



DETAILED DESCRIPTION OF THE INVENTION
Method and structural embodiments described herein provide a polysilicon material with different absorption losses in different regions of an optoelectronic integrated structure such that low loss waveguides and high absorption signal detector photonic devices can be formed in the different regions. Method and apparatus embodiments also provide an optoelectronic structure in which a polysilicon material is used to form transistor gates, a low loss waveguide, and a defect-state photodetector in different regions of the optoelectronic structure. Generally, polysilicon, which is used for transistor gate formation in CMOS circuits, has a high optical signal absorption. As a result, method and structural embodiments employed herein provide polysilicon material having lower optical absorption in regions intended for optical waveguide formation, while leaving the inherent properties of a higher absorption in other regions of the optoelectronic structure for transistor gate formation and for defect-state photodetector formation.
Various method and structural embodiments of the invention will now be described in connection with the drawings. It should be understood that the specific method and structural embodiments described are examples and that modifications can be made without departing from the spirit or scope of the invention.
FIG. 1 illustrates a starting structure in the form of a substrate 101. The substrate 101 can be formed of various materials on which optoelectronic integrated devices can be constructed, for example, substrate 101 can be a semiconductor substrate, for example, a silicon substrate.
FIG. 2 illustrates formation of various shallow trench regions 103 and deeper trench regions 105a and 105b within the substrate 101. Conventional photo lithographic techniques employing a pattern photoresist and etching can be used to form the trenches 103, 105a and 105b. 
Following the trench formation illustrated in FIG. 2, and as illustrated in FIG. 3, the trench areas 103, 105a, 105b are filled with an oxide material 107, for example, silicon dioxide. Shallow filled trench areas 103 will be used for electronic device isolation, while the deeper filled trenches 105a, 105b will be used for optically isolating photonic devices from the substrate 101. Following this, the deposited oxide material 107 can be planarized down to the surface of the substrate 101 after which, as shown in FIG. 4, a further thin oxide 108, for example, silicon dioxide, can be grown or deposited on exposed surfaces of substrate 101 as a gate oxide for later transistor formation. Alternatively, the planarization of the oxide fill 107, as illustrated in FIG. 3 can be such that a thin layer of oxide 107 remains over the entire surface of the substrate 101 as a gate oxide 108.
In either case, as further illustrated in FIG. 4, after the formation of a thin gate oxide material 108, a polysilicon material 109 and an oxide material 111, e.g., silicon dioxide, are sequentially blanket deposited over the thin oxide material 108. Following this, and as shown in FIG. 5, a pattern photoresist material 113 is formed having an opening 115 over the filled trench 105a. This opening is used, as shown in FIG. 6, as a mask for an etch through the oxide material 111 and polysilicon material 109 to the level of the gate oxide material 108, forming opening 116.
As shown in FIG. 7, an amorphous silicon 117 is blanket deposited over the FIG. 6 structure including within the opening 116 shown in FIG. 6. As shown in FIG. 8, a photoresist 119 is patterned and located within opening 116 and over the filled trench 105a and amorphous silicon 117 within the opening 116 (FIG. 6). The photoresist 119 is used as a mask during an etching of the amorphous silicon 117 and oxide material 111 resulting in the structure illustrated in FIG. 9. FIG. 9 now has the original polysilicon layer 109 and, separated therefrom, and an amorphous silicon material 117 located over the deep trench 105a, which are both formed in the same plane at the same fabrication level. The FIG. 9 structure is subject to an annealing process which crystallizes the amorphous silicon 117, into a polysilicon material, denoted as 117a. Because the polysilicon material 117a started as an amorphous silicon layer which crystallizes during annealing, it has a lower optical signal absorption characteristic compared with the higher optical signal absorption characteristics of polysilicon material 109.
FIG. 10 further illustrates a patterned etching of the polysilicon material 109 to form, on the right side of FIG. 10, a gate 121 positioned between filled shallow trenches 103 for a transistor structure and on the left side, a polysilicon material element 122 which is over the filled deep trench 105b. The polysilicon material 117a, crystallized from amorphous silicon, can be used as a core of a low loss waveguide structure. Polysilicon material 109 has a higher absorption for photons and is suitable for transistor gates, and as a defect-state photodetector.
FIG. 11 is a cross-section of a starting structure for other method and structural embodiments. It illustrates the substrate 101, e.g. silicon substrate, the oxide filled shallow trenches 103 and the oxide filled deeper trench areas 105a and 105b. It also illustrates the gate oxide 108, and polysilicon material 109 over the gate oxide. These materials can be formed in the same manner as described above with reference to FIGS. 1-4.
FIG. 12 illustrates the formation of a patterned photoresist 123 having opening 122 over the FIG. 11 structure, and over oxide filled trench area 105a, and a subsequent doping implant (shown by arrows) into the polysilicon layer 109 through the opening 122 of the photoresist material 123. The implant in FIG. 12 is a high energy dose of silicon atoms which converts the implanted polysilicon material 109 into amorphous silicon in the region below opening 122. This amorphous silicon region is illustrated in FIG. 13 as amorphous silicon region 109a. This region is then recrystallized back into a polysilicon material through a suitable high temperature anneal. The recrystallized polycrystalline material in region 109a possesses a low photonic loss (lower attenuation) compared with the remaining region of polysilicon material 109.
FIG. 14 illustrates a subsequent etching of the polysilicon material 109 and 109a to produce a transistor gate 121, a high photon absorption area 122 for use as a phototector, and a low loss low absorption polysilicon material 109a which can be used as a core for waveguide formation. Once again, the polysilicon materials 109, 109a are formed in the optoelectronic integrated structure of polysilicon material having different properties in different regions of the optoelectronic structure. The lower 109a and higher 109 attenuation polysilicon elements are fabricated in the same plane at a same fabrication level to provide a higher attenuation transistor gate 121 and a higher attenuation defect-state photodetector 122, and a lower attenuation waveguide core 109a. 
FIG. 15 illustrates a starting structure for further processing which can either be the FIG. 14 structure or the FIG. 10 structure, as indicated by the polysilicon material 117 (or 109a) in FIG. 15. FIG. 15 further illustrates further processing by formation of source/drain regions 130 around gate 121 and an additional doped well 160. A threshold voltage (Vt) implant can also be provided. The various implants for determining desired transistor characteristics are well known in the art.
FIG. 16 illustrates the subsequent formation of a thin oxide material 125, for example, silicon dioxide, and followed by a thicker nitride material 127, e.g., silicon nitride, as blanket depositions over the FIG. 15 structure.
FIG. 17 illustrates the FIG. 16 structure after an etching to remove the nitride 127 and oxide 125 materials over the source/drain regions 130 and over the top of the transistor gate 121. This exposes copper areas of the gate 121 polysilicon and substrate containing the source/drain regions for a subsequent silicide operation.
FIG. 17 also illustrates the blanket deposition of a thin metal material 128 over the entire substrate for use in forming a silicide on exposed areas of polysilicon material of gate 121 and semiconductor substrate 101. The metal material can be, for example, chromium. Subsequently, a high temperature anneal converts the upper areas of the polysilicon in the gate 121 and silicon at the source/drain regions 130 into silicide areas 131, 132, shown in FIG. 18, providing highly conductive contacts. After the silicide areas 131, 132 are formed, the metal which remains on the nitride layer 127 and is unreacted is removed by a chemical etch, as further shown in FIG. 18.
FIG. 19 illustrates the selective etch and removal of the nitride 127 and optionally, the oxide 125, as shown, over the polysilicon area 122, which will be fabricated into a photodetector. It has been observed that removal of the nitride material 127 over the top surface of the polysilicon material 122 for use as a photodetector increases absorption and thus electrical signal output from the fabricated photodetector.
FIG. 20 illustrates the subsequent formation of an oxide material 135, for example, SiO2, or BPSG or PSG, over the entire structure and the subsequent formation of conductive vias 141 down to what is now a defect state photodetector 150. At this stage, the polysilicon material 117 (or 109a) is now entirely surrounded by cladding material and can be used as a low loss, low absorption, waveguide 154, the polysilicon material 121 is now a gate for a transistor 152.
The structure illustrated in FIG. 20 can now be further processed to complete an optoelectronic structure by forming interlayer dielectric (ILD) materials and associated metallization materials to interconnect the various photonic devices and circuit devices together, as well known in the art.
As evident from the foregoing, an optoelectronic structure is provided in which a polysilicon material has different attenuation and signal propogation characteristics in different regions. All fabricated polysilicon structures are also fabricated at the same physical level as the transistor gate to form both a low loss, lower absorption waveguide 154 as well as a higher absorption defect state photodetector 150.
While various embodiments of the invention have been described above, the invention is not confined to the specific disclosed method and structural embodiments as many modifications can be made without departing from the spirit or scope of the invention. Accordingly, the invention is not limited by the foregoing description but is only limited by the scope of the appended claims.

## Claims

1. An integrated structure comprising:
a first photonic device formed of a first polysilicon material;
a second photonic device formed of a second polysilicon material, different from the first polysilicon material, wherein the first polysilicon material and second polysilicon material are coplanar in the integrated structure and have different optical properties, wherein the first and second polysilicon materials reside on a common physical layer of the integrated structure; and
an electronic circuit comprising at least one transistor, wherein a gate of the at least one transistor is formed of the first polysilicon material.

2. An integrated structure as in claim 1, wherein the first and second polysilicon materials have different optical transmission properties.

3. An integrated structure as in claim 1, wherein the first and second polysilicon materials have different optical absorption properties.

4. An integrated structure as in claim 1 wherein the first and second polysilicon materials have different grain structures.

5. An integrated structure as in claim 1, wherein the first photonic device comprises a defect state photodetector and the second photonic device comprises a waveguide.

6. An integrated structure as in claim 5, wherein the second polysilicon material comprises an amorphized and recrystallized polysilicon material.

7. An integrated structure as in claim 5, wherein the second polysilicon material is located in a region where the first polysilicon material has been removed.

8. An integrated structure as in claim 5, further comprising a nitride material over the second polysilicon material, but not over the first polysilicon material.

9. An integrated structure as in claim 8, wherein the nitride material comprises silicon nitride.

10. An integrated structure as in claim 1, further comprising a first dielectric isolation region within a substrate for electrically isolating the transistor and a second deeper dielectric optical isolation region within the substrate and below the second polysilicon material.