# Patent

## Title
Method and apparatus for providing power conversion using an interleaved flyback converter with automatic balancing

## Abstract

Method and apparatus for converting DC input power to DC output power. In one embodiment, the apparatus comprises a plurality of flyback circuits, coupled in parallel, for providing DC-to-DC conversion; and a controller for automatically adjusting activation timing of each flyback circuit in said plurality of flyback circuits to achieve a balanced operation.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention is a continuation of co-pending U.S. patent application Ser. No. 14/028,349, filed Sep. 16, 2013, which is a continuation of U.S. patent application Ser. No. 12/284,985, filed Sep. 26, 2008 (now U.S. Pat. No. 8,537,572, issued Sep. 17, 2013), which claims benefit of U.S. provisional patent application Ser. No. 60/995,784, filed Sep. 28, 2007. Each of the aforementioned patent applications is herein incorporated in its entirety by reference.


BACKGROUND OF THE INVENTION
Field of the Invention
Embodiments of the present invention generally relate to power conversion and, more particularly, to a method and apparatus for performing power conversion using an interleaved flyback converter with automatic balancing.
Description of the Related Art
A number of switched mode (pulse width modulated) DC-to-DC converter topologies are available in the power electronics arts for performing DC-to-DC conversion. Such converters employ a flyback converter topology which is used in instances that require electrical isolation, voltage boost-up, and high efficiency. A flyback converter topology consists of a transformer, a switch (usually a power MOS FET transistor) and a diode. Typically, the switch is in series with the primary winding of the transformer and the secondary winding the transformer is serially coupled through the diode to a load. By switching a current through the primary coil, the DC voltage applied across the primary coil and switch is “boosted” to a higher voltage level at the load.
In order to double the output power available from a typical DC-to-DC converter, two flyback converters may be connected in parallel and operated in an interleaved fashion. Each of the flyback converters forms a “leg” of the overall DC-to-DC conversion process. Each leg is activated independently and in an interleaved manner. To facilitate a balanced operation such that the power is accurately converted from the input DC to the DC applied to the load, each leg must be “matched”. To be able to exactly split the load in a balanced fashion across the legs and be able to activate one leg while the other leg is completely deactivated, the components of the two converters must exactly match each other. In practical implementations, this is simply not possible, which leads to misbehavior, i.e., activation and deactivation times are not synchronized and the load is not balanced. Such operation can lead to inefficient conversion and, in some instances, damage to the DC-to-DC converter circuitry.
Therefore, there is a need in the art for a method and apparatus for providing power conversion using interleaved flyback converters with automatic balancing.
SUMMARY OF THE INVENTION
Embodiments of the present invention generally relate to a method and apparatus for converting DC input power to DC output power. In one embodiment, the apparatus comprises a plurality of flyback circuits, coupled in parallel, for providing DC-to-DC conversion; and a controller for automatically adjusting activation timing of each flyback circuit in said plurality of flyback circuits to achieve a balanced operation.



BRIEF DESCRIPTION OF THE DRAWINGS
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG. 1 is a schematic diagram of a DC-to-DC converter in accordance with one or more embodiments of the present invention;
FIG. 2 is a timing diagram of the signals used within the DC-to-DC converter of FIG. 1; and
FIG. 3 is a timing diagram representing the automatic signal balancing within the DC-to-DC converter that occurs in accordance with one embodiment of the invention.



DETAILED DESCRIPTION
FIG. 1 is a schematic diagram of a DC-to-DC converter 100 in accordance with one or more embodiments of the present invention. This diagram only portrays one variation of the myriad of possible DC-to-DC converter configurations. The present invention can function in a variety of power conversion environments including photovoltaic systems, DC-to-AC inverters, and other systems requiring DC-to-DC conversion.
The DC-to-DC converter 100 (an interleaved flyback converter) comprises a plurality of flyback circuits 105 such as first flyback circuit 106 and a second flyback circuit 108 coupled to a controller 112. The DC-to-DC converter converts DC voltage from a DC source 102 to a DC voltage for a load 110. The flyback circuits are arranged in a parallel manner with respect to the load and input DC source 102. The DC-to-DC converter comprises an input capacitor 104 that is used for storing energy to facilitate an accurate DC-to-DC conversion process when using a DC source 102 having limited current generation capability. The DC source 102 may be a photo voltaic (PV) panel or some other source of DC power. The load 110 may be a device that uses the DC power, including a DC-to-AC converter such that the circuit becomes a DC-to-AC inverter using the DC-to-DC converter 100 as the first stage of a DC-to-AC inversion process.
The first flyback circuit 106 comprises a transformer T1 and a switch Q1. The primary coil of the transformer is coupled in series to the switch Q1. The secondary coil of the transformer T1 is coupled through a diode D1 to a load 110. The flyback circuit 106, in one embodiment, uses a field effect transistor (FET) as the switch Q1. The gate of the transistor is coupled to the controller 112. The drain of the transistor is coupled to ground as well as to one terminal of the DC source 102, and the source of the transistor Q1 is coupled to the primary coil of the transformer T1. A capacitor 104 is coupled across the input to the flyback circuit 106 such that one terminal of the capacitor 104 is coupled to one terminal of the primary coil of the transformer T1, and the second terminal of the capacitor 104 is coupled to the drain of the transistor Q1 (i.e., ground).
In a similar manner, the second flyback circuit 108 comprises a transformer T2 and a switch Q2 which is, for example, a field effect transistor Q2. The drain of the transistor Q2 is coupled to ground. The gate of the transistor Q2 is coupled to the controller 112, and the source of the transistor Q2 is coupled to the primary coil of transformer T2. The second terminal of the transformer T2 is coupled to the first terminal of the capacitor 104. In this manner, the input of the flyback circuit 108 is coupled in parallel with the input of the flyback circuit 106. The output of the flyback circuit 108 formed by the secondary coil of transformer T2 is coupled through a diode D2 to the load 110. In this manner, the output of the flyback circuit 108 is coupled in parallel with the output of the flyback circuit 106.
Between the primary coil and the switch of each flyback circuit 106, 108 is a current monitoring element 114, 118 and a voltage monitoring element 116, 120. The voltage and current monitored in each flyback circuit 106, 108 is coupled to the controller 112 to control activation timing of each of the legs (circuits 106, 108) of the DC-to-DC converter 100 and to achieve automatic load balancing.
The controller 112 comprises a central processing unit (CPU) 122, support circuits 124 and memory 126. The CPU 122 may be a form of processor, microprocessor, microcontroller including an application specific integrated circuit (ASIC). The support circuits 124 comprise well known circuits that support the functionality of the CPU 122 including power supplies, clock circuits, bus circuits, interface circuits and the like. The memory 126 comprises random access memory, read only memory, and combinations thereof. The memory 126 stores the control software 128 that is executed by the CPU 122 to control the operation of the interleaved flyback circuits 106 and 108. To facilitate digital control, the signals from the sensors 114, 116, 118 and 120 are converted from analog signals to digital signals using analog-to-digital conversions (ADC) that may stand-alone or be part of the controller 112.
In operation, the controller 112 processes the sensor signals to derive timing signals for the switches Q1 and Q2 to achieve timing synchronization and load balancing for the interleaved flyback circuits 106 and 108. The use of interleaved flyback circuits reduces ripple current in the output power, doubles the ripple frequency to facilitate simplified filtering to remove the ripple, and doubles the output power of the converter. Interleaving functions best when the activation and deactivation cycles of each flyback circuit are exactly 180 degrees out of phase. For embodiments of the present invention to achieve automatic balancing and timing accuracy, the conversion frequency of the converter must be dependent upon the current (IP) through the transformer primary coil. The nature of the signal processing used to achieve balance and timing accuracy is discussed with respect to FIG. 3 below.
Although the DC-to-DC converter 100 of FIG. 1 depicts two flyback circuits 106, 108 operating in parallel, the invention can be expanded to any number of flyback circuits coupled in parallel.
FIG. 2 depicts the relative timing of signals used within the DC-to-DC converter 100 of FIG. 1 in accordance with one embodiment of the invention. Graphs 202 and 204 depict the activation and deactivation times of each leg (each flyback circuit 106, 108) within the DC-to-DC converter 100. Each leg is operated on an interleaved manner such that one leg is activated while the other leg is deactivated and vice versa. The graph 206 shows the composite current through the primary windings where the primary winding current flows through each transformer when an associated leg is active. As such, there is no time when current is not flowing through one of the primary windings. The secondary winding current shown at graph 208 depicts the repetitive nature of the current flowing from the secondary windings. In a single stage flyback circuit, there is always a substantial period of time when the current is not flowing through the primary or secondary winding. Such deactivation causes a substantial ripple in the output DC voltage. By using a plurality of legs that are switched in an interleaved manner, current is continuously coupled to the load and the amount of ripple in the output DC voltage is significantly reduced. In addition, the use of parallel connected flyback circuits enables the output power to be substantially increased to the load, e.g., for two circuits, the available power is doubled.
Due to the mismatch in the components of the two interleaved legs, two issues arise: (1) the signal timing does not match on both legs, resulting in unsynchronized operation of the two legs (e.g., both legs may be active simultaneously) and (2) the load does not distribute equally on both legs due to the mismatch in other parts of the circuits such as a digital-to-analog converter in the sensing circuits used to monitor the current and voltage. Specifically, if the two transformers T1 and T2 primary coil winding inductances (LP1 and LP2) do not match, then the switching timing and the power delivered by each transformer will be different in each leg. In order to mitigate these issues, embodiments of the present invention utilize two techniques to improve timing synchronization and load balancing.
One embodiment of the invention uses timing equalization to ensure that the timing in each leg is accurate and there is no overlap between the active time of leg operation. For a given primary current (IP) the TON and TOFF times are determined. Hence, if there is a mismatch between LP1 and LP2, then the required IP is modified for leg 1 and leg 2, i.e., resulting in two current values:

IP1=IP+α1 

IP2=IP+α2 

Where the parameters α1 and α2 are the adjustment factors that are proportional to phase error. By adding α1 and α2 to the desired current (IP), the active time for each leg (TON1 and TON2) are made equal. The parameters are estimated as follows:
In one embodiment, α1=0 and α2 is adjusted to achieve the proper timing such that one flyback circuit (i.e., termed the master leg) has fixed timing and the other flyback circuit (i.e., termed the slave leg) is adjusted. Although such a compensation technique is sufficient for many applications, it can produce a fluctuation in the total output power as α2 is adjusted.
In detail, at startup, the first leg (leg 1) activates by turning Q1 on until IP is reached, at which time transistor Q1 is turned off.
In subsequent cycles, the interleaving phase (time) between the falling edge of the on period of leg 1 and the rising edge of the on period of leg 2 is measured as a period τ using, for example, a 25 MHz clock sampling clock.
The result, which could be positive or negative, is then used to derive α1 and α2 as:

α1=0→IP1=IP 

α2=τ→IP2=IP+τ

Note that τ can be either a positive or a negative number, i.e., the factor can be either decremented or incremented, but in complementary fashion. Thus, timing accuracy is achieved and maintained.
In an alternative embodiment, the controller measures the previous cycle duration for one of the flyback circuits (i.e., termed the master leg). A “zero error point” is derived as one-half the duration of the master cycle. This zero error point is used as the activation point for the other flyback circuit (i.e., termed the slave leg).
FIG. 3 depicts the process discussed above, wherein the “on” times in the first cycle are shown as T1 and T2 at 310 and 314. The pulses that start the “on” time are shown at 312 and 316. The delay between periods T1 and T2 is shown as the period τ. During period of the first cycle, the correction a is determined. Then, α is used to adjust the timing of the flyback beginning at the circuits to achieve a τ equal to zero, where the end of the “on” time 318 of the first leg and the “on” time 322 of the second leg are aligned such that activation periods do not overlap. The switching pulses are also aligned at 320 and 324 to form a T equal to zero.
In another embodiment, both α1 and α2 have value such that both IP1 and IP2 are adjusted in a complementary fashion. Because of the complementary adjustment, the total output power is substantially constant while the adjustment is occurring. In this embodiment,

IP1=IP+α1 

IP2=IP+α2 

By determining a, timing synchronization is automatically achieved. As such, the interleaved flyback circuits form an efficient DC-to-DC converter.
In the embodiments described above, the controller forms part of a phase locked loop (PLL) using a proportional control technique, i.e., the correction is proportional to the error. An alternative controller may use an alternative technique such as a proportional integral technique or a proportional-integral-derivative (PID) technique.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

## Claims

1. An apparatus for converting power comprising:
a plurality of flyback circuits, coupled in parallel, for providing DC-to-DC conversion; and
a controller for automatically adjusting activation timing of each flyback circuit in said plurality of flyback circuits to achieve a balanced operation by minimizing the differences in the times between the end of each flyback circuit activation period and the beginning of the subsequent flyback circuit activation period.

2. The apparatus of claim 1 further comprising a current sensor and a voltage sensor associated with each flyback circuit in the plurality of flyback circuits and coupled to the controller.

3. The apparatus of claim 1 wherein the plurality of flyback circuits comprises a first flyback circuit and a second flyback circuit, and the controller minimizes the differences by activating the second flyback circuit at a time equal to half of the duration of a previous cycle of the first flyback circuit.

4. The apparatus of claim 1 wherein the controller adjusts timing of switching the plurality of flyback circuits to achieve predefined current and voltage levels within the plurality of flyback circuits that establish at least one current control factor to balance a current produced by each flyback circuit in the plurality of flyback circuits.

5. The apparatus of claim 1 wherein the controller adjusts current control of each flyback circuit of the plurality of flyback circuits to achieve balanced timing.

6. The apparatus of claim 5 wherein each flyback circuit comprises a transformer having a primary winding, the controller controls a primary winding current to achieve current balancing across the plurality of flyback circuits.

7. The apparatus of claim 1 wherein the controller uses a proportional technique, a proportional-integral technique, or a proportional-integral-derivative technique.

8. A method of converting power using a plurality of flyback circuits coupled to each other in parallel comprising:
separately activating each flyback circuit in the plurality of flyback circuits on an interleaved basis; and
controlling activation of the plurality of flyback circuits to achieve a balanced operation by minimizing the differences in the times between the end of each flyback period.

9. The method of claim 8 wherein the controlling step further comprises controlling a current in a primary winding of a transformer located in each of the flyback circuits in the plurality of flyback circuits.

10. The method of claim 9 wherein the current controlling step further comprises minimizing a time between an end of a first activation pulse for a first flyback circuit and a beginning of an activation pulse for a second flyback circuit.

11. The method of claim 8 wherein the controlling step utilizes a set of factors that are automatically adjusted to achieve the balanced operation.

12. The method of claim 8 wherein the controlling step comprises using a proportional technique, a proportional-integral technique, or a proportional-integral-derivative technique.