# Patent

## Title
Driving device for display device

## Abstract

A driving device for a display device wherein the display device and a source driver are connected by a plurality of external lines. A bias voltage generating part generates a bias voltage for controlling internal operating current of the plurality of amplifiers in the source driver to supply to each amplifier via a bias voltage supply line. The bias voltage supply line is laid out such that for the amplifier connected to the external line of a longer length, the length of the bias voltage supply line from the bias voltage generating part to the amplifier is shorter so as to raise a bias voltage supplied to the amplifier.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display-device driving device that drives a display device according to a video signal.
2. Description of the Related Art
In, for example, a liquid crystal display panel as a display device, a plurality of gate lines extending in a horizontal direction of the two-dimensional screen and a plurality of source lines extending in a vertical direction of the two-dimensional screen are arranged to intersect. Further, in the liquid crystal display panel, a source driver that applies gradation display voltages corresponding to the luminance levels of pixels denoted by an input video signal to the source lines respectively and a gate driver that applies scan signals to the gate lines respectively are incorporated (refer to, e.g., Japanese Patent Application Laid-Open No. 2004-301946). In this source driver, by making timings when the latches take in display data differ from one another by means of delay circuits using the element delays of inverter elements, the state where steep changes in the amounts of current of the source lines occur simultaneously is avoided so as to prevent noise that would occur if in this state.
SUMMARY OF THE INVENTION
Where a liquid crystal display panel having a size greater than the chip size of the source driver is driven by a single source driver, the respective lengths of lines connecting the source driver and the source lines of the liquid crystal display panel are not the same. Thus, the wiring resistances of the lines are different, and hence times until gradation display voltages sent out from the driver reach the source lines are different. Therefore, gradation display voltages are supplied to pixels connected to source lines placed farther from the driver with greater delays, which causes the problem that display unevenness occurs.
An object of the present invention is to provide a display-device driving device that can perform image display of high quality without display unevenness even if the lengths of a plurality of lines connecting between a display device and the driver are different.
According to the present invention, there is provided a driving device for driving a display device which has a source driver that applies pixel drive voltages respectively denoting luminance levels of pixels to a plurality of source lines of the display device via external lines respectively. The source driver includes: a plurality of amplifiers provided correspondingly to the plurality of source lines respectively and configured to generate the pixel drive voltages so as to supply it to the external lines respectively, the respective one of the plurality of amplifiers having a control terminal and operating with a transition speed in accordance with a voltage supplied thereto via the control terminal; a bias voltage supply line having its opposed ends; and a bias voltage generating part that generates a bias voltage and supplies the bias voltage across the opposed ends. The bias voltage supply line is connected to the control terminal of the respective one of the amplifiers so that the respective length from the either one end of said bias voltage supply line to the respective control terminal of the amplifiers correspond in length to the external line connected to the respective one of the amplifier.
According to the present invention, there is provided a driving device for a display device which has a source driver that applies pixel drive voltages respectively denoting luminance levels of pixels to a plurality of source lines of the display device via external lines respectively. The source driver includes a first group of amplifiers provided corresponding to source lines in charge of the left region of a two-dimensional screen of the display device from among the plurality of source lines and that generate the pixel drive voltages to send onto the external lines respectively; a second group of amplifiers provided corresponding to source lines in charge of the right region of the two-dimensional screen of the display device from among the plurality of source lines and that generate the pixel drive voltages to send onto the external lines respectively; a bias voltage generating part that generates a bias voltage for controlling output delays of the first and second groups of amplifiers; a first bias voltage supply line via which to supply the bias voltage to the first group of amplifiers; and a second bias voltage supply line via which to supply the bias voltage to the second group of amplifiers. The bias voltage generating part has a first terminal connected to one end of the first bias voltage supply line, a second terminal connected to the other end thereof, a third terminal connected to one end of the second bias voltage supply line, and a fourth terminal connected to the other end thereof. In a first mode, the bias voltage is applied to the first terminal and the third terminal, and simultaneously a voltage lower than the bias voltage is applied to the second terminal and the fourth terminal, and in a second mode, with the second terminal and the fourth terminal being short-circuited, the bias voltage is applied to the first terminal, and simultaneously a voltage lower than the bias voltage is applied to the third terminal, and in a third mode, with the second terminal and the fourth terminal being short-circuited, the bias voltage is applied to the third terminal, and simultaneously a voltage lower than the bias voltage is applied to the first terminal. The longer the length of the external line connected to any of the amplifiers is, the shorter the length of the first and second bias voltage supply lines connecting a terminal to which the bias voltage is applied from among the first and third terminals and an input terminal of the amplifier is.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a display apparatus including a driving device according to the present invention;
FIG. 2 is a block diagram showing the internal configuration of a source driver 3;
FIG. 3 is a diagram showing the internal configuration of an output amplifier circuit 134;
FIG. 4 is a block diagram showing another example of the display apparatus including the driving device according to the present invention;
FIG. 5 is a block diagram showing another example of the internal configuration of the source driver 3;
FIG. 6 is a block diagram showing another example of the display apparatus including the driving device according to the present invention;
FIG. 7 is a block diagram showing another example of the internal configuration of the source driver 3; and
FIG. 8 is a diagram showing another example of the output amplifier circuit 134.



DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing schematically the configuration of a display apparatus having incorporated therein a driving device for a display device according to the present invention. As shown in FIG. 1, this display apparatus includes a drive control part 1, a scan driver 2, a source driver 3, and a display device 20.
The display device 20 is constituted by, e.g., a liquid crystal or organic EL panel, or the like. In the display device 20, there are formed m number of horizontal scan lines S1 to Sm (m is a natural number of two or greater), which extend in a horizontal direction of a two-dimensional screen and n number of source lines D1 to Dn (n is a natural number of two or greater), which extend in a vertical direction of the two-dimensional screen. Further, in each of the intersection regions of the horizontal scan lines and the source lines, a display cell for a pixel is formed.
The drive control part 1 extracts a horizontal synchronizing signal from a video signal to supply this signal to the scan driver 2. Further, the drive control part 1 generates a sequence of pixel data PD each denoting the luminance level of a pixel in, e.g., eight bits based on this video signal to supply this sequence as a pixel data signal PDS to the source driver 3.
The scan driver 2 generates horizontal scan pulses synchronous with the above horizontal synchronizing signal to apply them sequentially, respectively to the scan lines S1 to Sm of the display device 20.
The source driver 3 is formed on, e.g., a semiconductor chip and takes in the sequence of pixel data PD in the pixel data signal PDS. Each time that one horizontal scan line worth of, i.e., n number of pixel data PD, where n is the total number of the source lines, are taken in, the source driver 3 converts the n number of pixel data PD taken in into pixel drive voltages having voltage values corresponding to the respective luminance levels denoted by them to apply to the source lines D1 to Dn of the display device 20.
FIG. 2 is a block diagram showing the internal configuration of the source driver 3. As shown in FIG. 2, the source driver 3 includes a shift register 131, a data latch part 132, a gradation voltage converter circuit 133, and an output amplifier circuit 134.
The shift register 131 takes in the sequence of pixel data PD from the pixel data signal PDS supplied from the drive control part 1 to supply one horizontal scan line worth (n number) of pixel data PD as pixel data P1 to Pn to the data latch part 132.
The data latch part 132 takes in the pixel data P1 to Pn to supply them as pixel data R1 to Rn to the gradation voltage converter circuit 133.
The gradation voltage converter circuit 133 converts the above pixel data R1 to Rn to pixel drive voltages V1 to Vn having voltage values corresponding to their respective luminance levels to supply to the output amplifier circuit 134. The output amplifier circuit 134 applies the pixel drive voltages V1 to Vn amplified to a desired level, as pixel drive voltages G1 to Gn, to the source lines D1 to Dn of the display device respectively. The output amplifier circuit 134 is put in a bias voltage set mode, that is, one of a V-slew mode, an R-slew mode, and an L-slew mode described later, which is designated by a bias supply line setting signal BSS supplied from the drive control part 1.
In the case where the source driver 3 having a chip size smaller than the lateral width of the display device 20 is placed along one side of the display device 20 and on the middle of the side as shown in FIGS. 1 and 2, as to the lengths of external lines U1 to Un connecting the output amplifier circuit 134 and the source lines D1 to Dn, those on the middle of the side of the display device 20 are the shortest, and, when going toward either end, those become longer. For example, where n is an even number, in the example shown in FIG. 1, from among the external lines U1 to Un, the lengths of the external lines UQ and UQ+1 (Q=n/2) placed on the middle are the shortest, and the lengths of the external lines U1 and Un placed in both ends are the longest. Accordingly, as to the values of the wiring resistances of U1 to Un, those on the middle of the side of the display device 20 are smaller, and, when going toward either end, those become greater. Thus, as to the transmission delays on the external lines U1, U2, . . . , UQ, UQ+1, . . . , Un−1, Un, that on U1 (Un) is the largest, and the transmission delay decreases in the order of U2 (Un−1), U3 (Un−2), . . . , UQ (UQ−1).
Where n is an odd number, from among the external lines U1 to Un, the length (wiring length) of the external line UQ (Q=(n+1)/2) placed on the middle is the shortest, and the lengths of the external lines U1 and Un placed in both ends are the longest. Thus, as to the transmission delays on the external lines U1, U2, . . . , UQ−1, UQ, UQ+1, . . . , Un−1, Un, that on U1 (Un) is the largest, and the transmission delay decreases in the order of U2 (Un−1), U3 (Un−2), . . . , UQ−1 (UQ+1), UQ.
FIG. 3 is a block diagram showing the internal configuration of the output amplifier circuit 134. As shown in FIG. 3, the output amplifier circuit 134 has a bias voltage generating part 30, a bias voltage supply line setting part 40, and amplifiers AP1 to APn respectively corresponding to the source lines D1 to Dn. The bias voltage generating part 30 and the amplifiers AP1 to APn are connected by bias voltage supply lines BL1 and BL2.
The amplifiers AP1 to APn are arranged in a line along the side thereof in the semiconductor chip. The amplifiers AP1 to APn are constituted by, e.g., operational amplifiers and apply the pixel drive voltages G1 to Gn respectively obtained by amplifying the pixel drive voltages V1 to Vn supplied from the gradation voltage converter circuit 133 to the source lines D1 to Dn of the display device 20 via the external lines U1 to Un respectively. A bias voltage input terminal (a control terminal), via which to input a bias voltage to control current flowing through the differential stage of the operational amplifier, i.e., internal operating current, is provided in each of the amplifiers AP1 to APn. Hence, individually for each of the amplifiers AP1 to APn, the internal operating current is adjusted through the bias voltage supplied to the bias voltage input terminal. The higher the bias voltage supplied to the bias voltage input terminal is, the larger the internal operating current is, and thus the amplifier AP operates at higher speed (with higher transition speed), so that its output delay becomes smaller.
The bias voltage supply line setting part 40 switches the connection of switches 31 to 36 formed in the bias voltage generating part 30 according to the bias voltage set mode designated by the bias supply line setting signal BSS.
The bias voltage generating part 30 generates various bias voltages to control the internal operating current of each of the amplifiers AP1 to APn and supplies these to the respective bias voltage input terminals of the AP1 to APn via the bias voltage supply lines BL1 and BL2.
As shown in FIG. 3, the bias voltage generating part 30 includes the switches 31 to 36, a voltage generating unit 37, and terminals T1 to T4 via which to output bias voltages.
The voltage generating part 37 generates voltages V1 to V8 which have a magnitude relation that, e.g., V1>V2>V3>V4>V5>V6>V7>V8 and supplies the voltages V1 to V4 of them to each of the switches 31 and 32 and the voltages V5 to V8 to each of the switches 33 and 34.
The switch 31 selects one of the voltages V1 to V4 according to a switch switching signal supplied from the bias voltage supply line setting part 40 to apply the selected voltage onto the terminal T1.
The switch 32 selects one of the voltages V1 to V4 according to a switch switching signal supplied from the bias voltage supply line setting part 40 to apply the selected voltage onto the terminal T3.
The switch 33 selects one of the voltages V5 to V8 according to a switch switching signal supplied from the bias voltage supply line setting part 40 to supply the selected voltage to the switch 35.
The switch 34 selects one of the voltages V5 to V8 according to a switch switching signal supplied from the bias voltage supply line setting part 40 to supply the selected voltage to the switch 36.
The switch 35 applies one of the voltage supplied from the switch 33 and a voltage supplied via a short line SL onto the terminal T2 according to a switch switching signal supplied from the bias voltage supply line setting part 40.
The switch 36 applies one of the voltage supplied from the switch 34 and a voltage supplied via the short line SL onto the terminal T4 according to a switch switching signal supplied from the bias voltage supply line setting part 40.
As shown in FIG. 3, the terminal T1 of the bias voltage generating part 30 is connected to one end of the bias voltage supply line BL1, and the terminal T2 of the bias voltage generating part 30 is connected to the other end of the BL1. Further, the respective bias voltage input terminals of the AP1 to APQ (a first amplifier group) placed in the left region from among the amplifiers AP1 to APn are connected to the bias voltage supply line BL1. Note that as to the lengths (wiring lengths) of the bias voltage supply line BL1 from the terminal T1 to the respective bias voltage input terminals of the AP1 to APQ, that for APQ is the longest, and the length decreases in the order of APQ−1, . . . , AP2, AP1.
Further, as shown in FIG. 3, the terminal T3 of the bias voltage generating part 30 is connected to one end of the bias voltage supply line BL2, and the terminal T4 of the bias voltage generating part 30 is connected to the other end of the BL2. The respective bias voltage input terminals of the APQ+1 to APn (a second amplifier group) placed in the right region from among the amplifiers AP1 to APn are connected to the bias voltage supply line BL2. Note that as to the lengths of the bias voltage supply line BL2 from the terminal T3 to the respective bias voltage input terminals of the APQ+1 to APn, that for APQ+1 is the longest, and the length decreases in the order of APQ+2, APQ+3, . . . , APn−2, APn−1, APn.
As described above, the bias voltage supply lines BL1 and BL2 are connected to the control terminal of the respective one of the amplifiers AP1 to APn so that the respective length from the either one end of the bias voltage supply lines BL1 and BL2 to the respective control terminal of the amplifiers AP1 to APn correspond in length to the external line U1 to Un connected to the respective one of the amplifier AP1 to APn.
The supply of bias voltages via the bias voltage supply lines BL1 and BL2 shown in FIG. 3 will be described below.
First, in the example shown in FIG. 1, since the source driver 3 is placed on the middle of one side of the display device 20, the drive control part 1 supplies the bias supply line setting signal BSS designating the V-slew mode (first mode) to the bias voltage supply line setting part 40. The bias voltage supply line setting part 40, according to this bias supply line setting signal BSS designating the V-slew mode, supplies switch switching signals to the bias voltage generating part 30 to apply, e.g., the largest voltage V1 as a bias voltage to each of the terminals T1 and T3 as first terminals and to apply the voltage V8 smaller than the voltage V1 to the terminals T2 and T4 as second terminals. Thus, the switch 31 applies the voltage V1 as a bias voltage onto the bias voltage supply line BL1 via the terminal T1. The switch 32 applies the voltage V1 as a bias voltage onto the bias voltage supply line BL2 via the terminal T3. The switches 33 and 35 applies the voltage V8 onto the bias voltage supply line BL1 via the terminal T2. The switches 34 and 36 applies the voltage V8 onto the bias voltage supply line BL2 via the terminal T4.
Thus, in the V-slew mode, because the potential on the terminal T1 is at V1 and higher than the potential V8 on the terminal T2, a current flows in the direction from the terminal T1 toward the terminal T2 via the bias voltage supply line BL1. Also, because the potential on the terminal T3 is at V1 and higher than the potential V8 on the terminal T4, a current flows in the direction from the terminal T3 toward the terminal T4 via the bias voltage supply line BL2.
As described above, the lengths of the bias voltage supply line BL1 from the terminal T1 to the respective bias voltage input terminals of the AP1 to APQ are ranked from longest in the order of APQ, APQ−1, . . . , AP2, AP1. Accordingly, the wiring resistances are also ranked from highest in the order of APQ, APQ−1, . . . , AP2, AP1. Thus, the bias voltage supplied to each amplifier is, in a sense, a voltage divided according to the wiring resistance of the bias voltage supply line BL1; the bias voltage having the largest voltage value is supplied to AP1; and the bias voltage supplied to AP decreases in the order of AP2, AP3, . . . , APQ−1, APQ.
According to these bias voltages, as to the output delays of AP1 to APQ, that of AP1 is the smallest, and the output delay increases in the order of AP2, AP3, . . . , APQ−1, APQ. Meanwhile, as to the transmission delays on the external lines U1 to UQ respectively connected to the amplifiers AP1 to APQ, that on the external line U1 is the largest, and the transmission delay decreases in the order of U1, U2, . . . , UQ−1, UQ as mentioned previously. Therefore, the application timings of the pixel drive voltages G1 to GQ that are applied to the source lines D1 to DQ via the amplifiers AP1 to APQ and the external lines U1 to UQ respectively become the same. That is, the bias voltage supply line BL1 is laid out in such a way that the respective lengths thereof from the terminal T1 to the AP1 to APQ are ranked from longest to shortest in the order of APQ, APQ−1, . . . , AP2, AP1 so that a higher bias voltage is supplied to the amplifier AP connected to the external line U having a longer length.
As such, by making the output delay of the amplifier AP connected to the external line U having a longer length smaller, the differences between the transmission delays on the external lines U1 to UQ are reduced. With this configuration, over the left region of the two-dimensional screen that the source lines D1 to DQ are in charge of, image display of high quality without display unevenness can be performed. Further, in the configuration shown in FIG. 3, different bias voltages are supplied by voltage division using the wiring resistance of the bias voltage supply line BL1 to the amplifiers AP1 to APQ respectively, and hence the area occupied by the output amplifier circuit in the chip can be reduced as compared with the case where a dedicated bias voltage supply line is provided for each amplifier AP to supply a bias voltage thereto individually.
Meanwhile, the lengths of the bias voltage supply line BL2 from the terminal T3 to the respective bias voltage input terminals of the APQ+1 to APn are ranked from longest in the order of APQ+1, APQ+2, . . . , APn−2, APn−1, APn. Accordingly, the wiring resistances are also ranked from highest in the order of APQ+1, APQ+2, . . . , APn−2, APn−1, APn. Thus, the bias voltage supplied to each amplifier is, in a sense, a voltage divided according to the wiring resistance of the bias voltage supply line BL2; the bias voltage having the largest voltage value is supplied to APn; and the bias voltage supplied to AP decreases in the order of APn−1, APn−2, . . . , APQ+2, APQ+1.
According to these bias voltages, as to the output delays of APQ+1 to APn, that of APn is the smallest, and the output delay increases in the order of APn−1, APn−2, . . . , APQ+2, APQ+1. Meanwhile, as to the transmission delays on the external lines UQ+1 to Un respectively connected to the amplifiers APQ+1 to APn, that on the external line Un is the largest, and the transmission delay decreases in the order of Un−1, Un−2, . . . , UQ+2, UQ+1 as mentioned previously.
Therefore, the application timings of the pixel drive voltages GQ+1 to Gn that are applied to the source lines DQ+1 to Dn via the amplifiers APQ+1 to APn and the external lines UQ+1 to Un respectively become the same. That is, the bias voltage supply line BL2 is laid out in such a way that the respective lengths thereof from the terminal T3 to the APQ+1 to APn are ranked from longest to shortest in the order of APQ+1, APQ+2, . . . , APn−2, APn−1, APn so that a higher bias voltage is supplied to the amplifier AP connected to the external line U having a longer length.
As such, by making the output delay of the amplifier AP connected to the external line U having a longer length smaller, the differences between the transmission delays on the external lines UQ+1 to Un are reduced. With this configuration, over the right region of the two-dimensional screen that the source lines DQ+1 to Dn are in charge of, image display of high quality without display unevenness can be performed. Further, in the configuration shown in FIG. 3, different bias voltages are supplied by voltage division using the wiring resistance of the bias voltage supply line BL2 to the amplifiers APQ+1 to APn respectively, and hence the area occupied by the output amplifier circuit in the chip can be reduced as compared with the case where a dedicated bias voltage supply line is provided for each amplifier AP to supply a bias voltage thereto individually.
As described above, in the output amplifier circuit 134 shown in FIG. 3, in forming the bias voltage supply lines in order to supply the bias voltages generated by the bias voltage generating part 30 respectively to the amplifiers AP1 to APn via the first terminals (T1, T3) and the bias voltage supply lines (BL1, BL2), the bias voltage supply lines are laid out in such a way that the longer the length of the external line (U1 to Un) connected to any of the amplifiers is, the shorter the length thereof from the first terminal to the amplifier is. With this configuration, the respective application timings of the pixel drive voltages G1 to Gn that are applied to the source lines D1 to Dn via the amplifiers AP1 to APn and the external lines U1 to Un respectively become the same, so that image display of high quality without display unevenness is performed.
Although the above embodiment describes an example of the case where the source driver 3 having a chip size smaller than the lateral width of the display device 20 is placed on the middle of one side of the display device 20, the position of the source driver is not limited to this. For example, as shown in FIGS. 4 and 5, the source driver 3 may be placed along the left end side of one side of the display device 20.
In this case, as shown in FIG. 5, as to the lengths of the external lines U1 to Un connecting the output amplifier circuit 134 and the source lines D1 to Dn, that of the external line located at the left end of one side of the display device 20 is the shortest, and when going toward the right end, the length of the external line becomes longer. In an example shown in FIG. 4, from among the external lines U1 to Un, the external line U1 placed at the left end is the shortest in length, and the external line Un placed at the right end is the longest in length. Thus, also as to the wiring resistances of U1 to Un, that of the external line located at the left end of one side of the display device 20 is smaller, and when going toward the right end, the wire resistance of the external line becomes larger. Therefore, as to the transmission delays on the external lines U1 to Un, that on Un is the largest, and the transmission delay decreases in the order of Un−1, Un−2, . . . , U3, U2, U1.
As such, where the source driver 3 is located along the left end side of the display device 20, the drive control part 1 supplies the bias supply line setting signal BSS designating the R-slew mode (second mode) to the bias voltage supply line setting part 40.
The bias voltage supply line setting part 40, according to this bias supply line setting signal BSS designating the R-slew mode, supplies switch switching signals to the bias voltage generating part 30 to apply, e.g., the largest voltage V1 as a bias voltage to the terminal T3 as the first terminal and to apply the voltage V4 smaller than the voltage V1 to the terminal T1 as the second terminal. Further, the bias voltage supply line setting part 40 supplies switch switching signals to short-circuit the terminals T2 and T4 to the bias voltage generating part 30.
Thus, the switch 32 applies the voltage V1 as a bias voltage onto the bias voltage supply line BL2 via the terminal T3. The switch 31 applies the voltage V4 onto the bias voltage supply line BL1 via the terminal T1. The switches 35 and 36 short-circuits the terminals T2 and T4 via a short line SL.
Thus, in the R-slew mode, because the potential on the terminal T3 is at V1 and higher than the potential V4 on the terminal T1, a current flows in the direction from the terminal T3 via the terminals T4 and T2 toward the terminal T1 via the bias voltage supply line BL2, the short line SL, and the bias voltage supply line BL1.
The lengths of the bias voltage supply line (BL2, SL, BL1) from the terminal T3 to the respective bias voltage input terminals of the AP1 to APn are ranked from longest in the order of AP1, AP2, . . . , APn−1, APn. Accordingly, the wiring resistances are also ranked from highest in the order of AP1, AP2, . . . , APn−1, APn.
Thus, the bias voltage supplied to each amplifier is, in a sense, a voltage divided according to the wiring resistance of the bias voltage supply line BL2, the short line SL, and the bias voltage supply line BL1; the bias voltage having the largest voltage value is supplied to APn; and the bias voltage supplied to AP decreases in the order of APn−1, APn−2, . . . , AP2, AP1. According to these bias voltages, as to the output delays of AP1 to APn, that of APn is the smallest, and the output delay increases in the order of APn−1, APn−2, . . . , AP2, AP1. Meanwhile, as to the transmission delays on the external lines U1 to Un respectively connected to the amplifiers AP1 to APn, that on the external line Un is the largest, and the transmission delay decreases in the order of Un−1, Un−2, . . . , U2, U1 as mentioned previously.
Therefore, the application timings of the pixel drive voltages G1 to Gn that are applied to the source lines D1 to Dn via the amplifiers AP1 to APn and the external lines U1 to Un respectively become the same. That is, the bias voltage supply lines BL1 and BL2 are laid out in such a way that the respective lengths thereof from the terminal T3 to the AP1 to APn are ranked from longest to shortest in the order of AP1, AP2, . . . , APn−2, APn−1, APn so that a higher bias voltage is supplied to the amplifier AP connected to the external line U having a longer length.
As such, by making the output delay of the amplifier AP connected to the external line U having a longer length smaller, the differences between the transmission delays on the external lines U1 to Un are reduced. With this configuration, over the entire region of the two-dimensional screen that the source lines D1 to Dn are in charge of, image display of high quality without display unevenness can be performed.
Or, as shown in FIGS. 6 and 7, the source driver 3 may be placed along the right end side of the display device 20. In this case, as shown in FIG. 6, as to the lengths of the external lines U1 to Un connecting the output amplifier circuit 134 and the source lines D1 to Dn, that of the external line located at the right end of one side of the display device 20 is the shortest, and when going toward the left end, the length of the external line becomes longer. In an example shown in FIG. 6, from among the external lines U1 to Un, the external line Un placed at the right end is the shortest in length, and the external line U1 placed at the left end is the longest in length. Thus, also as to the wiring resistances of U1 to Un, that of the external line located at the right end of one side of the display device 20 is smaller, and when going toward the left end, the wire resistance of the external line becomes larger. Therefore, as to the transmission delays on the external lines U1 to Un, that on U1 is the largest, and the transmission delay decreases in the order of U2, U3, . . . , Un−1, Un.
As such, where the source driver 3 is located along the right end side of the display device 20, the drive control part 1 supplies the bias supply line setting signal BSS designating the L-slew mode (third mode) to the bias voltage supply line setting part 40.
The bias voltage supply line setting part 40, according to this bias supply line setting signal BSS designating the L-slew mode, supplies switch switching signals to the bias voltage generating part 30 to apply, e.g., the largest voltage V1 as a bias voltage to the terminal T1 as the first terminal and to apply the voltage V4 smaller than the voltage V1 to the terminal T3 as the second terminal. Further, the bias voltage supply line setting part 40 supplies switch switching signals to short-circuit the terminals T2 and T4 to the bias voltage generating part 30. Thus, the switch 32 applies the voltage V4 onto the bias voltage supply line BL2 via the terminal T3. The switch 31 applies the voltage V1 as a bias voltage onto the bias voltage supply line BL1 via the terminal T1. The switches 35 and 36 short-circuits the terminals T2 and T4 via the short line SL.
Thus, in the L-slew mode, because the potential on the terminal T1 is at V1 and higher than the potential V4 on the terminal T3, a current flows in the direction from the terminal T1 via the terminals T2 and T4 toward the terminal T3 via the bias voltage supply line BL1, the short line SL, and the bias voltage supply line BL2.
The lengths of the bias voltage supply line (BL1, SL, BL2) from the terminal T1 to the respective bias voltage input terminals of the AP1 to APn are ranked from longest in the order of APn, APn−1, . . . , AP2, AP1. Accordingly, the wiring resistances are also ranked from highest in the order of APn, APn−1, . . . , AP2, AP1.
Thus, the bias voltage supplied to each amplifier is, in a sense, a voltage divided according to the wiring resistance of the bias voltage supply line BL1, the short line SL, and the bias voltage supply line BL2; the bias voltage having the largest voltage value is supplied to AP1; and the bias voltage supplied to AP decreases in the order of AP2, AP3, . . . , APn−1, APn. According to these bias voltages, as to the output delays of AP1 to APn, that of AP1 is the smallest, and the output delay increases in the order of AP2, AP3, . . . , APn−1, APn. Meanwhile, as to the transmission delays on the external lines U1 to Un respectively connected to the amplifiers AP1 to APn, that on the external line U1 is the largest, and the transmission delay decreases in the order of U2, U3, . . . , Un−1, Un as mentioned previously.
Therefore, the application timings of the pixel drive voltages G1 to Gn that are applied to the source lines D1 to Dn via the amplifiers AP1 to APn and the external lines U1 to Un respectively become the same. That is, the bias voltage supply lines BL1 and BL2 are laid out in such a way that the respective lengths thereof from the terminal T1 to the AP1 to APn are ranked from longest to shortest in the order of APn, APn−1, . . . , AP3, AP2, AP1 so that a higher bias voltage is supplied to the amplifier AP connected to the external line U having a longer length.
As such, by making the output delay of the amplifier AP connected to the external line U having a longer length smaller, the differences between the transmission delays on the external lines U1 to Un are reduced. With this configuration, over the entire region of the two-dimensional screen that the source lines D1 to Dn are in charge of, image display of high quality without display unevenness can be performed.
Although in the above embodiment, in the V-slew mode, the potentials on the terminals T3 and T1 are set at V1, and the potentials on the terminals T4 and T2 are set at V8, not being limited to this, the potentials on the terminals can be set according to the differences between the transmission delays as needed. Where the differences between the transmission delays are small, for example, by setting the potentials on the terminals T3 and T1 at V4 and the potentials on the terminals T4 and T2 at V5, the differences between the output delays of the amplifiers are made smaller, so that image unevenness can be suppressed more precisely. Likewise, also in the R-slew mode and L-slew mode, by setting the potentials on the terminals T3 and T1 according to the differences between the transmission delays as needed, image unevenness can be suppressed more precisely.
Where the voltage generating part 37 cannot generate desired bias voltages in the V-slew mode, a bias voltage amplifier may be provided to amplify bias voltages which the voltage generating part 37 applies to the terminals T3 and T4.
For example, as shown in FIG. 8, a first bias voltage amplifier 52 is provided between the bias voltage supply line BL2 and the terminal T3, and a second bias voltage amplifier 51 is provided between the bias voltage supply line BL1 and the terminal T1.
To sum up, the first and second bias voltage supply lines BL1 and BL2 are laid out in such a way that the longer the length of the external line U connected to any of the amplifiers AP belonging to the APQ+1 to APn (the first amplifier group) and the AP1 to APQ (the second amplifier group) is, the shorter the length of the BL1 and BL2 from the terminal to which a bias voltage is applied from among the first and third terminals to the amplifier is.
This application is based on a Japanese Patent application No. 2014-042363 which is hereby incorporated by reference.

## Claims

1. A driving device for driving a display device, comprising:
a source driver that applies pixel drive voltages respectively denoting luminance levels of pixels to a plurality of source lines of the display device via external lines respectively, wherein said source driver includes:
a plurality of amplifiers provided correspondingly to the plurality of source lines respectively and configured to generate said pixel drive voltages, each of the plurality of amplifiers having a control terminal and an output terminal with one of said external lines connected thereto, said each amplifier being configured to output one of the generated pixel drive voltages to the one external line via the output terminal and to operate with a transition speed based on a voltage supplied thereto via the control terminal;
a bias voltage supply line having its opposed ends that are respectively a first end and a second end; and
a bias voltage generating part that generates a bias voltage and supplies said bias voltage across said opposed ends so that said first end has a voltage higher than a voltage than at said second end,
wherein for each of said amplifiers, said bias voltage supply line is connected to the control terminal of said each amplifier so that the longer a length of the external line connected to the output terminal of said each amplifier is, the shorter a length of said bias voltage supply line between the control terminal of said each amplifier and said first end of the bias voltage supply line is, and
wherein an external line at one side of the display is the shortest, and each of said external lines are longer in length as they approach the other side of the display.

2. The driving device for a display device according to claim 1, wherein an operating current of each of the plurality of the amplifiers varies in accordance with the voltage supplied to the control terminal of said each amplifier.

3. The driving device for a display device according to claim 1, wherein a bias voltage amplifier amplifying said bias voltage is provided between said first end and an output of said bias voltage generating part.

4. A driving device for a display device, comprising:
a source driver that applies pixel drive voltages respectively denoting luminance levels of pixels to a plurality of source lines of the display device via external lines respectively, wherein said source driver includes:
a first group of amplifiers provided corresponding to source lines in charge of the left region of a two-dimensional screen of said display device from among the plurality of source lines and that generate first pixel drive voltages for said left region of said pixel drive voltages to send onto first external lines for said left region of said external lines respectively;
a second group of amplifiers provided corresponding to source lines in charge of the right region of the two-dimensional screen of said display device from among the plurality of source lines and that generate second pixel drive voltages for said right region of said pixel drive voltages to send onto second external lines for said right region of said external lines respectively;
a bias voltage generating part that generates a bias voltage for controlling output delays of said first and second groups of amplifiers;
a first bias voltage supply line to supply therethrough said bias voltage to said first group of amplifiers; and
a second bias voltage supply line to supply therethrough said bias voltage to said second group of amplifiers,
wherein said bias voltage generating part has a first terminal connected to one end of said first bias voltage supply line, a second terminal connected to the other end thereof, a third terminal connected to one end of said second bias voltage supply line, and a fourth terminal connected to the other end thereof,
wherein in a first mode, said bias voltage is applied to said first terminal and said third terminal, and simultaneously a voltage lower than said bias voltage is applied to said second terminal and said fourth terminal, and in a second mode, with said second terminal and said fourth terminal being short-circuited, said bias voltage is applied to said first terminal, and simultaneously a voltage lower than said bias voltage is applied to said third terminal, and in a third mode, with said second terminal and said fourth terminal being short-circuited, said bias voltage is applied to said third terminal, and simultaneously a voltage lower than said bias voltage is applied to said first terminal, and
wherein the longer the length of said external line connected to any of said amplifiers is, the shorter the length of said first and second bias voltage supply lines connecting a terminal to which said bias voltage is applied from among said first and third terminals and an input terminal of said amplifier is, and
wherein an external line at one side of the display is the shortest, and each of said external lines are longer in length as they approach the other side of the display.

5. The driving device for a display device according to claim 4, wherein the higher said bias voltage is, the smaller the output delays of said amplifiers are.

6. The driving device for a display device according to claim 4, wherein a bias voltage amplifier part to amplify said bias voltage is provided between each of said first and third terminals and said one end of said bias voltage supply line.