# Patent

## Title
Current sampling circuit and method

## Abstract

Disclosed is a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit, specifically the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current. Further disclosed is a current sampling method.

## Background
TECHNICAL FIELD
The present disclosure relates to current sampling techniques in the field of circuit design, and in particular to a current sampling circuit and method.
BACKGROUND
In related arts, implementation of a highly accurate current sampling circuit is as shown in FIG. 1, the current sampling circuit includes a power transistor M1, sampling transistors M2 and M3, and a close loop negative feedback circuit consisting of an operational amplifier, a transistor M4 and resistors R1, R2; wherein R1=R2, I1 and I2 are bias currents providing a quiescent operating point of the close loop negative feedback circuit, and the gain of the close loop negative feedback circuit is:

Afeedback=Aop·gm4Ro 

In the current sampling circuit as shown in FIG. 1, the current in the power transistor M1 is firstly mirrored into the sampling transistors M2 and M3, after passing through the close loop negative feedback circuit consisting of the operational amplifier, the transistor M4 and the resistors R1 and R2, the mirrored current is output as a sampling current. In the above current sampling circuit, the clamping effect of the operational amplifier is used to ensure that a first input voltage Vn is equal to a second input voltage Vp so that the output sampling current Iout is the same as the current flowing through the sampling transistors M2 and M3, thereby the current in the power transistor M1 can be sampled stably and accurately; if the current in the power transistor M1 changes direction, the output sampling current also changes direction, thereby implementing accurate sampling of current in both directions.
The current sampling scheme in the related arts has the following disadvantages: 1) it is disadvantageous for applications in large-scale circuits having a high integration density; 2) the current sampling circuit is not energy-saving due to its high power consumption.
SUMMARY
Embodiments of the disclosure are intended to provide a current sampling circuit that has an integrated circuit structure, a low power consumption and a low cost and can output a stable and accurate sampling current, and a corresponding current sampling method.
The technical solutions of the disclosure are implemented as follows.
An embodiment of the disclosure provides a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit,
specifically, the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and
the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
In the above solution, the power device may be implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor (LDNMOS);
the proportional current output circuit may include a second LDNMOS, a third LDNMOS, a fourth LDNMOS and a fifth LDNMOS; and
the full differential common mode negative feedback circuit may include a first P-channel Metal-Oxide-Semiconductor (PMOS), a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, a third reference current source, a fourth reference current source, and a fifth reference current source.
In the above solution, in the proportional current output circuit, the drain of the second LDNMOS is connected with the drain of the fourth LDNMOS and a power supply, the gate of the second LDNMOS is connected with the gate of the first LDNMOS, the gate of the third LDNMOS and a gate driving voltage (hdrv_in from a gate driving circuit), the source of the second LDNMOS is connected respectively with the drain of the third LDNMOS and the drain of the fifth LDNMOS; the source of the third LDNMOS is connected respectively with the source of the first LDNMOS and a first end of the first reference current source; the gate of the fourth LDNMOS is connected with the gate of the fifth LDNMOS, the source of the fourth LDNMOS is connected respectively with the source of the first PMOS and the source of the third PMOS in the full differential common mode negative feedback circuit; the source of the fifth LDNMOS is connected respectively with the source of the second PMOS and the source of the fourth PMOS in the full differential common mode negative feedback circuit;
in the full differential common mode negative feedback circuit, the gate of the first PMOS is connected with the gate of the second PMOS, the drain of the first PMOS is connected respectively with a first end of the first resistor, the gate of the fourth PMOS and a first end of the third reference current source; the drain of the second PMOS is connected respectively with a first end of the second resistor, the gate of the third PMOS and a first end of the fourth reference current source; the drain of the third PMOS is connected with a first end of the second reference current source; the drain of the fourth PMOS is connected with the fifth reference current source; a second end of the first resistor is connected respectively with a second end of the second resistor, the gate of the first PMOS and the gate of the second PMOS; second ends of the first reference current source, the second reference current source, the third reference current source, the fourth reference current source and the fifth reference current source are all connected to a ground point; and
the drain of the first LDNMOS is connected to the power supply.
Based on the above current sampling circuit, an embodiment of the disclosure further provides a current sampling method, and the method includes:
a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current; and
the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
In the above solution, the step that a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current may include:
a ratio between the current output from the power device and the preset proportion is calculated, and an obtained ratio is taken as a current value of a proportional branch;
the first proportional current and the second proportional current are determined according to the current value of the proportional branch.
In the above solution, the step that the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current may include:

    
    
        the first sampling current Isense+ and the second sampling current Isense− are obtained from the following formula:

Isense+=IJ1−Ib 

Isense−=IJ2−Ib 

    
    


where IJ1 is the first proportional current, IJ2 is the second proportional current, and Ib is the bias current in microamps provided by the full differential common mode negative feedback network.
Compared to the related arts, the current sampling circuit and method provided by the embodiments of the disclosure have the following advantages:
1) in the embodiments of the disclosure, a full differential common mode negative feedback circuit including four PMOSs and two resistors is used to replace a close loop negative feedback circuit including transistors and an operational amplifiers, in this way, it can be ensured that the full differential common mode negative feedback network has a gain larger than 60 dB, generally between 70 to 88 dB, and the higher the gain is, the more a stable sampling current output can be ensured, thereby implementing a stable sampling current out; in addition, the structure of the full differential common mode negative feedback circuit according to the embodiments of the disclosure is simpler when compared to that of the close loop negative feedback circuit in th related arts; and a sampling current output from the full differential common mode negative feedback circuit is only related to dimensions of a transistor and not affected by process variations, thus an accurate sampling current can be output;
2) compared to its counterparts in the related arts, the full differential common mode negative feedback circuit according to the embodiments of the disclosure has a higher integration density, occupies smaller pattern area and has lower cost; and
3) the full differential common mode negative feedback circuit according to the embodiments of the disclosure requires a smaller bias current that is in microamps and generally of 10-20 μA, thus its power consumption is reduced greatly.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic structural diagram of a current sampling circuit in related arts of an embodiment of the disclosure;
FIG. 2 is a schematic structural diagram of a current sampling circuit according to an embodiment of the disclosure;
FIG. 3 is a schematic structural diagram of a current sampling circuit during practical application of an embodiment of the disclosure;
FIG. 4 is an equivalent structural diagram of a full differential common mode negative feedback network according to an embodiment of the disclosure;
FIG. 5 is a schematic structural diagram of a folding current sampling circuit according to an embodiment of the disclosure; and
FIG. 6 is a flow chart of a current sampling method according to an embodiment of the disclosure.



DETAILED DESCRIPTION
During implementation of the present application, the applicant finds that current sampling schemes in related arts include at least the following disadvantages:
1) in the above current sampling circuit, in order to provide a main gain of the close loop negative feedback circuit, it is required to add an error amplifier or a adjustment transistor to the clamp of the operational amplifier, thus a close loop negative feedback circuit including the operational amplifier and the error amplifier or the adjustment transistor is intended to occupy too much pattern area, and required overheads of pattern area is higher, therefore, the above current sampling circuit is disadvantageous for applications in large-scale circuits having a high integration density; and
2) in the above current sampling circuit, the close loop negative feedback circuit requires large bias currents I1 and I2 in amps or milliamps, thus the above current sampling circuit consumes more power and is disadvantageous for the energy-saving development trend.
In an embodiment of the disclosure, a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current; and the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
Specific embodiments of the disclosure will be further elaborated below with reference to the drawings.
An embodiment of the disclosure provides a current sampling circuit for sampling current of a power device, as shown in FIG. 2, the current sampling circuit includes a proportional current output circuit 201 and a full differential common mode negative feedback circuit 202,
specifically, the proportional current output circuit 201 is configured to calculate a current output from a power device according to a preset proportion to obtain a proportional current, and to output the proportional current to the full differential common mode negative feedback circuit 202; and
the full differential common mode negative feedback circuit 202 is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
Herein, the power device may be implemented by a Negative channel Metal Oxide Semiconductor (NMOS), a Positive channel Metal Oxide Semiconductor (PMOS), a Lateral Diffusion NMOS (LDNMOS), a Lateral Diffusion PMOS (LDPMOS), and a PNP transistor or an NPN transistor that has power output function; preferably, the embodiment of the disclosure is implemented by an LDNMOS, and a first LDNMOS M1 shown in FIG. 3 is namely a power device.
Specific structures of the proportional current output circuit 201 and of the full differential common mode negative feedback circuit 202 will be elaborated below based on the current sampling circuit shown in FIG. 3 from a practical application perspective.
the proportional current output circuit 201 includes a second LDNMOS M2, a third LDNMOS M3, a fourth LDNMOS M4 and a fifth LDNMOS M5; and
The full differential common mode negative feedback circuit 202 includes a first
PMOS M6, a second PMOS M7, a third PMOS M8, a fourth PMOS M9, a first resistor R1, a second resistor R2, a second reference current source I2, a third reference current source I3, a fourth reference current source I4, and a fifth reference current source I5.
Herein transistors M2, M3, M4, M5 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M1, with a gate voltage being a gate driving voltage (hdrv_in output from a gate driving circuit), thus respective transistors operate in the linear region and are equivalent to resistors, and the maximum withstanding voltage of each of the transistors M1, M2, M3, M4, M5 is 18V.
Herein transistors M6, M7, M8, M9 in the full differential common mode negative feedback circuit 202 are implemented by a PMOS transistor with a maximum withstanding voltage of 20V.
Herein transistors in the full differential common mode negative feedback circuit 203 can also be implemented, as required, by NMOS, NPN or PNP transistors.
Further, the connection relation of respective devices in the current sampling circuit according to the embodiment of the disclosure is elaborated with reference to FIG. 2.
in the proportional current output circuit 201, the drain of the second LDNMOS M2 is connected with the drain of the fourth LDNMOS M4 and a power supply Vin, the gate of the second LDNMOS M2 is connected with the gate of the first LDNMOS M1, the gate of the third LDNMOS and an output hdrv_in of a gate driving circuit (namely driven by a voltage signal output from the gate driving circuit), the source of the second LDNMOS M2 is connected respectively with the drain of the third LDNMOS M3 and the drain of the fifth LDNMOS M5; the source of the third LDNMOS M3 is connected respectively with the source of the first LDNMOS M1 and one end of the first reference current source I1; the gate of the fourth LDNMOS M4 is connected with the gate of the fifth LDNMOS M5, the source of the fourth LDNMOS M4 is connected respectively with the source of the first PMOS M6 and the source of the third PMOS M8 in the full differential common mode negative feedback circuit 202; the source of the fifth LDNMOS M5 is connected respectively with the source of the second PMOS M7 and the source of the fourth PMOS M9 in the full differential common mode negative feedback circuit 202;
in the full differential common mode negative feedback circuit 202, the gate of the first PMOS M6 is connected with the gate of the second PMOS M7, the drain of the first PMOS M6 is connected with one end of the first resistor R1, the gate of the fourth PMOS M9 and one end of the third reference current source I3; the drain of the second PMOS M7 is connected with one end of the second resistor R2, the gate of the third PMOS M8 and one end of the fourth reference current source I4; the drain of the third PMOS M8 is connected with one end of the second reference current source I2; the drain of the fourth PMOS M9 is connected with the fifth reference current source I5; the other end of the first resistor R1 is connected respectively with the other end of the second resistor R2, the gate of the first PMOS M6 and the gate of the second PMOS M7; the other ends of the first reference current source the second reference current source I2, the third reference current source I3, the fourth reference current source I4 and the fifth reference current source I5 are all connected to a ground point;
the drain of the first LDNMOS M1 is connected to the power supply Vin.
In the embodiment of the disclosure, based on the above circuit structure and connection relation between devices, the operation principle of the current sampling circuit is as follows.
Firstly, the power device, i.e., a first LDNMOS M1 outputs Ipower to the proportional current output circuit 201, the proportional current output circuit 201 calculates the output current Ipower according to a preset proportion to obtain a first proportional current and a second proportional current and outputs them to the full differential common mode negative feedback circuit 202.
Herein, the gate voltage of the transistors M1, M2, M3, M4, M5 are driven by hdrv_in, thus these transistors operate in the linear region and are equivalent to resistors, and each of the transistors M1, M2, M3, M4, M5 has a maximum withstanding voltage of 18 V since the voltage Vin input by the power supply has a maximum value of 18 V.
Herein, the conductance of a transistor




  
    G
    =
    
      
        
          μ
          ·
          
            C
            ox
          
          ·
          
            W
            L
          
        
        ⁢
        
          (
          
            
              V
              gs
            
            -
            
              V
              th
            
            -
            
              V
              ds
            
          
          )
        
      
      ≈
      
        W
        L
      
    
  
  ,




where μ·Cox is a constant factor of the transistor, Vgs is a gate-source voltage of the transistor, Vth is a threshold voltage of the transistor, Vds is a drain-source voltage of the transistor, W is the width of the channel, L is the length of the channel; since the conductance of the transistor





  
    G
    ≈
    
      W
      L
    
  
  ,




the conductance G of the transistor can be adjusted by setting the width and the length of the channel of the transistor; in the embodiment of the disclosure, for conductance of M1, M2, M3, M4, M5, it is preset that G1=X×G2=X×G3; G2=G3=Y×G4=Y×G5, where X and Y are preset constants of proportionality.

Specifically, the proportional current output circuit 201 firstly calculates the output current Ipower according to the preset proportion to obtain:




  
    
      
        
          
            I
            power
          
          /
          
            I
            
              s
              ⁢
              
                
              
              ⁢
              1
            
          
        
        =
        
          
            
              (
              
                
                  1
                  
                    G
                    2
                  
                
                +
                
                  1
                  
                    G
                    3
                  
                
              
              )
            
            /
            
              (
              
                1
                
                  G
                  1
                
              
              )
            
          
          =
          
            2
            ⁢
            X
          
        
      
    
    
      
        (
        1
        )
      
    
  




where Is1 is the value of current flowing through the transistor M2, and





  
    1
    
      G
      1
    
  
  ,
  
    1
    
      G
      2
    
  
  ,
  
    1
    
      G
      3
    
  




are resistances of the transistors M1, M2, M3 respectively;

then the obtained current Is1 is output to drains of transistors M3, M5 so as to obtain a first proportional current IJ1 flowing through the transistor M4 and a second proportional current IJ2 flowing through the transistor M5, the first proportional current IJ1 is output to sources of the transistors M6 and M8 in the full differential common mode negative feedback circuit 202, and the second proportional current IJ2 is output to sources of the transistors M7 and M9 in the full differential common mode negative feedback circuit 202; the transistors M4 and M5 have an effect of isolating a high voltage, thus it is possible to prevent breakdown of the full differential common mode negative circuit 202 by the high voltage.
Finally, the full differential common mode negative feedback circuit 202 is in the form of a full differential common mode negative feedback network consisting of transistors M6, M7, M8, M9, resistors R1, R2, the second reference current source I2, a third reference current source I3, a fourth reference current source I4, and a fifth reference current source I5, and the third reference current source and the fourth reference current source are used to provide the full differential common mode negative feedback network with a bias current Ib in microamps; the first proportional current IJ1 and the second proportional current IJ2 are shunted respectively to obtain a first sampling current Isense+ and a second sampling current Isense−.
where IJ1=Isense++I3, IJ2=Isense−+I4, Isense+ is a current flowing through the transistor M8, Isense− is a current flowing through the transistor M9, I3 is a current flowing through the third reference current source, I4 is a current flowing through the fourth reference current source, and I3=I4=Ib, where Ib is a benchmark bias current providing the transistors M6, M7 with a quiescent operating point and as low as 10 to 20 μA, thus compared to the current sampling circuit in related arts, the current sampling circuit according to the embodiment of the disclosure has a greatly-reduced power consumption.
In above embodiments of the disclosure, the full differential common mode negative feedback network is equivalent to a negative feedback network including an operational amplifier, as shown in FIG. 4; wherein a circuit consisting of transistors M6, M7 and resistors R1, R2 is equivalent to an operational amplifier, points C and D are taken as inputs of the operational amplifier, and the two sampling currents are taken approximately as being connected to the input and output of the operational amplifier. Due to the clamping effect of the operational amplifier, its inputs C and D have a same voltage, the first sampling current Isense+ from the output is fed back to the input C of the operational amplifier via the transistor M8, the second sampling current Isense− from the output is fed back to the input D of the operational amplifier via the transistor M9, thus an effect of an operational amplifier feedback network is resulted, and it is possible to provide the current sampling circuit with a stable gain, therefore, the current sampling circuit according to the embodiment of the disclosure occupies smaller pattern area, has a higher integration density and lower cost.
Herein, when a current flowing through the transistor M1 is downwards, a forward first sampling current Isense++ will flow through a branch where the transistor M8 is located, and a reverse second sampling current Isense− of 0 will flow through the transistor M9; on the contrary, when the current flowing through the transistor M1 is upwards (i.e., reverse), the forward first sampling current of 0 will flow through the branch where the transistor M8 is located, and the reverse second sampling current Isense− will flow through the transistor M9, and Isense+=Isense−, thus two branches operate separately and there is no interference therebetween, thereby implementing current sampling in both directions.
How to obtain the forward first sampling current Isense+ in an embodiment of the disclosure will be elaborated below by taking current sampling in a forward direction as an example, KVL (Kirchhoff's Voltage Law) equations obtained from point A to point G are as follows.




  
    
      
        
          
            
              I
              
                J
                ⁢
                
                  
                
                ⁢
                1
              
            
            *
            
              (
              
                1
                
                  G
                  4
                
              
              )
            
          
          +
          
            V
            
              s
              ⁢
              
                
              
              ⁢
              g
              ⁢
              
                
              
              ⁢
              6
            
          
        
        =
        
          
            
              I
              
                s
                ⁢
                
                  
                
                ⁢
                1
              
            
            *
            
              (
              
                1
                
                  G
                  2
                
              
              )
            
          
          +
          
            
              I
              b
            
            ⁡
            
              (
              
                1
                
                  G
                  5
                
              
              )
            
          
          +
          
            V
            
              sg
              ⁢
              
                
              
              ⁢
              7
            
          
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          V
          
            sg
            ⁢
            
              
            
            ⁢
            6
          
        
        =
        
          V
          
            sg
            ⁢
            
              
            
            ⁢
            7
          
        
      
    
    
      
        (
        3
        )
      
    
  
  
    
      
        
          I
          
            J
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            I
            b
          
          +
          
            I
            
              sense
              +
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




where Vsg6 is a gate-source voltage of the transistor M6, Vsg7 is a gate-source voltage of the transistor M7; it can be obtained from equations (1), (2), (3) and (4):




  
    
      I
      
        sense
        +
      
    
    =
    
      
        
          I
          
            s
            ⁢
            
              
            
            ⁢
            1
          
        
        *
        
          (
          
            
              G
              4
            
            
              G
              2
            
          
          )
        
      
      =
      
        
          
            I
            
              s
              ⁢
              
                
              
              ⁢
              1
            
          
          /
          Y
        
        =
        
          
            I
            power
          
          /
          
            (
            
              2
              ⁢
              
                
              
              ⁢
              XY
            
            )
          
        
      
    
  
  ;




it can be seen that the first sampling current Isense+ in the embodiment of the disclosure is only related to the width and length of a transistor and not affected by process variations, thus a sampling current with improved accuracy can be obtained.
In the embodiment of the disclosure, the method for calculating the reverse second sampling current Isense− is similar to the method for calculating the forward first sampling current Isense+; and the reverse second sampling current is equal to the forward first sampling current, i.e., the second sampling current Isense−=Ipower/(2XY), thus duplicated content thereof will be omitted.
In practical applications, the proportional current output circuit 201 and the full differential common mode negative feedback circuit 202 can be applied to a charger chip of a power supply management chip.
The current sampling circuit in the embodiment of the disclosure can also be of a folding structure, the folding current sampling circuit has a similar principle as that of the above current sampling circuit, and it has flexible applications, as shown in FIG. 5, the current sampling circuit includes a proportional current output circuit 501 and a full differential common mode negative feedback circuit 502;
specifically, the proportional current output circuit 501 includes a second LDNMOS M2, a third LDNMOS M3, a fourth LDNMOS M4, a fifth LDNMOS M5, a sixth LDNMOS M6, a seventh LDNMOS M7, and a eighth LDNMOS M8;
the full differential common mode negative feedback circuit 502 includes a first PMOS M9, a second PMOS M10, a third PMOS M11, a fourth PMOS M12, a fifth PMOS M13, a sixth PMOS M14, a first resistor R1, a second resistor R2, a second reference current source I2, a third reference current source I3, a fourth reference current source I4, a ninth NMOS M19, a tenth NMOS M20, a eleventh NMOS M21, a twelfth NMOS M22, a thirteenth NMOS M23, and a fourteenth NMOS M24;
Herein, transistors M2, M3, M4, M5, M6, M7, M8 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M1, with a gate voltage being a gate driving voltage hdrv_in, thus respective transistors operate in the linear region and are equivalent to resistors, and each of the transistors is implemented by a transistor with the maximum withstanding voltage of 18 V.
Herein, voltages of transistors M9, M10, M11, M12, M13, M14 in the full differential common mode negative feedback circuit are all maintained at a voltage of 20 V; voltages of transistors M19, M20, M21, M22, M23, M24 can be adjusted appropriately to ensure a benchmark bias current Ib desired in the full differential common mode negative feedback circuit 502, and the benchmark bias current Ib providing M10, M11 with a quiescent operating point is as low as 10 to 20 μA.
Herein, transistors in the full differential common mode negative feedback circuit 502 can also be implemented, as required, by NMOS, NPN or PNP transistors.
The connection relation of respective devices in the folding current sampling circuit according to the embodiment of the disclosure is elaborated below with reference to FIG. 5.
in the proportional current output circuit 501, the drain of the transistor M2 is connected with a power supply Vin, the gate of the transistor M2 is connected with the gate of the transistor M1, the gate of the transistor M3, the gate of the transistor M4, the gate of the transistor M5 and a driving voltage hdrv_in, the source of the transistor M2 is connected with the drain of the transistor M3 and the drain of the transistor M6 in a current mirror circuit 502; the source of the transistor M3 is connected with the source of the transistor M4 and one end of the first reference current source I1; the gate of the transistor M6 is connected with the gate of the transistor M7 and the gate of transistor M8, the source of the transistor M6 is connected with the source of the transistor M9 and the source of the transistor M13 in the full differential common mode negative feedback circuit 502; the source of the transistor M7 is connected with the source of the transistor M10 and the source of the transistor M11 in the full differential common mode negative feedback circuit 502; the source of the transistor M8 is connected with the source of the transistor M12 and the source of the transistor M14 in the full differential common mode negative feedback circuit 502;
in the full differential common mode negative feedback circuit 502, the drain of the transistor M9 is connected with the source of the transistor M21 and the drain of the transistor M22, the gate of the transistor M9 is connected with the gate of the transistor M10, the gate of the transistor M11 and the gate of the transistor M12; the drain of the transistor M10 is connected with the resistor R1 and the drain of the transistor M21; the drain of the transistor M11 is connected with the resistor R2 and the drain of the transistor M23; the drain of the transistor M12 is connected with the source of the transistor M23 and the drain of the transistor M24; the drain of the transistor M13 is connected with one end of the second reference current source I2; the drain of the transistor M14 is connected with one end of the fourth reference current source I4, the gate of the transistor M13 is connected with the drain of the transistor M21; the gate of the transistor M19 is connected with the gate of the transistor M21, the drain of the transistor M19 is connected with the gate of the transistor M21, the gate of the transistor M23 and one end of the third reference current source I3, the drain of the transistor M19 is connected with the drain of the transistor M20, the gate of the transistor M22 and the gate of the transistor M24; the source of the transistor M20 is connected to the a ground point, the gate of the transistor M20 is connected with the gate of the transistor M22 and the gate of the transistor M24; the source of the transistor M21 is connected with the drain of the transistor M9 and the drain of the transistor M22; the source of the transistor M22 is connected to the ground point; the source of the transistor M23 is connected with the drain of the transistor M12 and the drain of the transistor M24; the source of the transistor M24 is connected to the ground point; other ends of the first reference current source I1, the second reference current source I2, and the fourth reference current I4 source are connected to the ground point; the other end of the third reference current source I3 is connected with the power supply VDD;
the drain of the transistor M1 is connected to the power supply
In the above embodiment of the disclosure, the current of the transistor M1 in the folding current sampling circuit is scaled twice through the proportional current output circuit 501, the output current becomes smaller than that of the above current sampling circuit, thus the power consumption is lowered further; the transistors M10, M11, M13, M14, the first resistor R1 and the second resistor constitute a full differential common mode negative feedback network; the transistors M9, M20, M21, M22, M23, M24 constitute a folding structure, and the folding current sampling circuit according to the embodiment of the disclosure can meet application demand in low voltage field.
In the embodiments of the disclosure, current sampling circuits shown in FIG. 2, 3 or 5 can be applied in devices or apparatuses that need current sampling.
Based on same technical ideas, an embodiment of the disclosure further provides a current sampling method, since the principle of the method is similar to that of the current sampling circuit, for the implementation of the method and its principle, please refer to the implementation of the circuit and its corresponding principle, and duplicated content thereof will be omitted.
As shown in FIG. 6, the current sampling method provided by the embodiment of the disclosure includes:
step S601, a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current;
specifically, firstly, a ratio between the current output from the power device and the preset proportion is calculated according to Is1=Ipower/2X, and an obtained ratio is taken as a current value of a proportional branch; then the first proportional and the second proportional current are determined according to the current value of the proportional branch;
where Ipower is the current output from the power device; Is1 is the current value of the proportional branch, and 2X is the preset proportion.
Step S602, the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
Specifically, the first sampling current Isense+ and the second sampling current Isense− obtained from the following formula:

Isense+=IJ1−Ib 

Isense−=IJ2−Ib 

where IJ1 is the first proportional current, IJ2 is the second proportional current, and Ib is the bias current in microamps provided by the full differential common mode negative feedback network.
Although only preferable embodiments of the disclosure are described, once those skilled in the art know the basic inventive concept, they can make other modifications and changes to these embodiments. Thus the accompanying claims are intended to include preferable embodiments and all changes and modifications within the scope of protection of the disclosure.
It is obvious that various changes and variations can be made by those skilled in the art without departing from the spirit and scope of the disclosure. In this way, if these modifications and variations fall within the scope of the claims and equivalent techniques, the disclosure is intended to include these changes and variations.

## Claims

1. A current sampling circuit, comprising: a proportional current output circuit and a full differential common mode negative feedback circuit,
the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and
the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current; and
wherein the power device is implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor (LDNMOS);
the proportional current output circuit comprises a second LDNMOS, a third LDNMOS, a fourth LDNMOS and a fifth LDNMOS; and
the full differential common mode negative feedback circuit comprises a first P-channel Metal-Oxide-Semiconductor (PMOS), a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, a third reference current source, a fourth reference current source, and a fifth reference current source; and
wherein in the proportional current output circuit, the drain of the second LDNMOS is connected with the drain of the fourth LDNMOS and a power supply, the gate of the second LDNMOS is connected with the gate of the first LDNMOS, the gate of the third LDNMOS and a gate driving voltage, the source of the second LDNMOS is connected respectively with the drain of the third LDNMOS and the drain of the fifth LDNMOS; the source of the third LDNMOS is connected respectively with the source of the first LDNMOS and a first end of the first reference current source; the gate of the fourth LDNMOS is connected with the gate of the fifth LDNMOS, the source of the fourth LDNMOS is connected respectively with the source of the first PMOS and the source of the third PMOS in the full differential common mode negative feedback circuit; the source of the fifth LDNMOS is connected respectively with the source of the second PMOS and the source of the fourth PMOS in the full differential common mode negative feedback circuit;
in the full differential common mode negative feedback circuit, the gate of the first PMOS is connected with the gate of the second PMOS, the drain of the first PMOS is connected respectively with a first end of the first resistor, the gate of the fourth PMOS and a first end of the third reference current source; the drain of the second PMOS is connected respectively with a first end of the second resistor, the gate of the third PMOS and a first end of the fourth reference current source; the drain of the third PMOS is connected with a first end of the second reference current source; the drain of the fourth PMOS is connected with the fifth reference current source; a second end of the first resistor is connected respectively with a second end of the second resistor, the gate of the first PMOS and the gate of the second PMOS; second ends of the first reference current source, the second reference current source, the third reference current source, the fourth reference current source and the fifth reference current source are all connected to a ground point; and
the drain of the first LDNMOS is connected to the power supply.

2. A current sampling method, comprising:
calculating a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current; and
shunting respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and outputting constantly the first sampling current and the second sampling current;
wherein the shunting respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current comprises:
obtaining the first sampling current Isense+ and the second sampling current Isense− from the following formula:


Isense+=IJ1−Ib 



Isense−=IJ2−Ib−


where IJ1 is the first proportional current, IJ2 is the second proportional current, and Ib is the bias current in microamps provided by the full differential common mode negative feedback network.

3. The current sampling method according to claim 2, wherein the calculating a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current comprises:
calculating a ratio between the current output from the power device and the preset proportion, and taking an obtained ratio as a current value of a proportional branch;
determining the first proportional current and the second proportional current according to the current value of the proportional branch.