# Patent

## Title
Coulomb counting using analog-to-frequency conversion

## Abstract

In an analog-to-frequency converting circuit, a set of switches receive a first sense signal indicative of a current and provides a second sense signal that alternates between an original version of the first sense signal and a reversed version of the first sense signal, under control of a switching signal. An integral comparing circuit integrates the second sense signal to generate an integral value and generates a train of trigger signals. Each trigger signal is generated when the integral value reaches a preset reference. A compensation circuit compensates for the integral value with a predetermined value in response to each trigger signal. A control circuit generates the switching signal such that a time interval during which the second sense signal is the original version and a time interval during which the second sense signal is the reversed version are substantially the same.

## Background
BACKGROUND
A conventional method for counting charges passing in and out of a battery (referred to as “coulomb counting”) includes generating a sense voltage linearly proportional to a current (e.g., a charging current or a discharging current) of the battery, using a voltage-to-frequency converter to convert the sense voltage to a frequency signal linearly proportional to the sense voltage, and counting a number of waves/pulses of the frequency signal to generate a count value. The count value can represent an amount of accumulation of electric charges passing in and out of the battery.
FIG. 1 illustrates a circuit diagram of a conventional voltage-to-frequency converter 100. As shown in FIG. 1, the voltage-to-frequency converter 100 includes a sense resistor R′SEN, an integrator (e.g., a combined circuit of a resistor R′INT, an integrating capacitor C′INT, and an operational amplifier (OPA) 112; hereinafter, integrator (R′INT, C′INT, 112)), comparators 114 and 116, compensation circuitry (e.g., a combined circuit of capacitors CP1 and CP1, and switches M1-M8), and a control circuit 150.
The sense resistor R′SEN senses a battery current I′BAT of a battery 152 to generate a sense voltage V′SEN. The integrator (R′INT, C′INT, 112) integrates the sense voltage V′SEN to generate an integral result V′INT. The integral result V′INT represents an integral value of the sense voltage V′SEN, and therefore represents an integral value of the battery current I′BAT. The comparators 114 and 116 compare the integral result V′INT with voltage references V′H and V′L (V′L<V′H) to generate a train of pulse signals CMP′H and CMP′L. The control circuit 150 controls the switches M1-M8 according to the pulse signals CMP′H and CMP′L. A frequency f′CMP of the pulse signals CMP′H or CMP′L represents the battery current I′BAT.
By way of example, if the battery 152 is in a charging mode, then the sense voltage V′SEN labeled in FIG. 1 has a positive value, and the integral result V′INT decreases because of integration of the positive sense voltage V′SEN. When the integral result V′INT decreases to the voltage reference V′L, the comparator 116 generates a pulse signal CMP′L, and the control circuit 150 turns on a first group of switches M1, M4, M6 and M7, and turns off a second group of switches M2, M3, M5 and M8. Hence, the capacitor CP1 provides an amount of compensation charges Q′REF to the integrating capacitor C′INT through the inverting input terminal 154 of the OPA 112 to increase the integral result V′INT, and the capacitor CP2 is charged by the voltage V′REF to store an amount of compensation charges Q′REF. The increased integral result V′INT continues to decrease because of the integration of the positive sense voltage V′SEN. When the integral result V′INT decreases to the voltage reference V′L, the comparator 116 generates a next pulse signal CMP′L, and the control circuit 150 turns off the first group of switches and turns on the second group of switches. Hence, the capacitor CP2 provides the stored compensation charges Q′REF to the integrating capacitor C′INT through the terminal 154 to increase the integral result V′INT, and the capacitor CP1 is charged by the voltage V′REF to store an amount of compensation charges Q′REF. Thus, if the battery 152 is in a charging mode, then the control circuit 150 alternately turns on the first group of switches and the second group of switches, and the comparator 116 generates a train of pulse signals CMP′L at a frequency f′CMP that is linearly proportional to the charging current I′BAT. Similarly, if the battery 152 is in a discharging mode, then the control circuit 150 alternately turns a third group of switches M1, M2, M7 and M8 and a fourth group of switches M3, M4, M5 and M6, and the comparator 114 can generate a train of pulse signals CMP′H at a frequency f′CMP that is linearly proportional to the discharging current I′BAT. The frequency f′CMP of the trigger signals CMP′H/CMP′L can be used for the abovementioned coulomb counting.
However, the voltage-to-frequency converter 100 has some shortcomings. For example, the frequency f′CMP may have error caused by an input voltage offset V′OS of the OPA 112. Thus, a count value obtained by counting a number of the pulse signals CMP′H/CMP′L may have error caused by the input voltage offset V′OS.
Additionally, because the OPA 112 controls its inverting input terminal 154 and its non-inverting input terminal 156 to have the same voltage level, and the inverting input terminal 154 receives either a voltage level of V′REF or a voltage level of −V′REF from the capacitors CP1 and CP1, a voltage level at the non-inverting input terminal 156, which is also a terminal 156 of the sense resistor R′SEN, should be neither relatively high nor relatively low compared with the voltage levels V′REF and −V′REF. Because the voltage V′REF is relatively small compared with a voltage level at a positive terminal of the battery 152, the voltage level at the terminal 156 of the sense resistor R′SEN should be relatively small. Thus, the sense resistor R′SEN can be placed at the negative terminal of the battery 152 and cannot be placed at the positive terminal of the battery 152. In some situations, it would be beneficial to place the sense resistor R′SEN at the positive terminal of the battery 154. For example, there may be a thermistor (not shown) connected to the negative terminal of the battery 152 to measure temperature of the battery 152, and a sense resistor R′SEN placed at the negative terminal of the battery 152 may cause error in the measurement of the temperature. Placing the sense resistor R′SEN at the positive terminal of the battery 152 can avoid this error.
Moreover, the compensation circuitry in the voltage-to-frequency converter 100 uses two capacitors CP1 and CP1 to provide compensation charges to the integrator (R′INT, C′INT, 112). It would be beneficial to use one capacitor instead of two capacitors to provide compensation charges, so as to reduce the cost and size of the compensation circuitry.
Furthermore, when the capacitor CP1 provides compensation charges to the integrator (R′INT, C′INT, 112), the capacitor CP1 attempts to apply a voltage level V′REF or −V′REF to the inverting input terminal 154 of the OPA 112 that is different from a voltage level, e.g., zero volts, at the non-inverting input terminal 156 of the OPA 112. Because the OPA 112 controls the terminals 154 and 156 to have the same voltage level, a relatively big current may be generated by the OPA 112 to flow through the capacitors C′INT and CP1 to discharge the capacitor CP1, so as to reduce the voltage level V′REF or −V′REF of the capacitor CP1 to zero volts relatively quickly. This requires that the OPA 112 has a relatively high sensibility, and is able to generate and sustain a relatively big current. Such an OPA is relatively expensive and consumes relatively high power.
FIG. 2 illustrates a circuit diagram of a conventional coulomb counter 200. The coulomb counter 200 includes a sense resistor R′SEN, a counter 262, and a voltage-to-frequency converter. The voltage-to-frequency converter includes switches S1-S4, an integrator (e.g., a combined circuit of a resistor R′INT, a capacitor C′INT, and an operational amplifier OPA 212; hereinafter, integrator (R′INT, C′INT, 212)), an RC filter (including a resistor RFLT and a capacitor RFLT), comparators 214 and 216, and a control logic & polarity detection module 260.
The sense resistor R′SEN generates a sense voltage V′SEN1 indicative of a battery current I′BAT. The switches S1-S4 receive the sense voltage V′SEN1 and provide a voltage V′SEN2 to the integrator (R′INT, C′INT, 212). The integrator (R′INT, C′INT, 112) integrates the voltage V′SEN2 to generate an integral result V′INT. The integral result V′INT ramps up and down alternately, under control of the switches S1-S4. The comparators 214 and 216 compare the integral result V′INT with voltage references V′H and V′L (V′L<V′H) to generate trigger signals CMP′H and CMP′L, alternately. The module 260 controls the switches S1-S4 according to the trigger signals CMP′H and CMP′L such that the voltage V′SEN2 alternates between a voltage level of V′SEN1 and a voltage level of −V′SEN1. A frequency f′CMP at which the trigger signals CMP′H and CMP′L alternate represents the battery current I′BAT. The counter 262 counts a number of the trigger signals CMP′H and CMP′L to generate a count value representing an amount of accumulation of electric charges in the battery current I′BAT.
By way of example, in a situation when the battery current I′BAT flows through the sense resistor R′SEN from the terminal labeled “CS+” to the terminal labeled “CS−,” the sense voltage V′SEN1 labeled in FIG. 2 has a positive value. The module 260 can turn on the switches S1 and S4 and turn off the switches S2 and S3, and therefore the integrator (R′INT, C′INT, 212) integrates the voltage level of V′SEN1 to decrease the integral result V′INT. When the integral result V′INT decreases to the voltage reference V′L, the comparator 216 generates a trigger signal CMP′L, and the module 260 turns off the switches S1 and S4 and turns on the switches S2 and S3 in response to the trigger signal CMP′L. Hence, the integrator (R′INT, C′INT, 212) integrates the voltage level of −V′SEN1 to increase the integral result V′INT. When the integral result V′INT increases to the voltage reference V′H, the comparator 214 generates a trigger signal CMP′H, and the module 260 turns on the switches S1 and S4 and turns off the switches S2 and S3 in response to the trigger signal CMP′H. Thus, by alternately turning on the pair of switches S1 and S4 and the pair of switches S2 and S3 according to the trigger signals CMP′H and CMP′L, the coulomb counter 200 alternately generates the trigger signals CMP′H and CMP′L at an alternation frequency f′CMP that is linearly proportional to the battery current I′BAT. Similarly, when the battery current I′BAT flows through the sense resistor R′SEN from the terminal labeled “CS−” to the terminal labeled “CS+,” the coulomb counter 200 can also alternately generate trigger signals CMP′H and CMP′L at an alternation frequency f′CMP that is linearly proportional to the battery current I′BAT. The alternation frequency f′CMP can be used for coulomb counting.
However, the coulomb counter 200 has some shortcomings. For example, in a first time interval, the integrator (R′INT, C′INT, 212) can integrate a voltage level of V′SEN1 so that the integral result V′INT decreases from the voltage reference V′H to the voltage reference V′L; and in a second time interval, the integrator (R′INT, C′INT, 212) can integrate a voltage level of −V′SEN1 so that the integral result V′INT increases from the voltage reference V′L to the voltage reference V′H. The OPA 212 may have an input voltage offset V′OS, which causes a time difference between the first and second time intervals. Consequently, the alternation frequency f′CMP of the trigger signals CMP′H and CMP′L may have error caused by an integration of the voltage offset V′OS based on the time difference. A count value obtained by counting a number of the trigger signals CMP′H/CMP′L may have error caused by the input voltage offset V′OS.
Additionally, due to non-ideality of the comparators 214 and 216, there may be time delays in generation of the trigger signals CMP′H and CMP′L. This may result in error, e.g., a decrement, in the alternation frequency f′CMP of the trigger signals CMP′H and CMP′L. Comparators with relatively fast response speed may be used to reduce the error in the alternation frequency f′CMP. However, such comparators may be relatively expensive and consume relatively high power.
A coulomb counter that addresses the abovementioned shortcomings would be beneficial.
SUMMARY
In one embodiment, an analog-to-frequency converting circuit includes a set of switches, an integral comparing circuit, a compensation circuit, and a control circuit. The switches receive a first sense signal indicative of a current and provide a second sense signal that alternates between an original version of the first sense signal and a reversed version of the first sense signal, under control of a switching signal. The integral comparing circuit integrates the second sense signal to generate an integral value and generates a train of trigger signals at a frequency indicative of the current. Each trigger signal of the trigger signals is generated when the integral value reaches a preset reference. The compensation circuit compensates for the integral value with a predetermined value in response to each trigger signal of the trigger signals. The control circuit generates the switching signal such that a first time interval during which the second sense signal is the original version and a second time interval during which the second sense signal is the reversed version are substantially the same.



BRIEF DESCRIPTION OF THE DRAWINGS
Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, wherein like numerals depict like parts, and in which:
FIG. 1 illustrates a circuit diagram of a conventional voltage-to-frequency converter.
FIG. 2 illustrates a circuit diagram of a conventional coulomb counter.
FIG. 3 illustrates a circuit diagram of an example of a coulomb counter, in an embodiment according to the present invention.
FIG. 4 illustrates a circuit diagram of an example of a coulomb counter, in an embodiment according to the present invention.
FIG. 5A illustrates examples of waveforms of signals associated with a coulomb counter, in an embodiment according to the present invention.
FIG. 5B illustrates examples of waveforms of signals associated with a coulomb counter, in an embodiment according to the present invention.
FIG. 6A illustrates a circuit diagram of an example of a control circuit, in an embodiment according to the present invention.
FIG. 6B illustrates a circuit diagram of an example of a control circuit, in an embodiment according to the present invention.
FIG. 7 illustrates examples of waveforms of signals associated with a coulomb counter, in an embodiment according to the present invention.
FIG. 8 illustrates a flowchart of examples of operations performed by a coulomb counter, in an embodiment according to the present invention.



DETAILED DESCRIPTION
Reference will now be made in detail to the embodiments of the present invention. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.
Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Embodiments according to the present invention provide solutions to convert an analog signal, e.g., a current signal or a voltage signal, to a frequency signal indicative of, e.g., linearly proportional to, the analog signal. The frequency signal can be used for coulomb counting.
FIG. 3 illustrates a circuit diagram of an example of a coulomb counter 300, in an embodiment according to the present invention. In one embodiment, the coulomb counter 300 includes an analog-to-frequency converting circuit, a logic circuit 304, and a counter 306. The analog-to-frequency converter can include a sense resistor RSEN, a set of switches 302, an integral comparing circuit 310, a control circuit 320, and a compensation circuit 330.
In one embodiment, the analog-to-frequency converting circuit converts an analog signal (e.g., a current ISEN flowing through the sense resistor RSEN, a first sense voltage VSEN1 across the sense resistor RSEN, or a second sense voltage VSEN2 input to the integral comparing circuit 310) to a frequency signal such as a train of trigger signals SFREQ (e.g., a series of rising edges or a series of falling edges) at a frequency fCMP indicative of (e.g., linearly proportional to) the analog signal. The counter 306 can count a number of the trigger signals SFREQ (e.g., rising edges or falling edges) to generate a count value NCOUNT. The count value NCOUNT can represent a result of integrating the analog signal. In one embodiment, the analog signal includes a current ISEN of a battery 344. In one such embodiment, the count value NCOUNT obtained by counting the trigger signals SFREQ can represent an amount of accumulation of electric charges in the current ISEN, e.g., an amount of accumulation of electric charges passing in and out of the battery 344.
More specifically, in the analog-to-frequency converting circuit in one embodiment, the sense resistor RSEN senses a current ISEN flowing through the sense resistor RSEN, and generates a first sense signal VSEN1, e.g., a voltage signal, indicative of the current ISEN. The switches 302 receive the sense signal VSEN1 and provide a second sense signal VSEN2, e.g., a voltage signal, that alternates between an original version of the sense signal VSEN1 (e.g., VSEN2=VSEN1) and a reversed version of the sense signal VSEN1 (e.g., VSEN2=−VSEN1), under control of a switching signal FCHOP. The integral comparing circuit 310 integrates the sense signal VSEN2 to generate an integral value VINT of the sense signal VSEN2. The integral value VINT may increase or decrease depending on whether the sense signal VSEN2 is the original version of VSEN1 or the reversed version of VSEN1. The integral comparing circuit 310 also compares the integral value VINT with preset references VH and VL (VL<VH) and generates a train of trigger signals CMPH and CMPL at a frequency fCMP indicative of the current ISEN. In one embodiment, the abovementioned trigger signals SFREQ include the trigger signals CMPH and CMPL. Each trigger signal of the trigger signals CMPH and CMPL is generated when the integral value VINT of the sense signal VSEN2 reaches a preset reference VH or VL. In one embodiment, a trigger signal CMPH represents that the integral value VINT has increased to the preset reference VH, and a trigger signal CMPL represents that the integral value VINT has decreased to the preset reference VL. The compensation circuit 330 can compensate, e.g., decrease, the integral value VINT with a predetermined value in response to each trigger signal CMPH such that a train of trigger signals CMPH are generated. Similarly, the compensation circuit 330 can compensate, e.g., increase, the integral value VINT with a predetermined value in response to each trigger signal CMPL such that a train of trigger signals CMPL are generated. The control circuit 320 can generate the switching signal FCHOP such that a first time interval TA during which the sense signal VSEN2 is in the original version of the sense signal VSEN1 (e.g., VSEN2=VSEN1) and a second time interval TB during which the sense signal VSEN2 is in the reversed version of the sense signal VSEN1 (e.g., VSEN2=−VSEN1) are substantially the same.
By way of example, the switches 302 include switches SA1, SA2, SB1 and SB2. The switching signal FCHOP can turn off the switches SB1 and SB2 and turn on the switches SA1 and SA2 so that the sense signal VSEN2 is in an original version of the sense signal VSEN1, e.g., VSEN2=VSEN1. The switching signal FCHOP can also turn off the switches SA1 and SA2 and turn on the switches SB1 and SB2 so that the sense signal VSEN2 is in a reversed version of the sense signal VSEN1, e.g., VSEN2=−VSEN1.
The integral comparing circuit 310 can include an integrator (e.g., a combined circuit of an integrating resistor RINT, an integrating capacitor CINT, and an operational amplifier (OPA) 312; hereinafter, integrator (RINT, CINT, 312)) and comparator circuitry (e.g., including comparators 314 and 316; hereinafter, comparator circuitry 314-316). The integrator (RINT, CINT, 312) integrates the sense signal VSEN2 and generates an integral value VINT of the sense signal VSEN2. The integral value VINT can be given by:




  
    
      V
      INT
    
    =
    
      
        
          1
          
            
              R
              INT
            
            ⁢
            
              C
              INT
            
          
        
        ⁢
        
          ∫
          
            
              (
              
                
                  V
                  OS
                
                -
                
                  V
                  
                    SEN
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
              )
            
            ⁢
            d
            ⁢
            
              
            
            ⁢
            t
          
        
      
      +
      
        V
        R
        ′
      
    
  
  ,




where, RINT represents the resistance of the integrating resistor RINT, CINT represents the capacitance of the integrating capacitor CINT, VOS represents an input offset of the OPA 312, VSEN2 represents a voltage level of the sense signal VSEN2, and V′R represents a voltage level at the non-inverting input terminal of the OPA 312. Hence, the integral value VINT decreases if the sense signal VSEN2 is positive, and increases if the sense signal VSEN2 is negative. The comparator circuitry 314-316 compares the integral value VINT with a high-side reference VH and a low-side reference VL that is less than the high-side reference VH, generates a trigger signal CMPH if the integral value VINT is greater than the high-side reference VH, and generates a trigger signal CMPL if the integral value VINT is less than the low-side reference VL. In the example of FIG. 3, the trigger signals CMPH and CMPL are logic-low signals (e.g., falling edges of signals). However, the invention is not so limited. In another embodiment, the comparator circuitry is in another structure, and the trigger signals CMPH and CMPL can be logic-high signals (e.g., rising edges of signals) or a combination of a logic-high signal and a logic-low signal.

The control circuit 320 can receive the trigger signals CMPH and CMPL and generate one or more control signals SCTRL to control the compensation circuit 330 according to the trigger signals CMPH and CMPL, so as to control a frequency fCMP of the trigger signals CMPH/CMPL to be indicative of (e.g., linearly proportional to) the sense signal VSEN2. More specifically, in one embodiment, the compensation circuit 330 can provide compensation charges to the integral comparing circuit 310 such that positive charges pass through the integrating capacitor CINT from the inverting input terminal of the OPA 312 to the output terminal of the OPA 312, and therefore the integral value VINT decreases. Such compensation charges can be referred to as “positive compensation charges.” The compensation circuit 330 can also provide compensation charges to the integral comparing circuit 310 such that positive charges pass through the integrating capacitor CINT from the output terminal of the OPA 312 to the inverting input terminal of the OPA 312, and therefore the integral value VINT increases. Such compensation charges can be referred to as “negative compensation charges.” In one embodiment, if a trigger signal CMPH is generated from the comparator 314, e.g., indicating that the integral value VINT increases to the high-side reference VH, then the control circuit 320 controls the compensation circuit 330 to provide positive compensation charges in a predetermined amount QREF to the integrating capacitor CINT, so as to decrease the integral value VINT by a predetermined value ΔVINT. The predetermined value ΔVINT can be determined by the value of QREF/CINT. After it is decreased, the decreased integral value VINT may continue to increase because of the integration of the sense signal VSEN2. When the integral value VINT increases to the high-side reference VH, the compensation circuit 330 provides positive compensation charges QREF to the integrating capacitor CINT again, so as to again decease the integral value VINT by the predetermined value ΔVINT. By compensating the integrating capacitor CINT with the same amount of electric charges QREF each time the integral value VINT increases to the high-side reference VH, the integral value VINT can ramp up and down alternately, and the integral comparing circuit 310 can generate a train of trigger signals CMPH at a frequency fCMP linearly proportional to the sense signal VSEN2, e.g., linearly proportional to the current ISEN. Similarly, if a trigger signal CMPL is generated from the comparator 316, e.g., indicating that the integral value VINT decreases to the low-side reference VL, then the control circuit 320 controls the compensation circuit 330 to provide negative compensation charges in the predetermined amount QREF to the integrating capacitor CINT, so as to increase the integral value VINT by a predetermined value ΔVINT. The predetermined value ΔVINT can be determined by the value of QREF/CINT. The compensation circuit 330 can compensate the integrating capacitor CINT with the same amount of electric charges QREF to increase the integral value VINT each time the integral value VINT decreases to the low-side reference VL. Hence, the integral comparing circuit 310 can generate a train of trigger signals CMPL at a frequency fCMP linearly proportional to the sense signal VSEN2, e.g., linearly proportional to the current ISEN.
FIG. 4 illustrates a circuit diagram of an example of a compensation circuit 330 in a coulomb counter 400, in an embodiment according to the present invention. In one embodiment, the compensation circuit 330 described in relation to FIG. 3 has the circuit structure of the compensation circuit 330 disclosed in FIG. 4.
As shown in FIG. 4, the compensation circuit 330 includes a capacitive component CCOM, e.g., a compensation capacitor, a set of switches 434, e.g., including switches SL1, SL2, SH1, SH2, SC1 and SC2, and a voltage source 432. The capacitive component CCOM can be used to store and provide the abovementioned compensation charges QREF. Under control of the control circuit 320, the switches 434 can selectively connect the voltage source 432 to the capacitive component CCOM to charge the capacitive component CCOM so that the capacitive component CCOM has a voltage level VREF of the voltage source 432. The switches 434 can also selectively connect the capacitive component CCOM to the integral comparing circuit 310 so that the compensation circuit 330 provides a compensation signal VCOM to compensate, e.g., increase or decrease, the integral value VINT. By way of example, the voltage source 432 provides a reference voltage VREF. The control circuit 320 can generate control signals SCTRL1 and SCTRL2 to turn on the switches SC1 and SC2 and turn off the switches SL1, SL2, SH1 and SH1, so that the capacitive component CCOM is charged to have a voltage level of VREF. The capacitive component CCOM can store an amount of compensation charges QREF that is given by: QREF=VREF*CCOM. The control circuit 320 can also generate control signals SCTRL1 and SCTRL2 to turn off the switches SC1 and SC2 and turn on the switches SH1 and SH2 or the switches SL1 and SL2, and therefore the two terminals of the capacitive component CCOM are coupled to the two input terminals of the OPA 312 respectively. In one embodiment, because the OPA 312 controls its two input terminals to have the same voltage level, which results in controlling a voltage across the capacitive component CCOM to be zero volts, the capacitive component CCOM can discharge compensation charges QREF to the integral comparing circuit 310. As shown in FIG. 4, when the switches SH1 and SH2 are on and the switches SL and SL2 are off, the compensation signal VCOM provided to the integral comparing circuit 310 is at a voltage level of VREF, e.g., a positive level, and therefore the compensation circuit 330 provides positive compensation charges QREF to the integrating capacitor CINT to decrease the integral value VINT. When the switches SL1 and SL2 are on and the switches SH1 and SH2 are off, the compensation signal VCOM provided to the integral comparing circuit 310 is at a voltage level of −VREF, e.g., a negative level, and therefore the compensation circuit 330 provides negative compensation charges QREF to the integrating capacitor CINT to increase the integral value VINT.
In one embodiment, the control circuit 320 controls the switches 434 according to the trigger signals CMPH and CMPL such that the compensation signal VCOM is selectively at the voltage level VREF and a reversed level −VREF of the voltage level VREF. For example, as mentioned above, the capacitive component CCOM can be charged to have the voltage level VREF when the switches SC1 and SC2 are on and the switches SL1, SL2, SH1 and SH2 are off. If the control circuit 320 detects that a trigger signal CMPH is generated, e.g., indicating that the integral value VINT increases to the high-side reference VH, then the control circuit 320 turns off the switches SC1 and SC2, turns on the switches SH1 and SH2, and maintain the switches SL1 and SL2 off. Hence, the compensation circuit 330 provides a compensation signal VCOM at the voltage level VREF to the integral comparing circuit 310 to decrease the integral value VINT. For another example, the capacitive component CCOM can be charged to have a voltage level of VREF when the switches SC1 and SC2 are on and the switches SL1, SL2, SH1 and SH2 are off. If the control circuit 320 detects that a trigger signal CMPL is generated, e.g., indicating that the integral value VINT decreases to the low-side reference VL, then the control circuit 320 turns off the switches SC1 and SC2, turns on the switches SL1 and SL2, and maintain the switches SH1 and SH2 off. Hence, the compensation circuit 330 provides a compensation signal VCOM at the voltage level −VREF to the integral comparing circuit 310 to increase the integral value VINT.
In one embodiment, the compensation circuit 330 also include a filter circuit 436 such as a low-pass filter. The filter circuit 436 can be implemented in many different circuit structures, and FIG. 4 shows an example thereof. In the example of FIG. 4, the filter circuit 436 includes resistors R1 and R2 and a capacitor CLPF. The filter circuit 436 can pass the compensation charges QREF from the compensation circuit 330 to the integral comparing circuit 310 to change the integral value VINT. The filter circuit 436 can also buff, e.g., slow down, the flowing of the compensation charges QREF from the capacitive component CCOM to the integral comparing circuit 310, so as to reduce/smoothen the change in the integral value VINT caused by the compensation charges QREF. More details are described in combination with FIG. 5A and FIG. 5B.
FIG. 5A illustrates examples of waveforms of the sense signal VSEN2, the integral value VINT, the trigger signal CMPH, and a charge capacity QCOM of the capacitive component CCOM, in an embodiment according to the present invention. FIG. 5A is described in combination with FIG. 3 and FIG. 4.
In the example of FIG. 5A, the sense signal VSEN2 has a negative voltage level, and the integral value VINT increases due to integration of the negative sense signal VSEN2. At time tN1, the integral value VINT increases to the high-side reference VH, and a trigger signal CMPH (e.g., a falling edge of a signal) is generated. Hence, the control circuit 320 turns on the switches SH1 and SH2 and turns off the switches SL1, SL2, SC1 and SC2 so that the capacitive component CCOM discharges an amount of the compensation charges QREF to the integrating capacitor CINT to decrease the integral value VINT by a decrement ΔVINT. In one embodiment, the decrement ΔVINT can be considered to be QREF/CINT, where QREF represents the amount of compensation charges provided to the integrating capacitor CINT, and CINT represents the capacitance of the integrating capacitor CINT. In other words, as shown in FIG. 5A, at time tN1, the integral value VINT can be considered to decrease to the voltage level of VH-QREF/CINT, and then linearly increases from the voltage level of VH-QREF/CINT toward the high-side reference VH. In one embodiment, because the filter circuit 436 such as a low-pass filter can reduce/smoothen the change in the integral value VINT caused by the compensation charges QREF, the integral value VINT does not decrease to the voltage level of VH-QREF/CINT in practice. However, because the change in the charge capacity of the integrating capacitor CINT caused by the compensation charges QREF is equal to QREF, the change in a voltage across the integrating capacitor CINT, e.g., the change in the integral value VINT, caused by the compensation charges QREF can be considered to be equal to QREF/CINT.
Between time tN1 and time tN2, the charge capacity QCOM of the capacitive component CCOM decreases to zero because the two terminals of the capacitive component CCOM, coupled to the two input terminals of the OPA 312 respectively, are controlled to have the same voltage level by the OPA 312. At time tN2, the control circuit 320 turns on the switches SC1 and SC2 and turns off the switches SH1, SH2, SL1 and SL2 so that the capacitive component CCOM is charged by the voltage source 432 and the charge capacity QCOM of the capacitive component CCOM increases to QREF, e.g., QREF=VREF*CCOM.
As shown in FIG. 5A, a trigger signal CMPH is generated each time the integral value VINT increases to the high-side reference VH. In response to each trigger signal CMPH, the capacitive component CCOM discharges to provide an amount of compensation charges QREF to the integrating capacitor CINT to decrease the integral value VINT by a decrement ΔVINT, e.g., ΔVINT=QREF/CINT. The charge capacity QCOM of the capacitive component CCOM can decrease to zero. After a preset time interval Δt from the generation of each trigger signal CMPH, e.g., Δt=tN2−tN1=tN4−tN3=tN6−tN5 . . . , the capacitive component CCOM is charged by the voltage source 432. The charge capacity QCOM of the capacitive component CCOM can increase to QREF. Thus, in one embodiment, each time the integral value VINT increases to the high-side reference VH, the compensation circuit 330 provides the same amount of compensation charges QREF to the integrating capacitor CINT to decrease the integral value VINT, e.g., by the same decrement QREF/CINT. In one embodiment, an integration time TINT, e.g., tN3−tN1, tN5−tN3, etc., for integrating the sense signal VSEN2 so that the integral value VINT increases from the voltage level VH−QREF/CINT to the voltage level VH can be given by: TINT=QREF*RINT/VSEN2. Thus, the integration time TINT is inversely proportional to the sense signal VSEN2. In other words, the trigger signals CMPH are generated at a frequency fCMP (e.g., 1/TINT) that is linearly proportional to the sense signal VSEN2.
FIG. 5B illustrates examples of waveforms of the sense signal VSEN2, the integral value VINT, the trigger signal CMPL, and the charge capacity QCOM of the capacitive component CCOM, in an embodiment according to the present invention. FIG. 5B is described in combination with FIG. 3, FIG. 4, and FIG. 5A. In the example of FIG. 5B, the sense signal VSEN2 has a positive voltage level, and the integral value VINT decreases due to integration of the positive sense signal VSEN2.
Similar to the operations described in relation to FIG. 5A, as shown in FIG. 5B, a trigger signal CMPL is generated each time the integral value VINT decreases to the low-side reference VL. In response to each trigger signal CMPL, the capacitive component CCOM discharges to provide an amount of compensation charges QREF to the integrating capacitor CINT to increase the integral value VINT by an increment ΔVINT, e.g., ΔVINT=QREF/CINT. The charge capacity QCOM of the capacitive component CCOM can decrease to zero. After a preset time interval Δt from the generation of each trigger signal CMPL, e.g., Δt=tP2−tP1=tP4−tN3=tP6−tP5 . . . , the capacitive component CCOM is charged by the voltage source 432. The charge capacity QCOM of the capacitive component CCOM can increase to QREF. Thus, in one embodiment, each time the integral value VINT decreases to the low-side reference VL, the compensation circuit 330 provides the same amount of compensation charges QREF to the integrating capacitor CINT to increase the integral value VINT, e.g., by the same increment QREF/CINT. In one embodiment, an integration time TINT, e.g., tP3−tP1, tP5−tP3, etc., for integrating the sense signal VSEN2 so that the integral value VINT decreases from the voltage level VL+QREF/CINT to the voltage level VL can be given by: TINT=QREF*RINT/VSEN2. Thus, the integration time TINT is inversely proportional to the sense signal VSEN2. In other words, the trigger signals CMPL are generated at a frequency fCMP (e.g., 1/TINT) that is linearly proportional to the sense signal VSEN2.
Accordingly, in one embodiment, the analog-to-frequency converting circuit, e.g., including the sense resistor RSEN, the switches 302, the integral comparing circuit 310, the control circuit 320, and the compensation circuit 330, can sense a current ISEN flowing through the sense resistor RSEN and generate a train of trigger signals CMPH/CMPL (e.g., a series of rising edges or a series of a falling edges) at a frequency fCMP indicative of (e.g., linearly proportional to) the current ISEN.
Returning to FIG. 4, the capacitive component CCOM includes a first terminal 450 and a second terminal 452 selectively coupled to a first terminal 454 of the OPA 312 and a second terminal 456 of the OPA 312 through the switches SL1, SL2, SH1 and SH1. The control circuit 320 controls the switches SL1, SL2, SH1 and SH1 such that if the first terminal 450 of the capacitive component CCOM is coupled to the first terminal 454 of the OPA 312, then the second terminal 452 of the capacitive component CCOM is coupled to the second terminal 456 of the OPA 312, and if the first terminal 450 of the capacitive component CCOM is coupled to the second terminal 456 of the OPA 312, then the second terminal 452 of the capacitive component CCOM is coupled to the first terminal 454 of the OPA 312. In other words, when the compensation circuit 330 provides compensation charges to the integral comparing circuit 310, the two terminals of the capacitive component CCOM are coupled to the two input terminals of the OPA 312 respectively. This capacitive component CCOM can be referred to as a “flying” or “floating” capacitor. Thus, terminals 340 and 342 of the sense resistor RSEN, different from the terminal 156 of the sense resistor R′SEN in FIG. 1, can have voltage levels independent of the compensation signal VCOM, e.g., VREF or −VREF, from the capacitive component CCOM. Advantageously, the sense resistor RSEN can be placed at a negative terminal of a battery or a positive terminal of a battery.
Although FIG. 3 and FIG. 4 disclose that the positive terminal of the battery 344 is coupled to the terminal 342 of the sense resistor RSEN, the invention is not so limited. In another embodiment, the positive terminal of the battery 344 can be coupled to the other terminal 340 of the sense resistor RSEN. In yet another embodiment, the negative terminal of the battery 344 can be coupled to the terminal 340 or the terminal 342 of the sense resistor RSEN.
Additionally, in one embodiment, the compensation circuit 330 can, but not necessarily, use one capacitor CCOM to provide compensation charges. Thus, compared with the compensation circuitry in FIG. 1 that includes two capacitors CP1 and CP1, the compensation circuit 330 can cost less and have a smaller size.
Moreover, in one embodiment, due to non-ideality of the comparators 314 and 316, there may be delays, e.g., Δt, in the generation of the trigger signals CMPH and CMPL. With reference to FIG. 5A, in one embodiment, the trigger signals CMPH may be generated at times tN1+Δt, tN3+Δt, tN5+Δt, etc., instead of times tN1, tN3, tN5, etc., due to non-ideality of the comparator 314. In this embodiment, the delay Δt exists each time a trigger signal CMPH is generated. Thus, the delays in generation of the trigger signals CMPH may not result in error, e.g., a decrement, in the frequency fCMP of the trigger signals CMPH. Similarly, delays in generation of trigger signals CMPL may not result in error, e.g., a decrement, in the frequency fCMP of the trigger signals CMPL.
Furthermore, as mentioned above, the filter circuit 436 such as a low-pass filter can buff, e.g., slow down, the flowing of the compensation charges QREF from the capacitive component CCOM to the integral comparing circuit 310, so as to reduce/smoothen the change in the integral value VINT caused by the compensation charges QREF. Thus, a current generated by the OPA 312 and through the integrating capacitor CINT and the capacitive component CCOM to discharge the capacitive component CCOM can be reduced, compared with the current generated to discharge the capacitor CP1 described in relation to FIG. 1.
Returning to FIG. 3, the coulomb counter 300 also includes a logic circuit 304 and a counter 306. The counter 306 can count a number of the trigger signals SFREQ, e.g., including signals CMPH and CMPL, to generate a count value NCOUNT. The count value NCOUNT can represent a result of integrating a current ISEN flowing through the sense resistor RSEN. In one embodiment, the current ISEN can be a charging current or a discharging current of a battery 344. In one such embodiment, the count value NCOUNT can represent an amount of accumulation of electric charges in the battery current ISEN, e.g., an amount of accumulation of electric charges passing in and out of the battery 344.
In one embodiment, the OPA 312 may include an input offset VOS, e.g., an input voltage offset, which may cause error in the frequency fCMP of the trigger signals SFREQ, e.g., including signals CMPH and CMPL. Advantageously, as mentioned above, the control circuit 320 can generate a switching signal FCHOP to control the switches 302 such that the sense signal VSEN2 alternates between an original version of the sense signal VSEN1 (e.g., VSEN2=VSEN1) and a reversed version of the sense signal VSEN1 (e.g., VSEN2=−VSEN1), and that a first time interval TA during which the sense signal VSEN2 is in the original version VSEN1 (e.g., VSEN2=VSEN1) and a second time interval TB during which the sense signal VSEN2 is in the reversed version −VSEN1 (e.g., VSEN2=−VSEN1) are substantially the same. As used herein, “substantially the same” means that the time intervals TA and TB are controlled to be the same but a negligibly small difference may exist between the time intervals TA and TB due to non-ideality of the control circuit 320 and/or the switches 302. The counter 306 can count a number ΔNSUM of the trigger signals SFREQ for the first and second time interval to generate a count value, e.g., ΔNSUM=ΔN1+ΔN2 where ΔN1 represents the number of the trigger signals SFREQ generated in the first time interval, and ΔN2 represents the number of the trigger signals SFREQ generated in the second time interval. For example, the counter 306 can increase the count value NCOUNT by an increment of ΔN1+ΔN2 if the current ISEN is a charging current of the battery 344, or decrease the count value NCOUNT by a decrement of ΔN1+ΔN2 if the current ISEN is a discharging current of the battery 344. As a result, the control circuit 320 can counteract error, caused by the input offset VOS of the OPA 312, in the count value NCOUNT by controlling the first and second time intervals TA and TB to be substantially the same. More details will be described in combination with FIG. 7.
In one embodiment, the logic circuit 304 cooperates with the control circuit 320 to generate a count-direction signal SD/U. The count-direction signal SD/U can represent a flowing direction of the current ISEN, e.g., indicate whether the current ISEN is a charging current or a discharging current of the battery 344, and can control the counter 306 to increase or decrease the count value NCOUNT when a trigger signal SFREQ is generated. More specifically, in one embodiment, the logic circuit 304 includes an XOR gate, and the control circuit 320 includes a circuit structure disclosed in FIG. 6A.
FIG. 6A illustrates a circuit diagram of an example of the control circuit 320, e.g., labeled 320A, in an embodiment according to the present invention. FIG. 6A is described in combination with FIG. 3 and FIG. 4. As shown in FIG. 6A, the control circuit 320A includes a switch control circuit 622 and a logic circuit 624A. The switch control circuit 622 can generate a switching signal FCHOP to control the switches 302, and generate one or more control signals SCTRL to control the compensation circuit 330, e.g., generate control signals SCTRL1 and SCTRL2 to control the switches 434 in FIG. 4. In one embodiment, when the switching signal FCHOP is in a first status, e.g., logic high (or logic low), the switches 302 can provide a sense signal VSEN2 at the voltage level of VSEN1 to the integral comparing circuit 310; and when the switching signal FCHOP is in a second status, e.g., logic low (or logic high; the opposite of the first status), the switches 302 can provide a sense signal VSEN2 at the voltage level of −VSEN1 to the integral comparing circuit 310. The switch control circuit 622 can control the switching signal FCHOP to have a 50% duty cycle such that the abovementioned first time interval TA and second time interval TB are the same.
In one embodiment, the logic circuit 624A generates a trigger signal SFREQ on detection of each trigger signal of the signals CMPH and CMPL. By way of example, the logic circuit 624A includes an AND gate 626A coupled to the comparators 314 and 316 and operable for receiving trigger signals CMPH and CMPL from the comparators 314 and 316. In the example of FIG. 6A, the comparator 314 receives the integral value VINT at its inverting input terminal and receives the high-side reference VH at its non-inverting input terminal. Thus, the trigger signal CMPH, representing that the integral value VINT has increased to the high-side reference VH, is a logic-low signal, e.g., a falling edge of a signal. Similarly, the comparator 316 receives the integral value VINT at its non-inverting input terminal and receives the low-side reference VL at its inverting input terminal. Thus, the trigger signal CMPL, representing that the integral value VINT has decreased to the low-side reference VL, is a logic-low signal, e.g., a falling edge of a signal. The AND gate 626A can output a trigger signal SFREQ at logic-low when detecting a trigger signal CMPH or CMPL, e.g., a logic-low signal, at its input terminals. Consequently, the trigger signals SFREQ represent a combination of the trigger signal CMPH and CMPL and can be considered to include the trigger signal CMPH or CMPL.
In one embodiment, the logic circuit 624A cooperates with the switch control circuit 622 and the logic circuit 304 to generate a count-direction signal SD/U. The count-direction signal SD/U determines whether to increase or decrease the abovementioned count value NCOUNT when a trigger signal SFREQ is generated. More specifically, in one embodiment, the logic circuit 624A generates a polarity signal SPOL, sets the polarity signal SPOL to a first logic level on detection of the trigger signal CMPH, and sets the polarity signal SPOL to a second logic level on detection of the trigger signal CMPL. The first and second logic levels are different. As used herein, two logic levels are “different” if the two logic levels are inverted relative to each other. For example, if one of the logic levels is logic high, then the other one of the logic levels is logic low; and if one of the logic levels is logic low, then the other one of the logic levels is logic high. In the example of FIG. 6A, a set-reset NAND latch 628A in the logic circuit 624A can set the polarity signal SPOL to be logic high on detection of a trigger signal CMPH at its set input terminal labeled “S”, and set the polarity signal SPOL to be logic low on detection of a trigger signal CMPL at its reset input terminal labeled “R”. In one embodiment, as mentioned above, a trigger signal CMPH can be generated during a situation where the sense signal VSEN2 is positive, and a trigger signal CMPL can be generated during a situation where the sense signal VSEN2 is negative. Thus, the polarity signal SPOL can represent whether the second sense signal VSEN2 is positive or negative.
Additionally, the logic circuit 304 such as an XOR gate can set the count-direction signal SD/U to a third logic level if a logic level of the polarity signal SPOL and a logic level of the switching signal FCHOP are the same, and set the count-direction signal SD/U to a fourth logic level if a logic level of the polarity signal SPOL and a logic level of the switching signal FCHOP are the different. The third and fourth logic levels are different, similar to the abovementioned first and second logic levels. As used herein, two logic levels are “the same” if the two logic levels are either logic high at the same time or logic low at the same time. In the example of FIG. 6A, the logic circuit 304 can set the count-direction signal SD/U to be logic low if the polarity signal SPOL and the switching signal FCHOP both are logic high or logic low. The logic circuit 304 can also set the count-direction signal SD/U to be logic high if the polarity signal SPOL is logic high and the switching signal FCHOP is logic low, or if the polarity signal SPOL is logic low and the switching signal FCHOP is logic high. In one embodiment, whether the polarity signal SPOL and the switching signal FCHOP have the same logic level is determined by the direction the current ISEN is flowing through the sense resistor RSEN (shown in FIG. 3). Thus, the logic level of the count-direction signal SD/U can represent whether the current ISEN is a charging current or a discharging current of the battery 344, and therefore can determine whether to increase or decrease the abovementioned count value NCOUNT when a trigger signal SFREQ is generated. More details are described in combination with FIG. 7.
FIG. 7 illustrates examples of waveforms of the first sense signal VSEN1, the second sense voltage VSEN2, the trigger signals SFREQ, the polarity signal SPOL, the switching signal FCHOP, the count-direction signal SD/U, and the count value NCOUNT, in an embodiment according to the present invention. FIG. 7 is described in combination with FIG. 3, FIG. 4, and FIG. 6A. In the example of FIG. 7, during time to and time t4, the battery 344 is in a charging mode, the first sense signal VSEN1 is positive, and the count value NCOUNT increases in response to each trigger signal SFREQ; and during time t4 to time t8, the battery 344 is in a discharging mode, the first sense signal VSEN1 is negative, and the count value NCOUNT decreases in response to each trigger signal SFREQ.
In the example of FIG. 7, the control circuit 320 can turn off the switches SA1 and SA2 and turn on the switches SB1 and SB2 by setting the switching signal FCHOP to be logic high, and can turn off the switches SB1 and SB2 and turn on the switches SA1 and SA2 by setting the switching signal FCHOP to be logic low. Thus, as shown in FIG. 7, when the battery 344 is in a charging mode, e.g., from time t0 to time t4, the second sense voltage VSEN2 is negative if the switching signal FCHOP is logic high, and is positive if the switching signal FCHOP is logic low. When the battery 344 is in a discharging mode, e.g., from time t4 to time t8, the second sense voltage VSEN2 is positive if the switching signal FCHOP is logic high, and is negative if the switching signal FCHOP is logic low.
From time t0 to time t1, the switching signal FCHOP is logic high, and the second sense voltage VSEN2 is negative. Hence, a set of trigger signals CMPH are generated, and the latch 628A sets the polarity signal SPOL to be logic high accordingly. Because the polarity signal SPOL and the switching signal FCHOP have the same logic level, e.g., logic high, the logic circuit 304 sets the count-direction signal SD/U to be logic low. Similarly, from time t1 to time t2, the switching signal FCHOP is logic low, and the second sense voltage VSEN2 is positive. Hence, a set of trigger signals CMPL are generated, and the latch 628A sets the polarity signal SPOL to be logic low accordingly. Because the polarity signal SPOL and the switching signal FCHOP have the same logic level, e.g., logic low, the logic circuit 304 sets the count-direction signal SD/U to be logic low. In addition, from time t4 to time t5, the switching signal FCHOP is logic high, and the second sense voltage VSEN2 is positive. Hence, a set of trigger signals CMPL are generated, and the latch 628A sets the polarity signal SPOL to be logic low accordingly. Because the polarity signal SPOL and the switching signal FCHOP have different logic levels, the logic circuit 304 sets the count-direction signal SD/U to be logic high. Similarly, from time t5 to time t6, the switching signal FCHOP is logic low, and the second sense voltage VSEN2 is negative. Hence, a set of trigger signals CMPH are generated, and the latch 628A sets the polarity signal SPOL to be logic high accordingly. Because the polarity signal SPOL and the switching signal FCHOP have different logic levels, the logic circuit 304 sets the count-direction signal SD/U to be logic high. Thus, in this example of FIG. 7, the count-direction signal SD/U is logic low if the battery 344 is in a charging mode, and is logic high if the battery 344 is in a discharging mode. If the counter 306 detects that the count-direction signal SD/U is logic low, then the counter 306 increases the count value NCOUNT in response to each trigger signal SFREQ; and if the counter 306 detects that the count-direction signal SD/U is logic high, then the counter 306 decreases the count value NCOUNT in response to each trigger signal SFREQ.
FIG. 7 shows examples of the signals associated with the coulomb counter 300 (or 400) in one embodiment, but the invention is not limited to these examples. In another embodiment, the control circuit 320 can turn off the switches SA1 and SA2 and turn on the switches SB1 and SB2 by setting the switching signal FCHOP to be logic low, and can turn off the switches SB1 and SB2 and turn on the switches SA1 and SA2 by setting the switching signal FCHOP to be logic high. In one such embodiment, if the count-direction signal SD/U is logic high, then it indicates that the battery 344 is in a charging mode, and the counter 306 increases the count value NCOUNT in response to each trigger signal SFREQ. If the count-direction signal SD/U is logic low, then it indicates that the battery 344 is in a discharging mode, and the counter 306 decreases the count value NCOUNT in response to each trigger signal SFREQ. In yet other embodiments, the battery 344 may be coupled to the sense resistor RSEN in other manners, and the signals VSEN1, VSEN2, SFREQ, SPOL, FCHOP, and SD/U can have different waveforms accordingly.
Additionally, as mentioned above, the control circuit 320 can counteract error, caused by an input offset VOS of the OPA 312, in the count value NCOUNT by controlling the first and second time intervals TA and TB to be substantially the same. Taking FIG. 7 as an example, the reference line labeled “VR” represents a voltage level at the terminal 342 of the sense resistor RSEN, and the reference line labeled “V′R” represents a voltage level at the non-inverting input terminal of the OPA 312. A voltage difference, e.g., labeled “VOS” in FIG. 7, between the voltage levels VR and V′R can represent an input offset of the OPA 312. Thus, from time t0 to time t1, the integral comparing circuit 310 integrates a voltage level of −(VSEN1+VOS) and generates a number ΔN1 of the trigger signals CMPH. The number ΔN1 represents a result of integrating an absolute value |VSEN1+VOS| for the time duration between to and t1 (e.g., referred to as “second time interval TB”). From time t1 to time t2, the integral comparing circuit 310 integrates a voltage level of VSEN1−VOS and generates a number ΔN2 of the trigger signals CMPL. The number ΔN2 represents a result of integrating an absolute value |VSEN1−VOS| for the time duration between t1 and t2 (e.g., referred to as “first time interval TA”). In one embodiment, the control circuit 320 controls the switching signal FCHOP to have a 50% duty cycle such that the first time interval TA and the second time interval TB are the same. Consequently, the error caused by integrating the input offset VOS for the first time interval TA and the error caused by integrating the input offset VOS for the second time interval TB can be counteracted by each other. The sum ΔNSUM of the numbers ΔN1 and ΔN2 can represent a result of integrating an absolute value |VSEN2|.
FIG. 6B illustrates a circuit diagram of another example of the control circuit 320, e.g., labeled 320B, in an embodiment according to the present invention. FIG. 6B is described in combination with FIG. 3, FIG. 4, and FIG. 6A. The example of FIG. 6B is similar to the example of FIG. 6A except that the comparator 314 in FIG. 6B receives the integral value VINT at its non-inverting input terminal and receives the high-side reference VH at its inverting input terminal, the comparator 316 receives the integral value VINT at its inverting input terminal and receives the low-side reference VL at its non-inverting input terminal, and the control circuit 320B includes a logic circuit 624B. In the example of FIG. 6B, trigger signals CMPH and CMPL generated by the comparators 314 and 316 are logic-high signals, e.g., rising edges. The logic circuit 624B includes an OR gate 626B and a set-reset latch 628B. The OR gate 626B can detect the trigger signals CMPH and CMPL, and output a logic-high trigger signal SFREQ if detecting that a trigger signal CMPH or CMPL is generated. The latch 628B, similar to the latch 628A, can set the polarity signal SPOL to a first logic level, e.g., logic high, on detection of a trigger signal CMPH, and sets the polarity signal SPOL to a second logic level, e.g., logic low, on detection of a trigger signal CMPL. Similar to the example of FIG. 6A, the logic circuit 624B can cooperate with the switch control circuit 622 and the logic circuit 304 to generate a count-direction signal SD/U, and the count-direction signal SD/U determines whether to increase or decrease the count value NCOUNT when a trigger signal SFREQ is generated.
Although, as disclosed in FIG. 6A (and similarly disclosed in FIG. 6B), the output terminal of the compactor 314 is coupled to the set terminal of the latch 628A (or 628B), and the output terminal of the compactor 316 is coupled to the reset terminal of the latch 628A (or 628B), the invention is not so limited. In another embodiment, the output terminal of the compactor 314 can be coupled to the reset terminal of the latch 628A (or 628B), and the output terminal of the compactor 316 is coupled to the set terminal of the latch 628A (or 628B).
Returning to FIG. 3, in one embodiment, in operation, the control circuit 320 generates a switching signal FCHOP to control the switches 302 such that the second sense voltage VSEN2 alternates between the voltage levels of VSEN1 and −VSEN. Based on the integrating of the second sense voltage VSEN2, the comparing between the integral value VINT and the references VH and VL, and the compensating with electric charges from the compensation circuit 330, the integral comparing circuit 310 can alternately generate a set of trigger signals CMPH and a set of trigger signals CMPL. The control circuit 320 can generate a set of trigger signals SFREQ that present a combination of the trigger signals CMPH and CMPL. The control circuit 320 can also set a polarity signal SPOL to a first logic level when receiving a trigger signal CMPH, and set the polarity signal SPOL to a second logic level when receiving a trigger signal CMPL. The logic circuit 304 can output a count-direction signal SD/U according to the polarity signal SPOL and the switching signal FCHOP. The counter 306 can count the number of the trigger signals SFREQ to generate a count value NCOUNT, and increase or decrease the count value NCOUNT according to the count-direction signal SD/U.
FIG. 8 illustrates a flowchart 800 of examples of operations performed by a coulomb counter, e.g., 300 or 400, in an embodiment according to the present invention. FIG. 8 is described in combination with FIG. 3, FIG. 4, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, and FIG. 7.
In block 802, the sense resistor RSEN generates a first sense signal VSEN1 indicative of a current ISEN flowing through the sense resistor RSEN.
In block 804, the switches 302 provide a second sense signal VSEN2 that alternates between an original version of the first sense signal VSEN1 (e.g., VSEN2=VSEN1) and a reversed version of the first sense signal VSEN1 (e.g., VSEN2=−VSEN1).
In block 806, the integral comparing circuit 310 integrates the second sense signal VSEN2 to generate an integral value VINT.
In block 808, the integral comparing circuit 310 generates a train of trigger signals SFREQ, e.g., including trigger signals CMPH and CMPL. Each trigger signal of the trigger signals SFREQ is generated when the integral value VINT reaches a preset reference VH or VL.
In block 810, the compensation circuit 330 compensates for the integral value VINT with a predetermined value, e.g., QREF/CINT, in response to each trigger signal of the trigger signals SFREQ.
In block 812, the control circuit 320 controls a first time interval TA, during which the second sense signal VSEN2 is the original version of VSEN1, and a second time interval TB, during which the second sense signal VSEN2 is the reversed version of VSEN1, to be substantially the same.
In summary, embodiments according to the present invention provide analog-to-frequency converting circuits to convert an analog signal, e.g., a current of a battery, to a train of trigger signals at a frequency. By using an integral comparing circuit, compensation circuit, and control circuit in the analog-to-frequency converting circuit, in one embodiment according to the present invention, to generate the trigger signals, the frequency of the trigger signals can be linearly proportional to the current of the battery. A coulomb counter can count the trigger signals to generate a count value, and the count value can represent an accumulation of charges passing in and out of the battery. In one embodiment, by controlling the abovementioned first time interval TA and second time interval TB to be substantially the same, error in the count value caused by an input offset of the integral comparing circuit can be eliminated. The analog-to-frequency converting circuit can be used for coulomb counting in many applications such as battery monitoring and battery management in various portable electronic devices, e.g., mobile phones, cameras, laptop computers, tablet computers, GPS navigation devices, etc. The analog-to-frequency converting circuit can also be used in other situations in which an analog signal is needed to be converted to a frequency signal to indicate the analog signal.
While the foregoing description and drawings represent embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the principles of the present invention as defined in the accompanying claims. One skilled in the art will appreciate that the invention may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.

## Claims

1. An analog-to-frequency converting circuit comprising:
a first plurality of switches operable for receiving a first sense signal indicative of a current and providing a second sense signal that alternates between an original version of said first sense signal and a reversed version of said first sense signal, under control of a switching signal;
an integral comparing circuit, coupled to said first plurality of switches, operable for integrating said second sense signal to generate an integral value, and operable for generating a train of trigger signals at a frequency indicative of said current, wherein each trigger signal of said trigger signals is generated when said integral value reaches a preset reference;
a compensation circuit, coupled to said integral comparing circuit, operable for compensating for said integral value with a predetermined value in response to each trigger signal of said trigger signals, wherein said compensation circuit comprises:
a capacitive component; and
a second plurality of switches, coupled to said capacitive component, operable for selectively connecting a voltage source to said capacitive component to charge said capacitive component so that said capacitive component has a voltage level of said voltage source, and selectively connecting said capacitive component to said integral comparing circuit so that said compensation circuit provides a compensation signal to compensate for said integral value, wherein said control circuit controls said second plurality of switches according to said trigger signals such that said compensation signal is selectively at said voltage level and a reversed level of said voltage level; and

a control circuit, coupled to said first plurality of switches, operable for generating said switching signal such that a first time interval during which said second sense signal is said original version and a second time interval during which said second sense signal is said reversed version have substantially the same time length.

2. The analog-to-frequency converting circuit of claim 1, wherein said control circuit counteracts error, caused by an input offset of said integral comparing circuit, in a count value by controlling said first and second time intervals to be substantially the same, and wherein said count value is obtained by counting a number of said trigger signals and represents an amount of accumulation of electric charges in said current.

3. The analog-to-frequency converting circuit of claim 1, wherein said integral comparing circuit comprises:
comparator circuitry operable for comparing said integral value with a first reference and a second reference that is less than said first reference, generating a first trigger signal if said integral value is greater than said first reference, and generating a second trigger signal if said integral value is less than said second reference, wherein said preset reference is one of said first and second references.

4. The analog-to-frequency converting circuit of claim 3, wherein if said first trigger signal is generated, then said compensation circuit provides compensation charges in a predetermined amount to said integral comparing circuit to decrease said integral value by a predetermined value, and wherein if said second trigger signal is generated, then said compensation circuit provides compensation charges in said predetermined amount to said integral comparing circuit to increase said integral value by a predetermined value.

5. The analog-to-frequency converting circuit of claim 1, wherein said capacitive component comprises a first terminal and a second terminal selectively coupled to a first terminal of said integral comparing circuit and a second terminal of said integral comparing circuit through said second plurality of switches, and wherein said control circuit controls said second plurality of switches such that if said first terminal of said capacitive component is coupled to said first terminal of said integral comparing circuit, then said second terminal of said capacitive component is coupled to said second terminal of said integral comparing circuit, and such that if said first terminal of said capacitive component is coupled to said second terminal of said integral comparing circuit, then said second terminal of said capacitive component is coupled to said first terminal of said integral comparing circuit.

6. The analog-to-frequency converting circuit of claim 1, wherein said compensation circuit comprises a filter circuit operable for passing compensation charges from said compensation circuit to said integral comparing circuit to change said integral value and reducing a change in said integral value caused by said compensation charges.

7. A coulomb counter comprising:
an analog-to-frequency converting circuit operable for converting a current to a train of trigger signals at a frequency indicative of said current, said analog-to-frequency converting circuit comprising:
a first plurality of switches operable for receiving a first sense signal indicative of said current and providing a second sense signal that alternates between an original version of said first sense signal and a reversed version of said first sense signal, under control of a switching signal;
an integral comparing circuit, coupled to said first plurality of switches, operable for integrating said second sense signal to generate an integral value, and operable for generating a trigger signal of said trigger signals when said integral value reaches a preset reference;
a compensation circuit, coupled to said integral comparing circuit, operable for compensating for said integral value with a predetermined value in response to each trigger signal of said trigger signals, wherein said compensation circuit comprises:
a capacitive component; and
a second plurality of switches, coupled to said capacitive component, operable for selectively connecting a voltage source to said capacitive component to charge said capacitive component so that said capacitive component has a voltage level of said voltage source, and selectively connecting said capacitive component to said integral comparing circuit so that said compensation circuit provides a compensation signal to compensate for said integral value, wherein said control circuit controls said second plurality of switches according to said trigger signals such that said compensation signal is selectively at said voltage level and a reversed level of said voltage level; and

a control circuit, coupled to said first plurality of switches, operable for generating said switching signal such that a first time interval during which said second sense signal is said original version and a second time interval during which said second sense signal is said reversed version have substantially the same time length; and

a counter, coupled to said analog-to-frequency converting circuit, operable for counting a number of said trigger signals to generate a count value representing an amount of accumulation of electric charges in said current.

8. The coulomb counter of claim 7, wherein said control circuit counteracts error, caused by an input offset of said integral comparing circuit, in said count value by controlling said first and second time intervals to be substantially the same.

9. The coulomb counter of claim 7, wherein said integral comparing circuit comprises:
comparator circuitry operable for comparing said integral value with a first reference and a second reference that is less than said first reference, generating a first trigger signal if said integral value is greater than said first reference, and generating a second trigger signal if said integral value is less than said second reference, wherein said preset reference is one of said first and second references.

10. The coulomb counter of claim 9, further comprising:
a first logic circuit, coupled to said comparator circuitry, operable for generating a polarity signal, setting said polarity signal to a first logic level on detection of said first trigger signal, and setting said polarity signal to a second logic level on detection of said second trigger signal, wherein said first and second logic levels are different; and
a second logic circuit, coupled to said first logic circuit and said control circuit, operable for generating a count-direction signal, setting said count-direction signal to a third logic level if a logic level of said polarity signal and a logic level of said switching signal are the same, and setting said count-direction signal to a fourth logic level if a logic level of said polarity signal and a logic level of said switching signal are different, wherein said third and fourth logic levels are different, and wherein said count-direction signal controls said counter to increase or decrease said count value when a trigger signal of said trigger signals is generated.

11. The coulomb counter of claim 9, wherein if said first trigger signal is generated, then said compensation circuit provides compensation charges in a predetermined amount to said integral comparing circuit to decrease said integral value by a predetermined value, and wherein if said second trigger signal is generated, then said compensation circuit provides compensation charges in said predetermined amount to said integral comparing circuit to increase said integral value by a predetermined value.

12. A method comprising:
generating a first sense signal indicative of a current;
providing a second sense signal that alternates between an original version of said first sense signal and a reversed version of said first sense signal;
integrating said second sense signal to generate an integral value;
generating a train of trigger signals, wherein each trigger signal of said trigger signals is generated when said integral value reaches a preset reference;
compensating for said integral value with a predetermined value in response to each trigger signal of said trigger signals, wherein said compensating comprises:
selectively connecting a voltage source to a capacitive component in a compensation circuit that performs said compensating, to charge said capacitive component so that said capacitive component has a voltage level of said voltage source;
selectively connecting said capacitive component to an integral comparing circuit that performs said integrating, so that said compensation circuit provides a compensation signal to compensate for said integral value; and
controlling said compensation signal to be selectively at said voltage level and a reversed level of said voltage level according to said trigger signals; and

controlling a first time interval during which said second sense signal is said original version and a second time interval during which said second sense signal is said reversed version to have substantially the same time length.

13. The method of claim 12, further comprising:
generating said trigger signals at a frequency indicative of said current.

14. The method of claim 12, further comprising:
counting a number of said trigger signals to generate a count value representing an amount of accumulation of electric charges in said current.

15. The method of claim 12, further comprising:
comparing said integral value with a first reference and a second reference that is less than said first reference;
generating a first trigger signal if said integral value is greater than said first reference; and
generating a second trigger signal if said integral value is less than said second reference,
wherein said preset reference is one of said first and second references.

16. The method of claim 15, further comprising:
setting a polarity signal to a first logic level on detection of said first trigger signal;
setting said polarity signal to a second logic level on detection of said second trigger signal, wherein said first and second logic levels are different;
setting a count-direction signal to a third logic level if a logic level of said polarity signal and a logic level of said switching signal are the same;
setting said count-direction signal to a fourth logic level if a logic level of said polarity signal and a logic level of said switching signal are different, wherein said third and fourth logic levels are different; and
controlling said counter to increase or decrease said count value when a trigger signal of said trigger signals is generated, according to said count-direction signal.

17. The method of claim 15, wherein said compensating comprises:
providing compensation charges in a predetermined amount to said integral comparing circuit to decrease said integral value by a predetermined value if said first trigger signal is generated; and
providing compensation charges in said predetermined amount to said integral comparing circuit to increase said integral value by a predetermined value if said second trigger signal is generated.