# Patent

## Title
Constant current source circuit

## Abstract

One current source includes a first transistor including a drain connected to an output terminal, and a source directly connected to a first power supply, a second transistor including a drain connected to a gate, the gate of the second transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third transistor opposite the first channel type including a drain connected to the drain of the second transistor, a fourth transistor including a drain connected to the source of the third transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third transistor.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Continuation application of U.S. patent application Ser. No. 14/149,773 which was filed on Jan. 7, 2014, now U.S. Pat. No. 9,152,164 which issued on Oct. 6, 2015, which is a Continuation application of U.S. patent application Ser. No. 12/285,089, which was filed on Sep. 29, 2008, now U.S. Pat. No. 8,648,585 which issued on Feb. 11, 2014, which are all incorporated herein by reference in their entirety.


BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to constant current source circuits that are used in integrated circuits and are produced by way of CMOS integrated circuit technologies.
The present application claims priority on Japanese Patent Application No. 2007-258529, the content of which is incorporated herein by reference.
Description of Related Art
It becomes difficult for engineers to determine lower limits for operation voltages of analog circuits due to demands for reducing operation voltages of LSI (Large Scale Integration) circuits used in electronic devices having reduced power consumptions.
This is greatly affected by the fact in which threshold voltages Vt for MOS (Metal Oxide Semiconductor) transistors will not be subjected to scaling relative to reductions of operation voltages.
For example, when the minimum output voltage of a constant current source is to be reduced, it is necessary to reduce the threshold voltage Vt of a MOS transistor in response to a reduction of the operation voltage.
However, there is a limit in reducing the threshold voltage Vt due to an increase of a leak current.
When low currents flow through MOS transistors each having a very large area so as to secure certain voltage margins by reducing voltages applied thereto, the manufacturing cost may be pushed up so as to cause demerits economically.
Various types of LSI circuits essentially incorporate constant current source circuits which have low current reductions in case of low voltages and which can stabilize currents in a relatively broad range of voltages.
Various types of constant current source circuits have been developed and disclosed in various documents such as Patent Document 1 and Patent Document 2.
Patent Document 1: Japanese Unexamined Patent Application Publication No. H04-160511
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-330657
As a first example of the circuitry (serving as a constant current source circuit), FIG. 13 shows a current mirror circuit, wherein a reference current I0 flows through an n-channel MOS transistor M100 subjected to diode connection in which the same potential is applied to the gate and drain, hence, VGS0=VDS0.
A MOS transistor M101 is used as the output of the constant current source circuit, wherein when the gate voltage VGS0 is identical to the drain voltage VDS0, the same operation condition is applied to both of the transistors M100 and M101. When they have the same dimensions regarding the factor L/W (where L designates the channel length, and W designates the channel width), an output current I1 becomes identical to the reference current I0 (see Patent Document 1).
When an output voltage VOUT becomes higher than the gate voltage VGS0, the effective channel length may decrease due to the channel length modifying effect of the transistor while the drain voltage of the transistor M101 increases, wherein the output current I1 increases relative to the reference current I0 so that I1>I0, whereby the same current does not flow through the transistors M100 and M101.
In contrast, when the output voltage VOUT becomes lower than the gate voltage VGS0, the output current I1 decreases so that I1<I0, wherein the same current does not flow through the transistors M100 and M101.
FIG. 14 shows an example of IDS-VDS characteristics of an n-channel MOS transistor (where IDS designates a drain-source current, and VDS designates a drain-source voltage), whereby an output resistance rOUT of the circuitry of FIG. 13 substantially matches a drain resistance rDS1 of the transistor M101 when the inverse of the slope of the drain current IDS in the saturation region is expressed as rDS=ΔVDS/ΔIDS (where rDS Designates a Drain resistance).
In order to suppress variations of the output current I1 dependent upon the output voltage VOUT, it is necessary to increase the output resistance rOUT, whereas the circuitry of FIG. 13 suffers from a problem in that the output resistance rOUT cannot be increased to be higher than the drain resistance rDS1.
In the case that I0=100 μA and rDS1=50 kΩ, for example, current variations of 20 μA occur responsive to voltage variations of 1 V; this causes relatively high current variations of 20%/V, resulting in an incapability of supplying a constant current at a high precision.
As a second example of the circuitry which is designed as the countermeasure to the circuitry of FIG. 13 by increasing the output resistance of a constant current source, FIG. 15 shows a cascode current mirror circuit constituted of transistors M100, M101, M102, and M103 (see Patent Document 2).
In the case of Patent Document 2, the gate potential of the transistor M101 is identical to the gate potential VGS0, while the gate potential of the transistor M103 is identical to the gate potential VGS0+VGS2 of the transistor M102.
In the saturation region of the transistor M103, the gate-source voltage VGS3 of the transistor M103 is identical to the gate-source voltage VGS2 of the transistor M102; hence, the drain potential of the transistor M101 becomes identical to the gate-source voltage VGS0 of the MOS transistor M100.
Since potential variations of the output terminal do not affect the drain voltage of the transistor M101, it is possible to increase the output resistance rOUT, thus stabilizing the output current.
By use of the drain resistance rDS3 and the mutual conductance gm3 of the transistor M103, gate-source voltage variations ΔVGS3 of the transistor M103 dependent upon output voltage variations ΔVOUT is expressed as follows:

ΔVGS3=ΔVOUT/(gm3·rDS3)

In the case that gm3=1 ms and rDS3=50 kΩ, for example, the above equation can be rewritten as ΔVGS3=ΔVOUT/50. This indicates that potential variations of the output terminal may affect the drain potential of the MOS transistor M100 by 1/50 of the actual variations.
The output resistance rOUT of the circuitry of FIG. 15 is expressed as follows:

rOUT=(gm3·rDS3)·rDS1 

Compared with the circuitry of FIG. 13, the circuitry of FIG. 15 provides (gm3·rDS3) times higher output resistance. In the case that I0=100 μA, rDS1=rDS3=50 kΩ, and gm3=1 mS, for example, the above equation produces rOUT=2.5 MΩ, wherein potential variations of 1 V may result in current variations of 0.4 μA; hence, output current variations can be suppressed as 0.4%/V.
However, the present inventor has recognized that, in the constant current source circuit disclosed in Patent Document 2, due to the relatively high gate potential VGS0+VGS2 of the transistor M103, the transistor M103 produces the minimum value of the output voltage, i.e. VOUT(min), during the operation in the saturation region.
VOUT(min)≧VGS0+VGS2−VT3 
This reduces the range of operation voltage of the transistor M103 by VGS2.
To cope with such a problem, as a further example of the constant current source circuit (having intermediate characteristics between the characteristics of Patent Document 1 and the characteristics of Patent Document 2), FIG. 16 shows a cascode current mirror circuit for use at a low voltage.
In the circuitry of FIG. 16 constituted of the four transistors M100 to M103, each of the drain voltages of the transistors M100 and M101 is expressed as VDS0=Vncas−VGS2 or VDS1=Vncas−VGS3 (where Vncas is a gate potential).
In the above, the drain voltages VDS0 and VDS1 are reduced by adjusting the gate potential Vncas with respect to the transistors M102 and M103, thus decreasing the lower limit of the operation voltage in a similar manner to the circuitry of FIG. 15.
Since both the drain voltages VDS0 and VDS1 are relatively low, both transistors M100 and M101 do not operate in the saturation region but in the linear region, wherein the characteristics thereof may be similar to resistance characteristics.
Since the drain voltages of the transistors M100 and M101 are maintained constant by way of the transistors M102 and M103, the circuitry of FIG. 16 is capable of operating as the constant current source.
The output resistance rOUT of the circuitry of FIG. 16 is identical to that of the circuitry of FIG. 15, where rOUT=(gm3·rDS3)·rDS1.
Compared with the circuitry of FIG. 15, the drain resistance rDS1 has a lower value in the circuitry of FIG. 16 that operates in the linear region. In the case that the current of 100 μA in which the gate potential Vncas is adjusted to achieve VDS1=200 mV, it is possible to calculate the drain resistance rDS1 by the following equation based on the approximation that the transistor M101 has a linear resistance.
rDS1=200 mV/100 μA=2 kΩ
In the case that rDS3=50 kΩ and gm3=1 mS (in a similar manner to the circuitry of FIG. 15), rOUT=100 kΩ, wherein current variations of 10 μA occur responsive to potential variations of 1 V; hence, it is possible to suppress output current variations by 10%/V.
The aforementioned calculations indicate that when the gate potential Vncas is intentionally reduced with respect to the transistors M102 and M103 in order to increase the lower-limit range of the operation voltage, the drain voltage VDS1 becomes low so that the drain resistance rDS1 correspondingly becomes low, thus reducing the output resistance rOUT.
In order to obtain the cascode effect in the aforementioned circuitries, it is necessary to establish a balance between the operation voltage and the output resistance by increasing the drain voltage VDS1.
In the case of the low-voltage cascode configuration, engineers cannot neglect a problem in that the range of the operation voltage is inevitably reduced by VDS1.
SUMMARY
The invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part.
In one embodiment, there is provided a constant current source circuit that includes a control voltage generation section for detecting the output voltage at the output terminal and for generating a control voltage based on the detected output voltage, a reference current adjustment section for adjusting a reference current based on the control voltage, and a current mirror section for outputting an output current responsive to the adjusted reference current at the output terminal.
In another embodiment, there is provided a constant current source circuit that includes a reference current adjustment section for adjusting a reference current based on the output voltage at the output terminal, and a current mirror section for outputting the output current in response to the adjusted reference current.
In the above, since the constant current source circuit of the present invention controls the reference current to be constant so as to reduce an influence of the output voltage to the output current at the output terminal, it is possible to reduce variations of the output current due to variations of the output voltage. Thus, the constant current source circuit is capable of supplying substantially the “constant” output current in the low-voltage range.



BRIEF DESCRIPTION OF THE DRAWINGS
The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram showing the constitution of a constant current source circuit according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing the detailed constitution of the constant current source circuit of FIG. 1;
FIG. 3 is a graph showing potential variations of nodes dependent upon variations of output voltage in the constant current source circuit;
FIG. 4 is a graph showing the relationship between the output voltage and the output current in connection with constant current source circuits of first and second embodiments;
FIG. 5 is a circuit diagram showing the constitution of a constant current source circuit according to a second embodiment of the present invention;
FIG. 6 is a circuit diagram showing the constitution of a constant current source circuit according to a third embodiment of the present invention;
FIG. 7 is a graph showing potential variations of nodes dependent upon variations of output voltage in the constant current source circuit of the third embodiment;
FIG. 8 is a graph showing the relationship between the output voltage and the output current in the constant current source circuit of the third embodiment;
FIG. 9 is a circuit diagram showing the constitution of a constant current source circuit according to a fourth embodiment of the present invention;
FIG. 10 is a circuit diagram showing the constitution of a constant current source circuit according to a fifth embodiment of the present invention;
FIG. 11 is a circuit diagram showing the constitution of a constant current source circuit according to a sixth embodiment of the present invention;
FIG. 12 is a circuit diagram showing the constitution of a constant current source circuit according to a seventh embodiment of the present invention;
FIG. 13 is a circuit diagram showing one example of the constant current source circuit adapted to a current mirror circuit;
FIG. 14 is a graph showing current-voltage characteristics of an n-channel MOS transistor;
FIG. 15 is a circuit diagram showing another example of the constant current source circuit adapted to a cascode current mirror circuit; and
FIG. 16 is a circuit diagram showing a further example of the constant current source circuit adapted to a cascode current mirror circuit for low voltage.



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The present invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
First Embodiment
Referring now to FIG. 1, a constant current source circuit according to a first embodiment of the present invention includes a bias generation section 1, a reference current adjustment section 2, a control voltage generation section 3, and a current mirror section 4.
Based on a reference current I0 caused by a constant current source 100, the bias generation section 1 generates a first bias voltage pbias and a second bias voltage pcas for use in the reference current adjustment section 2 as well as a third bias voltage ncas for use in the current mirror section 4.
The output voltage of an output terminal TOUT is applied to the control voltage generation section 3. The control voltage generation section 3 generates a control voltage oshift, which is produced by shifting a prescribed voltage from the output voltage. It outputs the control voltage oshift to the reference current adjustment section 2.
The reference current adjustment section 2 is constituted of p-channel MOS transistors M1, M2, and M3, which generates a current Im that is adjusted in response to the output voltage based on the first bias voltage pbias, the second bias voltage pcas, and the control voltage oshift.
The current mirror section 4 is a cascode current mirror circuit and is constituted of n-channel MOS transistors M4, M5, and M6A. It outputs a constant current I1 to the output terminal TOUT based on the current Im output from the reference current adjustment section 2.
Next, the detailed constitution of the constant current source circuit of FIG. 1 will be described with reference to FIG. 2. FIG. 2 is a circuit diagram showing the detailed constitution of the constant current source circuit of FIG. 1.
The bias generation section 1 is constituted of p-channel MOS transistors M10, M11, and M12 and n-channel MOS transistors M13 and M14. The source of the transistor M10 is connected to a voltage supply, while the gate and the drain of the transistor M10 are connected together.
The source of the transistor M11 is connected to the drain and gate of the transistor M10, while the gate and drain of the transistor M11 are grounded via the constant current source 100.
The source of the transistor M12 is connected to the voltage supply, while the gate of the transistor M12 is connected to the gate and drain of the transistor M10.
The drain and gate of the transistor M13 are connected to the drain of the transistor M12.
The drain and gate of the transistor M14 are connected to the source of the transistor M13.
In the above constitution, the drain of the transistor M10 outputs the first bias voltage pbias to the transistor M1 which is a p-channel MOS transistor serving as a constant current source transistor of a cascode current mirror circuit.
The drain of the transistor M11 outputs the second bias voltage pcas to the transistor M3, which is a p-channel MOS transistor serving as a cascode transistor of the current mirror circuit.
The drain of the transistor M13 outputs the third bias voltage ncas to the transistor M5, which is an n-channel MOS transistor serving as an n-channel cascode transistor of the current mirror circuit.
The control voltage generation section 3 is constituted of a p-channel MOS transistor M7 and n-channel MOS transistors M8 and M9.
The source of the transistor M7 is connected to the voltage supply, while the gate of the transistor M7 is connected to the gate and drain of the transistor M10.
The drain of the transistor M8 is connected to the drain of the transistor M7, while the gate of the transistor M8 is connected to the output terminal TOUT.
The drain of the transistor M9 is connected to the source of the transistor M8, the source of the transistor M9 is grounded, and the gate of the transistor M9 is supplied with an internal bias voltage mbias of the “cascode” current mirror section 4.
The source of the transistor M8 outputs the control voltage oshift as a gate bias to the gate of the transistor M2 in the reference current adjustment section 2.
As described above, the reference current adjustment section 2 is constituted of the transistors M1, M2, and M3.
The source of the transistor M1 is connected to the voltage supply, while the gate of the transistor M1 is connected to the gate and drain of the transistor M10 so as to receive the first bias voltage pbias.
The source of the transistor M2 is connected to the drain of the transistor M1, while the gate of the transistor M2 is connected to the source of the transistor M8 so as to receive the control voltage oshift.
The source of the transistor M3 is connected to the drain of the transistor M1, while the gate of the transistor M3 is connected to the gate and drain of the transistor M11 so as to receive the second bias voltage pcas. The drain of the transistor M3 is connected to the drain of the transistor M2.
As described above, the current mirror section 4 is constituted of the transistors M4, M5, and M6A.
The gate and drain of the transistor M4 are connected to the drain of the transistor M2, while the source of the transistor M4 is grounded, wherein the drain of the transistor M4 outputs the internal bias voltage mbias. In addition, the gate and drain of the transistor M4 are connected to the gate of the transistor M9, which thus receives the internal bias voltage mbias.
The drain of the transistor M5 is connected to the output terminal TOUT, while the gate of the transistor M5 is connected to the gate and drain of the transistor M13 so as to receive the third bias voltage ncas.
The drain of the transistor M6A is connected to the source of the transistor M5, while the gate of the transistor M6A is connected to the gate and drain of the transistor M4 so as to receive the internal bias voltage mbias. The source of the transistor M6A is grounded.
Next, the operation of the constant current source circuit of the first embodiment will be described with reference to FIG. 3. FIG. 3 shows simulation results of the constant current source circuit of FIG. 2, i.e., potential variations of nodes dependent upon variations of the output voltage in which the voltage supply is set to 1.5 V. The horizontal axis of the graph of FIG. 3 represents the potential (or output voltage) of the output terminal TOUT, and the vertical axis represents potentials of nodes in the constant current source circuit.
FIG. 3 apparently shows that the transistor M2 of the reference current adjustment section 2 is turned off when the control voltage oshift, which is produced by shifting the level of the output voltage of the output terminal TOUT in the control voltage generation section 3, is higher than the second bias voltage pcas generated by the bias generation section 1, wherein the potential of the drain “md” of the transistor M1 is clamped by the transistor M3 and therefore becomes identical to the first bias voltage pbias.
Since the transistors M1 and M3 are coupled together to form a cascode current mirror circuit, the current Im flowing through the MOS transistor M1 becomes identical to the reference current I0.
In contrast, the transistor M3 of the reference current adjustment section 2 is turned off when the control voltage oshift is lower than the second bias voltage pcas, wherein the potential of the drain md of the transistor M1 decreases following up with variations of the control voltage oshift.
That is, the transistor M2 forms a bypass path allowing a current to pass therethrough, wherein the source-drain voltage of the transistor M1 increases as the control voltage oshift decreases, so that the current Im flowing through the transistor M1 becomes higher than the reference current I0.
The dotted line vertically drawn in the center of the graph of FIG. 3 indicates the intersection point between the second bias voltage pcas and the control voltage oshift. In FIG. 3, the “stable” condition in which the relationship of Im=I0 is fixed is established in the region (where pcas≦oshift) to the right of the dotted line.
In the region (where pcas>oshift) to the left of the dotted line, the reference current adjustment section 2 adjusts the current Im based on the voltage difference between the first bias voltage pbias and the potential of the drain and of the transistor M1, thus establishing the relationship of Im>I0.
In short, the constant current source circuit of the first embodiment makes the current Im, which flows through the transistor M1 and which is adjusted based on the output voltage of the output terminal TOUT, flow through the transistor M4 of the current mirror section 4, thus producing the current I1 in response to the current Im from the output terminal TOUT.
FIG. 4 is a graph showing the relationship between the output voltage at the output terminal TOUT and the output current I1 in the constant current source circuit of the first embodiment. In FIG. 4, the horizontal axis represents the output voltage at the output terminal TOUT, while the vertical axis represents the output current I1 output from the output terminal TOUT.
In FIG. 4, a one-dashed curve C indicates the voltage-current characteristics of the first example of the circuitry (serving as the current mirror circuit) shown in FIG. 13, while a two-dashed curve D indicates the voltage-current characteristics of the second example of the circuitry (serving as the cascode current mirror circuit) shown in FIG. 15.
In relation to the curves C and D, a thin curve A indicates the voltage-current characteristics of the constant current source circuit of the first embodiment shown in FIG. 2.
In the characteristics D of the cascode current mirror circuit of FIG. 15, the transistor M103 cannot operate in the saturation region below the output voltage of 0.5 V so that the output resistance decreases so as to decrease the output current I1.
As shown in FIG. 4, in the constant current source circuit of the first embodiment, the transistor M2 turns on so as to compensate for a reduction of the current Im occurring due to a reduction of the output voltage at the output terminal TOUT, wherein the current Im flowing through the transistor M1 is increased so as to expand the operation region below the output voltage of 0.2 V or so.
Second Embodiment
Next, a constant current source circuit according to a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 5 is a circuit diagram showing the constitution of the constant current source circuit of the second embodiment.
Similar to the first embodiment, the constant current source circuit of the second embodiment is constituted of the bias generation section 1, the reference current adjustment section 2, the control voltage generation section 3, and the current mirror section 4.
In FIG. 5, parts identical to those of the first embodiment shown in FIG. 2 are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the second embodiment.
Based on the reference current I0 created by the constant current source 100, the bias generation section 1 generates and outputs the first bias voltage pbias and the second bias voltage peas for use in the reference current adjustment section 2 as well as the third bias voltage ncas and the fourth bias voltage nbias for use in the current mirror section 4.
The fourth bias voltage nbias is output from the drain of the transistor M14 of the bias generation section 1.
In the current mirror section 4, an n-channel MOS transistor M6B is connected in parallel to the transistor M6A, wherein it is an additional constituent element incorporated into the second embodiment compared to the first embodiment.
The drain of the transistor M6B is connected to the source of the transistor M5; the gate of the transistor M6B is connected to the drain and gate of the transistor M14 so as to receive the fourth bias voltage nbias; and the source of the transistor M6B is grounded.
The current flowing through the transistor M6A has the voltage-current characteristics indicated by the thin curve A shown in FIG. 4.
The current flowing through the transistor M6B has the voltage-current characteristics indicated by the two-dashed curve D (representing the cascode current mirror circuit) shown in FIG. 4.
By appropriately adjusting the voltage-current characteristics applied to the transistors M6A and M6B, it is possible to achieve the intermediate characteristics indicated by a bold curve B between the thin curve A and the two-dashed curve D in FIG. 4.
That is, the second embodiment of FIG. 5 is designed to adjust the voltage-current characteristics from the thin curve A (which shows “excessive” current compensation characteristics) to the bold curve B (which shows “flat” characteristics compared to the characteristics of the thin curve A).
Third Embodiment
Next, a constant current source circuit according to a third embodiment of the present invention will be described with reference to FIGS. 6 to 8. FIG. 6 is a circuit diagram showing the constitution of the constant current source circuit of the third embodiment. The third embodiment is designed to apply the reference current adjustment section 2 of the first embodiment to the low-voltage cascode current mirror circuit shown in FIG. 16.
The constant current source circuit of the third embodiment does not include the control voltage generation section 3 used in the first embodiment and is thus constituted of the bias generation section 1, the reference current adjustment section 2, and the current mirror section 4.
In FIG. 6, parts identical to those of the second embodiment shown in FIG. 5 are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with reference to the third embodiment.
Due to the absence of the control voltage generation section 3, the gate of the transistor M2 is directly connected to the output terminal TOUT and is thus applied with the output voltage.
The bias generation section 1 included in the third embodiment is designed differently from the bias generation section 1 of the first embodiment and is constituted of p-channel MOS transistors M15, M18, M21, and M22 and n-channel MOS transistor M16, M17, M19, M20, and M23 as well as the transistors M10, M11, and M12.
In FIG. 6, the source of the transistor M10 is connected to the voltage supply, and the gate of the transistor M10 is connected to the constant current source 100, which is grounded.
The source of the transistor M11 is connected to the drain of the transistor M10, and the drain of the transistor M11 is connected to the gate of the transistor M10 and is also connected to the constant current source 100, which is grounded.
In the above constitution, the transistors M10 and M11 generate the first bias voltage pbias based on the current I0 created by the constant current source 100.
The transistor M11 serving as a cascode transistor is arranged to maintain the current flowing through the transistor M10 constant.
Since the gate of the transistor M10 is connected to the drain of the transistor M11, the transistor M10 normally operates in the linear region.
The source of the transistor M12 is connected to the voltage supply, and the gate of the transistor M12 is connected to the gate of the transistor M10 and the drain of the transistor M11.
The source of the transistor M15 is connected to the drain of the transistor M12, and the gate of the transistor M15 is connected to the gate of the transistor M11.
The drain of the transistor M16 is connected to the drain of the transistor M15.
The drain of the transistor M17 is connected to the source of the transistor M16, the gate of the MOS transistor M17 is connected to the drain of the transistor M16, and the source of the transistor M17 is grounded.
In the above constitution, the transistors M12 and M15 form a current mirror circuit which makes the prescribed current corresponding to the reference current I0 flow through the transistors M16 and M17.
The transistors M16 and M17 generate the fourth bias voltage nbias.
The source of the transistor M18 is connected to the voltage supply, and the gate and drain of the transistor M18 are connected to the gates of the transistors M11 and M15.
The drain of the transistor M19 is connected to the gate and drain of the transistor M18, and the gate of the transistor M19 is connected to the gate of the transistor M16.
The drain of the transistor M20 is connected to the source of the transistor M19, and the gate of the transistor M20 is connected to the drain of the transistor M16 and the gate of the transistor M17. The source of the transistor M20 is grounded.
In the above constitution, the transistors M19 and M20 form a current mirror circuit which makes the prescribed current (corresponding to the current flowing through the transistor M17) flow through the transistor M18. By appropriately adjusting the size (or dimensions) of the transistor M18, they generate the second bias voltage pcas having the prescribed level.
The source of the transistor M21 is connected to the voltage supply, and the gate of the transistor M21 is connected to the gate of the transistor M10 and the drain of the transistor M11.
The source of the transistor M22 is connected to the drain of the transistor M21, and the gate of the transistor M22 is connected to the gate and drain of the transistor M18.
The gate and drain of the transistor M23 are connected to the drain of the transistor M22 and the gate of the transistor M19, and the source of the transistor M23 is grounded.
In the above constitution, the transistors M21 and M22 form a current mirror circuit which makes prescribed current (corresponding to the current flowing through the transistor M10) flow through the transistor M23. By appropriately adjusting the size (or dimensions) of the transistor M23, they generate the third bias voltage ncas having the prescribed level.
The drain of the transistor M11 outputs the first bias voltage pbias to the gate of the transistor M1 included in the reference current adjustment section 2.
The drain of the transistor M18 outputs the second bias voltage pcas to the gate of the transistor M3 included in the reference current adjustment section 2.
The drain of the transistor M23 outputs the third bias voltage ncas to the gate of the transistor M5 included in the current mirror section 4.
The drain of the transistor M16 outputs the fourth bias voltage nbias to the gate of the transistor MB6 included in the current mirror section 4.
As described above, the constant current source circuit of the third embodiment shown in FIG. 6 does not include the control voltage generation section 3, which is included in both of the first and second embodiments.
The reason why the control voltage generation section 3 is not arranged in the third embodiment is that the second bias voltage pcas is maintained at a relatively high level in the low-voltage cascode current mirror circuit.
If the third embodiment is designed in a similar manner to the first and second embodiment, the control voltage generation section 3 performs level shifting so as to supply the control voltage oshift, which is lower than the output voltage of the output terminal TOUT, to the gate of the transistor M2, wherein the intersecting point between the second bias voltage pcas and the control voltage oshift should be raised to a very high level compared to the output voltage of the output terminal TOUT.
In this case, the output current I1 should be excessively corrected in the stable region in which the output current I1 is not corrected any more.
In order to avoid the occurrence of the above phenomenon, the third embodiment is designed so as not to arrange the control voltage generation section 3 but to directly connect the output terminal TOUT to the gate of the transistor M2, wherein the output voltage of the output terminal TOUT is directly applied to the gate of the transistor M2.
Next, the operation of the constant current source circuit of the third embodiment will be described with reference to FIG. 7. FIG. 7 shows simulation results of the constant current source circuit of FIG. 6, wherein similar to FIG. 3, FIG. 7 shows variations of the output voltage which is produced based on the supply voltage of 1.5 V. In FIG. 7, the horizontal axis represents the output voltage of the output terminal TOUT, and the vertical axis represents potentials of various nodes.
In the region to the right of the intersecting point between the output voltage of the output terminal TOUT and the second bias voltage pcas in FIG. 7, the potential of the drain md of the transistor M1 is maintained to be substantially identical to the potential of the drain pd of the transistor M12, wherein the current Im flowing through the transistor M1 becomes identical to the current I0, i.e., Im=I0.
In the region to the left of the intersecting point in FIG. 7, the output voltage of the output terminal TOUT gets smaller in comparison with the second bias voltage pcas, wherein the difference between the potential of the drain pd of the transistor M12 and the potential of the drain md of the transistor M1 is additionally applied to the drain of the transistor M1; hence, Im>I0.
FIG. 8 is a graph showing the relationship between the output voltage of the output terminal TOUT and the output current I1 in the constant current source circuit of the third embodiment. In FIG. 8, the horizontal axis represents the output voltage of the output terminal TOUT, and the vertical axis represents the output current I1 output from the output terminal TOUT.
In FIG. 8, a bold line C indicates the voltage-current characteristics of the low-voltage cascode current mirror circuit. A dashed line A indicates the voltage-current characteristics of the constant current source circuit (excluding the transistor M6B) which outputs the current Im at 100%. A thin line B indicates the voltage-current characteristics of the constant current source circuit in which the transistor M6A outputs the current Im and I0 at 50% each.
FIG. 8 clearly shows that, in the constant current source circuit of the third embodiment compared to the low-voltage cascode current mirror circuit shown in FIG. 16, the transistor M2 turns on so as to compensate for a reduction of the current Im due to a reduction of the output voltage of the output terminal TOUT, wherein it is possible to expand the operation region below the output voltage of 0.2 V or so by increasing the current Im flowing through the transistor M1.
Fourth Embodiment
Next, a constant current source circuit according to a fourth embodiment of the present invention will be described with reference to FIG. 9. FIG. 9 is a circuit diagram showing the constitution of the constant current source circuit of the fourth embodiment, which is designed by eliminating the transistor M3 from the reference current adjustment section 2 compared to the reference current adjustment section 2 included in the constant current source circuit of the second embodiment shown in FIG. 5. Due to the elimination of the transistor M3, it is unnecessary to produce the second bias voltage pcas; hence, the transistor M11 is also eliminated from the bias generation section 1.
In FIG. 9, parts identical to those of the second embodiment shown in FIG. 5 are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the fourth embodiment.
The source of the transistor M10 is connected to the voltage supply, and the gate and drain of the transistor M10 are connected to the constant current source 100, which is grounded.
In the above constitution, when the output voltage of the output terminal TOUT increases to be higher in level, the source-drain voltage of the transistor M8 (configured of an n-channel MOS transistor) decreases so that the operating state of the constant current source circuit is changed from the saturation region to the linear region.
In the linear region, the transistor M8 cannot achieve the source-follower function. This is clearly shown in FIG. 3 in terms of the relationship between the control voltage oshift and the output voltage of the output terminal TOUT. In FIG. 3, the control voltage oshift is maintained in a flat manner above the output voltage of 1.1 V.
In the fifth embodiment in which the transistor M3 is eliminated from the second embodiment, the transistor M2 does not turn off even when the output voltage of the output terminal TOUT increases to be higher in level in the right region from the dotted line in FIG. 3 or FIG. 4. This makes it possible for the current Im to flow through the transistors M1 and M2.
In the region to the right of the dotted line in FIG. 4, the function for maintaining the constant current due to the cascode effect may disappear, whereby a tendency in which the output current I1 gradually decreases appears in the region to the right of the dotted line.
The fourth embodiment works effectively in the case in which the output voltage of the output terminal TOUT is used in only the low-level region in a similar manner to a tail current of a differential amplifier (not shown).
Fifth Embodiment
Next, a constant current source circuit according to a fifth embodiment of the present invention will be described with reference to FIG. 10. FIG. 10 is a circuit diagram showing the constitution of the constant current source circuit of the fifth embodiment.
In FIG. 10, parts identical to those of the second embodiment shown in FIG. 5 are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the fifth embodiment.
Instead of the internal bias voltage mbias of the current mirror section 4, the fourth bias voltage nbias is applied to the gate of the transistor M9 of the control voltage generation section 3 included in the constant current source circuit of the fifth embodiment compared to the second embodiment. The drain of the transistor M9 is connected to the source of the transistor M8, and the gate of the transistor M9 is connected to the gate and drain of the transistor M14.
When the internal bias voltage (or gate bias voltage) mbias is applied to the gate of the transistor M9, the drain current of the transistor M9 is forced to be maintained constant in the region to the left of the dotted line in FIG. 4 which occurs due to a reduction of the output voltage of the output terminal TOUT. This may excessively reduce the control voltage oshift.
Since the fourth bias voltage nbias is applied to the gate of the transistor M9, even when the output voltage of the output terminal TOUT decreases such that the control voltage oshift (which corresponds to the drain voltage of the transistor M9) also decreases, it is possible to moderate an excessive reduction of the control voltage oshift by way of a reduction of the drain current of the transistor M9, thus making it possible to relieve the output current I1 from further correcting.
Sixth Embodiment
Next, a constant current source circuit according to a sixth embodiment of the present invention will be described with reference to FIG. 11. FIG. 11 is a circuit diagram showing the constitution of the constant current source circuit of the sixth embodiment.
The sixth embodiment shown in FIG. 11 is designed to additionally introduce the control voltage generation section 3 into the third embodiment shown in FIG. 6. In FIG. 11, parts identical to those of the third embodiment shown in FIG. 6 are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the sixth embodiment.
The control voltage generation section 3 is constituted of n-channel MOS transistors M25 and M26 as well as the p-channel MOS transistors M7 and M8.
The source of the transistor M7 is connected to a voltage supply, and the gate of the transistor M7 is connected to the drain of the transistor M11.
The source of the transistor M8 is connected to the drain of the transistor M7, and the gate of the transistor M8 is connected to the output terminal TOUT.
The drain of the transistor M25 is connected to the drain of the transistor M8, and the gate of the transistor M25 is connected to the drain of the transistor M23 so as to receive the third bias voltage ncas.
The drain of the transistor M26 is connected to the source of the transistor M25, and the gate of the transistor M26 is connected to the drain of the transistor M16 so as to receive the fourth bias voltage nbias. The source of the transistor M26 is grounded.
In the above constitution, when the voltage higher than the output voltage of the output terminal TOUT is applied to the gate of the transistor M2, the dotted lines of FIGS. 7 and 8 are moved leftward so as to moderate the excessive correction, thus achieving the flat characteristics with respect to the output current I1.
Seventh Embodiment
FIG. 12 is a circuit diagram showing a constant current source circuit according to a seventh embodiment of the present invention. The seventh embodiment shown in FIG. 12 is designed to additionally insert resistors R1 and R2 in series between the source of the transistor M8 and the drain of the transistor M9 in the control voltage generation section 3 used in the second embodiment shown in FIG. 5. In addition, the connection point between the resistors R1 and R2 is connected to the gate of the transistor M2, whereby the voltage at the connection point is applied to the gate of the transistor M2 as the control voltage oshift.
Compared to the second embodiment, the seventh embodiment is designed to additionally insert the resistors R1 and R2 between the transistors M8 and M9, thus reducing the control voltage oshift. This moves the dotted lines of FIGS. 7 and 8 rightward so as to make the constant current source circuit of the seventh embodiment operate in a further low-voltage region.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.

## Claims

1. A method for providing a constant current output comprising:
mirroring a first reference current in a first current mirror having two transistors with sources connected to a first power supply voltage to provide current to an output terminal;
detecting the voltage at the output terminal; and
increasing the first reference current if the voltage difference between the voltage at the output terminal and the first power supply voltage is less than a predetermined voltage.

2. The method as claimed in claim 1, wherein the predetermined voltage is a voltage at which an output transistor of the first current mirror does not operate in the saturation region.

3. The method as claimed in claim 1, wherein the first power supply voltage is a ground supply voltage.

4. The method as claimed in claim 3, wherein the first current mirror comprises n-channel MOS transistors.

5. The method as claimed in claim 1, wherein the first current mirror comprises a cascode transistor connected to the output terminal.

6. The method as claimed in claim 1, further comprising mirroring a second reference current in a second current mirror having two transistors with sources connected to the first power supply voltage to provide current to the output terminal.

7. The method as claimed in claim 6, further comprising a cascode transistor connected between the output terminal and the first and second current mirrors.

8. The method as claimed in claim 1, further comprising mirroring a second reference current in a second current mirror having two transistors with sources connected to a second power supply voltage to provide the first reference current.

9. The method as claimed in claim 8, wherein the first power supply voltage is a ground supply voltage and the second power supply voltage is a positive supply voltage.

10. The method as claimed in claim 9, wherein the first current mirror comprises n-channel MOS transistors and the second current mirror comprises p-channel MOS transistors.

11. The method as claimed in claim 8, wherein the first current mirror and the second current mirror each comprise a cascode transistor connected to respective current mirror outputs.

12. The method as claimed in claim 8, further comprising increasing the voltage difference between the output of the second current mirror and the second power supply voltage when the voltage difference between the voltage at the output terminal and the first power supply voltage is less than the predetermined voltage.

13. The method as claimed in claim 12, further comprising shifting the voltage at the output terminal towards the first power supply voltage and applying the shifted voltage to a first cascode transistor at the output of the second current mirror.

14. The method as claimed in claim 13, further comprising applying a bias voltage to a second cascode transistor at the output of the second current mirror.