# Patent

## Title
Analog signal processing method for accurate single antenna direction finding

## Abstract

Embodiments are directed to receiving an incoming signal, converting, by an analog circuit, the signal to a discrete time signal, applying, by the analog circuit, a transformation algorithm to the discrete time signal to obtain frequency samples of the discrete time signal, applying, by the analog circuit, a cross correlation algorithm to the frequency samples to obtain a cross spectral density (CSD), detecting, by the analog circuit, phase slopes associated with the CSD, and calculating an angle of arrival (AoA) of the incoming signal based on the phase slopes.

## Background
BACKGROUND
The present disclosure relates to electronics, and more specifically, to analog signal processing used to determine an angle of arrival (AoA) of an incident wave on an array.
Determining an AoA of an incident wave or signal on an array is of interest in a variety of applications, such as radar and aerospace applications. For example, signals that are detected can be wideband in nature with a low signal-to-noise ratio (SNR) and subject to narrowband interference.
Current implementations for detecting signals accurately are digital in nature, cannot be ultra wideband due to limitations in analog-to-digital converter (ADC) technology, and are size, weight, power, and cost (SWAP-C) intensive. Other approaches in analog use multiple antennas to detect or get the AoA, resulting in a wide angle. Still other techniques use a phase slope of a cross spectral density (CSD). But, use of CSD has only been accomplished with digital circuitry, resulting in a SWAP-C penalty and limiting wideband operation.
SUMMARY
According to one embodiment, a method comprises: receiving an incoming signal, converting, by an analog circuit, the signal to a discrete time signal, applying, by the analog circuit, a transformation algorithm to the discrete time signal to obtain frequency samples of the discrete time signal, applying, by the analog circuit, a cross correlation algorithm to the frequency samples to obtain a cross spectral density (CSD), detecting, by the analog circuit, phase slopes associated with the CSD, and calculating an angle of arrival (AoA) of the incoming signal based on the phase slopes.
According to another embodiment, an apparatus comprises: a first analog circuit configured to generate frequency samples associated with a continuous incoming signal, a second analog circuit configured to obtain a cross spectral density (CSD) based on the frequency samples, a third analog circuit configured to detect phase slopes associated with the CSD, and a fourth circuit configured to calculate an angle of arrival (AoA) of the incoming signal based on the phase slopes.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.



BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts:
FIG. 1 is a block diagram of an exemplary system;
FIG. 2 illustrates a diagram of an exemplary sample-and-hold circuit;
FIG. 3 illustrates a diagram of an exemplary circuit configured to implement a fast Fourier transform algorithm;
FIG. 4 illustrates a diagram of an exemplary circuit of a cross correlator; and
FIG. 5 illustrates a flow chart of an exemplary method.



DETAILED DESCRIPTION
It is noted that various connections are set forth between elements in the following description and in the drawings (the contents of which are included in this disclosure by way of reference). It is noted that these connections in general and, unless specified otherwise, may be direct or indirect and that this specification is not intended to be limiting in this respect. In this respect, a coupling between entities may refer to either a direct or an indirect connection.
Exemplary embodiments of apparatuses, systems, and methods are described for determining or detecting an angle of arrival (AoA) associated with an incident wave or signal. Analog circuitry performs the detection of the AoA, resulting in a low size, weight, power, and cost (SWAP-C) implementation across a wide bandwidth (e.g., up to 20 GHz). In some embodiments, an analog correlator is constructed using wire delays and analog multipliers to apply a complex weight and sum. Sample-and-hold (S/H) circuits, potentially in combination with one or more amplifiers, are used to facilitate a discrete time analog fast Fourier transform (FFT). A direction filter is implemented in analog to calculate a direction-filtered cross spectral density (CSD). A phase slope of the CSD is used to calculate AoA. Some or all of the implementation is conducted in analog and/or at radio frequency (RF). In some embodiments, the AoA is detected or calculated to within 1 degree of accuracy.
Referring to FIG. 1, a system 100 is shown. The system 100 determines or detects an AoA associated with an incoming wave or signal. The incoming signal may be an RF signal and may be continuous in nature.
The incoming signal is incident upon one or more sub-arrays, such as sub-array 1 and sub-array 2 in FIG. 1. The sub-arrays correspond to spatially-separated antennas or antenna elements. The incoming signal is incident upon a first of the sub-arrays (e.g., sub-array 1) at a first time that is different from (e.g., earlier than) a second time that the incoming signal is incident upon one or more other sub-arrays (e.g., sub-array 2).
Sub-array 1 and sub-array 2 are coupled to receivers 106-1 and 106-2, respectively. The receivers 106-1 and 106-2 receive the incoming signal. The receivers 106-1 and 106-2 may include components or devices of a type known to one of skill in the art, such as low noise amplifiers (LNAs), frequency down-converters, and the like.
The receivers 106-1 and 106-2 are coupled to S/H circuits 112-1 and 112-2, respectively. As shown in FIG. 2, the S/H circuits 112-1 and 112-2 are configured to turn the received, continuous signal into a discrete time signal or samples of a discrete time signal based on an application of a number ‘N’ of clocks, denoted as Clk1, Clk2, Clk3, . . . ClkN, to one or more sample-and-hold amplifiers (SHAs). A clock divider 204 generates one or more of the clocks Clk1, Clk2, Clk3, . . . ClkN based on a division of an input master clock. The S/H circuits 112-1 and 112-2 may implement a serial-to-parallel conversion.
Referring back to FIG. 1, the S/H circuits 112-1 and 112-2 are coupled to fast Fourier transform (FFT) circuits 118-1 and 118-2, respectively. The FFT circuits 118-1 and 118-2 may be implemented as an ‘n’-point FFT, where the value for ‘n’ is set by a frequency resolution that may be required in a given application or environment.
As shown in FIG. 3, the FFT circuits 118-1 and 118-2 of FIG. 1 may include a FFT signal flow graph (SFG) 302. The SFG 302 generates and outputs frequency samples corresponding to the discrete time samples generated by the S/H circuits 112. The outputs of the SFG 302 are provided to an equalizer 324. The equalizer 324 is configured to strengthen (e.g., boost) or weaken (e.g., cut) the energy of specific frequencies or frequency bands. The output of the equalizer 324 is coupled to a parallel to serial converter 340. The parallel-to-serial converter 340 generates a constant stream output. The parallel-to-serial converter 340 includes clocked SHAs similar to those described above in connection with the S/H circuits 112-1 and 112-2.
Referring back to FIG. 1, the FFT circuits 118-1 and 118-2 are coupled to a cross correlator circuit 124. The output of a first of the FFT circuits (e.g., FFT circuit 118-1) is subject to an amplifier or phase shift circuit 130 relative to the output of a second of the FFT circuits (e.g., FFT circuit 118-2). The circuit 130 generates the complex conjugate of the output of one FFT circuit relative to the other FFT circuit. The output of the cross correlator provides the CSD.
Referring to FIG. 4, an embodiment of the cross correlator circuit 124 is shown. The inputs to the cross correlator 124 are subject to one or more intermediate frequency (IF) amplifiers, such as amplifiers 402-1 and 402-2. A phase shift 414 of, e.g., 90 degrees is introduced in the output of one of the amplifiers (e.g., amplifier 402-1). The signals are subject to one or more lengths of line, where the length of the line results in a delay in signal in the analog domain. In FIG. 4, the various lines are shown as a 16-way split. Multiplier circuits (denoted as boxes 432) are present at various points along the lines.
An embodiment of a multiplier circuit 432 is shown in box 444 of FIG. 4. The multiplier circuit 432/444 includes one or more transistors arranged as shown. An input current (denoted as Iin2) is transduced into a voltage weight (Vin2). A second input current (denoted as Iin1) is multiplied by weight Vin2 and calibrated by a programmable floating gate to generate an output current (Iout) that is equal to, or proportional to, the product of the input currents Iin1 and Iin2. Thus, Iout is a function of currents Iin1 and Iin2. Of course, other techniques for performing multiplication could be used, such as a charge domain multiply or voltage domain multiply. In some embodiments, a charge is held on a gate of one of the transistors using a digital to analog converter (DAC) with a constant value wired to the gate.
Referring back to FIG. 1, the cross correlator circuit 124 is coupled to one or more phase detect circuits 136-1 and 136-2. The output of the cross-correlator 124 is subject to a S/H circuit 142 with respect to one of the phase detect circuits (e.g., phase detect circuit 136-2). The phase detect circuits 136-1 and 136-2 are configured to detect a phase slope of the CSD. The outputs of the phase detect circuits 136-1 and 136-2 are subtracted 148 from one another, which provides an indication of the AoA of the incoming or incident wave or signal.
Referring now to FIG. 5, a flow chart of an exemplary method 500 is shown. The method 500 may execute in accordance with one or more devices, components, or systems, such as those described herein. The method 500 is used to determine an AoA associated with an incoming or incident wave or signal.
In block 502, the incoming signal is received. For example, one or more sub-arrays or elements, such as one or more antennas or antenna elements, receives the incoming signal.
In block 504, the received signal is converted to a discrete time signal or discrete time signal samples. As part of block 504, the received signal is subject to serial-to-parallel conversion.
In block 506, a FFT algorithm is applied to the discrete time signal or discrete time signal samples. In this manner, a transition is made from a discrete time analog domain to a discrete time complex domain. The FFT algorithm is applied to obtain frequency components or samples.
In block 508, the output of the FFT algorithm of block 506 is applied to a cross correlation algorithm. The cross correlation algorithm is applied to obtain the CSD.
In block 510, one or more phase slopes of the CSD is detected.
In block 512, a difference in the phase slopes of block 510 is calculated to generate the AoA.
Embodiments of the disclosure include analog circuits configured to calculate a CSD and phase slope of the CSD. The analog circuits may operate in conjunction with one or more frequency bands, such as the X-band and the Ku band. The analog circuits may be ultra wideband and may operate from direct current (DC) to 12 GHz and beyond. The analog circuits use several orders of magnitude less power than corresponding digital circuits.
In some embodiments various functions or acts may take place at a given location and/or in connection with the operation of one or more apparatuses, systems, or devices. For example, in some embodiments, a portion of a given function or act is performed at a first device or location, and the remainder of the function or act is performed at one or more additional devices or locations.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
While the preferred embodiments to the invention have been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

## Claims

1. A method comprising:
receiving an incoming signal;
converting, by an analog circuit, the signal to a discrete time signal;
applying, by the analog circuit, a transformation algorithm to the discrete time signal to obtain frequency samples of the discrete time signal;
applying, by the analog circuit, a cross correlation algorithm to the frequency samples to obtain a cross spectral density (CSD), the cross correlation algorithm comprising application of a plurality of lines of differing length to generate delay in an analog domain;
detecting, by the analog circuit, phase slopes associated with the CSD; and
calculating, via an electronic analog direction filter, an angle of arrival (AoA) of the incoming signal based on the phase slopes,
wherein each of the plurality of lines is associated with a multiply circuit.

2. The method of claim 1, wherein the AoA is calculated by the analog circuit based on a difference in the phase slopes.

3. The method of claim 1, wherein the transformation algorithm comprises a fast Fourier transform (FFT).

4. The method of claim 1, wherein the incoming signal is received by a plurality of sub-arrays.

5. The method of claim 1, wherein the discrete time signal is generated using a sample-and-hold circuit that performs serial-to-parallel conversion.

6. The method of claim 1, wherein the multiply circuit comprises three transistors that generate an output current as a function of a product of two input currents.

7. The method of claim 6, wherein one of the transistors comprises a programmable floating gate or wherein a charge is held on a gate of one of the transistors using a digital to analog converter with a constant value wired to the gate.

8. An apparatus comprising:
a first analog circuit configured to generate frequency samples associated with a continuous incoming signal;
a second analog circuit configured to obtain a cross spectral density (CSD) based on the frequency samples, the second analog is configured to obtain the CSD based on an application of a plurality of lines of differing length to generate delay in an analog domain;
a third analog circuit configured to detect phase slopes associated with the CSD; and
a fourth circuit configured to calculate an angle of arrival (AoA) of the incoming signal based on the phase slopes,
wherein each of the plurality of lines is associated with a multiply circuit.

9. The apparatus of claim 8, wherein the first analog circuit is configured to apply a Fourier transform (FT) algorithm to a discrete time representation of the incoming signal.

10. The apparatus of claim 8, wherein the multiply circuit comprises three transistors configured to generate an output current as a function of a product of two input currents.

11. The apparatus of claim 10, wherein the multiply circuit is configured to transduce a first of the two input currents into a voltage weight.

12. The apparatus of claim 11, wherein a second of the two input currents is multiplied by the voltage weight and calibrated by a programmable floating gate to generate the output current.

13. The apparatus of claim 8, further comprising:
at least one array coupled to receivers configured to receive the incoming signal; and
respective sample-and-hold circuits coupled to one of each of the receivers and the first analog circuit, wherein each of the sample-and-hold circuits is configured to generate a discrete time representation of the incoming signal.

14. The apparatus of claim 13, wherein the at least one array comprises at least two sub-arrays.

15. The apparatus of claim 8, wherein a first output of the first analog circuit coupled to the second analog circuit corresponds to a complex conjugate of a second output of the first analog circuit coupled to the second analog circuit.