# Patent

## Title
Systems and methods for regulating output currents of power conversion systems

## Abstract

Systems and methods are provided for regulating a power conversion system. An example system controller includes: a signal generator configured to receive a converted signal and a first compensation signal and generate a second compensation signal based at least in part on the converted signal and the first compensation signal, the converted signal being associated with an input signal for a power conversion system; a modulation component configured to receive the second compensation signal and a ramping signal and generate a modulation signal based at least in part on the second compensation signal and the ramping signal; and a drive component configured to receive the modulation signal and output a drive signal based at least in part on the modulation signal to a switch to affect the first current, the drive signal being associated with an on-time period, the switch being closed during the on-time period.

## Background
1. CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority to Chinese Patent Application No. 201510413940.8, filed Jul. 15, 2015, incorporated by reference herein for all purposes. In addition, this application is a continuation-in-part of U.S. patent application Ser. No. 14/272,323, filed May 7, 2014, claiming priority to Chinese Patent Application No. 201410157557.6, filed Apr. 18, 2014, both of these applications being incorporated by reference herein for all purposes.


2. BACKGROUND OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for current regulation. Merely by way of example, the invention has been applied to power conversion systems in quasi-resonance mode. But it would be recognized that the invention has a much broader range of applicability.
Light emitting diodes (LEDs) are widely used for lighting applications. Oftentimes, approximately constant currents are used to control working currents of LEDs to achieve constant brightness. FIG. 1 is a simplified diagram showing a conventional power conversation system for LED lighting. The power conversion system 100 includes a controller 102, resistors 104, 124, 126 and 132, capacitors 106, 120 and 134, a diode 108, a transformer 110 including a primary winding 112, a secondary winding 114 and an auxiliary winding 116, a power switch 128, a current sensing resistor 130, and a rectifying diode 118. The controller 102 includes terminals (e.g., pins) 138, 140, 142, 144, 146 and 148. For example, the power switch 128 is a bipolar junction transistor. In another example, the power switch 128 is a MOS transistor.
An alternate-current (AC) input voltage 152 is applied to the system 100. A bulk voltage 150 (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage 152 is received by the resistor 104. The capacitor 106 is charged in response to the bulk voltage 150, and a voltage 154 is provided to the controller 102 at the terminal 138 (e.g., terminal VCC). If the voltage 154 is larger than a predetermined threshold voltage in magnitude, the controller 102 begins to operate normally, and outputs a drive signal 156 through the terminal 142 (e.g., terminal GATE). For example, the drive signal 156 is a pulse-width-modulation (PWM) signal with a switching frequency and a duty cycle. The switch 128 is closed (e.g., being turned on) or open (e.g., being turned off) in response to the drive signal 156 so that the output current 158 is regulated to be approximately constant.
The auxiliary winding 116 charges the capacitor 106 through the diode 108 when the switch 128 is opened (e.g., being turned off) in response to the drive signal 156 so that the controller 102 can operate normally. For example, a feedback signal 160 is provided to the controller 102 through the terminal 140 (e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding 118 for charging or discharging the capacitor 134 using an internal error amplifier in the controller 102. In another example, the feedback signal 160 is provided to the controller 102 through the terminal 140 (e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding 118. The resistor 130 is used for detecting a primary current 162 flowing through the primary winding 112, and a current-sensing signal 164 is provided to the controller 102 through the terminal 144 (e.g., terminal CS) to be processed during each switching cycle. Peak magnitudes of the current-sensing signal 164 are sampled and provided to the internal error amplifier. The capacitor 120 is used to maintain an output voltage 168 so as to keep a stable output current through an output load (e.g., one or more LEDs 122). For example, the system 100 operates in a quasi-resonant mode.
FIG. 2 is a simplified conventional diagram showing the controller 102 as part of the system 100. The controller 102 includes a ramp-signal generator 202, an under-voltage lock-out (UVLO) component 204, a modulation component 206, a logic controller 208, a driving component 210, a demagnetization detector 212, an error amplifier 216, and a current-sensing component 214.
As shown in FIG. 2, the UVLO component 204 detects the signal 154 and outputs a signal 218. If the signal 154 is larger than a first predetermined threshold in magnitude, the controller 102 begins to operate normally. If the signal 154 is smaller than a second predetermined threshold in magnitude, the controller 102 is turned off. The second predetermined threshold is smaller than the first predetermined threshold in magnitude. The error amplifier 216 receives a signal 220 from the current-sensing component 214 and a reference signal 222 and outputs an amplified signal 224 to the modulation component 206. The modulation component 206 also receives a signal 228 from the ramp-signal generator 202 and outputs a modulation signal 226. For example, the signal 228 is a ramping signal and increases, linearly or non-linearly, to a peak magnitude during each switching period. The logic controller 208 processes the modulation signal 226 and outputs a control signal 230 to the driving component 210 which generates the signal 156 to turn on or off the switch 128. For example, the demagnetization detector 212 detects the feedback signal 160 and outputs a signal 232 for determining the end of the demagnetization process of the secondary winding 114. In another example, the demagnetization detector 212 detects the feedback signal 160 and outputs the signal 232 for determining the beginning and the end of the demagnetization process of the secondary winding 114. In addition, the demagnetization detector 212 outputs a trigger signal 298 to the logic controller 208 to start a next cycle. The controller 102 is configured to keep an on-time period associated with the modulation signal 226 approximately constant for a given output load.
The controller 102 is operated in a voltage-mode where, for example, the signal 224 from the error amplifier 216 and the signal 228 from the oscillator 202 are both voltage signals and are compared by the comparator 206 to generate the modulation signal 226 to drive the power switch 128. Therefore, an on-time period associated with the power switch 128 is determined by the signal 224 and the signal 228.
FIG. 3 is a simplified conventional diagram showing the current-sensing component 214 and the error amplifier 216 as parts of the controller 102. The current-sensing component 214 includes a switch 302 and a capacitor 304. The error amplifier 216 includes switches 306 and 308, an operational transconductance amplifier (OTA) 310.
As shown in FIG. 3, the current-sensing component 214 samples the current-sensing signal 164 and the error amplifier 216 amplifies the difference between the signal 220 and the reference signal 222. Specifically, the switch 302 is closed (e.g., being turned on) or open (e.g., being turned off) in response to a signal 314 in order to sample peak magnitudes of the current-sensing signal 164 in different switching periods. If the switch 302 is closed (e.g., being turned on) in response to the signal 314 and the switch 306 is open (e.g., being turned off) in response to the signal 232 from the demagnetization detector 212, the capacitor 304 is charged and the signal 220 increases in magnitude. If the switch 306 is closed (e.g., being turned on) in response to the signal 232, the switch 308 is open (e.g., being turned off) in response to a signal 312 and the difference between the signal 220 and the reference signal 222 is amplified by the amplifier 310. The signal 312 and the signal 232 are complementary to each other. For example, during the demagnetization process of the secondary winding 114, the signal 232 is at a logic high level. The switch 306 remains closed (e.g., being turned on) and the switch 308 remains open (e.g., being turned off). The OTA 310, together with the capacitor 134, performs integration associated with the signal 220.
Under stable normal operations, an average output current is determined, according to the following equation, without taking into account any error current:




  
    
      
        
          
            I
            o
          
          _
        
        =
        
          
            1
            2
          
          ×
          N
          ×
          
            
              V
              ref_ea
            
            
              R
              
                c
                ⁢
                
                  
                
                ⁢
                s
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        )
      
    
  




where N represents a turns ratio between the primary winding 112 and the secondary winding 114, Vref_ea represents the reference signal 222 and Rcs represents the resistance of the resistor 130. As shown in Equation 1, the parameters associated with peripheral components, such as N and Rcs, can be properly selected through system design to achieve output current regulation.

For LED lighting, efficiency, power factor and total harmonic are also important. For example, efficiency is often needed to be as high as possible (e.g., >90%), and a power factor is often needed to be greater than 0.9. Moreover, total harmonic distortion is often needed to be as low as possible (e.g., <10%) for some applications. But the system 100 often cannot satisfy all these needs.
Hence it is highly desirable to improve the techniques of regulating output currents of power conversion systems.



3. BRIEF SUMMARY OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for current regulation. Merely by way of example, the invention has been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.
According to one embodiment, a system controller for regulating a power conversion system includes a first controller terminal and a second controller terminal. The first controller terminal is configured to receive a first signal associated with an input signal for a primary winding of a power conversation system. The second controller terminal is configured to output a drive signal to a switch to affect a first current flowing through the primary winding of the power conversion system, the drive signal being associated with an on-time period, the switch being closed during the on-time period. The system controller is configured to adjust a duration of the on-time period based on at least information associated with the first signal.
According to another embodiment, a system controller for regulating a power conversion system includes a first controller terminal, a ramp-signal generator, and a second controller terminal. The first controller terminal is configured to provide a compensation signal based on at least information associated with a first current flowing through a primary winding of a power conversion system. The ramp-signal generator is configured to receive a first signal associated with the compensation signal and generate a ramping signal based on at least information associated with the first signal, the ramping signal being associated with a ramping slope. The second controller terminal is configured to output a drive signal to a switch based on at least information associated with the ramping signal to affect the first current. The system controller is configured to adjust the ramping slope of the ramping signal based on at least information associated with the compensation signal.
According to yet another embodiment, a method for regulating a power conversion system includes: receiving a first signal from a first controller terminal, the first signal being associated with an input signal for a primary winding of a power conversation system; adjusting a duration of an on-time period related to a drive signal based on at least information associated with the first signal; and outputting the drive signal from a second controller terminal to a switch to affect a first current flowing through the primary winding of the power conversion system, the switch being closed during the on-time period.
According to yet another embodiment, a method for regulating a power conversion system includes: providing a compensation signal by a first controller terminal based on at least information associated with a first current flowing through a primary winding of a power conversion system; generating a first signal based on at least information associated with the compensation signal; and processing information associated with the first signal. The method further includes: adjusting a ramping slope associated with a ramping signal based on at least information associated with the first signal; receiving the ramping signal; generating a drive signal based on at least information associated with the ramping signal; and outputting the drive signal from a second controller terminal to a switch to affect the first current.
In one embodiment, a system controller for regulating a power conversion system includes: a signal generator configured to receive a converted signal and a first compensation signal and generate a second compensation signal based at least in part on the converted signal and the first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system; a modulation component configured to receive the second compensation signal and a ramping signal and generate a modulation signal based at least in part on the second compensation signal and the ramping signal; and a drive component configured to receive the modulation signal and output a drive signal based at least in part on the modulation signal to a switch to affect the first current, the drive signal being associated with an on-time period, the switch being closed during the on-time period. The system controller is configured to adjust a duration of the on-time period based at least in part on the converted signal and the second compensation signal.
In another embodiment, a method for regulating a power conversion system includes: receiving a converted signal and a first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system; generating a second compensation signal based at least in part on the converted signal and the first compensation signal; receiving the second compensation signal and a ramping signal; generating a modulation signal based at least in part on the second compensation signal and the ramping signal; receiving the modulation signal; and outputting a drive signal based at least in part on the modulation signal to affect the first current, the drive signal being associated with an on-time period. The outputting a drive signal based at least in part on the modulation signal to affect the first current includes adjusting a duration of the on-time period based at least in part on the converted signal and the second compensation signal.
Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.
4. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram showing a conventional power conversation system for LED lighting.
FIG. 2 is a simplified conventional diagram showing a controller as part of the system as shown in FIG. 1.
FIG. 3 is a simplified conventional diagram showing the current-sensing component and the error amplifier as parts of the controller as shown in FIG. 2.
FIG. 4(a) is a simplified diagram showing a power conversion system according to an embodiment of the present invention.
FIG. 4(b) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 4(a) according to an embodiment of the present invention.
FIG. 4(c) is a simplified timing diagram for a controller as part of a power conversion system as shown in FIG. 4(a) according to an embodiment of the present invention.
FIG. 4(d) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 4(a) according to another embodiment of the present invention.
FIG. 5(a) is a simplified diagram showing a power conversion system according to another embodiment of the present invention.
FIG. 5(b) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 5(a) according to an embodiment of the present invention.
FIG. 5(c) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 5(a) according to another embodiment of the present invention.
FIG. 6(a) is a simplified diagram showing a power conversion system according to yet another embodiment of the present invention.
FIG. 6(b) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 6(a) according to an embodiment of the present invention.
FIG. 7(a) is a simplified diagram showing a power conversion system according to yet another embodiment of the present invention.
FIG. 7(b) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 7(a) according to an embodiment of the present invention.
FIG. 7(c) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 7(a) according to another embodiment of the present invention.
FIG. 8(a) is a simplified diagram showing certain components as part of a controller as shown in FIG. 4(b), a controller as shown in FIG. 5(b), and/or a controller as shown in FIG. 7(b) according to some embodiments of the present invention.
FIG. 8(b) is a simplified diagram showing certain components as part of a controller as shown in FIG. 4(d), a controller as shown in FIG. 5(c), and/or a controller as shown in FIG. 7(c) according to certain embodiments of the present invention.
FIG. 8(c) is a simplified diagram showing certain components as part of a controller as shown in FIG. 6(b) according to another embodiment of the present invention.
FIG. 9 is a simplified diagram showing certain components of a controller according to yet another embodiment of the present invention.
FIG. 10(a) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 4(a) according to yet an embodiment of the present invention.
FIG. 10(b) is a simplified timing diagram for a controller as part of a power conversion system as shown in FIG. 4(a) according to another embodiment of the present invention.
FIG. 10(c) is a simplified diagram showing certain components of a controller as part of a power conversion system as shown in FIG. 4(a) according to another embodiment of the present invention.
FIG. 11(a) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 5(a) according to yet an embodiment of the present invention.
FIG. 11(b) is a simplified diagram showing certain components of a controller as part of a power conversion system as shown in FIG. 5(a) according to another embodiment of the present invention.
FIG. 12(a) is a simplified diagram showing a controller as part of a power conversion system as shown in FIG. 7(a) according to yet an embodiment of the present invention.
FIG. 12(b) is a simplified diagram showing certain components of a controller as part of a power conversion system as shown in FIG. 7(a) according to another embodiment of the present invention.



5. DETAILED DESCRIPTION OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for current regulation. Merely by way of example, the invention has been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.
FIG. 4(a) is a simplified diagram showing a power conversion system according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system 400 includes a controller 402, resistors 404, 424, 426, 432, 466 and 498, capacitors 406, 420, 434 and 470, a diode 408, a transformer 410 including a primary winding 412, a secondary winding 414 and an auxiliary winding 416, a power switch 428, a current sensing resistor 430, and a rectifying diode 418. The controller 402 includes terminals (e.g., pins) 438, 440, 442, 444, 446, 448 and 464. For example, the power switch 428 includes a bipolar junction transistor. In another example, the power switch 428 includes a MOS transistor. In yet another example, the power switch 428 includes an insulated-gate bipolar transistor. The system 400 provides power to an output load 422, e.g., one or more LEDs. In some embodiments, the resistor 432 is removed. For example, the system 400 operates in a quasi-resonant mode.
According to one embodiment, an alternate-current (AC) input voltage 452 is applied to the system 400. For example, a bulk voltage 450 (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage 452 is received by the resistor 404. In another example, the capacitor 406 is charged in response to the bulk voltage 450, and a voltage 454 is provided to the controller 402 at the terminal 438 (e.g., terminal VCC). In yet another example, if the voltage 454 is larger than a predetermined threshold voltage in magnitude, the controller 402 begins to operate normally, and outputs a signal through the terminal 442 (e.g., terminal GATE). In yet another example, the switch 428 is closed (e.g., being turned on) or open (e.g., being turned off) in response to a drive signal 456 so that the output current 458 is regulated to be approximately constant.
According to another embodiment, the auxiliary winding 416 charges the capacitor 406 through the diode 408 when the switch 428 is opened (e.g., being turned off) in response to the drive signal 456 so that the controller 402 can operate normally. For example, a feedback signal 460 is provided to the controller 402 through the terminal 440 (e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding 414 for charging or discharging the capacitor 434 using an internal error amplifier in the controller 402. In another example, the feedback signal 460 is provided to the controller 402 through the terminal 440 (e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding 414. As an example, the capacitor 434 is charged or discharged in response to a compensation signal 474 at the terminal 448 (e.g., terminal COMP). In another example, the resistor 430 is used for detecting a primary current 462 flowing through the primary winding 412, and a current-sensing signal 496 is provided to the controller 402 through the terminal 444 (e.g., terminal CS) to be processed during each switching cycle. In yet another example, peak magnitudes of the current-sensing signal 496 are sampled and provided to the internal error amplifier. In yet another example, the capacitor 434 is coupled to an output terminal of the internal error amplifier. In yet another example, the capacitor 420 is used to maintain an output voltage 468.
According to yet another embodiment, the bulk voltage 450 is sensed by the controller 402 through the terminal 464 (e.g., terminal VAC). For example, the controller 402 includes a ramp-signal generator which generates a ramping signal, and the controller 402 is configured to change the ramping slope of the ramping signal based on at least information associated with a signal 472 related to the bulk voltage 450. In another example, an on-time period associated with the drive signal 456 varies based on at least information associated with the signal 450. As an example, the duration of the on-time period increases when the bulk voltage 450 is at a peak magnitude. In another example, the duration of the on-time period decreases when the bulk voltage 450 is at a valley magnitude. The signal 472 is determined according to the following equation:




  
    
      
        VAC
        =
        
          
            
              R
              9
            
            
              
                R
                8
              
              +
              
                R
                9
              
            
          
          ×
          
            V
            bulk
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        )
      
    
  
  
    
      
        
          V
          bulk
        
        =
        
          
          
            A
            ⁢
            
              
            
            ⁢
            
              sin
              ⁡
              
                (
                
                  
                    ω
                    ⁢
                    
                      
                    
                    ⁢
                    t
                  
                  +
                  φ
                
                )
              
            
          
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        )
      
    
  




where VAC represents the signal 472, Vbulk represents the bulk voltage 450, R8 represents a resistance of the resistor 466, and R9 represents a resistance of the resistor 498. In addition, A represents a magnitude, ω represents a frequency, and φ represents a phase angle. In some embodiments, the controller is configured to adjust the ramping signal based on information associated with both the signal 472 and the compensation signal 474. In certain embodiments, the controller 402 is configured to adjust the ramping slope of the ramping signal based on information associated with the signal 472 or the compensation signal 474.

FIG. 4(b) is a simplified diagram showing the controller 402 as part of the power conversion system 400 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 402 includes a ramp-signal generator 602, an under-voltage lock-out (UVLO) component 604, a modulation component 606, a logic controller 608, a driving component 610, a demagnetization detector 612, an error amplifier 616, a current-sensing-and-sample/hold component 614, a jittering-signal generator 699, and voltage-to-current-conversion components 640 and 642.
According to one embodiment, the UVLO component 604 detects the signal 454 and outputs a signal 618. For example, if the signal 454 is larger than a first predetermined threshold in magnitude, the controller 402 begins to operate normally. If the signal 454 is smaller than a second predetermined threshold in magnitude, the controller 402 is turned off. In another example, the second predetermined threshold is smaller than the first predetermined threshold in magnitude. In yet another example, the error amplifier 616 receives a signal 620 from the current-sensing-and-sample/hold component 614 and a reference signal 622, and the signal 474 is provided to the modulation component 606 and the voltage-to-current-conversion component 642. As an example, the voltage-to-current-conversion component 640 receives the signal 472 and outputs a signal 636 to the ramp-signal generator 602. In another example, the ramp-signal generator 602 also receives a current signal 694 and a jittering signal 697 (e.g., a jittering current) generated by the jittering-signal generator 699 and generates a ramping signal 628.
According to another embodiment, the jittering current 697 flows from the jittering-signal generator 699 to the ramp-signal generator 602. For example, the jittering current 697 flows from the ramp-signal generator 602 to the jittering-signal generator 699. In another example, the modulation component 606 receives the ramping signal 628 and outputs a modulation signal 626. For example, the signal 628 increases, linearly or non-linearly, to a peak magnitude during each switching period. The logic controller 608 processes the modulation signal 626 and outputs a control signal 630 to the current-sensing-and-sample/hold component 614 and the driving component 610.
According to yet another embodiment, the current-sensing-and-sample/hold component 614 samples the current sensing signal 496 in response to the control signal 630 and then holds the sampled signal until the current-sensing-and-sample/hold component 614 samples again the current sensing signal 496. For example, the driving component 610 generates a signal 656 related to the drive signal 456 to affect the switch 428. As an example, the demagnetization detector 612 detects the feedback signal 460 and outputs a demagnetization signal 632 for determining the end of the demagnetization process of the secondary winding 414. As another example, the demagnetization detector 612 detects the feedback signal 460 and outputs the demagnetization signal 632 for determining the beginning and the end of the demagnetization process of the secondary winding 414. In yet another example, the demagnetization detector 612 outputs a trigger signal 698 to the logic controller 608 to start a next cycle (e.g., corresponding to a next switching period). In yet another example, when the signal 656 is at a logic high level, the signal 456 is at a logic high level, and when the signal 656 is at a logic low level, the signal 456 is at a logic low level. In yet another example, the capacitor 434 is coupled to the terminal 448 and forms, together with the error amplifier 616, an integrator or a low-pass filter. In yet another example, the error amplifier 616 is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal 622 and the signal 620. In yet another example, the error amplifier 616 together with the capacitor 434 generates the signal 474 which is a voltage signal. In yet another example, the ramping slope of the ramping signal 628 is modulated in response to the jittering signal 697.
In some embodiments, the jittering signal 697 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 697 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 656 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 402 changes the ramping slope associated with the ramping signal 628 based on at least information associated with the jittering signal 628 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 402 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 697 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 402 changes the ramping slope associated with the ramping signal 628 based on at least information associated with the random jittering signal 628 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 402 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
In some embodiments, the signal 636 represents a current and is used for adjusting a ramping slope associated with the ramping signal 628. In certain embodiments, the signal 638 represents a current and is used for adjusting the ramping slope associated with the ramping signal 628. For example, information associated with both the signal 636 and the signal 638 is used for adjusting the ramping slope associated with the ramping signal 628, so as to adjust the duration of an on-time period associated with the drive signal 456. In another example, the current 636 flows from the voltage-to-current-conversion component 640 to the ramp-signal generator 602. In yet another example, the current 636 flows from the ramp-signal generator 602 to the voltage-to-current-conversion component 640. In yet another example, the current 638 flows from the voltage-to-current-conversion component 642 to the ramp-signal generator 602. In yet another example, the current 638 flows from the ramp-signal generator 602 to the voltage-to-current-conversion component 642.
FIG. 4(c) is a simplified timing diagram for the controller 402 as part of the power conversion system 400 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform 902 represents the signal 626 as a function of time, the waveform 904 represents the signal 656 as a function of time, the wave form 906 represents the demagnetization signal 632 as a function of time, the waveform 908 represents the trigger signal 698 as a function of time, and the waveform 910 represents the ramping signal 628 as a function of time.
An on-time period and an off-time period associated with the signal 656 are shown in FIG. 4(c). The on-time period begins at a time t3 and ends at a time t5, and the off-time period begins at the time t5 and ends at a time t7. For example, t0≦t1≦t2≦t3≦t4≦t5≦t6≦t7.
According to one embodiment, at t0, the demagnetization signal 632 changes from the logic low level to the logic high level. For example, the demagnetization detector 612 generates a pulse (e.g., between t0 and t2) in the trigger signal 698 to trigger a new cycle. As an example, the ramping signal 628 begins to increases from a magnitude 912 to a magnitude 914 (e.g., at t4). In another example, at t1, the signal 626 changes from the logic low level to the logic high level. After a short delay, the signal 656 changes (e.g., at t3) from the logic low level to the logic high level, and in response the switch 428 is turned on. In yet another example, at t4, the signal 626 changes from the logic high level to the logic low level, and the ramping signal 628 decreases from the magnitude 914 to the magnitude 912. After a short delay, the signal 656 changes (e.g., at t5) from the logic high level to the logic low level, and in response, the switch 428 is turned off. As an example, at t6, the demagnetization signal 632 changes from the logic low level to the logic high level which indicates a beginning of a demagnetization process. In another example, at t7, the demagnetization signal 632 changes from the logic high level to the logic low level which indicates an end of the demagnetization process. In yet another example, the demagnetization detector 612 generates another pulse in the trigger signal 698 to start a next cycle. In yet another example, the magnitude 914 of the ramping signal 628 is associated with the magnitude of the signal 474.
According to another embodiment, the magnitude change of the ramping signal 628 during the on-time period is determined as follows:

ΔVramp=Vcomp−Vref_1=slope×Ton  (Equation 4)

where ΔVramp represents the magnitude changes of the ramping signal 628, Vcomp represents the signal 474, Vref_1 represents a predetermined voltage magnitude, slope represents a ramping slope associated with the ramping signal 628, and Ton represents the duration of the on-time period. For example, Vref_1 corresponds to a minimum magnitude of the ramping signal 628. Based on Equation 4, the duration of the on-time period is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              V
              comp
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          5
        
        )
      
    
  




As shown in Equation 5, for a given compensation signal (e.g., the signal 474), the duration of the on-time period is determined by the ramping slope of the ramping signal 628. In some embodiments, the ramping slope of the ramping signal 628 is adjusted according to the signal 636 and the signal 638, so that the duration of the on-time period associated with the drive signal 456 is adjusted. For example, adjusting the ramping slope of the ramping signal 628 to change the duration of the on-time period is applicable to power conversion systems with a buck-boost topology operated in a quasi-resonant (QR) mode. In another example, a slope of the waveform 910 between t1 and t4 corresponds to the ramping slope of the ramping signal 628.
As discussed above and further emphasized here, FIGS. 4(b) and 4(c) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the voltage-to-current-conversion component 642 is removed from the controller 402, as shown in FIG. 4(d).
FIG. 4(d) is a simplified diagram showing the controller 402 as part of the power conversion system 400 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 402 includes a ramp-signal generator 1402, an under-voltage lock-out (UVLO) component 1404, a modulation component 1406, a logic controller 1408, a driving component 1410, a demagnetization detector 1412, an error amplifier 1416, a current-sensing-and-sample/hold component 1414, a jittering-signal generator 1499, and a voltage-to-current-conversion component 1440.
In some embodiments, the ramp-signal generator 1402 receives a current signal 1494, a jittering signal 1497 (e.g., a jittering current) generated by the jittering-signal generator 1499 and a signal 1436 from the voltage-to-current-conversion component 1440 and outputs a ramping signal 1428. For example, the jittering current 1497 flows from the jittering-signal generator 1499 to the ramp-signal generator 1402. In another example, the jittering current 1497 flows from the ramp-signal generator 1402 to the jittering-signal generator 1499. For example, a ramping slope associated with the ramping signal 1428 is adjusted based on at least information associated with the signal 1436 that is related to the bulk voltage 450. The operations of other components in FIG. 4(d) are similar to what are described in FIG. 4(b). For example, the timing diagram for the controller 402 as part of the system 400 is similar to what is shown in FIG. 4(c). As an example, the signal 1436 represents a current. In another example, the current 1436 flows from the voltage-to-current-conversion component 1440 to the ramp-signal generator 1402. In yet another example, the current 1436 flows from the ramp-signal generator 1402 to the voltage-to-current-conversion component 1440. In yet another example, the ramping slope of the ramping signal 1428 is modulated in response to the jittering signal 1497.
In certain embodiments, the jittering signal 1497 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 1497 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 1456 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 402 changes the ramping slope associated with the ramping signal 1428 based on at least information associated with the jittering signal 1428 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 402 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 1497 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 402 changes the ramping slope associated with the ramping signal 1428 based on at least information associated with the random jittering signal 1428 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 402 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
As discussed above and further emphasized here, FIG. 4(a), FIG. 4(b), FIG. 4(c), and/or FIG. 4(d) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the ramping slope associated with an internal ramping signal in a controller is adjusted using a current signal associated with a bulk voltage, as shown in FIG. 5(a), FIG. 5(b), and FIG. 5(c).
FIG. 5(a) is a simplified diagram showing a power conversion system according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system 800 includes a controller 802, resistors 804, 824, 826, 832 and 866, capacitors 806, 820, and 834, a diode 808, a transformer 810 including a primary winding 812, a secondary winding 814 and an auxiliary winding 816, a power switch 828, a current sensing resistor 830, and a rectifying diode 818. The controller 802 includes terminals (e.g., pins) 838, 840, 842, 844, 846, 848 and 864. For example, the power switch 828 includes a bipolar junction transistor. In another example, the power switch 828 includes a MOS transistor. In yet another example, the power switch 828 includes an insulated-gate bipolar transistor. The system 800 provides power to an output load 822, e.g., one or more LEDs. In some embodiments, the resistor 832 is removed. For example, the system 800 operates in a quasi-resonant mode.
According to one embodiment, an alternate-current (AC) input voltage 852 is applied to the system 800. For example, a bulk voltage 850 (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage 852 is received by the resistor 804. In another example, the capacitor 806 is charged in response to the bulk voltage 850, and a voltage 854 is provided to the controller 802 at the terminal 838 (e.g., terminal VCC). In yet another example, if the voltage 854 is larger than a predetermined threshold voltage in magnitude, the controller 802 begins to operate normally, and outputs a signal through the terminal 842 (e.g., terminal GATE). In yet another example, the switch 828 is closed (e.g., being turned on) or open (e.g., being turned off) in response to a drive signal 856 so that the output current 858 is regulated to be approximately constant.
According to another embodiment, the auxiliary winding 816 charges the capacitor 806 through the diode 808 when the switch 828 is opened (e.g., being turned off) in response to the drive signal 856 so that the controller 802 can operate normally. For example, a feedback signal 860 is provided to the controller 802 through the terminal 840 (e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding 814 for charging or discharging the capacitor 834 using an internal error amplifier in the controller 802. In another example, the feedback signal 860 is provided to the controller 802 through the terminal 840 (e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding 814. As an example, the capacitor 834 is charged or discharged in response to a compensation signal 874 at the terminal 848 (e.g., terminal COMP). In another example, the resistor 830 is used for detecting a primary current 862 flowing through the primary winding 812, and a current-sensing signal 896 is provided to the controller 802 through the terminal 844 (e.g., terminal CS) to be processed during each switching cycle. In yet another example, peak magnitudes of the current-sensing signal 896 are sampled and provided to the internal error amplifier. In yet another example, the capacitor 834 is coupled to an output terminal of the internal error amplifier. In yet another example, the capacitor 820 is used to maintain an output voltage 868.
According to yet another embodiment, the bulk voltage 850 is sensed by the controller 802 through the terminal 864 (e.g., terminal IAC). For example, the controller 802 includes a ramp-signal generator which generates a ramping signal, and the controller 802 is configured to change the ramping slope of the ramping signal based on at least information associated with a signal 872 related to the bulk voltage 850. In another example, an on-time period associated with the drive signal 856 varies based on at least information associated with the signal 850. As an example, the duration of the on-time period increases when the bulk voltage 850 is at a peak magnitude. In another example, the duration of the on-time period decreases when the bulk voltage 850 is at a valley magnitude. The signal 872 is determined according to the following equation:




  
    
      
        
          I
          ac
        
        =
        
          μ
          ×
          
            
              V
              bulk
            
            
              R
              8
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          6
        
        )
      
    
  




where Iac represents the signal 872, Vbulk represents the bulk voltage 850, R8 represents a resistance of the resistor 866, and μ represents a constant.

In some embodiments, the controller is configured to adjust the ramping signal based on information associated with both the signal 872 and the compensation signal 874. In certain embodiments, the controller is configured to adjust the ramping signal based on information associated with the signal 872 or the compensation signal 874.
FIG. 5(b) is a simplified diagram showing the controller 802 as part of the power conversion system 800 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 802 includes a ramp-signal generator 1002, an under-voltage lock-out (UVLO) component 1004, a modulation component 1006, a logic controller 1008, a driving component 1010, a demagnetization detector 1012, an error amplifier 1016, a current-sensing-and-sample/hold component 1014, another current-sensing component 1040, a jittering-signal generator 1099, and a voltage-to-current-conversion components 1042.
According to one embodiment, the UVLO component 1004 detects the signal 854 and outputs a signal 1018. For example, if the signal 854 is larger than a first predetermined threshold in magnitude, the controller 802 begins to operate normally. If the signal 854 is smaller than a second predetermined threshold in magnitude, the controller 802 is turned off. In yet another example, the second predetermined threshold is smaller than the first predetermined threshold in magnitude. In yet another example, the error amplifier 1016 receives a signal 1020 from the current-sensing-and-sample/hold component 1014 and a reference signal 1022, and the signal 874 is provided to the modulation component 1006 and the voltage-to-current-conversion component 1042. As an example, the current-sensing component 1040 receives the signal 872 and outputs a signal 1036 to the ramp-signal generator 1002 which also receives a current signal 1094 and a jittering signal 1097 (e.g., a jittering current) generated by the jittering-signal generator 1099. In another example, the jittering current 1097 flows from the jittering-signal generator 1099 to the ramp-signal generator 1002. In yet another example, the jittering current 1097 flows from the ramp-signal generator 1002 to the jittering-signal generator 1099. In yet another example, the modulation component 1006 receives a ramping signal 1028 from the ramp-signal generator 1002 and outputs a modulation signal 1026. For example, the signal 1028 increases, linearly or non-linearly, to a peak magnitude during each switching period. The logic controller 1008 processes the modulation signal 1026 and outputs a control signal 1030 to the current-sensing-and-sample/hold component 1014 and the driving component 1010. For example, the driving component 1010 generates a signal 1056 related to the drive signal 856 to affect the switch 828. As an example, the demagnetization detector 1012 detects the feedback signal 860 and outputs a demagnetization signal 1032 for determining the end of the demagnetization process of the secondary winding 814. As another example, the demagnetization detector 1012 detects the feedback signal 860 and outputs the demagnetization signal 1032 for determining the beginning and the end of the demagnetization process of the secondary winding 814. In another example, the demagnetization detector 1012 outputs a trigger signal 1098 to the logic controller 1008 to start a next modulation cycle. In yet another example, when the signal 1056 is at a logic high level, the signal 856 is at a logic high level, and when the signal 1056 is at a logic low level, the signal 856 is at a logic low level. In yet another example, the ramping slope of the ramping signal 1028 is modulated in response to the jittering signal 1097.
In some embodiments, the jittering signal 1097 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 1097 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 1056 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 802 changes the ramping slope associated with the ramping signal 1028 based on at least information associated with the jittering signal 1028 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 802 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 1097 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 802 changes the ramping slope associated with the ramping signal 1028 based on at least information associated with the random jittering signal 1028 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 802 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
In some embodiments, the signal 1036 represents a current and is used for adjusting a ramping slope associated with the ramping signal 1028. In certain embodiments, the signal 1038 represents a current and is used for adjusting the ramping slope associated with the ramping signal 1028. For example, information associated with both the signal 1036 and the signal 1038 is used for adjusting the ramping slope associated with the ramping signal 1028, so as to adjust the duration of an on-time period associated with the drive signal 856. For example, the timing diagram for the controller 802 as part of the system 800 is similar to what is shown in FIG. 4(c). In another example, the current 1036 flows from the current-sensing component 1040 to the ramp-signal generator 1002. In yet another example, the current 1036 flows from the ramp-signal generator 1002 to the current-sensing component 1040. In yet another example, the current 1038 flows from the voltage-to-current-conversion component 1042 to the ramp-signal generator 1002. In yet another example, the current 1038 flows from the ramp-signal generator 1002 to the voltage-to-current-conversion component 1042.
FIG. 5(c) is a simplified diagram showing the controller 802 as part of the power conversion system 800 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 802 includes a ramp-signal generator 1502, an under-voltage lock-out (UVLO) component 1504, a modulation component 1506, a logic controller 1508, a driving component 1510, a demagnetization detector 1512, an error amplifier 1516, a current-sensing-and-sample/hold component 1514, a jittering-signal generator 1599, and another current-sensing component 1540.
In some embodiments, the ramp-signal generator 1502 receives a current signal 1594, a jittering signal 1597 (e.g., a jittering current) generated by the jittering-signal generator 1599, and a signal 1536 from the current-sensing component 1540 and outputs a ramping signal 1528. As an example, the jittering current 1597 flows from the jittering-signal generator 1599 to the ramp-signal generator 1502. As another example, the jittering current 1597 flows from the ramp-signal generator 1502 to the jittering-signal generator 1599. For example, a ramping slope associated with the ramping signal 1528 is adjusted based on at least information associated with the signal 1536 that is related to a current signal associated with the bulk voltage 850. The operations of other components in FIG. 5(c) are similar to what are described in FIG. 5(b). As an example, the signal 1536 represents a current. In another example, the current 1536 flows from the current-sensing component 1540 to the ramp-signal generator 1502. In yet another example, the current 1536 flows from the ramp-signal generator 1502 to the current-sensing component 1540. In yet another example, the ramping slope of the ramping signal 1528 is modulated in response to the jittering signal 1597.
In some embodiments, the jittering signal 1597 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 1597 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 1556 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 802 changes the ramping slope associated with the ramping signal 1528 based on at least information associated with the jittering signal 1528 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 802 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 1597 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 802 changes the ramping slope associated with the ramping signal 1528 based on at least information associated with the random jittering signal 1528 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 802 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
As discussed above and further emphasized here, FIG. 4(a), FIG. 4(b), FIG. 5(a), and/or FIG. 5(b) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, a terminal (e.g., the terminal 464, the terminal 864) configured to receive signals related to a bulk voltage (e.g., the bulk voltage 450, the bulk voltage 850) is removed from a controller (e.g., the controller 402, the controller 802) for a power conversion system, as shown in FIG. 6(a) and FIG. 6(b).
FIG. 6(a) is a simplified diagram showing a power conversion system according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system 500 includes a controller 502, resistors 504, 524, 526 and 532, capacitors 506, 520 and 534, a diode 508, a transformer 510 including a primary winding 512, a secondary winding 514 and an auxiliary winding 516, a power switch 528, a current sensing resistor 530, and a rectifying diode 518. The controller 502 includes terminals (e.g., pins) 538, 540, 542, 544, 546 and 548. For example, the power switch 528 is a bipolar junction transistor. In another example, the power switch 528 is a MOS transistor. In yet another example, the power switch 528 includes an insulated-gate bipolar transistor. The system 500 provides power to an output load 522, e.g., one or more LEDs. In some embodiments, the resistor 532 is removed. For example, the system 500 operates in a quasi-resonant mode.
According to one embodiment, an alternate-current (AC) input voltage 552 is applied to the system 500. For example, a bulk voltage 550 (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage 552 is received by the resistor 504. In another example, the capacitor 506 is charged in response to the bulk voltage 550, and a voltage 554 is provided to the controller 502 at the terminal 538 (e.g., terminal VCC). In yet another example, if the voltage 554 is larger than a predetermined threshold voltage in magnitude, the controller 502 begins to operate normally, and outputs a signal through the terminal 542 (e.g., terminal GATE). In yet another example, the switch 528 is closed (e.g., being turned on) or open (e.g., being turned off) in response to a drive signal 556 so that the output current 558 is regulated to be approximately constant.
According to another embodiment, the auxiliary winding 516 charges the capacitor 506 through the diode 508 when the switch 528 is opened (e.g., being turned off) in response to the drive signal 556 so that the controller 502 can operate normally. For example, a feedback signal 560 is provided to the controller 502 through the terminal 540 (e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding 514 for charging or discharging the capacitor 534 using an internal error amplifier in the controller 502. In another example, the feedback signal 560 is provided to the controller 502 through the terminal 540 (e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding 514. As an example, the capacitor 534 is charged or discharged in response to a compensation signal 574 provided at the terminal 548 (e.g., terminal COMP). In another example, the resistor 530 is used for detecting a primary current 562 flowing through the primary winding 512, and a current-sensing signal 564 is provided to the controller 502 through the terminal 544 (e.g., terminal CS) to be processed during each switching cycle. In yet another example, peak magnitudes of the current-sensing signal 564 are sampled and provided to the internal error amplifier. In yet another example, the capacitor 520 is used to maintain an output voltage 568. In some embodiments, the controller 502 includes a ramp-signal generator which generates a ramping signal, and the controller 502 is configured to change the ramping slope of the ramping signal based on at least information associated with the compensation signal 574.
FIG. 6(b) is a simplified diagram showing the controller 502 as part of the power conversion system 500 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 502 includes a ramp-signal generator 702, an under-voltage lock-out (UVLO) component 704, a modulation component 706, a logic controller 708, a driving component 710, a demagnetization detector 712, an error amplifier 716, a current-sensing-and-sample/hold component 714, a jittering-signal generator 799, and a voltage-to-current-conversion component 742.
According to one embodiment, the UVLO component 704 detects the signal 554 and outputs a signal 718. For example, if the signal 554 is larger than a first predetermined threshold in magnitude, the controller 502 begins to operate normally. If the signal 554 is smaller than a second predetermined threshold in magnitude, the controller 502 is turned off. In another example, the second predetermined threshold is smaller than the first predetermined threshold in magnitude. In yet another example, the error amplifier 716 receives a signal 720 from the current-sensing-and-sample/hold component 714 and a reference signal 722 and the compensation signal 574 is provided to the modulation component 706 and the voltage-to-current-conversion component 742. In yet another example, the voltage-to-current-conversion component 742 receives the signal 574 and outputs a signal 738 to the ramp-signal generator 702 which also receives a current signal 794 and a jittering signal 797 (e.g., a jittering current) generated by the jittering-signal generator 799. In yet another example, the jittering current 797 flows from the jittering-signal generator 799 to the ramp-signal generator 702. In yet another example, the jittering current 797 flows from the ramp-signal generator 702 to the jittering-signal generator 799. In yet another example, the modulation component 706 receives a ramping signal 728 from the ramp-signal generator 702 and outputs a modulation signal 726. For example, the signal 728 increases, linearly or non-linearly, to a peak magnitude during each switching period. In another example, the logic controller 708 processes the modulation signal 726 and outputs a control signal 730 to the current-sensing-and-sample/hold component 714 and the driving component 710. In yet another example, the driving component 710 generates a signal 756 associated with the drive signal 556 to affect the switch 528. As an example, the demagnetization detector 712 detects the feedback signal 560 and outputs a signal 732 for determining the end of the demagnetization process of the secondary winding 514. As another example, the demagnetization detector 712 detects the feedback signal 560 and outputs the signal 732 for determining the beginning and the end of the demagnetization process of the secondary winding 514. In another example, the demagnetization detector 712 outputs a trigger signal 798 to the logic controller 708 to start a next cycle (e.g., corresponding to a next switching period). In yet another example, when the signal 756 is at a logic high level, the signal 556 is at a logic high level, and when the signal 756 is at a logic low level, the signal 556 is at a logic low level. In yet another example, the ramping slope of the ramping signal 728 is modulated in response to the jittering signal 797.
In some embodiments, the jittering signal 797 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 797 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 756 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 502 changes the ramping slope associated with the ramping signal 728 based on at least information associated with the jittering signal 728 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 502 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 797 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 502 changes the ramping slope associated with the ramping signal 728 based on at least information associated with the random jittering signal 728 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 502 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
In some embodiments, the signal 738 represents a current and is used for adjusting the ramping slope associated with the ramping signal 728. For example, information associated with the signal 738 is used for adjusting the ramping slope associated with the ramping signal 728, so as to adjust the duration of an on-time period associated with the drive signal 556. For example, the timing diagram for the controller 502 as part of the system 500 is similar to what is shown in FIG. 4(c). In another example, the current 738 flows from the voltage-to-current-conversion component 742 to the ramp-signal generator 702. In yet another example, the current 738 flows from the ramp-signal generator 702 to the voltage-to-current-conversion component 742.
FIG. 7(a) is a simplified diagram showing a power conversion system according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system 1100 includes a controller 1102, resistors 1104, 1124, 1126 and 1132, capacitors 1106, 1120 and 1134, a diode 1108, a transformer 1110 including a primary winding 1112, a secondary winding 1114 and an auxiliary winding 1116, a power switch 1128, a current sensing resistor 1130, and a rectifying diode 1118. The controller 1102 includes terminals (e.g., pins) 1138, 1140, 1142, 1144, 1146 and 1148. For example, the power switch 1128 is a bipolar junction transistor. In another example, the power switch 1128 is a MOS transistor. In yet another example, the power switch 1128 includes an insulated-gate bipolar transistor. The system 1100 provides power to an output load 1122, e.g., one or more LEDs. In some embodiments, the resistor 1132 is removed. For example, the system 1100 operates in a quasi-resonant mode.
According to one embodiment, an alternate-current (AC) input voltage 1152 is applied to the system 1100. For example, a bulk voltage 1150 (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage 1152 is received by the resistor 1104. In another example, the capacitor 1106 is charged in response to the bulk voltage 1150, and a voltage 1154 is provided to the controller 1102 at the terminal 1138 (e.g., terminal VCC). In yet another example, if the voltage 1154 is larger than a predetermined threshold voltage in magnitude, the controller 1102 begins to operate normally, and outputs a signal through the terminal 1142 (e.g., terminal GATE). In yet another example, the switch 1128 is closed (e.g., being turned on) or open (e.g., being turned off) in response to a drive signal 1156 so that the output current 1158 is regulated to be approximately constant.
According to another embodiment, the auxiliary winding 1116 charges the capacitor 1106 through the diode 1108 when the switch 1128 is opened (e.g., being turned off) in response to the drive signal 1156 so that the controller 1102 can operate normally. For example, a signal 1160 is provided at the terminal 1140 (e.g., terminal FB). In another example, during an on-time period associated with the drive signal 1156, the signal 1198 is related to the bulk voltage 1150 through the transformer's coupling. In yet another example, the bulk voltage 1150 is sensed through the terminal 1140 (e.g., terminal FB). In yet another example, during an off-time period associated with the drive signal 1156, the signal 1160 is related to an output voltage 1168 and is used to detect the end of a demagnetization process of the secondary winding 1114 for charging or discharging the capacitor 1134 using an internal error amplifier in the controller 1102. As an example, the capacitor 1134 is charged or discharged in response to a compensation signal 1174 provided at the terminal 1148 (e.g., terminal COMP). For example, the resistor 1130 is used for detecting a primary current 1162 flowing through the primary winding 1112, and a current-sensing signal 1164 is provided to the controller 1102 through the terminal 1144 (e.g., terminal CS) to be processed during each switching cycle. In yet another example, peak magnitudes of the current-sensing signal 1164 are sampled and provided to the internal error amplifier. In yet another example, the capacitor 1120 is used to maintain the output voltage 1168. In some embodiments, the controller 1102 includes a ramp-signal generator which generates a ramping signal, and the controller 1102 is configured to change the ramping slope of the ramping signal based on at least information associated with the signal 1160 and the compensation signal 1174.
FIG. 7(b) is a simplified diagram showing the controller 1102 as part of the power conversion system 1100 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 1102 includes a ramp-signal generator 1202, an under-voltage lock-out (UVLO) component 1204, a modulation component 1206, a logic controller 1208, a driving component 1210, a demagnetization detector 1212, an error amplifier 1216, a current-sensing-and-sample/hold component 1214, another current-sensing component 1240, a jittering-signal generator 1299, and a voltage-to-current-conversion component 1242.
According to one embodiment, the UVLO component 1204 detects the signal 1154 and outputs a signal 1218. For example, if the signal 1154 is larger than a first predetermined threshold in magnitude, the controller 1102 begins to operate normally. If the signal 1154 is smaller than a second predetermined threshold in magnitude, the controller 1102 is turned off. In another example, the first predetermined threshold is larger than the second predetermined threshold in magnitude. In yet another example, the error amplifier 1216 receives a signal 1220 from the current-sensing-and-sample/hold component 1214 and a reference signal 1222 and the compensation signal 1174 is provided to the modulation component 1206 and the voltage-to-current-conversion component 1242. In yet another example, the voltage-to-current-conversion component 1242 receives the signal 1174 and outputs a signal 1238 to the ramp-signal generator 1202 which also receives a current signal 1294 and a jittering signal 1297 (e.g., a jittering current) generated by the jittering-signal generator 1299. In yet another example, the jittering current 1297 flows from the jittering-signal generator 1299 to the ramp-signal generator 1202. In yet another example, the jittering current 1297 flows from the ramp-signal generator 1202 to the jittering-signal generator 1299. In yet another example, the current-sensing component 1240 outputs a signal 1236 to the ramp-signal generator 1202 in response to a current signal 1296 associated with the terminal 1140 (e.g., terminal FB). As an example, the current signal 1296 is related to the bulk voltage 1150 during the on-time period associated with the driving signal 1156. In yet another example, the ramping slope of the ramping signal 1228 is modulated in response to the jittering signal 1297.
In some embodiments, the jittering signal 1297 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 1297 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 1256 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 1102 changes the ramping slope associated with the ramping signal 1228 based on at least information associated with the jittering signal 1228 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 1102 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 1297 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 1102 changes the ramping slope associated with the ramping signal 1228 based on at least information associated with the random jittering signal 1228 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 1102 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
According to another embodiment, the modulation component 1206 receives a ramping signal 1228 from the ramp-signal generator 1202 and outputs a modulation signal 1226. For example, the signal 1228 increases, linearly or non-linearly, to a peak magnitude during each switching period. In another example, the logic controller 1208 processes the modulation signal 1226 and outputs a control signal 1230 to the current-sensing-and-sample/hold component 1214 and the driving component 1210. In yet another example, the driving component 1210 generates a signal 1256 associated with the drive signal 1156 to affect the switch 1128. As an example, the demagnetization detector 1212 detects the signal 1160 and outputs a signal 1232 (e.g., during an off-time period associated with the drive signal 1156) for determining the end of the demagnetization process of the secondary winding 1114. As another example, the demagnetization detector 1212 detects the signal 1160 and outputs the signal 1232 (e.g., during the off-time period associated with the drive signal 1156) for determining the beginning and the end of the demagnetization process of the secondary winding 1114. In another example, the demagnetization detector 1212 outputs a trigger signal 1298 to the logic controller 1208 to start a next cycle (e.g., corresponding to a next switching period). In yet another example, when the signal 1256 is at a logic high level, the signal 1156 is at a logic high level, and when the signal 1256 is at a logic low level, the signal 1156 is at a logic low level.
In some embodiments, the signal 1236 represents a current and is used for adjusting a ramping slope associated with the ramping signal 1228. In certain embodiments, the signal 1238 represents a current and is used for adjusting the ramping slope associated with the ramping signal 1228. For example, information associated with both the signal 1236 and the signal 1238 is used for adjusting the ramping slope associated with the ramping signal 1228, so as to adjust the duration of an on-time period associated with the drive signal 1156. In another example, the current 1236 flows from the current-sensing component 1240 to the ramp-signal generator 1202. In yet another example, the current 1236 flows from the ramp-signal generator 1202 to the current-sensing component 1240. In yet another example, the current 1238 flows from the voltage-to-current-conversion component 1242 to the ramp-signal generator 1202. In yet another example, the current 1238 flows from the ramp-signal generator 1202 to the voltage-to-current-conversion component 1242.
Referring to FIG. 7(a) and FIG. 7(b), during an on-time period, a voltage 1198 associated with the auxiliary winding 1116 is determined as follows, in some embodiments:




  
    
      
        
          V
          aux
        
        =
        
          
            -
            
              
                N
                aux
              
              
                N
                p
              
            
          
          ×
          
            V
            bulk
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          7
        
        )
      
    
  




where Vaux represents the voltage 1198, Naux/Np represents a turns ratio between the auxiliary winding 1116 and the primary winding 1112, and Vbulk represents the bulk voltage 1150. In certain embodiments, when a voltage at the terminal 1140 (e.g., terminal FB) is regulated to be approximately zero, the current signal 1296 is detected by the current-sensing component 1240:





  
    
      
        
          I
          FB
        
        =
        
          
            
              V
              aux
            
            
              R
              6
            
          
          =
          
            
              
                N
                aux
              
              
                
                  N
                  p
                
                ×
                
                  R
                  6
                
              
            
            ×
            
              V
              bulk
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          8
        
        )
      
    
  




where IFB represents the current signal 1296 and R6 represents the resistance of the resistor 1124. According to some embodiments, the current signal 1296 indicates a waveform of the bulk voltage 1150 during the on-time period associated with the drive signal 1156, and the signal 1236 is determined as follows:





  
    
      
        
          I
          ac
        
        =
        
          
            δ
            ×
            
              I
              FB
            
          
          =
          
            δ
            ×
            
              
                N
                aux
              
              
                
                  N
                  p
                
                ×
                
                  R
                  6
                
              
            
            ×
            
              V
              bulk
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          9
        
        )
      
    
  




where Iac represents the signal 1236 and δ represents a constant.

Similar to what is described above in FIG. 4(c), the ramping signal 1228 increases in magnitude during the on-time period, in certain embodiments. For example, the ramping slope of the ramping signal 1228 is modulated based on at least information associated with the signal 1236 generated through detecting the current signal 1296 during the on-time period. For example, the timing diagram for the controller 1102 as part of the system 1100 is similar to what is shown in FIG. 4(c).
FIG. 7(c) is a simplified diagram showing the controller 1102 as part of the power conversion system 1100 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 1102 includes a ramp-signal generator 1602, an under-voltage lock-out (UVLO) component 1604, a modulation component 1606, a logic controller 1608, a driving component 1610, a demagnetization detector 1612, an error amplifier 1616, a current-sensing component 1614, a jittering-signal generator 1699, and another current-sensing component 1640.
In some embodiments, the ramp-signal generator 1602 receives a current signal 1694, a jittering signal 1697 (e.g., a jittering current) generated by the jittering-signal generator 1699, and a signal 1636 from the current-sensing component 1640 and outputs a ramping signal 1628. In yet another example, the jittering current 1697 flows from the jittering-signal generator 1699 to the ramp-signal generator 1602. In yet another example, the jittering current 1697 flows from the ramp-signal generator 1602 to the jittering-signal generator 1699. For example, a ramping slope associated with the ramping signal 1628 is adjusted based on at least information associated with the signal 1636 that is related to a current signal 1696 detected at the terminal 1140 (e.g., terminal FB) during an on-time period associated with the driving signal 1156. The operations of other components in FIG. 7(c) are similar to what are described in FIG. 7(b). As an example, the signal 1636 represents a current. In another example, the current 1636 flows from the current-sensing component 1640 to the ramp-signal generator 1602. In yet another example, the current 1636 flows from the ramp-signal generator 1602 to the current-sensing component 1640. In yet another example, the ramping slope of the ramping signal 1628 is modulated in response to the jittering signal 1697.
In some embodiments, the jittering signal 1697 corresponds to a deterministic signal, such as a triangle waveform (e.g., with a frequency of several hundred Hz), or a sinusoidal waveform (e.g., with a frequency of several hundred Hz). For example, the jittering signal 1697 is associated with multiple jittering cycles corresponding to a predetermined jittering frequency (e.g., approximately constant) related to a predetermined jittering period (e.g., approximately constant). As an example, the signal 1656 is associated with multiple modulation cycles corresponding to a modulation frequency (e.g., not constant) related to a modulation period (e.g., not constant). In another example, the system controller 1102 changes the ramping slope associated with the ramping signal 1628 based on at least information associated with the jittering signal 1628 so that, within a same jittering cycle of the multiple jittering cycles, the ramping slope is changed (e.g., increased, or decreased) by different magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles not adjacent to each other. In yet another example, the system controller 1102 adjusts the modulation frequency based on at least information associated with the changed ramping slope.
In certain embodiments, the jittering signal 1697 corresponds to a random (e.g., pseudo-random) signal with a random (e.g., pseudo-random) waveform. For example, the system controller 1102 changes the ramping slope associated with the ramping signal 1628 based on at least information associated with the random jittering signal 1628 so that the ramping slope is changed by random magnitudes corresponding to different modulation cycles respectively. In yet another example, the ramping slope is changed during different modulation cycles that are adjacent to each other. In yet another example, the ramping slope is changed during different modulation cycles that are not adjacent to each other. In yet another example, the system controller 1102 adjusts the modulation frequency based on at least information associated with the ramping slope changed by the random magnitudes.
FIG. 8(a) is a simplified diagram showing certain components as part of the controller 402 as shown in FIG. 4(b), the controller 802 as shown in FIG. 5(b), and/or the controller 1102 as shown in FIG. 7(b) according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. A ramp-signal generator 1300 includes transistors 1308, 1310, 1312, 1314, 1316 and 1320, an amplifier 1322, and a NOT gate 1324. In addition, current-source components 1302, 1304, 1306 and 1399 are included in the controller 402 as shown in FIG. 4(b), the controller 802 as shown in FIG. 5(b), and/or the controller 1102 as shown in FIG. 7(b).
According to one embodiment, the current-source components 1302, 1304, 1306 and 1399 are related to currents 1332, 1334, 1336 and 1397 respectively. For example, a current-mirror circuit including the transistors 1308, 1310, 1312 and 1314 is configured to generate a charging current 1340 (e.g., Icharge) that flows through the transistor 1316 which is controlled by a signal 1328. In another example, the amplifier 1322 receives a reference signal 1330 and outputs an amplified signal 1338. In yet another example, the capacitor 1318 is charged or discharged to generate a ramping signal 1398 as the output signal of the ramp-signal generator 1300.
In some embodiments, the ramp-signal generator 1300 is the same as the ramp-signal generator 602, the ramp-signal generator 1002, or the ramp-signal generator 1202. For example, the current 1332 is the same as the current 636 that flows between the ramp-signal generator 602 and the voltage-to-current-conversion component 640, the current 1036 that flows between the ramp-signal generator 1002 and the current-sensing component 1040, or the current 1236 that flows between the ramp-signal generator 1202 and the current-sensing component 1240. In another example, the current 1334 is the same as the current 638 that flows between the ramp-signal generator 602 and the voltage-to-current-conversion component 642, the current 1038 that flows between the ramp-signal generator 1002 and the voltage-to-current-conversion component 1042, or the current 1238 that flows between the ramp-signal generator 1202 and the voltage-to-current-conversion component 1242. In yet another example, the current 1336 is the same as the current 694, the current 1094, or the current 1294. In yet another example, the current 1397 is the same as the jittering current 697, the jittering current 1097, or the jittering current 1297. In yet another example, the ramping signal 1398 is the same as the ramping signal 628, the ramping signal 1028, or the ramping signal 1228. In yet another example, the current-source component 1302 is included in the voltage-to-current-conversion component 640, the current-sensing component 1040, or the current-sensing component 1240. In yet another example, the current-source component 1304 is included in the voltage-to-current-conversion component 642, the voltage-to-current-conversion component 1042, or the voltage-to-current-conversion component 1242. In yet another example, the current-source component 1399 is included in the jittering-signal generator 699, the jittering-signal generator 1099, or the jittering-signal generator 1299.
In certain embodiments, the ramping slope of the ramping signal 1398 is determined as follows:

slope=f(I0,Iac,Icomp,Ij)  (Equation 10)

For example, specifically, the ramping slope of the ramping signal 1398 is determined as follows:

slope ∝(α×I0−β×Iac−δ×Icomp−γ×Ij)  (Equation 11A)

where I0 represents the signal 1336, Iac represents the signal 1332, and Icomp represents the signal 1334. In addition, α, β, δ, and γ represent coefficients (e.g., larger than 0). In another example, the ramping slope of the ramping signal 1398 is determined as follows:

slope ∝(α×I0−β×Iac−δ×Icomp+γ×Ij)  (Equation 11B)

In yet another example, the signal 1332 and the signal 1334 are determined as follows:

Iac=f1(Vbulk)

Icomp=f2(Vcomp)  (Equation 12)

where f1 and f2 represent non-linear or linear operators. As an example,

Iac=γ×(Vbulk−Vth2),Iac=0 when Vbulk≦Vth 

Icomp=η×(Vcomp−Vth1),Icomp=0 when Vbulk≦Vth1  (Equation 13)

where γ and η represent coefficients (e.g., larger than 0), Vth1 and Vth2 represent predetermined thresholds.

In one embodiment, if a ratio related to the transistors 1308 and 1310 is K and another ratio related to the transistors 1312 and 1314 is M, the charging current 1340 is determined as follows:

Icharge=K×M×(I0−Iac−Icomp−Ij)  (Equation 14)

For example, a ramping slope associated with the ramping signal 1398 is determined as follows:





  
    
      
        slope
        =
        
          
            I
            charge
          
          C
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          15
        
        )
      
    
  




where Icharge represents the charging current 1340, and C represents the capacitance of the capacitor 1318. In certain embodiments, for a given I0 and Icomp, the ramping slope of the ramping signal 1398 decreases in magnitude and in turn the duration of an on-time period increases when a bulk voltage increases in magnitude. In yet another example, Icharge is also determined as follows:

Icharge=K×M×(I0−Iac−Icomp+Ij)  (Equation 16)

FIG. 8(b) is a simplified diagram showing certain components as part of the controller 402 as shown in FIG. 4(d), the controller 802 as shown in FIG. 5(c), and/or the controller 1102 as shown in FIG. 7(c) according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. A ramp-signal generator 1800 includes transistors 1808, 1810, 1812, 1814, 1816 and 1820, an amplifier 1822, and a NOT gate 1824. In addition, current-source components 1802, 1806 and 1899 are included in the controller 402 as shown in FIG. 4(d), the controller 802 as shown in FIG. 5(c), and/or the controller 1102 as shown in FIG. 7(c).
According to one embodiment, the current-source components 1802, 1806 and 1899 are related to currents 1832, 1836 and 1897 respectively. For example, a current-mirror circuit including the transistors 1808, 1810, 1812 and 1814 is configured to generate a charging current 1840 (e.g., Icharge) that flows through the transistor 1816 which is controlled by a signal 1828. In another example, the amplifier 1822 receives a reference signal 1830 and outputs an amplified signal 1838. In yet another example, the capacitor 1818 is charged or discharged to generate a ramping signal 1898 as the output signal of the ramp-signal generator 1800.
In some embodiments, the ramp-signal generator 1800 is the same as the ramp-signal generator 1402. For example, the current 1832 is the same as the current 1436 that flows between the ramp-signal generator 1402 and the voltage-to-current-conversion component 1440, the current 1536 that flows between the ramp-signal generator 1502 and the current-sensing component 1540, or the current 1636 that flows between the ramp-signal generator 1602 and the current-sensing component 1640. In another example, the current 1836 is the same as the current 1494, the current 1594, or the current 1694. In yet another example, the current 1897 is the same as the current 1497, the current 1597, or the current 1697. In yet another example, the ramping signal 1898 is the same as the ramping signal 1428, the ramping signal 1528, or the ramping signal 1628. In yet another example, the current-source component 1802 is included in the voltage-to-current-conversion component 1440, the current-sensing component 1540, or the current-sensing component 1640. In yet another example, the current-source component 1899 is included in the jittering-signal generator 1499, the jittering-signal generator 1599, or the jittering-signal generator 1699.
FIG. 8(c) is a simplified diagram showing certain embodiments as part of the controller 502 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. A ramp-signal generator 1700 includes transistors 1708, 1710, 1712, 1714, 1716 and 1720, an amplifier 1722, and a NOT gate 1724. In addition, current-source components 1704, 1706 and 1799 are included in the controller 502.
According to one embodiment, the current-source components 1704, 1706 and 1799 are related to currents 1734, 1736 and 1797 respectively. For example, a current-mirror circuit including the transistors 1708, 1710, 1712 and 1714 is configured to generate a charging current 1740 (e.g., Icharge) that flows through the transistor 1716 which is controlled by a signal 1728. In another example, the amplifier 1722 receives a reference signal 1730 and outputs an amplified signal 1738. In yet another example, the capacitor 1718 is charged or discharged to generate a ramping signal 1798 as the output signal of the ramp-signal generator 1700.
In some embodiments, the ramp-signal generator 1700 is the same as the ramp-signal generator 502. For example, the current 1734 is the current 738 that flows from the ramp-signal generator 702 to the voltage-to-current-conversion component 742. In yet another example, the current 1736 is the same as the current 794. In yet another example, the current 1797 is the same as the current 797. In yet another example, the ramping signal 1798 is the same as the ramping signal 728. In yet another example, the current-source component 1704 is included in the voltage-to-current-conversion component 742. In yet another example, the current-source component 1799 is included in the jittering-signal generator 799.
FIG. 9 is a simplified diagram showing certain components of a controller according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 1900 includes voltage-to-current-conversion components 1902 and 1904, current-source components 1906 and 1997, and a ramp-signal generator 1999. The ramp-signal generator 1999 includes transistors 1908, 1910, 1912, 1914, 1916 and 1920, an amplifier 1922, and a NOT gate 1924. The voltage-to-current-conversion component 1902 includes an operational amplifier 1970, a current-source component 1958, transistors 1960, 1962, 1964 and 1968, and a resistor 1966. The voltage-to-current-conversion component 1904 includes an operational amplifier 1976, a current-source component 1984, transistors 1978, 1980, 1986 and 1988, and a resistor 1982.
According to one embodiment, the voltage-to-current-conversion components 1902 and 1904, the current-source component 1906, and the current-source component 1997 are related to currents 1932, 1934, 1936 and 1995 respectively. For example, a current-mirror circuit including the transistors 1908, 1910, 1912 and 1914 is configured to generate a charging current 1940 (e.g., Icharge) that flows through the transistor 1916 which is controlled by a signal 1928. In another example, the amplifier 1922 receives a reference signal 1930 and outputs an amplified signal 1938. In yet another example, the capacitor 1918 is charged or discharged to generate a ramping signal 1998 as the output signal of the ramp-signal generator 1999.
According to another embodiment, the operational amplifier 1976 receives a compensation signal 1974 and outputs a signal 1990 which is received by a current-mirror circuit including the transistors 1978, 1980, 1986 and 1988 to generate the current 1934. For example, the operational amplifier 1970 receives a signal 1972 and outputs a signal 1956 which is received by a current-mirror circuit including transistors 1968, 1964, 1962 and 1960 to generate the current 1932.
In some embodiments, the controller 1900 is the same as the controller 402. For example, the ramp-signal generator 1999 is the same as the ramp-signal generator 602. As an example, the current 1932 is the same as the current 636 that flows between the ramp-signal generator 602 and the voltage-to-current-conversion component 640. In another example, the current 1934 is the same as the current 638 that flows between the ramp-signal generator 602 and the voltage-to-current-conversion component 642. In yet another example, the current 1936 is the same as the current 694. In yet another example, the current 1995 is the same as the jittering current 697. In yet another example, the ramping signal 1998 is the same as the ramping signal 628. In yet another example, the compensation signal 1974 is related to the compensation signal 474, and the signal 1972 is related to the signal 472. In yet another example, the voltage-to-current-conversion component 1902 is the same as the voltage-to-current-conversion component 640. In yet another example, the voltage-to-current-conversion component 1904 is the same as the voltage-to-current-conversion component 642. In yet another example, the current-source component 1997 is included in the jittering-signal generator 699.
According to another embodiment, based on Equation 12 and Equation 13, a current 1992 (e.g., Ib1) related to the current-source component 1984 is associated with η×Vth1, and a current 1954 (e.g., Ib2) related to the current-source component 1958 is associated with γ×Vth2. For example, the ramping signal 1998 increases, linearly or non-linearly, to a peak magnitude during each switching period of the power conversion system. In another example, a ramping slope associated with the ramping signal 1998 is determined as follows:




  
    
      
        slope
        =
        
          
            I
            charge
          
          C
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          16
        
        )
      
    
  




where Icharge represents the charging current 1940, and C represents the capacitance of the capacitor 1918. In yet another example, an on-time period associated with a drive signal related to a power switch is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              
                V
                comp
              
              -
              
                V
                ref
              
            
            
              I
              charge
            
          
          ×
          C
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          17
        
        )
      
    
  




where Vcomp represents the signal 1974, Vref represents the signal 1930, Icharge represents the charging current 1940, and C represents the capacitance of the capacitor 1918.

As discussed above and further emphasized here, FIG. 9 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the current-source component 1904 is removed from the controller 1900, and the ramp-signal generator 1999 is then the same as the ramp-signal generator 1800. In another example, the current-source component 1902 is removed from the controller 1900, and the ramp-signal generator 1999 is then the same as the ramp-signal generator 1700.
As discussed above and further emphasized here, FIG. 4(a), FIG. 4(b), FIG. 4(c), and/or FIG. 4(d) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, to achieve high efficiency (e.g., >90%), the system 400 operates in a quasi-resonant (QR) mode. As an example, the controller 402 is implemented to change the duration of an on-time period (e.g., Ton) with the bulk voltage 450 (e.g., associated with a rectified sine waveform) to improve the total harmonic distortion, e.g., as shown in FIG. 10(a), FIG. 10(b), and/or FIG. 10(c).
FIG. 10(a) is a simplified diagram showing the controller 402 as part of the power conversion system 400 according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 402 includes a ramp-signal generator 2602, a UVLO component 2604, a modulation component 2606, a logic controller 2608, a driving component 2610, a demagnetization detector 2612, an error amplifier 2616, a current-sensing-and-sample/hold component 2614, a total-harmonic-distortion (THD) optimizer 2699, a conversion component 2640, and a voltage-to-current-conversion component 2642.
According to one embodiment, the UVLO component 2604 detects the signal 454 and outputs a signal 2618 (e.g., por). For example, if the signal 454 is larger than a first predetermined threshold in magnitude, the controller 402 begins to operate normally. If the signal 454 is smaller than a second predetermined threshold in magnitude, the controller 402 is turned off. In another example, the second predetermined threshold is smaller than the first predetermined threshold in magnitude. As another example, the conversion component 2640 receives the signal 472 at the terminal 464 (e.g., terminal VAC) and outputs a signal 2636 to the THD optimizer 2699. In yet another example, the THD optimizer 2699 also receives the compensation signal 474 at the terminal 448 (e.g., terminal COMP) and outputs a signal 2697 (e.g., Vcomp_int). In yet another example, the THD optimizer 2699 transforms the compensation signal 474 to the signal 2697 (e.g., Vcomp_int) based at least in part on the signal 2636 associated with the signal 472. In yet another example, the capacitor 434 is coupled to the terminal 448 (e.g., terminal COMP) and forms, together with the error amplifier 2616, an integrator or a low-pass filter. In yet another example, the error amplifier 2616 is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal 2622 and the signal 2620. In yet another example, the error amplifier 2616 together with the capacitor 434 generates the compensation signal 474 which is a voltage signal. As an example, the signal 2636 includes one or more current signals. As another example, the signal 2636 includes one or more voltage signals.
According to another embodiment, the error amplifier 2616 receives a signal 2620 from the current-sensing-and-sample/hold component 2614 and a reference signal 2622, and the compensation signal 474 is provided to the voltage-to-current-conversion component 2642 which outputs a current 2638 (e.g., Icomp) to the ramp-signal generator 2602. For example, the current-sensing-and-sample/hold component 2614 samples the current sensing signal 496 in response to the control signal 2630 and then holds the sampled signal until the current-sensing-and-sample/hold component 2614 samples again the current sensing signal 496. As an example, the ramp-signal generator 2602 also receives a current signal 2694 (e.g., I0) and generates a ramping signal 2628 to the modulation component 2606 (e.g., a comparator) which also receives the signal 2697 (e.g., Vcomp_int) from the THD optimizer 2699. As an example, the ramping signal 2628 increases, linearly or non-linearly, to a peak magnitude during each switching period. As another example, the ramping slope of the ramping signal 2628 varies based at least in part on the compensation signal 474. In yet another example, the current 2638 (e.g., Icomp) flows from the voltage-to-current-conversion component 2642 to the ramp-signal generator 2602. In yet another example, the current 2638 (e.g., Icomp) flows from the ramp-signal generator 2602 to the voltage-to-current-conversion component 2642.
According to yet another embodiment, the modulation component 2606 outputs a modulation signal 2626. For example, the logic controller 2608 processes the modulation signal 2626 and outputs a control signal 2630 to the current-sensing-and-sample/hold component 2614 and the driving component 2610. In another example, the driving component 2610 generates a signal 2656 related to the drive signal 456 to affect the switch 428. In yet another example, if the signal 2656 is at the logic high level, the signal 456 is at the logic high level, and if the signal 2656 is at the logic low level, the signal 456 is at the logic low level.
In one embodiment, the demagnetization detector 2612 detects the feedback signal 460 and outputs a demagnetization signal 2632 for determining the end of the demagnetization process of the secondary winding 414. As another example, the demagnetization detector 2612 detects the feedback signal 460 and outputs the demagnetization signal 2632 for determining the beginning and the end of the demagnetization process of the secondary winding 414. In yet another example, the demagnetization detector 2612 outputs a trigger signal 2698 to the logic controller 2608 to start a next cycle (e.g., corresponding to a next switching period).
In another embodiment, the system controller 402 changes the duration of the on-time period during which the power switch 428 is kept closed (e.g., being turned on) by different magnitudes corresponding to different switching periods of the power switch 428 respectively, based on at least information associated with the signal 472. For example, the duration of the on-time period associated with the power switch 428 is changed during different switching periods of the power switch 428 adjacent to each other. In another example, the duration of the on-time period associated with the power switch 428 is changed during different switching periods of the power switch 428 not adjacent to each other.
FIG. 10(b) is a simplified timing diagram for the controller 402 as part of the power conversion system 400 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform 2902 represents the signal 2626 as a function of time, the waveform 2904 represents the signal 2656 as a function of time, the wave form 2906 represents the demagnetization signal 2632 as a function of time, the waveform 2908 represents the trigger signal 2698 as a function of time, and the waveform 2910 represents the ramping signal 2628 as a function of time.
An on-time period and an off-time period associated with the signal 2656 are shown in FIG. 10(b). The on-time period begins at a time t13 and ends at a time t15, and the off-time period begins at the time t15 and ends at a time t18. For example, t10≦t11≦t12≦t13≦t14≦t15≦t16≦t17≦t18.
According to one embodiment, at t10, the demagnetization signal 2632 changes from the logic low level to the logic high level. For example, the demagnetization detector 2612 generates a pulse (e.g., between t10 and t12) in the trigger signal 2698 to trigger a new cycle. As an example, the ramping signal 2628 begins to increases from a magnitude 2912 to a magnitude 2914 (e.g., at t14). In another example, at t11, the signal 2626 changes from the logic low level to the logic high level. After a short delay, the signal 2656 changes (e.g., at t13) from the logic low level to the logic high level, and in response the switch 428 is turned on. In yet another example, at t14, the signal 2626 changes from the logic high level to the logic low level, and the ramping signal 2628 decreases from the magnitude 2914 to the magnitude 2912. After a short delay, the signal 2656 changes (e.g., at t15) from the logic high level to the logic low level, and in response, the switch 428 is turned off. As an example, at t16, the demagnetization signal 2632 changes from the logic low level to the logic high level which indicates a beginning of a demagnetization process. In another example, at t17, the demagnetization signal 2632 changes from the logic high level to the logic low level which indicates an end of the demagnetization process. In yet another example, the demagnetization detector 2612 generates another pulse in the trigger signal 2698 to start a next cycle. In yet another example, the magnitude 2914 of the ramping signal 2628 is associated with the magnitude of the signal 474.
According to another embodiment, the magnitude change of the ramping signal 2628 during the on-time period is determined as follows:

ΔVramp=Vcomp_int−Vref=slope×Ton  (Equation 18)

where ΔVramp represents the magnitude changes of the ramping signal 2628, Vcomp_int represents the signal 2697, Vref represents a predetermined voltage magnitude, slope represents a ramping slope associated with the ramping signal 2628, and Ton represents the duration of the on-time period. For example, Vref corresponds to a minimum magnitude of the ramping signal 2628. As an example, based on Equation 18, the duration of the on-time period is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              V
              comp_int
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          19
        
        )
      
    
  




According to yet another embodiment, the signal 2697 (e.g., Vcomp_int) is determined as follows:

Vcomp_int+Vcomp+α×Vbulk  (Equation 20)

where Vcomp represents the compensation signal 474, Vbulk represents the bulk voltage 450, and a represents a coefficient parameter. Combining Equations 19 and 20, for example, the duration of the on-time period is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              V
              comp
            
            +
            
              α
              ×
              
                V
                bulk
              
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          21
        
        )
      
    
  




Combining Equations 3 and 21, as an example, the duration of the on-time period is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              V
              comp
            
            +
            
              α
              ×
              
                
                
                  A
                  ⁢
                  
                    
                  
                  ⁢
                  
                    sin
                    ⁡
                    
                      (
                      
                        
                          ω
                          ⁢
                          
                            
                          
                          ⁢
                          t
                        
                        +
                        φ
                      
                      )
                    
                  
                
                
              
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          22
        
        )
      
    
  




As shown in Equations 21 and 22, the duration of the on-time period is not constant, and varies with the bulk voltage 450 associated with the AC input signal 452, according to some embodiments. For example, changing the duration of the on-time period with the bulk voltage 450 is applicable to power conversion systems with a buck-boost topology operated in a quasi-resonant (QR) mode. In another example, a slope of the waveform 2910 between t11 and t14 corresponds to the ramping slope of the ramping signal 2628. In yet another example, changing the duration of the on-time period with the bulk voltage 450 is applicable to power conversion systems with a flyback topology operated in a quasi-resonant (QR) mode.
FIG. 10(c) is a simplified diagram showing certain components of the controller 402 as part of the system 400 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
For example, the voltage-to-current-conversion component 2642 includes an operational amplifier 3976, a current-source component 3984, transistors 3978, 3980, 3986 and 3988, and a resistor 3982. The ramp-signal generator 2602 includes transistors 3908, 3910, 3912, 3914, 3916 and 3920, an amplifier 3922, and an NOT gate 3924. The conversion component 2640 includes an operational amplifier 3970, a current-source component 3958, transistors 3995, 3997, 3932, 3960, 3962, 3964 and 3968, and a resistor 3966. The THD optimizer 2699 includes an operational amplifier 3936, and resistors 3944 and 3946. The controller 402 further includes a current-source component 3906 which provides the current signal 2694 (e.g., I0). As an example, the transistors 3908, 3910, 3920, 3986, 3988, 3962, 3960 and 3932 are N-channel transistors, and the transistors 3978, 3980, 3912, 3914, 3916, 3968, 3964, 3995 and 3997 are P-channel transistors.
According to one embodiment, the amplifier 3922 receives a reference signal 3930 (e.g., Vref) at its non-inverting terminal (e.g., terminal “+”) and outputs an amplified signal 3938, where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier 3922 are connected together. For example, the signal 3928 (e.g., PWM_N) is generated by the NOT gate 3924 and is complementary to the modulation signal 2626 (e.g., PWM). As an example, if the modulation signal 2626 (e.g., PWM) is at the logic high level, the signal 3928 (e.g., PWM_N) is at the logic low level, and if the modulation signal 2626 (e.g., PWM) is at the logic low level, the signal 3928 (e.g., PWM_N) is at the logic high level. In another example, the transistors 3920 and the transistor 3916 are controlled by the signal 3928 (e.g., PWM_N). In one embodiment, if the signal 3928 (e.g., PWM_N) is at the logic high level, the transistor 3920 is turned on and the transistor 3916 is turned off. The amplified signal 3938 is provided through the transistor 3920 to generate the ramping signal 2628 as the output signal of the ramp-signal generator 2602. In another embodiment, if the signal 3928 (e.g., PWM_N) is at the logic low level, the transistor 3920 is turned off and the transistor 3916 is turned on. A current-mirror circuit including the transistors 3908, 3910, 3912 and 3914 is configured to generate a charging current 3940 (e.g., Icharge) that flows through the transistor 3916. The capacitor 3918 is charged in response to the current 3940 through the transistor 3916 to generate the ramping signal 2628 as the output signal of the ramp-signal generator 2602.
According to another embodiment, the operational amplifier 3976 receives the compensation signal 474 (e.g., Vcomp) at its non-inverting terminal (e.g., terminal “+”) and outputs a signal 3990 which is received by a current-mirror circuit including the transistors 3978, 3980, 3986 and 3988 to generate the current 2638 (e.g., Icomp). For example, a current 3981 that flows through the transistor 3978 is proportional in magnitude to (e.g., equal to) a sum of a current 3992 provided by the current-source component 3984 and a current 3991 that flows through the transistor 3986. In another example, the current 3991 is proportional in magnitude to (e.g., equal to) the current 2638 (e.g., Icomp). In yet another example, the current 2694 (e.g., I0) is proportional in magnitude to (e.g., equal to) a sum of the current 2638 (e.g., Icomp) and a current 3911 that flows through the transistor 3908. In yet another example, the current 3911 is proportional in magnitude to (e.g., equal to) the current 3940 (e.g., Icharge).
According to yet another embodiment, the operational amplifier 3970 receives the signal 472 associated with the bulk voltage 450 and outputs a signal 3956 to the transistor 3968 to generate a current 3967 flowing through the resistor 3966 (e.g., R2). For example, a current-mirror circuit including the transistors 3968 and 3964 generates a current 3969 that flows through the transistor 3964. As an example, the current 3969 is proportional in magnitude to (e.g., equal to) the current 3967. As another example, the current-source component 3958 provides a current 3954 (e.g., Ib2), and a current 3963 that flows through the transistor 3962 is equal in magnitude to a difference between the current 3969 and the current 3954. As yet another example, a current-mirror circuit including the transistors 3962 and 3960 generates a current 3961. For example, the current 3961 flows through the transistor 3960 and is mirrored to generate a current 3942 (e.g., Iac_n). In another example, the current 3961 flows through the transistor 3995 and is mirrored to generate a current 3940 (e.g., Iac_p). In yet another example, the current 3961 is proportional in magnitude to (e.g., equal to) the current 3940 (e.g., Iac_p). In yet another example, the current 3961 is proportional in magnitude to (e.g., equal to) the current 3942 (e.g., Iac_n).
In one embodiment, the THD optimizer 2699 receives both the current 3940 (e.g., Iac_p) and the current 3942 (e.g., Iac_p) as well as the compensation signal 474 (e.g., Vcomp) and outputs the signal 2697 (e.g., Vcomp_int) to the modulation component 2606 (e.g., a comparator). As an example, the operational amplifier 3936 receives the compensation signal 474 (e.g., Vcomp) at its non-inverting terminal (e.g., terminal “+”), where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier 3936 are connected together. As another example, the current 3942 (e.g., Iac_n) flows through the resistor 3944 (e.g., R3) and the current 3940 (e.g., Iac_p) flows through the resistor 3946 (e.g., R4) to generate the signal 2697 (e.g., Vcomp_int). For example, the current 3940 (e.g., Iac_p) and the current 3942 (e.g., Iac_n) are included in the signal 2636 generated by the conversion component 2640 (e.g., as shown in FIG. 10(a)).
In another embodiment, the current 3940 (e.g., Iac_p) is determined as follows:




  
    
      
        
          I
          ac_p
        
        =
        
          
            VAC
            
              R
              ⁢
              
                
              
              ⁢
              2
            
          
          -
          
            Ib
            ⁢
            
              
            
            ⁢
            2
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          23
        
        )
      
    
  




where VAC represents the signal 472, R2 represents the resistance of the resistor 3966, and Ib2 represents the current 3954. As an example, VAC=γ×Vbulk, where γ represents a coefficient parameter. For example, if





  
    
      γ
      ×
      
        
          V
          bulk
        
        
          R
          ⁢
          
            
          
          ⁢
          2
        
      
    
    ≥
    
      Ib
      ⁢
      
        
      
      ⁢
      2
    
  
  ,




the current 3940 (e.g., Iac_p) is determined as follows:





  
    
      
        
          I
          ac_p
        
        =
        
          
            
              γ
              ×
              
                V
                bulk
              
            
            
              R
              ⁢
              
                
              
              ⁢
              2
            
          
          -
          
            Ib
            ⁢
            
              
            
            ⁢
            2
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          24
        
        )
      
    
  




In another example, if





  
    
      γ
      ×
      
        
          V
          bulk
        
        
          R
          ⁢
          
            
          
          ⁢
          2
        
      
    
    <
    
      Ib
      ⁢
      
        
      
      ⁢
      2
    
  
  ,




the current 3940 (e.g., Iac_p) is determined to be zero. In some embodiments, the current 3942 (e.g., Iac_n) is equal in magnitude to the current 3940 (e.g., Iac_p).

In yet another embodiment, if




  
    
      
        γ
        ×
        
          
            V
            bulk
          
          
            R
            ⁢
            
              
            
            ⁢
            2
          
        
      
      -
      
        Ib
        ⁢
        
          
        
        ⁢
        2
      
    
    ≥
    0
  
  ,




the signal 2697 (e.g., Vcomp_int) is determined as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  a
                  ⁢
                  
                    
                  
                  ⁢
                  c
                  ⁢
                  
                    
                  
                  ⁢
                  _
                  ⁢
                  
                    
                  
                  ⁢
                  p
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                (
                
                  
                    
                      γ
                      ×
                      
                        V
                        bulk
                      
                    
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  -
                  
                    Ib
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                )
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          25
        
        )
      
    
  




where Vcomp represents the compensation signal 474, R3 represents the resistance of the resistor 3944, and R4 represents the resistance of the resistor 3946. For example, if Ib2 is equal to zero, the signal 2697 (e.g., Vcomp_int) is determined, based on Equation 25, as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    c
                    ⁢
                    
                      
                    
                    ⁢
                    _
                    ⁢
                    
                      
                    
                    ⁢
                    p
                  
                  ⁢
                  
                    
                  
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                
                  γ
                  ×
                  
                    V
                    bulk
                  
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          26
        
        )
      
    
  




Combining Equation 3 and Equation 26, the signal 2697 (e.g., Vcomp_int) is determined as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  a
                  ⁢
                  
                    
                  
                  ⁢
                  c
                  ⁢
                  
                    
                  
                  ⁢
                  _
                  ⁢
                  
                    
                  
                  ⁢
                  p
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                
                  γ
                  ×
                  
                    
                    
                      A
                      ⁢
                      
                        
                      
                      ⁢
                      
                        sin
                        ⁡
                        
                          (
                          
                            
                              ω
                              ⁢
                              
                                
                              
                              ⁢
                              t
                            
                            +
                            φ
                          
                          )
                        
                      
                    
                    
                  
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          27
        
        )
      
    
  




In yet another embodiment, combining Equation 19 and Equation 27, the duration of the on-time period associated with the switch 428 is determined as follows:




  
    
      
        
          T
          on
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                
                  γ
                  ×
                  
                    
                    
                      A
                      ⁢
                      
                        
                      
                      ⁢
                      
                        sin
                        ⁡
                        
                          (
                          
                            
                              ω
                              ⁢
                              
                                
                              
                              ⁢
                              t
                            
                            +
                            φ
                          
                          )
                        
                      
                    
                    
                  
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          28
        
        )
      
    
  




As discussed above and further emphasized here, FIG. 5(a), FIG. 5(b), and/or FIG. 5(c) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, to achieve high efficiency (e.g., >90%), the system 800 operates in a quasi-resonant (QR) mode. As an example, the controller 802 is implemented to change the duration of an on-time period (e.g., Ton) with the bulk voltage 850 (e.g., associated with a rectified sine waveform) to improve the total harmonic distortion, e.g., as shown in FIG. 11(a) and/or FIG. 11(b).
FIG. 11(a) is a simplified diagram showing the controller 802 as part of the power conversion system 800 according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 802 includes a ramp-signal generator 3002, a UVLO component 3004, a modulation component 3006, a logic controller 3008, a driving component 3010, a demagnetization detector 3012, an error amplifier 3016, a current-sensing-and-sample/hold component 3014, a total-harmonic-distortion (THD) optimizer 3099, a current-sensing component 3040, and a voltage-to-current-conversion component 3042.
According to one embodiment, the UVLO component 3004 detects the signal 854 and outputs a signal 3018 (e.g., por). For example, if the signal 854 is larger than a first predetermined threshold in magnitude, the controller 802 begins to operate normally. If the signal 854 is smaller than a second predetermined threshold in magnitude, the controller 802 is turned off. In another example, the second predetermined threshold is smaller than the first predetermined threshold in magnitude. As another example, the current-sensing component 3040 receives the signal 872 at the terminal 864 (e.g., terminal I_AC) and outputs a signal 3036 to the THD optimizer 3099. In yet another example, the THD optimizer 3099 also receives the compensation signal 874 at the terminal 848 (e.g., terminal COMP) and outputs a signal 3097 (e.g., Vcomp_int). In yet another example, the THD optimizer 3099 transforms the compensation signal 874 to the signal 3097 (e.g., Vcomp_int) based at least in part on the signal 3036 associated with the signal 872. In yet another example, the capacitor 834 is coupled to the terminal 848 (e.g., terminal COMP) and forms, together with the error amplifier 3016, an integrator or a low-pass filter. In yet another example, the error amplifier 3016 is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal 3022 and the signal 3020. In yet another example, the error amplifier 3016 together with the capacitor 834 generates the compensation signal 874 which is a voltage signal. As an example, the signal 3036 includes one or more current signals. As another example, the signal 3036 includes one or more voltage signals.
According to another embodiment, the error amplifier 3016 receives a signal 3020 from the current-sensing-and-sample/hold component 3014 and a reference signal 3022, and the compensation signal 874 is also provided to the voltage-to-current-conversion component 3042 which outputs a current 3038 (e.g., Icomp) to the ramp-signal generator 3002. For example, the current-sensing-and-sample/hold component 3014 samples the current sensing signal 896 in response to the control signal 3030 and then holds the sampled signal until the current-sensing-and-sample/hold component 3014 samples again the current sensing signal 896. As an example, the ramp-signal generator 3002 also receives a current signal 3094 (e.g., I0) and generates a ramping signal 3028 to the modulation component 3006 (e.g., a comparator) which also receives the signal 3097 (e.g., Vcomp_int) from the THD optimizer 3099. As an example, the ramping signal 3028 increases, linearly or non-linearly, to a peak magnitude during each switching period. As another example, the ramping slope of the ramping signal 3028 varies based at least in part on the compensation signal 874. In yet another example, the current 3038 (e.g., Icomp) flows from the voltage-to-current-conversion component 3042 to the ramp-signal generator 3002. In yet another example, the current 3038 (e.g., Icomp) flows from the ramp-signal generator 3002 to the voltage-to-current-conversion component 3042.
According to yet another embodiment, the modulation component 3006 outputs a modulation signal 3026. For example, the logic controller 3008 processes the modulation signal 3026 and outputs a control signal 3030 to the current-sensing-and-sample/hold component 3014 and the driving component 3010. In another example, the driving component 3010 generates a signal 3056 related to the drive signal 856 to affect the switch 828. In another example, if the signal 3056 is at a logic high level, the signal 856 is at a logic high level, and if the signal 3056 is at a logic low level, the signal 856 is at a logic low level.
In one embodiment, the demagnetization detector 3012 detects the feedback signal 860 and outputs a demagnetization signal 3032 for determining the end of the demagnetization process of the secondary winding 814. As another example, the demagnetization detector 3012 detects the feedback signal 860 and outputs the demagnetization signal 3032 for determining the beginning and the end of the demagnetization process of the secondary winding 814. In yet another example, the demagnetization detector 3012 outputs a trigger signal 3098 to the logic controller 3008 to start a next cycle (e.g., corresponding to a next switching period).
In another embodiment, the system controller 802 changes the duration of the on-time period during which the power witch 828 is kept closed (e.g., being turned on) by different magnitudes corresponding to different switching periods of the power switch 828 respectively, based on at least information associated with the signal 872. For example, the duration of the on-time period associated with the power switch 828 is changed during different switching periods of the power switch 828 adjacent to each other. In another example, the duration of the on-time period associated with the power switch 828 is changed during different switching periods of the power switch 828 not adjacent to each other.
FIG. 11(b) is a simplified diagram showing certain components of the controller 802 as part of the system 800 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
For example, the ramp-signal generator 3002 includes transistors 3108, 3110, 3112, 3114, 3116 and 3120, an amplifier 3122, and an NOT gate 3124. The THD optimizer 3099 includes an operational amplifier 3136, and resistors 3144 and 3146. The current-sensing component 3040 includes transistors 3132, 3160, 3162, 3164 and 3168, and a current-source component 3134. As an example, the transistors 3108, 3110, 3120, 3162, 3160 and 3132 are N-channel transistors, and the transistors 3112, 3114, 3116, 3168 and 3164 are P-channel transistors.
According to one embodiment, the amplifier 3122 receives a reference signal 3130 (e.g., Vref) at its non-inverting terminal (e.g., terminal “+”) and outputs an amplified signal 3138, where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier 3122 are connected together. In another example, the signal 3128 (e.g., PWM_N) is generated by the NOT gate 3124 and is complementary to the modulation signal 3026 (e.g., PWM). As an example, if the modulation signal 3026 (e.g., PWM) is at the logic high level, the signal 3128 (e.g., PWM_N) is at the logic low level, and if the modulation signal 3026 (e.g., PWM) is at the logic low level, the signal 3128 (e.g., PWM_N) is at the logic high level. In another example, the transistors 3120 and the transistor 3116 are controlled by the signal 3128 (e.g., PWM_N). In one embodiment, if the signal 3128 (e.g., PWM_N) is at the logic high level, the transistor 3120 is turned on and the transistor 3116 is turned off. The amplified signal 3138 is provided through the transistor 3120 to generate the ramping signal 3028 as the output signal of the ramp-signal generator 3002. In another embodiment, if the signal 3128 (e.g., PWM_N) is at the logic low level, the transistor 3120 is turned off and the transistor 3116 is turned on. A current-mirror circuit including the transistors 3108, 3110, 3112 and 3114 is configured to generate a charging current 3140 (e.g., Icharge) that flows through the transistor 3116. The capacitor 3118 is charged in response to the current 3140 through the transistor 3116 to generate the ramping signal 3028 as the output signal of the ramp-signal generator 3002. For example, a current 3198 flows through the transistor 3108 and is proportional in magnitude to the current 3140 (e.g., Icharge). In another example, the current 3094 (e.g., I0) is equal in magnitude to a sum of the current 3198 and the current 3038 (e.g., Icomp).
According to another embodiment, a current 3196 flows through the transistor 3162 and the current 872 (e.g., Iac) is equal in magnitude to a sum of the current 3196 and a current 3154 (e.g., Ib2) provided by the current-source component 3134. For example, a current-mirror circuit including the transistors 3162, 3160 and 3132 generates a current 3142 (e.g., Iac_n) which is proportional in magnitude to (e.g., equal to) the current 3196. In another example, a current-mirror circuit including the transistors 3162, 3160, 3168 and 3164 generates a current 3140 (e.g., Iac_p) which is proportional in magnitude to (e.g., equal to) the current 3196.
According to yet another embodiment, the operational amplifier 3136 receives the compensation signal 874 (e.g., Vcomp) at its non-inverting terminal (e.g., terminal “+”) and outputs a signal 3190 to the resistor 3144 (e.g., R3) and the resistor 3146 (e.g., R4). For example, the signal 3190 is associated with at least the current 3142 (Iac_n). As an example, the signal 3097 (e.g., Vcomp_int) is generated based at least in part on the current 3140 (e.g., Iac_p) and the current 3142 (Iac_n) and output to the modulation component 3006 (e.g., a comparator). For example, the current 3140 (e.g., Iac_p) and the current 3142 (e.g., Iac_n) are included in the signal 3036 generated by the current-sensing component 3040 (e.g., as shown in FIG. 11(a)).
In one embodiment, if Iac≧Ib2, the current 3140 (e.g., Iac_p) is determined as follows:

Iac_p=Iac−Ib2  (Equation 29)

where Iac represents the current signal 872, and Ib2 represents the current 3154. For example, if Iac<Ib2, the current 3140 (e.g., Iac_p) is determined to be zero. In some embodiments, the current 3142 (e.g., Iac_n) is equal in magnitude to the current 3140 (e.g., Iac_p).

As discussed above and further emphasized here, FIG. 7(a), FIG. 7(b), and/or FIG. 7(c) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, to achieve high efficiency (e.g., >90%), the system 1100 operates in a quasi-resonant (QR) mode. As an example, the controller 1102 is implemented to change the duration of an on-time period (e.g., Ton) with the bulk voltage 1150 (e.g., associated with a rectified sine waveform) to improve the total harmonic distortion, e.g., as shown in FIG. 12(a) and/or FIG. 12(b).
FIG. 12(a) is a simplified diagram showing the controller 1102 as part of the power conversion system 1100 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller 1102 includes a ramp-signal generator 3202, a UVLO component 3204, a modulation component 3206, a logic controller 3208, a driving component 3210, a demagnetization detector 3212, an error amplifier 3216, a current-sensing-and-sample/hold component 3214, a current-sensing component 3240, a total-harmonic-distortion (THD) optimizer 3299, and a voltage-to-current-conversion component 3242.
According to one embodiment, the UVLO component 3204 detects the signal 1154 and outputs a signal 3218 (e.g., por). For example, if the signal 1154 is larger than a first predetermined threshold in magnitude, the controller 1102 begins to operate normally. If the signal 1154 is smaller than a second predetermined threshold in magnitude, the controller 1102 is turned off. In another example, the first predetermined threshold is larger than the second predetermined threshold in magnitude.
According to another embodiment, the ramp-signal generator 3202 receives a current signal 3294 (e.g., I0) and a current 3238 (e.g., Icomp) from the voltage-to-current-conversion component 3242 and generates a ramping signal 3228 to the modulation component 3206. As an example, the ramping signal 3228 increases, linearly or non-linearly, to a peak magnitude during each switching period. As another example, the ramping slope of the ramping signal 3228 varies based at least in part on the compensation signal 1174. In another example, the modulation component 3206 also receives a signal 3297 (e.g., Vcomp_int) from the THD optimizer 3299 and outputs a modulation signal 3226 to the logic controller 3208. For example, the logic controller 3208 processes the modulation signal 3226 and outputs a control signal 3230 to the current-sensing-and-sample/hold component 3214 and the driving component 3210. In another example, the driving component 3210 generates a signal 3256 related to the drive signal 1156 to affect the switch 1128. In yet another example, if the signal 3256 is at the logic high level, the signal 1156 is at the logic high level, and if the signal 3256 is at the logic low level, the signal 1156 is at the logic low level.
According to yet another embodiment, the error amplifier 3216 receives a signal 3220 from the current-sensing-and-sample/hold component 3214 and a reference signal 3222 (e.g., Vref_ea) and the compensation signal 1174 is provided to the THD optimizer 3299 and the voltage-to-current-conversion component 3242. As an example, the capacitor 1134 is coupled to the terminal 1148 (e.g., terminal COMP) and forms, together with the error amplifier 3216, an integrator or a low-pass filter. In another example, the error amplifier 3216 is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal 3222 and the signal 3220. In yet another example, the error amplifier 3216 together with the capacitor 1134 generates the compensation signal 1174 which is a voltage signal. In yet another example, the current 3238 (e.g., Icomp) flows from the THD optimizer 3299 to the ramp-signal generator 3202. In yet another example, the current 3238 (e.g., Icomp) flows from the ramp-signal generator 3202 to the THD optimizer 3299.
According to yet another embodiment, the current-sensing component 3240 outputs a signal 3236 to the ramp-signal generator 3202 in response to a current signal 3296 associated with the terminal 1140 (e.g., terminal FB). For example, the current signal 3296 is related to the bulk voltage 1150 during the on-time period associated with the driving signal 1156. As an example, the signal 3236 includes one or more current signals. As another example, the signal 3236 includes one or more voltage signals.
In one embodiment, the demagnetization detector 3212 detects the feedback signal 1160 and outputs a demagnetization signal 3232 for determining the end of the demagnetization process of the secondary winding 1114. As another example, the demagnetization detector 3212 detects the feedback signal 1160 and outputs the demagnetization signal 3232 for determining the beginning and the end of the demagnetization process of the secondary winding 1114. In yet another example, the demagnetization detector 3212 outputs a trigger signal 3298 to the logic controller 3208 to start a next cycle (e.g., corresponding to a next switching period).
In another embodiment, the system controller 1102 changes the duration of the on-time period during which the power witch 1128 is kept closed (e.g., being turned on) by different magnitudes corresponding to different switching periods of the power switch 1128 respectively. For example, the duration of the on-time period associated with the power switch 1128 is changed during different switching periods of the power switch 1128 adjacent to each other. In another example, the duration of the on-time period associated with the power switch 1128 is changed during different switching periods of the power switch 1128 not adjacent to each other.
FIG. 12(b) is a simplified diagram showing certain components of the controller 1102 as part of the system 1100 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
For example, the ramp-signal generator 3202 includes transistors 3308, 3310, 3312, 3314, 3316 and 3320, an amplifier 3322, and an NOT gate 3324. The THD optimizer 3299 includes an operational amplifier 3336, and resistors 3344 and 3346. The current-sensing component 3240 includes transistors 3332, 3360, 3362, 3364 and 3368, and a current-source component 3334. As an example, the transistors 3308, 3310, 3320, 3362, 3360 and 3332 are N-channel transistors, and the transistors 3312, 3314, 3316, 3368 and 3364 are P-channel transistors.
According to one embodiment, the amplifier 3322 receives a reference signal 3330 (e.g., Vref) at its non-inverting terminal (e.g., terminal “+”) and outputs an amplified signal 3338, where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier 3322 are connected together. For example, the signal 3328 (e.g., PWM_N) is generated by the NOT gate 3324 and is complementary to the modulation signal 3226 (e.g., PWM). As an example, if the modulation signal 3226 (e.g., PWM) is at the logic high level, the signal 3328 (e.g., PWM_N) is at the logic low level, and if the modulation signal 3226 (e.g., PWM) is at the logic low level, the signal 3328 (e.g., PWM_N) is at the logic high level. In another example, the transistors 3320 and the transistor 3316 are controlled by the signal 3328 (e.g., PWM_N). In one embodiment, if the signal 3328 (e.g., PWM_N) is at the logic high level, the transistor 3320 is turned on and the transistor 3316 is turned off. The amplified signal 3338 is provided through the transistor 3320 to generate the ramping signal 3228 as the output signal of the ramp-signal generator 3202. In another embodiment, if the signal 3328 (e.g., PWM_N) is at the logic low level, the transistor 3320 is turned off and the transistor 3316 is turned on. A current-mirror circuit including the transistors 3308, 3310, 3312 and 3314 is configured to generate a charging current 3340 (e.g., Icharge) that flows through the transistor 3316. The capacitor 3318 is charged in response to the current 3340 through the transistor 3316 to generate the ramping signal 3228 as the output signal of the ramp-signal generator 3202. For example, a current 3398 flows through the transistor 3308 and is proportional in magnitude to the current 3340 (e.g., Icharge). In another example, the current 3294 (e.g., I0) is equal in magnitude to a sum of the current 3398 and the current 3238 (e.g., Icomp).
According to another embodiment, a current 3396 flows through the transistor 3362, and a current 3496 (e.g., Iac) associated with the current 3296 (e.g., IFB) is equal in magnitude to a sum of the current 3396 and a current 3354 (e.g., Ib2) provided by the current-source component 3334. For example, a current-mirror circuit including the transistors 3362, 3360 and 3332 generates a current 3342 (e.g., Iac_n) which is proportional in magnitude to (e.g., equal to) the current 3396. In another example, a current-mirror circuit including the transistors 3362, 3360, 3368 and 3364 generates a current 3340 (e.g., Iac_p) which is proportional in magnitude to (e.g., equal to) the current 3396.
According to yet another embodiment, the operational amplifier 3336 receives the compensation signal 1174 (e.g., Vcomp) at its non-inverting terminal (e.g., terminal “+”) and outputs a signal 3390 to the resistor 3344 (e.g., R3) and the resistor 3346 (e.g., R4). For example, the signal 3390 is associated with at least the current 3342 (Iac_n). As an example, the signal 3297 (e.g., Vcomp_int) is generated based at least in part on the current 3340 (e.g., Iac_p) and the current 3342 (Iac_n) and output to the modulation component 3206 (e.g., a comparator). For example, the current 3340 (e.g., Iac_p) and the current 3342 (e.g., Iac_n) are included in the signal 3236 generated by the current-sensing component 3240 (e.g., as shown in FIG. 12(a)).
Referring to FIG. 7(a), FIG. 12(a) and FIG. 12(b), during an on-time period, the voltage 1198 associated with the auxiliary winding 1116 is determined as follows, in some embodiments:




  
    
      
        
          V
          aux
        
        =
        
          
            -
            
              
                N
                aux
              
              
                N
                p
              
            
          
          ×
          
            V
            bulk
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          30
        
        )
      
    
  




where Vaux represents the voltage 1198, Naux/Np represents a turns ratio between the auxiliary winding 1116 and the primary winding 1112, and Vbulk represents the bulk voltage 1150. In certain embodiments, if a voltage at the terminal 1140 (e.g., terminal FB) is regulated to be approximately zero, the current signal 3296 (e.g., IFB) is detected by the current-sensing component 3240:





  
    
      
        
          I
          FB
        
        =
        
          
            
              V
              aux
            
            
              R
              6
            
          
          =
          
            
              
                N
                aux
              
              
                
                  N
                  p
                
                ×
                
                  R
                  6
                
              
            
            ×
            
              V
              bulk
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          31
        
        )
      
    
  




where IFB represents the current signal 3296 and R6 represents the resistance of the resistor 1124.

According to some embodiments, the current signal 3296 indicates a waveform of the bulk voltage 1150 during the on-time period associated with the drive signal 1156, and the current signal 3496 is determined as follows:




  
    
      
        
          I
          
            a
            ⁢
            
              
            
            ⁢
            c
          
        
        =
        
          
            δ
            ×
            
              I
              FB
            
          
          =
          
            δ
            ×
            
              
                N
                aux
              
              
                
                  N
                  p
                
                ×
                
                  R
                  6
                
              
            
            ×
            
              V
              bulk
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          32
        
        )
      
    
  




where Iac represents the current signal 3496 and 5 represents a constant. For example, if Iac≧Ib2, the current 3340 (e.g., Iac_p) is determined as follows:

Iac_p=Iac−Ib2  (Equation 33)

where Iac represents the current signal 3496, and Ib2 represents the current 3354. For example, if Iac<Ib2, the current 3340 (e.g., Iac_p) is determined to be zero. In some embodiments, the current 3342 (e.g., Iac_n) is equal in magnitude to the current 3340 (e.g., Iac_p).

In one embodiment, if




  
    
      
        δ
        ×
        
          
            N
            aux
          
          
            
              N
              p
            
            ×
            
              R
              6
            
          
        
        ×
        
          V
          bulk
        
      
      -
      
        Ib
        ⁢
        
          
        
        ⁢
        2
      
    
    ≥
    0
  
  ,




the signal 3297 (e.g., Vcomp_int) is determined as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  a
                  ⁢
                  
                    
                  
                  ⁢
                  c
                  ⁢
                  
                    
                  
                  ⁢
                  _
                  ⁢
                  
                    
                  
                  ⁢
                  p
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                (
                
                  
                    δ
                    ×
                    
                      
                        N
                        aux
                      
                      
                        
                          N
                          p
                        
                        ×
                        
                          R
                          6
                        
                      
                    
                    ×
                    
                      V
                      bulk
                    
                  
                  -
                  
                    Ib
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                )
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          34
        
        )
      
    
  




where Vcomp represents the compensation signal 1174, R3 represents the resistance of the resistor 3344, and R4 represents the resistance of the resistor 3346. For example, if Ib2 is equal to zero, the signal 3297 (e.g., Vcomp_int) is determined, based on Equation 34, as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  a
                  ⁢
                  
                    
                  
                  ⁢
                  c
                  ⁢
                  
                    
                  
                  ⁢
                  _
                  ⁢
                  
                    
                  
                  ⁢
                  p
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              δ
              ×
              
                
                  N
                  aux
                
                
                  
                    N
                    p
                  
                  ×
                  
                    R
                    6
                  
                
              
              ×
              
                V
                bulk
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          35
        
        )
      
    
  




Combining Equation 3 and Equation 35, the signal 3297 (e.g., Vcomp_int) is determined as follows:





  
    
      
        
          V
          
            comp
            ⁢
            
              
            
            ⁢
            _
            ⁢
            
              
            
            ⁢
            int
          
        
        =
        
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              
                I
                
                  a
                  ⁢
                  
                    
                  
                  ⁢
                  c
                  ⁢
                  
                    
                  
                  ⁢
                  _
                  ⁢
                  
                    
                  
                  ⁢
                  p
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
          =
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  +
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
              
              ×
              
                V
                comp
              
            
            +
            
              δ
              ×
              
                
                  N
                  aux
                
                
                  
                    N
                    p
                  
                  ×
                  
                    R
                    6
                  
                
              
              ×
              
                
                
                  A
                  ⁢
                  
                    
                  
                  ⁢
                  
                    sin
                    ⁡
                    
                      (
                      
                        
                          ω
                          ⁢
                          
                            
                          
                          ⁢
                          t
                        
                        +
                        φ
                      
                      )
                    
                  
                
                
              
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          36
        
        )
      
    
  




In another embodiment, the magnitude change of the ramping signal 3228 during the on-time period is determined as follows:

ΔVramp=Vcomp_int−Vref=slope×Ton  (Equation 37)

where ΔVramp represents the magnitude changes of the ramping signal 3228, Vcomp_int represents the signal 3297, Vref represents a predetermined voltage magnitude (e.g., the signal 3330), slope represents a ramping slope associated with the ramping signal 3228, and Ton represents the duration of the on-time period. For example, Vref corresponds to a minimum magnitude of the ramping signal 3228. As an example, based on Equation 37, the duration of the on-time period is determined as follows:





  
    
      
        
          T
          on
        
        =
        
          
            
              V
              
                comp
                ⁢
                
                  
                
                ⁢
                _
                ⁢
                
                  
                
                ⁢
                int
              
            
            -
            
              V
              ref
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          38
        
        )
      
    
  




Based on Equation 36 and Equation 38, the duration of the on-time period is determined as follows:




  
    
      
        
          T
          on
        
        =
        
          
            
              
                
                  
                    
                      
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                      
                        
                          R
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                        +
                        
                          R
                          ⁢
                          
                            
                          
                          ⁢
                          4
                        
                      
                    
                    ×
                    
                      V
                      comp
                    
                  
                  +
                  
                    δ
                    ×
                  
                
              
            
            
              
                
                  
                    
                      
                        N
                        aux
                      
                      
                        
                          N
                          p
                        
                        ×
                        
                          R
                          6
                        
                      
                    
                    ×
                    
                      
                      
                        A
                        ⁢
                        
                          
                        
                        ⁢
                        
                          sin
                          ⁡
                          
                            (
                            
                              
                                ω
                                ⁢
                                
                                  
                                
                                ⁢
                                t
                              
                              +
                              φ
                            
                            )
                          
                        
                      
                      
                    
                    ×
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  -
                  
                    V
                    ref
                  
                
              
            
          
          slope
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          39
        
        )
      
    
  




According to one embodiment, a system controller for regulating a power conversion system includes a first controller terminal and a second controller terminal. The first controller terminal is configured to receive a first signal associated with an input signal for a primary winding of a power conversation system. The second controller terminal is configured to output a drive signal to a switch to affect a first current flowing through the primary winding of the power conversion system, the drive signal being associated with an on-time period, the switch being closed during the on-time period. The system controller is configured to adjust a duration of the on-time period based on at least information associated with the first signal. For example, the system controller is implemented according to at least FIG. 4(a), FIG. 4(b), FIG. 4(d), FIG. 5(a), FIG. 5(b), FIG. 5(c), FIG. 7(a), FIG. 7(b), FIG. 7(c), FIG. 8(a), FIG. 8(b), and/or FIG. 9.
According to another embodiment, a system controller for regulating a power conversion system includes a first controller terminal, a ramp-signal generator, and a second controller terminal. The first controller terminal is configured to provide a compensation signal based on at least information associated with a first current flowing through a primary winding of a power conversion system. The ramp-signal generator is configured to receive a first signal associated with the compensation signal and generate a ramping signal based on at least information associated with the first signal, the ramping signal being associated with a ramping slope. The second controller terminal is configured to output a drive signal to a switch based on at least information associated with the ramping signal to affect the first current. The system controller is configured to adjust the ramping slope of the ramping signal based on at least information associated with the compensation signal. For example, the system controller is implemented according to at least FIG. 4(a), FIG. 4(b), FIG. 5(a), FIG. 5(b), FIG. 6(a), FIG. 6(b), FIG. 7(a), FIG. 7(b), FIG. 8(a), FIG. 8(c), and/or FIG. 9.
According to yet another embodiment, a method for regulating a power conversion system includes: receiving a first signal from a first controller terminal, the first signal being associated with an input signal for a primary winding of a power conversation system; adjusting a duration of an on-time period related to a drive signal based on at least information associated with the first signal; and outputting the drive signal from a second controller terminal to a switch to affect a first current flowing through the primary winding of the power conversion system, the switch being closed during the on-time period. For example, the method is implemented according to at least FIG. 4(a), FIG. 4(b), FIG. 4(d), FIG. 5(a), FIG. 5(b), FIG. 5(c), FIG. 7(a), FIG. 7(b), FIG. 7(c), FIG. 8(a), FIG. 8(b), and/or FIG. 9.
According to yet another embodiment, a method for regulating a power conversion system includes: providing a compensation signal by a first controller terminal based on at least information associated with a first current flowing through a primary winding of a power conversion system; generating a first signal based on at least information associated with the compensation signal; and processing information associated with the first signal. The method further includes: adjusting a ramping slope associated with a ramping signal based on at least information associated with the first signal; receiving the ramping signal; generating a drive signal based on at least information associated with the ramping signal; and outputting the drive signal from a second controller terminal to a switch to affect the first current. For example, the method is implemented according to at least FIG. 4(a), FIG. 4(b), FIG. 5(a), FIG. 5(b), FIG. 6(a), FIG. 6(b), FIG. 7(a), FIG. 7(b), FIG. 8(a), FIG. 8(c), and/or FIG. 9.
In one embodiment, a system controller for regulating a power conversion system includes: a signal generator configured to receive a converted signal and a first compensation signal and generate a second compensation signal based at least in part on the converted signal and the first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system; a modulation component configured to receive the second compensation signal and a ramping signal and generate a modulation signal based at least in part on the second compensation signal and the ramping signal; and a drive component configured to receive the modulation signal and output a drive signal based at least in part on the modulation signal to a switch to affect the first current, the drive signal being associated with an on-time period, the switch being closed during the on-time period. The system controller is configured to adjust a duration of the on-time period based at least in part on the converted signal and the second compensation signal. For example, the system controller is implemented according to at least FIG. 4(a), FIG. 5(a), FIG. 7(a), FIG. 10(a), FIG. 10(b), FIG. 10(c), FIG. 11(a), FIG. 11(b), FIG. 12(a), and/or FIG. 12(b).
In another embodiment, a method for regulating a power conversion system includes: receiving a converted signal and a first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system; generating a second compensation signal based at least in part on the converted signal and the first compensation signal; receiving the second compensation signal and a ramping signal; generating a modulation signal based at least in part on the second compensation signal and the ramping signal; receiving the modulation signal; and outputting a drive signal based at least in part on the modulation signal to affect the first current, the drive signal being associated with an on-time period. The outputting a drive signal based at least in part on the modulation signal to affect the first current includes adjusting a duration of the on-time period based at least in part on the converted signal and the second compensation signal. For example, the method is implemented according to at least FIG. 4(a), FIG. 5(a), FIG. 7(a), FIG. 10(a), FIG. 10(b), FIG. 10(c), FIG. 11(a), FIG. 11(b), FIG. 12(a), and/or FIG. 12(b).
For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined.
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.

## Claims

1. A system controller for regulating a power conversion system, the system controller comprising:
a signal generator configured to receive a converted signal and a first compensation signal and generate a second compensation signal based at least in part on the converted signal and the first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system;
a modulation component configured to receive the second compensation signal and a ramping signal and generate a modulation signal based at least in part on the second compensation signal and the ramping signal; and
a drive component configured to receive the modulation signal and output a drive signal based at least in part on the modulation signal to a switch to affect the first current, the drive signal being associated with an on-time period, the switch being closed during the on-time period;
wherein the system controller is configured to adjust a duration of the on-time period based at least in part on the converted signal and the second compensation signal.

2. The system controller of claim 1, further comprising: a conversion component configured to receive a first voltage signal related to the input signal and generate the converted signal based at least in part on the first voltage signal.

3. The system controller of claim 2, further comprising:
a first controller terminal coupled to a voltage processing component, the voltage processing component being configured to receive the input signal and generate the first voltage signal based at least in part on the input signal;
wherein the input signal is received by the primary winding.

4. The system controller of claim 3 wherein the voltage processing component includes a capacitor and two resistors.

5. The system controller of claim 2 wherein the conversion component includes:
an amplifier configured to receive the first voltage signal and a second voltage signal and generate an amplified signal based at least in part on the first voltage signal and the second voltage signal; and
a current-mirror circuit configured to generate the converted signal based at least in part on the amplified signal.

6. The system controller of claim 5 wherein:
the current-mirror circuit is further configured to generate a second current based at least in part on the amplified signal; and
the conversion component further includes: a resistor configured to generate the second voltage signal based at least in part on the second current.

7. The system controller of claim 6 wherein:
the amplifier includes a first input terminal, a second input terminal and an output terminal;
the first input terminal is configured to receive the first voltage signal; and
the second input terminal is coupled to the resistor.

8. The system controller of claim 1 wherein the signal generator includes:
an amplifier configured to receive the first compensation signal and generate an amplified signal based at least in part on the first compensation signal; and
a resistive network configured to generate the second compensation signal based at least in part on the amplified signal and the converted signal.

9. The system controller of claim 8 wherein:
the resistive network includes:
a first resistor including a first resistor terminal and a second resistor terminal; and
a second resistor including a third resistor terminal and a fourth resistor terminal;

the first resistor terminal is coupled to an output terminal of the amplifier; and
the second resistor terminal is coupled to a third resistor terminal and configured to generate the second compensation signal.

10. The system controller of claim 1, further comprising:
a current sensing component configured to receive the sensing signal and generate a first voltage signal based at least in part on the sensing signal; and
an error amplifier configured to receive the first voltage signal and a reference signal and generate an amplified signal based at least in part on the first voltage signal and the reference signal, the amplified signal being related to the first compensation signal.

11. The system controller of claim 10, further comprising: a first controller terminal coupled to a capacitor configured to generate the first compensation signal based at least in part on the amplified signal.

12. The system controller of claim 10, further comprising: a demagnetization component configured to receive a feedback signal associated with an auxiliary winding of the power conversion system and generate a demagnetization signal associated with a demagnetization process of the power conversion system based at least in part on the feedback signal.

13. The system controller of claim 12 wherein:
the demagnetization component is further configured to generate a trigger signal based at least in part on the feedback signal; and
the drive component is further configured to change the drive signal in response to the trigger signal to start a next switching cycle of the power conversion system.

14. The system controller of claim 12 wherein the error amplifier is further configured to:
in response to the demagnetization signal being at a first logic level, receive the first voltage signal and generate the amplified signal based at least in part on the first voltage signal; and
in response to the demagnetization signal being at a second logic level, receive a ground voltage and generate the amplified signal based at least in part on the ground voltage.

15. The system controller of claim 10 wherein:
the drive component includes:
a logic controller configured to receive the modulation signal and generate a control signal based at least in part on the modulation signal; and
a gate driver configured to receive the control signal and generate the drive signal based at least in part on the control signal; and

the current-sensing component is further configured to sample one or more peak magnitudes of the sensing signal in response to the control signal.

16. The system controller of claim 1, further comprising: a ramping-signal generator configured to receive a third compensation signal and generate the ramping signal based at least in part on the third compensation signal.

17. The system controller of claim 16, further comprising: a conversion component configured to receive the first compensation signal and generate the third compensation signal based at least in part on the first compensation signal.

18. The system controller of claim 17 wherein:
the first compensation signal includes a voltage signal; and
the third compensation signal includes a current signal.

19. The system controller of claim 17 wherein the conversion component includes:
an amplifier configured to receive the first compensation signal and generate an amplified signal based at least in part on the first compensation signal; and
a current-mirror circuit configured to generate the third compensation signal based at least in part on the amplified signal.

20. The system controller of claim 19 wherein:
the current-mirror circuit is further configured to generate a second current based at least in part on the amplified signal; and
the conversion component further includes: a resistor configured to generate the first voltage signal based at least in part on the second current.

21. The system controller of claim 16 wherein the ramping-signal generator includes:
a current-mirror circuit configured to generate a second current based at least in part on a reference current;
a first switch configured to be closed in response to the modulation signal being at a first logic level to charge a capacitor with the second current to generate the ramping signal;
an amplifier configured to receive a reference signal and output an amplified signal based at least in part on the reference signal; and
a second switch configured to be closed in response to the modulation signal being at a second logic level to generate the ramping signal based at least in part on the amplified signal.

22. The system controller of claim 1, further comprising: a current sensing component configured to receive a second current signal related to the input signal and generate the converted signal based at least in part on the second current signal.

23. The system controller of claim 22, further comprising:
a first controller terminal coupled to a resistor, the resistor being configured to generate the second current signal based at least in part on the input signal;
wherein the input signal is received by the primary winding.

24. The system controller of claim 22 wherein:
the current sensing component includes:
a current source component configured to provide a third current signal; and
a current-mirror circuit configured to receive a fourth current signal and generate the converted signal based at least in part on the fourth current signal; and

the second current signal is equal in magnitude to a sum of the third current signal and the fourth current signal.

25. The system controller of claim 1, further comprising:
a first controller terminal configured to receive a second current signal related to a feedback signal associated with an auxiliary winding of the power conversion system; and
a current sensing component coupled to the first controller terminal and configured to generate the converted signal based at least in part on the second current signal.

26. The system controller of claim 25 wherein:
the current sensing component includes:
a current source component configured to provide a third current signal; and
a current-mirror circuit configured to receive a fourth current signal and generate the converted signal based at least in part on the fourth current signal; and

the second current signal is equal in magnitude to a sum of the third current signal and the fourth current signal.

27. The system controller of claim 1 wherein the converted signal includes one or more current signals.

28. The system controller of claim 1 wherein the converted signal includes one or more voltage signals.

29. A method for regulating a power conversion system, the method comprising:
receiving a converted signal and a first compensation signal, the converted signal being associated with an input signal for a power conversion system, the first compensation signal being associated with a sensing signal related to a first current flowing through a primary winding of the power conversion system;
generating a second compensation signal based at least in part on the converted signal and the first compensation signal;
receiving the second compensation signal and a ramping signal;
generating a modulation signal based at least in part on the second compensation signal and the ramping signal;
receiving the modulation signal; and
outputting a drive signal based at least in part on the modulation signal to affect the first current, the drive signal being associated with an on-time period;
wherein the outputting a drive signal based at least in part on the modulation signal to affect the first current includes adjusting a duration of the on-time period based at least in part on the converted signal and the second compensation signal.