# Patent

## Title
Semipolar nitride semiconductor structure and method of manufacturing the same

## Abstract

Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Patent Application No. 10-2013-0133820, filed on Nov. 5, 2013, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND
The inventive concept relates to a nitride semiconductor, and more particularly, to a semipolar nitride semiconductor structure having a semipolar characteristic, and a method of manufacturing the semipolar nitride semiconductor structure.
It is absolutely necessary to lower a price of a light emitting diode (LED) for market entry of solid state lighting. For this, it is necessary to increase productivity by increasing the size of a substrate and to reduce cost by increasing chip efficiency.
Methods to reduce costs include reducing the price of a luminaire by suppressing efficiency droop to reduce the number of chips used for a bulb, and replacing a present phosphor conversion LED with color mixing to increase efficiency. As a method of replacing a present fluorescent light by reducing the price of solid state lighting, an LED is used that increases productivity and has high efficiency and low efficiency droop, having a large substrate of 8 inches or more.
There have been many arguments on reasons for efficiency droop. Known reasons are light leakage due to many dislocations within a quantum well and an overflow of electrons due to energy band bending through a piezoelectric field. As a method of suppressing efficiency droop caused by the above-described reasons, there a nonpolar GaN substrate has been implemented. When a nonpolar substrate is used, no polarization field is generated, and thus energy band bending is prevented. Thus, overflow may be reduced, and defects occurring due to the use of a GaN bulk substrate may be reduced by more than 100 times as compared with a hetero-epitaxy method of the related art.
However, a GaN bulk substrate has a diameter of 4 to 6 inches, and the price thereof is several thousands of dollars, and thus it is difficult to apply the GaN bulk substrate for commercial purposes. Furthermore, in practice, the price of a non-polar or semipolar GaN substrate is high.
SUMMARY
The inventive concept provides a semipolar nitride semiconductor structure that may be manufactured using a silicon substrate, and a method of manufacturing the semipolar nitride semiconductor structure.
According to an aspect of the inventive concept, there is provided a semipolar nitride semiconductor structure including a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer on the silicon substrate, wherein the nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
The Si(11k) surface of the silicon substrate may include an Si(111) facet being exposed by a larger amount than that of an Si(100) facet.
The nitride semiconductor layer may be a GaN thin film.
An angle θ between a c-axis of the GaN thin film and the Si(11k) surface of the silicon substrate may be within a range satisfying 35°≦θ≦45°.
The semipolar nitride semiconductor structure may further include a buffer layer interposed between the silicon substrate and the nitride semiconductor layer. The buffer layer may be formed of a material including any one selected from a group consisting of AlN, AlGaN, a step grade AlxInyGa1-x-yN (0≦x, y≦1, x+y≦1), and an Alx1Iny1Ga1-x1-y1N/Alx2Iny2Ga1-x2-y2N (0≦x1, x2, y1, y2≦1, x1≠x2 or y1≠y2, x1+y1≦1, x2+y2≦1) superlattice.
The semipolar nitride semiconductor structure may further include a nucleation-growth layer interposed between the silicon substrate and the buffer layer. The nucleation-growth layer may be formed of AlN.
According to another aspect of the inventive concept, there is provided a method of manufacturing a semipolar nitride structure, the method including: preparing a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and growing a nitride semiconductor layer on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
The method may further include performing anisotropic etching on the Si(11k) surface of the silicon substrate so that an Si(111) facet is exposed by a larger amount than that of an Si(100) facet. The anisotropic etching may be performed using any one etching solution selected from a group consisting of KOH, TMAH, EDP, N2H2, HaOH, and CsOH. The anisotropic etching may be maskless etching.
The nitride semiconductor layer may be a single crystalline GaN thin film. A c-axis of the GaN thin film may be within a range satisfying 35°≦θ≦45°.
The growing of the nitride semiconductor layer may include forming a buffer layer on the silicon substrate. The buffer layer may be formed of a material including any one selected from a group consisting of AlN, AlGaN, a step grade AlxInyGa1-x-yN (0≦x, y≦1, x+y≦1), and an Alx1Iny1Ga1-x1-y1N/Alx2Iny2Ga1-x2-y2N (0≦x1, x2, y1, y2≦1, x1≠x2 or y1≠y2, x1+y1≦1, x2+y2≦1) superlattice.
The growing of the nitride semiconductor layer may include forming a nucleation-growth layer on the silicon substrate.
The nucleation-growth layer may be formed of AlN.
The method may further include forming a nitride bulk layer using the nitride semiconductor layer as a seed layer.
The method may further include removing the silicon substrate. When the silicon substrate is removed, at least portions of the nucleation-growth layer and the buffer layer may be removed.
The semipolar nitride semiconductor structure according to the above-described embodiments may have a good semipolar characteristic in which a polarization field substantially has a value of approximately 0.
In the method of manufacturing the semipolar nitride semiconductor structure according to the above-described embodiments, anisotropic etching is performed on a silicon substrate with an Si(11k) surface having a high index by using an anisotropic etching solution so as to sufficiently expose a Si(111) facet. Thus, it is possible to form a single crystalline nitride semiconductor structure having a good semipolar characteristic on a silicon substrate across a large area.
The semipolar nitride semiconductor structure according to the above-described embodiments may be manufactured as a nitride bulk substrate by using a nitride semiconductor layer formed on a silicon substrate as a seed layer.



BRIEF DESCRIPTION OF THE DRAWINGS
Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a flowchart illustrating a method of manufacturing a semipolar nitride semiconductor structure according to an embodiment of the inventive concept;
FIGS. 2A to 2D are diagrams sequentially illustrating a semipolar nitride semiconductor structure that is manufactured according to an embodiment of the inventive concept;
FIGS. 3A to 3C are schematic diagrams illustrating a silicon substrate for manufacturing a semipolar nitride semiconductor structure on which anisotropic etching is performed, according to an embodiment of the inventive concept;
FIG. 4 is a graph illustrating a relation between a crystallization angle and a semipolar characteristic
FIGS. 5A and 5B are diagrams illustrating a method of manufacturing a nitride semiconductor structure according to another embodiment of the inventive concept; and
FIG. 6 is a diagram illustrating a semipolar nitride semiconductor bulk substrate that is manufactured according to another embodiment of the inventive concept.



DETAILED DESCRIPTION OF THE EMBODIMENTS
Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. The same reference numerals in the drawings denote the same element. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
FIG. 1 is a flowchart illustrating a method of manufacturing a semipolar nitride semiconductor structure according to an embodiment of the inventive concept. FIGS. 2A to 2D are diagrams sequentially illustrating a semipolar nitride semiconductor structure manufactured according to an embodiment of the inventive concept.
FIG. 2A and FIG. 3A to FIG. 6C show a process of preparing a silicon substrate 100 used to grow a nitride semiconductor.
Referring to FIG. 2A, the silicon substrate 100 having a high index crystal orientation for manufacturing a semipolar nitride semiconductor structure is prepared (operation S10). The term “silicon substrate 100 having a high index crystal orientation” used herein means an Si substrate having an Si(11k) surface with a high k value satisfying 7≦k≦13. For example, a large-scaled substrate having a diameter of 10 mm to 18 inches may be used as the silicon substrate 100, but the inventive concept is not limited thereto.
Next, anisotropic etching is performed on the Si(11k) surface of the silicon substrate 100 (operation S20). The Si(11k) surface of the silicon substrate 100 may allow an Si(111) facet to be exposed by a larger amount than an Si(100) facet through the anisotropic etching. The anisotropic etching may be wet etching. The anisotropic etching may be maskless etching.
FIG. 3A illustrates that anisotropic etching is performed on a silicon substrate having an Si(117) surface to expose the Si(111) facet. FIG. 3B illustrates that anisotropic etching is performed on a silicon substrate having an Si(119) surface to expose the Si(111) facet. FIG. 3C illustrates that anisotropic etching is performed on a silicon substrate having an Si(11 11) surface to expose the Si(111) facet. It is known that etching speed of the Si(111) facet is considerably lower than etching speed of the Si(001) facet in terms of crystallography of silicon. Table 1 below shows anisotropic etching of anisotropic etching solutions for silicon. Besides the anisotropic etching solutions shown in Table 1, a well-known silicon anisotropic etching solution such as N2H2, HaOH, or CsOH may be used.









TABLE







Etching
Ratio of Etching Rates
Etching Rate (Absolute Value)












Solution
100/(111)
(110)/(111)
100
Si3N4
SiO2















KOH (44%, 85° C.)
300
600
 1.4 μm/min
<1 Å/min
<14 Å/min 


TMAH (25%, 80° C.)
37
68
0.3-1 μm/min 
<1 Å/min
<2 Å/min


EDP (115° C.)
20
10
1.25 μm/min
<1 Å/min
<2 Å/min









When anisotropic etching is performed on the Si(11k) surface of the silicon substrate 100, the Si(001) facet is etched at a higher speed than that of the Si(111) facet, as illustrated in FIGS. 3A to 3C, and thus the Si(111) facet that is exposed by a terrace portion of the Si(11k) surface increases. Unlike a silicon substrate having a low index satisfying 2≦k≦6, in the case of a silicon substrate having a high index satisfying 7≦k≦13, when the Si(111) facet is exposed by a smaller amount than that of the Si(001) facet, a single crystalline GaN thin film is not easily grown. On the other hand, in the current embodiment, the Si(111) facet is exposed by a larger amount than that of the Si(100) facet through anisotropic etching, with respect to the silicon substrate 100 having a high index crystal orientation, thereby allowing a single crystalline GaN thin film 130 to be easily formed on the silicon substrate 100. In addition, the related art regarding the growth of a semipolar GaN uses a silicon substrate that is patterned using an ordinary method, and thus an etching process using a mask is necessary. On the other hand, the manufacturing method according to the current embodiment does not require an etching process using a mask.
Referring to FIG. 2B, a nucleation-growth layer 110 is formed on the silicon substrate 100 (operation S30). A nucleation-growth layer 120 may be formed of AlN. The nucleation-growth layer 110 may have a thickness of several tens to several hundreds of nanometers. The nucleation-growth layer 120 may be formed using any one of metal organic chemical vapor deposition (MOCVD), sputtering, and hydride vapor phase epitaxy (HYPE). In the step of growing the nucleation-growth layer 110, an Al source is injected to a deposition apparatus prior to an N source. This is for the purpose of preventing, in a case of using ammonia which is an N source, the silicon substrate 100 from being exposed first by ammonia and being nitrified. The nucleation-growth layer 110 is a layer for forming a nucleus of crystallization growth, and prevents a melt-back phenomenon occurring by reaction between the silicon substrate 100 and a buffer layer 120 that is subsequently formed. The melt-back phenomenon means a phenomenon in which Ga contained in the buffer layer 120 contacts and reacts with the silicon substrate 100. When the melt-back phenomenon occurs, crystallizability of a semiconductor device collapses. In addition, the nucleation-growth layer 110 may take a role in satisfactorily wetting the buffer layer 120 to be grown thereon.
Referring to FIG. 2C, the buffer layer 120 is formed on the nucleation-growth layer 110 (operation S40). The buffer layer 120 includes one layer or a plurality of layers, and may be formed of a material including any one selected from a group consisting of AlN, AlGaN, a step grade AlxInyGa1-x-yN (0≦x, y≦1, x+y≦1), and an Alx1Iny1Ga1-x1-y1N/Alx2Iny2Ga1-x2-y2N (0≦x1, x2, y1, y2≦1, x1≠x2 or y1≠y2, x1+y1≦1, x2+y2≦1) superlattice. The buffer layer 120 is a layer for growing the GaN thin film 130 having a high crystallizability and generating a crack by suppressing a difference in lattice and thermal expansion coefficient between the silicon substrate 100 and the GaN thin film 130. The buffer layer 120 may be formed using any one of MOCVD, sputtering, and HVPE.
Although FIG. 2C illustrates the buffer layer 120 that is configured as one layer, the number of buffer layers 120 may be plural. In addition, one buffer layer 120 or one of the plurality of buffer layers 120 may act as a nucleation-growth layer. The current embodiment describes an example in which the nucleation-growth layer 110 is AlN, but the nucleation-growth layer 110 may be formed of Alx3Iny3Ga1-x3-y3N (0≦x3, y3≦1, x3+y3≦1). The nucleation-growth layer 110 and the buffer layer 120 may be distinguished from each other by the respective composition materials.
FIG. 2D illustrates a nitride semiconductor structure in which the GaN thin film 130 is formed. Referring to FIG. 2D, the GaN thin film 130 is formed on the buffer layer 120 (operation S50). The GaN thin film 130 may be laminated to have a thickness of, for example, approximately 1 μm to 500 μm. The GaN thin film 130 may be formed using any one of MOCVD, sputtering, and HVPE.
FIG. 4 is a graph illustrating a relation between a crystallization angle and a semipolar characteristic, and shows changes in a polarization field according to a c-axis and the Si(111) facet (hereinafter, referred to as an angle of a c-axis). Referring to FIG. 4, when the angle of the c-axis is within a range satisfying 35°≦k≦50°, and preferably, when the angle is approximately 45°, a polarization field of GaN becomes approximately 0, and thus it is seen that GaN has a semipolar characteristic.
Meanwhile, Table 2 shows an angle between the Si(111) facet and GaN(0001) of the GaN thin film 130 according to changes in a k value in the Si(11k) surface of the silicon substrate 100. Referring to Table 2, it is seen that the angle of the GaN thin film 130 formed on the silicon substrate 100 having a high index satisfying 7≦k≦13 is within a range of approximately 43°≦k≦49°.












TABLE 2







Si(117)
Si(119)
Si(11 11)
Si(11 13)




















Angle Between Si(111) and
43.4°
45.8°
47.4°
48.55°


GaN(0001)









As described above, since the amount of Si(111) facet generated in the Si(11k) surface of the silicon substrate 100 is greater that of Si(100) facet through anisotropic etching (and since the Si(111) facet has a lower formation energy than that of the Si(001) facet), a deposition of the GaN thin film 130 (and also depositions of the nucleation-growth layer 110 and the buffer layer 120) on the Si(111) facet is superior to that on the Si(100) facet, the GaN thin film 130 may be grown so that GaN (0001)//Si(111). That is, the c-axis of the GaN thin film 130 grown on the Si(11k) surface having a high index of 7≦k≦13 has an angle illustrated in Table 2. Accordingly, the nitride semiconductor structure manufactured according to the current embodiment may have a semipolar characteristic in which a polarization field is approximately 0, as illustrated in FIG. 4. On the other hand, in a case of GaN (comparative example) which is grown on a silicon substrate having (112) to (116) facets, it is seen that the c-axis has an angle of equal to or less than 30 degrees, and thus a polarization field becomes relatively larger.
As described above, the nitride semiconductor structure manufactured according to the current embodiment has a semipolar characteristic, and thus the nitride semiconductor structure manufactured may be used as a semipolar nitride semiconductor substrate, for example, a GaN wafer. In addition, a light emitting device using the nitride semiconductor structure may reduce droop, may be manufactured to have a large size, and may improve its competitive price with respect to a present fluorescent light by reducing cost.
FIGS. 5A and 5B are diagrams illustrating a method of manufacturing a nitride semiconductor structure according to another embodiment of the inventive concept. In-situ etching may be performed on a silicon substrate 100 to obtain a GaN structure being relatively thin in a freestanding state from which the silicon substrate 100 is removed, as illustrated in FIG. 5A. Then, a nitride bulk layer 140 is further laminated on a GaN thin film 130 that is previously laminated, to obtain a nitride semiconductor structure 200 having a desired thickness. In this manner, the nitride semiconductor structure 200 that is obtained after further laminating the nitride bulk layer 140 may be used as a freestanding nitride semiconductor substrate. For example, a GaN layer obtained by further laminating GaN on the GaN thin film 130 that is previously laminated may be used as a freestanding GaN semiconductor substrate. At this time, the freestanding nitride semiconductor substrate may include a nucleation-growth layer 110 and a buffer layer 120 as illustrated in FIG. 5B, and may have a structure from which the nucleation-growth layer 110 and the buffer layer 120 are removed, when necessary. The nucleation-growth layer 110 and the buffer layer 120 may be removed after etching the silicon substrate 100 or may be removed after laminating the nitride bulk layer 140.
A process of etching the silicon substrate 100 may be performed after laminating the GaN thin film 130 to have a thickness of approximately 1 μm to 500 μm, for example, a thickness of several to several tens of μm. The silicon substrate 100 may be etched using an HCl gas within a reactor under a temperature of, for example, approximately 800° C. to 1100° C. At this time, a partial pressure of the HCl gas may be 1 to 100%. The etching of the silicon substrate 100 may be performed until an N-face of the GaN thin film 130 is exposed, thereby completely etching the silicon substrate 100.
The etching of the silicon substrate 100 may be performed in a state where the growth of the nitride semiconductor is stopped. The etching of the silicon substrate 100 may be performed at the same time when the growth of the nitride semiconductor is proceeding. That is, in a state where the GaN thin film 130 is first laminated to have an appropriate thickness, the laminating processing of the nitride semiconductor and the etching process of the silicon substrate 100 may be performed simultaneously. Simultaneous performance is possible because the etching of the silicon substrate 100 is performed in situ within the reactor.
Meanwhile, the nitride bulk layer 140 may further be grown on the GaN thin film 130, previously laminated, using an HVPE process to have a thickness of at least 10 μm, more specifically, a thickness of several hundreds of μm to several mm. For example, the silicon substrate 100 is completely etched, and GaN may be further grown to have a thickness of approximately 400 μm.
FIG. 6 is a diagram illustrating a semipolar nitride semiconductor bulk substrate manufactured according to another embodiment of the present invention. Referring to FIG. 6, the semipolar nitride semiconductor bulk substrate according to the current embodiment may be manufactured by further forming nitride bulk layers 210 and 220 by using the nitride semiconductor structure 200, manufactured as described above with reference to FIGS. 5A and 5B, as a seed layer. The nitride bulk layers 210 and 220 may be formed using an ammonothermal technique of regrowing the nitride semiconductor structure 200 as a seed layer within, for example, a container in a supercritical state.
While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

## Claims

1. A method of manufacturing a semipolar nitride structure, the method comprising:
preparing a silicon substrate having a Si(11k) surface satisfying 7≦k≦13;
performing anisotropic etching on the Si(11k) surface of the prepared silicon substrate so that, at least at a first region of the Si(11k) surface of the silicon substrate, a Si(111) facet is exposed by a larger amount than a Si(100) facet; and
growing a nitride semiconductor layer on the first region of the silicon substrate,
wherein the nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.

2. The method of claim 1, wherein the anisotropic etching is performed using any one etching solution selected from a group consisting of KOH, TMAH, EDP, N2H2, HaOH, and CsOH.

3. The method of claim 1, wherein the anisotropic etching is maskless etching.

4. The method of claim 1, wherein the nitride semiconductor layer is a single crystalline GaN thin film.

5. The method of claim 4, wherein a c-axis of the GaN thin film is within a range satisfying 35°≦θ≦45°.

6. The method of claim 1, wherein the growing of the nitride semiconductor layer comprises forming a buffer layer on the silicon substrate.

7. The method of claim 6, wherein the buffer layer is formed of a material comprising any one selected from a group consisting of AlN, AlGaN, a step grade AlxInyGa1-x-yN (0≦x, y≦1, x+y≦1), and an Alx1Iny1Ga1-x1-y1N/Alx2Iny2Ga1-x2-y2N (0≦x1, x2, y1, y2≦1, x1≠x2 or y1≠y2, x1+y1≦1, x2+y2≦1) superlattice.

8. The method of claim 6, wherein the growing of the nitride semiconductor layer comprises forming a nucleation-growth layer on the silicon substrate, wherein the nucleation-growth layer is formed of AlN.

9. The method of claim 1, further comprising forming a nitride bulk layer using the nitride semiconductor layer as a seed layer.

10. The method of claim 9, further comprising removing the silicon substrate.

11. A method of manufacturing a semipolar nitride structure, the method comprising:
performing anisotropic etching on a Si(11k) surface of a silicon substrate, where 7≦k≦13, so that, at least at a first region of the Si(11k) surface of the silicon substrate, a Si(111) facet is exposed by a larger amount than a Si(100) facet;
forming a nitride semiconductor layer on the buffer layer, wherein the nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0; and
removing the silicon substrate from the nitride semiconductor layer.

12. The method of claim 11, wherein the nitride semiconductor layer is GaN.