# Patent

## Title
Branch target address cache with hashed indices

## Abstract

In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.

## Background
This invention was made with United States Government support under Agreement No. HR0011-07-9-0002 awarded by DARPA. THE GOVERNMENT HAS CERTAIN RIGHTS IN THE INVENTION.


BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to branch prediction. Still more particularly, the present invention relates to a data processing system, processor and method of data processing with an improved branch target address cache (BTAC).
2. Description of the Related Art
A state-of-the-art microprocessor can comprise, for example, a cache for storing instructions and data, an instruction sequencing unit for fetching instructions from the cache, ordering the fetched instructions, and dispatching the fetched instructions for execution, one or more sequential instruction execution units for processing sequential instructions, and a branch processing unit (BPU) for processing branch instructions.
Branch instructions processed by the BPU can be classified as either conditional or unconditional branch instructions. Unconditional branch instructions are branch instructions that change the flow of program execution from a sequential execution path to a specified target execution path and which do not depend upon a condition supplied by the occurrence of an event. Thus, the branch specified by an unconditional branch instruction is always taken. In contrast, conditional branch instructions are branch instructions for which the indicated branch in program flow may be taken or not taken depending upon a condition within the processor, for example, the state of specified condition register bit(s) or the value of a counter.
Conditional branch instructions can be further classified as either resolved or unresolved based upon whether or not the condition upon which the branch depends is available when the conditional branch instruction is evaluated by the BPU. Because the condition upon which a resolved conditional branch instruction depends is known prior to execution, resolved conditional branch instructions can typically be executed and instructions within the target execution path fetched with little or no delay in the execution of sequential instructions. Unresolved conditional branches, on the other hand, can create significant performance penalties if fetching of sequential instructions is delayed until the condition upon which the branch depends becomes available and the branch is resolved.
Therefore, in order to minimize execution stalls, some processors speculatively predict the outcomes of unresolved branch instructions as taken or not taken. Utilizing the result of the prediction, the instruction sequencing unit is then able to fetch instructions within the speculative execution path prior to the resolution of the branch, thereby avoiding a stall in the execution pipeline in cases in which the branch is subsequently resolved as correctly predicted. Conventionally, prediction of unresolved conditional branch instructions has been accomplished utilizing static branch prediction, which predicts resolutions of branch instructions based upon criteria determined prior to program execution, or utilizing dynamic branch prediction, which predicts resolutions of branch instructions by reference to branch history accumulated on a per-address basis within a branch history table (BHT) and/or branch target address cache (BTAC).
Modern microprocessors require multiple cycles to fetch instructions from the instruction cache, scan the fetched instructions for branches, and predict the outcome of unresolved conditional branch instructions. If any branch is predicted as taken, instruction fetch is redirected to the new, predicted address. This process of changing which instructions are being fetched is called “instruction fetch redirect”. During the several cycles required for the instruction fetch, branch scan, and instruction fetch redirect, instructions continue to be fetched along the not taken path; in the case of a predicted-taken branch, the instructions within the predicted-taken path are discarded, resulting in decreased performance and wasted power dissipation.
Several existing approaches are utilized to reduce or to eliminate the instruction fetch redirect penalty. One commonly used method is the implementation of a BTAC that in each entry caches the branch target address of a taken branch in association with the branch instruction's tag. In operation, the BTAC is accessed in parallel with the instruction cache and is searched for an entry whose instruction tag matches the fetch address transmitted to the instruction cache. If such a BTAC entry exists, instruction fetch is redirected to the branch target address provided in the matching BTAC entry. Because the BTAC access typically takes fewer cycles than the instruction fetch, branch scan, and taken branch redirect sequence, a correct BTAC prediction can improve performance by causing instruction fetch to begin at a new address sooner than if there were no BTAC present.
However, in conventional designs, the BTAC access still generally requires multiple cycles, meaning that in the case of a BTAC hit at least one cycle elapses before the taken branch redirect. The interval between the BTAC access and the instruction fetch redirect represents a “bubble” during which no useful work is performed by the instruction fetch pipeline. Unfortunately, this interval tends to grow as processors achieve higher and higher operating frequencies and as BTAC sizes increase in response to the larger total number of instructions (i.e., “instruction footprint”) of newer software applications.
SUMMARY OF THE INVENTION
In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an exemplary embodiment of a data processing system in accordance with the present invention;
FIG. 2 is a more detailed block diagram of the branch logic within the data processing system of FIG. 1;
FIG. 3 is a high level logical flowchart of an exemplary method by which a Branch Target Address Cache (BTAC) generates instruction fetch addresses in accordance with the present invention; and
FIG. 4 is a high level logical flowchart of an exemplary method by which the branch target address predictions within the BTAC are updated by branch logic in accordance with the present invention.



DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT
With reference now to FIG. 1, there is illustrated a high level block diagram of an exemplary data processing system 8 in accordance with the present invention. As shown, data processing system 8 includes a processor 10 comprising a single integrated circuit superscalar processor, which, as discussed further below, includes various execution units, registers, buffers, memories, and other functional units that are all formed by integrated circuitry. Processor 10 may be coupled to other devices, such as a system memory 12 and a second processor 10, by an interconnect fabric 14 to form a data processing system 8 such as a workstation or server computer system. Processor 10 also includes an on-chip multi-level cache hierarchy including a unified level two (L2) cache 16 and bifurcated level one (L1) instruction (I) and data (D) caches 18 and 20, respectively. As is well known to those skilled in the art, caches 16, 18 and 20 provide low latency access to cache lines corresponding to memory locations in system memory 12.
Instructions are fetched and ordered for processing by instruction sequencing logic 13 within processor 10. In the depicted embodiment, instruction sequencing logic 13 includes an instruction fetch address register (IFAR) 30 that contains an effective address (EA) indicating a block of instructions (e.g., a 32-byte cache line) to be fetched from L1 I-cache 18 for processing. During each cycle, a new instruction fetch address (IFA) may be loaded into IFAR 30 from one of at least three sources: branch logic 36, which provides speculative branch target addresses resulting from the prediction of conditional branch instructions, global completion table (GCT) 38, which provides sequential path addresses, and branch execution unit (BEU) 92, which provides non-speculative addresses resulting from the resolution of predicted conditional branch instructions. The effective address loaded into IFAR 30 is selected from among the addresses provided by the multiple sources according to a prioritization scheme, which may take into account, for example, the relative priorities of the sources presenting addresses for selection in a given cycle and the age of any outstanding unresolved conditional branch instructions.
If hit/miss logic 22 determines, after translation of the EA contained in IFAR 30 by effective-to-real address translation (ERAT) 32 and lookup of the real address (RA) in I-cache directory 34, that the block of instructions corresponding to the EA in IFAR 30 does not reside in L1 I-cache 18, then hit/miss logic 22 provides the RA to L2 cache 16 as a request address via I-cache request bus 24. Such request addresses may also be generated by prefetch logic within L2 cache 16 or elsewhere within processor 10 based upon recent access patterns. In response to a request address, L2 cache 16 outputs a cache line of instructions, which are loaded into prefetch buffer (PB) 28 and L1 I-cache 18 via I-cache reload bus 26, possibly after passing through predecode logic (not illustrated).
Once the block of instructions specified by the EA in IFAR 30 resides in L1 cache 18, L1 I-cache 18 outputs the block of instructions to both branch logic 36 and to instruction fetch buffer (IFB) 40. As described further below with respect to FIG. 2, branch logic 36 scans the block of instructions for branch instructions and predicts the outcome of conditional branch instructions in the instruction block, if any. Following a branch prediction, branch logic 36 furnishes a speculative instruction fetch address to IFAR 30, as discussed above, and passes the prediction to branch instruction queue 64 so that the accuracy of the prediction can be determined when the conditional branch instruction is subsequently resolved by branch execution unit 92.
IFB 40 temporarily buffers the block of instructions received from L1 I-cache 18 until the block of instructions can be translated, if necessary, by an instruction translation unit (ITU) 42. In the illustrated embodiment of processor 10, ITU 42 translates instructions from user instruction set architecture (UISA) instructions (e.g., PowerPC® instructions) into a possibly different number of internal ISA (IISA) instructions that are directly executable by the execution units of processor 10. Such translation may be performed, for example, by reference to microcode stored in a read-only memory (ROM) template. In at least some embodiments, the UISA-to-IISA translation results in a different number of IISA instructions than UISA instructions and/or IISA instructions of different lengths than corresponding UISA instructions. The resultant IISA instructions are then assigned by global completion table 38 to an instruction group, the members of which are permitted to be executed out-of-order with respect to one another. Global completion table 38 tracks each instruction group for which execution has yet to be completed by at least one associated EA, which is preferably the EA of the oldest instruction in the instruction group.
Following UISA-to-IISA instruction translation, instructions are dispatched in-order to one of latches 44, 46, 48 and 50 according to instruction type. That is, branch instructions and other condition register (CR) modifying instructions are dispatched to latch 44, fixed-point and load-store instructions are dispatched to either of latches 46 and 48, and floating-point instructions are dispatched to latch 50. Each instruction requiring a rename register for temporarily storing execution results is then assigned one or more registers within a register file by the appropriate one of CR mapper 52, link and count (LC) register mapper 54, exception register (XER) mapper 56, general-purpose register (GPR) mapper 58, and floating-point register (FPR) mapper 60.
The dispatched instructions are then temporarily placed in an appropriate one of CR issue queue (CRIQ) 62, branch issue queue (BIQ) 64, fixed-point issue queues (FXIQs) 66 and 68, and floating-point issue queues (FPIQs) 70 and 72. From issue queues 62, 64, 66, 68, 70 and 72, instructions can be issued opportunistically (i.e., possibly out-of-order) to the execution units of processor 10 for execution. In some embodiments, the instructions are also maintained in issue queues 62-72 until execution of the instructions is complete and the result data, if any, are written back, in case any of the instructions needs to be reissued.
As illustrated, the execution units of processor 10 include a CR unit (CRU) 90 for executing CR-modifying instructions, a branch execution unit (BEU) 92 for executing branch instructions, two fixed-point units (FXUs) 94 and 100 for executing fixed-point instructions, two load-store units (LSUs) 96 and 98 for executing load and store instructions, and two floating-point units (FPUs) 102 and 104 for executing floating-point instructions. Each of execution units 90-104 is preferably implemented as an execution pipeline having a number of pipeline stages.
During execution within one of execution units 90-104, an instruction receives operands, if any, from one or more architected and/or rename registers within a register file coupled to the execution unit. When executing CR-modifying or CR-dependent instructions, CRU 90 and BEU 92 access the CR register file 80, which in a preferred embodiment contains a CR and a number of CR rename registers that each comprise a number of distinct fields formed of one or more bits. Among these fields are LT, GT, and EQ fields that respectively indicate if a value (typically the result or operand of an instruction) is less than zero, greater than zero, or equal to zero. Link and count register (LCR) register file 82 contains a count register (CTR), a link register (LR) and rename registers of each, by which BEU 92 may also resolve conditional branches to obtain a path address. General-purpose register files (GPRs) 84 and 86, which are synchronized, duplicate register files, store fixed-point and integer values accessed and produced by FXUs 94 and 100 and LSUs 96 and 98. Floating-point register file (FPR) 88, which like GPRs 84 and 86 may also be implemented as duplicate sets of synchronized registers, contains floating-point values that result from the execution of floating-point instructions by FPUs 102 and 104 and floating-point load instructions by LSUs 96 and 98.
After an execution unit finishes execution of an instruction, the execution notifies GCT 38, which schedules completion of instructions in program order. To complete an instruction executed by one of CRU 90, FXUs 94 and 100 or FPUs 102 and 104, GCT 38 signals the appropriate mapper, which sets an indication to indicate that the register file register(s) assigned to the instruction now contains the architected state of the register. The instruction is then removed from the issue queue, and once all instructions within its instruction group have completed, is removed from GCT 38. Other types of instructions, however, are completed differently.
When BEU 92 resolves a conditional branch instruction and determines the path address of the execution path that should be taken, the path address is compared against the speculative path address predicted by branch logic 36. If the path addresses match, branch logic 36 updates its prediction facilities, if necessary. If, however, the calculated path address does not match the predicted path address, BEU 92 supplies the correct path address to IFAR 30, and branch logic 36 updates its prediction facilities, as described further below. In either event, the branch instruction can then be removed from BIQ 64, and when all other instructions within the same instruction group have completed, from GCT 38.
Following execution of a load instruction (including a load-reserve instruction), the effective address computed by executing the load instruction is translated to a real address by a data ERAT (not illustrated) and then provided to L1 D-cache 20 as a request address. At this point, the load operation is removed from FXIQ 66 or 68 and placed in load data queue (LDQ) 114 until the indicated load is performed. If the request address misses in L1 D-cache 20, the request address is placed in load miss queue (LMQ) 116, from which the requested data is retrieved from L2 cache 16, and failing that, from another processor 10 or from system memory 12.
Store instructions (including store-conditional instructions) are similarly completed utilizing a store queue (STQ) 110 into which effective addresses for stores are loaded following execution of the store instructions. From STQ 110, data can be stored into either or both of L1 D-cache 20 and L2 cache 16, following effective-to-real translation of the target address.
Referring now to FIG. 2, there is depicted a more detailed block diagram of an exemplary embodiment of branch logic 36 of FIG. 1 in relation to other components of instruction sequencing logic 13. In the illustrated embodiment, branch logic 36 includes a historical instruction fetch address (IFA) buffer 160 that buffers one or more previous values of IFAR 30 (if available), an instruction decoder 128, branch direction prediction circuitry, such as branch history table (BHT) 130, and branch target address prediction circuitry, such as branch target address cache (BTAC) 132. In alternative embodiments of the present invention, the branch direction prediction circuitry can be implemented utilizing any other type of branch direction prediction circuitry, including without limitation, static branch prediction circuitry or two-level dynamic branch prediction circuitry. In addition, the branch target address prediction circuitry can also be implemented utilizing other known or future developed branch target address prediction circuitry, such as a branch target buffer (BTB). Further, in some embodiments, the physical structures utilized for branch direction prediction and branch target address prediction may be merged. The present invention is equally applicable to all such embodiments.
Instruction decoder 128 is coupled to receive each cache line of instructions as it is fetched from L1 I-cache 18 and placed in instruction fetch buffer 40. Instruction decoder 128 scans each cache line of instructions for branch instructions, and in response to detecting a branch instruction, forwards the branch instruction to the branch direction prediction circuitry (e.g., BHT 130) for direction prediction. As further indicated by the connection between BHT 130 and instruction fetch buffer 40, in the event BTAC 132 invokes fetching along a path that BHT 130 predicts as not-taken, BHT 130 cancels the instructions in the incorrect path from instruction fetch buffer 40 and redirects fetching along the correct path.
In accordance with at least some embodiments of the present invention, the branch target address prediction circuitry (hereinafter, referred to as BTAC 132) includes a BTAC array 140 that has an N-cycle access latency (e.g., two cycles) and that stores addresses of instruction blocks to be fetched N processor clock cycle later. For example, in embodiments in which N=2, BTAC array 140 stores address of instruction blocks to be fetched in the processor clock cycle following fetching of the next instruction block.
In the depicted embodiment, BTAC array 140 includes W ways (W≧1) each containing multiple (e.g., 4) entries 142. Each entry 142 includes a tag (T) field 144 utilized to match the entry 142 with the instruction fetch address (IFA) of an instruction block, a branch target address (BTA) field 146 for storing a BTA, and a state (S) field 148 indicating state information for the entry 142. In various embodiments, state field 148 may simply indicate validity of its entry 142 or may alternatively or additionally provide additional information, such as the type of entry and/or a score indicating a confidence in the correctness of the BTA. Particular entries 142 of BTAC array 140 are selected for read and write access with a BTAC index 158 computed by index logic 156 within BTAC 132.
In conventional BTACs, the BTAC index is formed from a small number of lower order bits of an instruction address. Using only a small number of lower order bits to index into a BTAC array can overload one or more entries, while under-utilizing one or more other entries. For example, consider a conventional processor that utilizes 64-bit addresses, fetches 32-byte instruction blocks, and employs a BTAC having four direct-mapped entries numbered entry 0 through entry 3. If the conventional processor processes an exemplary instruction fetch sequence containing the following instruction fetch addresses (expressed in hexadecimal):

    
    
        0x100, 0x120, 0x20, 0x264, 0x310, . . .

and lower order bits 60-61 of the instruction address are utilized as the index bits, then the BTAC will map all of instruction addresses 0x100, 0x120, 0x220 and 0x310 to entry 0 (corresponding to index 0b00, as expressed in binary) and will map instruction address 0x264 to entry 1 (corresponding to index 0b01). Entries 2 and 3 (corresponding to indices 0b10 and 0b11) will be unused. As will be appreciated, the failure of the conventional BTAC to distribute instruction addresses across all entries will lead to a higher percentage of BTAC misses than if a more balanced distribution were achieved.

    
    


In accordance with the present invention, the distribution of instruction addresses over the entries of BTAC array 140 is enhanced by forming BTAC index 158 utilizing both higher order bits and lower order bits of the instruction fetch addresses of instruction blocks. In one preferred embodiment, in which instruction fetch blocks are B bytes in length and BTAC array 140 includes N entries 142 and is W-way set associative, the following set of formulas can be utilized to described the generation of a BTAC index 158 for accessing BTAC array 140 from the IFA “iaddr”:

block_bits=log2(B)

index_bits=log2(N/W)

plain_index=(iaddr>>2) AND ((1<<index_bits)−1)

high_order bits=(iaddr>>(2+index_bits)) AND ((1<<(block_bits−2))−1)

BTAC index=plain_index XOR high_order_bits

Thus, in this exemplary embodiment, BTAC index 158 is formed by a logical combination of both higher order and lower order bits of the instruction fetch address.

Returning the exemplary instruction address sequence set forth above, application of the above formulas would yield a BTAC index 158 given by:

BTAC index=((iaddr>>2) AND 0x3) XOR ((iaddr>>4) AND 0x3)

If BTAC array 140 contains 4-entry direct mapped entries 142 as posited above, index logic 156 will map instruction address 0x100 to entry 0 (corresponding to BTAC index 0b00), instruction address 0x310 to entry 1 (corresponding to BTAC index 0b01), instruction addresses 0x120 and 0x220 to entry 2 (corresponding to BTAC index 0b10, and instruction address 0x264 to entry 3 (corresponding to BTAC index 0b11). As can be seen, this distribution of instruction addresses is much more balanced than that achieved by through the conventional use of only lower order bits to form the BTAC index.

With reference now to FIG. 3, there is illustrated a high level logical flowchart of an exemplary method by which BTAC 132 provides speculative branch target address predictions in accordance with the present invention. As a logical flowchart, it will be appreciated that in at least some embodiments of the process depicted in FIG. 3 at least some of the illustrated steps can be performed concurrently and/or in a different order than that shown.
The process of FIG. 3 begins at block 300 and then proceeds to block 302, which illustrates BTAC 132 receiving the instruction fetch address (IFA) in IFAR 30 concurrently with the transmission of the IFA to L1 I-cache 18 to initiate a fetch of an instruction block. In response to receipt of the IFA, index logic 156 of BTAC 132 computes BTAC index 158 from higher order and lower order bits from the IFA received from IFAR 30, for example, utilizing logic implementing the formulas set forth above (block 304). As depicted at block 306, BTAC index 158 selects a particular entry 142 in each of the W ways of BTAC array 140. BTAC array 140 then determines at block 306 whether or not the tag 162 of the IFA hits in any of the one or more entries 142 selected by BTAC index 158, that is, whether the tag 162 matches the contents of any of tag fields 144 of the one or more selected entries 142 (block 308).
If tag 162 of the IFA does not match the contents of the tag field 144 of any selected entry 142 of BTAC array 140, BTAC array 140 deasserts its hit signal 152, and the process terminates at block 312. If, on the other hand, tag 162 matches the contents of a tag field 144 of a selected entry 142 of BTAC array 140, BTAC array 140 asserts hit signal 152 and outputs the BTA associated with the matching tag field 144. The BTA is qualified at a first buffer 154 by the state information within the state field 148 of the matching entry 142, and if successfully qualified, is presented to IFAR 30 for selection as the IFA, as shown at block 310. Following block 310, the process illustrated in FIG. 3 terminates at block 312 until a next IFA is received by BTAC 132.
Referring now to FIG. 4, there is illustrated a high level logical flowchart that depicts an exemplary method by which the branch target address predictions within BTAC 132 are updated in accordance with the present invention. The process begins at block 400 of FIG. 4 and then passes to block 402, which depicts branch logic 36 determining whether or not a block of instructions (e.g., a 32-byte cache line) fetched from L1 I-cache 18 includes a branch instruction. If not, no update to BTAC 132 is made. The process shown in FIG. 4 therefore passes from block 402 to block 440, which depicts branch logic 36 saving the IFA of the instruction fetch block within historical IFA buffer 160 at block 440. The process thereafter terminates at block 441 until a subsequent instruction block is fetched.
Returning to block 402, if branch logic 36 determines at block 402 that the fetched instruction block includes a branch instruction, the process proceeds to block 410. Block 410 depicts branch logic 36 determining whether the fetched instruction block contains an unconditional taken branch or a conditional branch predicted as “taken” by BHT 130. If so, the process proceeds from block 410 to block 420, which is described below. If not, the process passes to block 412, which depicts BHT 130 determining from hit signal 152 whether the tag 162 of the IFA hit in BTAC array 140. If not, no update to BTAC 132 is made, and the process passes from block 412 to blocks 440-441, which have been described. If, however, a determination is made at block 412 that tag 162 hit in BTAC array 140, meaning that BTAC 132 has at least one entry 142 predicting a redirect target address for a fetched instruction block containing no branch that would cause a fetch redirect, BHT 130 invalidates the entry 142 in BTAC array 140 matching tag 162 (block 414). Such invalidation may be performed, for example, by updating the state field of the relevant entry 142. Thereafter, the process passes to blocks 440-441, which have been described.
Referring now to block 420, if branch logic 36 determines that a branch instruction within the fetched instruction block was either unconditionally “taken” or predicted as “taken” and tag 162 hit in BTAC array 140, the process proceeds to block 430, which is described below. If, however, branch logic 36 determines at block 420 that a branch instruction within the fetched instruction block was “taken” and the combination of tag 162 missed in BTAC array 140, the process proceeds to block 422. Block 422 illustrates branch logic 36 determining whether historical IFA buffer 160 buffers the previous IFA immediately preceding the IFA that generated the fetch of the instruction block containing the taken branch instruction in question. IFA buffer 160 may not buffer the IFA for a number of reasons, for example, a reboot of the machine, a context switch, or a pipeline flush.
If branch logic 36 determines at block 422 that the previous IFA is not available, no entry 142 is inserted in BTAC array 140, and the process proceeds to blocks 440-441, which have been described. If, on the other hand, branch logic 36 determines at block 422 that historical IFA buffer 160 retains the previous IFA immediately preceding the current IFA that generated the fetch of the instruction block containing the conditional branch instruction in question, branch logic 36 inserts within BTAC array 140 a new branch target address prediction associating the tag portion of the previous IFA in tag field 144 with the branch target address predicted by BHT 130 in BTA field 146. As noted above, the newly allocated branch target address prediction is placed within BTAC array 140 in an entry 142 identified by a BTAC index 158 generated by index logic 156 from higher order and lower order bits of the previous IFA. If multiple ways are implemented in BTAC array 140, the particular entry 142 to be allocated to the new branch target address prediction can be further selected, for example, according to a round robin or least recently used algorithm, as is known in the art. Following block 426, the process passes to blocks 440-441, which have been described.
With reference now to block 430, if branch logic 36 determines that the fetched instruction block contains a taken branch and the tag 162 hit in BTAC 132, branch logic 36 further determines whether the BTA prediction is confirmed as correct by BHT 130. If so, no update to BTAC 132 is required, and the process proceeds to blocks 440-441, which have been described. If, however, BHT 130 indicates at block 430 that the BTA predicted by BTAC array 140 was incorrect, branch logic 36 updates the BTA field 146 of the entry 142 that provided the incorrect BTA prediction with the correct BTA. Thereafter, the process proceeds to blocks 440-441, which have been described.
As has been described, the present invention provides a data processing system, processor and method of data processing in which an improved branch target address cache (BTAC) is utilized to generate branch target address predictions. According to at least some embodiments, the BTAC includes index logic that computes an index for accessing the BTAC from higher order and lower order bits of the instruction fetch address.
While the invention has been particularly shown as described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

## Claims

1. A processor, comprising:
at least one execution unit that executes instructions; and
instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions, wherein the BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon a combination of at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address, wherein the set of higher order bits and the set of lower order bits are discontiguous.

2. The processor of claim 1, wherein the BTAC is a set-associative cache including multiple ways, wherein each of the multiple ways contains multiple of the plurality of entries.

3. The processor of claim 1, wherein each of said plurality of entries includes a respective tag field for holding a tag portion of an instruction address.

4. The processor of claim 3, wherein:
the BTAC outputs a branch target address of a branch target address prediction in response to a match between contents of the tag field of the entry selected by the selection logic.

5. The processor of claim 1, wherein the instruction address comprises at least two bytes including a most significant byte and a least significant byte, and wherein the most significant byte contains the higher order bits and the least significant byte contains the lower order bits.

6. The processor of claim 1, wherein the index logic computes the BTAC index by an exclusive-OR of the higher order bits and the lower order bits.

7. The processor of claim 1, wherein:
a number of the higher order bits depends upon a size of an instruction fetch block addressed by the instruction address; and
a number of lower order bits depends upon a number of the plurality of entries.

8. The processor of claim 1, wherein:
the memory system includes a cache memory within the processor; and
the instruction sequencing logic accesses the BTAC and the cache memory concurrently with the instruction address.

9. A data processing system, comprising:
at least one processor in accordance with claim 1;
an interconnect coupled to the processor; and
the memory system coupled to the processor via the interconnect and operable to communicate data with the at least one processor.

10. A method of data processing in a processor including at least one execution unit and an instruction sequencing logic containing a branch target address cache (BTAC) having a plurality of entries for storing branch target address predictions, said method comprising:
receiving at least a portion of an instruction address identifying an instruction block to be fetched from a memory system for execution by at least one execution unit of the processor;
in response to receiving at least the portion of the instruction address, index logic within the BTAC selecting an entry to access utilizing a BTAC index based upon a combination of at least a set of higher order bits of the instruction address and a set of lower order bits of the instruction address, wherein the set of higher order bits and the set of lower order bits are discontiguous;
comparing a tag portion of the instruction address with contents of a tag field of the selected entry; and
in response to the tag portion of the instruction address matching contents of the tag field, the BTAC outputting a branch target address indicated by the selected entry to redirect instruction fetching.

11. The method of claim 10, wherein:
the BTAC is a set-associative cache including multiple ways, wherein each of the multiple ways contains multiple of the plurality of entries; and
wherein the selecting includes selecting an entry in each of the multiple ways.

12. The method of claim 10, wherein:
the instruction address comprises at least two bytes including a most significant byte and a least significant byte; and
the most significant byte contains the higher order bits and the least significant byte contains the lower order bits.

13. The method of claim 10, wherein the selecting includes the index logic computing the BTAC index by an exclusive-OR of the higher order bits and the lower order bits.

14. The method of claim 10, wherein:
a number of the higher order bits depends upon a size of an instruction fetch block addressed by the instruction address; and
a number of lower order bits depends upon a number of the plurality of entries.

15. The method of claim 10, wherein:
the memory system includes a cache memory within the processor; and
the receiving comprises receiving the at a portion of the instruction address concurrently with receipt of the instruction address by the cache memory.