# Patent

## Title
Print engine pipeline subsystem of a printer controller

## Abstract

Provided is a print engine pipeline subsystem of a printer controller. The subsystem includes a print engine pipeline controller for reading and writing print engine pipeline registers, and a contone decoder unit for expanding JPEG compressed continuous tone (“contone”) layers. Also included are a lossless bi-level decoder for expanding compressed bi-level layers, a line loader unit for expanding page images for a printhead, and a printhead interface for sending dot data to the printhead and for providing line synchronization between multiple printer controllers.

## Background
CROSS REFERENCE RELATED TO APPLICATION
This application is a continuation of U.S. application Ser. No. 11/706,295 filed on Feb. 15, 2007, which is a continuation of U.S. application Ser. No. 10/854,510 filed on May 27, 2004, now issued U.S. Pat. No. 7,188,928, all of which are herein incorporated by reference.


FIELD OF THE INVENTION
The present invention relates to a printer comprising one or more printhead modules and a printer controller for supplying the printhead modules with data to be printed.
CO-PENDING APPLICATIONS
Various methods, systems and apparatus relating to the present invention are disclosed in the following co-pending applications filed by the applicant or assignee of the present invention simultaneously with the present application:

















7,374,266
10/854,522
10/854,488
7,281,330
10/854,503
7,328,956


10/854,509
7,093,989
7,377,609
10/854,495
10/854,498
10/854,511


7,390,071
10/854,525
10/854,526
10/854,516
10/854,508
7,252,353


10/854,515
7,267,417
10/854,505
10/854,493
7,275,805
7,314,261


10/854,490
7,281,777
7,290,852
10/854,528
10/854,523
10/854,527


10/854,524
10/854,520
10/854,514
10/854,519
10/854,513
10/854,499


10/854,501
7,266,661
7,243,193
10/854,518
10/854,517









The disclosures of these co-pending applications are incorporated herein by cross-reference.

CROSS-REFERENCES
Various methods, systems and apparatus relating to the present invention are disclosed in the following co-pending applications filed by the applicant or assignee of the present invention. The disclosures of all of these co-pending applications are incorporated herein by cross-reference.

















7,249,108
6,566,858
6,331,946
6,246,970
6,442,525
7,346,586


09/505,951
6,374,354
7,246,098
6,816,968
6,757,832
6,334,190


6,745,331
7,249,109
10/636,263
10/636,283
10/407,212
7,252,366


10/683,064
7,360,865
10/727,181
10/727,162
7,377,608
7,399,043


7,121,639
7,165,824
7,152,942
10/727,157
7,181,572
7,096,137


7,302,592
7,278,034
7,188,282
10/727,159
10/727,180
10/727,179


10/727,192
10/727,274
10/727,164
10/727,161
10/727,198
10/727,158


10/754,536
10/754,938
10/727,160
6,795,215
6,859,289
6,977,751


6,398,332
6,394,573
6,622,923
6,747,760
6,921,144
10/780,624


7,194,629
10/791,792
7,182,267
7,025,279
6,857,571
6,817,539


6,830,198
6,992,791
7,038,809
6,980,323
7,148,992
7,139,091


6,947,173









BACKGROUND OF THE INVENTION
Printer controllers face difficulties when they have to send print data to two or more printhead modules in a printhead, each of the modules having one or more rows of print nozzles for outputting ink. In one embodiment favored by the applicant, data for each row is shifted into a shift register associated with that row.
The applicant has discovered that some manufacturing advantages arise when printhead modules of different lengths are used within a product range. For example, a particular width of printhead for a pagewidth printer can be achieved with various different combinations of printhead module. So, a 10 inch printhead can be formed from two 5 inch printhead modules, a 6 and a 4 inch module, or a 7 and a 3 inch module.
Whilst useful in some ways, printhead modules of different lengths raise some other issues. One of these is that when one of the modules is longer, it must be loaded with more data than the other module in a given load period.
One way of dealing with the problem is to use a printer controller with sufficient processing power and data delivery capabilities that the data imbalance is not problematic. Alternatively, in some cases it may be feasible to add one or more additional printer controllers to help deal with the high data rates involved. However, if the data rates for the printer controller providing data to the longer printhead module are already relatively close to that printer controller's capabilities, it may be not be commercially feasible for either of these solutions to be implemented.
It would be useful to provide a printhead module that addresses at least some of the disadvantages of known printhead modules.
SUMMARY OF THE INVENTION
In a first aspect the present invention provides a printer comprising:
a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, the first and second printhead modules having different lengths; and
first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, the first printer controller being arranged to output dot data to both the first and second printhead modules and the second printer controller being arranged to output dot data only to the second printhead module,
wherein one or more of the printhead modules has at least one row of print nozzles and at least two shift registers for shifting in the dot data to at least one row, each print nozzle obtaining the dot data from an element of one of the shift registers.
The printhead modules may be configured such that no dot data passes between them.
The printer may further comprise at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot data by the printer controllers.
Each of the printer controllers may be configurable to supply the dot data to printhead modules of a plurality of different lengths.
The printhead may be a pagewidth printhead.
The first and second printer controllers may be configured to send to the printhead dot data to be printed with at least two different inks and control data for controlling printing of the dot data, and the first and second printer controllers may have at least one communication output which is configured to output at least some of the control data and at least some of the dot data for the at least two inks.
The first and second printhead modules may be configured to receive the dot data to be printed using at least two different inks and control data for controlling printing of the dot data, and the first and second printhead modules may have a communication input for receiving the dot data for the at least two colors and the control data.
The first and second printer controllers may be configured to receive first data and manipulate the first data to produce the dot data, and the first and second printer controllers may have at least two serial outputs for supplying the dot data to the printhead.
Each shift register may feed dot data to a group of the nozzles, each group of the nozzles being interleaved with at least one of the other groups of the nozzles.
The printhead may be capable of printing a maximum of n channels of print data and is configurable into:
a first mode, in which the printhead is configured to receive print data for a first number of the channels; and
a second mode, in which the printhead is configured to receive print data for a second number of the channels, the first number being greater than the second number.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1. Single SoPEC A4 Simplex system
FIG. 2. Dual SoPEC A4 Simplex system
FIG. 3. Dual SoPEC A4 Duplex system
FIG. 4. Dual SoPEC A3 simplex system
FIG. 5. Quad SoPEC A3 duplex system
FIG. 6. SoPEC A4 Simplex system with extra SoPEC used as DRAM storage
FIG. 7. SoPEC A4 Simplex system with network connection to Host PC
FIG. 8. Document data flow
FIG. 9. Pages containing different numbers of bands
FIG. 10. Contents of a page band
FIG. 11. Page data path from host to SoPEC
FIG. 12. Page structure
FIG. 13. SoPEC System Top Level partition
FIG. 14. Proposed SoPEC CPU memory map (not to scale)
FIG. 15. Possible USB Topologies for Multi-SoPEC systems
FIG. 16. Printhead Nozzle Layout for conceptual 36 Nozzle AB single segment printhead
FIG. 17. Paper and printhead nozzles relationship (example with D1=D2=5)
FIG. 18. Dot line store logical representation
FIG. 19. Conceptual view of 2 adjacent printhead segments possible row alignment
FIG. 20. Conceptual view of 2 adjacent printhead segments row alignment (as seen by the LLU)
FIG. 21. Even dot order in DRAM (13312 dot wide line)
FIG. 22. Dotline FIFO data structure in DRAM (LLU specification)
FIG. 23. DWU partition
FIG. 24. Sample dot data generation for color 0 even dot
FIG. 25. Buffer address generator sub-block
FIG. 26. DIU Interface sub-block
FIG. 27. Interface controller state diagram
FIG. 28. High level data flow diagram of LLU in context
FIG. 29. Paper and printhead nozzles relationship (example with D1=D2=5)
FIG. 30. Conceptual view of vertically misaligned printhead segment rows (external)
FIG. 31. Conceptual view of vertically misaligned printhead segment rows (internal)
FIG. 32. Conceptual view of color dependent vertically misaligned printhead segment rows (internal)
FIG. 33. Conceptual horizontal misalignment between segments
FIG. 34. Relative positions of dot fired (example cases)
FIG. 35. Example left and right margins
FIG. 36. Dot data generated and transmitted order
FIG. 37. Dotline FIFO data structure in DRAM (LLU specification)
FIG. 38. LLU partition
FIG. 39. DIU interface
FIG. 40. Interface controller state diagram
FIG. 41. Address generator logic
FIG. 42. Write pointer state machine
FIG. 43. PHI to linking printhead connection (Single SoPEC)
FIG. 44. PHI to linking printhead connection (2 SoPECs)
FIG. 45. CPU command word format
FIG. 46. Example data and command sequence on a print head channel
FIG. 47. PHI block partition
FIG. 48. Data generator state diagram
FIG. 49. PHI mode Controller
FIG. 50. Encoder RTL diagram
FIG. 51. 28-bit scrambler
FIG. 52. Printing with 1 SoPEC
FIG. 53. Printing with 2 SoPECs (existing hardware)
FIG. 54. Each SoPEC generates dot data and writes directly to a single printhead
FIG. 55. Each SoPEC generates dot data and writes directly to a single printhead
FIG. 56. Two SoPECs generate dots and transmit directly to the larger printhead
FIG. 57. Serial Load
FIG. 58. Parallel Load
FIG. 59. Two SoPECs generate dot data but only one transmits directly to the larger printhead
FIG. 60. Odd and Even nozzles on same shift register
FIG. 61. Odd and Even nozzles on different shift registers
FIG. 62. Interwoven shift registers
FIG. 63. Linking Printhead Concept
FIG. 64. Linking Printhead 30 ppm
FIG. 65. Linking Printhead 60 ppm
FIG. 66. Theoretical 2 tiles assembled as A-chip/A-chip—right angle join
FIG. 67. Two tiles assembled as A-chip/A-chip
FIG. 68. Magnification of color n in A-chip/A-chip
FIG. 69. A-chip/A-chip growing offset
FIG. 70. A-chip/A-chip aligned nozzles, sloped chip placement
FIG. 71. Placing multiple segments together
FIG. 72. Detail of a single segment in a multi-segment configuration
FIG. 73. Magnification of inter-slope compensation
FIG. 74. A-chip/B-chip
FIG. 75. A-chip/B-chip multi-segment printhead
FIG. 76. Two A-B-chips linked together
FIG. 77. Two A-B-chips with on-chip compensation
FIG. 78. Print construction and Nozzle position
FIG. 79. Conceptual horizontal misplacement between segments
FIG. 80. Printhead row positioning and default row firing order
FIG. 81. Firing order of fractionally misaligned segment
FIG. 82. Example of yaw in printhead IC misplacement
FIG. 83. Vertical nozzle spacing
FIG. 84. Single printhead chip plus connection to second chip
FIG. 85. Two printheads connected to form a larger printhead
FIG. 86. Colour arrangement.
FIG. 87. Nozzle Offset at Linking Ends
FIG. 88. Bonding Diagram
FIG. 89. MEMS Representation.
FIG. 90. Line Data Load and Firing, properly placed Printhead,
FIG. 91. Simple Fire order
FIG. 92. Micro positioning
FIG. 93. Measurement convention
FIG. 94. Scrambler implementation
FIG. 95. Block Diagram
FIG. 96. Netlist hierarchy
FIG. 97. Unit cell schematic
FIG. 98. Unit cell arrangement into chunks
FIG. 99. Unit Cell Signals
FIG. 100. Core data shift registers
FIG. 101. Core Profile logical connection
FIG. 102. Column SR Placement



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Various aspects of the preferred and other embodiments will now be described. Much of this description is based on technical design documents, so the use of words like “must”, “should” and “will”, and all others that suggest limitations or positive attributes of the performance of a particular product, should not be interpreted as applying to the invention in general. These comments, unless clearly referring to the invention in general, should be considered as desirable or intended features in a particular design rather than a requirement of the invention. The intended scope of the invention is defined in the claims.
This document describes the SoPEC ASIC (Small office home office Print Engine Controller) suitable for use in price sensitive SoHo printer products. The SoPEC ASIC is intended to be a relatively low cost solution for linking printhead control, replacing the multichip solutions in larger more professional systems with a single chip. The increased cost competitiveness is achieved by integrating several systems such as a modified PEC1 printing pipeline, CPU control system, peripherals and memory sub-system onto one SoC ASIC, reducing component count and simplifying board design. SoPEC contains features making it suitable for multifunction or “all-in-one” devices as well as dedicated printing systems.
The following terms are used throughout this specification:













CPU
Refers to CPU core, caching system and MMU.


Host
A PC providing control and print data to a 



Memjet printer.


ISCMaster
In a multi-SoPEC system, the ISCMaster 



(Inter SoPEC Communication Master) is the SoPEC



device that initiates communication with other SoPECs



in the system. The ISCMaster interfaces with the host.


ISCSlave
In a multi-SoPEC system, an ISCSlave is a SoPEC 



device that responds to communication initiated by



the ISCMaster.


LEON
Refers to the LEON CPU core.


LineSyncMaster
The LineSyncMaster device generates the line 



synchronisation pulse that all SoPECs in the system



must synchronise their line outputs to.


Linking Printhead
Refers to a page-width printhead constructed from 



multiple linking printhead ICs


Linking Printhead IC
A MEMS IC. Multiple ICs link together to form 



a complete printhead. An A4/Letter page width



printhead requires 11 printhead ICs.


Multi-SoPEC
Refers to SoPEC based print system with 



multiple SoPEC devices


Netpage
Refers to page printed with tags (normally in



infrared ink).


PEC1
Refers to Print Engine Controller version 1, 



precursor to SoPEC used to control printheads 



constructed from multiple angled printhead segments.


PrintMaster
The PrintMaster device is responsible for coordinating 



all aspects of the print operation. There may only be one



PrintMaster in a system.


QA Chip
Quality Assurance Chip


Storage SoPEC
A SoPEC used as a DRAM store and which does not 



print.


Tag
Refers to pattern which encodes information about 



its position and orientation which allow it to be



optically located and its data contents read.









The following acronyms and abbreviations are used in this specification CFU Contone FIFO53 Unit; CPU Central Processing Unit; DIU DRAM Interface Unit; DNC Dead Nozzle Compensator; DRAM Dynamic Random Access Memory; DWU DotLine Writer Unit; GPIO General Purpose Input Output; HCU Halftoner Compositor Unit; ICU Interrupt Controller Unit; LDB Lossless Bi-level Decoder; LLU Line Loader Unit; LSS Low Speed Serial interface; MEMS Micro Electro Mechanical System; MMI Multiple Media Interface; MMU Memory Management Unit; PCU SoPEC Controller Unit; PHI PrintHead Interface; PHY USB multi-port Physical Interface; PSS Power Save Storage Unit; RDU Real-time Debug Unit; ROM Read Only Memory; SFU Spot FIFO Unit; SMG4 Silverbrook Modified Group 4; SoPEC Small office home office Print Engine Controller; SRAM Static Random Access Memory; TE Tag Encoder; TFU Tag FIFO Unit; TIM Timers Unit; UDU USB Device Unit; UHU USB Host Unit; USB Universal Serial Bus
The preferred embodiment linking printhead produces 1600 dpi bi-level dots. On low-diffusion paper, each ejected drop forms a 22.5 □m diameter dot. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest. Since the preferred form of the linking printhead is pagewidth and operates with a constant paper velocity, color planes are printed in good registration, allowing dot-on-dot printing. Dot-on-dot printing minimizes ‘muddying’ of midtones caused by inter-color bleed.
A page layout may contain a mixture of images, graphics and text. Continuous-tone (contone) images and graphics are reproduced using a stochastic dispersed-dot dither. Unlike a clustered-dot (or amplitude-modulated) dither, a dispersed-dot (or frequency-modulated) dither reproduces high spatial frequencies (i.e. image detail) almost to the limits of the dot resolution, while simultaneously reproducing lower spatial frequencies to their full color depth, when spatially integrated by the eye. A stochastic dither matrix is carefully designed to be free of objectionable low-frequency patterns when tiled across the image. As such its size typically exceeds the minimum size required to support a particular number of intensity levels (e.g. 16□168 bits for 257 intensity levels).
Human contrast sensitivity peaks at a spatial frequency of about 3 cycles per degree of visual field and then falls off logarithmically, decreasing by a factor of 100 beyond about 40 cycles per degree and becoming immeasurable beyond 60 cycles per degree. At a normal viewing distance of 12 inches (about 300 mm), this translates roughly to 200-300 cycles per inch (cpi) on the printed page, or 400-600 samples per inch according to Nyquist's theorem.
In practice, contone resolution above about 300 ppi is of limited utility outside special applications such as medical imaging. Offset printing of magazines, for example, uses contone resolutions in the range 150 to 300 ppi. Higher resolutions contribute slightly to color error through the dither.
Black text and graphics are reproduced directly using bi-level black dots, and are therefore not anti-aliased (i.e. low-pass filtered) before being printed. Text should therefore be supersampled beyond the perceptual limits discussed above, to produce smoother edges when spatially integrated by the eye. Text resolution up to about 1200 dpi continues to contribute to perceived text sharpness (assuming low-diffusion paper).
A Netpage printer, for example, may use a contone resolution of 267 ppi (i.e. 1600 dp 6), and a black text and graphics resolution of 800 dpi. A high end office or departmental printer may use a contone resolution of 320 ppi (1600 dpi/5) and a black text and graphics resolution of 1600 dpi. Both formats are capable of exceeding the quality of commercial (offset) printing and photographic reproduction.
The SoPEC device can be used in several printer configurations and architectures. In the general sense, every preferred embodiment SoPEC-based printer architecture will contain:

    
    
        One or more SoPEC devices.
        One or more linking printheads.
        Two or more LSS busses.
        Two or more QA chips.
        Connection to host, directly via USB2.0 or indirectly.
        Connections between SoPECs (when multiple SoPECs are used).
    
    


The SoPEC device contains several system on a chip (SoC) components, as well as the print engine pipeline control application specific logic.
The PEP reads compressed page store data from the embedded memory, optionally decompresses the data and formats it for sending to the printhead. The print engine pipeline functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, rendering of Netpage tags, compensation for dead nozzles in the printhead, and sending the resultant image to the linking printhead.
SoPEC contains an embedded CPU for general-purpose system configuration and management. The CPU performs page and band header processing, motor control and sensor monitoring (via the GPIO) and other system control functions. The CPU can perform buffer management or report buffer status to the host. The CPU can optionally run vendor application specific code for general print control such as paper ready monitoring and LED status update.
A 2.5 Mbyte embedded memory buffer is integrated onto the SoPEC device, of which approximately 2 Mbytes are available for compressed page store data. A compressed page is divided into one or more bands, with a number of bands stored in memory. As a band of the page is consumed by the PEP for printing a new band can be downloaded. The new band may be for the current page or the next page.
Using banding it is possible to begin printing a page before the complete compressed page is downloaded, but care must be taken to ensure that data is always available for printing or a buffer underrun may occur. A Storage SoPEC acting as a memory buffer could be used to provide guaranteed data delivery.
The embedded single-port USB2.0 device controller can be used either for interface to the host PC, or for communication with another SoPEC as an ISCSlave. It accepts compressed page data and control commands from the host PC or ISCMaster SoPEC, and transfers the data to the embedded memory for printing or downstream distribution.
The embedded three-port USB2.0 host controller enables communication with other SoPEC devices as a ISCMaster, as well as interfacing with external chips (e.g. for Ethernet connection) and external USB devices, such as digital cameras.
SoPEC contains embedded controllers for a variety of printer system components such as motors, LEDs etc, which are controlled via SoPEC's GPIOs. This minimizes the need for circuits external to SoPEC to build a complete printer system.
The printhead is constructed by abutting a number of printhead ICs together. Each SoPEC can drive up to 12 printhead ICs at data rates up to 30 ppm or 6 printhead ICs at data rates up to 60 ppm. For higher data rates, or wider printheads, multiple SoPECs must be used.
Each SoPEC device has 2 LSS system buses for communication with QA devices for system authentication and ink usage accounting. The number of QA devices per bus and their position in the system is unrestricted with the exception that PRINTER_QA and INK_QA devices should be on separate LSS busses.
Each SoPEC system can have several QA devices. Normally each printing SoPEC will have an associated PRINTER_QA. Ink cartridges will contain an INK_QA chip. PRINTER_QA and INK_QA devices should be on separate LSS busses. All QA chips in the system are physically identical with flash memory contents defining PRINTER_QA from INK_QA chip.
In a multi-SoPEC system, the primary communication channel is from a USB2.0 Host port on one SoPEC (the ISCMaster), to the USB2.0 Device port of each of the other SoPECs (ISCSlaves). If there are more ISCSlave SoPECs than available USB Host ports on the ISCMaster, additional connections could be via a USB Hub chip, or daisy-chained SoPEC chips. Typically one or more of SoPEC's GPIO signals would also be used to communicate specific events between multiple SoPECs.
The communication between the host PC and the ISCMaster SoPEC may involve an external chip or subsystem, to provide a non-USB host interface, such as ethernet or WiFi. This subsystem may also contain memory to provide an additional buffered band/page store, which could provide guaranteed bandwidth data deliver to SoPEC during complex page prints.
Several possible SoPEC based system architectures exist. It is possible to have extra SoPEC devices in the system used for DRAM storage. The QA chip configurations shown are indicative of the flexibility of LSS bus architecture, but not limited to those configurations.
In FIG. 1, a single SoPEC device is used to control a linking printhead with 11 printhead ICs. The SoPEC receives compressed data from the host through its USB device port. The compressed data is processed and transferred to the printhead. This arrangement is limited to a speed of 30 ppm. The single SoPEC also controls all printer components such as motors, LEDs, buttons etc, either directly or indirectly.
In FIG. 2, two SoPECs control a single linking printhead, to provide 60 ppm A4 printing. Each SoPEC drives 5 or 6 of the printheads ICs that make up the complete printhead. SoPEC #0 is the ISCMaster, SoPEC #1 is an ISCSlave. The ISCMaster receives all the compressed page data for both SoPECs and re-distributes the compressed data for the ISCSlave over a local USB bus. There is a total of 4 MBytes of page store memory available if required. Note that, if each page has 2 MBytes of compressed data, the USB2.0 interface to the host needs to run in high speed (not full speed) mode to sustain 60 ppm printing. (In practice, many compressed pages will be much smaller than 2 MBytes). The control of printer components such as motors, LEDs, buttons etc, is shared between the 2 SoPECs in this configuration.
In FIG. 3, two SoPEC devices are used to control two printheads. Each printhead prints to opposite sides of the same page to achieve duplex printing. SoPEC #0 is the ISCMaster, SoPEC #1 is an ISCSlave. The ISCMaster receives all the compressed page data for both SoPECs and re-distributes the compressed data for the ISCSlave over a local USB bus. This configuration could print 30 double-sided pages per minute.
In FIG. 4, two SoPEC devices are used to control one A3 linking printhead, constructed from 16 printhead ICs. Each SoPEC controls 8 printhead ICs. This system operates in a similar manner to the 60 ppm A4 system in FIG. 2, although the speed is limited to 30 ppm at A3, since each SoPEC can only drive 6 printhead ICs at 60 ppm speeds. A total of 4 Mbyte of page store is available, this allows the system to use compression rates as in a single SoPEC A4 architecture, but with the increased page size of A3.
In FIG. 5 a four SoPEC system is shown. It contains 2 A3 linking printheads, one for each side of an A3 page. Each printhead contain 16 printhead ICs, each SoPEC controls 8 printhead ICs. SoPEC #0 is the ISCMaster with the other SoPECs as ISCSlaves. Note that all 3 USB Host ports on SoPEC #0 are used to communicate with the 3 ISCSlave SoPECs. In total, the system contains 8 Mbytes of compressed page store (2 Mbytes per SoPEC), so the increased page size does not degrade the system print quality, from that of an A4 simplex printer. The ISCMaster receives all the compressed page data for all SoPECs and re-distributes the compressed data over the local USB bus to the ISCSlaves. This configuration could print 30 double-sided A3 sheets per minute.
Extra SoPECs can be used for DRAM storage e.g. in FIG. 6 an A4 simplex printer can be built with a single extra SoPEC used for DRAM storage. The DRAM SoPEC can provide guaranteed bandwidth delivery of data to the printing SoPEC. SoPEC configurations can have multiple extra SoPECs used for DRAM storage.
FIG. 7 shows a configuration in which the connection from the host PC to the printer is an ethernet network, rather than USB. In this case, one of the USB Host ports on SoPEC interfaces to a external device that provide ethernet-to-USB bridging. Note that some networking software support in the bridging device might be required in this configuration. A Flash RAM will be required in such a system, to provide SoPEC with driver software for the Ethernet bridging function.
The SoPEC is a page rendering engine ASIC that takes compressed page images as input, and produces decompressed page images at up to 6 channels of bi-level dot data as output. The bi-level dot data is generated for the Memjet linking printhead. The dot generation process takes account of printhead construction, dead nozzles, and allows for fixative generation.
A single SoPEC can control up to 12 linking printheads and up to 6 color channels at >10,000 lines/sec, equating to 30 pages per minute. A single SoPEC can perform full-bleed printing of A4 and Letter pages. The 6 channels of colored ink are the expected maximum in a consumer SOHO, or office Memjet printing environment:

    
    
        CMY, for regular color printing.
        K, for black text, line graphics and gray-scale printing.
        IR (infrared), for Netpage-enabled applications.
        F (fixative), to enable printing at high speed. Because the Memjet printer is capable of printing so fast, a fixative may be required on specific media types (such as calendared paper) to enable the ink to dry before the page touches a previously printed page. Otherwise the pages may bleed on each other. In low speed printing environments, and for plain and photo paper, the fixative is not be required.
    
    


SoPEC is color space agnostic. Although it can accept contone data as CMYX or RGBX, where X is an optional 4th channel (such as black), it also can accept contone data in any print color space. Additionally, SoPEC provides a mechanism for arbitrary mapping of input channels to output channels, including combining dots for ink optimization, generation of channels based on any number of other channels etc. However, inputs are typically CMYK for contone input, K for the bi-level input, and the optional Netpage tag dots are typically rendered to an infra-red layer. A fixative channel is typically only generated for fast printing applications.
SoPEC is resolution agnostic. It merely provides a mapping between input resolutions and output resolutions by means of scale factors. The expected output resolution is 1600 dpi, but SoPEC actually has no knowledge of the physical resolution of the linking printhead.
SoPEC is page-length agnostic. Successive pages are typically split into bands and downloaded into the page store as each band of information is consumed and becomes free.
SoPEC provides mechanisms for synchronization with other SoPECs. This allows simple multi-SoPEC solutions for simultaneous A3/A4/Letter duplex printing. However, SoPEC is also capable of printing only a portion of a page image. Combining synchronization functionality with partial page rendering allows multiple SoPECs to be readily combined for alternative printing requirements including simultaneous duplex printing and wide format printing.
The required printing rate for a single SoPEC is 30 sheets per minute with an inter-sheet spacing of 4 cm. To achieve a 30 sheets per minute print rate, this requires:

300 mm×63 (dot/mm)/2 sec=105.8 □seconds per line, with no inter-sheet gap.

340 mm×63 (dot/mm)/2 sec=93.3 □seconds per line, with a 4 cm inter-sheet gap.

A printline for an A4 page consists of 13824 nozzles across the page. At a system clock rate of 192 MHz, 13824 dots of data can be generated in 69.2 □seconds. Therefore data can be generated fast enough to meet the printing speed requirement.
Once generated, the data must be transferred to the printhead. Data is transferred to the printhead ICs using a 288 MHz clock (3/2 times the system clock rate). SoPEC has 6 printhead interface ports running at this clock rate. Data is 8b/10b encoded, so the thoughput per port is 0.8×288=230.4 Mb/sec. For 6 color planes, the total number of dots per printhead IC is 1280×6=7680, which takes 33.3 □seconds to transfer. With 6 ports and 11 printhead ICs, 5 of the ports address 2 ICs sequentially, while one port addresses one IC and is idle otherwise. This means all data is transferred on 66.7 □seconds (plus a slight overhead). Therefore one SoPEC can transfer data to the printhead fast enough for 30 ppm printing.
From the highest point of view the SoPEC device consists of 3 distinct subsystems

    
    
        CPU Subsystem
        DRAM Subsystem
        Print Engine Pipeline (PEP) Subsystem

See FIG. 13 for a block level diagram of SoPEC.

    
    


The CPU subsystem controls and configures all aspects of the other subsystems. It provides general support for interfacing and synchronising the external printer with the internal print engine. It also controls the low speed communication to the QA chips. The CPU subsystem contains various peripherals to aid the CPU, such as GPIO (includes motor control), interrupt controller, LSS Master, MMI and general timers. The CPR block provides a mechanism for the CPU to powerdown and reset individual sections of SoPEC. The UDU and UHU provide high-speed USB2.0 interfaces to the host, other SoPEC devices, and other external devices. For security, the CPU supports user and supervisor mode operation, while the CPU subsystem contains some dedicated security components.
The DRAM subsystem accepts requests from the CPU, UHU, UDU, MMI and blocks within the PEP subsystem. The DRAM subsystem (in particular the DIU) arbitrates the various requests and determines which request should win access to the DRAM. The DIU arbitrates based on configured parameters, to allow sufficient access to DRAM for all requestors. The DIU also hides the implementation specifics of the DRAM such as page size, number of banks, refresh rates etc.
The Print Engine Pipeline (PEP) subsystem accepts compressed pages from DRAM and renders them to bi-level dots for a given print line destined for a printhead interface that communicates directly with up to 12 linking printhead ICs.
The first stage of the page expansion pipeline is the CDU, LBD and TE. The CDU expands the JPEG-compressed contone (typically CMYK) layer, the LBD expands the compressed bi-level layer (typically K), and the TE encodes Netpage tags for later rendering (typically in IR, Y or K ink). The output from the first stage is a set of buffers: the CFU, SFU, and TFU. The CFU and SFU buffers are implemented in DRAM.
The second stage is the HCU, which dithers the contone layer, and composites position tags and the bi-level spot0 layer over the resulting bi-level dithered layer. A number of options exist for the way in which compositing occurs. Up to 6 channels of bi-level data are produced from this stage. Note that not all 6 channels may be present on the printhead. For example, the printhead may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the position tags may be printed in K or Y if IR ink is not available (or for testing purposes).
The third stage (DNC) compensates for dead nozzles in the printhead by color redundancy and error diffusing dead nozzle data into surrounding dots.
The resultant bi-level 6 channel dot-data (typically CMYK-IRF) is buffered and written out to a set of line buffers stored in DRAM via the DWU.
Finally, the dot-data is loaded back from DRAM, and passed to the printhead interface via a dot FIFO. The dot FIFO accepts data from the LLU up to 2 dots per system clock cycle, while the PHI removes data from the FIFO and sends it to the printhead at a maximum rate of 1.5 dots per system clock cycle.







TABLE 9







Units within SoPEC










Sub-
Unit




system
Acronym
Unit Name
Description





DRAM
DIU
DRAM
Provides the interface for DRAM




interface
read and write access for the various




unit
PEP units, CPU, UDU, UHU and





MMI. The DIU provides arbitration





between competing units controls





DRAM access.



DRAM
Embedded
20 Mbits of embedded DRAM,




DRAM



CPU
CPU
Central
CPU for system configuration and




Process-
control




ing Unit




MMU
Memory
Limits access to certain memory




Manage-
address areas in CPU user mode




ment Unit




RDU
Real-time
Facilitates the observation of the




Debug
contents of most of the CPU




Unit
addressable registers in SoPEC in





addition to some pseudo-registers in





realtime.



TIM
General
Contains watchdog and general




Timer
system timers



LSS
Low Speed
Low level controller for interfacing




Serial
with the QA chips




Interfaces




GPIO
General
General IO controller, with built-in




Purpose
Motor control unit, LED pulse units




IOs
and de-glitch circuitry



MMI
Multi-
Generic Purpose Engine for protocol




Media
generation and control with




Interface
integrated DMA controller.



ROM
Boot ROM
16 KBytes of System Boot ROM





code



ICU
Interrupt
General Purpose interrupt controller




Control-
with configurable priority, and




ler Unit
masking.



CPR
Clock,
Central Unit for controlling and




Power
generating the system clocks and




and Reset
resets and powerdown mechanisms




block




PSS
Power
Storage retained while system is




Save
powered down




Storage




USB
Universal
USB multiport (4) physical interface.



PHY
Serial





Bus (USB)





Physical




UHU
USB Host
USB host controller interface with




Unit
integrated DIU DMA controller



UDU
USB
USB Device controller interface with




Device
integrated DIU DMA controller




Unit



Print
PCU
PEP
Provides external CPU with the


Engine

control-
means to read and write PEP Unit


Pipe-

ler
registers, and read and write DRAM


line


in single 32-bit chunks.


(PEP)
CDU
Contone
Expands JPEG compressed contone




decoder
layer and writes decompressed




unit
contone to DRAM



CFU
Contone
Provides line buffering between




FIFO Unit
CDU and HCU



LBD
Lossless
Expands compressed bi-level layer.




Bi-level





Decoder




SFU
Spot FIFO
Provides line buffering between




Unit
LBD and HCU



TE
Tag
Encodes tag data into line of tag




encoder
dots.



TFU
Tag FIFO
Provides tag data storage between




Unit
TE and HCU



HCU
Halftoner
Dithers contone layer and




compos-
composites the bi-level spot 0 and




itor unit
position tag dots.



DNC
Dead
Compensates for dead nozzles by




Nozzle
color redundancy and error diffusing




Compen-
dead nozzle data into surrounding




sator
dots.



DWU
Dotline
Writes out the 6 channels of dot data




Writer
for a given printline to the line store




Unit
DRAM



LLU
Line
Reads the expanded page image from




Loader
line store, formatting the data




Unit
appropriately for the linking





printhead.



PHI
PrintHead
Is responsible for sending dot data to




Interface
the linking printheads and for





providing line synchronization





between multiple SoPECs. Also





provides test interface to printhead





such as temperature monitoring and





Dead Nozzle Identification.









SoPEC must address 20 Mbit DRAM, PCU addressed registers in PEP and CPU-subsystem addressed registers.
SoPEC has a unified address space with the CPU capable of addressing all CPU-subsystem and PCU-bus accessible registers (in PEP) and all locations in DRAM. The CPU generates byte-aligned addresses for the whole of SoPEC.
22 bits are sufficient to byte address the whole SoPEC address space.
The embedded DRAM is composed of 256-bit words. Since the CPU-subsystem may need to write individual bytes of DRAM, the DIU is byte addressable. 22 bits are required to byte address 20 Mbits of DRAM.
Most blocks read or write 256-bit words of DRAM. For these blocks only the top 17 bits i.e. bits 21 to 5 are required to address 256-bit word aligned locations.
The exceptions are

    
    
        CDU which can write 64-bits so only the top 19 address bits i.e. bits 21-3 are required.
        The CPU-subsystem always generates a 22-bit byte-aligned DIU address but it will send flags to the DIU indicating whether it is an 8, 16 or 32-bit write.
        The UHU and UDU generate 256-bit aligned addresses, with a byte-wise write mask associated with each data word, to allow effective byte addressing of the DRAM.

Regardless of the size no DIU access is allowed to span a 256-bit aligned DRAM word boundary.

    
    


PEP Unit configuration registers which specify DRAM locations should specify 256-bit aligned DRAM addresses i.e. using address bits 21:5. Legacy blocks from PEC1 e.g. the LBD and TE may need to specify 64-bit aligned DRAM addresses if these reused blocks DRAM addressing is difficult to modify. These 64-bit aligned addresses require address bits 21:3. However, these 64-bit aligned addresses should be programmed to start at a 256-bit DRAM word boundary.
Unlike PEC1, there are no constraints in SoPEC on data organization in DRAM except that all data structures must start on a 256-bit DRAM boundary. If data stored is not a multiple of 256-bits then the last word should be padded.
The CPU subsystem bus supports 32-bit word aligned read and write accesses with variable access timings. The CPU subsystem bus does not currently support byte reads and writes.
The PCU only supports 32-bit register reads and writes for the PEP blocks. As the PEP blocks only occupy a subsection of the overall address map and the PCU is explicitly selected by the MMU when a PEP block is being accessed the PCU does not need to perform a decode of the higher-order address bits. The system wide memory map is shown in FIG. 14.
The MMU performs the decode of cpu_adr[21:12] to generate the relevant cpu_block select signal for each block. The addressed blocks decode however many of the lower order bits of cpu_adr as are required to address all the registers or memory within the block. The effect of decoding fewer bits is to cause the address space within a block to be duplicated many times (i.e. mirrored) depending on how many bits are required.
A write to a undefined register address within the defined address space for a block can have undefined consequences, a read of an undefined address will return undefined data. Note this is a consequence of only using the low order bits of the CPU address for an address decode (cpu_adr).
The PEP blocks are addressed via the PCU. From FIG. 14, the PCU mapped registers are in the range 0x0004—0000 to 0x0004_BFFF. There are 12 sub-blocks within the PCU address space. Therefore, only four bits are necessary to address each of the sub-blocks within the PEP part of SoPEC. A further 12 bits may be used to address any configurable register within a PEP block. This gives scope for 1024 configurable registers per sub-block (the PCU mapped registers are all 32-bit addressed registers so the upper 10 bits are required to individually address them). This address will come either from the CPU or from a command stored in DRAM. The bus is assembled as follows:

    
    
        address[15:12]=sub-block address,
        address[n:2]=register address within sub-block, only the number of bits required to decode the registers within each sub-block are used,
        address[1:0]=byte address, unused as PCU mapped registers are all 32-bit addressed registers.
    
    


So for the case of the HCU, its addresses range from 0x7000 to 0x7FFF within the PEP subsystem or from 0x0004—7000 to 0x0004—7FFF in the overall system.
SoPEC has a requirement to print 1 side every 2 seconds i.e. 30 sides per minute. Approximately 2 Mbytes of DRAM are reserved for compressed page buffering in SoPEC. If a page is compressed to fit within 2 Mbyte then a complete page can be transferred to DRAM before printing. USB2.0 in high speed mode allows the transfer of 2 Mbyte in less than 40 ms, so data transfer from the host is not a significant factor in print time in this case. For a host PC running in USB1.1 compatible full speed mode, the transfer time for 2 Mbyte approaches 2 seconds, so the cycle time for full page buffering approaches 4 seconds.
The SoPEC page-expansion blocks support the notion of page banding. The page can be divided into bands and another band can be sent down to SoPEC while the current band is being printed. Therefore printing can start once at least one band has been downloaded.
The band size granularity should be carefully chosen to allow efficient use of the USB bandwidth and DRAM buffer space. It should be small enough to allow seamless 30 sides per minute printing but not so small as to introduce excessive CPU overhead in orchestrating the data transfer and parsing the band headers. Band-finish interrupts have been provided to notify the CPU of free buffer space. It is likely that the host PC will supervise the band transfer and buffer management instead of the SoPEC CPU.
If SoPEC starts printing before the complete page has been transferred to memory there is a risk of a buffer underrun occurring if subsequent bands are not transferred to SoPEC in time e.g. due to insufficient USB bandwidth caused by another USB peripheral consuming USB bandwidth. A buffer underrun occurs if a line synchronisation pulse is received before a line of data has been transferred to the printhead and causes the print job to fail at that line. If there is no risk of buffer underrun then printing can safely start once at least one band has been downloaded.
If there is a risk of a buffer underrun occurring due to an interruption of compressed page data transfer, then the safest approach is to only start printing once all of the bands have been loaded for a complete page. This means that some latency (dependent on USB speed) will be incurred before printing the first page. Bands for subsequent pages can be downloaded during the printing of the first page as band memory is freed up, so the transfer latency is not incurred for these pages.
A Storage SoPEC, or other memory local to the printer but external to SoPEC, could be added to the system, to provide guaranteed bandwidth data delivery.
The most efficient page banding strategy is likely to be determined on a per page/print job basis and so SoPEC will support the use of bands of any size.
In a system containing more than one SoPECs, the high bandwidth communication path between SoPECs is via USB. Typically, one SoPEC, the ISCMaster, has a USB connection to the host PC, and is responsible for receiving and distributing page data for itself and all other SoPECs in the system. The ISCMaster acts as a USB Device on the host PC's USB bus, and as the USB Host on a USB bus local to the printer.
Any local USB bus in the printer is logically separate from the host PC's USB bus; a SoPEC device does not act as a USB Hub. Therefore the host PC sees the entire printer system as a single USB function.
The SoPEC UHU supports three ports on the printer's USB bus, allowing the direct connection of up to three additional SoPEC devices (or other USB devices). If more than three USB devices need to be connected, two options are available: expand the number of ports on the printer USB bus using a USB Hub chip; and create one or more additional printer USB busses, using the UHU ports on other SoPEC devices. FIG. 15 shows these options.
Since the UDU and UHU for a single SoPEC are on logically different USB busses, data flow between them is via the on-chip DRAM, under the control of the SoPEC CPU. There is no direct communication, either at control or data level, between the UDU and the UHU. For example, when the host PC sends compressed page data to a multi-SoPEC system, all the data for all SoPECs must pass via the DRAM on the ISCMaster SoPEC. Any control or status messages between the host and any SoPEC will also pass via the ISCMaster's DRAM.
Further, while the UDU on SoPEC supports multiple USB interfaces and endpoints within a single USB device function, it typically does not have a mechanism to identify at the USB level which SoPEC is the ultimate destination of a particular USB data or control transfer. Therefore software on the CPU needs to redirect data on a transfer-by-transfer basis, either by parsing a header embedded in the USB data, or based on previously communicated control information from the host PC. The software overhead involved in this management adds to the overall latency of compressed page download for a multi-SoPEC system.
The UDU and UHU contain highly configurable DMA controllers that allow the CPU to direct USB data to and from DRAM buffers in a flexible way, and to monitor the DMA for a variety of conditions. This means that the CPU can manage the DRAM buffers between the UDU and the UHU without ever needing to physically move or copy packet data in the DRAM.
The bi-lithic printhead is now described, as distinct from the linking printhead, from the point of view of printing 30 ppm from a SoPEC ASIC, as well as architectures that solve the 60 ppm printing requirement using the bi-lithic printhead model.
To print at 30 ppm, the printheads must print a single page within 2 seconds. This would include the time taken to print the page itself plus any inter-page gap (so that the 30 ppm target could be met). The required printing rate assumes an inter-sheet spacing of 4 cm.
A baseline SoPEC system connecting to two printhead segments is shown in FIG. 52. The two segments (A and B) combine to form a printhead of typical width 13,824 nozzles per color. Decoupling of data generation, transmission to the printhead, and firing are assumed.
A single SoPEC produces the data for both printheads for the entire page. Therefore it has the entire line time in which to generate the dot data.
A Letter page is 11 inches high. Assuming 1600 dpi and a 4 cm inter-page gap, there are 20,120 lines. This is a line rate of 10.06 KHz (a line time of 99.4 us).
The printhead is 14,080 dots wide. To calculate these dots within the line time, SoPEC requires a 140.8 MHz dot generation rate. Since SoPEC is run at 160 MHz and generates 1 dot per cycle, it is able to meet the Letter page requirement and cope with a small amount of stalling during the dot generation process.
An A4 page is 297 mm high. Assuming 62.5 dots/mm and a 4 cm inter-page gap, there are 21,063 lines. This is a line rate of 10.54 KHz (a line time of 94.8 us).
The printhead is 14,080 dots wide. To calculate these dots within the line time, SoPEC requires a 148.5 MHz dot generation rate. Since SoPEC is run at 160 MHz and generates 1 dot per cycle, it is able to meet the A4 page requirement and cope with minimal stalling.
Assuming an n-color printhead, SoPEC must transmit 14,080 dots □ n-bits within the line time. i.e. n □ the data generation rate=n-bits □ 14,080 dots □ 10.54 KHz. Thus a 6-color printhead requires 874.2 Mb/sec.
The transmission time is further constrained by the fact that no data must be transmitted to the printhead segments during a window around the linesync pulse. Assuming a 1% overhead for linesync overhead (being very conservative), the required transmission bandwidth for 6 colors is 883 Mb/sec.
However, the data is transferred to both segments simultaneously. This means the longest time to transfer data for a line is determined by the time to transfer print data to the longest print segment. There are 9744 nozzles per color across a type7 printhead. We therefore must be capable of transmitting 6-bits □ 9744 dots at the line rate i.e. 6-bits □ 9744 □ 10.54 KHz=616.2 Mb/sec. Again, assuming a 1% overhead for linesync overhead, the required transmission bandwidth to each printhead is 622.4 Mb/sec.
The connections from SoPEC to each segment consist of 2 □ 1-bit data lines that operate at 320 MHz each. This gives a total of 640 Mb/sec.
Therefore the dot data can be transmitted at the appropriate rate to the printhead to meet the 30 ppm requirement.
SoPEC has a dot generation pipeline that generates 1 □ 6-color dot per cycle.
The LBD and TE are imported blocks from PEC1, with only marginal changes, and these are therefore capable of nominally generating 2 dots per cycle. However the rest of the pipeline is only capable of generating 1 dot per cycle.
SoPEC is capable of transmitting data to 2 printheads simultaneously. Connections are 2 data plus 1 clock, each sent as an LVDS 2-wire pair. Each LVDS wire-pair is run at 320 MHz.
SoPEC is in a 100-pin QFP, with 12 of those wires dedicated to the transmission of print data (6 wires per printhead segment). Additional wires connect SoPEC to the printhead, but they are not considered for the purpose of this discussion.
The dot data is accepted by the printhead at 2-bits per cycle at 320 MHz. 6 bits are available after 3 cycles at 320 MHz, and these 6-bits are then clocked into the shift registers within the printhead at a rate of 106 MHz.
Thus the data movement within the printhead shift registers is able to keep up with the rate at which data arrives in the printhead.
This chapter describes the issues introduced by printing at 60 ppm, with the cases of 4, 5, and 6 colors in the printhead. The arrangement is shown in FIG. 53.
A 60 ppm printer is 1 page per second, i.e., A4=21,063 lines. This is a line rate of 21.06 KHz (a line time of 47.4 us) and Letter=20,120 lines. This is a line rate of 20.12 KHz (a line time of 49.7 us)
If each SoPEC is responsible for generating the data for its specific printhead, then the worst case for dot generation is the largest printhead. The dot generation rate for the 3 printhead configurations is shown in Table 1.







TABLE 1







Dot generation rate required











5:5
6:4
7:3
















# dots in largest printhead
6912

8328

9744



segment








Required dot generation
145.6
MHz
175.4
MHz
205.2
MHz


rate









Since the preferred embodiment of SoPEC is run at 160 MHz, it is only able to meet the dot requirement rate for the 5:5 printhead, and not the 6:4 or 7:3 printheads.
Each SoPEC must transmit a printhead's worth of bits per color to the printhead per line. The transmission time is further constrained by the fact that no data must be transmitted to the printhead segments during a window around the linesync pulse. Assuming that the line sync overhead is constant regardless of print speed, then a 1% overhead at 30 ppm translates into a 2% overhead at 60 ppm.
The required transmission bandwidths are therefore as described in Table 2.







TABLE 2







Transmission bandwidth required











5:5
6:4
7:3
















# dots in largest 
6912

8328

9744



printhead segment








Transmission rate per
145.6
Mb/sec
175.4
Mb/sec
205.2
Mb/sec


color plane








With linesync overhead
148.5
Mb/sec
179
Mb/sec
209.3
Mb/sec


of 2%








Transmission rate for 4
594
Mb/sec
716
Mb/sec
837
Mb/sec


colors








Transmission rate for 5
743
Mb/sec
895
Mb/sec
1047
Mb/sec


colors








Transmission rate for 6
891
Mb/sec
1074
Mb/sec
1256
Mb/sec


colors









Since we have 2 lines to the printhead operating at 320 MHz each, the total bandwidth available is 640 Mb/sec. The existing connection to the printhead will only deliver data to a 4-color 5:5 arrangement printhead fast enough for 60 ppm. The connection speed in the preferred embodiment is not fast enough to support any other printhead or color configuration.
The dot data is currently accepted by the printhead at 2-bits per cycle at 320 MHz. Although the connection rate is only fast enough for 4 color 5:5 printing, the data must still be moved around in the shift registers once received.
The 5:5 printer 4-color dot data is accepted by the printhead at 2-bits per cycle at 320 MHz. 4 bits are available after 2 cycles at 320 MHz, and these 4-bits would then need to be clocked into the shift registers within the printhead at a rate of 160 MHz.
Since the 6:4 and 7:3 printhead configuration schemes require additional bandwidth etc., the printhead needs some change to support these additional forms of 60 ppm printing.
Given the problems described above, the following issues have been addressed for 60 ppm printing based on the earlier SoPEC architecture:

    
    
        rate of data generation
        transmission to the printhead
        shift register setup within the printhead.
    
    


Assuming the current bi-lithic printhead, there are 3 basic classes of solutions to allow 60 ppm:

    a. Each SoPEC generates dot data and transmits that data to a single printhead connection, as shown in FIG. 54.
    b. One SoPEC generates data and transmits to the smaller printhead, but both SoPECs generate and transmit directly to the larger printhead, as shown in FIG. 55.
    c. Same as (b) except that SoPEC A only transmits to printhead B via SoPEC B (i.e. instead of directly), as shown in FIG. 56.


In Class A each SoPEC writes to a printhead. This solution class is where each SoPEC generates dot data and transmits that data to a single printhead connection, as shown in FIG. 54. The existing SoPEC architecture is targeted at this class of solution.
Two methods of implementing a 60 ppm solution of this class are now examined.
To achieve 60 ppm using the same basic architecture as currently implemented, the following needs to occur:

    
    
        Increase effective dot generation rate to 206 MHz
        Increase bandwidth to printhead to 1256 Mb/sec
        Increase bandwidth of printhead shift registers to match transmission bandwidth
    
    


It should be noted that even when all these speed improvements are implemented, one SoPEC will still be producing 40% more dots than it would be under a 5:5 scheme. i.e. this class of solution is not load balanced.
In this scenario, each SoPEC generates data as if for a 5:5 printhead, and the printhead, even though it is physically a 5:5, 6:4 or 7:3 printhead, maintains a logical appearance of a 5:5 printhead.
There are a number of means of accomplishing this logical appearance, but they all rely on the two printheads being connected in some way, as shown in FIG. 55.
In this embodiment, the dot generation rate no longer needs to be addressed as only the 5:5 dot generation rate is required, and the current speed of 160 MHz is sufficient.
In class B two SoPECs write directly to a single printhead. This solution class is where one SoPEC generates data and transmits to the smaller printhead, but both SoPECs generate and transmit directly to the larger printhead, as shown in FIG. 56. i.e. SoPEC A transmits to printheads A and B, while SoPEC B transmits only to printhead B. The intention is to allow each SoPEC to generate the dot data for a type 5 printhead, and thereby to balance the dot generation load.
Since the connections between SoPEC and printhead are point-to-point, it requires a doubling of printhead connections on the larger printhead (one connection set goes to SoPEC A and the other goes to SoPEC B).
The two methods of implementing a 60 ppm solution of this class depend on the internals of the printhead, and are now examined.
The serial load scenario is when the two connections on the printhead are connected to the same shift register. Thus the shift register can be driven by either SoPEC, as shown in FIG. 57.
The 2 SoPECs take turns (under synchronisation) in transmitting on their individual lines as follows:

    
    
        SoPEC B transmits even (or odd) data for 5 segments
        SoPEC A transmits data for 5-printhead A segments even and odd
        SoPEC B transmits the odd (or even) data for 5 segments.
    
    


Meanwhile SoPEC A is transmitting the data for printhead A, which will be length 3, 4, or 5.
Note that SoPEC A is transmitting as if to a printhead combination of N:5N, which means that the dot generation pathway (other than synchronization) is already as defined.
Although the dot generation problem is resolved by this scenario (each SoPEC generates data for half the page width and therefore it is load balanced), the transmission speed for each connection must be sufficient to deliver to a type7 printhead i.e. 1256 Mb/sec. In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth.
The parallel load scenario when the two connections on the printhead are connected to different shift registers, as shown in FIG. 58. Thus the two SoPECs can write to the printhead in parallel.
Note that SoPEC A is transmitting as if to a printhead combination of N:5-N, which means that the dot generation pathway is already as defined.
The dot generation problem is resolved by this scenario since each SoPEC generates data for half the page width and therefore it is load balanced.
Since the connections operate in parallel, the transmission speed required is that required to address 5:5 printing, i.e. 891 Mb/sec. In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth.
In class C two SoPECs write to a single printhead, one indirectly. This solution class is the same as class B except that SoPEC A only transmits to printhead B via SoPEC B (i.e. instead of directly), as shown in FIG. 59 i.e. SoPEC A transmits directly to printhead A and indirectly to printhead B via SoPEC B, while SoPEC B transmits only to printhead B.
This class of architecture has the attraction that a printhead is driven by a single SoPEC, which minimizes the number of pins on a printhead. However it requires receiver connections on SoPEC B. It becomes particularly practical (costwise) if those receivers are currently unused (i.e. they would have been used for transmitting to the second printhead in a single SoPEC system). Of course this assumes that the pins are not being used to achieve the higher bandwidth.
Since there is only a single connection on the printhead, the serial load scenario would be the mechanism for transfer of data, with the only difference that the connections to the printhead are via SoPEC B.
Although the dot generation problem is resolved by this scenario (each SoPEC generates data for half the page width and therefore it is load balanced), the transmission speed for each connection must be sufficient to deliver to a type7 printhead i.e. 1256 Mb/sec. In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth.
If SoPEC B provides at least a line buffer for the data received from SoPEC A, then the transmission between SoPEC A and printhead A is decoupled, and although the bandwidth from SoPEC B to printhead B must be 1256 Mb/sec, the bandwidth between the two SoPECs can be lower i.e. enough to transmit 2 segments worth of data (359 Mb/sec).
Architecture A has the problem that no matter what the increase in speed, the solution is not load balanced, leaving architecture B or C the more preferred solution where load-balancing between SoPEC chips is desirable or necessary. The main advantage of an architecture A style solution is that it reduces the number of connections on the printhead.
All architectures require the increase in bandwidth to the printhead, and a change to the internal shift register structure of the printhead.
Other architectures can be used where different printhead modules are used. For example, in one embodiment, the dot data is provided from a single printed controller (SoPEC) via multiple serial links to a printhead. Preferably, the links in this embodiment each carry dot data for more than one channel (color, etc) of the printhead. For example, one link can carry CMY dot data from the printer controller and the other channel can carry K, IR and fixative channels.
The clock frequency of SoPEC could be increased from 160 MHz, e.g. to 176 or 192 MHz. 192 MHz is convenient because it allows the simple generation of a 48 MHz clock as required for the USB cores.
Under architecture A, a 176 MHz clock speed would be sufficient to generate dot data for 5:5 and 6:4 printheads, but would not be sufficient to generate data for a 7:3 printhead.
With architectures B and C, any clock speed increase can be applied to increasing the inter-page gap, or the ability to cope with local stalling.
The cost of increasing the dot generation speed is:

    
    
        a slight increase in area within SoPEC
        an increase in time to achieve timing closure in SoPEC
        the possibility of the JPEG core being reduced to half speed if it can't be run at the target frequency (current speed rating on CU 11 is 185 MHz)
        the possibility of the LEON core being reduced in speed if it can't be run at the target frequency
        an increase in power consumption thereby requiring a different (more expensive) package.
    
    


All of these factors are exacerbated by the proportion of speed increase. A 10% speed increase is within the JPEG core tolerance.
Since a single SoPEC is incapable of generating the data required for a type6 or type 7 printhead, yet is capable of generating the data for a type5 printhead, it is possible to share the generation load by having each SoPEC generate the data for half the total printhead width.
Architectures B and C are specifically designed to load share dot generation.
The problem introduced by load sharing is that the data from both SoPEC A and SoPEC B must be transmitted to the larger printhead.
At present there are 2 sets of connections from SoPEC to the printheads. Each set consists of 2 data plus a clock, running at twice the nominal SoPEC clock frequency i.e. 160 MHz gives 320 Mb/sec per channel.
Instead of having the odd and even nozzles connected by a single shift register, as is currently done and shown in FIG. 60, it is possible to place the even and odd nozzles on separate shift registers, as shown in FIG. 61.
By having the odd and even nozzles on different shift registers, the 6-bits of data is still received at the high rate (e.g. 320 MHz), but the shift register rate is halved, since each shift register is written to half as frequently. Thus it is possible to collect 12 bits (an odd and even dot), then shift them into the 12 shift registers (6 even, 6 odd) at 80 MHz (or whatever appropriate).
The effect is that data for even and odd dots has the same sense (i.e. always increasing or decreasing depending on the orientation of the printhead to the paper movement). However for the two printhead segments (and therefore the 2 SoPECs), the sense would be opposite (i.e. the data is always shifting towards the join point at the centre of the printhead).
As long as each SoPEC is responsible for writing to a single printhead segment (in a 5:5 printer this will be the case), then no change is required to SoPEC's DWU or PHI given the shift register arrangement in FIG. 61. The LLU needs to change to allow reading of odd and even data in an interleaved fashion (in the preferred form, all evens are read before all odds or vice versa). Additionally, the LLU would need to be changed be to permit the data rate required for data transmission.
However testing the integrity of the shift registers is of concern since there is no path back.
Instead of having odd and even dots on separate shift registers, it is possible to interweave the shift registers to keep the same sense of data transmission (e.g. from within the LLU), but keep the CMOS testing and lower speed shift-registers. Thus it is possible to collect 12 bits (representing two dots), then shift them into the 12 shift registers at 80 MHz (or as appropriate). The arrangement is shown FIG. 62.
The interweaving requires more wiring however it has the following advantages:

    
    
        The DWU is unchanged.
        The LLU stays the same in so far as the even dots are generated first, then the odd dots (or vice versa). The LLU still needs the bandwidth change for transmission.
        A shift register test path is enabled.
        The relative dot generation and bandwidth required is lower for A4 printing due to only half of the off-page dots needing to be sent.
    
    


The basic idea of the linking printhead is that we create a printhead from tiles each of which can be fully formed within the reticle. The printheads are linked together as shown in FIG. 63 to form the page-width printhead. For example, an A4/Letter page is assembled from 11 tiles.
The printhead is assembled by linking or butting up tiles next to each other. The physical process used for linking means that wide-format printheads are not readily fabricated (unlike the 21 mm tile). However printers up to around A3 portrait width (12 inches) are expected to be possible.
The nozzles within a single segment are grouped physically to reduce ink supply complexity and wiring complexity. They are also grouped logically to minimize power consumption and to enable a variety of printing speeds, thereby allowing speed/power consumption trade-offs to be made in different product configurations.
Each printhead segment contains a constant number of nozzles per color (currently 1280), divided into half (640) even dots and half (640) odd dots. If all of the nozzles for a single color were fired at simultaneously, the even and odd dots would be printed on different dot-rows of the page such that the spatial difference between any even/odd dot-pair is an exact number of dot lines. In addition, the distance between a dot from one color and the corresponding dot from the next color is also an exact number of dot lines.
The exact distance between even and odd nozzle rows, and between colors will vary between embodiments, so it is preferred that these relationships be programmable with respect to SoPEC.
When 11 segments are joined together to create a 30 ppm printhead, a single SoPEC will connect to them as shown in FIG. 64.
Notice that each phDataOutn lvds pair goes to two adjacent printhead segments, and that each phClkn signal goes to 5 or 6 printhead segments. Each phRstn signal goes to alternate printhead segments.
SoPEC drives phRst0 and phRst1 to put all the segments into reset.
SoPEC then lets phRst1 come out of reset, which means that all the segment 1, 3, 5, 7, and 9 are now alive and are capable of receiving commands.
SoPEC can then communicate with segment 1 by sending commands down phDataOut0, and program the segment 1 to be id 1. It can communicate with segment 3 by sending commands down phDataOut1, and program segment 3 to be id 1. This process is repeated until all segments 1, 3, 5, 7, and 9 are assigned ids of 1. The id only needs to be unique per segment addressed by a given phDataOutn line.
SoPEC can then let phRst0 come out of reset, which means that segments 0, 2, 4, 6, 8, and 10 are all alive and are capable of receiving commands. The default id after reset is 0, so now each of the segments is capable of receiving commands along the same pDataOutn line.
SoPEC needs to be able to send commands to individual printheads, and it does so by writing to particular registers at particular addresses.
The exact relationship between id and register address etc. is yet to be determined, but at the very least it will involve the CPU being capable of telling the PHI to send a command byte sequence down a particular phDataOutn line.
One possibility is that one register contains the id (possibly 2 bits of id). Further, a command may consist of:

    
    
        register write
        register address
        data
    
    


A 10-bit wide fifo can be used for commands in the PHI.
When 11 segments are joined together to create a 60 ppm printhead, the 2 SoPECs will connect to them as shown in FIG. 65.
In the 60 ppm case only phClk0 and phRst0 are used (phClk1 and phRst1 are not required). However note that lineSync is required instead. It is possible therefore to reuse phRst1 as a lineSync signal for multi-SoPEC synchronisation. It is not possible to reuse the pins from phClk1 as they are lvds. It should be possible to disable the lvds pads of phClk1 on both SoPECs and phDataOut5 on SoPEC B and therefore save a small amount of power.
Various classes of printhead that can be used. With the exception of the PEC1 style slope printhead, SoPEC is designed to be capable of working with each of these printhead types at full 60 ppm printing speed.
The A-chip/A-chip printhead style consists of identical printhead tiles (type A) assembled in such a way that rows of nozzles between 2 adjacent chips have no vertical misalignment.
The most ideal format for this kind of printhead from a data delivery point of view is a rectangular join between two adjacent printheads, as shown in FIG. 66. However due to the requirement for dots to be overlapping, a rectangular join results in a it results in a vertical stripe of white down the join section since no nozzle can be in this join region. A white stripe is not acceptable, and therefore this join type is not acceptable.
FIG. 67 shows a sloping join similar to that described for the bi-lithic printhead chip, and FIG. 68 is a zoom in of a single color component, illustrating the way in which there is no visible join from a printing point of view (i.e. the problem seen in FIG. 66 has been solved).
The A-chip/A-chip setup requires perfect vertical alignment. Due to a variety of factors (including ink sealing) it may not be possible to have perfect vertical alignment. To create more space between the nozzles, the A-chip/A-chip growing offset printhead style in which A-chips are joined with a growing vertical offset can be used, as shown in FIG. 69.
The growing offset comes from the vertical offset between two adjacent tiles. This offset increases with each join. For example, if the offset were 7 lines per join, then an 11 segment printhead would have a total of 10 joins, and 70 lines.
To supply print data to the printhead for a growing offset arrangement, the print data for the relevant lines must be present. A simplistic solution of simply holding the entire line of data for each additional line required leads to increased line store requirements. For example, an 11 segment×1280-dot printhead requires an additional 11×1280-dots×6-colors per line i.e. 10.3125 Kbytes per line. 70 lines requires 722 Kbytes of additional storage. Considering SoPEC contains only 2.5 MB total storage, an additional 722 Kbytes just for the offset component is not desirable. Smarter solutions require storage of smaller parts of the line, but the net effect is the same: increased storage requirements to cope with the growing vertical offset.
The A-chip/A-chip aligned nozzles, sloped chip placement printhead style overcomes the problem of a growing offset that a number of additional lines of storage need to be kept, and this number increases proportional to the number of joins i.e. the longer the printhead the more lines of storage are required.
This done by placing each chip on a mild slope to achieve a constant number of printlines regardless of the number of joins. The arrangement is similar to that used in PEC1, where the printheads are sloping. The difference here is that each printhead is only mildly sloping, for example so that the total number of lines gained over the length of the printhead is 7. The next printhead can then be placed offset from the first, but this offset would be from the same base. i.e. a printhead line of nozzles starts addressing line n, but moves to different lines such that by the end of the line of nozzles, the dots are 7 dotlines distant from the startline. This means that the 7-line offset required by a growing-offset printhead can be accommodated. The arrangement is shown in FIG. 70.
If the offset were 7 rows, then a total of 72.2 KBytes are required to hold the extra rows.
Note also, that in this example, the printhead segments are vertically aligned (as in PEC1). It may be that the slope can only be a particular amount, and that growing offset compensates for additional differences—i.e. the segments could in theory be misaligned vertically. In general SoPEC must be able to cope with vertically misaligned printhead segments.
The question then arises as to how much slope must be compensated for at 60 ppm speed. Basically—as much as can comfortably handled without too much logic. However, amounts like 1 in 256 (i.e. 1 in 128 with respect to a half color), or 1 in 128 (i.e. 1 in 64 with respect to a half color) must be possible. Greater slopes and weirder slopes (e.g. 1 in 129 with respect to a half color) must be possible, but with a sacrifice of speed i.e. SoPEC must be capable even if it is a slower print.
Note also that the nozzles are aligned, but the chip is placed sloped. This means that when horizontal lines are attempted to be printed and if all nozzles were fired at once, the effect would be lots of sloped lines. However, if the nozzles are fired in the correct order relative to the paper movement, the result is a straight line for n dots, then another straight line for n dots 1 line up.
The PEC1 style slope is the physical arrangement used by printhead segments addressed by PEC1. Note that SoPEC is not expected to work at 60 ppm speed with printheads connected in this way. However it is expected to work and is shown here for completeness, and if tests should prove that there is no working alternative to the 21 mm tile, then SoPEC will require significant reworking to accommodate this arrangement at 60 ppm.
In this scheme, the segments are joined together by being placed on an angle such that the segments fit under each other, as shown in FIG. 71. The exact angle will depend on the width of the Memjet segment and the amount of overlap desired, but the vertical height is expected to be in the order of 1 mm, which equates to 64 dot lines at 1600 dpi.
FIG. 72 shows more detail of a single segment in a multi-segment configuration, considering only a single row of nozzles for a single color plane. Each of the segments can be considered to produce dots for multiple sets of lines. The leftmost d nozzles (d depends on the angle that the segment is placed at) produce dots for line n, the next d nozzles produce dots for line n−1, and so on.
The A-chip/A-chip with inter-line slope compensation has the nozzles physically arranged inside the printhead to compensate for the nozzle firing order given the desire to spread the power across the printhead. This means that one nozzle and its neighbor can be vertically separated on the printhead by 1 printline. i.e. the nozzles don't line up across the printhead. This means a jagged effect on printed “horizontal lines” is avoided, while achieving the goal of averaging the power.
The arrangement of printheads is the same as that shown in FIG. 71. However the actual nozzles are slightly differently arranged, as illustrated via magnification in FIG. 73.
The A-chip/B-chip printhead style uses two kinds of printing chips: an A-type and a B-type. The two types of chips have different shapes, but can be joined together to form long printheads. A parallelogram is formed when the A-type and B-type are joined. The two types are joined together as shown in FIG. 74.
Note that this is not a growing offset. The segments of a multiple-segment printhead have alternating fixed vertical offset from a common point, as shown in FIG. 75.
If the vertical offset from a type-A to a type-B printhead were n lines, the entire printhead regardless of length would have a total of n lines additionally required in the line store. This is certainly a better proposition than a growing offset).
However there are many issues associated with an A-chip/B-chip printhead. Firstly, there are two different chips i.e. an A-chip, and a B-chip. This means 2 masks, 2 developments, verification, and different handling, sources etc. It also means that the shape of the joins are different for each printhead segment, and this can also imply different numbers of nozzles in each printhead. Generally this is not a good option.
The A-B chip with SoPEC compensation printhead style incorporates the above general linking concept illustrated in the A-chip/B-chip into a single printhead chip that contains the A-B join within the single chip type.
This kind of joining mechanism is referred to as the A-B chip since it is a single chip with A and B characteristics. The two types are joined together as shown in FIG. 76.
This has the advantage of the single chip for manipulation purposes.
Note that as with the A-chip/B-chip style, SoPEC must compensate for the vertical misalignment within the printhead. The amount of misalignment is the amount of additional line storage required.
Note that this kind of printhead can effectively be considered similar to the mildly sloping printhead described above except that the step at the discontinuity is likely to be many lines vertically (on the order of 7 or so) rather than the 1 line that a gentle slope would generate.
The A-B chip with printhead compensation printhead style is where we push the A-B chip discontinuity as far along the printhead segment as possible—right to the edge. This maximises the A part of the chip, and minimizes the B part of the chip. If the B part is small enough, then the compensation for vertical misalignment can be incorporated on the printhead, and therefore the printhead appears to SoPEC as if it was a single typeA chip. This only makes sense if the B part is minimized since printhead real-estate is more expensive at 0.35 microns rather than on SoPEC at 0.18 microns. The arrangement is shown in FIG. 77.
Note that since the compensation is accomplished on the printhead, the direction of paper movement is fixed with respect to the printhead. This is because the printhead is keeping a history of the data to apply at a later time and is only required to keep the small amount of data from the B part of the printhead rather than the A part.
Within reason, some of the various linking methods can be combined. For example, we may have a mild slope of 5 over the printhead, plus an on-chip compensation for a further 2 lines for a total of 7 lines between type A chips. The mild slope of 5 allows for a 1 in 128 per half color (a reasonable bandwidth increase), and the remaining 2 lines are compensated for in the printheads so do not impact bandwidth at all.
However we can assume that some combinations make less sense. For example, we do not expect to see an A-B chip with a mild slope.
SoPEC also caters for printheads and printhead modules that have redundant nozzle rows. The idea is that for one print line, we fire from nozzles in row x, in the next print line we fire from the nozzles in row y, and the next print line we fire from row x again etc. Thus, if there are any defective nozzles in a given row, the visual effect is halved since we only print every second line from that row of nozzles. This kind of redundancy requires SoPEC to generate data for different physical lines instead of consecutive lines, and also requires additional dot line storage to cater for the redundant rows of nozzles.
Redundancy can be present on a per-color basis. For example, K may have redundant nozzles, but C, M, and Y have no redundancy.
In the preferred form, we are concerned with redundant row pairs, i.e. rows 0+1 always print odd and even dots of the same colour, so redundancy would require say rows 0+1 to alternate with rows 2+3.
To enable alternating between two redundant rows (for example), two additional registers REDUNDANT_ROWS—0[7:0] and REDUNDANT_ROWS—1 [7:0] are provided at addresses 8 and 9. These are protected registers, defaulting to 0x00. Each register contains the following fields:
Bits [2:0]—RowPairA (000 means rows 0+1, 001 means rows 2+3 etc)
Bits [5:3]—RowPairB (000 means rows 0+1, 001 means rows 2+3 etc)
Bit [6]—toggleAB (0 means loadA/fireB, 1 means loadB/fireA)
Bit [7]—valid (0 means ignore the register).
The toggle bit changes state on every FIRE command; SoPEC needs to clear this bit at the start of a page.
The operation for redundant row printing would use similar mechanism to those used when printing less than 5 colours:

    
    
        with toggleAB=0, the RowPairA rows would be loaded in the DATA_NEXT sequence, but the RowPairB rows would be skipped. The TDC FIFO would insert dummy data for the RowPairB rows. The RowPairA rows would not be fired, while the RowPairB rows would be fired.
        with toggleAB=1, the RowPairB rows would be loaded in the DATA_NEXT sequence, but the RowPairA rows would be skipped. The TDC FIFO would insert dummy data for the RowPairA rows. The RowPairB rows would not be fired, while the RowPairA rows would be fired.
    
    


In other embodiments, one or more redundant rows can also be used to implement per-nozzle replacement in the case of one or more dead nozzles. In this case, the nozzles in the redundant row only print dots for positions where a nozzle in the main row is defective. This may mean that only a relatively small numbers of nozzles in the redundant row ever print, but this setup has the advantage that two failed printhead modules (ie, printhead modules with one or more defective nozzles) can be used, perhaps mounted alongside each other on the one printhead, to provide gap-free printing. Of course, if this is to work correctly, it is important to select printhead modules that have different defective nozzles, so that the operative nozzles in each printhead module can compensate for the dead nozzle or nozzles in the other.
Whilst probably of questionable commercial usefulness, it is also possible to have more than one additional row for redundancy per color. It is also possible that only some rows have redundant equivalents. For example, black might have a redundant row due to its high visibility on white paper, whereas yellow might be a less likely candidate since a defective yellow nozzle is much less likely to produce a visually objectionable result.
To accomplish the various printhead requirements, the DWU specification must be updated. The changes to the DWU are minor and basically result in a simplification of the unit.
The preferred data skew block copes with a maximum skew of 24 dots by the use of 12 12-bit shift registers (one shift register per half-color). This can be improved where desired; to cope with a 64 dot skew (i.e. 12 32-bit shift registers), for example.
The DWU currently has an ability to write data in an increasing sense (ascending addresses) or in a decreasing sense (descending addresses). So for example, registers such as ColorLineSense specify direction for a particular half-color.
The DWU now only needs to deal with increasing sense only.
To accomplish the various printhead requirements, the LLU specification must be updated. The LLU needs to provide data for up to eleven printhead segments. It will read this data out of fifos written by the DWU, one fifo per half-color.
The PHI needs to send data out over 6 data lines, where each data line may be connected to up to two segments. When printing A4 portrait, there will be 11 segments. This means five of the datalines will have two segments connected and one will have a single segment connected. (I say ‘one’ and not ‘the last’, since the singly used line may go to either end, or indeed into the middle of the page.) In a dual SoPEC system, one of the SoPECs will be connected to 5 segments, while the other is connected to 6 segments.
Focusing for a moment on the single SoPEC case. SoPEC maintains a data generation rate of 6 bpc throughout the data calculation path. If all six data lines broadcast for the entire duration of a line, then each would need to sustain 1 bpc to match SoPEC's internal processing rate. However, since there are eleven segments and six data lines, one of the lines has only a single segment attached. This dataline receives only half as much data during each print line as the other datalines. So if the broadcast rate on a line is 1 bpc, then we can only output at a sustained rate of 5.5 bpc, thus not matching the internal generation rate. These lines therefore need an output rate of at least 6/5.5 bpc. However, from an earlier version of the plan for the PHI and printheads the dataline is set to transport data at 6/5 bpc, which is also a convenient clock to generate and thus has been retained.
So, the datalines carry over one bit per cycle each. While their bandwidth is slightly more than is needed, the bandwidth needed is still slightly over 1 bpc, and whatever prepares the data for them must produce the data at over 1 bpc. To this end the LLU will target generating data at 2 bpc for each data line.
The LLU will have six data generators. Each data generator will produce the data from either a single segment, or two segments. In those cases where a generator is servicing multiple segments the data for one entire segment is generated before the next segment is generated. Each data generator will have a basic data production rate of 2 bpc, as discussed above. The data generators need to cater to variable segment width. The data generators will also need to cater for the full range of printhead designs currently considered plausible. Dot data is generated and sent in increasing order.
The generators need to be able to cope with segments being vertically offset relative to each other. This could be due to poor placement and assembly techniques, or due to each printhead being placed slightly above or below the previous printhead.
They need to be able to cope with the segments being placed at mild slopes. The slopes being discussed and thus planned for are on the order of 5-10 lines across the width of the printhead.
It is necessary to cope with printhead that have a single internal step of 3-10 lines thus avoiding the need for continuous slope. To solve this we will reuse the mild sloping facility, but allow the distance stepped back to be arbitrary, thus it would be several steps of one line in most mild sloping arrangements and one step of several lines in a single step printhead.
SoPEC should cope with a broad range of printhead sizes. It is likely that the printheads used will be 1280 dots across. Note this is 640 dots/nozzles per half color.
A dot generator will process zero or one or two segments, based on a two bit configuration. When processing a segment it will process the twelve half colors in order, color zero even first, then color zero odd, then color 1 even, etc. The LLU will know how long a segments is, and we will assume all segments are the same length.
To process a color of a segment the generator will need to load the correct word from dram. Each color will have a current base address, which is a pointer into the dot fifo for that color. Each segment has an address offset, which is added to the base address for the current color to find the first word of that colour. For each generator we maintain a current address value, which is operated on to determine the location future reads occur from for that segment. Each segment also has a start bit index associated with it that tells it where in the first word it should start reading data from.
A dot generator will hold a current 256 bit word it is operating on. It maintains a current index into that word. This bit index is maintained for the duration of one color (for one segment), it is incremented whenever data is produced and reset to the segment specified value when a new color is started. 2 bits of data are produced for the PHI each cycle (subject to being ready and handshaking with the PHI).
From the start of the segment each generator maintains a count, which counts the number of bits produced from the current line. The counter is loaded from a start-count value (from a table indexed by the half-color being processed) that is usually set to 0, but in the case of the A-B printhead, may be set to some other non-zero value. The LLU has a slope span value, which indicates how many dots may be produced before a change of line needs to occur. When this many dots have been produced by a dot generator, it will load a new data word and load 0 into the slope counter. The new word may be found by adding a dram address offset value held by the LLU. This value indicates the relative location of the new word; the same value serves for all segment and all colours. When the new word is loaded, the process continues from the current bit index, if bits 62 and 63 had just been read from the old word (prior to slope induced change) then bits 64 and 65 would be used from the newly loaded word.
When the current index reaches the end of the 256 bits current data word, a new word also needs to be loaded. The address for this value can be found by adding one to the current address.
It is possible that the slope counter and the bit index counter will force a read at the same time. In this case the address may be found by adding the slope read offset and one to the current address.
Observe that if a single handshaking is use between the dot generators and the PHI then the slope counter as used above is identical between all 6 generators, i.e. it will hold the same counts and indicate loads at the same times. So a single slope counter can be used. However the read index differs for each generator (since there is a segment configured start value. This means that when a generator encounters a 256-bit boundary in the data will also vary from generator to generator.
After all of the generators have calculated data for all of their segments the LLU should advance a line. This involves signalling the consumption to the DWU, and incrementing all the base address pointers for each color. This increment will generally be done by adding an address offset the size of a line of data. However, to support a possible redundancy model for the printheads, we may need to get alternate lines from different offsets in the fifo. That is, we may print alternate lines on the page from different sets of nozzles in the print head. This is presented as only a single line of nozzles to the PHI and LLU, but the offset of that line with respect to the leading edge of the printhead changes for alternating line. To support this incrementing the LLU stores two address offsets. These offsets are applied on alternate lines. In the normal case both these offsets will simply be programmed to the same value, which will equate to the line size.
The LLU allows the current base addresses for each color to be writeable by the CPU. These registers will then be set to point to appropriate locations with respect to the starting location used by the DWU, and the design of the printhead in question.
Each data generator needs

    
    
        A 2 bit description indicating how many segments it is dealing with.
        Each segment (allowing for 12) requires:
        A bit index (2 bit aligned)
        A dram address offset. (indicates the relative location of the first address to be loaded to the current base address for that color
    
    


Each page/printhead configuration requires:

    
    
        segment width (from the perspective of half colors so eg 640, not 1280)
        slope span (dots counted before stepping)
        start count [x12] (loaded into the slope counter at the start of the segment), typically 0
        slope step dram offset (distance to new word when a slope step occurs)
        current color base address [x12] (writeable work registers)
        line dram offset [x2] (address offset for current color base address for each alternating line)

The following current registers remain:

        Reset
        Go
        FifoReadThreshold,
        FillLevel (work reg)
    
    


Note each generator is specifically associated with two entries in the segment description tables. (So generator 0->0&1, 1->2&3, etc.)
The 2 bits indicating how many segments can be a counter, or just a mask. The latter may contribute to load balancing in some cases.
Data generation involves

    
    
        a current nozzle count
        a current slope count
        a current data word.
        a current index.
        a current segment (of the two to choose from)
        future data words, pre-loaded by some means.
    
    


Firstly a word on bandwidth. The old LLU needed to load the full line of data once, so it needed to process at the same basic rate as the rest of SoPEC, that is 6 bpc. The new LLU loads data based on individual colors for individual segments. A segment probably has 640 nozzles in it. At 256 bits per read, this is typically three reads. However obviously not all of what is read is used. At best we use all of two 256-bit reads, and 128 bits of a third read. This results in a 6/5 wastage. So instead of 6 bpc will would need to average 7.2 bpc over the line. If implemented, mild sloping would make this worse.
Dram reads are not instantaneous. As a result, the next word to be used by a generators should attempt to be loaded in advance. How do we do this?
Consider a state the generator may be in. Say it has the address of the last word we loaded. It has the current index, into that word, as well as the current count versus the segment width and the current count used to handle sloping. By inspecting these variables we can readily determine if the next word to be read for a line we are generating will be read because the slope count was reached or a 256-bit boundary was reached by the index, or both, or because the end of the segment was reached. Since we can make that determination, it is simple to calculate now the next word needed, instead of waiting until it is actually needed. Note with the possibility that the end of the segment will be reached before, or at, either slope or 256-bit effect, in which case the next read in based on the next color (or the next segment).
If that were all we did, it would facilitate double buffering, because whenever we loaded 256 bit data value into the generator we can deduce from the state at that time the next location to read from and start loading it.
Given the potentially high bandwidth requirements for this block it is likely that a significant over-allocation of DIU slots would be needed to ensure timely delivery. This can be avoided by using more buffering as is done for the CFU.
On this topic, if the number of slots allocated is sufficiently high, it may be required that the LLU be able to access every second slot in a particular programming of the DIU. For this to occur, it needs to be able to lodge its next request before it has completed processing the prior request. i.e. after the ack it must be able to request instead of waiting for all the valids like the rest of the PEP units do.
Consider having done the advance load as described above. Since we know why we did the load, it is a simple matter to calculate the new index and slope count and dot count (vs printhead width) that would coincide with it being used. If we calculate these now and store them separately to the ones being used directly by the data generator, then we can use them to calculate the next word again. And continue doing this until we ran out of buffer allocation, at which point we could hold these values until the buffer was free.
Thus if a certain size buffer were allocated to each data generator, it would be possible for it to fill it up with advance reads, and maintain it in that state if enough bandwidth was allocated.
One point not yet considered is the end-of-line. When the lookahead state says we have finished a color we can move to the next, and when it says we have finished the first of two segments, we can move to the next. But when we finished reading the last data of our last segment (whether two or one) we need to wait for the line based values to update before we can continue reading. This could be done after the last read, or before the first read which ever is easier to recognize. So, when the read ahead for a generator realises it needs to start a new line, it should set a bit. When all the non-idle generators have reached this start then the line advance actions take place. These include updating the color base address pointers, and pulsing the DWU.
The above implies a fifo for each generator, of (3−4)×256 bits, and this may be a reasonable solution. It may in fact be smaller to have the advance data read into a common storage area, such as 1×6×256 bit for the generators, and 12×256 bit for the storage area for example.
The PHI has six input data lines and it needs to have a local buffer for this data. The data arrives at 2 bits per cycle, needs to be stored in multiples of 8 bits for exporting, and will need to buffer at least a few of these bytes to assist the LLU, by making its continuous supply constraints much weaker.
The PHI accepts data from the LLU, and transmits the data to the printheads. Each printhead is constructed from a number of printhead segments. There are six transmission lines, each of which can be connected to two printhead segments, so up to 12 segments may be addressed. However, for A4 printing, only 11 segments are needed, so in a single SOPEC system, 11 segments will be connected. In a dual SOPEC system, each SOPEC will normally be connect to 5 or 6 segments. However, the PHI should cater for any arrangement of segments off its data lines.
Each data line performs 8b10b encoding. When transmitting data, this converts 8 bits of data to a 10 bit symbol for transmission. The encoding also support a number of Control characters, so the symbol to be sent is specified by a control bit and 8 data bits. When processing dot data, the control bit can be inferred to be zero. However, when sending command strings or passing on CPU instructions or writes to the printhead, the PHI will need to be given 9 bit values, allowing it to determine what to do with them.
The PHI accepts six 2-bit data lines from the LLU. These data lines can all run off the same enable and if so the PHI will only need to produce a single ready signal (or which fine grained protocol is selected). The PHI collects the 2-bit values from each line, and compiles them into 8-bit values for each line. These 8 bit values are store in a short fifo, and eventually fed to the encoder for transmission to printheads. There is a fixed mapping between the input lines and the output lines. The line are label 0 to 5 and they address segments 0 to 11. (0->[0,1] and 1->[2,3]).
The connection requirements of the printheads are as follows. Each printhead has 1 LVDS clk input, 1 LVDS data input, 1 RstL input and one Data out line. The data out lines will combined to a single input back into the SOPEC (probably via the GPIO). The RstL needs to be driven by the board, so the printhead reset on power-up, but should also be drivable by SOPEC (thus supporting differentiation for the printheads, this would also be handled by GPIOs, and may require 2 of them.
The data is transmitted to each printhead segment in a specified order. If more than one segment is connected to a given data line, then the entire data for one segment will be transmitted, then the data for the other segment.
For a particular segment, a line consists of a series of nozzle rows. These consist of a control sequence to start each color, followed by the data for that row of nozzles. This will typically be 80 bytes. The PHI is not told by the LLU when a row has ended, or when a line has ended, it maintains a count of the data from the LLU and compares it to a length register. If the LLU does not send used colors, the PHI also needs to know which colors aren't used, so it can respond appropriately. To avoid padding issues the LLU will always be programmed to provide a segment width that is a multiple of 8 bits. After sending all of the lines, the PHI will wait for a line sync pulse (from the GPIO) and, when it arrives, send a line sync to all of the printheads. Line syncs handling has changed from PEC1 and will be described further below. It is possible that in addition to this the PHI may be required to tell the printhead the line sync period, to assist it in firing nozzles at the correct rate.
To write to a particular printhead the PHI needs to write the message over the correct line, and address it to the correct target segment on that line. Each line only supports two segments. They can be addressed separately or a broadcast address can be used to address them both.
The line sync and if needed the period reporting portion of each line can be broadcast to every printhead, so broadcast address on every active line. The nozzle data portion needs to be line specific.
Apart from these line related messages, SOPEC also needs to send other commands to the printheads. These will be register read and write commands. The PHI needs to send these to specific segments or broadcast them, selected on a case by case basis. This is done by providing a data path from the CPU to the printheads via the PHI. The PHI holds a command stream the CPU has written, and sends these out over the data lines. These commands are inserted into the nozzle data streams being produced by the PHI, or into the gap between line syncs and the first nozzle line start. Each command terminates with a resume nozzle data instruction.
CPU instructions are inserted into the dot data stream to the printhead. Sometimes these instructions will be for particular printheads, and thus go out over single data line. If the LLU has a single handshaking line then the benefit of stalling only on will be limited to the depth of the fifo of data coming from the LLU. However there if a number of short commands are sent to different printheads they could effectively mask each other by taking turns to load the fifo corresponding to that segment. In some cases, the benefit in time may not warrant the additional complexity, since with single handshaking and good cross segment synchronisation, all the fifo logic can be simplified and such register writes are unlikely to be numerous. If there is multiple handshaking with the LLU, then stalling a single line while the CPU borrows it is simple and a good idea.
The data is sent via LVDS lines to the printhead. The data is 8b10b encoded to include lots of edges, to assist in sampling the data at the correct point. The line requires continuous supply of symbols, so when not sending data the PHI must send Idle commands. Additionally the line is scrambled using a self-synchronising scrambler. This is to reduce emissions when broadcast long sequences of identical data, as would be the case when idling between lines. See printhead doc for more info.
It is possible that when a line sync pulse arrives at the PHI that not all the data has finished being sent to the printheads. If the PHI were to forward this signal on then it would result in an incorrect print of that line, which is an error condition. This would indicate a buffer underflow in PEC1. However, in SoPEC the printhead can only receive line sync signals from the SOPEC providing them data. Thus it is possible that the PHI could delay in sending the line sync pulse until it had finished providing data to the printheads. The effect of this would be a line that is printed very slightly after where it should be printed. In a single SOPEC system the this effect would probably not be noticeable, since all printhead would have undergone the same delay. In a multi-SoPEC system delays would cause a difference in the location of the lines, if the delay was great this may be noticeable. So, rather than entering an error state when a line sync arrive prior to sending the line, we will simply record its arrival and send it as soon as possible. If a single line sync is early (with respect to data processing completing) than it will be sent out with a delay, however it is likely the next line sync will arrive early as well. If the reason for this is mechanical, such as the paper is moving too fast, then it is conceivable that a line sync may arrive at a point in which a line sync is currently pending, so we would have two pending.
Whether or not this is an error condition may be printer specific, so rather than forcing it to be an error condition, the PHI will allow a substantial number of pending line syncs. To assist in making sure no error condition has arrived in a specific system, the PHI will be configured to raise an interrupt when the number pending exceeds a programmed value. The PHI continues as normal, handling the pending line sync as before, it is up to the CPU to deal with the possibility this is an error case. This means a system may be programmed to notice a single line sync that is only a few cycles early, or to remain unaware of being several lines behind where it is supposed to be. The register counting the number of pending line syncs should be 10+ bits and should saturate if incremented past that. Given that line syncs aren't necessarily performing any synchronisation it may be preferable to rename them, perhaps line fire.
As in PEC1 there is a need to set a limiting speed. This could be done at the generation point, but since motor control may be a share responsibility with the OEM, it is safer to place a limiting factor in the PHI. Consequently the PHI will have a register which is the minimum time allowed between it sending line syncs. If this time has not expire when a line sync would have otherwise been sent, then the line remains pending, as above, until the minimum period has passed.
The printhead will support a small range of activities. Most likely these include register reads and writes and line fire actions. The encoding scheme being used between the PHI and the printhead sends 10 bits symbols, which decode to either 8 bit data values or to a small number of non-data symbols. The symbols can be used to form command sequences. For example, a 16-bit register write might take the form of <WRITE SYMBOL><data reg_addr><data value1><data value2>. More generally, a command sequence will be considered to be a string of symbols and data of fixed length, which starts with a non-data symbol and which has a known effect on the printhead. This definition covers write, reads, line syncs, idle indicators, etc.
Unfortunately there are a lot of symbols and data to be sent in a typical page. There is a trade-off that can be made between the lengths of command sequences and their resistance to isolated bit errors. Clearly, resisting isolated bit errors in the communications link is a good thing, but reducing overhead sent with each line is also a good thing. Since noise data for this line is difficult to guess in advance, and the tolerance for print failure may vary from system to system, as will the tolerance for communication overhead, the PHI will try to approach it requirements in a very general way.
Rather than defining at this point the specific content and structure of the command sequences the printhead will accept, instead we will define the general nature, and the specific purpose of each command that the PHI needs to know about.
The PHI has a bit mask of active segments. It processes the data for the line in two halves: the even segments and then the odd segments. If none of the bits are set for a particular half, then it is skipped.
Processing of segment data involves collecting data from the LLU, collating it, and passing through the encoder, wrapped in appropriate command sequences. If the PHI was required to transmit register addresses of each nozzle line, prior to sending the data, then it would need either storage for twenty four command strings (one for each nozzle row on each segment for a wire), or it would need to be able to calculate the string to send, which would require setting that protocol exactly. Instead, printheads will accept a “start of next nozzle data” command sequence, which instruct the printhead that the following bytes are data for the next nozzle row. This command sequence needs to be printhead specific, so only one of the two printheads on any particular line will start listen for nozzle data. Thus to send a line's worth of data to a particular segment one needs to, for each color in the printhead, send a StartNextNozzleRow string followed by SegmentWidth bytes of data. When sending nozzle data, if the supply of data fails, the IDLE command sequence should be inserted. If necessary this can be inserted many times. After sending all of the data to one segment, data is then sent to the other segment. After all the nozzle data is sent to both printhead the PHI should issue IDLE command sequences until it receives a line sync pulse. At this point it should send the LineSync command sequence and start the next line.
The PHI has six data out lines. Each of these needs a fifo. To avoid having six separate fifo management circuits, the PHI will process the data for each line in synch with the other lines. To allow this the same number of symbols must be placed into each fifo at a time. For the nozzle data this is managed by having the PHI unaware of which segments actually exist, it only needs to know if any have two segments. If any have two segments, then it produces two segments worth of data onto every active line. If adding command data from the CPU to a specific fifo then we insert Idle command sequences into each of the other fifos so that an equal number of byte have been sent. It is likely that the IDLE command sequence will be a single symbol, if it isn't then this would require that all CPU command sequences were a multiple of the length of the IDLE sequence. This guarantee has been given by the printhead designers.
The PHI may need to tell the printheads how long the line syncs are. It is possible that the printheads will determine this for themselves, this would involve counting the time since the last Isync. This would make it difficult to get the first line correct on a page and require that the first line be all zeroes, or otherwise tolerant of being only partially fired.
Other options include:
PHI calculated and transmits a period with each line sync.
the PCU calculates a period and writes it to the printheads occasionally.
the line fire command includes a line sync period (again written by the CPU or perhaps calculated by the PHI.
A linking printhead is constructed from linking printhead ICs, placed on a substrate containing ink supply holes. An A4 pagewidth printer used 11 linking printhead ICs. Each printhead is placed on the substrate with reference to positioning fidicuals on the substrate.
FIG. 78 shows the arrangement of the printhead ICs (also known as segments) on a printhead. The join between two ICs is shown in detail. The left-most nozzles on each row are dropped by 10 line-pitches, to allow continuous printing across the join. FIG. 78 also introduces some naming and co-ordinate conventions used throughout this document.
FIG. 78 shows the anticipated first generation linking printhead nozzle arrangements, with 10 nozzle rows supporting five colours. The SoPEC compensation mechanisms are general enough to cover other nozzle arrangements.
Printheads ICs may be misplaced relative to their ideal position. This misplacement may include any combination of:

    
    
        x offset
        y offset
        yaw (rotation around z)
        pitch (rotation around y)
        roll (rotation around z)
    
    


In some cases, the best visual results are achieved by considering relative misplacement between adjacent ICs, rather than absolute misplacement from the substrate. There are some practical limits to misplacement, in that a gross misplacement will stop the ink from flowing through the substrate to the ink channels on the chip.
Correcting for misplacement obviously requires the misplacement to be measured. In general this may be achieved directly by inspection of the printhead after assembly, or indirectly by scanning or examining a printed test pattern.
SoPEC can compensate for misplacement of linking chips in the X-direction, but only snapped to the nearest dot. That is, a misplacement error of less than 0.5 dot-pitches or 7.9375 microns is not compensated for, a misplacement more that 0.5 dot-pitches but less than 1.5 dot-pitches is treated as a misplacement of 1 dot-pitch, etc.
Uncompensated X misplacement can result in three effects:

    
    
        printed dots shifted from their correct position for the entire misplaced segment
        missing dots in the overlap region between segments.
        duplicated dots in the overlap region between segments.

SoPEC can correct for each of these three effects.

    
    


Correction for overall position in X. In preparing line data to be printed, SoPEC buffers in memory the dot data for a number of lines of the image to be printed. Compensation for misplacement generally involves changing the pattern in which this dot data is passed to the printhead ICs.
SoPEC uses separate buffers for the even and odd dots of each colour on each line, since they are printed by different printhead rows. So SoPEC's view of a line at this stage is as (up to) 12 rows of dots, rather than (up to) 6 colours. Nominally, the even dots for a line are printed by the lower of the two rows for that colour on the printhead, and the odd dots are printed by the upper row (see FIG. 78). For the current linking printhead IC, there are 640 nozzles in row. Each row buffer for the full printhead would contain 640×11 dots per line to be printed, plus some padding if required.
In preparing the image, SoPEC can be programmed in the DWU module to precompensate for the fact that each row on the printhead IC is shifted left with respect to the row above. In this way the leftmost dot printed by each row for a colour is the same offset from the start of a row buffer. In fact the programming can support arbitrary shapes for the printhead IC.
SoPEC has independent registers in the LLU module for each segment that determine which dot of the prepared image is sent to the left-most nozzle of that segment. Up to 12 segments are supported. With no misplacement, SoPEC could be programmed to pass dots 0 to 639 in a row to segment 0, dots 640 to 1279 in a row to segment 1, etc.
If segment 1 was misplaced by 2 dot-pitches to the right, SoPEC could be adjusted to pass to dots 641 to 1280 of each row to segment 1 (remembering that each row of data consists entirely of either odd dots or even dots from a line, and that dot 1 on a row is printed two dot positions away from dot 0). This means the dots are printed in the correct position overall. This adjustment is based on the absolute placement of each printhead IC. Dot 640 is not printed at all, since there is no nozzle in that position on the printhead.
A misplacement of an odd number of dot-pitches is more problematic, because it means that the odd dots from the line now need to be printed by the lower row of a colour pair, and the even dots by the upper row of a colour pair on the printhead segment. Further, swapping the odd and even buffers interferes with the precompensation. This results in the position of the first dot to be sent to a segment being different for odd and even rows of the segment. SoPEC addresses this by having independent registers in the LLU to specify the first dot for the odd and even rows of each segment, i.e. 2×12 registers. A further register bit determines whether dot data for odd and even rows should be swapped on a segment by segment basis.
Correcting for duplicate and missing dots. FIG. 79 shows the detailed alignment of dots at the join between two printhead ICs, for various cases of misplacement, for a single colour.
The effects at the join depend on the relative misplacement of the two segments. In the ideal case with no misplacement, the last 3 nozzles of upper row of the segment N interleave with the first three nozzles of the lower row of segment N+1, giving a single nozzle (and so a single printed dot) at each dot-pitch.
When segment N+1 is misplaced to the right relative to segment N (a positive relative offset in X), there are some dot positions without a nozzle, i.e. missing dots. For positive offsets of an odd number of dot-pitches, there may also be some dot positions with two nozzles, i.e. duplicated dots. Negative relative offsets in X of segment N+1 with respect to segment N are less likely, since they would usually result in a collision of the printhead ICs, however they are possible in combination with an offset in Y. A negative offset will always cause duplicated dots, and will cause missing dots in some cases. Note that the placement and tolerances can be deliberately skewed to the right in the manufacturing step to avoid negative offsets.
Where two nozzles occupy the same dot position, the corrections will result in SoPEC reading the same dot data from the row buffer for both nozzles. To avoid printing this data twice SoPEC has two registers per segment in the LLU that specify a number (up to 3) of dots to suppress at the start of each row, one register applying to even dot rows, one to odd dot rows.
SoPEC compensates for missing dots by add the missing nozzle position to its dead nozzle map. This tells the dead nozzle compensation logic in the DNC module to distribute the data from that position into the surrounding nozzles, before preparing the row buffers to be printed.
Y Offset. SoPEC can compensate for misplacement of printhead ICs in the Y-direction, but only snapped to the nearest 0.1 of a line. Assuming a line-pitch of 15.875 microns, if an IC is misplaced in Y by 0 microns, SoPEC can print perfectly in Y. If an IC is misplaced by 1.5875 microns in Y, then we can print perfectly. If an IC is misplaced in Y by 3.175 microns, we can print perfectly. But if an IC is misplaced by 3 microns, this is recorded as a misplacement of 3.175 microns (snapping to the nearest 0.1 of a line), and resulting in a Y error of 0.175 microns (most likely an imperceptible error).
Uncompensated Y misplacement results in all the dots for the misplaced segment being printed in the wrong position on the page.
SoPEC's compensation for Y misplacement uses two mechanism, one to address whole line-pitch misplacement, and another to address fractional line-pitch misplacement. These mechanisms can be applied together, to compensate for arbitrary misplacements to the nearest 0.1 of a line.
Compensating for whole line-pitch misplacement. Buffers are used to hold dot data to be printed for each row. These buffers contain dot data for multiple lines of the image to be printed. Due to the physical separation of nozzle rows on a printhead IC, at any time different rows are printing data from different lines of the image.
For a printhead on which all ICs are ideally placed, row 0 of each segment is printing data from the line N of the image, row 1 of each segment is printing data from row N-M of the image etc. where N is the separation of rows 0 and 1 on the printhead. Separate SoPEC registers in the LLU for each row specify the designed row separations on the printhead, so that SoPEC keeps track of the “current” image line being printed by each row.
If one segment is misplaced by one whole line-pitch, SoPEC can compensate by adjusting the line of the image being sent to each row of that segment. This is achieved by adding an extra offset on the row buffer address used for that segment, for each row buffer. This offset causes SoPEC to provide the dot data to each row of that segment from one line further ahead in the image than the dot data provided to the same row on the other segments. For example, when the correctly placed segments are printing line N of an image with row 0, line N-M of the image with row 1, etc, then the misplaced segment is printing line N+1 of the image with row 0, line N−M+1 of the image with row 1, etc.
SoPEC has one register per segment to specify this whole line-pitch offset. The offset can be multiple line-pitches, compensating for multiple lines of misplacement. Note that the offset can only be in the forward direction, corresponding to a negative Y offset. This means the initial setup of SoPEC must be based on the highest (most positive) Y-axis segment placement, and the offsets for other segments calculated from this baseline. Compensating for Y displacement requires extra lines of dot data buffering in SoPEC, equal to the maximum relative Y offset (in line-pitches) between any two segments on the printhead. For each misplaced segment, each line of misplacement requires approximately 640×10 or 6400 extra bits of memory.
Compensation for fractional line-pitch displacement of a segment is achieved by a combination of SoPEC and printhead IC fire logic.
The nozzle rows in the printhead are positioned by design with vertical spacings in line-pitches that have a integer and fractional component. The fractional components are expressed relative to row zero, and are always some multiple of 0.1 of a line-pitch. The rows are fired sequentially in a given order, and the fractional component of the row spacing matches the distance the paper will move between one row firing and the next. FIG. 80 shows the row position and firing order on the current implementation of the printhead IC. Looking at the first two rows, the paper moves by 0.5 of a line-pitch between the row 0 (fired first) and row 1 (fired sixth). is supplied with dot data from a line 3 lines before the data supplied to row 0. This data ends up on the paper exactly 3 line-pitches apart, as required.
If one printhead IC is vertically misplaced by a non-integer number of line-pitches, row 0 of that segment no longer aligns to row 0 of other segments. However, to the nearest 0.1 of a line, there is one row on the misplaced segment that is an integer number of line-pitches away from row 0 of the ideally placed segments. If this row is fired at the same time as row 0 of the other segments, and it is supplied with dot data from the correct line, then its dots will line up with the dots from row 0 of the other segments, to within a 0.1 of a line-pitch. Subsequent rows on the misplaced printhead can then be fired in their usual order, wrapping back to row 0 after row 9. This firing order results in each row firing at the same time as the rows on the other printheads closest to an integer number of line-pitches away.
FIG. 81 shows an example, in which the misplaced segment is offset by 0.3 of a line-pitch. In this case, row 5 of the misplaced segment is exactly 24.0 line-pitches from row 0 of the ideal segment. Therefore row 5 is fired first on the misplaced segment, followed by row 7, 9, 0 etc. as shown. Each row is fired at the same time as the a row on the ideal segment that is an integer number of lines away. This selection of the start row of the firing sequence is controlled by a register in each printhead IC.
SoPEC's role in the compensation for fractional line-pitch misplacement is to supply the correct dot data for each row. Looking at FIG. 362, we can see that to print correct, row 5 on the misplaced printhead needs dot data from a line 24 lines earlier in the image than the data supplied to row 0. On the ideal printhead, row 5 needs dot data from a line 23 lines earlier in the image than the data supplied to row 0. In general, when a non-default start row is used for a segment, some rows for that segment need their data to be offset by one line, relative to the data they would receive for a default start row. SoPEC has a register in LLU for each row of each segment, that specifies whether to apply a one line offset when fetching data for that row of that segment.
Roll (rotation around X). This kind of erroneous rotational displacement means that all the nozzles will end up pointing further up the page in Y or further down the page in Y. The effect is the same as a Y misplacement, except there is a different Y effect for each media thickness (since the amount of misplacement depends on the distance the ink has to travel).
In some cases, it may be that the media thickness makes no effective visual difference to the outcome, and this form of misplacement can simply be incorporated into the Y misplacement compensation. If the media thickness does make a difference which can be characterised, then the Y misplacement programming can be adjusted for each print, based on the media thickness.
It will be appreciated that correction for roll is particularly of interest where more than one printhead module is used to form a printhead, since it is the discontinuities between strips printed by adjacent modules that are most objectionable in this context.
Pitch (rotation around Y). In this rotation, one end of the IC is further into the substrate than the other end. This means that the printing on the page will be dots further apart at the end that is further away from the media (i.e. less optical density), and dots will be closer together at the end that is closest to the media (more optical density) with a linear fade of the effect from one extreme to the other. Whether this produces any kind of visual artifact is unknown, but it is not compensated for in SoPEC.
Yaw (rotation around Z). This kind of erroneous rotational displacement means that the nozzles at one end of a IC will print further down the page in Y than the other end of the IC. There may also be a slight increase in optical density depending on the rotation amount.
SoPEC can compensate for this by providing first order continuity, although not second order continuity in the preferred embodiment. First order continuity (in which the Y position of adjacent line ends is matched) is achieved using the Y offset compensation mechanism, but considering relative rather than absolute misplacement. Second order continuity (in which the slope of the lines in adjacent print modules is at least partially equalised) can be effected by applying a Y offset compensation on a per pixel basis. Whilst one skilled in the art will have little difficulty deriving the timing difference that enables such compensation, SoPEC does not compensate for it and so it is not described here in detail.
FIG. 82 shows an example where printhead IC number 4 is be placed with yaw, is shown in FIG. 82, while all other ICs on the printhead are perfectly placed. The effect of yaw is that the left end of segment 4 of the printhead has an apparent Y offset of −1 line-pitch relative to segment 3, while the right end of segment 4 has an apparent Y offset of 1 line-pitch relative to segment 5.
To provide first-order continuity in this example, the registers on SoPEC would be programmed such that segments 0 to 3 have a Y offset of 0, segment 4 has a Y offset of −1, and segments 5 and above have Y offset of −2. Note that the Y offsets accumulate in this example—even though segment 5 is perfect aligned to segment 3, they have different Y offsets programmed.
It will be appreciated that some compensation is better than none, and it is not necessary in all cases to perfectly correct for roll and/or yaw. Partial compensation may be adequate depending upon the particular application. As with roll, yaw correction is particularly applicable to multi-module printheads, but can also be applied in single module printheads.
The printhead will be designed for 5 colors. At present the intended use is:

    
    
        cyan
        magenta
        yellow
        black
        infra-red
    
    


However the design methodology must be capable of targeting a number other than 5 should the actual number of colors change. If it does change, it would be to 6 (with fixative being added) or to 4 (with infra-red being dropped).
The printhead chip does not assume any particular ordering of the 5 colour channels.
The printhead will contain 1280 nozzles of each color—640 nozzles on one row firing even dots, and 640 nozzles on another row firing odd dots. This means 11 linking printheads are required to assemble an A4/Letter printhead.
However the design methodology must be capable of targeting a number other than 1280 should the actual number of nozzles per color change. Any different length may need to be a multiple of 32 or 64 to allow for ink channel routing.
The printhead will target true 1600 dpi printing. This means ink drops must land on the page separated by a distance of 15.875 microns.
The 15.875 micron inter-dot distance coupled with mems requirements mean that the horizontal distance between two adjacent nozzles on a single row (e.g. firing even dots) will be 31.75 microns.
All 640 dots in an odd or even colour row are exactly aligned vertically. Rows are fired sequentially, so a complete row is fired in small fraction (nominally one tenth) of a line time, with individual nozzle firing distributed within this row time. As a result dots can end up on the paper with a vertical misplacement of up to one tenth of the dot pitch. This is considered acceptable.
The vertical distance between rows is adjusted based on the row firing order. Firing can start with any row, and then follows a fixed rotation. FIG. 83 shows the default row firing order from 1 to 10, starting at the top even row. Rows are separated by an exact number of dot lines, plus a fraction of a dot line corresponding to the distance the paper will move between row firing times. This allows exact dot-on-dot printing for each colour. The starting row can be varied to correct for vertical misalignment between chips, to the nearest 0.1 pixels. SoPEC appropriate delays each row's data to allow for the spacing and firing order
An additional constraint is that the odd and even rows for given colour must be placed close enough together to allow them to share an ink channel. This results in the vertical spacing shown in FIG. 84, where L represents one dot pitch.
Multiple identical printhead chips must be capable of being linked together to form an effectively horizontal assembled printhead.
Although there are several possible internal arrangements, construction and assembly tolerance issues have made an internal arrangement of a dropped triangle (ie a set of rows) of nozzles within a series of rows of nozzles, as shown in FIG. 85. These printheads can be linked together as shown in FIG. 86.
Compensation for the triangle is preferably performed in the printhead, but if the storage requirements are too large, the triangle compensation can occur in SoPEC. However, if the compensation is performed in SoPEC, it is required in the present embodiment that there be an even number of nozzles on each side of the triangle.
It will be appreciated that the triangle disposed adjacent one end of the chip provides the minimum on-printhead storage requirements. However, where storage requirements are less critical, other shapes can be used. For example, the dropped rows can take the form of a trapezoid.
The join between adjacent heads has a 45° angle to the upper and lower chip edges. The joining edge will not be straight, but will have a sawtooth or similar profile. The nominal spacing between tiles is 10 microns (measured perpendicular to the edge). SoPEC can be used to compensate for both horizontal and vertical misalignments of the print heads, at some cost to memory and/or print quality.
Note also that paper movement is fixed for this particular design.
A print rate of 60 A4/Letter pages per minute is possible. The printhead will assume that page length=297 mm (A4 is longest page length) and an inter-page gap of 60 mm or less (current best estimate is more like 15+/−5 mm
This implies a line rate of 22,500 lines per second. Note that if the page gap is not to be considered in page rate calculations, then a 20 KHz line rate is sufficient.
Assuming the page gap is required, the printhead must be capable of receiving the data for an entire line during the line time. i.e. 5 colors □ 1280 dots □ 22,500 lines=144 MHz or better (173 MHz for 6 colours).
An overall requirement is to minimize the number of pins.
Pin count is driven primarily by the number of supply and ground pins for Vpos. There is a lower limit for this number based on average current and electromigration rules. There is also a significant routing area impact from using fewer supply pads.
In summary a 200 nJ ejection energy implies roughly 12.5 W average consumption for 100% ink coverage, or 2.5 W per chip from a 5V supply. This would mandate a minimum of 20 Vpos/Gnd pairs. However increasing this to around 40 pairs might save approximately 100 microns from the chip height, due to easier routing.
At this stage the print head is assuming 40 Vpos/Gnd pairs, plus 11 Vdd (3.3V) pins, plus 6 signal pins, for a total of 97 pins per chip.
At the CMOS level, the ink supply hole for each nozzle is defined by a metal seal ring in the shape of rectangle (with square corners), measuring 11 microns horizontally by 26 microns vertically. The centre of each ink supply hole is directly under the centre of the MEMs nozzle, i.e. the ink supply hole horizontal and vertical spacing is same as corresponding nozzle spacing.
The printhead will most likely be inserted into a print cartridge for user-insertion into the printer, similar to the way a laser-printer toner cartridge is inserted into a laser printer.
In a home/office environment, ESD discharges up to 15 kV may occur during handling. It is not feasible to provide protection against such discharges as part of the chip, so some kind of shielding will be needed during handling.
The printhead chip itself will target MIL-STD-883 class 1 (2 kV human body model), which is appropriate for assembly and test in a an ESD-controlled environment.
There is no specific requirement on EMI at this time, other than to minimize emissions where possible.
2.11 Hot Plug/Unplug
Cartridge (and hence printhead) removal may be required for replacement of the cartridge or because of a paper jam.
There is no requirement on the printhead to withstand a hot plug/unplug situation. This will be taken care of by the cradle and/or cartridge electromechanics. More thought is needed on exactly what supply & signal connection order is required.
The printhead does not have a particular requirement for sequencing of the 3.3V and 5V supplies. However there is a requirement to held reset asserted (low) as power is applied.
Will be supplied to the printhead. There is no requirement for Power-on-Reset circuitry inside the printhead.
Any output pins (typically going to SoPEC) will drive at 3.3VDD+−5%.
The print head CMOS will be verified for operation over a range of −10 C to 110 C.
The print head CMOS will target a lifetime of at least 10 billion ejections per nozzle.
The print head will not contain any circuits for keep-wet, dead nozzle detection or temperature sensing. It does have a declog (“smoke”) mode.
The SRM043 is a CMOS and MEMS integrated chip. The MEMS structures/nozzles can eject ink which has passed through the substrate of the CMOS via small etched holes.
The SRM043 has nozzles arranged to create a accurately placed 1600 dots per inch printout. The SRM043 has 5 colours, 1280 nozzles per colour.
The SRM043 is designed to link to a similar SRM043 with perfect alignment so the printed image has no artifacts across the join between the two chips.
SRM043 contains 10 rows of nozzles, arranged as upper and lower row pairs of 5 different inks. The paired rows share a common ink channel at the back of the die. The nozzles in one of the paired rows are horizontally spaced 2 dot pitches apart, and are offset relative to each other.
1600 dpi has a dot pitch of DP □15.875 □m. The MEMS print nozzle unit cell is 2DP wide by 5DP high (31.75 □m×79.375 □m). To achieve 1600 dpi per colour, 2 horizontal rows of (1280/2) nozzles are placed with a horizontal offset of 5DP (2.5 cells). Vertical offset is 3.5DP between the two rows of the same colour and 10.1DP between rows of different colour. This slope continues between colours and results in a print area which is a trapezoid as shown in FIG. 87.
Within a row, the nozzles are perfectly aligned vertically.
For ink sealing reasons a large area of silicon beyond the end nozzles in each row is required on the base of the die, near where the chip links to the next chip. To do this the first 4*Row#+4−2*(Row# mod 2) nozzles from each row are vertical shifted down DP.
Data for the nozzles in the triangle must be delayed by 10 line times to match the triangle vertical offset. The appropriate number of data bits at the start of each row are put into a FIFO. Data from the FIFO's output is used instead. The rest of the data for the row bypasses the FIFO.
SRM043 consists of a core of 10 rows of 640 MEMS constructed ink ejection nozzles. Around each of these nozzles is a CMOS unit cell.
The basic operation of the SRM043 is to receive dot data for all colours for a single line and fire all nozzles according to that dot data
To minimise peak power, nozzles are not all fired simultaneously, but are spread as evenly as possible over a line time. The firing sequence and nozzle placement are designed taking into account paper movement during a line, so that dots can be optimally placed on the page. Registers allow optimal placement to be achieved for a range of different MEMs firing pulse widths, printing speeds and inter-chip placement errors.
The MEMS device can be modelled as a resistor, that is heated by a pulse applied to the gate of a large PMOS FET.
The profile (firing) pulse has a programmable width which is unique to each ink colour. The magnitude of the pulse is fixed by the external Vpos supply less any voltage drop across the driver FET.
The unit cell contains a flip-flop forming a single stage of a shift register extending the length of each row. These shift registers, one per row, are filled using a register write command in the data stream. Each row may be individually addressed, or a row increment command can be used to step through the rows.
When a FIRE command is received in the data stream, the data in all the shift register flip-flops is transferred to a dot-latch in each of the unit cells, and a fire cycle is started to eject ink from every nozzle that has a 1 in its dot-latch.
The FIRE command will reset the row addressing to the last row. A DATA_NEXT command preceding the first row data will then fill the first row. While the firing/ejection is taking place, the data for the next line may be loaded into the row shift registers.
Due to the mechanism used to handle the falling triangle block of nozzles the following restrictions apply:
The rows must be loaded in the same order between FIRE commands. Any order may be used, but it must be the same each time.
Data must be provided for each row, sufficient to fill the triangle segment.
A fire cycle sequences through all of the nozzles on the chip, firing all of those with a 1 in their dot-latch. The sequence is one row at a time, each row taking 10% of the total fire cycle. Within a row, a programmable value called the column Span is used to control the firing. Each <span>'th nozzle in the row is fired simultaneously, then their immediate left neighbours, repeating <span> times until all nozzles in that row have fired. This is then repeated for each subsequent row, according the row firing order described below. Hence the maximum number of nozzles firing at any one time is 640 divided by <span>.
In the default case, row 0 of the chip is fired first, according to the span pattern. These nozzles will all fired in the first 10% of the line time. Next all nozzles in row 2 will fire in the same pattern, similarly then rows 4, 6 then 8. Immediately following, half way through the line time, row 1 will start firing, followed by rows 3, 5, 7 then 9.
FIG. 91 shows this for the case of Span=2.
The 1/10 line time together with the 10.1DP vertical colour pitch appear on paper as a 10DP line separation. The odd and even same-colour rows physically spaced 3.5DP apart vertically fired half a line time apart results on paper as a 3DP separation.
A modification of the firing order shown in FIG. 92 can be used to assist in the event of vertical misalignment of the printhead when physically mounted into a cartridge. This is termed micro positioning in this document.
FIG. 93 shows in general how the fire pattern is modified to compensate for mounting misalignment of one printhead with respect to its linking partner. The base construction of the printhead separates the row pairs by slightly more than an integer times the dot Pitch to allow for distributing the fire pattern over the line period. This architecture can be exploited to allow micro positioning.
Consider for example the printhead on the right being placed 0.3 dots lower than the reference printhead to the left. The reference printhead if fired with the standard pattern.
This scheme can compensate for printhead placement errors to 1/10 dot pitch accuracy, for arbitrary printhead vertical misalignment.
The VPOSITION register holds the row number to fire first. The printhead performs sub-line placement, the correct line must be loaded by SoPEC.
The width of the pulse that turns a heater on to eject an ink drop is called the profile. The profile is a function of the MEMs characteristics and the ink characteristics. Different profiles might be used for different colours.
Optimal dot placement requires each line to take 10% of the line time. to fire. So, while a row for a colour with a shorter profile could in theory be fired faster than a colour with a longer profile, this is not desirable for dot placement.
To address this, the fire command includes a parameter called the fireperiod. This is the time allocated to fire a single nozzle, irrespective of its profile. For best dot placement, the fireperiod should be chosen to be greater than the longest profile. If a profile is programmed to be longer than a fireperiod, then that nozzle pulse will be extended to match the profile. This extends the line time, it does not affect subsequent profiles. This will degrade dot placement accuracy on paper.
The fireperiod and profiles are measured in wclks. A wclk is a programmable number of 288 Mhz clock periods. The value written to fireperiod and profile registers should be one less than the desired delay in wclks. These registers are all 8 bits wide, so periods from 1 to 256 wclks can be achieved. The Wclk prescaler should be programmed such that the longest profile is between 128 and 255 wclks long. This gives best line time resolution.
The ideal value for column span and fireperiod can be chosen based on the maximum profile and the linetime. The linetime is fixed by the desired printing speed, while the maximum profile depends on ink and MEMs characteristics as described previously.
To ensure than all nozzles are fired within a line time, the following relationship must be obeyed:

# rows*columnspan*fireperiod<linetime

To reduce the peak Vpos current, the column span should be programmed to be the largest value that obeys the above relationship. This means making fireperiod as small as possible, consistent with the requirement that fireperiod be longer than the maximum profile, for optimal dot placement.
As an example, with a 1 uS maximum profile width, 10 rows, and 44 us desired row time a span of 4 yields 4*10*1=40 uS minimum time. A span of 5 would require 50 uS which is too long.
Having chosen the column span, the fireperiod should be adjusted upward from its minimum so that nozzle firing occupies all of the available linetime. In the above example, fireperiod would be set to 44 us/(4*10)=1.1 uS. This will produce a 10% gap between individual profiles, but ensures that dots are accurately placed on the page. Using a fireperiod longer or shorter than the scaled line time will result in inaccurately placed ink dots.
The fireperiod to be used is updated as a parameter to every FIRE command. This is to allow for variation in the linetime, due to changes in paper speed. This is important because a correctly calculated fireperiod is essential for optimal dot placement.
If a FIRE command is received before a fire cycle is complete, the error bit NO_EARLY_ERR is set and the next fire cycle is started immediately. The final column(s) of the previous cycle will not have been fully fired. This can only occur if the new FIRE command is given early than expected, based on the previous fireperiod.
The profile pulse can only be a rectangular pulse. The only controls available are pulse width and how often the nozzle is fired.
A nozzle can be fired rapidly if required by making the column span 1. Control of the data in the whole array is essential to select which nozzle[s] are fired.
Using this technique, a nozzle can be fired for 1/10 of the line period. Data in the row shift registers must be used to control which nozzles are unclogged, and to manage chip peak currents.
It is possible to fire individual nozzles even more rapidly by reducing the profile periods on colours not being cleared, and using a short fireperiod.
The program registers generally require multiple bytes of data. and will not be stable until the write operation is complete. An incomplete write operation (not enough data) will leave the register with an unknown value.
Sensitive registers are write protected to make it more difficult for noise or transmission errors to affect them unintentionally. Writes to protected registers must be immediately preceded with a UNPROTECT command. Unprotected registers can be written at any time. Reads are not protected.
A fire cycle will be terminated early when registers controlling fire parameters are written. Hence these registers should preferably not be written while printing a page.
Readback of the core requires the user to suspend core write operations to the target row for the duration of the row read. There is no ability to directly read the TDC fifo. It may be indirectly read by writing data to the core with the TDC fifo enabled, then reading back the core row. The triangle sized segment at the start of the core row will contain TDC fifo data.
Reads are performed bit serially, using the read_address command to select a register, and the read_next command repeatedly to step through the register bits sequentially from bit 0. While reading, part or all of a register may be read prior to issuing the read done command. Register bits which are currently undefined will read X.
The printhead is little-endian. Bit order is controlled by the 8B/10B encode on write, and is LSB first on read. Byte 0 is the least significant byte and is sent first. Registers are a varying number of bytes deep, ranging from 0 (unprotect) to 80 (any core row.)







TABLE 3







Register Table
















Register Name









Address
Field Name
Readable
Writable
Protected
Suspend Fire
Reset state
Field
Description






ENABLE
y
y
y
y
0
9:0
Enable Profiles to row










‘bit’. If BitN is ‘0’ the










profile signal for the










rowN is disabled, and the










nozzles in this row can










not fire. The row can be










written.



TEST
y
y
y
y
0

Reserved test bits. Write










0. Do not use.



STATUS
y
y
n
n

31:0 
Entire Register



NO_ERRORS




x
0
Low on any error



NO_DISPARITY_ERR




x
1
Low on disparity error



NO_DECODE_ERR




x
2
Low on 8b10b symbol










error



NO_ADDRESS_ERR




x
3
Low on bad write address










pair



NO_SLIP_ERR




x
4
Low on alignment slip










error



NO_UNDER_ERR




x
5
Low on less than 80 bytes










per row



NO_OVER_ERR




x
6
Low on more than 80










bytes per row



NO_EARLY_ERR




x
7
Low on early fire










command, last cycles not










finished










Once asserted by the










event, each bit must be










deasserted by writing 1 to










the specific register bit



DESIGN_ID
y
n
n
n
n
15:8 
Design_ID: status[15:8] =










8′d43



CMOS_VER
y
n
n
n
0x0c
23:16
CMOS Version = 0



MEMS_VER
y
n
n
n
0x91
31:24
MEMS Version = 0



SPAN
y
y
y
y
0x280
[9:0]
Column span



VPOSITION
y
y
y
y
0
[3:0]
Compensate for vertical










printhead misalignment,










see see “Dot Placement,










General case” on page 13.



DEVICE_ID
y
y
y
y
0
1:0
Head Addr: Address of










head, forms bits [7:6] of










addr of commands.










“b00” is the default










device id










“b11” is the broadcast










device id.


5
MAIN
y
y
y
y

5:0
Entire Register



Tristate
y
y
y
y
0
0
if 1, DO is tristate not










open drain.



WCLK
y
y
y
y
001
3:1
Create working clock,










WCLK by dividing the










main 288 MHz MHz










clock, Clk by (x + 1) * 2










000 = 144 MHz (










001 = 72 MHz (default)










010 = 48 MHz










011 = 36 MHz










100 = 28.8 MHz



BYPASS_TDC
y
y
y
y
0
4
Bypass triangle delay










compensator



Powerdown
n
y
y
y
0
6
powers down the chip










when asserted to a very










low power state. Disables










LVDS IO. Assert reset to










exit powerdown.



ld_n
y
n
n
y
1
6
reads state of internal










ld_n fire signal



done_n
y
n
n
y
0
7
reads the state of the










internal done_n bit,










showing whether a fire










cycle is currently










underway.


6
FIRE
y
y
n
n
0
15:0 
Command to trigger the










fire cycles.










ROW_ADDRESS will be










set to 9. A DATA_NEXT










later will write to the first










core row.



FIRE_PERIOD
y
y
n
n
0
15:0 
The data provided is the










number of cycles of










WCLK in a profile










period.










The gap between fire










commands must be at










least 32 Profile periods.










Values between 2 and










0xffff are acceptable.


3
PULSE_PROFILE


y
y

50:0 
Entire Register



PG_WIDTH0
y
y


X
7:0
Profile width for colour 0










(row0, 1)



PG_WIDTH1
y
y


X
15:8 
Profile width for colour 1










(row2, 3)



PG_WIDTH2
y
y


X
23:16
Profile width for colour 2










(row4, 5)



PG_WIDTH3
y
y


X
31:24
Profile width for colour 3










(row6, 7)



PG_WIDTH4
y
y


X
39:32
Profile width for colour 4










(row8, 9)



profile[n]






10 individual row profiles



fireclk






fireclk



PG_DELAYN
y
n


0
49:40




PG_WIDTHN
y
n


0
50 



4
ROW_ADDRESS
y
y
n
n
X
3:0
Current Row for data



ROW_BYTE_CNT






written to the core.










ROW_ADDRESS is










incremented whenever










register DATA_NEXT is










accessed unless no data










has been written to the










core since










ROW_ADDRESS was










last changed.










ROW_ADDRESS will










wrap from 9 to 0 when










incremented, and will










reset to 9.


7
DATA_RESUME
y
y
n
n
X
639:0 
Nozzle data for










ROW_ADDRESS. Data










will not be written to the










core once the row is full.










This is the address to use










if the core is to be read.










Note the TDC_FIFO may










be in series for write, not










for read.


9
DATA_NEXT
n
y
n
n
X
639:0 
Nozzle data for










ROW_ADDRESS. Pre-










increment










ROW_ADDRESS before










the write if the current










row is not empty. This










means two more










DATA_NEXT writes will










not change the current










row address if no data is










provided


0
UNPROTECT
—
—
n
n
—
—
A write to a protected










register is enabled only if










immediately preceeded










by this command This










command has no data..


5
READ_ADDRESS
n
y
n
n
X
4:0
Output bit[0] of the










register addressed by this










register on Do.


6
READ_NEXT
—
—
n
n
—
—
Output the next bit of the










register addressed by










READ_ADDRESS on










Do. This command has










no data.


8
READ_DONE
—
—
n
n
—
—
Tristate Do. This










command has no data.









The printhead should be powered up with RstL low. This ensures that the printhead will not attempt to fire any nozzle due to the unknown state of power up. This will put registers into their default state (usually zero).
RstL may be released after 3 Clk cycles, and IDLE symbols should be send to the printhead.
During these IDLE symbols, the printhead will find the correct delay to correctly sample the Data. Once communication is established, functional registers can be programmed and status flags initialized.
For a multi-drop Data, RstL should be deasserted for one chip at a time, and that chip given a unique DEVICE_ID with a write to that register. The last chip may keep the default DEVICE_ID. After this step all chips can be addressed, either separately or by broadcast as desired.
A broadcast write may be used to set system parameters such as FIRE, PULSE_PROFILE, MAIN and ENABLE.
Data is written to the core one row at a time. Data is written to the row indexed by ROW_ADDRESS, using the data symbols following a write to the DATA_RESUME or DATA_NEXT register. It is also possible to interrupt this data transfer phase with another (not row data) register write. Use DATA_RESUME to continue the data transfer after the interruption is completed.
Only the first 640 bits of data sent to the current row are used, further data is ignored.
In this mode data to the core should be written with the DATA_NEXT command. DATA_RESUME is used if a complete transfer is interrupted. A FIRE command or RstL leaves the ROW_ADDRESS in the correct state for this method to work correctly
In this mode the ROW_ADDRESS is manually set and 80 bytes are provided with the DATA_RESUME write. If this method is used, rows can be filled in any order, but for correct print behaviour, this order must be the same for all lines on a page.
The registers are read by writing their address to the READ_ADDRESS. This will put the least significant bit of the addressed register is output on Do.
Reading an undefined or unreadable register, will result in an unknown value driven on Do.
A write to READ_NEXT will present the next bit of the current addressed register on Do. Advancing past the most significant bit of the current addressed register will result in an unknown value on Do.
A write to READ_DONE is required to finish the read and tristate Do. A read may be terminated before all bits are read. Other commands can be interleaved with READ_NEXT and READ_DONE commands.
Output timing of Do depends heavily on PCB and cabling. The device has a 4 mA output capability, and particularly when open drain mode is used rise time will be limited by board capacitance and externally sourced pullup current. In an application with a 2 mA pullup source and 100 pf stray capacitance, a maximum line bit rate of 150 ns or 6 MHz can be achieved. Hence the protocol allows the application to set the bit rate by issuing READ_NEXT commands. The command consists of 3 symbols at a 28.8 MHz symbol rate. There is also a fixed latency in the chip of 5 symbols or 150 nS.
The bit that is monitored by the read is unregistered. If it changes dynamically, Do will reflect the change. This is useful for monitoring any of the error bits of the STATUS register. Since bit 0 of this register, NO_ERRORS reflects all error conditions, this bit can be watched until an error condition occurs, then the read can be advanced until the source of the error is found. As Do is an open-drain output in normal operation, all devices can be selected simultaneously if desired for this.
Error bits are reset by a write with a 1 in the specific bit position to the STATUS register. An error bit cannot be written to 0.
It will be appreciated by those skilled in the art that the foregoing represents only a preferred embodiment of the present invention. Those skilled in the relevant field will immediately appreciate that the invention can be embodied in many other forms.

## Claims

1. A print engine pipeline subsystem of a printer controller, said subsystem comprising:
a print engine pipeline controller for reading and writing print engine pipeline registers;
a contone decoder unit for expanding JPEG compressed continuous tone (“contone”) layers;
a lossless bi-level decoder for expanding compressed bi-level layers;
a line loader unit for expanding page images for a printhead; and
a printhead interface for sending dot data to the printhead and for providing line synchronization between multiple printer controllers.

2. The print engine pipeline subsystem of claim 1, which includes a halftoner compositor unit for dithering contone layers and compositing the bi-level layers into spot and position tag dots.

3. The print engine pipeline subsystem of claim 2, which includes a contone FIFO unit for providing line buffering between the contone decoder unit and the halftoner compositor unit.

4. The print engine pipeline subsystem of claim 3, which includes a spot FIFO unit for providing line buffering between the lossless bi-level decoder and the halftoner compositor unit.

5. The print engine pipeline subsystem of claim 2, which includes a tag encoder for encoding tag data into a line of tag dots.

6. The print engine pipeline subsystem of claim 5, which includes a tag FIFO unit for providing tag data storage between the tag encoder and the halftoner compositor unit.

7. The print engine pipeline subsystem of claim 1, which includes a dead nozzle compensator for compensating for dead printhead nozzles by color redundancy and error diffusion of dead nozzle data into surrounding data dots.