# Patent

## Title
Drive method of display device, drive unit of display device, program of the drive unit and storage medium thereof, and display device including the drive unit

## Abstract

In one embodiment of the present invention, in the case of dark display on sub-pixels, a sub-frame processing section is disclosed which sets video data for a sub-frame to a value falling within the range for dark display, and increases or decreases video data for a sub-frame so as to control luminance of the sub-pixels. In the case of bright display, the sub-frame processing section sets video data to a value falling within the range for bright display, and increase or decreases video data so as to control luminance of the sub-pixels. A modulation processing section corrects video data of each frame and then outputs corrected video data to the sub-frame processing section. Also, the modulation processing section predicts luminance that the sub-pixels reach at the end of the frame and then stores prediction results for correction and prediction in the subsequent frame. This realizes a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.

## Background
TECHNICAL FIELD
The present invention relates to a drive method of a display device which is capable of improving image quality and brightness in displaying a moving image, a drive unit of a display device, a program of the drive unit and a storage medium thereof, and a display device including the drive unit.
BACKGROUND ART
As described in, for example, the patent documents 1-5 below, there are commonly used display devices which divide a frame for one screen into plural sub frames by time division. According to the documents, the quality of moving images is improved such that impulse-type light emission typified by CRTs (Cathode-Ray Tube) is simulated by a hold-type display device such as a liquid crystal display device by providing a black display or dark display period in one frame period.
Also, as taught by the patent document 6 below, the response speed of a liquid crystal display device is improved by modulating a drive signal in such a way as to emphasize grayscale transition between two frames.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 302289/1994 (Tokukaihei 4-302289 published on Oct. 26, 1994)
[Patent Document 2]
Japanese Unexamined Patent Publication No. 68221/1995 (Tokukaihei 5-68221; published on Mar. 19, 1995)
[Patent Document 3]
Japanese Unexamined Patent Publication No. 2001-281625/2001 (Tokukai 2001-281625; published on Oct. 10, 2001)
[Patent Document 4]
Japanese Unexamined Patent Publication No. 23707/2002 (Tokukai 2002-23707; published on Jan. 25, 2002)
[Patent Document 5]
Japanese Unexamined Patent Publication No. 22061/2003 (Tokukai 2003-22061; published on Jan. 24, 2003)
[Patent Document 6]
Japanese Patent No. 2650479 (issued on Sep. 3, 1997) [Non-Patent Document 1]
Handbook of Color Science; second edition (University of Tokyo Press, published on Jun. 10, 1998)
DISCLOSURE OF INVENTION
Problem to be Solved by the Invention
However, the improvement in the quality of moving images is insufficient in all of the arrangements above. It is therefore required a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.
The present invention has been attained in view of the problem above, and an object of the present invention is to provide a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.
Means for Solving the Problem
In order to solve the above problem, a drive method of a display device according to the present invention is a drive method of a display device, comprising the step of (i) generating predetermined plural sets of output video data supplied to a pixel, in response to each input cycle of inputting input video data to the pixel, the plural sets of output video data being generated for driving the pixel by time division, the drive method further comprising the step of: (ii) prior to or subsequent to the step (i), correcting correction target data which is either the input video data or the plural output video data, and predicting luminance at which the pixel reaches at the end of a drive period of the correction target data, the drive period being a period in which the pixel is driven based on the corrected correction target data, the step (i) including the sub steps of: (I) in case where the input video data indicates luminance lower than a predetermined threshold, setting luminance of at least one of the plural sets of output video data to be at a value within a predetermined luminance range for dark display, and controlling a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing at least one of the remaining sets of output video data; and (II) in case where the input video data indicates luminance higher than the predetermined threshold, setting at least one of the plural sets of output video data to be at a value within a predetermined luminance range for bright display, and controlling a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing at least one of the remaining sets of output video data, the step (ii) including the sub steps of: (III) correcting the correction target data based on a prediction result, among past prediction results, which indicates luminance that the pixel reaches at the beginning of a drive period of the correction target data; and (IV) predicting luminance at the end of the drive period of the correction target data of the present time, at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time.
According to the arrangement above, when the input video data indicates luminance lower than a predetermined threshold (i.e. in the case of dark display), at least one of the plural sets of output video data is set at a value indicating luminance within a predetermined range for dark display (i.e. luminance for dark display), and at least one of the remaining sets of output video data is increased or decreased to control a time integral value of the luminance of the pixel in the periods in which the pixel is driven based on the plural sets of output video data. Therefore, in most cases, the luminance of the pixel in the period (dark display period) in which the pixel is driven based on the output video data indicating luminance for dark display is lower than the luminance in the remaining periods.
On the other hand, when the input video data indicates luminance higher than the predetermined threshold (i.e. in the case of bright display), at least one of said plural sets of output video data is set at a value indicating luminance within a predetermined range for bright display (i.e. luminance for bright display), and one of the remaining sets of output video data is increased or decreased to control a time integral value of the luminance of the pixel in the periods in which the pixel is driven based on said plural sets of output video data. Therefore, in most cases, the luminance of the pixel in the periods other than the period (bright display period) in which the pixel is driven based on the output video data indicating luminance for bright display is lower than the luminance in the bright display period.
As a result, in most cases, it is possible to provide a period in which luminance of the pixel is lower than that of the other periods, at least once in each input cycle. It is therefore possible to improve the quality in moving images displayed on the display device. Also, when bright display is performed, luminance indicated by the input video data increases as luminance of the pixel in the periods other than the bright display period increases. On this account, it is possible to increase a time integral value of the luminance of the pixel in the whole input cycle as compared to a case where dark display is performed at least once in each input cycle. Therefore a display device which can perform brighter display can be realized.
Even if the luminance of the pixel in the periods other than the bright display period is high, the quality in moving images can be improved on condition that the luminance in the bright display period is sufficiently different from the luminance in the periods other than the bright display period. It is therefore possible to improve the quality in moving images in most cases.
In many display devices, the range of viewing angles in which luminance is maintained at an allowable value is widened when the luminance of the pixel is close to the maximum or minimum, as compared to a case where the luminance of the pixel has an intermediate value. This is because, when the luminance is close to the maximum or minimum, the alignment of the liquid crystal molecules is simple and easily correctable on account of a requirement of contrast and because visually suitable results can be easily obtained, and hence a viewing angle at the maximum or minimum (in particular, a part close to the minimum luminance) is selectively assured. On this account, if time-division driving is not performed, a range of viewing angles in which intermediate luminance can be suitably reproduced is narrowed, and problems such as whitish appearance may occur when the display device is viewed at an angle out of the aforesaid range.
According to the arrangement above, in the case of dark display, one of the sets of output video data is set at a value indicating luminance for dark display. It is therefore possible to widen the range of viewing angles in which the luminance of the pixel falls within an allowable range. Similarly, in the case of bright display, one of the sets of output video data is set at a value indicating luminance for bright display. It is therefore possible to widen the range of viewing angles in which the luminance of the pixel falls within an allowable range, in the bright display period. As a result, problems such as whitish appearance can be prevented in comparison with the arrangement in which the time-division driving is not performed, and hence the range of viewing angles can be increased.
In addition, according to the arrangement above, among the past prediction results, the correction target data is corrected based on the prediction result indicating the luminance at which the pixel reaches at the beginning of the drive period of the correction target data. It is therefore possible to increase the response speed of the pixel and increase the types of display devices which can be driven by the aforesaid drive method.
More specifically, when the pixel is driven by time division, the pixel is required to have a faster response speed than a case where no time division is performed. If the response speed of the pixel is sufficient, the luminance of the pixel at the end of the drive period reaches the luminance indicated by the correction target data, even if the correction target data is output without referring to the prediction result. However, if the response speed of the pixel is insufficient, it is difficult to cause the luminance of the pixel at the end to reach the luminance indicated by the correction target data, if the correction target data is output without referring to the prediction result. On this account, the types of display devices that the time division drive unit can drive are limited in comparison with the case where no time division is performed.
In this regard, according to the arrangement above, the correction target data is corrected in accordance with the prediction result. On this account, when, for example, the response speed seems insufficient, a process in accordance with the prediction result, e.g. increase in the response speed of the pixel by emphasizing the grayscale transition, is possible. It is therefore possible to increase the response speed of the pixel.
Moreover, the luminance at the end of the drive period of the correction target data is predicted at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time. With this arrangement, a highly precise prediction can be performed and moving image quality can be improved, as compared to the arrangement with the assumption that the luminance has reached the luminance indicated by the correction target data of the present time.
More specifically, as described previously, in the case of dark display, at least one of the plural sets of output video data is set to luminance for dark display, and in the case of bright display, at least one of the plural sets of output video data is set to luminance for bright display. With this arrangement, it is possible to widen the range of viewing angles of a display device.
However, with this arrangement, grayscale transition to increase luminance and grayscale transition to decrease luminance are likely to be repeated alternately. Then, in a case where a response speed of the pixel is slow, a desired luminance cannot be obtained by emphasis of the grayscale transition. Under such a situation, when grayscale transition is emphasized on the assumption that a desired luminance has been obtained by the grayscale transition of the last time, the grayscale transition is excessively emphasized in a case where there has occurred the repetition. This may causes a pixel with inappropriately increased or decreased luminance. In particular, when luminance of a pixel is inappropriately high, the user is likely to take notice of it and hence the image quality is significantly deteriorated.
On the contrary, according to the arrangement above, prediction with highly precision is possible since the prediction is performed as described above. Thus, it is possible to prevent image quality deterioration caused by excessive emphasis of grayscale transition, to widen the range of viewing angles of a display device, and to improve moving image quality.
As a result, it is possible to provide a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.
In order to solve the above problem, a drive unit of a display device according to the present invention is a drive unit of a display device, comprising generation means for generating predetermined plural sets of output video data supplied to a pixel, in response to each of the input cycles of inputting input video data to the pixel, the plural sets of output video data being generated for driving the pixel by time division, the drive unit further comprising: correction means, provided prior to or subsequent to the generation means, for correcting correction target data which is either the input video data or the plural output video data, and predicting luminance at which the pixel reaches at the end of a drive period of the correction target data, the drive period being a period in which the pixel is driven based on the corrected correction target data, the generation means performing control so as to: (i) in case where the input video data indicates luminance lower than a predetermined threshold, set luminance of at least one of the plural sets of output video data at a value within a predetermined luminance range for dark display, and control a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing at least one of the remaining sets of output video data; and (ii) in case where the input video data indicates luminance higher than the predetermined threshold, set luminance of at least one of the plural sets of output video data at a value within a predetermined luminance range for bright display, and control a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing at least one of the remaining sets of output video data, and the correction means correcting the correction target data based on a prediction result, among past prediction results, which indicates luminance that the pixel reaches at the beginning of a drive period of the correction target data, and predicting luminance at the end of the drive period of the correction target data of the present time, at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time.
In the drive unit of a display device with the arrangement above, being similar to the aforesaid drive method of a display device, in most cases, it is possible to provide a period in which luminance of the pixel is lower than that of the other periods, at least once in each input cycle. It is therefore possible to improve the quality in moving images displayed on the display device. Also, when bright display is performed, luminance indicated by the input video data increases as luminance of the pixel in the periods other than the bright display period increases. On this account, a display device which can perform brighter display can be realized.
As in the case of the aforesaid drive method of a display device, among the past prediction results, the correction target data is corrected based on the prediction result indicating the luminance at which the pixel reaches at the beginning of the drive period of the correction target data. It is therefore possible to increase the response speed of the pixel and increase the types of display devices which can be driven by the aforesaid drive unit.
Moreover, as in the case of the aforesaid drive method of a display device, the luminance at the end of the drive period of the correction target data is predicted at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time. It is therefore possible to predict the luminance at the end of the drive period with higher precision. Accordingly, the properties are improved including image quality and brightness in displaying a moving image on a display device, and viewing angles. This makes it possible to prevent deteriorated image quality caused by excessive emphasis of grayscale transition, and to improve moving image quality, even when grayscale transition to increase luminance and grayscale transition to decrease luminance are repeated alternately.
In addition to the arrangement above, the drive unit may be such that the correction target data is input video data, and the correction means is provided prior to the generation means and predicts, as luminance that the pixel reaches at the end of a drive period of the correction target data, luminance that the pixel reaches at the end of periods in which the pixel is driven based on the plural sets of output video data, which have been generated based on corrected input video data by the generation means. Examples of a circuit for prediction include a circuit which reads out a prediction result corresponding to an actual input value from storage means in which values indicating prediction results corresponding to possible input values are stored in advance.
When the corrected input video data is determined, sets of output video data corresponding to the corrected input video data are determined. When (a) luminance that the pixel reaches at the beginning of periods in which the pixel is driven based on the plural sets of output video data, which have been generated based on the corrected input video data by the generation means, and (b) the sets of output video data are determined, the luminance of the pixel at the end of the drive period is determined.
Therefore, although predicting the luminance at the end of the drive period only once in one input cycle, the correction means can predict luminance at the end of the drive period of the input video data of the present time, without a hitch, at least based on the prediction result indicating the luminance at which the pixel reaches at the beginning of the drive period of the input video data of the present time (drive period of the correction target data) and the input video data of the present time, among the past prediction results. As a result of this, it is possible to reduce an operation speed of the correction means.
Moreover, the correction means may be provided subsequent to the generation means and correct the sets of output video data as the correction target data. According to this arrangement, the sets of output video data are corrected by the correction means. This makes it possible to perform more appropriate correction and further increase a response speed of the pixel.
In addition to the arrangement above, the drive unit may be such that the correction means includes: a correction section which corrects the plural sets of output video data generated in response to each of the input cycles and outputs sets of corrected output video data corresponding to respective divided periods into which the input cycle is divided, the number of the divided periods corresponding to the number of the plural sets of output video data; and a prediction result storage section which stores a prediction result regarding a last divided period among the prediction results, wherein in a case where the correction target data corresponds to a first divided period, the correction section corrects the correction target data based on a prediction result read out from the prediction result storage section, in a case where the correction target data corresponds to a second or subsequent divided period, the correction section predicts the luminance at the beginning of the drive period, based on (a) output video data corresponding to a divided period which is prior to the divided period corresponding to the correction target data and (b) the prediction result stored in the prediction result storage section, and corrects the correction target data according to the prediction result, the correction section predicts the luminance of the pixel at the end of a drive period of the output video data corresponding to the last divided period, based on (A) the output video data corresponding to the last divided period, (B) the output video data corresponding to a divided period which is prior to the divided period corresponding to the output video data (A), and (C) the prediction result stored in the prediction result storage section, and stores the thus obtained prediction result in the prediction result storage section.
According to this arrangement, in correcting output video data corresponding to a second or subsequent divided period, the luminance of the pixel at the beginning of the divided period corresponding to correction target data is predicated based on the correction target data, output video data corresponding to a divided period which is prior to the divided period corresponding to the correction target data, and the prediction result stored in the prediction result storage section, and the correction target data is corrected in such a manner so as to emphasize grayscale transition from a predicted luminance to luminance indicated by the correction target data.
Therefore, it is possible to correct the correction target data, without the need for each time storing in the prediction result storage section results of the prediction of the luminance that the pixel reaches at the end of the divided periods which are directly prior to the divided periods corresponding to the sets of correction target data. As a result, an amount of data of results of the prediction stored in the prediction result storage section in each input cycle can be reduced as compared to a case where the result of prediction in each divided period is each time stored in the prediction result storage section.
As the number of pixels in a display device increases, the number of prediction results which need to be stored in the prediction result storage section increases. This makes it difficult to incorporate the correction means and the prediction result storage section in one integrated circuit. In such a case, data transmissions between the correction means and the prediction result storage section are carried out via signal lines outside the integrated circuit. It is therefore difficult to increase the transmission speed as compared to a case where transmission is performed within the integrated circuit. This requires increase of the number of signal lines and increase of the number of pins of the integrated circuit, to increase the transmission speed, and hence the size of the integrated circuit tends to increase undesirably. On the contrary, according to the above arrangement, it is possible to reduce the amount of data of the prediction results stored in the prediction result storage section in each input cycle. This makes it possible to transmit the prediction results without any problem, even when the prediction result storage section is provided outside the integrated circuit including the correction means, as compared with the arrangement in which the prediction result is stored in the prediction result storage section each time.
In addition to the arrangement above, the drive unit may be such that the pixel is one of a plurality of pixels, in accordance with input video data for each of the pixels, the generation means generates predetermined plural of sets of output video data supplied to each of the pixels, in response to each of the input cycles, the correction means corrects the sets of output video data to be supplied to each of the pixels and stores prediction results corresponding to the respective pixels in the prediction result storage section, the generation means generates, for each of the pixels, the predetermined plural of sets of output video data to be supplied to the each of the pixels in each of the input cycles, and the correction section reads out, for each of the pixels, prediction results regarding the pixel predetermined number of times in each of the input cycles, and based on these prediction results and the sets of output video data, for each of the pixels, at least one process of writing of the prediction result is thinned out from processes of prediction of luminance at the end of the drive period and processes of storing the prediction result, which can be performed plural number of times in each of the input cycles.
In this arrangement, the number of sets of output video data generated in each input cycle is determined in advance, and the number of times the prediction results are read out in each input cycle is equal to the number of sets of output video data. On this account, based on the sets of output video data and the prediction results, it is possible to predict the luminance of the pixel at the end for plural times and store the prediction results. The number of the pixels is plural and the reading process and the generation process are performed for each pixel.
In the arrangement above, at least one process of writing of the prediction result is thinned out among the prediction processes and processes of storing prediction results which can be performed plural times in each input cycle.
Therefore, in comparison with the arrangement of no thin-out, it is possible to elongate the time interval of storing the prediction result of each pixel in the prediction result storage section, and hence the response speed that the prediction result storage section is required to have can be lowered.
An effect can be obtained by thinning out at least one writing process. A greater effect is obtained by reducing, for each pixel, the number of times of writing processes by the correction means to one in each input cycle.
In addition to the arrangement above, the drive unit may be such that the generation means controls the time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data by increasing or decreasing particular output video data which is a particular one of the remaining sets of output video data, and sets the remaining sets of output video data other than the particular output video data at either a value indicating luminance falling within the predetermined range for dark display or a value indicating luminance falling within the range for bright display.
According to this arrangement, among said plural sets of output video data, the sets of video data other than the particular output video data are set either at a value indicating luminance within the predetermined range for dark display or a value indicating luminance within the predetermined range for bright display. On this account, problems such as whitish appearance are further prevented and the range of viewing angles is further increased, as compared to a case where the sets of video data other than the particular output video data are set at values included neither one of the aforesaid ranges.
Also, in addition to the arrangement above, the drive unit may be such that provided that the periods in which the pixel is driven by said plural sets of output video data are divided periods whereas a period constituted by the divided periods and in which the pixel is driven by said plural sets of output video data is a unit period, the generation means selects, as the particular output video data, a set of output video data corresponding to a divided period which is closest to a temporal central position of the unit period, among the divided periods, in a region where luminance indicated by the input video data is lowest, and when luminance indicated by the input video data gradually increases and hence the particular output video data enters the predetermined range for bright display, the generation means sets the set of video data in that divided period at a value falling within the range for bright display, and selects, as new particular output video data, a set of output video data in a divided period which is closest to the temporal central position of the unit period, among the remaining divided periods.
According to the arrangement above, the temporal barycentric position of the luminance of the pixel in the unit period is set at around the temporal central position of the unit period, irrespective of the luminance indicated by the input video data. On this account, the following problem can be prevented: on account of a variation in the temporal barycentric position, needless light or shade, which is not viewed in a still image, appears at the anterior end or the posterior end of a moving image, and hence the quality of moving images is deteriorated. It is therefore possible to improve the quality of moving images.
Also, in addition to the arrangement above, the drive unit may be such that a ratio between the periods in which the pixel is driven based on said plural sets of output video data is set so that a timing to determine which set of output video data is selected as the particular output video data is closer to a timing at which a range of brightness that the pixel can reproduce is equally divided than a timing at which luminance that the pixel can reproduce is equally divided.
According to this arrangement, it is possible to determine which luminance of the output video data is mainly used for controlling the time integral value of the luminance of the pixel in the periods in which the pixel is driven based on said plural sets of output video data, with appropriate brightness. On this account, it is possible to further reduce human-recognizable whitish appearance as compared to a case where the determination is made at a timing to equally dividing a range of luminance, and hence the range of viewing angles is further increased.
The drive unit of a display device may be realized by hardware or by causing a computer to execute a program. More specifically, a program of the present invention causes a computer to operate as the foregoing means provided in any of the aforesaid drive units. A storage medium of the present invention stores this program.
When such a program is executed by a computer, the computer operates as the drive unit of the display device. Therefore, as in the case of the aforesaid drive unit of the display device, it is possible to realize a drive unit of a display device which unit can provide a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.
A display device of the present invention includes: any of the aforesaid drive units; and a display section including pixels driven by the drive unit. In addition to this arrangement, the display device may be arranged so as to further include image receiving means which receives television broadcast and supplies, to the drive unit of the display device, a video signal indicating an image transmitted by the television broadcast, the display section being a liquid crystal display panel, and said display device functions as a liquid crystal television receiver. Further, in addition to the arrangement above, the display device may be arranged such that the display section is a liquid crystal display panel, the drive unit of the display device receives a video signal from outside, and the display device functions as a liquid crystal monitor device which displays an image indicated by the video signal.
The above-arranged display device includes the above drive unit of the display device. Thus, as in the case of the above drive unit of the display device, it is possible to realize a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality.
Effects of the Invention
According to the present invention, with the driving as described above, it is possible to provide a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has better moving image quality. On this account, the present invention can be suitably and widely used as a drive unit of various display devices such as a liquid crystal television receiver and a liquid crystal monitor.



BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 relates to an embodiment of the present invention and is a block diagram showing the substantial part of a signal processing circuit in an image display device.
FIG. 2 is a block diagram showing the substantial part of the image display device.
FIG. 3(a) is a block diagram showing the substantial part of a television receiver provided with the foregoing image display device.
FIG. 3(b) is a block diagram showing the substantial part of a liquid crystal monitor device provided with the foregoing image display device.
FIG. 4 is a circuit diagram showing an example of a pixel in the image display device.
FIG. 5 is a graph showing the difference in luminance between a case where a pixel which is driven in non-time-division fashion is obliquely viewed and a case where that pixel is viewed head-on.
FIG. 6 is a graph showing the difference in luminance between a case where a pixel which is driven in response to a video signal from the signal processing circuit is obliquely viewed and a case where that pixel is viewed head-on.
FIG. 7 shows a comparative example and is a block diagram in which a gamma correction circuit is provided at the stage prior to a modulation processing section in the signal processing circuit.
FIG. 8 shows an example of the modulation processing section in the signal processing circuit of the embodiment and is a block diagram showing the substantial part of the modulation processing section.
FIG. 9 is a graph in which the luminance in the graph of FIG. 6 is converted to brightness.
FIG. 10 illustrates a video signal supplied to the frame memory shown in FIG. 1, and video signals supplied from the frame memory to a first LUT and a second LUT in case where division is carried out at the ratio of 3:1.
FIG. 11 is an explanatory view illustrating timings to turn on scanning signal lines in relation to a first display signal and a second display signal in the present embodiment, in case where a frame is divided into 3:1.
FIG. 12 is a graph showing relations between planned brightness and actual brightness in case where a frame is divided into 3:1.
FIG. 13(a) is an explanatory view illustrating a method of reversing the polarity of an interelectrode voltage in each frame.
FIG. 13(b) is an explanatory view illustrating another method of reversing the polarity of an interelectrode voltage in each frame.
FIG. 14(a) is provided for illustrating the response speed of liquid crystal and is an explanatory view illustrating an example of the variation of a voltage applied to liquid crystal in one frame.
FIG. 14(b) is provided for illustrating the response speed of liquid crystal and is an explanatory view illustrating the variation of an interelectrode voltage in accordance with the response speed of liquid crystal.
FIG. 14(c) is provided for illustrating the response speed of liquid crystal, and is an explanatory view illustrating an interelectrode voltage in case where the response speed of liquid crystal is low.
FIG. 15 is a graph showing the display luminance (relations between planned luminance and actual luminance) of a display panel when sub frame display is carried out by using liquid crystal with low response speed.
FIG. 16(a) is a graph showing the luminance generated in a first sub frame and a second sub frame, when the display luminance is 3⁄4 and 1⁄4 of Lmax.
FIG. 16(b) is a graph showing transition of a liquid crystal voltage in case where the polarity of the voltage (liquid crystal voltage) applied to liquid crystal is changed in each sub frame.
FIG. 17(a) is an explanatory view illustrating a method of reversing the polarity of an interelectrode voltage in each frame.
FIG. 17(b) is an explanatory view illustrating another method of reversing the polarity of an interelectrode voltage in each frame.
FIG. 18(a) is an explanatory view of four sub pixels in a liquid crystal panel and an example of polarities of liquid crystal voltages of the respective sub pixels.
FIG. 18(b) is an explanatory view illustrating a case where the polarities of liquid crystal voltages of the respective sub pixels in FIG. 18(a) are reversed.
FIG. 18(c) is an explanatory view illustrating a case where the polarities of liquid crystal voltages of the respective sub pixels in FIG. 18(b) are reversed.
FIG. 18(d) is an explanatory view illustrating a case where the polarities of liquid crystal voltages of the respective sub pixels in FIG. 18(c) are reversed.
FIG. 19 is a graph showing (i) results (dotted line and full line) of image display by diving a frame into three equal sub frames and (ii) results (dashed line and full line) of normal hold display.
FIG. 20 is a graph showing the transition of a liquid crystal voltage in case where a frame is divided into three and voltage polarity is reversed in each frame.
FIG. 21 is a graph showing the transition of a liquid crystal voltage in case where a frame is divided into three and voltage polarity is reversed in each sub frame.
FIG. 22 is a graph showing relations (actual measurement values of viewing angle grayscale properties) between a signal grayscale (%; luminance grayscale of a display signal) of a signal supplied to the display section and an actual luminance grayscale (%), in a sub frame with no luminance adjustment.
FIG. 23 relates to another embodiment of the present invention and is a block diagram showing the substantial part of a signal processing circuit.
FIG. 24 shows an example of a modulation processing section in the signal processing circuit and is a block diagram showing the substantial part of the modulation processing section.
FIG. 25 is a timing chart showing how the signal processing circuit operates.
FIG. 26 shows another example of the modulation processing section in the signal processing circuit and is a block diagram showing the substantial part of the modulation processing section.
FIG. 27 is a timing chart showing how the signal processing circuit operates.



EXPLANATIONS OF REFERENCE NUMERALS


    1 Image display apparatus (display apparatus)
    2 Pixel array (display section)
    42, 43 LUT (storage means)
    44, 44c Control circuit (generating means)
    31, 31a-31c Modulation processing section (correction means)
    52c-52d Correction processing section (correction means)
    53c-53d Predicted value storage means (correction means)
    51, 51a, 51b, 54 Frame memory (Predicted Value Storage Means)
    VS Video signal source (image receiving means)
    SPIX (1, 1) . . . . Sub-pixel (pixel)


BEST MODE FOR CARRYING OUT THE INVENTION
First Embodiment
The following will describe an embodiment of the present invention with reference to FIGS. 1-8. An image display device of the present embodiment is a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has improved moving image quality. The image display device of the present embodiment may be suitably used as, for example, an image display device of a television receiver. Examples of television broadcasts that the television receiver can receive include terrestrial television broadcast, satellite broadcasts such as BS (Broadcasting Satellite) digital broadcast and CS (Communication Satellite) digital broadcast, and cable television broadcast.
The overall arrangement of the image display device of the present embedment will be briefed, before discussing a signal processing circuit for performing data processing for making a brighter display, realizing a wider range of viewing angles, restraining deteriorated image quality caused by excessive emphasis of grayscale transition, and improving a moving image quality.
A panel 11 of the image display device (display device) 1 can display color images in such a manner that, for example, one pixel is constituted by three sub pixels corresponding to R, G, and B, respectively, and the luminance of each sub pixel is controlled. The panel 11 includes, for example, as shown in FIG. 2, a pixel array (display section) 2 having sub pixels SPIX (1, 1) to SPIX (n, m) provided in a matrix manner, a data signal line drive circuit 3 which drives data signal lines SL1-SLn on the pixel array 2, and a scanning signal line drive circuit 4 which drives scanning signal lines GL1-GLm on the pixel array 2. The image display device 1 is also provided with a control circuit 12 which supplies control signals to the drive circuits 3 and 4; and a signal processing circuit 21 which generates, based on a video signal DAT supplied from a video signal source VS, a video signal DAT2 which is supplied to the control circuit 12. These circuits operate thanks to power supply from a power source circuit 13. In the present embodiment, furthermore, one pixel PIX is constituted by three sub pixels SPIX which are provided side-by-side along the scanning signal lines GL1-GLm. It is noted that the sub pixel SPIX (1, 1) and the subsequent pixels correspond to the pixels in claims.
Any type of device may be used as the video signal source VS on condition that the video signal DAT can be generated. An example of the video signal source VS in case where a device including the image display device 1 is a television receiver is a tuner (image receiving means) which receives television broadcast so as to generate images of that television broadcast. In such a case, the video signal source as a tuner selects a channel of a broadcast signal, and sends a television video signal of the selected channel to the signal processing circuit 21. In response, the signal processing circuit 21 generates a video signal DAT2 after signal processing based on the television video signal. In case where a device including the video display device 1 is a liquid crystal monitor device, the video signal source VS may be a personal computer, for example.
More specifically, in case where the image display device 1 is included in a television receiver 100a, the television receiver 100a includes the video signal source VS and the image display device 1 and, as shown in FIG. 3(a), the video signal source VS receives a television broadcast signal, for example. This video signal source VS is further provided with a tuner section TS which selects a channel with reference to the television broadcast signal and outputs, as a video signal DAT, a television video signal of the selected channel.
On the other hand, in case where the image display device 1 is included in a liquid crystal monitor device 10b, the liquid crystal monitor device 100b includes, as shown in FIG. 3(b), a monitor signal processing section 101 which outputs, for example, a video monitor signal from a personal computer or the like, as a video signal supplied to the liquid crystal panel 11. The signal processing circuit 21 or the control circuit 12 functions as the monitor signal processing section 101, or the monitor signal processing section 101 may be provided at the stage prior to or subsequent to the signal processing circuit 21 or the control circuit 12.
In the descriptions below, a number or alphabet is added such as the i-th data signal line SLi only when it is required to specify the position, for convenience' sake. When it is unnecessary to specify the position or when a collective term is shown, the number or alphabet is omitted.
The pixel array 2 has plural (in this case, n) data signal lines SL1-SLn and plural (in this case, m) scanning signal lines GL1-GLm which intersect with the respective data signal lines SL1-SLn. Assuming that an arbitrary integer from 1 to n is i whereas an arbitrary integer from 1 to m is j, a sub pixel SPIX (i, j) is provided at the intersection of the data signal line SLi and the scanning signal line GLj.
In the present embodiment, a sub pixel SPIX (i, j) is surrounded by two adjacent data signal lines SL (i−1) and SLi and two adjacent scanning signal lines GL (j−1) and GLj.
The sub pixel SPIX may be any display element provided that the sub pixel SPIX is driven by the data signal line and the scanning signal line. The following description assumes that the image display device 1 is a liquid crystal display device, as an example. The sub pixel SPIX (i, j) is, for example as shown in FIG. 4, provided with: as a switching element, a field-effect transistor SW (i, j) whose gate is connected to the scanning signal line GLj and whose source is connected to the data signal line SLj; and a pixel capacity Cp (i, j), one of whose electrodes is connected to the drain of the field-effect transistor SW (i, j). The other electrode of the pixel capacity Cp (i, j) is connected to the common electrode line which is shared among all sub pixels SPIX. The pixel capacity Cp (i, j) is constituted by a liquid crystal capacity CL (i, j) and an auxiliary capacity Cs (i, j) which is added as necessity arises.
In the above-described sub pixel SPIX (i, j), the field-effect transistor SW (i, j) is switched on in response to the selection of the scanning signal line GLj, and a voltage on the data signal line SLi is supplied to the pixel capacity Cp (i, j). On the other hand, while the selection of the scanning signal line GLj ends and the field-effect transistor SW (i, j) is turned off, the pixel capacity Cp (i, j) keeps the voltage before the turnoff. The transmittance or reflectance of liquid crystal varies in accordance with a voltage applied to the liquid crystal capacity CL (i, j). It is therefore possible to change the display state of the sub pixel SPIX (i, j) in accordance with video data for the sub pixel SPIX (i, j), by selecting the scanning signal line GLj and supplying, to the data signal line SLi, a voltage corresponding to the video data.
The liquid crystal display device of the present embodiment adopts a liquid crystal cell in a vertical alignment mode, i.e. a liquid crystal cell which is arranged such that liquid crystal molecules with no voltage application are aligned to be substantially vertical to the substrate, and the vertically-aligned liquid crystal molecules tilt in accordance with the voltage application to the liquid crystal capacity CL (i, j) of the sub pixel SPIX (i, x). The liquid crystal cell in the present embodiment is in normally black mode (the display appears black under no voltage application).
In the arrangement above, the scanning signal line drive circuit 4 shown in FIG. 2 outputs, to each of the scanning signal lines GL1-GLm, a signal indicating whether the signal line is selected, for example a voltage signal. Also, the scanning signal line driver circuit 4 determines a scanning signal line GLj to which the signal indicating the selection is supplied, based on a timing signal such as a clock signal GCK and a start pulse signal GSP supplied from the control circuit 12, for example. The scanning signal lines GL1-GLm are therefore sequentially selected at predetermined timings.
As video signals, the data signal line drive circuit 3 extracts sets of video data which are supplied by time division to the respective sub pixels SPIX, by, for example, sampling the sets of data at predetermined timings. Also, the data signal line drive circuit 3 outputs, to the respective sub pixels SPIX (1, j) to SPIX (n, j) corresponding to the scanning signal line GLJ being selected by the scanning signal line drive circuit 4, output signals corresponding to the respective sets of video data. These output signals are supplied via the data signal lines SL1-SLn.
The data signal line drive circuit 3 determines the timings of sampling and timings to output the output signals, based on a timing signal such as a clock signal SCK and a start pulse signal SSP.
In the meanwhile, while the corresponding scanning signal line GLj is being selected, the sub pixels SPIX (1, j) to SPIX (n, j) adjust the luminance, transmittance and the like of light emission based on the output signals supplied to the data signal lines SL1-SLn corresponding to the respective sub pixels SPIX (1, j) to SPIX (n, j), so that the brightness of each sub pixel is determined.
Since the scanning signal line drive circuit 4 sequentially selects the scanning signal lines GL1-GLm, the sub pixels SPIX (1, 1) to SPIX (n, m) constituting the entire pixels of the pixel array 2 are set so as to have brightness (grayscale) indicated by the video data. An image displayed on the pixel array 2 is therefore refreshed.
The video data D supplied to each sub pixel SPIX may be a grayscale level or a parameter for calculating a grayscale level, on condition that the grayscale level of each sub pixel SPIX can be specified. In the following description, the video data D indicates a grayscale level of a sub pixel SPIX, as an example.
In the image display device 1, the video signal DAT supplied from the video signal source VS to the signal processing circuit 21 may be an analog signal or a digital signal, as described below. Also, a single video signal DAT may correspond to one frame (entire screen) or may correspond to each of fields by which one frame is constituted. In the following description, for example, a digital video signal DAT corresponds to one frame.
The video signal source VS of the present embodiment transmits video signals DAT to the signal processing circuit 21 of the image display device 1 via the video signal line VL. In doing so, video data for each frame is transmitted by time division, by, for example, transmitting video data for the subsequent frame only after all of video data for the current frame have been transmitted.
The aforesaid frame is constituted by plural horizontal lines. In the video signal line VL, for example, video data of the horizontal lines of each frame is transmitted by time division such that data of the subsequent line is transmitted only after all video data of the current horizontal line is transmitted. The video signal source VS drives the video signal line VL by time division, also when video data for one horizontal line is transmitted. Sets of video data are sequentially transmitted in predetermined order.
Sets of video data are required to allow a set of video data D supplied to each sub pixel to be specified. That is to say, sets of video data D may be individually supplied to the respective sub pixels and the supplied video data D may be used as the video data D supplied to the sub pixels. Alternatively, sets of video data D may be subjected to a data process and then the data as a result of the data process may be decoded to the original video data D by the signal processing circuit 21. In the present embodiment, for example, sets of video data (e.g. RGB data) indicating the colors of the pixels are sequentially transmitted, and the signal processing circuit 21 generates, based on these sets of video data for the pixels, sets of video data D for the respective sub pixels. For example, in case where the video signal DAT conforms to XGA (extended Graphics Array), the transmission frequency (dot clock) of the video data for each pixel is 65 (MHz).
In the meanwhile, the signal processing circuit 21 subjects the video signal DAT transmitted via the video signal line V1 to a process to emphasize grayscale transition, a process of division into sub frames, and a gamma conversion process. As a result, the signal processing circuit 21 outputs a video signal DAT2.
The video signal DAT2 is constituted by sets of video data after the processes, which are supplied to the respective sub pixels. A set of video data supplied to each sub pixel in a frame is constituted by sets of video data supplied to each sub pixel in the respective sub frames. In the present embodiment, the sets of video data constituting the video signal DAT2 are also supplied by time division.
More specifically, to transmit the video signal DAT2, the signal processing circuit 21 transmits sets of video data for respective frames by time division in such a manner that, for example, video data for a subsequent frame is transmitted only after all video data for a current frame is transmitted. Each frame is constituted by plural sub frames. The signal processing circuit 21 transmits video data for sub frames by time division, in such a manner that, for example, video data for a subsequent sub frame is transmitted only after all video data for a current sub frame is transmitted. Similarly, video data for the sub frame is made up of plural sets of video data for horizontal lines. Each set of video data for a horizontal line is made up of sets of video data for respective sub pixels. Furthermore, to send video data for a sub frame, the signal processing circuit 21 sends sets of video data for respective horizontal lines by time division in such a manner that, for example, video data for a subsequent horizontal line is transmitted only after all video data for a current horizontal line is transmitted. To send sets of video data for respective horizontal lines, for example, the signal processing circuit 21 sequentially sends the sets of video data for respective sub pixels, in a predetermined order.
The following will describe a case where a process of division into sub frames and a gamma conversion process are carried out after emphasizing grayscale transition. It is noted that the grayscale transition emphasizing process may be carried out later as described below.
That is to say, as shown in FIG. 1, the signal processing circuit 21 of the present embodiment includes: a modulation processing section (correction means) 31 which corrects a video signal DAT so as to emphasize grayscale transition in each sub pixel SPIX and outputs a video signal DATo as a result of the correction; and a sub frame processing section 32 which performs division into sub frames and gamma conversion based on the video signal DATo and outputs the above-described corrected video signal DAT2. The image display device 1 of the present embodiment is provided with R, G, and B sub pixels for color image display and hence the modulation processing section 31 and the sub frame processing section 32 are provided for each of R, G, and B. These circuits 31 and 32 for the respective colors are identically constructed irrespective of the colors, except video data D (i. j, k) to be input. The following therefore only deals with the circuits for R, with reference to FIG. 1.
As detailed later, the modulation processing section 31 corrects each set of video data (video data D (i, j, k) in this case) for each sub pixel, which data is indicated by a supplied video signal, and outputs a video signal DATo constituted by corrected video data (video data Do (i, j, k) in this case). In FIG. 1 and also in below-mentioned FIGS. 7, 8, 23, 24, and 26, only video data concerning a particular sub pixel SPIX (i, j) is illustrated. It is also noted that a sign such as (i, j) indicating a position is not suffixed to the video data, e.g. video data Do (k).
In the meanwhile, the sub frame processing section 32 divides one frame period into plural sub frames, and generates, based on video data Do (i, j, k) of a frame FR (k), sets of video data S (i, j, k) for the respective sub frames of the frame FR (k).
In the present embodiment, for example, one frame FR (k) is divided into two sub frames, and for each frame, the sub frame processing section 32 outputs sets of video data So1 (i, j, k) and So2 (i, j, k) for the respective sub frames based on the video data Do (i, j, k) of the frame (e.g. FR (k)).
The following assumes that, sub frames constituting a frame FR (k) are termed SFR1 (k) and SFR2 (k) which are temporally in this order, and the signal processing circuit 21 sends video data for the sub frame SFR2 (k) after sending video data for the sub frame SFR1 (k). The sub frame SFR1 (k) corresponds to video data So1 (i, j, k) whereas the sub frame SFR2 (k) corresponds to video data So2 (i, j, k). It is possible to optionally determine a time period from the input of video data D (i, j, k) of a frame FR (k) to the signal processing circuit 21 to the application of a voltage corresponding to the video data D (i, j, k) to the sub pixel SPIX (i, j). Irrespective of the length of this time period, the following (i), (ii), and (iii) are assumed to correspond to the same frame FR (k): (i) video data D (i, j, k) of a frame FR (k); (ii) data (sets of corrected data So1 (i, j, k) and So2 (i, j, k)) after the grayscale transition emphasizing process, frame division process, and gamma correction process; and (iii) voltages (V1 (i, j, k) and V2 (i, j, k)) corresponding to the corrected data. Also, a period corresponding to these sets of data and voltages is termed frame FR (k). These sets of data, the voltages, and the frame have the same frame number (k, for example).
To be more specific, the period corresponding to the sets of data and the voltages is one of the following periods: a period from the input of video data D (i, j, k) of a frame FR (k) to the sub pixel SPIX (i, j) to the input of video data D (i, j, k+1) of the next frame FR (k+1); a period from the output of the first one of (in this case, So1 (i, j, k)) the sets of corrected data So1 (i, j, k) and So2 (i, j, k) which are produced by conducting the aforesaid processes with respect to the video data D (i, j, k) to the output of the first one of (in this case, So1 (i, j, k+1)) the sets of corrected data So1 (i, j, k+1) and So2 (i, j, k+1) which are produced by conducting the aforesaid processes with respect to the video data D (i, j, k+1); and a period from the application of a voltage V1 (i, j, k+1) to the sub pixel SPIX (i, j) in accordance with the video data So1 (i, j, k) to the application of a voltage V1 (i, j, k+1) to the sub pixel SPIX (i, j, k+1) in accordance with the next video data So1 (i, j, k+1).
To simplify the description, when collectively termed, the suffixed number indicating the number of a sub frame is omitted from a sub frame and video data and voltages corresponding thereto, e.g. sub frame SFR (x). In such a case, sub frames SFR1 (k) and SFR2 (k) are termed as sub frames SFR (x) and SFR (x+1).
The aforesaid sub frame processing section 32 includes: a frame memory 41 which stores video data D for one frame, which is supplied to each sub pixel SPIX; a lookup table (LUT) 42 which indicates how video data corresponds to video data So1 for a first sub frame; an LUT 43 which indicates how video data corresponds to video data So2 for a second sub frame; and a control circuit 44 which controls the aforesaid members. It is noted that the LUTs 42 and 43 correspond to storage means in claims, whereas the control circuit 44 corresponds to generation means in claims.
The control circuit 44 can write, once in each frame, sets of video data D (1, 1, k) to D (n, m, k) of the frame (e.g. FR (k)) into the frame memory 41. Also, the control circuit 44 can read out the sets of video data D (1, 1, k) to D (n, m, k) from the frame memory 41. The number of times the control circuit 44 can read out in each frame corresponds to the number of sub frames (2 in this case).
In association with possible values of the sets of video data D (1, 1, k) to D (n, m, k) thus read out, the LUT 42 stores values indicating sets of video data So1 each of which is output when the video data D has the corresponding value. Similarly, in association with the possible values, the LUT 43 stores values indicating sets of video data So2 each of which is output when the video data D has the corresponding value.
Referring to the LUT 42, the control circuit 44 outputs video data So1 (i, j, k) corresponding to the video data D (i, j, k) thus read out. Also, referring to the LUT 43, the control circuit 44 outputs video data So2 (i, j, k) corresponding to the video data D (i, j, k) thus read out. The values stored in the LUTs 42 and 43 may be differences from the possible values, on condition that the sets of video data So1 and So2 can be specified. In the present embodiment, the values of the sets of video data So1 and So2 are stored, and the control circuit 44 outputs, as sets of video data So1 and So2, the values read out from the LUTs 42 and 43.
The values stored in the LUTs 42 and 43 are set as below, assuming that a possible value is g whereas stored values are P1 and P2. Although the video data So1 for the sub frame SFR1 (k) may be set so as to have higher luminance, the following assumes that the video data So2 for the sub frame SFR2 (k) has higher luminance than the video data So1.
In case where g indicates a grayscale not higher than a predetermined threshold (i.e. indicates luminance not higher than the luminance indicated by the threshold), the value P1 falls within a range determined for dark display, whereas the value P2 is set so as to correspond to the value P1 and the above value g. The range for dark display is a grayscale not higher than a grayscale determined in advance for dark display. If the predetermined grayscale for dark display indicates the minimum luminance, the range is at the grayscale with the minimum luminance (i.e. black). The predetermined grayscale for dark display is preferably set so that below-mentioned whitish appearance is restrained to a desired amount or below.
On the other hand, in case where g indicates a grayscale higher than a predetermined threshold (i.e. indicates higher luminance than the luminance indicated by the threshold), the value P2 is set so as to fall within a predetermined range for bright display whereas the value P1 is set so as to correspond to the value P2 and the value g. The range for bright display is not lower than a grayscale for bright display, which is determined in advance. If the grayscale determined in advance for bright display indicates the maximum luminance (white), the range is at the grayscale with the maximum luminance (i.e. white). The predetermined grayscale is preferably set so that whitish appearance is restrained to a desired amount or below.
As a result, in case where the video data D (i, j, k) supplied to the sub pixel SPIX (i, j) in a frame (FR (k) indicates a grayscale not higher than the aforesaid threshold, i.e., in a low luminance region, the magnitude of the luminance of the sub pixel SPIX (i, j) in the frame FR (k) mainly depends on the magnitude of the value P2. On this account, the state of the sub pixel SPIX (i, j) is dark display, at least in the sub frame SFR1 (k) in the frame FR (k). Therefore, in case where the video data D (i, j, k) in a frame indicates a grayscale in a low luminance region, the sub pixel SPIX (i, j) in the frame FR (k) can simulate impulse-type light emission typified by CRTs, and hence the quality of moving images on the pixel array 2 is improved.
In case where the luminance of the video data D (i, j, k) supplied to the sub pixel PIX (i,j) in a frame FR (k) is higher than the aforesaid threshold, i.e., in a high luminance region, the magnitude of the luminance of the sub pixel SPIX (i, j) in the frame FR (k) mainly depends on the magnitude of the value P1. Therefore, in comparison with the arrangement in which the luminances of the respective sub frames SFR1 (k) and SFR2 (k) are substantially equal, it is possible to greatly differentiate the luminance of the sub pixel SPIX (i, j) in the sub frame SFRL (k) from the luminance of the sub pixel SPIX (i, j) in the sub frame SFR2 (k). As a result, the sub pixel SPIX (i, j) in the frame FR (k) can simulate impulse-type light emission in most cases, even if the video data D (i, j, k) in the frame FR (k) indicates grayscale in a high luminance region. The quality of moving images on the pixel array 2 is therefore improved.
According to the arrangement above, in case where the video data (i, j, k) indicates a grayscale in a high luminance region, the video data So2 (i, j, k) for the sub frame SFR2 (k) indicates a value within the range for bright display, and the value of the video data So1 (i, j, k) for the sub frame SFR1 (k) increases as the luminance indicated by the video data D (i, j, k) increases. Therefore, the luminance of the sub pixel SPIX (i, j) in the frame FR (k) is high in comparison with an arrangement in which a period of dark display is always provided even when white display is required. As a result, while the quality of moving images is improved because the sub pixel SPIX simulates impulse-type light emission as above, the maximum value of the luminance of the sub pixel SPIX (i, j) is greatly increased. The image display device 1 can therefore produce brighter images.
Incidentally, even in a VA panel which has a wide range of viewing angles, it is not possible to completely eliminate the variation in grayscale characteristics caused by a change in the viewing angle. For example, the grayscale characteristics deteriorate as, for example, a range of viewing angles in the horizontal direction is increased.
For example, as shown in FIG. 5, the grayscale gamma characteristic at the viewing angle of 60° is different from the grayscale gamma characteristic when the panel is viewed head-on (at the viewing angle of 0°), and hence whitish appearance, which is excessive brightness in intermediate luminance, occurs at the viewing angle of 60°. Also in IPS-mode liquid crystal display panels, variations in grayscale characteristics occur more or less as a range of viewing angles is increased, although the variations depend on the design of an optical film in terms of optical properties.
On the other hand, according to the arrangement above, one of the sets of video data So1 (i, j, k) and So2 (i, j, k) is set so as to fall within the range for dark display or within the range for bright display, both in case where the video data D (i, j, k) indicates a grayscale in a high luminance region and in case where the video data D (i, j, k) indicates a grayscale in a low luminance region. Also, the magnitude of the luminance of the sub pixel SPIX (i, j) in the frame FR (k) mainly depends on the magnitude of the other video data.
As shown in FIG. 5, an amount of the whitish appearance (deviance from the desired luminance) is maximized around intermediate luminance, whereas an amount of the whitish appearance is relatively restrained when the luminance is sufficiently low or high.
Therefore, as shown in FIG. 6, a total amount of generated whitish appearance is greatly restrained in comparison with a case where both of the sub frames SFR1 (k) and SFR2 (k) are substantially equally varied so that the aforesaid luminance is controlled (i.e. intermediate luminance is attained in both sub frames and a case where an image is displayed without dividing a frame. It is therefore possible to greatly improve the viewing angle characteristics of the image display device 1.
In case where the gamma characteristic of a video signal DAT to be input is different from the gamma characteristic of the pixel array 2 (see FIG. 2) of the image display device 1, it is necessary to conduct gamma correction during a period from the input of the video signal DAT to the application of a voltage corresponding to the video signal DAT to the panel 11. Even if the video signal DAT and the pixel array 2 have the same gamma characteristics, it is necessary to conduct gamma correction during a period from the input of the video signal DAT to the application of a voltage corresponding to the video signal DAT to the panel 11, if, for example, an image will be displayed with gamma characteristic different from the original because of an instruction from the user.
In a first comparative example, gamma correction is conducted by not changing the signal supplied to the panel 11 but by controlling the voltage supplied to the panel 11. In this example, since a circuit for controlling a reference voltage is required, the circuit size may increase. In particular, if circuits for controlling reference voltages for respective color components (e.g. R, G, B) are provided for color image reproduction such as the present embodiment, the circuit size significantly increases.
In a second comparative example, as shown in a signal processing circuit 121 in FIG. 7, in addition to the circuits 131-144 similar to those shown in FIG. 1, a gamma correction circuit 133 for gamma correction is provided on the stage directly prior to or subsequent to (in the figure, prior to) the modulation processing section 31, so that a signal supplied to the panel 11 is changed. In this arrangement, the gamma correction circuit 133 is required in place of a circuit for controlling a reference voltage, and hence the circuit size may not be reducible. In the example shown in FIG. 7, the gamma correction circuit 133 generates video data after gamma correction, with reference to an LUT 133a which stores, in association with values which may be input, output values after gamma correction.
On the other hand, in the signal processing circuit 21 of the present embodiment, the LUTs 42 and 43 store values indicating video data for each sub frame after gamma correction, so that the LUTs 42 and 43 function as the LUTs 142 and 143 for time division driving and also the LUT 133a for gamma correction. As a result, the circuit size is reduced because the LUT 133a for gamma correction is unnecessary, and hence the circuit size required for the signal processing circuit 21 is significantly reduced.
Also, in the present embodiment, pairs of the LUTs 42 and 43 are provided for the respective colors (R, G, and B in this case) of the sub pixel SPIX (i, j). It is therefore possible to output different sets of video data So1 and So2 for the respective colors, and hence an output value is more suitable than a case where the same LUT is shared between different colors.
In particular, in case where the pixel array 2 is a liquid crystal display panel, gamma characteristic is different among colors because birefringence varies in accordance with a display wavelength. The aforesaid arrangement is particularly effective in this case, because independent gamma correction is preferable when grayscales are expressed by responsive integral luminance in case of time-division driving.
In case where a gamma value is changeable, a pair of LUTs 42 and 43 is provided for each changeable gamma value. When an instruction from, for example, the user to change a gamma value, the control circuit 44 selects a pair of LUTs 42 and 43 suitable for the instruction among the pairs of LUTs 42 and 43, and refers to the selected pair of LUTs 42 and 43. In this way the sub frame processing section 32 can change a gamma value to be corrected.
In response to an instruction to change a gamma value, the sub frame processing section 32 may change the time ratio between the sub frames SFR1 and SFR2. In such a case, the sub frame processing section 32 instructs the modulation processing section 31 to also change the time ratio between the sub frames SFR1 and SFR2 in the modulation processing section 31. Since the time ratio between the SFR1 and SFR2 is changeable in response to an instruction to change a gamma value, as detailed below, it is possible to change, with appropriate brightness, a sub frame (SFR1 or SFR2) whose luminance is used for mainly controlling the luminance in one frame period, no matter which gamma value is corrected in response to an instruction.
The following will discuss details of the modulation processing section 31, with reference to FIG. 8. The modulation processing section 31 of the present embodiment performs a predictive grayscale transition emphasizing process, and includes: a frame memory (predicted value storage means) 51 which stores a predicted value (i, j, k) of each sub pixel SPIX (i, j) until the next frame FR (k+1) comes; a correction processing section 52 which corrects video data D (i, j, k) of the current frame FR (k) with reference to the predicted value E (i, j, k−1) of the previous frame FR (k−1), which value has been stored in the frame memory 51, and outputs the corrected value as video data Do (i, j, k); and a prediction processing section 53 which updates the predicted value E (i, j, k−1) of the sub pixel SPIX (i, j), which value has been stored in the frame memory 51, to a new predicted value E (i, j, k), with reference to the video data D (i, j, k) supplied to the sub pixel (i, j) in the current frame FR (k).
The predicted value E (i, j, k) in the current frame FR (k) indicates a value of a grayscale corresponding to predicted luminance to which the sub pixel (SPIX (i, j) driven with the corrected video data Do (i, j, k) is assumed to reach at the start of the next frame FR (k+1), i.e. when the sub pixel SPIX (i, j) starts to be driven with the video data Do (i, j, k+1) in the next frame FR (k+1). Based on the predicted value E (i, j, k−1) in the previous frame FR (k−1) and the video data D (i, j, k) in the current frame FR (k), the prediction processing section 53 predicts the predicted value E (i, j, k).
As discussed above, the present embodiment is arranged as follows: frame division and gamma correction are conducted to corrected video data Do (i, j, k) so that two sets of video data So1 (i, j, k) and So2 (i, j, k) are generated in one frame, and voltages V1 (i, j, k) and V2 (i, j, k) corresponding to the respective sets of data are applied to the sub pixel SPIX (i, j) within one frame period. It is noted that, as discussed below, corrected video data Do (i, j, k) is specified by specifying a predicted value E (i, j, k−1) in the previous frame FR (k−1) and video data D (i, j, k) in the current frame FR (k), and the sets of video data So1 (i, j, k) and So2 (i, j, k) and the voltages V1 (i, j, k) and V2 (i, j, k) are specified by specifying the video data Do (i, j, k).
Since the aforesaid predicted value E (i, j, k−1) is a predicted value in the previous frame FR (k−1), the predicted value E (i, j, k−1) indicates, from the perspective of the current frame FR (k), a grayscale corresponding to predicted luminance to which the sub pixel SPIX (i, j) is assumed to reach at the start of the current frame FR (k), i.e. indicates the display state of the sub pixel SPIX (i, j) at the start of the current frame FR (k). In case where the sub pixel SPIX (i, j) is a liquid crystal display element, the aforesaid predicted value also indicates the alignment of liquid crystal molecules in the sub pixel SPIX (i, j).
Therefore, provided that the prediction by the prediction processing section 53 is accurate and the predicted value E (i, j, k−1) of the previous frame FR (k−1) has been accurately predicted, the prediction processing section 53 can precisely predict the aforesaid predicted value E (i, j, k) based on the predicted value E (i, j, k−1) of the previous frame FR (k−1) and the video data D (i, j, k) of the current frame FR (k).
In the meanwhile, the correction processing section 52 can correct video data D (i, j, k) in such a way as to emphasize the grayscale transition from the grayscale indicated by a predicted value E (i, j, k−1) in the previous frame FR (k−1) to the grayscale indicated by the video data D (i, j, k), based on (i) the video data D (i, j, k) in the current frame FR (k) and (ii) the predicted value E (i, j, k−1), i.e. the value indicating the display state of the sub pixel SPIX (i, j) at the start of the current frame FR (k).
The processing sections 52 and 53 may be constructed solely by LUTs, but the processing sections 52 and 53 of the present embodiment are constructed by using both reference process and interpolation process of the LUTs.
More specifically, the correction processing section 52 of the present embodiment is provided with an LUT 61. The LUT 61 stores, in association with respective pairs of sets of video data D (i, j, k) and predicted values (i, j, k−1), values of video data Do each of which is output when a corresponding pair is input. Any types of values may be used as the values of video data Do on condition that the video data Do can be specified by the same, as in the aforesaid case of the LUTs 42 and 43. The following description assumes that video data Do itself is stored.
The LUT 61 may store values corresponding to all possible pairs. The LUT 61 of the present embodiment, however, stores only values corresponding to predetermined pairs, in order to reduce the storage capacity. In case where a pair which is not stored in the LUT 61 is input, a calculation section 62 provided in the correction processing section 52 reads out values corresponding pairs similar to the pair thus input, and performs interpolation of these values by conducting a predetermined calculation so as to figure out a value corresponding to the pair thus input.
Similarly, an LUT 71 provided in the prediction processing section 53 of the present embodiment stores, in association with respective pairs of sets of video data (i, j, k) and predicted values E (i, j, k−1), values each of which is output when a corresponding pair is input. The LUT 71 also stores values to be output (in this case, predicted values E (i, j, k)) in a similar manner as above. Furthermore, as in the case above, pairs of values stored in the LUT 71 are limited to predetermined pairs, and a calculation section 72 of the prediction processing section 53 figures out a value corresponding to a pair thus input, by conducting an interpolation calculation with reference to the LUT 71.
In the arrangement above, the frame memory 51 stores not video data D (i, j, k−1) of the previous frame FR (k−1) but a predicted value E (i, j, k−1). The correction processing section 52 corrects the video data D (i, j, k) of the current frame FR (k) with reference to the predicted value E (i, j, k−1) of the previous frame FR, i.e. a value indicating predicted display state of the sub pixel SPIX (i, j) at the start of the current frame FR (k). It is therefore possible to prevent inappropriate grayscale transition emphasis, even if transition from rise to decay frequently occurs as a result of improvement in the quality of moving images by simulating impulse-type light emission.
More specifically, in case where a sub pixel SPIX (i, j) with a slow response speed is adopted, grayscale transition from last but one sub frame to last sub frame is emphasized, the luminance of the sub pixel SPIX at the end of the last sub frame SFR (x−1) (i.e. the luminance at the start of the current sub frame FR (x)) may not reach the luminance indicated by the video data So (i, j, x) in the last sub frame SFR (x−1). This occurs, for example, when a difference between grayscales is great and when a grayscale before grayscale transition emphasis is close to the maximum or minimum value so that the grayscale transition cannot be sufficiently emphasized.
In the case above, if the signal processing circuit 21 emphasizes grayscale transition with the assumption that the luminance at the start of the current sub frame FR (x) has reached the luminance indicated by the video data So (i, j, x) in the previous sub frame SFR (x−1), the grayscale transition may be excessive or insufficient.
In particular, when (rising) grayscale transition to increase luminance and (decaying) grayscale transition to decrease luminance are alternately repeated, the grayscale transition is excessive and hence the luminance of the sub pixel SPIX (i, j) is inappropriately high. As a result, the user is likely to take notice of the inappropriate grayscale transition emphasis and hence the image quality may be deteriorated.
On the other hand, as described above, the present embodiment is arranged in such a manner that voltages V1 (i, j, k) and V2 (i, j, k) corresponding to sets of video data So1 (i, j, k) and So2 (i, j, k) are applied to the sub pixel SPIX (i, j) so that the sub pixel SPIX (i, j) simulates impulse-type light emission. The luminance that the sub pixel SPIX (i, j) should have increased or decreased in each sub frame. Therefore the image quality may be deteriorated by inappropriate grayscale transition emphasis with the assumption above.
In this connection, in the present embodiment, prediction is highly precisely carried out with reference to a predicted value E (i, j, k), as compared to the assumption above. It is therefore possible, by simulating impulse-type light emission, to prevent grayscale transition emphasis from being inappropriate, even if transition from rise to decay frequently occurs. As a result, the quality of moving images is improved by simulating impulse-type light emission, without causing deterioration in image quality due to inappropriate grayscale transition emphasis. Other examples to carry out prediction with higher precision than the aforesaid assumption are as follows: prediction is carried out with reference to plural sets of video data which have been input; prediction is carried out with reference to plural results of previous predictions; and prediction is carried out with reference to plural sets of video data including at least a current set of video data, among sets of video data having been input and the current set of video data.
The response speed of a liquid crystal cell which is in the vertical alignment mode and the normally black mode is slow in decaying grayscale transition as compared to rising grayscale transition. Therefore, even if modulation and driving are performed in such a way as to emphasize grayscale transition, a difference between actual grayscale transition and desired grayscale transition tends to occur in grayscale transition from the last but one sub frame to the last sub frame. Therefore an exceptional effect is obtained when the aforesaid liquid crystal cell is used as the pixel array 2.
The following will give details of division into sub frames by the sub frame processing section 32 (i.e. generation of sets of video data So1 and So2) with reference to FIGS. 9-22, with the assumption that the pixel array 2 is a VA-mode active matrix (TFT) liquid crystal panel and each sub pixel SPIX is capable of expressing 8-bit grayscales. In the following, sets of video data So1 and So2 are termed a first display signal and a second display signal, respectively, for the sake of convenience.
First, typical display luminance (luminance of an image displayed on a liquid crystal panel) of a liquid crystal panel will be discussed.
In case where an image based on normal 8-bit data is displayed in one frame without using sub frames (i.e. normal hold display in which each of the scanning signal lines GL1-GLm of the liquid crystal panel is turned on only once in one frame period), the luminance grayscales (signal grayscales) of a signal (video signal DAT2) applied to the liquid crystal panel have 0 to 255 levels.
A signal grayscale and display luminance in the liquid crystal panel are approximated by the following equation (1).

((T−T0)/(Tmax−T0))=(L/Lmax)^γ  (1)

In the equation, L indicates a signal grayscale (frame grayscale) in case where an image is displayed in one frame (i.e., an image is displayed with normal hold display), Lmax indicates the maximum luminance grayscale (255), T indicates display luminance, Tmax indicates the maximum luminance (luminance when L=Lmax=255; white), T0 indicates the minimum luminance (luminance when L=0; black), and γ is a correction value (typically set at 2.2).
Although T0 is not 0 in an actual liquid crystal display panel, the following assumes that T0=0, for the sake of simplicity.
In addition, the display luminance T of the liquid crystal panel in the case above (normal hold display) is shown in above-mentioned FIG. 5.
In the graph in FIG. 5, the horizontal axis indicates luminance to be output (predicted luminance; which is a value corresponding to a signal grayscale and is equivalent to the display luminance T) whereas the vertical axis indicates luminance (actual luminance) which has actually been output.
As shown in the graph, in the case above, the aforesaid two sets of luminance are equal to one another when the liquid crystal panel is viewed head-on (i.e. the viewing angle is 0°).
On the other hand, in case where the viewing angle is 60°, actual luminance is unnecessarily bright around intermediate luminance, because of change in grayscale gamma characteristic.
Now, the display luminance of the image display device 1 of the present example will be discussed.
In the image display device 1, the control circuit 44 is designed to perform grayscale expression to meet the following conditions:
(a) a time integral value (integral luminance in one frame) of the luminance (display luminance) of an image displayed on the pixel array 2 in each of a first sub frame and a second sub frame is equal to the display luminance in one frame in the case of normal hold display; and
(b) black display (minimum luminance) or white display (maximum luminance) is conducted in either of the sub frames.
For that purpose, in the image display device 1 of the present example, the control circuit 44 is designed so that a frame is equally divided into two sub frames and luminance up to the half of the maximum luminance is attained in one sub frame.
That is to say, in case where luminance (threshold luminance; Tmax/2) up to the half of the maximum luminance is attained in one frame (i.e. in the case of low luminance), the control circuit 44 performs grayscale expression in such a way that display with minimum luminance (black) is performed in the first sub frame and display luminance is adjusted only in the second sub frame (in other words, grayscale expression is carried out by using only the second sub frame).
In this case, the integral luminance in one frame is expressed as (minimum luminance+luminance in the second sub frame)/2.
In case where luminance higher than the aforesaid threshold luminance is attained (in the case of high luminance), the control circuit 44 performs grayscale expression in such a manner that the maximum luminance (white) is attained in the second sub frame and the display luminance is adjusted in the first sub frame.
In this case, the integral luminance in one frame is represented as (luminance in the first sub frame+maximum luminance)/2.
The following will specifically discuss signal grayscale setting of display signals (first display signal and second display signal) for attaining the aforesaid display luminance.
The signal grayscale setting is carried out by the control circuit 44 shown in FIG. 1.
Using the equation (1), the control circuit 44 calculates a frame grayscale corresponding to the threshold luminance (Tmax/2) in advance.
That is to say, a frame grayscale (threshold luminance grayscale; Lt) corresponding to the display luminance above is figured out by the following equation (2), based on the equation (1).

Lt=0.5^(1/γ)×Lmax  (2)

In this equation, it is noted that Lmax=Tmax^γ  (2a)

To display an image, the control circuit 44 determines the frame grayscale L, based on the video signal supplied from the frame memory 41.
If L is not larger than Lt, the control circuit 44 minimizes (reduces to 0) the luminance grayscale (hereinafter, F) of the first display signal, by means of the first LUT 42.
On the other hand, based on the equation (1), the control circuit 44 determines the luminance grayscale (hereinafter, R) of the second display signal as follows, by means of the second LUT 43.

R=0.5^(1/γ)'L  (3)

In case where the frame grayscale L is larger than Lt, the control circuit 44 maximizes (increases to 255) the luminance grayscale R of the second display signal.
At the same time, based on the equation (1), the control circuit 44 determines the luminance grayscale F in the first sub frame as follows.

F=(L^γ−0.5×Lmax^γ)^(1/γ)  (4)

Now, the following gives details of how the image display device 1 of the present example outputs a display signal.

In the present case, the control circuit 44 send, to the control circuit 12 shown in FIG. 2, a video signal DAT2 after the signal processing, so as to cause, with a doubled clock, the data signal line drive circuit 3 to accumulate a first display signal supplied to (n) sub pixels SPIX on the first scanning signal line GL1.
The control circuit 44 then causes, via the control circuit 12, the scanning signal line drive circuit 4 to turn on (select) the first scanning signal line GL1, and also causes the scanning signal line drive circuit 4 to write a first display signal into the sub pixels SPIX on the scanning signal line GL1. Subsequently, the control circuit 44 similarly turns on second to m-th scanning signal lines GL2-GLm at a doubled clock, with first display signal to be accumulated being varied. With this, a first display signal is written into all sub pixels SPIX in the half of one frame (1⁄2 frame period).
The control circuit 44 then similarly operates so as to write a second display signal into the sub pixels SPIX on all scanning signal lines GL1-GLm, in the remaining 1⁄2 frame period.
As a result, the first display signal and the second display signal are written into the sub pixels SPIX in the respective periods (1⁄2 frame periods) which are equal to each other.
The above-mentioned FIG. 6 is a graph showing, along with the results (dashed line and full line) in FIG. 2, the results (dotted line and full line) of sub frame display by which the first display signal and the second display signal are output in the respective first and second sub frames.
As shown in FIG. 5, the image display device 1 of the present example adopts a liquid crystal panel which is arranged such that, the difference between actual luminance and planned luminance (equivalent to the full line) in a large viewing angle is minimized when the display luminance is minimum or maximum, whereas the difference is maximized in intermediate luminance (around the threshold luminance).
Also, the image display device 1 of the present example carries out sub frame display with which one frame is divided into sub frames.
Further, two sub frames are set so as to have the same length of time, and in case of low luminance, black display is carried out in the first sub frame and image display is carried out only by the second sub frame, to the extent that the integrated luminance in one frame is not changed.
Since the deviance in the first sub frame is minimized, the total deviance in the first and second sub frames is substantially halved as indicated by the dotted line in FIG. 6.
On the other hand, in the case of high luminance, white display is carried out in the second sub frame and image display is performed only by adjusting the luminance in the first sub frame, to the extent that the integrated luminance in one frame is not changed.
Since the deviance in the second sub frame is also minimized in this case, the total deviance in the first and second sub frames is substantially halved, as indicated by a doted line in FIG. 6.
In this way, in the image display device 1 of the present example, overall deviance is substantially halved as compared to normal hold display (an image is displayed in one frame, without adopting sub frames).
It is therefore possible to restrain the problem that an image with intermediate luminance is excessively bright and appears whitish (whitish appearance) as shown in FIG. 5.
The first sub frame and the second sub frame are equal in time length in the present example. This is because luminance half as much as the maximum luminance is attained in one sub frame.
These sub frames, however, may have different lengths.
The whitish appearance, which is a problem in the image display device 1 of the present example, is a phenomenon that actual luminance has the characteristics shown in FIG. 5 in the case of a large viewing angle, and hence an image with intermediate luminance is excessively bright and appears whitish.
An image taken by a camera is typically converted to a signal generated based on luminance. To send the image in a digital form, the image is converted to a display signal by using “γ” in the equation (1) (in other words, the signal based on luminance is raised to (1/γ)th power and grayscales are attained by equal division).
An image which is displayed based on the aforesaid display signal on the image display device 1 such as a liquid crystal panel has display luminance expressed by the equation (1).
Human eyes perceive an image not as variation in luminance but as variation in brightness. Brightness (brightness index) M is expressed by the following equations (5) and (6) (see non-patent document 1).

M=116×Y^(1⁄3)−16, Y≧0.008856  (5)

M=903.29×Y,Y≦0.008856  (6)

In the equations, Y is equivalent to the aforesaid actual luminance and Y=(y/yn). It is noted that y indicates a “y” value of three stimulation values in an xyz color system of a color, whereas yn is a y value of standard light from a perfectly diffuse reflector and yn=100.
The equations above show that humans are sensitive to images with low luminance and gets insensitive to images with higher luminance.
It is therefore considered that not deviance in luminance but deviance in brightness is perceived by humans as whitish appearance.
FIG. 9 is a graph in which the graph of luminance shown in FIG. 5 is converted to a graph of brightness.
In this graph, the horizontal axis indicates “brightness which should be attained (planned brightness; a value corresponding to a signal grayscale and equivalent to the aforesaid brightness M)” whereas the vertical axis indicates “brightness which is actually attained (actual brightness)”
As indicated by the full line in the graph, the above-described two sets of brightness are equal when the liquid crystal panel is viewed head-on (i.e. viewing angle of 0°).
On the other hand, in case where the viewing angle is 60° and sub frames are equal to each other (i.e. luminance up to the maximum value is attained in one sub frame), as indicated by the dotted line in the graph, the difference between the actual brightness and the planned brightness is restrained as compared to the conventional normal hold display. Whitish appearance is therefore restrained to some degree.
To further restrain whitish appearance in accordance with visual perception of humans, it is considered that the ratio of frame division is preferably determined in accordance with not luminance but brightness.
Difference between actual brightness and planned brightness is maximized at the brightness which is half as much as the maximum value of the planned brightness, as in the case of luminance.
For this reason, deviance (i.e. whitish appearance) perceived by humans is restrained when a frame is divided so that brightness up to the half of the maximum value is attained in one sub frame, as compared to the case where a frame is divided so that luminance up to the half of the maximum value is attained in one sub frame.
The following will discuss how a frame should preferably be divided.
To simplify calculations, the above-mentioned equations (5) and (6) are approximated into an equation (6a) (which is similar to the equation (1)).

M=Y^(1/α)  (6a)

With this conversion, a in this equation is about 2.5.
It is considered that the relationship between the luminance Y and the brightness M is appropriate (i.e. suitable for visual perception of humans), if the value of α is in a range between 2.2. and 3.0.
To attain the brightness M which is half as much as the maximum value in one sub frame, it has been known that two sub frames are set so as to be in the ration of about 1:3 when γ=2.2 or about 1:7 when γ=3.0.
In dividing a frame in this way, the sub frame for image display in the case of low luminance is set so as to be shorter than the other sub frame (in the case of high luminance, the sub frame in which the maximum luminance is maintained is set so as to be shorter than the other sub frame).
The following will discuss a case where the first sub frame and the second sub frame are in the ratio of 3:1 in time length.
First, display luminance in this case is discussed.
In this case, to perform low-luminance display with which luminance up to 1⁄4 of the maximum luminance (i.e. threshold luminance; Tmax/4) is attained in one frame, the control circuit 44 performs display with the minimum luminance (black). in the first sub frame and expresses a grayscale by only adjusting the display luminance in the second sub frame. (In other words, grayscale expression is carried out only by the second sub frame.)
On this occasion, the integrated luminance in one frame is figured out by (minimum luminance+luminance in the second sub frame)/4.
In case where luminance higher than the threshold luminance (Tmax/4) is attained in one frame (i.e. in case of high luminance), the control circuit 44 operates so that the maximum luminance (white) is attained in the second sub frame whereas grayscale expression is performed by only adjusting the display luminance in the first sub frame.
In this case, the integrated luminance in one frame is figured out by (luminance in the first sub frame+maximum luminance)/4.
Now, the following will specifically describe signal grayscale setting of display signals (first display signal and second display signal) for attaining the aforesaid display luminance.
Also in this case, the signal grayscale (and below-mentioned output operation) is (are) set so that the above-described conditions (a) and (b) are satisfied.
First, using the equation (1), the control circuit 44 calculates a frame grayscale corresponding to the threshold luminance (Tmax/4) in advance.
The frame grayscale (threshold luminance grayscale; Lt) corresponding to the display luminance is calculated by the following equation, based on the equation (1):

Lt=(1⁄4)^(1/γ)×Lmax  (7)

To display an image, the control circuit 44 works out a frame grayscale L based on a video signal supplied from the frame memory 41.
If L is not higher than Lt, the control circuit 44 minimizes (to 0) the luminance grayscale (F) of the first display signal, by using the first LUT 42.
In the meanwhile, the control circuit 44 sets the luminance grayscale (R) of the second display signal as follows, based on the equation (1).

R=(1⁄4)^(1/γ)×L  (8)

In doing so, the control circuit 44 uses the second LUT 43.
If the frame grayscale L is higher than Lt, the control circuit 44 maximizes (to 255) the luminance grayscale R of the second display signal.
In the meanwhile, the control circuit 44 sets the luminance grayscale F of the first sub frame as follows, based on the equation (1).

F=((L^γ-(1⁄4)×Lmax^γ))^(1/γ)  (9)

Now, the following will discuss how the above-mentioned first display signal and second display signal are output.

As discussed above, in the arrangement of equally dividing a frame, a first-stage display signal and a second-stage display signal are written into a sub pixel SPIX, for respective periods (1⁄2 frame periods) which are equal to one another.
This is because, since the second-stage display signal is written after all of the first-stage display signal is written at a doubled clock, periods in which the scanning signal lines GL are turned on are equal for the respective display signals.
Therefore, the ratio of division is changeable by changing the timing to start the writing of the second-stage display signal (i.e. timing to turns on the scanning signal lines GL for the second-stage display signal).
In FIG. 10, (a) indicates a video signal supplied to the frame memory 41, (b) indicates a video signal supplied from the frame memory 41 to the first LUT 42 when the division is carried out at the ratio of 3:1, and (c) indicates a video signal supplied to the second LUT 43.
FIG. 11 illustrates timings to turn on the scanning signal lines GL for the first-stage display signal and for the second-stage display signal, also in case where the division is carried out at the ratio of 3:1.
As shown in these figures, the control circuit 44 in this case writes the first-stage display signal for the first frame into the sub pixels SPIX on the respective scanning signal lines GL, at a normal clock.
After a 3⁄4 frame has passed, the writing of the second-stage display signal starts. From this time, the first-stage display signal and the second-stage display signal are alternately written at a doubled clock.
That is to say, after the first-stage display signal is written into the (3⁄4 of all scanning signal lines GL1-GLm)th GL(m*3⁄4) sub pixel SPIX, the second-stage display signal regarding the first scanning signal GL1 is accumulated in the data signal line drive circuit 3, and this scanning signal line GL1 is turned on.
In this way, after 3⁄4 of the first frame, the first-stage display signal and the second-stage display signal are alternately output at a doubled clock, with the result that the ratio between the first sub frame and the second sub frame is set at 3:1.
The time integral value (integral summation of the display luminance in these two sub frames indicates integral luminance of one frame.
The data stored in the frame memory 41 is supplied to the data signal line drive circuit 3, at timings to turn on the scanning signal lines GL.
FIG. 12 is a graph showing the relationship between planned brightness and actual brightness in case where a frame is divided at a ratio of 3:1.
As shown in the figure, in the arrangement above, the frame is divided at the point where the difference between planned brightness and actual brightness is maximized. For this reason, the difference between planned brightness and actual brightness at the viewing angle of 60° is very small as compared to the result shown in FIG. 9.
More specifically, in the image display device 1 of the present example, in the case of low luminance (low brightness) up to Tmax/4, black display is carried out in the first sub frame and hence image display is performed only in the second sub frame, to the extent that the integral luminance in one frame is not changed.
As such, the deviance in the first sub frame (i.e. the difference between actual brightness and planned brightness) is minimized. It is therefore possible to substantially halve the total deviance in the both sub frames, as indicated by the dotted line in FIG. 12.
On the other hand, in the case of high luminance (high brightness), white display is carried out in the second sub frame and hence image display is carried out by adjusting the luminance in the first sub frame, to the extent that the integral luminance in one frame is not changed.
Therefore, since the deviance in the second sub frame is also minimized in this case, the total deviance in the both sub frames is substantially halved as indicated by the dotted line in FIG. 12.
In this manner, in the image display device 1 of the present example, the overall deviance of brightness is substantially halved as compared to normal hold display.
It is therefore possible to effectively restrain the problem that an image with intermediate luminance is excessively bright and appears whitish (whitish appearance) as shown in FIG. 5.
In the case above, until a 3⁄4 frame period passes from the start of display, the first-stage display signal for the first frame is written into the sub pixels SPIX on all scanning signal lines GL, at a normal clock. This is because the timing to write the second-stage display signal has not come yet.
Alternatively, display with a doubled clock may be performed from the start of the display, by using a dummy second-stage display signal. In other words, the first-stage display signal and the (dummy) second-stage display signal whose signal grayscale is 0 may be alternately output until a 3⁄4 frame period passes from the start of display.
The following will deal with a more general case where the ratio between the first sub frame and the second sub frame is n:1.
In this case, to attain luminance up to 1/(n+1) (threshold luminance; Tmax/(n+1)) of the maximum luminance in one frame (i.e. in the case of low luminance), the control circuit 44 performs grayscale expression in such a manner that display with the minimum luminance (black) is performed in the first sub frame and hence grayscale expression is performed by only adjusting the luminance in the second sub frame (i.e. grayscale expression is carried out only by using the second sub frame).
In this case, the integral luminance in one frame is figured out by (minimum luminance+luminance in the second sub frame)/(n+1).
In case where luminance higher than a threshold luminance (Tmax/(n+1)) is output (i.e. in the case of high luminance), the control circuit 44 performs grayscale expression in such a manner that the maximum luminance (white) is attained in the second sub frame and the display luminance in the first sub frame is adjusted.
In this case, the integral luminance in one frame is figured out by (luminance in the first sub frame+maximum luminance)/(n+1).
The following will specifically discuss signal grayscale setting of signals (first-stage display signal and second-stage display signal) for attaining the aforesaid display luminance.
Also in this case, the signal grayscale (and below-mentioned output operation) is (are) set so as to satisfy the aforesaid conditions (a) and (b).
First, the control circuit calculates a frame grayscale corresponding to the above-described threshold luminance (Tmax/(n+1)), based on the equation (1) above.
Based on the equation (1), a frame grayscale (threshold luminance grayscale; Lt) corresponding to the display luminance is figured out as follows.

Lt=(1/(n+1))^(1/γ)×Lmax  (10)

To display an image, the control circuit 44 figures out a frame grayscale L based on a video signal supplied from the frame memory 41.
If L is not higher than Lt, the control circuit 44 minimizes (to 0) the luminance grayscale (F) of the first-stage display signal, by using the first LUT 42.
On the other hand, the control circuit 44 sets the luminance grayscale (R) of the second-stage display signal as follows, based on the equation (1).

R=(1/(n+1))^(1/γ)×L  (11)

In doing so, the control circuit 44 uses the second LUT 43.
If the frame grayscale L is higher than Lt, the control circuit 44 maximizes (to 255) the luminance grayscale R of the second-stage display signal.
In the meanwhile, the control circuit 44 sets the luminance grayscale F in the first sub frame as follows, based on the equation (1).

F=((L^γ−(1/(n+1))×Lmax^γ))^(1/γ)  (12)

The operation to output the display signals is arranged such that, in case where one frame is divided in the ratio of 3:1, the first-stage display signal and the second-stage display signal are alternately output at a doubled clock, when a n/(n+1) frame period has passed from the start of one frame.
An arrangement of equally dividing a frame is generalized as follows: one frame is divided into 1+n (=1) sub frame periods, and the first-stage display signal is output at a clock multiplied 1+n (=1) times in the first sub frame whereas the second-stage display signal is sequentially output in the following n (=1) sub frames.
In this arrangement, however, the clock is required to be significantly increased when n is 2 or more, thereby resulting increase in device cost.
On this account, if n is 2 or more, the aforesaid arrangement in which the first-stage display signal and the second-stage display signal are alternately output is preferable.
In this case, since the ratio between the first sub frame and the second sub frame can be set at n:1 by adjusting the timing to output the second-stage display signal, the required clock frequency is restrained to twice as fast as the normal clock.
The liquid crystal panel is preferably AC-driven, because, with AC drive, the electric field polarity (direction of a voltage (interelectrode voltage) between pixel electrodes sandwiching liquid crystal) of the sub pixel SPIX is changeable in each frame.
When the liquid crystal panel is DC-driven, a one-sided voltage is applied to the space between the electrodes and hence the electrodes are charged. If this state continues, an electric potential difference exists between the electrodes even if no voltage is applied (i.e. so-called burn-in occurs).
In case of sub frame display as in the case of the image display device 1 of the present example, voltage values (absolute values) applied to the space between the pixel electrodes are often different between sub frames.
Therefore, when the polarity of the interelectrode voltage is reversed in the cycle of sub frames, the interelectrode voltage to be applied is one-sided on account of the difference in voltage values between the first sub frame and the second sub frame. Therefore, the aforesaid burn-in, flicker, or the like may occur when the liquid crystal panel is driven for a long period of time, because the electrodes are charged.
Therefore, in the image display device 1 of the present example, the polarity of the interelectrode voltage is preferably reversed in the cycle of frames.
There are two methods to reverse the polarity of the interelectrode voltage in the cycle of frames. According to the first method, a voltage with the same polarity is applied for one frame.
According to the second method, the polarity of the interelectrode voltage is changed between two sub frames of one frame, and the second sub frame and the first sub frame of the directly subsequent frame are arranged so as to have the same polarity.
FIG. 13(a) shows the relationship between voltage polarity (polarity of the interelectrode voltage) and frame cycle, when the first method is adopted. FIG. 13(b) shows the relationship between voltage polarity and frame cycle, when the second method is adopted.
Since the interelectrode voltage is alternated in the cycle of frames, burn-in and flicker do not occur even if interelectrode voltage is significantly changed between sub frames.
Both of the aforesaid two methods are useful for preventing burn-in and flicker. However, the method in which the same polarity is maintained for one frame is preferable in case where relatively brighter display is performed in the second sub frame. More specifically, in the arrangement of division into sub frames, since time to charge the TFT is reduced and hence a margin for the charging is undeniably reduced as compared to cases where division to sub frames is not conducted. Therefore, in commercial mass production, the luminance may be inconstant among the products because charging is insufficient due to reasons such as inconsistency in panel and TFT characteristics. On the other hand, according to the above-discussed arrangement, the second frame, in which luminance is mainly produced, corresponds to the second same-polarity writing, and hence voltage variation in the second frame in which luminance is mainly produced is restrained. As a result, an amount of required electric charge is reduced and display failure on account of insufficient charging is prevented.
As discussed above, the image display device 1 of the present example is arranged in such a manner that the liquid crystal panel is driven with sub frame display, and hence whitish appearance is restrained.
However, the sub frame display may be ineffective when the response speed of liquid crystal (i.e. time required to equalize a voltage (interelectrode voltage) applied to the liquid crystal and the applied voltage) is slow.
In the case of normal hold display, one state of liquid crystal corresponds to one luminance grayscale, in a TFT liquid crystal panel. The response characteristics of liquid crystal do not therefore depend on a luminance grayscale of a display signal.
On the other hand, in the case of sub frame display such as the image display device 1 of the present example, a voltage applied to liquid crystal in one frame changes as shown in FIG. 14(a), in order to perform display based on a display signal of intermediate luminance, which indicates that the minimum luminance (white) is attained in the first sub frame whereas the maximum luminance is attained in the second sub frame.
The interelectrode voltage changes as indicated by the full line X shown in FIG. 14(b), in accordance with the response speed (response characteristics) of liquid crystal.
In case where the response speed of liquid crystal is slow, the interelectrode voltage (full line X) changes as shown in FIG. 14(c) when display with intermediate luminance is carried out.
In this case, therefore, the display luminance in the first sub frame does not reach the minimum and the display luminance in the second sub frame does not reach the maximum.
FIG. 15 shows the relationship between planned luminance and actual luminance in this case. As shown in the figure, even if sub frame display is performed, it is not possible to perform display with luminance (minimum luminance and maximum luminance) at which the difference (deviance) between planned luminance and actual luminance is small in the case of a large viewing angle.
The suppression of whitish appearance is therefore inadequate.
Therefore, to suitably conduct sub frame display as in the case of the image display device 1 of the present example, the response speed of liquid crystal in the liquid crystal panel is preferably designed to satisfy the following conditions (c) and (d).
(c) In case where a voltage signal (generated by the data signal line drive circuit 3 based on a display signal) indicating the maximum luminance (white; corresponding to the maximum brightness) is applied to liquid crystal which is in the state of the minimum luminance (black; corresponding to the minimum luminance), the voltage (interelectrode voltage) of the liquid crystal reaches a value not less than 90% of the voltage of the voltage signal (i.e. actual brightness when viewed head-on reaches 90% of the maximum brightness) in the shorter sub frame period.
(d) In case where a voltage signal indicating the minimum luminance (black) is applied to liquid crystal which is in the state of the maximum luminance (white), the voltage (interelectrode voltage) on the liquid crystal reaches a value which is not higher than 5% of the voltage of the voltage signal, in the shorter sub frame period (i.e. the actual brightness when viewed head-on reaches 5% of the minimum brightness).
The control circuit 44 is preferably designed to be able to monitor the response speed of liquid crystal.
If it is judged that the conditions (c) and (d) are no longer satisfiable because the response speed of liquid crystal is slowed down on account of change in an environmental temperature or the like, the control circuit 44 may suspend the sub frame display and start to drive the liquid crystal panel in normal hold display.
With this, the display method of the liquid crystal panel can be switched to normal hold display in case where whitish appearance is adversely conspicuous due to sub frame display.
In the present example, low luminance is attained in such a manner that black display is performed in the first sub frame and grayscale expression is carried out only in the second sub frame.
Alternatively, similar image display is achieved when the anteroposterior relation between the sub frames is reversed (i.e. low luminance is attained in such a manner that black display is carried out in the second sub frame and grayscale expression is carried out only in the first sub frame).
In the present example, the luminance grayscales (signal grayscales) of the display signals (first-stage display signal and second-stage display signal) are set based on the equation (1).
In an actual panel, however, luminance is not zero even when black display (grayscale of 0) is carried out, and the response speed of liquid crystal is limited. On this account, these factors are preferably taken into account for the setting of signal grayscale. In other words, the following arrangement is preferable: an actual image is displayed on the liquid crystal panel and the relationship between a signal grayscale and display luminance is actually measured, and LUT (output table) is determined to corresponds to the equation (1), based on the result of the actual measurement.
In the present example, α in the equation (6a) falls within the range of 2.2 to 3. Although this range is not strictly verified, it is considered to be more or less appropriate in terms of visual perception of humans.
When the data signal line drive circuit 3 of the image display device 1 of the present example is a data signal line drive circuit for normal hold display, a voltage signal is output to each pixel (liquid crystal) so that display luminance is attained by the equation (1) in which γ=2.2, in accordance with the signal grayscale (luminance grayscale of the display signal) to be input.
Even when sub frame display is adopted, the aforesaid data signal line drive circuit 3 outputs a voltage signal for normal hold display in each sub frame, in accordance with a signal grayscale to be input.
According to this method to output a voltage signal, however, the time integral value of luminance in one frame in the case of sub frame display may not be equal to the value in the case of normal hold display (i.e. a signal grayscale may not be properly expressed).
Therefore, for sub frame display the data signal line drive circuit 3 is preferably designed so as to output a voltage signal corresponding to divided luminance.
In other words, the data signal line drive circuit 3 is preferably designed so as to finely adjust a voltage (interelectrode voltage) applied to liquid crystal, in accordance with a signal grayscale.
It is therefore preferable that the data signal line drive circuit 3 is designed to be suitable for sub frame display so that the aforesaid fine adjustment is possible.
In the present example, the liquid crystal panel is a VA panel. However, this is not only the possibility. Alternatively, by using a liquid crystal panel in a mode different from the VA mode, whitish appearance can be restrained with sub frame display of the image display device 1 of the present example.
That is to say, sub frame display of the image display device 1 of the present example makes it possible to restrain whitish appearance in a liquid crystal panel in which actual luminance (actual brightness) deviates from planned luminance (planned brightness) when a viewing angle is large (i.e. a liquid crystal panel which is in a mode in which grayscale gamma characteristic change in accordance with viewing angles).
In particular, the sub frame display of the image display device 1 of the present example is effective for a liquid crystal panel in which display luminance increases as the viewing angle is increased.
A liquid crystal panel of the image display device 1 of the present example may be normally black or normally white.
Also, the image display device 1 of the present example may use other display panel (e.g. organic EL panel and plasma display panel), instead of a liquid crystal panel.
In the present example, one frame is preferably divided in the ratio of 1:3 to 1:7. Alternatively, the image display device 1 of the present example may be designed so that one frame is divided in the ratio of 1:n or n:1 (n is a natural number not less than 1).
In the present example, signal grayscale setting of display signals (first-stage display signal and second-stage display signal) is carried out by using the aforesaid equation (10).
This setting, however, assumes that the response speed of liquid crystal is 0 ms and T0 (minimum luminance)=0. The setting is preferably further refined for actual use.
The maximum luminance (threshold luminance) to be output in one sub frame (second sub frame) is Tmax/(n+1), if the liquid crystal response is 0 ms and T0=0. The threshold luminance grayscale Lt is equal to the frame grayscale of the maximum luminance.

Lt=((Tmax/(n+1)−T0)/(Tmax−T0))^(1/γ)

(γ=2.2, T0=0)

In case where the response speed of liquid crystal is not 0, the threshold luminance (luminance at Lt) is represented as follows, provided that response from black to white is Y % in a sub frame, response from white to black is Z % in a sub frame, and T0=T0.

Tt=((Tmax−T0)×Y/100+(Tmax−T0)×Z/100)/2

Therefore, the following equations holds true.

Lt=((Tt−T0)/(Tmax−T0))^(1/γ)

(γ=2.2)

Lt may be little more complicated in practice, and the threshold luminance Tt may not be expressed by a simple equation. On this account, it is sometimes difficult to express Lt by Lmax.
To work out Lt in such a case, a result of measurement of luminance of a liquid crystal panel is preferably used. That is, luminance of a liquid crystal panel, in case where maximum luminance is attained in one sub frame whereas minimum luminance is attained in the other sub frame, is measured, and this measured luminance is set as Tt. Spilled luminance Lt is determined based on the following equations.

Lt=((Tt−T0)/(Tmax−T0))^(1/γ)

(γ=2.2)

This Lt figured out by using the equation (10) is an ideal value, and is sometimes preferably used as a standard.
The above-described case is a model of display luminance of the present embodiment, and terms such as “Tmax/2”, “maximum luminance”, and “minimum luminance” are used for simplicity. Actual values may be varied to some extent, to realize smooth greyscale expression, user's preferred specific gamma characteristic, or the like. That is to say, the improvement in the quality of moving images and a viewing angle is obtained when display luminance is lower than threshold luminance, on condition that luminance in one frame is sufficiently darker than luminance in the other frame. Therefore, effects similar to the above can be obtained by an arrangement such that, at Tmax/2, for example, the ratios such as minimum luminance (10%) and maximum luminance (90%) and around these values appropriately change in series. The following descriptions also use similar expressions for the sake of simplicity, but the present invention is not limited to them.
In the image display device 1 of the present example, the polarity is preferably reversed in each frame cycle. The following will give details of this.
FIG. 16(a) is a graph showing the luminance attained in the first and second sub frames, in case where display luminance is 3⁄4 and 1⁄4 of Lmax.
As shown in the figure, in sub frame display as in the present example, voltages applied to liquid crystal (i.e. a value of voltage applied to the space between pixel electrodes; absolute value) are different between sub frames.
Therefore, in case where the polarity of the voltage (liquid crystal voltage) applied to liquid crystal is reversed in each sub frame, the applied liquid crystal voltage is one-sided (i.e. the total applied voltage is not 0V) because of the difference in voltage values in the first and second sub frames, as shown in FIG. 16(b). The DC component of the liquid crystal voltage cannot therefore be cancelled, and hence problems such as burn-in and flicker may occur when the liquid crystal panel is driven for a long period of time, because the electrodes are electrically charged.
For this reason, in the image display device 1 of the present example, the polarity of the liquid crystal voltage is preferably reversed in each frame cycle.
There are two ways to reverse the polarity of the liquid crystal voltage in each frame cycle. The first way is such that a voltage with a single polarity is applied for one frame.
According to the other way, the polarity of the liquid crystal voltage is reversed between two sub frames, and the polarity in the second sub frame is arranged to be identical with the polarity in the first sub frame of the directly subsequent frame.
FIG. 17(a) is a graph showing the relationship among voltage polarities (polarities of liquid crystal voltage), frame cycles, and liquid crystal voltages, in case where the former way is adopted. On the other hand, FIG. 17(b) shows the same relationship in case where the latter way is adopted.
As these graphs show, in case where the liquid crystal voltage is reversed in each frame cycle, the total voltage in the first sub frames in neighboring two frames and the total voltage in the second sub frames in neighboring two frames can be set at 0V. Therefore, since the total voltage in two frames can be set at 0V, it is possible to cancel the DC component of the applied voltage.
In this manner, the liquid crystal voltage is alternated in each frame period. It is therefore possible to prevent burn-in, flicker or the like even if liquid crystal voltages in respective sub frames are significantly different from one another.
FIGS. 18(a)-18(d) show four sub pixels SPIX in the liquid crystal panel and polarities of liquid crystal voltages on the respective sub pixels SPIX.
As described above, the polarity of a voltage applied to one sub pixel SPIX is preferably reversed in each frame period. In the present case, the polarity of the liquid crystal voltage on each sub pixel SPIX varies, in each frame period, in the order of FIG. 18(a), FIG. 18(b), FIG. 18(c), and FIG. 18(d).
The sum total of liquid crystal voltages applied to all sub pixels SPIX of the liquid crystal panel is preferably controlled to be 0V. This control is achieved, for example, in such a manner that the voltage polarities between the neighboring sub pixels SPIX are set so as to be different as shown in FIGS. 18(a)-18(d).
It has been described that a preferable ratio (frame division ratio) between the first sub frame period and the second sub frame period is 3:1 to 7:1. Alternatively, the ratio between the sub frames may be set at 1:1 or 2:1.
For example, in case where a frame is divided in the ratio of 1:1, as shown in FIG. 6, actual luminance is close to planned luminance in comparison with normal hold display. Also, as shown in FIG. 9, actual brightness is close to planned brightness in comparison with the normal hold display.
In this case, the viewing angle characteristic is clearly improved as compared to the normal hold display.
In the liquid crystal panel, a certain time in accordance with the response speed of liquid crystal is required for causing the liquid crystal voltage (voltage applied to the liquid crystal; interelectrode voltage) to reach a value corresponding to the display signal. Therefore, in case where one of the sub frame periods is too short, the voltage of the liquid crystal may not reach the value corresponding to the display signal, within the sub frame periods.
It is possible to prevent one of the first sub frame period and the second sub frame period from being too short, by setting the ratio between the sub frame periods at 1:1 or 2:1. On this account, image display is suitably performed even if liquid crystal with a slow response speed is adopted.
The ratio of frame division (ratio between the first sub frame and the second sub frame) may be set at n:1 (n is a natural number not less than 7).
The ratio of division may be set at n:1 (n is a real number not less than 1, more preferably a real number more than 1). For example, the viewing angle characteristic is improved by setting the ratio of division at 1.5:1, as compared to the case where the ration is set at 1:1. Also, as compared to the case where the ratio is set at 2:1, a liquid crystal material with a slow response speed can be easily used.
In case where the ratio of frame division is set at n:1 (n is a real number not less than 1), to display an image with low luminance (low brightness) up to maximum luminance/(n+1) (Tmax/(n+1)), image display is preferably performed in such a manner that black display is attained in the first sub frame and luminance is adjusted only in the second sub frame.
On the other hand, to display an image with high luminance (high brightness) not lower than Tmax/(n+1), image display is preferably carried out in such a manner that white display is carried out in the second sub frame and luminance is adjusted only in the first sub frame.
With this, it is possible to always keep actual luminance and planned luminance to be equal in one sub frame. The viewing angle characteristic of the image display device 1 of the present example is therefore good.
In case where the ratio of frame division is n:1, substantially same effects are obtained when the first frame is set at n and when the second frame is set at n. In other words, the case of n:1 is identical with the case of 1:n, in terms of the improvement in the viewing angle characteristic.
The arrangement in which n is a real number not less than 1 is effective for the control of luminance grayscale using the aforesaid equations (10)-(12).
In the present example, the sub frame display in regard to the image display device 1 is arranged such that one frame is divided into two sub frames. Alternatively, the image display device 1 may be designed to perform sub frame display in which a frame is divided into three or more sub frames.
In the case of sub frame display in which a frame is divided into s sub frames, when luminance is very low, black display is carried out in s−1 sub frames and luminance (luminance grayscale) is adjusted only in one sub frame. If the luminance is too high to be reproduced in one sub frame, white display is carried out in this sub frame, black display is carried out in s−2 sub frames, and luminance is adjusted in the remaining one sub frame.
In other words, also in the case of dividing a frame into s sub frames, it is preferable that luminance is adjusted (changed) only in one sub frame and white display or black display is carried out in the remaining sub frames. As a result of this, actual luminance and planned luminance are equal in s−1 sub frames It is therefore possible to improve the viewing angle characteristic of the image display device 1.
FIG. 19 is a graph showing both (i) the results (doted line and full line) of display with frame division into equal three sub frames and (ii) results (dashed line and full line; identical with those shown in FIG. 5) of normal hold display, in the image display device 1 of the present example.
As shown in the graph, in case where three sub frames are provided, actual luminance is significantly close to planned luminance. It is therefore possible to further improve the viewing angle characteristic of the image display device 1 of the present example.
Among the sub frames, the sub frame in which the luminance is adjusted is preferably arranged so that a temporal barycentric position of the luminance of the sub pixel in the frame period is close to a temporal central position of the frame period.
For example, in case where the number of sub frames is three, image display is performed by adjusting the luminance of the central sub frame, if black display is performed in two sub frames. If the luminance is too high to be represented in that sub frame, white display is performed in the sub frame (central sub frame) and the luminance is adjusted in the first or last sub frame. If the luminance is too high to be represented in that sub frame and the central sub frame (white display), the luminance is adjusted in the remaining sub frame.
According to the arrangement above, the temporal barycentric position of the luminance of the sub pixel in one frame period is set so as to be close to the temporal central position of said one frame period. The quality of moving images can therefore be improved because the following problem is prevented: on account of a variation in the temporal varycentric position, needless light or shade, which is not viewed in a still image, appears at the anterior end or the posterior end of a moving image, and hence the quality of moving images is deteriorated.
The polarity reversal drive is preferably carried out even in a case where a frame is divided into s sub frames. FIG. 20 is a graph showing transition of the liquid crystal voltage in case where the voltage polarity is reversed in each frame.
As shown in this figure, the total liquid crystal voltage in this case can be set at 0V in two frames.
FIG. 21 is a graph showing transition of the liquid crystal voltage in case where a frame is divided into three sub frames and the voltage polarity is reversed in each sub frame.
In this way, when a frame is divided into an odd-number of sub frames, the total liquid crystal voltage in two frames can be set at 0V even if the voltage polarity is reversed in each sub frame.
Therefore, in case where a frame is divided into s sub frames (s is an integer not less than 2), s-th sub frames in respective neighboring frames are preferably arranged so that respective liquid crystal voltages with different polarities are supplied. This allows the total liquid crystal voltage in two frames to be set at 0V.
In case where a frame is divided into s sub frames (s is an integer not less than 2), it is preferable that the polarity of the liquid crystal voltage is reversed in such a way as to set the total liquid crystal voltage in two frames (or more than two frames) to be 0V.
In the case above, in case where a frame is divided into s sub frames, the number of sub frame in which luminance is adjusted is always 1 and white display (maximum luminance) or black display (minimum luminance) is carried out in the remaining sub frames.
Alternatively, luminance may be adjusted in two or more sub frames. Also in this case, the viewing angle characteristic can be improved by performing white display (maximum luminance) or black display (minimum luminance) in at least one sub frame.
Alternatively, the luminance in a sub frame in which luminance is not adjusted may be set at not the maximum luminance but a value larger than the maximum or second predetermined value. Also, the luminance may be set at not the minimum luminance but a value which is smaller than the minimum or first predetermined value.
This can also sufficiently reduce the deviance (brightness deviance) of actual brightness from planned brightness in a sub frame in which luminance is not adjusted. It is therefore possible to improve the viewing angle characteristic of the image display device 1 of the present example.
FIG. 22 is a graph showing the relationship (viewing angle grayscale properties; actually measured) between a signal grayscale (%; luminance grayscale of a display signal) output to the panel 11 and an actual luminance grayscale (%) corresponding to each signal grayscale, in a sub frame in which luminance is not adjusted.
The actual luminance grayscale is worked out in such a manner that luminance (actual luminance) attained by the liquid crystal panel of the panel 11 in accordance with each signal grayscale is converted to a luminance grayscale by using the aforesaid equation (1).
As shown in the graph above, the aforesaid two grayscales are equal when the liquid crystal panel is viewed head-on (viewing angle of 0°). On the other hand, when the viewing angle is 60°, the actual luminance grayscale is higher than the signal grayscale in intermediate luminance, because of whitish appearance. The whitish appearance is maximized when the luminance grayscale is 20% to 30%, irrespective of the viewing angle.
It has been known that, in regard to the whitish appearance, the quality of image display by the image display device 1 of the present example is sufficient (i.e. the deviance in brightness is sufficiently small) when the whitish appearance is not higher than the “10% of the maximum value” in the graph, which is indicated by the dotted line. The ranges of signal grayscales in which the whitish appearance is not higher than the “10% of the maximum value” is 80-100% of the maximum value of the signal grayscale and 0-0.02% of the maximum value of the signal grayscale. These ranges are consistent even if the viewing angle changes.
The aforesaid second predetermined value is therefore preferably set at 80% of the maximum luminance, whereas the first predetermined value is preferably set at 0.02% of the maximum luminance.
Also, it may be unnecessary to provide a sub frame in which luminance is not adjusted. In other words, in case where image display is performed with s sub frames, it is unnecessary to set the display states of the respective sub frames to be different from one another. Even in such an arrangement, the aforesaid polarity reversal drive in which the polarity of the liquid crystal voltage is reversed in each frame is preferably carried out.
In case where image display is carried out with s sub frames, the viewing angle characteristic of the liquid crystal panel can be improved even by slightly differentiating the display states of the respective sub frames from one another.
Second Embodiment
In the embodiment above, the modulation processing section 31 which performs the grayscale transition emphasizing process is provided in the stage prior to the sub frame processing section 32 which performs frame division and gamma process. In the present embodiment, on the other hand, the modulation processing section is provided in the stage directly subsequent to the sub frame processing section.
As shown in FIG. 23, a signal processing circuit 21a of the present embodiment is provided with a modulation processing section 31a and a sub frame processing section 32a, whose functions are substantially identical with those of the modulation processing section 31 and the sub frame processing section 32 shown in FIG. 1. It is noted that the sub frame processing section 32a of the present embodiment is provided in the stage directly prior to the modulation processing section 31a, and frame division and gamma correction are conducted with respect to video data D (i, j, k) before correction, instead of video data Do (i, j, k) after correction. As a result, sets of video data S1 (i, j, k) and S2 (i, j, k) in the respective sub frames SFR1 (k) and SFR1 (k), which sets of video data correspond to the video data D (i, j, k), are output.
Because of the change in the circuit configuration, the modulation processing section 31a corrects, instead of video data D (i, j, k) before correction, sets of video data S1 (i, j, k) and S2 (i, j, k) to emphasize grayscale transition, and output the corrected video data as sets of video data S1o (i, j, k) and S2o (i, j, k) constituting a video signal DAT2. Being similar to the aforesaid sets of video data So1 (i, j, k) and So2 (i, j, k), the sets of video data S1o (i, j, k) and S2o (i, j, k) are transmitted by time division. 
Correction and prediction by the modulation processing section 31a are performed in units of sub frame. The modulation processing section 31a corrects video data So (i, j, x) of the current sub frame (x) based on (1) a predicted value E (i, j, x−1) of the previous sub frame SFR (x−1), which is read out from a frame memory (not illustrated) and (2) video data So (i, j, x) in the current sub frame SFR (x), which is supplied to the sub pixel SPIX (i, j). The modulation processing section 31a predicts a value indicating a grayscale which corresponds to luminance to which the sub pixel SPIX (i, j) is assumed to reach at the start of the next sub frame SFR (x+1), based on the predicted value E (i, j, x−1) and the video data So (i, j, x). The modulation processing section 31a then stores the predicted value E (i, j, x) in the frame memory.
Before describing an example in which writing speed is decreased, the following will discuss, in reference to FIG. 24, a case where the modulation processing section 31a is constructed using the same circuits as those in FIG. 8.
The modulation processing section 31b of the present example includes members 51a-53a for generating the aforesaid video data S1o (i, j, k) and members 51b-53b for generating the aforesaid video data S2o (i, j, k). These members 51a-53a and 51b-53b are substantially identical with the members 51-53 shown in FIG. 8.
Correction and prediction, however, are performed in units of sub frame. On this account, the members 51a-53b are designed so as to be capable of operating at a speed twice as fast as the members in FIG. 8. Also, values stored in the respective LUTs (not illustrated in FIG. 24) are different from those in the LUTs shown in FIG. 8.
Instead of the video data D (i, j, k) of the current frame FR (k), the correction processing section 52a and the prediction processing section 53a receive video data S1 (i, j, k) supplied from the sub frame processing section 32a. The correction processing section 52a outputs the corrected video data as video data S1o (i, j k). Similarly, instead of the video data D (i, j, k) of the current frame FR (k), the correction processing section 52b and the prediction processing section 53b receive video data S2 (i, j, k) supplied from the sub frame processing section 32a. The correction processing section 52a outputs the corrected video data as video data S2o (i, j, k). In the meanwhile, the prediction processing section 53a outputs a predicted value E1 (i, j, k) not to a frame memory 51a that the correction processing section 52a refers to but to a frame memory 51b that the correction processing section 52b refers to. The prediction processing section 53b outputs a predicted value E2 (i, j, k) to the frame memory 51a. 
The predicted value E1 (i, j, k) indicates a grayscale corresponding to luminance to which the sub pixel SPIX (i, j) is assumed to reach at the start of the next sub frame SFR2 (k), when the sub pixel SPIX (i, j) is driven by video data S1o (i, j, k) supplied from the correction processing section 52a. The prediction processing section 53a predicts the predicted value E1 (i, j, k), based on the video data S1 (i, j, k) of the current frame FR (k) and the predicted value E2 (i, k, k−1) of the previous frame FR (k−1), which value is read out from the frame memory 51a. Similarly, the predicted value E2 (i, j, k) indicates a grayscale corresponding to luminance to which the sub pixel SPIX (i, j) is assumed to reach at the start of the next sub frame SFR1 (k+1), when the sub pixel SPIX (i, j) is driven by video data S2o (i, j, k) supplied from the correction processing section 52b. The prediction processing section 53b predicts a predicted value E2 (i, j, k), based on the video data S2 (i, j, k) of the current frame FR (k) and the predicted value E1 (i, j, k) read out from the frame memory 51b. 
In the arrangement above, as shown in FIG. 25, when sets of video data D (1, 1, k) to D (n, m, k) of a frame FR (k) are supplied to the signal processing circuit 21a, these sets of video data D (1, 1, k) to D (n, m, k) are stored in a frame memory 41 (FM in the figure) of the sub frame processing section 32a (during a time period from t11 to t12). The control circuit 44 of the sub frame processing section 32a reads out these sets of video data D (1, 1, k) to D (n, m, k) twice in each frame (during a time period from t11 to t13). In the first read out, the control circuit 44 outputs sets of video data S1 (1, 1, k) to S1 (n, m, k) for the sub frame SFR1 (k) in reference to the LUT 42 (in a time period of t11-t12). In the second read out, the control circuit 44 outputs sets of video data S2 (1, 1, k) to S2 (n, m, k) for the sub frame SFR2 (k) for the sub frame SFR2 (k), in reference to the LUT 43 (in a time period of t12-t13). By providing a buffer memory, it is possible to adjust the time difference between a time t1 at which the signal processing circuit 21a receives the first set of video data D (1, 1, k) and a time t11 at which a set of video data S1 (1, 1, k) for the sub frame SFR1 (k), which data corresponds to the foregoing video data D (1, 1, k), is output. FIG. 25 shows a case where the time difference is a half of one frame (one sub frame), for example.
On the other hand, in the time period of t11 to t12, the frame memory 51a of the modulation processing section 31b stores predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) which are updated in reference to sets of video data S2 (1, 1, k−1) to S2 (n, m, k−1) of the sub frame SFR2 (k−1) in the previous frame FR (k−1). The correction processing section 52a corrects sets of video data S1 (1, 1, k) to S1 (n, m, k) in reference to the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1), and outputs the corrected vide data as sets of corrected video data S1o (1, 1, k) to S1o (n, m, k). In a similar manner, the prediction processing section 53a generates predicted values E1 (1, 1, k) to predicted value E1 (n, m, k) and stores them in the frame memory 51b, based on the sets of video data S1 (1, 1, K) to S1 (n, m, k) and the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1).
Similarly, in the time period of t12 to t13, the correction processing section 52b corrects sets of video data S2 (1, 1, k) to S2 (n, m, k) with reference to the predicted values E1 (1, 1, k) to E1 (n, m, k), and outputs the corrected video data as sets of corrected video data S2o (1, 1, k) to S2o (n, m, k). The prediction processing section 53b generates predicted values E2 (1, 1, k) to E2 (n, m, k) based on the sets of video data S2 (1, 1, k) to S2 (n, m, k) and the predicted values E1 (1, 1, k−1) to E1 (n, m, k−1), and stores the generated values in the frame memory 51a. 
Strictly speaking, in case where a buffer is provided between each pair of neighboring circuits for a delay of each circuit or timing adjustment, timings at which the former-stage circuit outputs data is different from timings at which the latter-stage circuit outputs data, because of a delay in the buffer circuit, or the like. In FIG. 25 or FIG. 27, which will be described later, illustration of the delay is omitted.
In this way, the signal processing circuit 21a of the present embodiment performs correction (emphasis of grayscale transition) and prediction in units of sub frame. Prediction can therefore be performed precisely as compared to the first embodiment in which the aforesaid processes are performed in units of frame. It is therefore possible to emphasize the grayscale transition with higher precision. As a result, deterioration of image quality on account of inappropriate grayscale transition emphasis is restrained, and the quality of moving images is improved.
Most of the members constituting the signal processing circuit 21a of the present embodiment are typically integrated in one integrated circuit chip, for the sake of speed-up. However, each of the frame memories 41, 51a, and 51b requires storage capacity significantly larger than a LUT, and hence cannot be easily integrated into an integrated circuit. The frame memories are therefore typically connected externally to the integrated circuit chip.
In this case, the data transmission paths for the frame memories 41, 51a and 51b are external signal lines. It is therefore difficult to increase the transmission speed as compared to a case where transmission is performed within the integrated circuit chip. Moreover, when the number of signal lines is increased to increase the transmission speed, the number of pins of the integrated circuit chip is also increased, and hence the size of the integrated circuit is significantly increased. Also, since the modulation processing section 31b shown in FIG. 24 is driven at a doubled clock, each of the frame memories 41, 51a, and 51b must have a large capacity and be able to operate at a high speed.
The following will give details of the transmission speed. As shown in FIG. 25, sets of video data D (1, 1, k) to D (n, m, k) are written into the frame memory 41 once in each frame. The frame memory 41 outputs sets of video data D (1, 1, k) to D (n, m, k) twice in each frame. Therefore, provided that, as in the case of a typical memory, processes of writing and reading share the same signal line for data transmission, the frame memory 41 is required to support access with a frequency of not less than three times as high as a frequency f at the time of transmission of sets of video data D for a video signal DAT. In FIG. 25, an access speed required in writing or reading is expressed in such a way that, after an alphabet (r/w) indicating reading/writing, a magnification is indicated such as r:2, assuming that the access speed required for reading or writing in the frequency f is 1.
On the other hand, to/from the frame memories 51a and 51b, the predicted values E2 (1, 1, k) to E2 (n, m, k) and the predicted values E1 (1, 1, k) to E1 (n, m, k) are written/read out once in each frame. In the arrangement of FIG. 24, as shown in FIG. 25, a time period for readout from the frame memory 51a (e.g. t11 to t12) is different from a time period for readout from the frame memory 51b (e.g. t12 to t13), and each of these time periods is half as long as one frame. Similarly, each of time periods for writing into the respective frame memories 51a and 51b is half as long as one frame. On this account, the frame memories 51a and 51b must support an access speed four times higher than the frequency f.
As a result, in case where the modulation processing section 31b shown in FIG. 24 is adopted, the frame memories 41, 51a, and 51b are required to support a higher access speed. This causes problems such that the manufacturing costs of the signal processing circuit 21a is significantly increased, and the size and the number of pins of the integrated circuit chip are increased because of the increase in signal lines.
On the other hand, in the signal processing circuit 21 of another example of the present embodiment, as shown in FIG. 27, sets of video data S1 (1, 1, k) to S1 (s, m, k), sets of video data S2 (1, 1, k) to S2 (n, m, k), and predicted values E1 (1, 1, k) to E1 (n, m, k) are generated twice in each frame, and a half of processes of generation and output of the predicted values E2 (1, 1, k) to E2 (n, m, k) is thinned out and the predicted values E2 (1, 1, k) to E2 (n, m, k) is stored in the frame memory once in each frame. The frequency of writing in the frame memory is reduced in this way.
More specifically, in the signal processing circuit 21c of the present example, the sub frame processing section 32c can output sets of video data S1 (1, 1, k) to S1 (n, m, k) and sets of video data S2 (1, 1, k) to S2 (n, m, k) twice in each frame.
That is to say, the control circuit 44 of the sub frame processing section 32a shown in FIG. 23 stops outputting sets of video data S2 (1, 1, k) to S2 (n, m, k) while outputting sets of video data S1 (1, 1, k) to S1 (n, m, k). On the other hand, as shown in FIG. 27, the control circuit 44c of the sub frame processing section 32c of the present example outputs sets of video data S2 (1, 1, k) to S2 (n, m, k) even while outputting sets of video data S1 (1, 1, k) to S1 (n, m, k) (in a time period of t21-t22), and also outputs sets of video data S1 (1, 1, k) to S1 (n, m, k) even while outputting sets of video data S2 (1, 1, k) to S2 (n, m, k) (in a time period of t22-t23).
The sets of video data S1 (i, j, k) and S2 (i, j, k) are generated based on the same value, i.e. the video data D (i, j, k). Therefore, the control circuit 44c generates the sets of video data S1 (i, j, k) and S2 (i, j, k) based on one set of video data D (i, j, k), each time one set of video data D (i, j, k) from the frame memory 41 is read out. This makes it possible to prevent an amount of data transmission between the frame memory 41 and the control circuit 44c from being increased. An amount of data transmission between the sub frame processing section 32c and the modulation processing section 31c is increased as compared to the arrangement shown in FIG. 24. No problem, however, is caused by this increase, because the transmission is carried out within the integrated circuit chip.
On the other hand, as shown in FIG. 26, the modulation processing section 31c of the present example includes a frame memory (predicted value storage means) 54 in place of frame memories 51a and 51b which store respective predicted values E1 and E2 for one sub frame. The frame memory 54 stores predicted values E2 for two sub frames and outputs the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) twice in each frame. The modulation processing section 31c of the present example is provided with members 52c, 52d, 53c, and 53d which are substantially identical with the members 52a, 52b, 53a, and 53d shown in FIG. 24. In the present example, these members 52c, 52d, 53c, and 53d correspond to correction means recited in claims.
However, being different from the arrangement shown in FIG. 24, predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) to the correction processing section 52c and the prediction processing section 53c are supplied not from the frame memory 41a but from the frame memory 54. Predicted values E1 (1, 1, k) to E1 (n, m, k) to the correction processing section 52d and the prediction processing section 53d are supplied not from the frame memory 41b but from the prediction processing section 53c. 
Also, as discussed above, in each frame, the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) and sets of video data S1 (1, 1, k) to S1 (n, m, k) are output twice, and the prediction processing section 53c generates, as shown in FIG. 26, the predicted values E1 (1, 1, k) to E1 (n, m, k) and output them, twice in each frame. Although the number of predicted values E1 which are output in each frame is different, the prediction process and the circuit configuration of the prediction processing section 53c are identical with those of the prediction processing section 53a shown in FIG. 24.
Also, in each frame, predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) and sets of video data S1 (1, 1, k) to S1 (n, m, k) are output twice. The correction processing section 52c generates and outputs sets of corrected video data S1o (1, 1, k) to S1o (n, m, k) (during a time period of t21-t22), based on the predicted values output in the first time. Furthermore, predicted values E1 (1, 1, k) to E1 (n, m, k) and sets of video data S2 (1, 1, k) to S2 (n, m, k) are output twice in each frame, and the correction processing section 52d generates and outputs sets of corrected video data S2o (1, 1, k) to S2o (n, m, k) (during a time period of t22 to t23), based on the predicted values and sets of video data output in the second time.
Since the sets of video data S2 (1, 1, k) to S2 (n, m, k) and the predicted values E1 (1, 1, k) to E1 (n, m, k) are output twice in each frame, predicted values E2 (1, 1, k) to E2 (n, m, k) can be generated twice in each frame. However, in the prediction processing section 53d of the present example, a half of the predicted values E2 (1, 1, k) to E2 (n, m, k) and the processes of generation and output of the predicted values E2 (1, 1, k) to E2 (n, m, k) are thinned out, and predicted values E2 (1, 1, k) to E2 (n, m, k) are generated and output once in each frame. Timings to generate and output the predicted values E2 in each frame are different from the above, but the prediction process is identical with that of the prediction processing section 53b shown in FIG. 24. The circuit configuration is substantially identical with the prediction processing section 53b, but a circuit to determine a timing to perform the thin-out and to thin out the generation processes and the output processes is additionally provided.
As an example of the thin-out, the following will describe an arrangement in which the prediction processing section 53d thins out every other generation processes and output processes, in case where the time ratio between the sub frames SFR1 and SFR1 is 1:1. More specifically, during a time period (of t21 to t22) in which video data S2 (i, j, k) and a predicted value E1 (i, j, k) for the first time are output, the prediction processing section 53d generates a predicted value E2 (i, j, k) based on a predetermined odd-number-th or even-number-th set of video data S2 (i, j, k) and predicted value E1 (i, j, k). On the other hand, in a time period (t22 to t23) in which a video data S2 (i, j, k) and a predicted value E1 (i, j, k) for the second time is output, the prediction process section 53d generates a predicted value E (i, j, k) based on the remaining video data and predicted value. With this, the prediction processing section 53d can output all predicted values E2 (1, 1, k) to E2 (n, m, k) once in each frame, and the time length required for outputting the predicted value E2 (i, j, k) is twice as long as the case of FIG. 24.
In the present arrangement, in each frame, the predicted values E2 (1, 1, k) to E2 (n, m, k) are written once in one frame period. It is therefore possible to reduce the access speed required by the frame memory 54 to 3⁄4 of the arrangement of FIG. 24. For example, in case of an XGA video signal, since the dot clock of each set of video data (i, j, k) is about 65 [MHz], the frame memories 51a and 51b shown in FIG. 24 must support an access with a dot clock four times higher than this, i.e. about 260 [MHz]. In the meanwhile, being similar to the frame memory 41, the frame memory 54 of the present example is required to support a dot clock only three times higher than the above, i.e. about 195 [MHz].
In the case above, the generation processes and output processes are alternately thinned out by the prediction processing section 53d of the present example when the time ratio between the sub frames SFR1 and SFR2 is 1:1. However, even if the time ratio is differently set, the access speed that the frame memory 54 is required to have can be decreased on condition that a half of the output processes is thinned out, in comparison with a case where the thin-out is not performed.
All storage areas (for two sub frames) of the frame memory 54 may be accessible with the aforesaid access speed but the frame memory 54 of the present example is composed of two frame memories 54a and 54b, and hence an access speed that one of these frame memories is required to have is further decreased.
More specifically, the frame memory 54 is composed of two frame memories 54a and 54b each of which can store predicted values E2 for one sub frame. To the frame memory 54a, a predicted value E2 (i, j, k) is written by the prediction processing section 53d. Predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) for one sub frame, which have been written in the previous frame FR (k−1), can be sent to the frame memory 54b, before these predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) are overwritten by predicted values E2 (1, 1, k) to E2 (n, m, k) of the current frame FR (k). Since reading/writing of predicted values E2 from/into the frame memory 54a in one frame period is only performed once, the frame memory 54a is required only to support an access with a frequency identical with the aforesaid frequency f.
On the other hand, the frame memory 54b receives the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1), and outputs the predicted values E2 (1, 1, k−1) to E2 (n, m, k−1) twice in each frame. In this case, in one frame period, it is necessary to write predicted values E2 for one sub frame once and read out these predicted values E2 twice. On this account, it is necessary to support an access with a frequency three times higher than the frequency f.
In the arrangement above, the predicted values E2 stored in the frame memory 54a by the prediction processing section 53d are sent to the frame memory 54b which is provided for outputting the predicted values E2 to the correction processing section 52c and the prediction processing section 53c. On this account, among the storage areas of the frame memory 54, an area where reading is carried out twice in each frame is limited to the frame memory 54b having a storage capacity for one sub frame. FIG. 27 shows an example in which sending from the frame memory 54a to the frame memory 54b is shifted for one sub frame, in order to reduce a storage capacity required for buffer.
As a result, as compared to the case where all storage areas of the frame memory 54 can respond to a frequency three times higher than the frequency f, it is possible to reduce the size of the storage areas which can respond to an access with a frequency three times higher than the frequency f, and hence the frame memory 54 can be provided easily and with lower costs.
In the case above, generation processes and output processes of predicted values E2 are thinned out in the prediction processing section 53d. Alternatively, only output processes may be thinned out. In this case, predicted values E1 (1, 1, k) to E1 (n, m, k) and sets of video data S2 (1, 1, k) to S2 (n, m, k) are generated in such a way as to generate predicted values E2 (1, 1, k) to E2 (n, m, k) twice in each frame period, and generation processes and output processes of predicted values E2 based on the generated predicted values are thinned out so that timings to generate the predicted values E2 (1, 1, k) to E2 (n, m, k) are dispersed across one frame period. Alternatively, the following arrangement may be used.
The modulation processing section includes: correction processing sections 52c and 52d which correct plural sets of video data S1 (i, j, k) and S2 (i, j, k) generated in each frame period and output sets of corrected video data S1o (i, j, k) and S2o (i, j, k) corresponding to respective sub frames SFR1 (k) and SFR2 (k) constituting the frame period, the number of sub frames corresponding to the number of aforesaid plural sets of video data; and a frame memory 54 which stores a predicted value E2 (i, j, k) indicating luminance that the sub pixel SPIX (i, j) reaches at the end of the period in which the sub pixel SPIX (i, j) is driven by corrected video data S2o (i, j, k) corresponding to the last sub frame SFR2 (k). When video data S1 (i, j, k) or S2 (i, j, k), which is the target of correction, corresponds to the first sub frame SFR1 (k) (i.e. in the case of video data S1 (i, j, k)), the correction processing section 52c corrects the video data S1 (i, j, k) in such a way as to emphasize the grayscale transition from the luminance indicated by the predicted value E2 (i, j, k−1) read out from the frame memory 54 to the luminance indicated by the video data S1 (i, j, k). Also, when video data S1 (i, j, k) or S2 (i, j, k), which is the target of correction, corresponds to the second sub frame or one of the subsequent sub frames (i.e. in the case of video data S2 (i, j, k)), the prediction processing section 53c of the modulation processing section and the correction processing section 52d predict the luminance of the sub pixel SPIX (i, j) at the start of the sub frame SFR2 (k), based on the video data S2 (i, j, k), the video data S1 (i, j, k) corresponding to the previous sub frame SFR1 (k), and the predicted value E2 (i, j, k−1) stored in the frame memory 54, and then correct the video data S2 (i, j, k) in such a way as to emphasize the grayscale transition from the predicted luminance (i.e. luminance indicated by E1 (i, j, k)) to the luminance indicated by the video data S2 (i, j, k). Furthermore, when video data S1 (i, j, k) or S2 (i, j, k), which is the target of correction, corresponds to the last sub frame SFR2 (k) (i.e. in the case of video data S2 (i, j, k)), the prediction processing sections 53c and 53d in the modulation processing section predict the luminance of the sub pixel SPIX (i, j) at the end of the sub frame SFR2 (k) corresponding to the video data S2 (i, j, k) which is the target of correction, based on the video data S2 (i, j, k), the video data S1 (i, j, k) corresponding to the previous sub frame SFR1 (k), and the predicted value E2 (i, j, k−1) stored in the frame memory 54, and then stores the predicted value E2 (i, j, k), which indicates the result of the prediction, in the frame memory 54.
In the arrangement above, being different from the arrangement shown in FIG. 24, the sets of video data S1 (i, j, k) and S2 (i, j, k) can be corrected without each time storing, in the frame memory, the results E1 (i, j, k) and E2 (i, j, k) of the prediction of the luminance that the sub pixel SPIX (i, j) reaches at the end of the sub frame SFR2 (k−1) and the sub frame SFR1 (k−1) which are directly prior to the sub frames SFR1 (k) and SFR2 (k) corresponding to the sets of video data S1 (i, j, k) and S2 (i, j,k).
As a result, an amount of data of predicted values stored in the frame memory in each frame period is reduced as compared to a case where the result of prediction in each sub frame is each time stored in the frame memories (51a and 51b) as shown in FIG. 24. Because of the reduction in data amount, even in a case, for example, where the access speed that the frame memory is required to have is reduced by providing buffer or the like, the reduction in the access speed can be achieved by providing a smaller circuit.
As shown in FIG. 26, however, it is possible to reduce the access speed that the frame memory is required to have without providing new buffer, by an arrangement such that the prediction processing section 53d thins out a half of predicted values E2 (1, 1, k) to E2 (n, m, k) and generation processes and output processes of the predicted values E2.(1, 1, k) to E2 (n, m, k), and the predicted values E2 (1, 1, k) to E2 (n, m, k) are generated and output once in each frame.
In the arrangement above, in the pixel array 2, one pixel is constituted by sub pixels SPIX for respective colors, and hence color images can be displayed. However, effects similar to the above can be obtained even if the pixel array is a monochrome type.
In the arrangement above, the control circuit (44 and 44c) refers to the same LUT (42, 43) irrespective of changes in the circumstance of the image display device 1, an example of such changes is temperature change which causes temporal change in luminance of a pixel (sub pixel). Alternatively, the following arrangement may be adopted: plural LUTs corresponding to respective circumstances are provided, sensors for detecting circumstances of the image display device 1 are provided, and the control circuit determines, in accordance with the result of detection by the sensors, which LUT is referred to at the time of generation of video data for each sub frame. According to this arrangement, since video data for each sub frame can be changed in accordance with the circumstances, the display quality is maintained even if the circumstances change.
For example, the response characteristic and grayscale luminance characteristic of a liquid crystal panel change in accordance with an environmental temperature (temperature of an environment of the panel 11). For this reason, even if the same video signal DAT is supplied, an optimum value as video data for each sub frame is different in accordance with the environmental temperature.
Therefore, when the panel 11 is a liquid crystal panel, LUTs (42 and 43) suitable for respective temperature ranges which are different from each other are provided, a sensor for measuring the environmental temperature is provided, and the control circuit (44, 44c) switches the LUT to be referred to, in accordance with the result of the measurement of the environmental temperature by the sensor. With this, the signal processing section (21-21d) including the control circuit can generate a suitable video signal DAT2 even if the same video signal DAT is supplied, and send the generated video signal to the liquid crystal panel. On this account, image display with suitable luminance is possible in all envisioned temperature ranges (e.g. 0° C. to 65° C.).
In the arrangement above, the LUTs 42 and 43 store a gamma-converted value indicating video data of each sub frame so that the LUTs 42 and 43 function not only as the LUT 142 and 143 for time-division driving shown in FIG. 7 but also as the LUT 133a for gamma conversion.
Alternatively, in place of the LUTs 42 and 43, LUTs 142 and 143 identical with those in FIG. 7 and a gamma correction circuit 133 may be provided. The gamma correction circuit 133 is unnecessary if gamma correction is unnecessary.
In the arrangement above, the sub frame processing section (32, 32c) mainly divides one frame into two sub frames. Alternatively, in case where video data (input video data) periodically supplied to a pixel indicates luminance lower than a predetermined threshold, the sub frame processing section may set at least one of sets of video data (S1o and S2o; S1 and S2) for each sub frame at a value indicating luminance falling within a predetermined range for dark display, and may control the time integral value of luminance of the pixel in each frame period by increasing or decreasing at least one of the sets of remaining video data for each sub frame. Also, when the input video data indicates luminance higher than the predetermined threshold, the sub frame processing section may set at least one of the sets of video data for each sub frame at a value indicating luminance falling within a predetermined range for bright display, and may control the time integral value of luminance of the pixel in each frame period by increasing or decreasing at least one of the remaining video data for each sub frame.
With this arrangement, it is possible to provide, at least once in each frame period in most cases, a period in which luminance of the pixel is lower than those of other periods, and hence the quality of moving images is improved. In the case of bright display, luminance of the pixel in the periods other than the bright display period increases as the luminance indicated by input video data increases. On this account, it is possible to increase the time integral value of luminance of the pixel in the whole frame period as compared to a case where dark display is performed at least once in each frame period, and hence brighter image display is possible.
In the arrangement above, in a case of dark display, one of the aforesaid sets of output video data is set at a value indicating luminance for dark display. On this account, in the dark display period, it is possible to widen the range of viewing angles in which the luminance of the pixel falls within an allowable range. Similarly, in a case of bright display, since one of the sets of output video data is set at a value indicating luminance for dark display, it is possible to widen the range of viewing angles in which the luminance of the pixel falls within an allowable range, in the dark display period. As a result, problems such as whitish appearance are restrained in comparison with a case where time-division driving is not carried out, and the range of viewing angles is widened.
Also, as described in the embodiments above, when the number of the pixel is more than one, the following arrangement may be adopted in addition to the arrangement above: in accordance with input video data for each of the pixels, the generation means generates predetermined plural of sets of output video data supplied to each of the pixels, in response to each of the input cycles, the correction means corrects the sets of output video data to be supplied to each of the pixels and stores prediction results corresponding to the respective pixels in the prediction result storage section, the generation means generates, for each of the pixels, the predetermined number of sets of output video data to be supplied to the each of the pixels in each of the input cycles, and the correction section reads out, for each of the pixels, prediction results regarding the pixel predetermined number of times in each of the input cycles, and based on these prediction results and the sets of output video data, for each of the pixels, at least one process of writing of the prediction result is thinned out from processes of prediction of luminance at the end of the drive period and processes of storing the prediction result, which can be performed plural number of times in each of the input cycles.
In this arrangement, the number of sets of output video data generated in each input cycle is determined in advance, and the number of times the prediction results are read out in each input cycle is equal to the number of sets of output video data. On this account, based on the sets of output video data and the prediction results, it is possible to predict the luminance of the pixel at the end for plural times and store the prediction results. The number of the pixels is plural and the reading process and the generation process are performed for each pixel.
In the arrangement above, at least one process of writing of the prediction result is thinned out among the prediction processes and processes of storing prediction results which can be performed plural times in each input cycle.
Therefore, in comparison with the arrangement of no thin-out, it is possible to elongate the time interval of storing the prediction result of each pixel in the prediction result storage section, and hence the response speed that the prediction result storage section is required to have can be lowered.
An effect can be obtained by thinning out at least one writing process. A greater effect is obtained by reducing, for each pixel, the number of times of writing processes by the correction means to one in each input cycle.
Regardless of whether a writing process is thinned out or not, when the dark display period or bright display period is provided, as described in the embodiments, in addition to the above, sets of video data for the remaining sub frames other than a particular one set of video data are preferably set at a value indicating luminance falling within a predetermined range for dark display or a value indicating luminance falling within a predetermined range for bright display, and the time integral value of luminance of the pixel in one frame period is controlled by increasing or decreasing the particular set of video data.
According to this arrangement, among sets of video data for each sub frame, sets of video data other than the particular set of video data are set at a value indicating luminance falling within a predetermined range for dark display or a value indicating luminance falling within a predetermined range for bright display. On this account, problems such as whitish appearance are restrained and the range of viewing angles is increased, as compared to a case where sets of video data for plural sub frames are set at values falling within neither of the ranges above.
Video data for each sub frame is preferably set so that the temporal barycentric position of the luminance of the sub pixel in one frame period is set so as to be close to the temporal central position of said one frame period.
More specifically, in the sub frame processing section (32, 32c), in a region where luminance indicated by input video data is lowest, a set of video data corresponding to a sub frame closest to the temporal central position of the frame period, among sub frames constituting one frame period, is selected as the particular set of video data, and the time integral value of luminance of the pixel in one frame period is controlled by increasing or decreasing the value of the particular set of video data.
As the luminance indicated by input video data gradually increases and the predetermined sets of video data falls the predetermined range for bright display, the video data of that sub frame is set at a value falling within that range, and a set of video data which is closest to the temporal central position of the frame period, among the remaining sub frames, is selected as the particular set of video data, and the time integral value of luminance of the pixel in one frame period is controlled by increasing or decreasing the value of the particular set of video data. The selection of the sub frame corresponding to the particular set of video data is repeated each time the particular set of video data falls within the predetermined range for bright display.
In the arrangement above, regardless of the luminance indicated by input video data, the temporal barycentric position of the luminance of the sub pixel in one frame period is set so as to be close to the temporal central position of said one frame period. It is therefore possible to prevent the following problem: on account of a variation in the temporal varycentric position, needless light or shade, which is not viewed in a still image, appears at the anterior end or the posterior end of a moving image, and hence the quality of moving images is deteriorated. The quality of moving images is therefore improved.
When the increase in the range of viewing angle is preferred to the reduction in the circuit size, the signal processing section (21-21f) preferably sets the time ratio of the sub frame periods in such a way as to cause a timing to switch a sub frame corresponding to the particular set of video data to be closer to a timing to equally divide a range of brightness that the pixel can attain than a timing to equally divide a range of luminance that the pixel can attain.
According to this arrangement, it is possible to determine in which sub frame the luminance to be mainly used for controlling the luminance in one frame period is attained, with appropriate brightness. On this account, it is possible to further reduce human-recognizable whitish appearance as compared to a case where the determination is made at a timing to equally dividing a range of luminance, and hence the range of viewing angles is further increased.
In the embodiments above, the members constituting the signal processing circuit (21-21c) are hardware. Alternatively, at least one of the members may be realized by a combination of a program for realizing the aforesaid function and hardware (computer) executing the program. For example, the signal processing circuit may be realized as a device driver which is used when a computer connected to the image display device 1 drives the image display device 1. In case where the signal processing circuit is realized as a conversion circuit which is included in or externally connected to the image display device 1 and the operation of a circuit realizing the signal processing circuit can be rewritten by a program such as firmware, the software may be delivered as a storage medium storing the software or through a communication path, and the hardware may execute the software. With this, the hardware can operate as the signal processing circuit of the embodiments above.
In the cases above, the signal processing circuit of the embodiments above can be realized by only causing hardware capable of performing the aforesaid functions to execute the program.
More specifically, CPU or computing means constituted by hardware which can perform the aforesaid functions execute a program code stored in a storage device such as ROM and RAM, so as to control peripheral circuits such as an input/output circuit (not illustrated). In this manner, the signal processing circuit of the embodiments above can be realized.
In this case, the signal processing circuit can be realized by combining hardware performing a part of the process and the computing means which controls the hardware and executes a program code for remaining process. Among the aforesaid members, those members described as hardware may be realized by combining hardware performing a part of the process with the computing means which controls the hardware and execute a program code for remaining process. The computing means may be a single member, or plural computing means connected to each other by an internal bus or various communication paths may execute the program code in cooperation.
A program code which is directly executable by the computing means or a program as data which can generate the program code by a below-mentioned process such as decompression is stored in a storage medium and delivered or delivered through communication means for transmitting the program code or the program by a wired or wireless communication path, and the program or the program code is executed by the computing means.
To perform transmission via a communication path, transmission mediums constituting the transmission path transmit a series of signals indicating a program, so that the program is transmitted via the communication path. To transmit a series of signals, a sending device may superimpose the series of signals indicating the program to a carrier wave by modulating the carrier wave by the series of signals. In this case, a receiving device demodulates the carrier wave so that the series of signals is restored. In the meanwhile, to transmit the series of signals, the sending device may divide the series of signals, which are series of digital data, into packets. In this case, the receiving device connects the supplied packets so as to restore the series of signals. Also, to send a series of signals, the sending device may multiplex the series of signals with another series of signals by time division, frequency-division, code-division, or the like. In this case, the receiving device extracts each series of signals from the multiplexed series of signals and restore each series of signals. In any case, effects similar to the above can be obtained when a program can be sent through a communication path.
A storage medium for delivering the program is preferable detachable, but a storage medium after the delivery of the program is not required to be detachable. As long as the program is stored, the storage medium may be or may not be rewritable, may be or may not be volatile, can adopt any recording method, any can have any shape. Examples of the storage medium are a tape, such as a magnetic tape and a cassette tape; a magnetic disk, such as a flexible disk and a hard disk; a disc including an optical disc, such as a CD-ROM/MO/MD/DVD; a card, such as an IC card; and a semiconductor memory, such as a mask ROM, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), or a flash ROM. Also, the storage medium may be a memory formed in computing means such as a CPU.
The program code may instruct the computing means to execute all procedures of each process. Alternatively, if a basic program (e.g. operation system and library) which can execute at least a part of the processes by performing calling by a predetermined procedure has already existed, at least a part of the procedures may be replaced with a code or a pointer which instructs the computing means to call the basic program.
The format of a program stored in the storage medium may be a storage format which allows the computing means to access and execute the program, as in the case of real memory, may be a storage format before being stored in real memory and after being installed in a local storage medium (e.g. real memory or a hard disc) to which the computing means can always access, or may be a storage format before being installed from a network or a portable storage medium to the local storage medium. The program is not limited to a compiled object code. Therefore the program may be stored as a source code or an intermediate code generated in the midst of interpretation or compilation. In any case, effects similar to the above can be obtained regardless of the format for storing a program in a storage medium, on condition that the format can be converted to a format that the computing means is executable, by means of decompression of compressed information, demodulation of modulated information, interpretation, completion, linking, placement in real memory, or a combination of these processes.
INDUSTRIAL APPLICABILITY
According to the present invention, with the driving performed as described above, it is possible to provide a display device which is brighter, has a wider range of viewing angles, restrains deteriorated image quality caused by excessive emphasis of grayscale transition, and has better moving image quality. On this account, the present invention can be suitably and widely used as a drive unit of various liquid crystal display devices such as a liquid crystal television receiver and a liquid crystal monitor.

## Claims

1. A drive method of a display device, comprising:
a step of (i) generating predetermined plural sets of output video data supplied to a pixel, in response to each input cycle of inputting input video data to the pixel, the plural sets of output video data being generated for driving the pixel by time division, the drive method further comprising a step of:
(ii) prior to or subsequent to the step (i), correcting correction target data which is either the input video data or the plural output video data, and predicting luminance at which the pixel reaches at the end of a drive period of the correction target data, the drive period being a period in which the pixel is driven based on the corrected correction target data,
the step (i) including sub steps of:
(I) in case where the input video data indicates luminance lower than a predetermined threshold, setting luminance of at least one of the plural sets of output video data to be at a value within a luminance range for dark display, and controlling a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing luminance of at least one of remaining sets of output video data; and
(II) in case where the input video data indicates luminance higher than the predetermined threshold, setting at least one of the plural sets of output video data to be at a value within a luminance range for bright display, and controlling a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing the luminance of at least one of the remaining sets of output video data,

the step (ii) including sub steps of:
(III) correcting the correction target data based on a prediction result, among past prediction results, which indicates luminance that the pixel reaches at the beginning of a drive period of the correction target data; and
(IV) predicting luminance at the end of the drive period of the correction target data of the present time, at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time.

2. A drive unit of a display device, comprising generation means for generating predetermined plural sets of output video data supplied to a pixel, in response to each of the input cycles of inputting input video data to the pixel, the plural sets of output video data being generated for driving the pixel by time division,
the drive unit further comprising:
correction means, provided prior to or subsequent to the generation means, for correcting correction target data which is either the input video data or the plural output video data, and predicting luminance at which the pixel reaches at the end of a drive period of the correction target data, the drive period being a period in which the pixel is driven based on the corrected correction target data,
the generation means performing control so as to: (i) in case where the input video data indicates luminance lower than a predetermined threshold, set luminance of at least one of the plural sets of output video data at a value within a luminance range for dark display, and control a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing luminance of at least one of remaining sets of output video data; and (ii) in case where the input video data indicates luminance higher than the predetermined threshold, set luminance of at least one of the plural sets of output video data at a value within a luminance range for bright display, and control a time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data, by increasing or decreasing the luminance of at least one of the remaining sets of output video data, and
the correction means correcting the correction target data based on a prediction result, among past prediction results, which indicates luminance that the pixel reaches at the beginning of a drive period of the correction target data, and predicting luminance at the end of the drive period of the correction target data of the present time, at least based on the prediction result indicating the luminance at the beginning of the drive period and the correction target data of the present time, among the past prediction results, past supplied correction target data, and the correction target data of the present time.

3. The drive unit according to claim 2, wherein
the correction target data is input video data, and
the correction means is provided prior to the generation means and predicts, as luminance that the pixel reaches at the end of a drive period of the correction target data, luminance that the pixel reaches at the end of periods in which the pixel is driven based on the plural sets of output video data, which have been generated based on corrected input video data by the generation means.

4. The drive unit according to claim 2, wherein
the correction means is provided subsequent to the generation means and corrects the sets of output video data as the correction target data.

5. The drive unit according to claim 4, wherein
the correction means includes:
a correction section which corrects the plural sets of output video data generated in response to each of the input cycles and outputs sets of corrected output video data corresponding to respective divided periods into which the input cycle is divided, the number of the divided periods corresponding to the number of the plural sets of output video data; and
a prediction result storage section which stores a prediction result regarding a last divided period among the prediction results, wherein
in a case where the correction target data corresponds to a first divided period, the correction section corrects the correction target data based on a prediction result read out from the prediction result storage section,
in a case where the correction target data corresponds to a second or subsequent divided period, the correction section predicts the luminance at the beginning of the drive period, based on (a) output video data corresponding to a divided period which is prior to the divided period corresponding to the correction target data and (b) the prediction result stored in the prediction result storage section, and corrects the correction target data according to the prediction result,
the correction section predicts the luminance of the pixel at the end of a drive period of the output video data corresponding to the last divided period, based on (A) the output video data corresponding to the last divided period, (B) the output video data corresponding to a divided period which is prior to the divided period corresponding to the output video data (A), and (C) the prediction result stored in the prediction result storage section, and stores the thus obtained prediction result in the prediction result storage section.

6. The drive unit according to claim 5, wherein
the pixel is one of a plurality of pixels,
in accordance with input video data for each of the pixels, the generation means generates predetermined plural of sets of output video data supplied to each of the pixels, in response to each of the input cycles,
the correction means corrects the sets of output video data to be supplied to each of the pixels and stores prediction results corresponding to the respective pixels in the prediction result storage section,
the generation means generates, for each of the pixels, the predetermined number of sets of output video data to be supplied to the each of the pixels in each of the input cycles, and
the correction section reads out, for each of the pixels, prediction results regarding the pixel predetermined number of times in each of the input cycles, and based on these prediction results and the sets of output video data, for each of the pixels, at least one process of writing of the prediction result is thinned out from processes of prediction of luminance at the end of the drive period and processes of storing the prediction result, which can be performed plural number of times in each of the input cycles.

7. The drive unit according to claim 2, wherein
the generation means controls the time integral value of the luminance of the pixel in periods in which the pixel is driven based on the plural sets of output video data by increasing or decreasing the luminance of particular output video data which is a particular one of the remaining sets of output video data, and sets the remaining sets of output video data other than the particular output video data at either a value indicating luminance falling within the predetermined range for dark display or a value indicating luminance falling within the range for bright display.

8. The drive unit as defined in claim 7, wherein
provided that the periods in which the pixel is driven by said plural sets of output video data are divided periods whereas a period constituted by the divided periods and in which the pixel is driven by said plural sets of output video data is a unit period, the generation means selects, as the particular output video data, a set of output video data corresponding to a divided period which is closest to a temporal central position of the unit period, among the divided periods, in a region where luminance indicated by the input video data is lowest, and when luminance indicated by the input video data gradually increases and hence the particular output video data enters the predetermined range for bright display, the generation means sets the set of video data in that divided period at a value falling within the range for bright display, and selects, as new particular output video data, a set of output video data in a divided period which is closest to the temporal central position of the unit period, among the remaining divided periods.

9. The drive unit as defined in claim 7, wherein
a ratio between the periods in which the pixel is driven based on said plural sets of output video data is set so that a timing to determine which set of output video data is selected as the particular output video data is closer to a timing at which a range of brightness that the pixel can reproduce is equally divided than a timing at which luminance that the pixel can reproduce is equally divided.

10. A program stored on a non-transitory computer readable storage medium, the program, when executed by a processor, causing the processor to operate as the foregoing means according to claim 2.

11. A non-transitory computer readable storage medium storing the program according to claim 10.

12. A display device, comprising:
the drive unit according to claim 2; and
a display section including pixels driven by the drive unit.

13. The display device according to claim 12, further comprising image receiving means which receives television broadcast and supplies, to the drive unit of the display device, a video signal indicating an image transmitted by the television broadcast, the display section being a liquid crystal display panel, wherein
the display device functions as a liquid crystal television receiver.

14. The display device according to claim 12, wherein
the display section is a liquid crystal display panel,
the drive unit of the display device receives a video signal from outside, and
the display device functions as a liquid crystal monitor device which displays an image indicated by the video signal.