# Patent

## Title
Sensor apparatus

## Abstract

The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

## Background
This is a continuation application of application Ser. No. 11/596,069, having a §371 date of Jul. 19, 2007, now abandoned which is a national stage filing based on PCT International Application No. PCT/JP05/08305, filed on May 2, 2005. The copending application Ser. No. 11/596,069 is incorporated by reference herein in its entirety.


TECHNICAL FIELD
The present invention relates to a sensor apparatus including a plurality of sensor elements.
BACKGROUND ART
In sensor apparatuses including a plurality of sensor elements, voltage values corresponding to the detection result of the amount of sensing by the respective sensor elements are outputted from a signal processing circuit, and further digital values corresponding to the voltage values are outputted from an A/D conversing circuit. Then, one- or two-dimensional distribution of the amount of sensing (e.g. light intensity, temperature, displacement) is obtained based on the digital values corresponding to the amount of sensing for the respective sensor elements. As an example of such a sensor apparatus, there can be cited an image pickup apparatus including a plurality of photodiodes that are arranged one or two-dimensionally (refer to Patent Document 1).

    Patent Document 1: Japanese Patent Application Laid-Open No. H9-51476


DISCLOSURE OF THE INVENTION
Problem to be Solved by the Invention
The inventors have studied conventional sensor apparatuses in detail, and as a result, have found problems as follows. That is, the amount of sensing detected by such a sensor apparatus as described above may include not only a signal component that is supposed to be detected but also a noise component (disturbing light component, background light component) that is superimposed on the signal component. When the noise component (disturbing light component, background light component) is significantly indefinite, the A/D conversing circuit requires 10-bit outputted digital values for inputted voltage values with noise components (disturbing light components, background light components) superimposed on signal components, though 8-bit outputted digital values would suffice for, for example, inputted voltage values including signal components only, to A/D-convert the signal components with an accuracy equivalent to the 8-bit case.
When the outputted digital value of the A/D conversing circuit has a large number of bits, the A/D conversing circuit results in a long conversion time, large power consumption, and large circuit scale. It is generally necessary to A/D-convert the detection result of the amount of sensing by all sensor elements within a certain time period, which may require parallel processing using a plurality of A/D conversing circuits, resulting in a larger power consumption and larger circuit scale.
In order to overcome the above-mentioned problems, it is an object of the present invention to provide a sensor apparatus capable of obtaining digital values of signal components with a high accuracy, even in the case of the amount of sensing with noise components (disturbing light components, background light components) superimposed on the signal components, using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.
Means for Solving Problem
A sensor apparatus according to the present invention comprises a sensor array section, a difference operating section, and an A/D converting section. In a first aspect of the sensor apparatus, the sensor array section includes N sensor elements (N represents an integer of 2 or more) and outputs a voltage value Vn in response to the result of sensing by the n-th sensor element (“n” represents any integer of 1 or more but N or less) among the N sensor elements. The difference operating section receives N voltage values V1 to VN outputted from the sensor array section and outputs a voltage value Un (n≠1) corresponding to the difference (Vn−Vn-1) between voltage values Vn and Vn-1. The A/D converting section receives the voltage value Un outputted from the difference operating section, converts the voltage value Un into a digital value, and then outputs the converted digital value.
In the sensor apparatus according to the above-described first aspect, the A/D converting section may converts at least one voltage value among the N voltage values V1 to VN into a digital value, and then outputs the converted digital value.
Also, in a second aspect of the sensor apparatus, the difference operating section may receives N voltage values V1 to VN outputted from the sensor array section and outputs a voltage value Wn corresponding to the difference (Vn−Vn0) between a specific voltage value Vn0 and the voltage value Vn among the N voltage values V1 to VN. In this case, the A/D converting section receives the voltage value Wn outputted from the difference operating section, converts the voltage value Wn into a digital value, and then outputs the converted digital value.
In the sensor apparatus according to the above-described second aspect, the A/D converting section may converts the specific voltage value Vn0 into a digital value, and then outputs the converted digital value.
The sensor apparatus according to the present invention preferably further includes a holding section that receives the N voltage values V1 to VN outputted from the sensor array section and once holds the N voltage values V1 to VN. In this case, the difference operating section outputs the voltage value Un or Wn based on the N voltage values V1 to VN held by the holding section.
In the sensor apparatus according to the present invention, each of the N sensor elements preferably includes a photodiode. In this case, the one- or two-dimensional intensity distribution of incident light can be detected. Also, even when the intensity of incident light may include signal components and noise components (disturbing light components, background light components) and the noise components (disturbing light components, background light components) may be significantly indefinite, it is possible to obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.
The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and are not to be considered as limiting the present invention.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will be apparent to those skilled in the art from this detailed description.
Effect of the Invention
In accordance with the sensor apparatus according to the present invention, it is possible to obtain digital values of signal components with a high accuracy, even in the case of the amount of sensing with noise components (disturbing light components, background light components) superimposed on the signal components, using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view showing the overall configuration of a sensor apparatus according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram including a photodiode PDn, an integrating circuit 11n, a CDS circuit 12n, and a holding circuit 21n in the sensor apparatus according to the first embodiment;
FIG. 3 is a timing chart for explaining the operation of a difference operating section and an A/D converting section in the sensor apparatus according to the first embodiment;
FIG. 4 is a view showing the intensity distribution of light to be detected by the sensor apparatus according to the first embodiment;
FIG. 5 is a view showing the overall configuration of a sensor apparatus according to a second embodiment of the present invention; and
FIG. 6 is a circuit diagram of an APS circuit included in each pixel, showing the partial configuration of a sensor apparatus according to a modified example of the present invention.



DESCRIPTION OF THE REFERENCE NUMERALS
1, 2 . . . sensor apparatuses; 10 . . . sensor array section; 11 . . . integrating circuit; 12 . . . CDS circuit; 20 . . . holding section; 30, 30A . . . difference operating sections; 33 . . . subtracting circuit; and 40 . . . A/D converting section.
BEST MODES FOR CARRYING OUT THE INVENTION
In the following, embodiments of a sensor apparatus according to the present invention will be explained in detail with reference to FIGS. 1 to 6. In the explanation of the drawings, constituents identical to each other will be referred to with numerals identical to each other without repeating their overlapping descriptions.
First Embodiment
First, a sensor apparatus according to a first embodiment of the present invention will be explained. FIG. 1 is a view showing the overall configuration of the sensor apparatus according to the first embodiment of the present invention. The sensor apparatus 1 shown in FIG. 1 comprises a sensor array section 10, a holding section 20, a difference operating section 30, and an A/D converting section 40.
The sensor array section 10 includes N photodiodes PD1 to PDN, N integrating circuits 111 to 11N, and N CDS circuits 121 to 12N. Also, the holding section 20 includes N holding circuits 211 to 21N. Each of the photodiodes PD1 to PDN has a common composition, each of the integrating circuits 111 to 11N also has a common composition, each of the CDS circuits 121 to 12N also has a common composition, and each of the holding circuits 211 to 21N also has a common composition. The N photodiodes PD1 to PDN are arranged one-dimensionally. The n-th integrating circuit 11n, n-th CDS circuit 12n, and n-th holding circuit 21n are provided correspondingly to the n-th photodiode PDn. Here, N represents an integer of 2 or more. Also, “n” represents any integer of 1 or more but N or less, unless otherwise specified.
The photodiode PDn generates electric charges corresponding to the amount of incident light and outputs the electric charges to the integrating circuit 11n. Each integrating circuit 11n accumulates the electric charges outputted from the photodiode PDn into a capacitive element and outputs a voltage value corresponding to the amount of accumulated charge to the CDS circuit 12n. The CDS circuit 12n receives the voltage value outputted from the integrating circuit 11n and outputs a voltage value corresponding to the change of the inputted voltage value after a reference time based on the inputted voltage value at the reference time to the holding circuit 21n. That is, the sensor array section 10 includes the N photodiodes PD1 to PDN as sensor elements and outputs a voltage value corresponding to the detection result of light by the photodiode PDn. The holding circuit 21n receives the voltage value outputted from the CDS circuit 12n and outputs the voltage value Vn held therein.
The difference operating section 30 includes switches SW31,1 to SW31,N, switches SW32,0 to SW32,N-1, and a subtracting circuit 33. The output terminal of the holding circuit 21n is connected to a wiring L1 via the switch SW31,n and to a wiring L2 via the switch SW32,n. However, the output terminal of the N-th holding circuit 21N is connected to the wiring L1 via the switch SW31,N but may not be connected to the wiring L2 via a switch. Also, the wiring L2 is connected with the ground potential via the switch SW32,0. The switches SW31,n and SW32,n-1 open and close based on the level of a control signal Sn. The subtracting circuit 33 outputs a voltage value corresponding to the difference between voltage values to be inputted through the respective wirings L1 and L2.
The A/D converting section 40 is used together with switches SW41 and SW42. The A/D converting section 40 receives one of a voltage value VFS1 to be inputted via the switch SW41 and a voltage value VFS2 to be inputted via the switch SW42 as a full scale in A/D conversion. Then, the A/D converting section 40 converts the voltage value outputted from the subtracting circuit 33 into a digital value at a resolution of one 2M-th of the full scale (voltage value VFS1 or VFS2), and then outputs the converted digital value. It is noted that M represents the number of bits of the outputted digital value. It is preferable that the voltage value VFS1 is greater than VFS2 and the ratio therebetween be a power of two. The switch SW41 opens and closes based on the level of a control signal Sel1, while the switch SW42 opens and closes based on the level of a control signal Sel2.
FIG. 2 is a circuit diagram including a photodiode PDn, an integrating circuit 11n, a CDS circuit 12n, and a holding circuit 21n in the sensor apparatus 1 according to the first embodiment. The anode terminal of the photodiode PDn is grounded, while the cathode terminal thereof is connected to the input terminal of the integrating circuit 11n, and the photodiode PDn generates electric charges corresponding to the amount of incident light and outputs the electric charges to the integrating circuit 11n.
The integrating circuit 11n includes an amplifier A11, a capacitive element C11, and a switch SW11. The input terminal of the amplifier A11 is connected to the cathode terminal of the photodiode PDn. The capacitive element C11 and switch SW11 are provided between the input and output terminals of the amplifier A11 by being connected parallel with each other. The outputted voltage value of the integrating circuit 11n is initialized by closing the switch SW11 so that the capacitive element C11 is discharged. The integrating circuit 11n also accumulates electric charges outputted from the photodiode PDn into the capacitive element C11 when the switch SW11 is opened, and then outputs a voltage value corresponding to the amount of accumulated charge to the CDS circuit 12n.
The CDS circuit 12n includes an amplifier A12, a capacitive element C12, and a switch SW12. The input terminal of the amplifier A12 is connected to the amplifier A11 in the integrating circuit 11n via the capacitive element C12 and is grounded via the switch SW12. The CDS circuit 12n receives the voltage value outputted from the integrating circuit 11n and outputs a voltage value corresponding to the change of the inputted voltage value after a reference time (when the switch SW12 is opened) based on the inputted voltage value at the reference time from the amplifier A12 to the holding circuit 21n.
The holding circuit 21n includes an amplifier A21, a capacitive element C21, and a switch SW21. The input terminal of the amplifier A21 is connected to the amplifier A12 in the CDS circuit 12n via the switch SW21 and is grounded via the capacitive element C21. The output terminal of the amplifier A21 is connected to the wiring L1 via the switch SW31,n and to the wiring L2 via the switch SW32,n. The holding circuit 21n holds the voltage value, which is outputted from the CDS circuit 12n at a time when the switch SW21 is opened, in the capacitive element C21 also after the time of the state variation, and then outputs a voltage value Vn corresponding to the held voltage value from the amplifier A21.
The operation of the photodiode PDn, integrating circuit 11n, CDS circuit 12n, and holding circuit 21n is as follows.
That is, when the switch SW11 in the integrating circuit 11n is opened, electric charges outputted from the photodiode PDn are accumulated into the capacitive element C11, and then a voltage value corresponding to the amount of accumulated charge is outputted from the integrating circuit 11n. As the amount of charge accumulated in the capacitive element C11 increases gradually, the voltage value outputted from the integrating circuit 11n varies. While the switch SW11 in the integrating circuit 11n is opened, the switch SW12 in the CDS circuit 12n is opened at a first time, and then the switch SW21 in the holding circuit 21n is opened at a second time. The voltage value outputted from the CDS circuit 12n after the first time corresponds to the change of the voltage value outputted from the integrating circuit 11n based on the voltage value outputted from the integrating circuit 11n at the first time. Then, the voltage value Vn held by the holding circuit 21n after the second time corresponds to the voltage value outputted from the CDS circuit 12n at the second time.
That is, the voltage value Vn held by the holding circuit 21n after the second time corresponds to the difference between the voltage values outputted from the integrating circuit 11n at the first and second time, and when the time difference between the first and second time is constant, corresponds to the intensity of light incident to the photodiode PDn. It is noted that the N integrating circuits 111 to 11N operate at the same timing; the N CDS circuits 121 to 12N also operate at the same timing; and the N holding circuits 211 to 21N also operate at the same timing. Therefore, a voltage value Vn corresponding to the amount of incident light to the photodiode PDn during a common period of time is to be held by the holding section 20.
Next, the operation of the difference operating section 30 and the A/D converting section 40 in the sensor apparatus 1 according to the first embodiment will be explained. FIG. 3 is a timing chart for explaining the operation of the difference operating section 30 and the A/D converting section 40 in the sensor apparatus 1 according to the first embodiment. FIG. 3 shows a timing chart when the difference operating section 30 and A/D converting section 40 process voltage values V1 to VN are held by the holding section 20 as described above. It is noted that not only the above-described operation of the sensor array section 10 and holding section 20 but also the operation of the difference operating section 30 and A/D converting section 40 to be explained hereinafter is performed based on various control signals outputted from a control section (not shown in the figures). FIG. 3 shows the level of each control signal Sn to be inputted to the difference operating section 30, the level of a control signal Sel1 for instructing the switch SW41 to open and close, and the level of a control signal Sel2 for instructing the switch SW42 to open and close in this order from the top.
As shown in FIG. 3, the control signals S1 to SN are made high sequentially. During the time period Tn from time tn,1 to time tn,2, only the control signal Sn is made high among the control signals S1 to SN. During the time period T1, the control signal Sel1 is made high, while the control signal Sel2 is made low. Also, from the time period T2 through the time period TN, the control signal Sel1 is made low, while the control signal Sel2 is made high.
During the time period T1 from time t1,1 to time t1,2, only the control signal S1 is made high among the control signals S1 to SN, so that the switches SW31,1 and SW32,0 in the difference operating section 30 are closed. Also, the control signal Sel1 is made high, so that the switch SW41 is closed. When the switch SW31,1 is closed, the voltage value V1 held by the holding circuit 211 is inputted to the subtracting circuit 33 through the switch SW31,1 and the wiring L1. Also, when the switch SW32,0 is closed, the ground potential is inputted to the subtracting circuit 33 through the switch SW32,0 and the wiring L2. In the subtracting circuit 33, the ground potential is subtracted from the voltage value V1, and the subtracted voltage value V1 is outputted. Then, in the A/D converting section 40, the voltage value V1 outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value VFS1 inputted through the switch SW41 as a full scale.
During the time period Tn from time tn,1 to time tn,2 (n≠1), only the control signal Sn, is made high among the control signals S1 to SN, so that the switches SW31,n and SW32,n-1 in the difference operating section 30 are closed. Also, the control signal Sel2 is made high, so that the switch SW42 is closed. When the switch SW31,n is closed, the voltage value Vn held by the holding circuit 21n is inputted to the subtracting circuit 33 through the switch SW31,n and the wiring L1. Also, when the switch SW32,n-1 is closed, the voltage value Vn-1 held by the holding circuit 21n-1 is inputted to the subtracting circuit 33 through the switch SW32,n-1 and the wiring L2. In the subtracting circuit 33, the voltage value Vn-1 is subtracted from the voltage value Vn, and a voltage value Un corresponding to the subtraction result is outputted. Then, in the A/D converting section 40, the voltage value Un outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value VFS2 inputted through the switch SW42 as a full scale.
That is, during the time period T1, the A/D converting section 40 converts the voltage value V1 corresponding to the amount of incident light to the first photodiode PD1 into an M-bit digital value using the voltage value VFS1 as a full scale. Also, during each time period Tn (n≠1), the difference operating section 30 calculates a voltage value Un according to the difference (Vn−Vn-1) between voltage values Vn and Vn-1 that correspond to the amount of incident light to the respective photodiodes PDn and PDn-1, and then the A/D converting section 40 converts the voltage value Un into an M-bit digital value using the voltage value VFS2 as a full scale.
Therefore, as shown in FIG. 4, even when significant noise components (disturbing light components, background light components) may be superimposed on signal components that are supposed to be detected in the intensity distribution of light to be detected by the sensor apparatus 1, the sensor apparatus 1 can obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40.
That is, the maximum value of the difference (Vn−Vn-1) between two adjacent voltage values Vn and Vn-1 among the voltage values V1 to VN outputted from the respective holding circuits 211 to 21N is smaller than the maximum value of the voltage values V1 to VN. Hence, the voltage value VFS2 to be used by the A/D converting section 40 as a full scale during the time period Tn (n≠1) is set to the maximum value of the difference (Vn−Vn-1) (or a value somewhat greater than the maximum value) or to the difference between the maximum and minimum values of signal components included in the voltage values V1 to VN (or a value somewhat greater than the difference). Thus, in the A/D converting section 40, the voltage value VFS2 to be used as a full scale is set appropriately and a voltage value Un corresponding to the difference (Vn−Vn-1) is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents signal components with a high accuracy, though having a small number of bits of M.
Meanwhile, the maximum value of the voltage values V1 to VN outputted from the respective holding circuits 211 to 21N is larger. Hence, the voltage value VFS1 to be used by the A/D converting section 40 as a full scale during the time period T1 is set to the maximum value of the voltage values V1 to VN (or a value somewhat greater than the maximum value) that is greater than the voltage value VFS2. Thus, in the A/D converting section 40, the voltage value VFS1 to be used as a full scale is set appropriately and the voltage value V1 is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents the sum of signal components and noise components (disturbing light components, background light components), though having a small number of bits of M.
As described heretofore, the sensor apparatus 1 according to the first embodiment can obtain digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40. Therefore, the A/D converting section 40 results in a short conversion time, small power consumption, and small circuit scale. Also, even in the case of performing A/D conversion processing in parallel due to the requirement of performing the A/D conversion processing within a certain time period, the number of A/D converting sections for the parallel processing may be small, which also results in a small power consumption and small circuit scale.
Second Embodiment
Next, a sensor apparatus according to a second embodiment of the present invention will be explained. FIG. 5 is a view showing the overall configuration of the sensor apparatus according to the second embodiment of the present invention. The sensor apparatus 2 shown in FIG. 5 comprises a sensor array section 10, a holding section 20, a difference operating section 30A, and an A/D converting section 40. As compared with the configuration of the sensor apparatus 1 according to the above-described first embodiment (FIGS. 1 and 2), the sensor apparatus 2 according to the second embodiment is different from the first embodiment in that the difference operating section 30A is provided instead of the difference operating section 30.
The difference operating section 30A includes switches SW31,1 to SW31,N, switches SW32,0 and SW32,1, and a subtracting circuit 33. The output terminal of the holding circuit 21n is connected to a wiring L1 via the switch SW31,n. The output terminal of the first holding circuit 211 is connected to a wiring L2 via the switch SW32,1. Also, the wiring L2 is connected with the ground potential via the switch SW32,0. The switch SW31,n opens and closes based on the level of a control signal Sn, and the switch SW32,0 opens and closes based on the level of a control signal Sel1, while the switch SW32,1 opens and closes based on the level of a control signal Sel2. The subtracting circuit 33 outputs a voltage value corresponding to the difference between voltage values to be inputted through the respective wirings L1 and L2.
Next, the operation of the difference operating section 30A and the A/D converting section 40 in the sensor apparatus 2 according to the second embodiment will be explained. The timing chart for explaining the operation of the difference operating section 30A and the A/D converting section 40 in the sensor apparatus 2 according to the second embodiment is the same as in FIG. 3.
During the time period T1 from time t1,1 to time t1,2, only the control signal S1 is made high among the control signals S1 to SN, so that the switch SW31,1 in the difference operating section 30A is closed. Also, the control signal Sel1 is made high, so that the switches SW32,0 and SW41 are closed. When the switch SW31,1 is closed, the voltage value V1 held by the holding circuit 211 is inputted to the subtracting circuit 33 through the switch SW31,1 and the wiring L1. Also, when the switch SW32,0 is closed, the ground potential is inputted to the subtracting circuit 33 through the switch SW32,0 and the wiring L2. In the subtracting circuit 33, the ground potential is subtracted from the voltage value V1, and the subtracted voltage value V1 is outputted. Then, in the A/D converting section 40, the voltage value V1 outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value VFS1 inputted through the switch SW41 as a full scale.
During the time period Tn from time tn,1 to time tn,2 (n≠1), only the control signal Sn is made high among the control signals S1 to SN, so that the switch SW31,n in the difference operating section 30A is closed. Also, the control signal Sel2 is made high, so that the switch SW42 is closed. When the switch SW31,n is closed, the voltage value Vn held by the holding circuit 21n is inputted to the subtracting circuit 33 through the switch SW31,n and the wiring L1. Also, when the switch SW32,1 is closed, the voltage value V1 held by the holding circuit 211 is inputted to the subtracting circuit 33 through the switch SW32,1 and the wiring L2. In the subtracting circuit 33, the voltage value V1 is subtracted from the voltage value Vn, and a voltage value Wn corresponding to the subtraction result is outputted. Then, in the A/D converting section 40, the voltage value Wn outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value VFS2 inputted through the switch SW42 as a full scale.
That is, during the time period T1, the A/D converting section 40 converts the voltage value V1 corresponding to the amount of incident light to the first photodiode PD1 into an M-bit digital value using the voltage value VFS1 as a full scale. Also, during the time period Tn (n≠1), the difference operating section 30A calculates a voltage value Wn corresponding to the difference (Vn−V1) between voltage values Vn and V1 that correspond to the amount of incident light to the respective photodiodes PDn and PD1, and then the A/D converting section 40 converts the voltage value Wn into an M-bit digital value using the voltage value VFS2 as a full scale.
Therefore, as shown in FIG. 4, even when significant noise components (disturbing light components, background light components) may be superimposed on signal components that are supposed to be detected in the intensity distribution of light to be detected by the sensor apparatus 2, the sensor apparatus 2 can obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40.
That is, the maximum value of the voltage value Wn to be obtained by a difference operation from the voltage values V1 to VN outputted from the respective holding circuits 211 to 21N is smaller than the maximum value of the voltage values V1 to VN. Hence, the voltage value VFS2 to be used by the A/D converting section 40 as a full scale during the time period Tn (n≠1) is set to the maximum value of the voltage value Wn (or a value somewhat greater than the maximum value) or to the difference between the maximum and minimum values of signal components included in the voltage values V1 to VN (or a value somewhat greater than the difference). Thus, in the A/D converting section 40, the voltage value VFS2 to be used as a full scale is set appropriately and a voltage value Wn corresponding to the difference (Vn−V1) is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents signal components with a high accuracy, though having a small number of bits of M.
Meanwhile, the maximum value of the voltage values V1 to VN outputted from the respective holding circuits 211 to 21N is larger. Hence, the voltage value VFS1 to be used by the A/D converting section 40 as a full scale during the time period T1 is set to the maximum value of the voltage values V1 to VN (or a value somewhat greater than the maximum value) that is greater than the voltage value VFS2. Thus, in the A/D converting section 40, the voltage value VFS1 to be used as a full scale is set appropriately and the voltage value V1 is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents the sum of signal components and noise components (disturbing light components, background light components), though having a small number of bits of M.
As described above, the sensor apparatus 2 according to the second embodiment can obtain digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40. Therefore, the A/D converting section 40 results in a short conversion time, small power consumption, and small circuit scale. Also, even in the case of performing A/D conversion processing in parallel due to the requirement of performing the A/D conversion processing within a certain time period, the number of A/D converting sections for the parallel processing may be small, which also results in a small power consumption and small circuit scale.
(Exemplary Variation)
The present invention is not restricted to the above-described first and second embodiments, and various modifications may be made. For example, although the sensor apparatuses according to the above-described first and second embodiments are image pickup apparatuses including a plurality of photodiodes that are arranged one-dimensionally, the sensor apparatus according to the present invention may be an image pickup apparatus including a plurality of photodiodes that are arranged two-dimensionally. Further, the sensor apparatus according to the present invention may be an imaging apparatus in which each pixel includes an APS (Active Pixel Sensor) circuit shown in FIG. 6 as well as a plurality of photodiodes and the pixels are arranged one- or two-dimensionally. Also, the sensor apparatus according to the present invention is not restricted to an image pickup apparatus, but may include a plurality of sensor elements for detecting the amount of another sensing parameter (e.g. temperature, displacement).
From the invention thus described, it will be obvious that the embodiments of the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.
INDUSTRIAL APPLICABILITY
The sensor apparatus according to the present invention is applicable to, for example, an image pickup apparatus including a plurality of photodiodes that are arranged one- or two-dimensionally.

## Claims

1. A sensor apparatus comprising:
a sensor array section including N sensor elements (N represents an integer of 2 or more) and outputting a voltage value Vn in response to the result of sensing by the n-th sensor element (“n” represents any integer of 1 or more but N or less) among said N sensor elements;
a difference operating section including:
a subtracting circuit having first and second input terminals for respectively inputting the voltage values Vn and Vn-1 among N voltage values V1 to VN outputted from said sensor array section and an output terminal for outputting a voltage value Un (n≠1) corresponding to the difference (Vn−Vn-1) between the voltage values Vn and Vn-1; and
a switching device having N first switch elements disposed on all lines connecting the first input terminal of said subtracting circuit to all N output terminals of said sensor array section for respectively outputting the N voltage values V1 to VN, and N second switch elements connecting the second input terminal of said subtracting circuit to the all N output terminals of said sensor array section; and

an A/D converting section converting the voltage value Un outputted from said difference operating section into a digital value.

2. A sensor apparatus according to claim 1, wherein said A/D converting section converts at least one voltage value of the N voltage values V1 to VN into a digital value.

3. A sensor apparatus according to claim 1, further comprising a holding section once holding the N voltage values V1 to VN outputted from said sensor array section, and
wherein said difference operating section outputs the voltage value Un based on the N voltage values V1 to VN held by said holding section.

4. A sensor apparatus according to claim 1, wherein each of said N sensor elements includes a photodiode.

5. A sensor apparatus according to claim 1, wherein said sensor array section further includes N CDS circuits respectively disposed between said N sensor elements and said N output terminals of said sensor array section.